首页 |元器件品牌

LP3970SQ-44/NOPB [TI]

IC,MULTIPLE REGULATOR CIRCUIT,CMOS,LLCC,48PIN,PLASTIC;
LP3970SQ-44/NOPB
型号： LP3970SQ-44/NOPB
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

IC,MULTIPLE REGULATOR CIRCUIT,CMOS,LLCC,48PIN,PLASTIC
文件： 总33页 (文件大小：619K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
OBSOLETE  
LP3970  
www.ti.com  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
Power Management Unit for Advanced Application Processor  
Check for Samples: LP3970  
1
FEATURES  
KEY SPECIFICATIONS  
2
•
Compatible with Advanced Applications  
Processors Requiring Dynamic Voltage  
Management (DVM)  
•
Buck Regulators  
–
–
–
–
Programmable VOUT from 0.8 to 3.3V  
Up to 95% efficiency  
•
Two Buck Regulator for Powering High  
Current Processor Functions or Peripheral  
Devices  
650 mA output current  
±3% output voltage accuracy  
•
LDO’s  
•
•
Eleven LDO's for Powering Internal Processor  
Functions and I/O's  
–
–
–
–
Programmable VOUT of 1.5-3.3V  
±3% output voltage accuracy  
50 mA to 300 mA output current  
100 mV dropout  
Backup Battery Charger with Automatic  
Switching for Lithium and Lithium-Manganese  
Coin Cell Batteries  
I2C Compatible High Speed Serial Interface  
•
•
DESCRIPTION  
Software Control of Regulator Functions and  
Settings  
The LP3970 is a multi-function, programmable Power  
Management Unit, designed especially for advanced  
application processors. The LP3970 is optimized for  
low power handheld PMU applications and provides  
11 low dropout, low noise linear regulators, two  
DC/DC magnetic buck regulators, a back-up battery  
charger and 4 GPO’s. A high speed serial interface is  
included to program individual regulator output  
voltages as well as on/off control.  
•
•
•
Thermal Overload Protection  
Current Overload Protection  
Tiny 48-Pin WQFN Package  
APPLICATIONS  
•
•
•
•
PDA Phones  
Smart Phones  
Personal Media Players  
Digital Cameras  
Simplified Application Circuit  
V
IN  
LDO1  
LDO2  
LDO10  
LDO9  
LDO8  
LDO3  
LDO4  
LDO5  
LDO7  
LDO6  
RTC  
LP3970  
BUCK1  
FB1  
BUCK2  
SYNC  
FB2  
BACK-UP  
BATTERY  
+
-
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2005–2013, Texas Instruments Incorporated  
OBSOLETE  
LP3970  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
www.ti.com  
Connection Diagrams and Package Mark Information  
36 35 34 33 32 31 30 29 28 27 26 25  
25 26 27 28 29 30 31 32 33 34 35 36  
37  
38  
24  
23  
24  
23  
37  
38  
22  
21  
20  
39  
40  
22  
21  
20  
39  
40  
41  
42  
41  
42  
19  
18  
17  
16  
19  
18  
17  
16  
43  
44  
45  
43  
44  
45  
46  
47  
48  
15  
14  
13  
46  
47  
48  
15  
14  
13  
1
2
3
4
5
6
7
8
9
10 11 12  
12 11 10  
9
8
7
6
5
4
3
2
1
Top View  
Bottom View  
Figure 1. 48-Pin WQFN  
ORDERING INFORMATION  
LDO 4 Default (V)  
Buck 2 Default (V)  
Orderable Number  
LP3970SQ/SQX-31  
LP3970SQ/SQX-35  
LP3970SQ/SQX-44  
LP3970SQ/SQX-45  
2.8  
1.8  
3.3  
3.0  
3.3  
3.0  
Table 1. Default VOUT Coding  
Y
1
2
3
4
5
Default VOUT  
1.8  
2.5  
2.8  
3.0  
3.3  
PIN DESCRIPTIONS(1)  
Pin #  
Name  
VOUT  
I/O  
O
G
O
I
Type  
Description  
1
2
3
4
5
6
9
P
LDO 9 output  
AGND 2,4,9  
nVDD_FLT  
SYS_EN  
G
D
D
D
A
Ground pin LDO’s 2,4,9  
Regulator fault output  
High voltage domain power enable  
Low voltage domain power enable  
LDO 2 output  
PWR_EN  
I
VOUT  
2
O
(1) A: Analog Pin  
I: Input Pin  
D: Digital Pin  
I/O: Input/Output Pin  
G: Ground Pin  
O: Output Pin  
P: Power Pin  
2
Submit Documentation Feedback  
Copyright © 2005–2013, Texas Instruments Incorporated  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
www.ti.com  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
PIN DESCRIPTIONS(1) (continued)  
Pin #  
Name  
I/O  
Type  
Description  
7
8
VIN  
VIN  
2
7
I
I
P
P
P
A
Input power terminal to LDO 2  
Input power terminal to LDO 7  
LDO 7 Output  
9
VOUT  
7
O
I
10  
VBIAS Cap LDO 7  
Voltage reference bypass output. Only connect a 0.01 µF ceramic capacitor  
from VREF to GND within 0.2 in. (5 mm) of the VREF pin  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
VOUT  
VIN  
1
O
I
P
P
G
D
D
D
P
P
P
P
A
LDO 1 output  
1
Input power terminal to LDO 1  
Ground pin LDO’s 1, 7, 8, RTC  
Output to applications processor from PMU  
Input to PMU  
AGND (LDO 1,7,8,RTC)  
nRSTO  
G
O
I
nRSTI  
nBAT_FLT  
O
I
Battery fault output  
VIN BU_Batt  
Back-up battery positive connection  
RTC LDO output  
VOUT RTC  
O
I
VIN 8, RTC, VBAT_MON  
Input power terminal to LDO's 8, RTC, battery monitor  
LDO 8 output  
VOUT  
8
O
I
VBIAS Cap LDO8  
Voltage reference bypass output. Only connect a 0.01 μF ceramic capacitor  
from VREF to AGND within 0.2 in. (5 mm) of the VREF pin  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
VOUT  
3
O
I
P
P
P
G
D
D
P
P
P
D
D
G
A
D
A
P
P
G
G
G
P
P
D
D
G
P
P
LDO 3 output  
VIN 3,10  
VOUT 10  
Input power terminal to LDO's 3 & 10  
LDO 10 output  
O
G
O
O
O
I
AGND 3,5,6,10  
GPO1  
Ground pin LDO's 3, 5, 6, 10  
General purpose CMOS output  
General purpose CMOS output  
LDO 5 Output  
GPO2  
VOUT  
VIN 5, 6  
VOUT  
5
Input power terminal to LDO’s. 5 & 6  
LDO 6 output  
6
O
O
O
G
I
GPO3  
GPO4  
BGND  
FB1  
General purpose CMOS Output  
General purpose CMOS Output  
Ground for buck isolation  
Feedback/VOUT Buck 1  
SYNC  
FB2  
I
System clock input for buck converters synchronization in PWM mode  
Feedback/VOUT Buck 2  
I
VIN B2  
SW2  
I
Input power terminal to buck 2  
Output switch pin buck 2  
O
G
G
G
O
I
PGND B2  
GND B1 ,B2  
PGND B1  
SW1  
NMOS power ground pin buck 2  
Circuit ground SW1 and SW2  
NMOS power ground pin buck 1  
Output switch pin buck 1  
VIN B1  
SDA  
Input power terminal to buck 1  
Serial interface data input/output  
Serial interface clock input  
Digital ground pin.  
I/O  
I
SCL  
DGND  
G
O
I
VOUT  
4
LDO 4 Output  
VIN 4, 9  
Input power terminal to LDO’s 4 & 9  
Copyright © 2005–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Links: LP3970  
 
OBSOLETE  
LP3970  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
www.ti.com  
Applications Schematic Diagram  
V
BAT  
1 mF 1 mF 10 mF  
1 mF 10 mF  
1 mF 1 mF 1 mF  
1 mF  
29  
43  
7
37  
12  
24  
48  
23  
19  
8
V
LDO1  
LDO2  
OUT  
11  
0.47 mF  
V
V
V
V
LD10  
OUT  
OUT  
OUT  
0.47 mF  
V
OUT  
6
22  
47  
28  
0.47 mF  
LD09  
0.47 mF  
1
V
OUT  
LDO3  
LDO4  
LD08  
0.47 mF  
20  
21  
0.47 mF  
V
OUT  
LD08  
0.47 mF  
BIAS  
0.01 mF  
V
LDO5  
LP3970  
OUT  
9
V
LD07  
OUT  
0.47 mF  
0.47 mF  
34  
10  
FB1  
V
LD07  
BIAS  
2.2 mH  
D1  
42  
41  
0.01 mF  
SW1  
V
BUCK1  
BUCK2  
OUT  
10 mF  
30  
18  
PGND B1  
FB2  
V
LD06  
OUT  
0.47 mF  
2.2 mH  
36  
38  
V
OUT  
SW2  
V
RTC  
OUT  
D2  
10 mF  
1 mF  
PGND B2  
39  
33  
2
SYNC  
35  
BGND  
17  
3
BACK-UP  
BATTERY  
+
-
14  
16  
44  
45  
AGND 2,4,9  
4
5
15  
27 31 32  
26  
46  
13  
25  
40  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
4
Submit Documentation Feedback  
Copyright © 2005–2013, Texas Instruments Incorporated  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
www.ti.com  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
Absolute Maximum Ratings(1)(2)  
All Input  
−0.3 to +6V  
±0.3V  
GND to GND Slug  
Junction Temperature (TJMAX  
Storage Temperature  
Power Dissipation  
)
150°C  
−65°C to 150°C  
(3)  
(TA = 70°C)  
3.2W  
25°C/W  
260°C  
θJA  
Maximum Lead Temp (Soldering)  
(4)  
ESD Rating  
Human Body Model  
Machine Model  
1.0 kV  
200V  
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which  
operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test  
conditions, see the Electrical Characteristics tables.  
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and  
specifications.  
(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may  
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-  
OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance  
of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA x PD-MAX).  
(4) The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (JESD22-A114C) The machine model  
is a 200 pF capacitor discharged directly into each pin. (EAIJ)  
(1)  
Operating Ratings  
VIN  
2.7 to 5.5V  
0 to (VIN + 0.3V)  
−40°C to 125°C  
−40°C to 85°C  
VEN  
Junction Temperature (TJ)  
Operating Temperature (TA)  
Maximum Power Dissipation  
(TA = 70°C)  
2.2W  
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which  
operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test  
conditions, see the Electrical Characteristics tables.  
General Electrical Characteristics — Supply Specification LP3970  
Unless otherwise noted, VIN = 3.6, CIN = 1.0 μF, COUT = 0.47 μF, COUT (VRTC) = 1.0 μF ceramic, CBYP = 0.1μF. Typical values  
and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction  
(1) (2)  
temperature range for operation, −40 ≤ TJ ≤ 125°C.  
,
Supply  
Supply Type  
Power Domain  
VOUT (Volts)  
IMAX  
Maximum  
Output Current  
(mA)  
Default  
(V)  
Range  
(V)  
Resolution  
(mV)  
LDO_RTC  
LDO1  
Digital  
Analog  
Digital  
Digital  
Digital  
Digital  
Digital  
VBATT  
VCC_PLL  
2.8  
1.3  
1.1  
2.8  
Fixed  
Fixed  
N/A  
N/A  
N/A  
100  
100  
100  
100  
5
100  
100  
150  
150  
150  
50  
LDO2  
VCC_SRAM  
VCC_USB  
VCC_IO  
Fixed  
LDO3  
1.5 to 3.4  
1.5 to 3.4  
1.5 to 3.4  
1.5 to 3.4  
LDO4  
LDO5  
VCC_USIM  
VCC_BB/LCD  
3.0  
2.8  
LDO6  
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which  
operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test  
conditions, see the Electrical Characteristics tables.  
(2) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are  
production tested, and specified through statistical analysis or specified by design. All limits at temperature extremes are specified via  
correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level  
(AOQL).  
Copyright © 2005–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
www.ti.com  
General Electrical Characteristics — Supply Specification LP3970 (continued)  
Unless otherwise noted, VIN = 3.6, CIN = 1.0 μF, COUT = 0.47 μF, COUT (VRTC) = 1.0 μF ceramic, CBYP = 0.1μF. Typical values  
and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction  
(1) (2)  
temperature range for operation, −40 ≤ TJ ≤ 125°C.  
,
Supply  
Supply Type  
Power Domain  
VOUT (Volts)  
IMAX  
Maximum  
Output Current  
(mA)  
Default  
(V)  
Range  
(V)  
Resolution  
(mV)  
LDO7  
LDO8  
Analog  
Analog  
Digital  
Digital  
Digital  
Digital  
GP Analog  
GP Analog  
GP Digital  
GP Digital  
VCC_CORE  
VCC_MEM  
1.8  
2.8  
Fixed  
N/A  
100  
100  
100  
50  
100  
150  
300  
300  
650  
650  
1.5 to 3.4  
1.5 to 3.4  
1.5 to 3.4  
0.8 to 2.0  
1.8 to 3.3  
LDO9  
2.8  
LDO10  
Buck 1  
Buck 2  
2.8  
1.45  
100  
Part Number  
LDO4 Default  
Buck 2 Default  
(V)  
2.8  
2.8  
3.0  
3.0  
(V)  
1.8  
3.3  
3.0  
3.3  
LP3970SQ-31  
LP3970SQ-35  
LP3970SQ-44  
LP3970SQ-45  
RTC LDO  
Unless otherwise noted, VIN = VBATT = 3.6V CIN = 1.0 μF, COUT (VRTC) = 0.47 μF ceramic. Typical values and limits  
appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature  
(1)(2)  
range for operation, −40 ≤ TJ ≤ 125°C.  
Symbol  
Parameter  
Output Voltage, Fixed (Note1)  
Line Regulation  
Condition  
Min Typ Max Unit  
s
VOUT  
VIN Connected, ILOAD = 1 mA  
2.63  
2
2.8  
2.96  
8
ΔVOUT  
VIN = (VOUT + 0.3V) to 5.5V  
Load Current = IMAX  
0.15 %/V  
Load Regulation  
VIN = 3.6V,  
0.05 %/m  
Load Current = 1 mA to IMAX  
A
IMAX  
ISC  
VIN  
VOUT  
IQ_Max Maximum Quiescent Current  
CO Output Capacitor  
Load Current  
VIN = VOUT +0.3 to 5.5V  
VOUT = 0V  
5
mA  
mA  
mV  
Short Circuit Current Limit  
Dropout Voltage  
35  
-
Load Current = IMAX  
220  
375  
(3)  
IOUT = 0 mA  
40  
1
μA  
μF  
Capacitance for Stability  
ESR  
0.7  
5
500  
mΩ  
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which  
operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test  
conditions, see the Electrical Characteristics tables.  
(2) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are  
production tested, and specified through statistical analysis or specified by design. All limits at temperature extremes are specified via  
correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level  
(AOQL).  
(3) Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. Dropout  
specification does not apply to LDO 1,2,6,7.  
6
Submit Documentation Feedback  
Copyright © 2005–2013, Texas Instruments Incorporated  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
www.ti.com  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
Common Performance Specifications LDO 1 to 10  
Unless otherwise noted, VIN = 3.6V, CIN = 1.0 μF, COUT = 0.47 μF, CBYP = 0.1 μF. Typical values and limits appearing in  
normal type apply for TJ= 25°C. Limits appearing in boldface type apply over the entire junction temperature range for  
(1)(2)  
operation, −40 ≤ TJ ≤ 125°C.  
Symbol  
Parameter  
Condition  
Min Typ Max Unit  
s
VOUT  
Accuracy  
LDO 1 Output Voltage  
Accuracy (Default VOUT  
ILOAD = 1 mA  
ILOAD = 1 mA  
ILOAD = 1 mA  
1.22  
85  
1.3  
1.37  
15  
)
)
V
LDO 2 Output Voltage  
Accuracy (Default VOUT  
1.05  
6
1.1  
1.14  
4
LDO 3-10 Output Voltage  
−3  
+3  
%
Accuracy (Default VOUT  
)
ΔVOUT  
Line Regulation  
VIN = (VOUT +0.3) to 5.5V,  
Load Current = IMAX  
0.15 %/V  
(3)  
Load Regulation LDO 1,2,7  
Load Regulation LDO 3,4,5,8  
Load Regulation LDO 6  
VIN = 3.6V,  
Load Current = 1 mA to IMAX  
0.01  
5
0.01  
1
%/m  
A
0.07  
5
Load Regulation LDO 9,10  
0.00  
6
ISC  
Short Circuit Current Limit  
VOUT = 0V  
400  
mA  
mV  
dB  
(4)  
VIN - VOUT Dropout Voltage  
Load Current = 50 mA  
150  
PSRR  
PSRR  
θn  
Digital Supply Ripple Rejection  
f = 10 kHz, Load Current = IMAX  
f = 10 kHz, Load Current = IMAX  
10 Hz < F < 100 kHz  
45  
60  
80  
Analog Supply Ripple Rejection  
dB  
Analog Supply Output Noise Voltage  
uVrm  
s
Analog  
IQ  
Quiescent Current “On”  
IOUT = 0 mA  
40  
60  
80  
IOUT = IMAX  
130  
μA  
μA  
Quiescent Current “Off”  
Quiescent Current “On”  
EN is de-asserted  
IOUT = 0 mA  
0.03  
40  
Digital  
IQ  
95  
IOUT = IMAX  
60  
180  
Quiescent Current “Off”  
Turn On Time  
EN is de-asserted  
0.03  
(5)  
TON  
TSD  
Start up from Shut-down  
300 μsec  
Thermal Shutdown  
Temperature  
160  
20  
°C  
Hysteresis  
COUT  
Output Capacitance  
LDO 1  
Capacitance for Stability  
0.33 0.47  
Output Capacitance  
LDO 2 - 10  
Capacitance for Stability  
°C ≤ TJ ≤ 125°C  
0.33 0.47  
µF  
−40 ≤ TJ ≤ 125°C  
0.68  
5
1
Output Capacitor  
LDO 1 - 10  
ESR  
500  
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which  
operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test  
conditions, see the Electrical Characteristics tables.  
(2) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are  
production tested, and specified through statistical analysis or specified by design. All limits at temperature extremes are specified via  
correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level  
(AOQL).  
(3) LDO 1,2,7 Line Regulation Specified as VIN = 2.5V to 5.5V ILOAD= IMAX. Specification does not apply to LDO 1.  
(4) Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. Dropout  
specification does not apply to LDO 1,2,6,7.  
(5) CBYP not connected to LDO 7 & 8. Use of a CBYP capacitor will increase the LDO's start-up time.  
Copyright © 2005–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
7
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
www.ti.com  
Buck Converters SW1, SW2  
Unless otherwise noted, VIN = VBATT = 3.6V CIN = 10 μF, COUT = 10 μF, LOUT = 2.2 μH Typical values and limits appearing in  
normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for  
(1)(2)  
operation, −40 ≤ TJ ≤ 125°C.  
Symbol  
VOUT  
Parameter  
Output Voltage Accuracy  
Efficiency  
Condition  
Min Typ Max Units  
Default VOUT  
3
3
%
%
Eff  
Load Current = 200 mA  
90  
0.1  
1.6  
1.6  
850  
33  
ISHDN  
Shutdown Supply Current  
Sync Mode Clock Frequency  
Internal Oscillator Frequency  
Peak Switching Current Limit  
Quiescent Current “On”  
EN is de-asserted  
μA  
Synchronized from 13 MHz System Clock  
MHz  
MHz  
mA  
μA  
fOSC  
IPEAK  
IQ  
1.1  
2.0  
55  
(Open Loop)  
No Load PFM Mode  
No Load PWM Mode  
200  
RDSON (P)  
RDSON (N)  
TON  
Pin-Pin Resistance PFET  
Pin-Pin Resistance NFET  
Turn On Time  
400 675  
250 500  
500  
mΩ  
mΩ  
μsec  
°C  
Start up from Shut-down  
Temperature  
TSD  
Thermal Shutdown  
150  
Hysteresis  
20  
CIN  
CO  
Input Capacitor  
Capacitance for Stability  
Capacitance for Stability  
10  
10  
µF  
µF  
Output Capacitor  
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which  
operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test  
conditions, see the Electrical Characteristics tables.  
(2) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are  
production tested, and specified through statistical analysis or specified by design. All limits at temperature extremes are specified via  
correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level  
(AOQL).  
Back-Up Charger Electrical Characteristics  
Unless otherwise noted, VIN = VBATT = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits  
(1)(2) (3)  
appearing in boldface type apply over the entire junction temperature range for operation, −40 ≤ TJ ≤ 125°C.  
,
Symbol  
Parameter  
Condition  
Min Typ Max Unit  
s
VIN  
Operational Voltage Range  
Voltage at VIN  
3.3  
2.8  
5.5  
V
IOUT  
Backup Battery Charging Current (Default  
Setting)  
VIN = 3.6V, Backup_Bat = 2.5V, Backup Battery  
Charger Enabled  
VIN = 5.5V Backup Battery Charger Enabled(4)  
500  
μA  
VOUT  
Charger Termination Voltage  
3.0  
9
3.2  
V
Backup Battery Charger Short Circuit  
Current  
Backup_Bat = 0V, Backup Battery Charger  
Enabled  
mA  
PSRR  
Power Supply Ripple Rejection Ratio  
IOUT ≤ 50 μA, VOUT = 3.15V  
15  
dB  
VOUT + 0.4 ≤ VBATT = VIN ≤ 5.5V  
f < 10 kHz  
IQ  
Quiescent Current  
IOUT < 50 μA  
25  
μA  
μF  
COUT  
Output Capacitance  
Output Capacitor ESR  
0 μA ≤ IOUT ≤ 100 μA  
0.1  
5
500  
MΩ  
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which  
operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test  
conditions, see the Electrical Characteristics tables.  
(2) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are  
production tested, and specified through statistical analysis or specified by design. All limits at temperature extremes are specified via  
correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level  
(AOQL).  
(3) Back-up battery charging current is programmable via the I2C compatible interface. Refer to the Application Hints for more information.  
(4) Test Condition: for Vout less than 2.5V, Vin = 3.6V; for Vout greater than or equal to 2.5V, VIN = Vout + 1V.  
8
Submit Documentation Feedback  
Copyright © 2005–2013, Texas Instruments Incorporated  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
www.ti.com  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
Logic Inputs DC Operating Conditions  
Logic input specifications applies to SYS_EN, PWR_EN and nRSTI.  
Symbol  
Parameter  
Condition  
Min Typ Max Unit  
s
VIL  
Low Level Input Voltage  
0.4  
V
V
VIH  
High Level Input Voltage  
Input Leakage Current  
1.6  
ILEAK  
0.01  
µA  
Logic Output DC Operating Conditions  
Symbol  
Parameter  
Condition  
Min Typ Max Unit  
s
VOL  
Output Low Level  
0.4  
V
V
VOH  
Output High Level  
2.3  
ILEAK  
Output Leakage Current  
+5  
μA  
GPO Logic Output DC Operating Conditions  
The LP3970 contains four (4) general purpose CMOS outputs (GPO) connected to the VDD_RTC. Each GPO can be set to  
high impendence (HiZ), logic high (VOH), or logic low (VOL) by using the serial interface. The default setting is HiZ  
Symbol  
Parameter  
Condition  
Min Typ Max Unit  
s
VOL  
Output Low Level  
0.4  
V
V
VOH  
VHZ  
Output High Level  
2.1  
Logic Current in High Z Mode  
VIN = VRTC/2  
5
μA  
nBATT_FLT DC Operating Conditions  
Symbol  
Parameter  
Condition  
Min Typ Max Unit  
s
nBATT_FLT Default Voltage  
nBATT_FLT Threshold Voltage  
Output Low Level  
2.8  
Programmable via serial data port  
2.5  
3.5  
V
V
VOL  
0.4  
VOH  
Output High Level  
2.3  
V
ILEAK  
Input Leakage Current  
+5  
μA  
I2C Compatible Serial Interface Electrical Specifications  
Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing  
(1)(2)(3)  
in boldface type apply over the entire junction temperature range for operation, −40°C ≤ TJ ≤ 125°C.  
Symbol  
VIL  
Parameter  
Condition  
Min Typ Max Units  
Low Level Input Voltage  
−0.5  
0.3  
V
VRTC  
VIH  
VOL  
IOL  
High Level Input Voltage  
Low Level Output Voltage  
Low Level Output Current  
0.7V  
RTC  
0
VRTC  
0.2  
VTRC  
VOL = 0.4V  
3.0  
mA  
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which  
operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test  
conditions, see the Electrical Characteristics tables.  
(2) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are  
production tested, and specified through statistical analysis or specified by design. All limits at temperature extremes are specified via  
correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level  
(AOQL).  
(3) Both I2C compatible signals from the applications processor have alternate functions as GPIO’s. Following cold-start power-on or a hard  
reset both signals default to GPIO”s. An internal pull-down resistor on each signal prevents them from floating during reset or power-on  
events. The I2C signals behave like open-drain outputs and require an external pull-up resistor on the system module in the 2 kΩ to 20  
kΩ range. The I2C signals from the processor are pulled low after power-up or reset.  
Copyright © 2005–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
9
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
www.ti.com  
I2C Compatible Serial Interface Electrical Specifications (continued)  
Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing  
(1)(2)(3)  
in boldface type apply over the entire junction temperature range for operation, −40°C ≤ TJ ≤ 125°C.  
Symbol  
FCLK  
Parameter  
Clock Frequency  
Condition  
Min Typ Max Units  
400  
kHz  
μs  
μs  
μs  
μs  
μs  
μs  
μs  
μs  
ns  
tBF  
Bus-Free Time Between Start and Stop  
Hold Time Repeated Start Condition  
CLK Low Period  
1.3  
0.6  
1.3  
0.3  
0.6  
0
tHOLD  
tCLKLP  
tCLKHP  
tSU  
CLK High Period  
Set Up Time Repeated Start Condition  
Data Hold Time  
tDATAHLD  
tCLKSU  
TSU  
Data Set Up Time  
100  
0.6  
Set Up Time for Start Condition  
TTRANS  
Maximum Pulse Width of Spikes that Must  
be Suppressed by the Input Filter of Both  
DATA & CLK Signals  
50  
10  
Submit Documentation Feedback  
Copyright © 2005–2013, Texas Instruments Incorporated  
Product Folder Links: LP3970  
 
OBSOLETE  
LP3970  
www.ti.com  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
Typical Performance Characteristics — LDO Characteristics  
Output Voltage Change  
vs.  
Ground Current  
vs.  
Load Current  
Temperature  
2.00  
1.50  
1.00  
0.50  
0.00  
-0.50  
-1.00  
-1.50  
-2.00  
80  
70  
60  
50  
40  
30  
20  
10  
0
T
= 125°C  
J
T
= -40°C  
J
T
J
= 25°C  
0
25  
50  
75  
100  
125  
150  
-40 -25  
0
25  
50  
75 100 125  
LOAD CURRENT (mA)  
TEMPERATURE (°C)  
Figure 2.  
Figure 3.  
Enable Start-Up Time  
Enable Start-Up Time  
I
1 mA  
I
150 mA  
L =  
L =  
LDO ENABLE  
LDO ENABLE  
TIME (50 ms/DIV)  
TIME (50 ms/DIV)  
Figure 4.  
Figure 5.  
Output Voltage  
vs.  
Temperature, VOUT = 1.45V)  
Load Transient  
1.480  
1.475  
1.470  
1.465  
1.460  
1.455  
1.450  
1.445  
1.440  
1.435  
1.430  
C
C
= 1 mF  
IN  
= 0.47 mF  
OUT  
PFM Mode  
I
= 10 mA  
OUT  
I
= 300 mA  
OUT  
PWM Mode  
150  
1
V
V
= 3.6V  
IN  
= 1.45V  
I
= 600 mA  
OUT  
OUT  
TIME (20 ms/DIV)  
-30  
-10  
10  
30  
50  
70 90  
TEMPERATURE (oC)  
Figure 6.  
Figure 7.  
Copyright © 2005–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
11  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
www.ti.com  
Typical Performance Characteristics — Buck Converter Characteristics  
Buck1 Change in Output Voltage  
RDSON  
vs.  
Temperature  
vs.  
Load Current  
600  
550  
500  
450  
400  
350  
300  
250  
200  
150  
100  
50  
40  
V
= 2.8V  
IN  
V
V
= 3.6V  
IN  
V
= 4.5V  
IN  
= 1.45V  
OUT  
V
= 3.6V  
= 2.8V  
IN  
30  
20  
PFET  
10  
V
IN  
0
-10  
-20  
-30  
-40  
-50  
V
= 4.5V  
IN  
NFET  
V
= 3.6V  
10  
IN  
0
100  
200  
300  
400  
500 600  
-30 -10  
30  
50  
70  
90 110  
TEMPERATURE (oC)  
LOAD CURRENT (mA)  
Figure 8.  
Figure 9.  
Efficiency  
vs.  
Efficiency  
vs.  
Output Current  
Output Current  
(VOUT = 1.45V, L = 2.2 µH)  
(VOUT = 1.8V, L = 2.2 µH)  
100  
100  
90  
80  
70  
60  
50  
40  
30  
20  
V
= 1.8V  
V
= 1.5V  
OUT  
OUT  
V
= 2.8V  
V
IN  
= 3.0V  
IN  
90  
80  
70  
60  
50  
40  
30  
20  
V
IN  
= 3.0V  
V
IN  
= 2.8V  
V
= 4.5V  
IN  
V
= 4.5V  
IN  
V
= 3.6V  
IN  
V
= 3.6V  
IN  
0.01  
0.10  
1.00  
10.00 100.00 1000.00  
0.01  
0.10  
1.00  
10.00 100.00 1000.00  
OUTPUT CURRENT (mA)  
OUTPUT CURRENT (mA)  
Figure 10.  
Figure 11.  
Switching Frequency  
vs.  
Temperature  
Line Transient Response (PWM Mode)  
1.62  
V
IN  
= 4.5V  
1.60  
1.58  
1.56  
1.54  
1.52  
1.50  
20 mV/DIV  
AC Coupled  
V
OUT  
V
= 3.6V  
= 2.8V  
IN  
V
IN  
3.6V  
3.0V  
V
IN  
V
I
= 1.5V  
OUT  
I
= 300 mA  
= 400 mA  
OUT  
OUT  
-
10  
_
10  
_
50  
_
70  
90  
40 ms/DIV  
-30  
30  
_
_
TEMPERATURE (oC)  
Figure 12.  
Figure 13.  
12  
Submit Documentation Feedback  
Copyright © 2005–2013, Texas Instruments Incorporated  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
www.ti.com  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
Typical Performance Characteristics — Buck Converter Characteristics (continued)  
Load Transient Response (PWM Mode)  
Load Transient Response (PFM Mode 0.5 mA to 50 mA)  
V
V
SW  
2V/DIV  
2V/DIV  
SW  
50 mV/DIV  
V
20 mV/DIV  
OUT  
AC Coupled  
AC Coupled  
V
I
OUT  
V
V
= 3.6V  
V
V
= 3.6V  
IN  
IN  
= 1.5V  
= 1.5V  
OUT  
OUT  
50 mA  
0.5 mA  
400 mA  
200 mA  
I
OUT  
OUT  
100 ms/DIV  
40 ms/DIV  
Figure 14.  
Figure 15.  
Load Transient Response (PFM Mode 50 mA to 0.5 mA)  
Start Up into PWM Mode (Output Current = 300 mA)  
2V/DIV  
V
SW  
V
SW  
2V/DIV  
I
= 300 mA  
OUT  
20 mV/DIV  
500 mA/DIV  
1V/DIV  
AC Coupled  
V
OUT  
OUT  
I
L
V
V
= 3.6V  
IN  
= 1.5V  
OUT  
V
50 mA  
0.5 mA  
OUT  
I
V
= 3.6V  
IN  
V
OUT  
= 1.5V  
40 ms/DIV  
TIME (100 ms/DIV)  
Figure 16.  
Figure 17.  
Start Up into PFM Mode (Output Current = 1 mA)  
2V/DIV  
V
SW  
500 mV/DIV  
V
OUT  
V
V
= 3.6V  
IN  
OUT  
= 1 mA  
= 1.5V  
I
OUT  
TIME (100 ms/DIV)  
Figure 18.  
Copyright © 2005–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
13  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
www.ti.com  
Functional Block Diagram  
GND  
BUCK2  
V
IN  
FB2  
BUCK2  
÷
SW2  
SYS_EN  
PWR_EN  
SYNC  
FB1  
BUCK1  
nRSTO  
nRSTI  
SW1  
V
BUCK1  
IN  
RESET  
GND  
LDO1  
V
LDO1  
OUT  
nBATT_FLT  
nVDD_FLT  
V
V
LDO1  
IN  
LDO2  
IN  
LDO2  
LDO9  
V
LDO2  
OUT  
POWER-ON/OFF  
LOGIC  
DIGITAL  
INTERFACE  
SCL  
V
LDO9  
OUT  
&
SDA  
REGISTERS  
V
LDO 4, 9  
LDO4  
IN  
SERIAL CONTROL  
DEFAULT VOLTAGE  
V
LDO4  
OUT  
GPO1  
GPO2  
GPO3  
GPO4  
V
LDO5  
LDO5  
LDO6  
OUT  
V
LDO 5, 6  
IN  
AGND  
DGND  
V
LDO6  
LDO7  
OUT  
V
V
LDO7  
IN  
LDO7  
OUT  
V
V
CAP  
BIAS  
LDO10  
LDO10  
OUT  
V
LDO 3,10  
IN  
V
LDO3  
OUT  
LDO3  
LDO8  
BU BATTERY  
CHARGER  
V
V
CAP LDO8  
LDO8  
BIAS  
OUT  
Batt_SW  
BACK-UP  
BATTERY IN  
LDO_RTC  
V
OUT  
RTC  
V
RTC, LDO8,  
IN  
BATT_MON  
MAIN BATTERY  
MONITOR  
14  
Submit Documentation Feedback  
Copyright © 2005–2013, Texas Instruments Incorporated  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
www.ti.com  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
BUCK CONVERTER OPERATION  
DEVICE INFORMATION  
The LP3970 includes two high efficiency step down DC-DC switching buck converters. Using a voltage mode  
architecture with synchronous rectification, the buck converters have the ability to deliver up to 600 mA  
depending on the input voltage, output voltage, ambient temperature and the inductor chosen.  
There are three modes of operation depending on the current required - PWM, PFM, and shutdown. The device  
operates in PWM mode at load currents of approximately 80 mA or higher, having voltage tolerance of ±4% with  
90% efficiency or better. Lighter load currents cause the device to automatically switch into PFM for reduced  
current consumption. Shutdown mode turns off the device, offering the lowest current consumption (IQ, SHUTDOWN  
= 0.01 μA typ).  
Additional features include soft-start, under voltage protection, current overload protection, and thermal shutdown  
protection.  
The part uses an internal reference voltage of 0.5V. It is recommended to keep the part in shutdown until the  
input voltage is 2.8V or higher.  
CIRCUIT OPERATION  
The buck converters operates as follows. During the first portion of each switching cycle, the control block turns  
on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter  
capacitor and load. The inductor limits the current to a ramp with a slope of (VIN–VOUT)/L, by storing energy in a  
magnetic field.  
During the second portion of each cycle, the controller turns the PFET switch off, blocking current flow from the  
input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the  
NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of - VOUT/L.  
The output filter stores charge when the inductor current is high, and releases it when inductor current is low,  
smoothing the voltage across the load.  
The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the  
load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and  
synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The  
output voltage is equal to the average voltage at the SW pin.  
PWM OPERATION  
During PWM operation the converter operates as a voltagemode controller with input voltage feed forward. This  
allows the converter to achieve good load and line regulation. The DC gain of the power stage is proportional to  
the input voltage. To eliminate this dependence, feed forward inversely proportional to the input voltage is  
introduced.  
While in PWM (Pulse Width Modulation) mode, the output voltage is regulated by switching at a constant  
frequency and then modulating the energy per cycle to control power to the load. At the beginning of each clock  
cycle the PFET switch is turned on and the inductor current ramps up until the comparator trips and the control  
logic turns off the switch. The current limit comparator can also turn off the switch in case the current limit of the  
PFET is exceeded. Then the NFET switch is turned on and the inductor current ramps down. The next cycle is  
initiated by the clock turning off the NFET and turning on the PFET.  
Copyright © 2005–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
15  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
www.ti.com  
V
SW  
2V/DIV  
I
L
200 mA/DIV  
V
V
= 3.6V  
IN  
I
= 400 mA  
OUT  
= 1.5V  
OUT  
V
OUT  
10 mV/DIV  
AC Coupled  
TIME (200 ns/DIV)  
Figure 19. Typical PWM Operation  
Internal Synchronous Rectification  
While in PWM mode, the converters uses an internal NFET as a synchronous rectifier to reduce rectifier forward  
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in  
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier  
diode.  
Current Limiting  
A current limit feature allows the converters to protect itself and external components during overload conditions.  
PWM mode implements current limiting using an internal comparator that trips at 850 mA (typ). If the output is  
shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration  
until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby  
preventing runaway.  
PFM OPERATION  
At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply  
current to maintain high efficiency.  
The part will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or  
more clock cycles:  
A:  
B:  
The inductor current becomes discontinuous.  
The peak PMOS switch current drops below the IMODE level, (Typically IMODE < 30 mA + VIN/42Ω).  
2V/DIV  
V
SW  
I
L
200 mA/DIV  
VIN = 3.6V  
I
= 20 mA  
OUT  
VOUT = 1.5V  
V
OUT  
20 mV/DIV  
AC Coupled  
TIME (4 ms/DIV)  
Figure 20. Typical PFM Operation  
16  
Submit Documentation Feedback  
Copyright © 2005–2013, Texas Instruments Incorporated  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
www.ti.com  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage  
during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy  
load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output  
FETs such that the output voltage ramps between ∼0.6% and ∼1.7% above the nominal PWM output voltage. If  
the output voltage is below the “high” PFM comparator threshold, the PMOS power switch is turned on. It  
remains on until the output voltage reaches the ‘high’ PFM threshold or the peak current exceeds the IPFM level  
set for PFM mode. The typical peak current in PFM mode is: IPFM = 112 mA + VIN/27Ω.  
Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps  
to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output  
voltage is below the ‘high’ PFM comparator threshold (see Figure 21), the PMOS switch is again turned on and  
the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM  
threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output  
switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this  
‘sleep’ mode is 16 μA (typ), which allows the part to achieve high efficiencies under extremely light load  
conditions. When the output drops below the ‘low’ PFM threshold, the cycle repeats to restore the output voltage  
(average voltage in PFM mode) to ∼1.15% above the nominal PWM output voltage.  
If the load current should increase during PFM mode (see Figure 21) causing the output voltage to fall below the  
‘low2’ PFM threshold, the part will automatically transition into fixed-frequency PWM mode. When VIN = 2.8V the  
part transitions from PWM to PFM mode at ∼35 mA output current and from PFM to PWM mode at ∼85 mA ,  
when VIN = 3.6V, PWM to PFM transition happens at ∼50 mA and PFM to PWM transition happens at ∼100 mA,  
when VIN = 4.5V, PWM to PFM transition happens at ∼65 mA and PFM to PWM transition happens at ∼115 mA.  
High PFM Threshold  
PFM Mode at Light Load  
~1.017*Vout  
Load current  
increases  
Low1 PFM Threshold  
~1.006*Vout  
Current load  
increases,  
draws Vout  
towards  
Low2 PFM  
Threshold  
High PFM  
Nfet on  
drains  
conductor  
current  
until  
I inductor=0  
Low PFM  
Threshold,  
turn on  
Pfet on  
until  
Voltage  
Threshold  
reached,  
go into  
Ipfm limit  
reached  
PFET  
Low2 PFM Threshold  
Vout  
sleep mode  
PWM Mode at  
Moderate to Heavy  
Loads  
Low2 PFM Threshold,  
switch back to PWMmode  
Figure 21. Operation in PFM Mode and Transfer to PWM Mode  
SHUTDOWN MODE  
During shutdown the PFET switch, NFET switch, reference, control and bias circuitry of the converters are turned  
off. When the converter is enabled, EN, soft start is activated. It is recommended to disable the converter during  
the system power up and undervoltage conditions when the supply is less than 2.8V.  
Copyright © 2005–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
17  
Product Folder Links: LP3970  
 
OBSOLETE  
LP3970  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
www.ti.com  
SOFT START  
The buck converter has a soft-start circuit that limits in-rush current during start-up. During start-up the switch  
current limit is increased in steps. Soft start is activated only if EN goes from logic low to logic high after VIN  
reaches 2.8V. Soft start is implemented by increasing switch current limit in steps of 70 mA, 140 mA, 280 mA  
and 1020 mA (typ. switch current limit). The start-up time thereby depends on the output capacitor and load  
current demanded at start-up. Typical start-up times with 22 μF output capacitor and 300 mA load current is 400  
μs and with 1 mA load current its 275 μs.  
LDO - LOW DROP OUT OPERATION  
The buck converter can operate at 100% duty cycle (no switching, PMOS switch completely on) for low drop out  
support of the output voltage. In this way the output voltage will be controlled down to the lowest possible input  
voltage.  
The minimum input voltage needed to support the output voltage is  
VIN, MIN = ILOAD * (RDSON, PFET + RINDUCTOR) + VOUT  
where  
•
•
•
ILOAD: Load Current  
RDSON, PFET: Drain to source resistance of PFET switch in the triode region  
RINDUCTOR: Inductor resistance  
(1)  
Table 2. Power Controller Interface Signals  
Signal  
PWR_EN  
SYS_EN  
PWR_SCL  
PWR_SDA  
nRSTI  
Definition  
Low voltage power enable  
High voltage power enable  
Serial bus clock  
Active State  
High  
Signal Direction (x)  
Input  
High  
Input  
Clock  
Input  
Serial bus data  
Bidirectional  
Input  
Forces an unconditional hardware reset  
Forces an unconditional hardware reset  
Low  
Low  
Low  
nRSTO  
Output  
nBATT_FLT  
Indicates main battery removed or  
discharged  
Output  
nVDD_FLT  
Indicates one or more supplies are out of  
regulation  
Low  
Output  
nRSTI Forces an unconditional reset when activated from a momentary contact push button switch.  
nRSTO is an active-low signal from the PMU to the Applications processor that tells the processor to enter the  
hardware-reset state. nRSTO is asserted for a cold start power-on or if the reset button is pushed. The  
PMU must assert nRSTO for both events. nRSTO will remain asserted for a minimum of 50 ms.  
PWR_EN is an active-high input to the PMU from the Applications processor that enables the low voltage power  
supplies (VCC_CORE, VCC_SRAM, and VCC_PLL).  
SYS_EN is an active-high input to the PMU from the Applications processor that enables the high voltage power  
supplies (VCC_IO, VCC_LCD, VCC_MEM, VCC_USIM, VCC_BB, and VCC_USB).  
nVDD_FLT signals the Applications processor that one or more of it’s enabled supplies are below the minimum  
regulation limit (supplies that are not enabled do not cause nVDD_FLT assertion).  
Table 3. Power Enables  
PMU Output  
LDO_RTC  
Enable  
Applications Input  
VCC_BAT  
Supply Reference  
Sleep-control subsystem. oscillators, and real-time clock  
Phase locked loops  
None  
LDO1  
LDO2  
LDO3  
LDO4  
LDO5  
PWR_EN  
PWR_EN  
SYS_EN  
SYS_EN  
SYS_EN  
VCC_PLL  
VCC_SRAM  
VCC_USB  
Internal SRAM  
Differential USB interface  
VCC_IO  
Peripheral input/output  
VCC_USIM  
USIM interface  
18  
Submit Documentation Feedback  
Copyright © 2005–2013, Texas Instruments Incorporated  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
www.ti.com  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
Table 3. Power Enables (continued)  
PMU Output  
Enable  
SYS_EN  
Applications Input  
Supply Reference  
LDO6  
LDO7  
LDO8  
LDO9  
LDO10  
SW1  
VCC_BB/LCD  
Peripheral  
Peripheral  
Peripheral  
Peripheral  
VCC_CORE  
VCC_MEM  
Baseband interface, LCD input/output  
PWR_EN  
SYS_EN  
SYS_EN  
SYS_EN  
PWR_EN  
SYS_EN  
AUX1, GP Analog  
AUX2, GP Analog  
AUX3, GP Digital  
AUX4, GP Digital  
CPU Core  
SW2  
Memory controller input/output  
I2C Compatible Interface  
I2C DATA VALIDITY  
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of  
the data line can only be changed when CLK is LOW.  
SCL  
SDA  
DATA  
DATA VALID  
DATA  
DATA  
DATA VALID  
CHANGE  
ALLOWED  
CHANGE  
ALLOWED  
CHANGE  
ALLOWED  
I2C START AND STOP CONDITIONS  
START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA  
signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA  
transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits.  
The I2C bus is considered to be busy after START condition and free after STOP condition. During data  
transmission, I2C master can generate repeated START conditions. First START and repeated START  
conditions are equivalent, function-wise.  
SDA  
SCL  
S
P
START CONDITION  
STOP CONDITION  
TRANSFERRING DATA  
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.  
The number of bytes that can be transmitted per transfer is unrestricted. Each byte of data has to be followed by  
an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases  
the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the  
9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an  
acknowledge after each byte has been received.  
After the START condition, a chip address is sent by the I2C master. This address is seven bits long followed by  
an eighth bit which is a data direction bit (R/W). The LP3970 address is 46h. For the eighth bit, a “0” indicates a  
WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The  
third byte contains data to write to the selected register.  
Copyright © 2005–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
19  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
www.ti.com  
ack from slave  
ack  
ack from slave  
ack stop  
ack from slave  
start  
msb Chip Address lsb  
w
ack  
msb Register Add lsb  
msb DATA lsb  
SCL  
SDA  
start  
Id = 46h  
w
ack  
addr = 02h  
ack  
address h‘02 data  
ack stop  
w = write (SDA = “0”)  
r = read (SDA = “1”)  
ack = acknowledge (SDA pulled down by either master or slave)  
rs = repeated start  
xx = 46h  
However, if a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in  
Figure 5.  
Figure 22. I2C Write Cycle  
ack from slave  
ack from slave repeated start  
ack from slave data from slave ack from master  
start msb Chip Address lsb  
w
msb Register Add lsb  
rs  
msb Chip Address lsb  
r
msb DATA lsb  
stop  
SCL  
SDA  
start  
Id = 46h  
w
ack  
addr = h‘00  
ack rs  
Id = 46h  
r
ack  
Address h‘00 data  
ack stop  
Figure 23. I2C Read Cycle  
SDA  
SCL  
10  
7
8
7
6
1
8
2
5
1
4
9
3
Figure 24. I2C Timing Diagram  
Table 4. LP3970 Serial Port Communication Address Code 7h’46  
1
0
0
0
1
1
0
R/W  
20  
Submit Documentation Feedback  
Copyright © 2005–2013, Texas Instruments Incorporated  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
www.ti.com  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
Numbers in parentheses indicate default setting. (0) bit is set to low state and(1) bit is set to high state. R/O  
–Read Only, All other bits are Read and Write.  
Table 5. LP3970 Control and Data Codes  
Addrs  
Register  
7
6
5
4
3
2
1
0
8h'0  
Enable 0  
LDO8–EN  
(1)  
LDO7–EN  
(1)  
LDO6–EN  
(1)  
LDO5–EN  
(1)  
LDO4–EN  
(1)  
LDO3–EN  
(1)  
LDO2–EN  
(1)  
LDO1_EN  
(1)  
8h'01  
8h'02  
Enable 1  
Not used  
(0)  
Not used  
(0)  
Not used  
(0)  
Not used  
(0)  
Buck2_EN  
(1)  
Buck1_EN LDO10_EN LDO9_EN  
(1)  
(1)  
(1)  
GPO  
Control  
GPO4  
nHZ EN  
(0)  
GPO4  
EN  
(0)  
GPO3  
nHZ EN  
(0)  
GPO3  
EN  
(0)  
GPO2  
nHZ EN  
(0)  
GPO2  
EN  
(0)  
GPO1  
nHZ EN  
(0)  
GPO1  
EN  
(0)  
8h'03  
8h'04  
8h'05  
8h'06  
8h'08  
8h'09  
8h'0A  
8h'0B  
8h'0C  
8h'0D  
LDO3  
Data  
Code  
Not used  
(0)  
Not used  
(0)  
Not used  
(0)  
VOUT  
(0)  
VOUT  
(1)  
VOUT  
(1)  
VOUT  
(0)  
VOUT  
(1)  
LDO4  
Data  
Code  
Not used  
(0)  
Not used  
(0)  
Not used  
(0)  
VOUT  
(0)  
VOUT  
(1)  
VOUT  
(1)  
VOUT  
(0)  
VOUT  
(1)  
LDO5  
Data  
Code  
Not used  
(0)  
Not used  
(0)  
Not used  
(0)  
VOUT  
(0)  
VOUT  
(1)  
VOUT  
(1)  
VOUT  
(1)  
VOUT  
(1)  
LDO6  
Data  
Code  
Not used  
(0)  
Not used  
(0)  
Not used  
(0)  
VOUT  
(0)  
VOUT  
(1)  
VOUT  
(1)  
VOUT  
(0)  
VOUT  
(1)  
LDO8  
Data  
Code  
Not used  
(0)  
Not used  
(0)  
Not used  
(0)  
VOUT  
(0)  
VOUT  
(1)  
VOUT  
(1)  
VOUT  
(0)  
VOUT  
(1)  
LDO9  
Data  
Code  
Not used  
(0)  
Not used  
(0)  
Not used  
(0)  
VOUT  
(0)  
VOUT  
(1)  
VOUT  
(1)  
VOUT  
(0)  
VOUT  
(1)  
LDO10  
Data  
Code  
Not used  
(0)  
Not used  
(0)  
Not used  
(0)  
VOUT  
(0)  
VOUT  
(1)  
VOUT  
(1)  
VOUT  
(0)  
VOUT  
(1)  
Buck1  
Data  
Code  
Not used  
(0)  
Ext_clk  
EN  
(0)  
nStep_EN  
(1)  
VOUT  
(0)  
VOUT  
(1)  
VOUT  
(1)  
VOUT  
(1)  
VOUT  
(0)  
Buck2  
Data  
Code  
Not used  
(0)  
Ext_clk  
EN  
(0)  
nStep_EN  
(1)  
VOUT  
(0)  
VOUT  
(0)  
VOUT  
(0)  
VOUT  
(0)  
VOUT  
(1)  
Back Up  
Battery  
Charger  
nBU_Bat  
EN  
nBat_FLT  
EN  
BAT_FLT  
Voltage  
(0)  
BAT_FLT  
Voltage  
(1)  
BAT_FLT  
Voltage  
(0)  
nBU_Bat  
Charger  
Enable  
(0)  
BU_Bat  
Charger  
Current  
(0)  
BU_Bat  
Charger  
Current  
(1)  
(0)  
(0)  
Output Voltage Selection Codes  
Data Code  
LDO's  
Buck_1 (V)  
N/A  
Buck _2 (V)  
N/A  
1.8  
5h'00  
5h'01  
5h'02  
5h'03  
5h'04  
5h'05  
5h'06  
5h'07  
5h'08  
5h'09  
5h'0A  
5h'0B  
1.5  
1.6  
1.7  
1.8  
1.9  
2.0  
2.1  
2.2  
2.3  
2.4  
2.5  
2.6  
0.80  
0.85  
1.9  
0.90  
2.0  
0.95  
2.1  
1.00  
2.2  
1.05  
2.3  
1.10  
2.4  
1.15  
2.5  
1.20  
2.6  
1.25  
2.7  
1.30  
2.8  
Copyright © 2005–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
21  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
www.ti.com  
Output Voltage Selection Codes  
5h'0C  
5h'0D  
5h'0E  
5h'0F  
5h'10  
5h'11  
5h'12  
5h'13  
5h'14  
5h'15  
5h'16  
5h'17  
5h'18  
5h'19  
5h'1A  
5h'1B  
5h'1C  
5h'1D  
5h'1E  
5h'1F  
2.7  
1.35  
1.40  
1.45  
1.50  
1.55  
1.60  
1.65  
1.70  
1.75  
1.80  
1.85  
1.90  
1.95  
2.00  
2.9  
3.0  
3.1  
3.2  
3.3  
2.8  
2.9  
3.0  
3.1  
3.2  
3.3  
3.4  
nBATT_FLT Threshold Voltage  
Voltage Selection Codes  
Bold face voltages are default values  
Data Code  
3h'00  
De-asserted  
Asserted  
2.4  
2.6  
2.8  
3.0  
3.2  
3.4  
2.6  
2.8  
3.0  
3.2  
3.4  
3.6  
3h'01  
3h'02  
3h'03  
3h'04  
3h'05  
Battery Monitoring  
When Back-Up battery is connected but Main battery removed or voltage too low, LP3970 uses Back-Up Battery  
for generating LDO_RTC voltage. When Main Battery is available the battery switch changes main battery for  
LDO_RTC voltage and Back-Up Battery charger starts charging. User can set the battery fault determination  
voltage and battery charging current via I2C compatible interface.  
BU Charger Current Selection Code  
Data Code  
2h'00  
ISET (μA)  
375  
2h'01  
500  
2h'02  
625  
Power On Sequence  
The Power Management Unit (PMU) supplies both high-voltage (I/O) and low-voltage power to the Applications  
processor. There are two power control signal inputs to the LM3970 PMU. SYS_EN controls the high-voltage  
supplies and PWR_EN controls the low-voltage supplies. When the back-up battery is installed, the processor  
begins the initial cold-start, power-up sequence enabling its internal power management unit and one oscillator.  
22  
Submit Documentation Feedback  
Copyright © 2005–2013, Texas Instruments Incorporated  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
www.ti.com  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
The LP3970 will monitor voltages and generate the nBATT_FLT and nVDD_FLT signals. The LP3970 will assert  
both nBATT_FLT and nVDD_FLT until VIN is above the default threshold voltage.  
INITIAL COLD START POWER ON SEQUENCE  
1. The Back up battery is connected to the PMU, power is applied to the back-up battery pin, the RTC_LDO  
turns on and supplies a stable output voltage to the VCC_BATT pin of the Applications processor (initiating  
the power-on reset event) with nRSTO asserted from the LP3970 to the processor.  
2. nRSTO de-asserts after a minimum of 50 mS.  
3. The Applications processor waits for the de-assertion of nBATT_FLT to indicate system power (VIN) is  
available.  
4. After system power (VIN) is applied, the LP3970 de-asserts nBATT_FLT.  
5. The Applications processor asserts SYS_EN, the LP3970 enables the system high-voltage power supplies.  
The Applications processor starts its countdown timer set to 125 mS  
6. The LP3970 enables the high-voltage power supplies.  
7. Countdown timer expires; the Applications processor asserts PWR_EN to enable the low-voltage power  
supplies. The processor starts the countdown timer set to 125 mS period.  
8. The Applications processor asserts PWR_EN, the LP3970 enables the low-voltage regulators.  
9. Countdown timer expires; If nVDD_FLT is de-asserted the power up sequence continues by enabling the  
processors 13 MHz oscillator and PLL’s.  
10. The Applications processor begins the execution of code.  
Figure 25. Cold Start Power on Timing  
t
t
t
4
t
5
3
1
V
BU BATT  
IN  
V
_RTC  
CC  
nRSTO  
V
IN  
MAIN BATT  
nBATT_FLT  
SYS_EN  
PXA27x OUTPUT  
PXA27x OUTPUT  
HIGH_VOLT_PD  
PWR_EN  
LOW_VOLT_PD  
nVDD_FLT  
t
2
t
6
PXA27x OUTPUT  
PXA27x OUTPUT  
nRESET_OUT  
13MHZ_OSC  
Table 6. Power-On Timing Specifications  
Symbol Description  
Min  
Typ  
Max  
Units  
ms  
μs  
t1  
t2  
t3  
t4  
t5  
t6  
Delay from VCC_RTC assertion to nRSTO de-assertion  
Delay from nBATT_FLT de-assertion to nRESET assertion  
Delay from nRST de-assertion to SYS_EN assertion  
Delay from SYS_EN assertion to PWT_EN assertion  
Delay from PWR_EN assertion to nVDD_FLT de-assertion  
Delay from PWR_EN assertion to nRST_OUT de-assertion  
50  
100  
10  
ms  
ms  
ms  
ms  
125  
120  
125  
Copyright © 2005–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
23  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
www.ti.com  
Hardware Reset Sequence  
Hardware reset initiates when the nRSTI signal is asserted (low). Upon assertion of nRST the processor enters  
hardware reset state. The LP3970 must hold the nRST low long enough to allow the processor time to initiate the  
reset state, which is a minimum of 50 ms  
RESET SEQUENCE  
1. nRSTI is asserted  
2. nRSTO is asserted and will de-asserts after a minimum of 50 ms.  
3. The Applications processor waits for the de-assertion of nBATT_FLT to indicate system power (VIN) is  
available.  
4. After system power (VIN) is turned on, the LP3970 de-asserts nBATT_FLT.  
5. The Applications processor asserts SYS_EN, the LP3970 enables the system high-voltage power supplies.  
The Applications processor starts its countdown timer set to 125 ms.  
6. The LP3970 enables the high-voltage power supplies.  
7. Countdown timer expires; the Applications processor asserts PWR_EN to enable the low-voltage power  
supplies. The processor starts the countdown timer set to 125 mS period.  
8. The Applications processor asserts PWR_EN, the LP3970 enables the low-voltage regulators.  
9. Countdown timer expires; If nVDD_FLT is de-asserted the power up sequence continues by enabling the  
processors 13 MHz oscillator and PLL’s.  
10. The Applications processor begins the execution of code.  
24  
Submit Documentation Feedback  
Copyright © 2005–2013, Texas Instruments Incorporated  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
www.ti.com  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
Typical Application Circuit  
CONNECTION DIAGRAM FOR PXA27X AND LP3970  
AUX 4 DIGITAL  
AUX 3 DIGTIAL  
AUX 2 ANALOG  
AUX 1 ANALOG  
LDO_10  
LDO_9  
LDO_8  
LDO_7  
SD/CF MEMORY  
EXT_SDMEM TABLE @ 100 mA  
CARD  
GPO‘s (4)  
4
SDRAM  
EXT_SDRAM TABLE @ 80mA  
V
_MEM TABLE @ 300 mA  
CC  
BUCK CONVERTER 2  
V
CC  
_LCD 2.8V @ 11 mA  
PX27x  
APPLICATION  
PROCESSOR  
V
_BB 2.8V @ 9mA  
CC  
LDO_6  
LDO_5  
LDO_4  
V
_USIM 3.0V @ 0.3 mA  
CC  
V
_IO TABLE @ 25 mA  
CC  
V
_USB 2.8V @ 25 mA  
CC  
LDO_3  
LDO_2  
LDO_1  
V
_SRAM 1.1V @ 50 mA  
_PLL 1.3V @ 40 mA  
CC  
V
CC  
BUCK CONVERTER_1  
0.85 to 2.0 V  
V
CORE  
1.45V @ 650 mA  
LDO_RTC/  
BATT_SW  
V
IN  
V
CC  
_RTC 2.8V @ 5 mA  
+
-
BACK-UP  
BATTERY  
2
2
I C  
I C SCL &SDA  
PWR_EN  
SYS_EN  
PWR_EN  
SYS_EN  
nREST  
nRSTI  
nRSTO  
nVDD_FLT  
nVDD_FAULT  
nBATT_FAULT  
nVBATT_FLT  
Figure 26. Power Domains  
Application Hints  
LDO CONSIDERATIONS  
External Capacitors  
The LP3970's regulators requires external capacitors for regulator stability. These are specifically designed for  
portable applications requiring minimum board space and smallest components. These capacitors must be  
correctly selected for good performance.  
Input Capacitor  
An input capacitor is required for stability. It is recommended that a 1.0 µF capacitor be connected between the  
LDO input pin and ground (this capacitance value may be increased without limit).  
Copyright © 2005–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
25  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
www.ti.com  
This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean  
analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.  
Important:Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low  
impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input,  
it must be specified by the manufacturer to have a surge current rating sufficient for the application.  
There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and  
temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain  
approximately 1.0 µF over the entire operating temperature range.  
Output Capacitor  
The LDO's are designed specifically to work with very small ceramic output capacitors. A 1.0 µF ceramic  
capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5 mΩ to 500 mΩ, are suitable in the  
application circuit.  
For this device the output capacitor should be connected between the VOUT pin and ground.  
It is also possible to use tantalum or film capacitors at the device output, COUT (or VOUT), but these are not as  
attractive for reasons of size and cost (see the section Capacitor Characteristics).  
The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR  
value that is within the range 5 mΩ to 500 mΩ for stability.  
No-Load Stability  
The LDO's will remain stable and in regulation with no external load. This is an important consideration in some  
circuits, for example CMOS RAM keep-alive applications.  
Capacitor Characteristics  
The LDO's are designed to work with ceramic capacitors on the output to take advantage of the benefits they  
offer. For capacitance values in the range of 0.47 µF to 4.7 µF, ceramic capacitors are the smallest, least  
expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The  
ESR of a typical 1.0 µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR  
requirement for stability for the LDO's.  
For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure  
correct device operation. The capacitor value can change greatly, depending on the operating conditions and  
capacitor type.  
In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the  
specification is met within the application. The capacitance can vary with DC bias conditions as well as  
temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging.  
The capacitor parameters are also dependant on the particular case size, with smaller sizes giving poorer  
performance figures in general. As an example, Figure 27 shows a typical graph comparing different capacitor  
case sizes in a Capacitance vs. DC Bias plot. As shown in the graph, increasing the DC Bias condition can result  
in the capacitance value falling below the minimum value given in the recommended capacitor specifications  
table. Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias  
voltages. It is therefore recommended that the capacitor manufacturers’ specifications for the nominal value  
capacitor are consulted for all conditions, as some capacitor sizes (e.g. 0402) may not be suitable in the actual  
application.  
26  
Submit Documentation Feedback  
Copyright © 2005–2013, Texas Instruments Incorporated  
Product Folder Links: LP3970  
 
OBSOLETE  
LP3970  
www.ti.com  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
0603, 10V, X5R  
100%  
80%  
60%  
0402, 6.3V, X5R  
40%_  
20%  
2.0  
_
3.0  
_
4.0  
_
5.0  
_
_
0
1.0  
DC BIAS (V)  
Figure 27. Graph Showing a Typical Variation in Capacitance vs. DC Bias  
The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a  
temperature range of −55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R  
has a similar tolerance over a reduced temperature range of −55°C to +85°C. Many large value ceramic  
capacitors, larger than 1 µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance  
can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over  
Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C.  
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more  
expensive when comparing equivalent capacitance and voltage ratings in the 0.47 µF to 4.7 µF range.  
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size  
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the  
stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic  
capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about  
2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed.  
BUCK CONSIDERATIONS  
Inductor Selection  
There are two main considerations when choosing an inductor; the inductor should not saturate, and the inductor  
current ripple is small enough to achieve the desired output voltage ripple. Different saturation current rating  
specs are followed by different manufacturers so attention must be given to details. Saturation current ratings are  
typically specified at 25°C so ratings at max ambient temperature of application should be requested from  
manufacturer.  
There are two methods to choose the inductor saturation current rating.  
Method 1:  
The saturation current is greater than the sum of the maximum load current and the worst case average to peak  
inductor current. This can be written as  
ISAT > IOUTMAX + IRIPPLE  
«
∆
∆
«
∆
∆
≈
«
∆
∆
≈
≈
∆
∆
«
≈
∆
∆
«
≈
∆
∆
«
VIN - VOUT  
VOUT  
VIN  
1
f
WHERE IRIPPLE  
=
*
*
≈
L
2
*
Copyright © 2005–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
27  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
www.ti.com  
where  
•
•
•
•
•
•
IRIPPLE: Average to peak inductor current  
IOUTMAX: Maximum load current (600 mA)  
VIN: Maximum input voltage in application  
L: Min inductor value including worst case tolerances (30% drop can be considered for method 1)  
f: Minimum switching frequency (1.6 MHz)  
VOUT: Output voltage  
(2)  
Method 2:  
A more conservative and recommended approach is to choose an inductor that has saturation current rating  
greater than the max current limit of 1150 mA.  
A 2.2 µH inductor with a saturation current rating of at least 1150 mA is recommended for most applications. The  
inductor’s resistance should be less than 0.3Ω for good efficiency. Table 1 lists suggested inductors and  
suppliers. For low-cost applications, an unshielded bobbin inductor could be considered. For noise critical  
applications, a toroidal or shielded bobbin inductor should be used. A good practice is to lay out the board with  
overlapping footprints of both types for design flexibility. This allows substitution of a low-noise shielded inductor,  
in the event that noise from low-cost bobbin models is unacceptable.  
INPUT CAPACITOR SELECTION  
A ceramic input capacitor of 10 µF, 6.3V is sufficient for most applications. Place the input capacitor as close as  
possible to the VIN pin of the device. A larger value may be used for improved input voltage filtering. Use X7R or  
X5R types, do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting  
case sizes like 0805 and 0603. The input filter capacitor supplies current to the PFET switch of the converter in  
the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor’s  
low ESR provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select a  
capacitor with sufficient ripple current rating. The input current ripple can be calculated as:  
«
r2  
∆
∆
≈
≈ VOUT  
VOUT  
VIN  
∆
IRMS = IOUTMAX  
1 -  
+
*
*
∆
VIN  
12  
«
VOUT  
(VIN - VOUT  
)
*
r =  
VIN  
L
f
IOUTMAX  
*
*
*
(3)  
The worst case is when VIN = 2 * VOUT  
Table 7. Suggested Inductors and their Suppliers  
Model  
Vendor  
Coilcraft  
Coilcraft  
Panasonic  
Sumida  
Dimensions LxWxH (mm)  
3.3 x 3.3 x 1.4  
D.C.R (Max)  
200 mΩ  
150 mΩ  
53 mΩ  
DO3314-222MX  
LPO3310-222MX  
ELL5GM2R2N  
CDRH2D14-2R2  
3.3 x 3.3 x 1.0  
5.2 x 5.2 x 1.5  
3.2 x 3.2 x 1.55  
94 mΩ  
OUTPUT CAPACITOR SELECTION  
Use a 10 µF, 6.3V ceramic capacitor. Use X7R or X5R types, do not use Y5V. DC bias characteristics of ceramic  
capacitors must be considered when selecting case sizes like 0805 and 0603. DC bias characteristics vary from  
manufacturer to manufacturer and dc bias curves should be requested from them as part of the capacitor  
selection process. The LP3970 has been evaluated with 10 µF, 6.3V, 0805 capacitor.  
The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output  
voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with  
sufficient capacitance and sufficiently low ESR to perform these functions.  
The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its  
ESR and can be calculated as:  
28  
Submit Documentation Feedback  
Copyright © 2005–2013, Texas Instruments Incorporated  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
www.ti.com  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
Voltage peak-to-peak ripple due to capacitance can be expressed as follows  
IRIPPLE  
VPP-C  
=
4 f C  
* *  
(4)  
(5)  
Voltage peak-to-peak ripple due to ESR can be expressed as follows  
VPP-ESR = (2 * IRIPPLE) * RESR  
Because these two components are out of phase the rms value can be used to get an approximate value of  
peak-to-peak ripple.  
Voltage peak-to-peak ripple, root mean squared can be expressed as follows  
2
VPP-C2 + VPP-ESR  
VPP-RMS  
=
(6)  
Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series  
resistance of the output capacitor (RESR).  
The RESR is frequency dependent (as well as temperature dependent); make sure the value used for  
calculations is at the switching frequency of the part.  
Table 8. Suggested Capacitor and their Suppliers  
Model  
Type  
Vendor  
Voltage  
Case Size  
Inch (mm)  
22 µF for COUT  
GRM21BR60J226K  
C2012X5R0J226K  
JMK212BJ226K  
Ceramic, X5R  
Ceramic, X5R  
Ceramic, X5R  
Murata  
TDK  
6.3V  
6.3V  
6.3V  
0805 (2012)  
0805 (2012)  
0805 (2012)  
Taiyo-Yuden  
10 µF for CIN or COUT  
GRM21BR60J106K  
JMK212BJ106K  
Ceramic, X5R  
Ceramic, X5R  
Ceramic, X5R  
Murata  
Taiyo-Yuden  
TDK  
6.3V  
6.3V  
6.3V  
0805 (2012)  
0805 (2012)  
0805 (2012)  
C2012X5R0J106K  
Board Layout Considerations  
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance  
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss  
in the traces. These can send erroneous signals to the DC-DC converter IC, resulting in poor regulation or  
instability.  
Good layout for the converters can be implemented by following a few simple design rules.  
1. Place the converters, inductor and filter capacitors close together and make the traces short. The traces  
between these components carry relatively high switching currents and act as antennas. Following this rule  
reduces radiated noise. Special care must be given to place the input filter capacitor very close to the VIN  
and GND pin.  
2. Arrange the components so that the switching current loops curl in the same direction. During the first half of  
each cycle, current flows from the input filter capacitor through the converter and inductor to the output filter  
capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled  
up from ground through the converter by the inductor to the output filter capacitor and then back through  
ground forming a second current loop. Routing these loops so the current curls in the same direction  
prevents magnetic field reversal between the two half-cycles and reduces radiated noise.  
3. Connect the ground pins of the converter and filter capacitors together using generous component-side  
copper fill as a pseudo-ground plane. Then, connect this to the ground-plane (if one is used) with several  
vias. This reduces ground-plane noise by preventing the switching currents from circulating through the  
ground plane. It also reduces ground bounce at the converter by giving it a low-impedance ground  
connection.  
4. Use wide traces between the power components and for power connections to the DC-DC converter circuit.  
This reduces voltage errors caused by resistive losses across the traces.  
Copyright © 2005–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
29  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
www.ti.com  
5. Route noise sensitive traces, such as the voltage feedback path, away from noisy traces between the power  
components. The voltage feedback trace must remain close to the converter circuit and should be direct but  
should be routed opposite to noisy components. This reduces EMI radiated onto the DC-DC converter’s own  
voltage feedback trace. A good approach is to route the feedback trace on another layer and to have a  
ground plane between the top layer and layer on which the feedback trace is routed. In the same manner for  
the adjustable part it is desired to have the feedback dividers on the bottom layer.  
6. Place noise sensitive circuitry, such as radio RF blocks, away from the DC-DC converter, CMOS digital  
blocks and other noisy circuitry. Interference with noise-sensitive circuitry in the system can be reduced  
through distance.  
Application Note 1 nVDD FLT  
When I2C commands are used to enable LDO 1 to 6 or Buck1, 2 the nVDD_FLT output momentarily glitches,  
see plot below.  
V
BUCK1  
OUT  
nVDD_FLT  
TIME (1.00 ms/DIV)  
Figure 28.  
The nVDD_FLT signal can be deglitched using the following circuit. This will deglitch nVDD_FLT and allow the  
system designer to use I2C commands to turn the supplies on or off.  
100 kW  
nVDD_FLT  
10 mF  
LP3970  
Application Note 2 Back-Up Battery Switch  
When operating from a backup battery the battery selection switch may latch up if the backup battery voltage has  
discharged below 2.0V. The circuit shown below will prevent back up battery from latching up under these  
conditions. D1 and D2 are silicon SMT diodes and the 10 kΩ resistor can be adjusted for different capacity BU  
batteries however care should be taken not to exceed manufactures specification.  
30  
Submit Documentation Feedback  
Copyright © 2005–2013, Texas Instruments Incorporated  
Product Folder Links: LP3970  
OBSOLETE  
LP3970  
www.ti.com  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
MAIN BATTERY  
D1  
D2  
LP3970  
10 kW  
BACK UP  
BATTERY BATTERY  
Application Note 3 VCC IO  
The PXA27x power requirements document states VCC_IO shall be ±200 mV of VCC_RTC when VCC_IO is active.  
The current LP3970 datasheet specification has VCC_RTC = 2.8V and VCC_IO = to 2.8V. The LP3970 does not  
incorporate circuitry for the RTC_LDO to tract VCC_IO. The LP3970 can accommodate VCC_IO voltages of no  
more then 3.0V. If a higher IO voltage is required an external low dropout regulator such as the LP3871 can be  
used to power VCC_RTC with the output voltage set to VCC_IO.  
Copyright © 2005–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
31  
Product Folder Links: LP3970  
 
OBSOLETE  
LP3970  
SNVS348G –JANUARY 2005–REVISED APRIL 2013  
www.ti.com  
REVISION HISTORY  
Changes from Revision F (April 2013) to Revision G  
Page  
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 31  
32  
Submit Documentation Feedback  
Copyright © 2005–2013, Texas Instruments Incorporated  
Product Folder Links: LP3970  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest  
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and  
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale  
supplied at the time of order acknowledgment.  
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary  
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily  
performed.  
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide  
adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or  
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information  
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or  
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the  
third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration  
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered  
documentation. Information of third parties may be subject to additional restrictions.  
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service  
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.  
TI is not responsible or liable for any such statements.  
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements  
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support  
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which  
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause  
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use  
of any TI components in safety-critical applications.  
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to  
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and  
requirements. Nonetheless, such components are subject to these terms.  
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties  
have executed a special agreement specifically governing such use.  
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in  
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components  
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and  
regulatory requirements in connection with such use.  
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of  
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.  
Products  
Applications  
Audio  
www.ti.com/audio  
amplifier.ti.com  
dataconverter.ti.com  
www.dlp.com  
Automotive and Transportation www.ti.com/automotive  
Communications and Telecom www.ti.com/communications  
Amplifiers  
Data Converters  
DLP® Products  
DSP  
Computers and Peripherals  
Consumer Electronics  
Energy and Lighting  
Industrial  
www.ti.com/computers  
www.ti.com/consumer-apps  
www.ti.com/energy  
dsp.ti.com  
Clocks and Timers  
Interface  
www.ti.com/clocks  
interface.ti.com  
logic.ti.com  
www.ti.com/industrial  
www.ti.com/medical  
Medical  
Logic  
Security  
www.ti.com/security  
Power Mgmt  
Microcontrollers  
RFID  
power.ti.com  
Space, Avionics and Defense  
Video and Imaging  
www.ti.com/space-avionics-defense  
www.ti.com/video  
microcontroller.ti.com  
www.ti-rfid.com  
www.ti.com/omap  
OMAP Applications Processors  
Wireless Connectivity  
TI E2E Community  
e2e.ti.com  
www.ti.com/wirelessconnectivity  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2013, Texas Instruments Incorporated  

相关型号：

SI9130DB

 5- and 3.3-V Step-Down Synchronous Converters

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135_11

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9136_11

 Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明