LP3995ILD-3.0/NOPB [TI]
Micropower 150-mA CMOS Voltage Regulator With Active Shutdown;
| 型号： | LP3995ILD-3.0/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Micropower 150-mA CMOS Voltage Regulator With Active Shutdown 输出元件 调节器 |
| 文件： | 总23页 (文件大小：1647K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP3995
www.ti.com
SNVS179E –FEBRUARY 2003–REVISED MARCH 2013
LP3995 Micropower 150mA CMOS Voltage Regulator with Active Shutdown
Check for Samples: LP3995
1
FEATURES
DESCRIPTION
The LP3995 linear regulator is designed to meet the
requirements of portable battery-powered applications
and will provide an accurate output voltage with low
noise and low quiescent current. Ideally suited for
powering RF/Analog devices, this device will also be
used to meet more general circuit needs in which a
fast turn-off is essential.
2
•
5 pin DSBGA Package
•
•
•
•
•
•
•
6 pin WSON Package
Stable With Ceramic Capacitor
Logic Controlled Enable
Fast Turn-On
Active Disable for Fast Turn-Off
Thermal-overload and Short-Circuit Protection
For battery powered applications the low dropout and
low ground current provided by the device allows the
lifetime of the battery to be maximized. The
Enable(/Disable) control allows the system to further
extend the battery lifetime by reducing the power
consumption to virtually zero.
−40 to +125°C Junction Temperature Range for
Operation
APPLICATIONS
The Enable(/Disable) function on the device
incorporates an active discharge circuit on the output
for faster device shutdown. Where the fast turn-off is
not required the LP3999 linear regulator is
recommended.
•
•
•
•
•
GSM Portable Phones
CDMA Cellular Handsets
Wideband CDMA Cellular Handsets
Bluetooth Devices
Portable Information Appliances
The LP3995 also features internal protection against
short-circuit
conditions.
currents
and
over-temperature
KEY SPECIFICATIONS
•
•
•
•
Input Range: 2.5V to 6.0V
The LP3995 is designed to be stable with small 1.0
µF ceramic capacitors. The small outline of the
LP3995 DSBGA package with the required ceramic
capacitors can realize a system application within
minimal board area.
Accurate Output Voltage: ±75mV / 2%
Typical Dropout with 150 mA Load: 60mV
Virtually Zero Quiescent Current when
Disabled
Performance is specified for a −40°C to +125°C
temperature range.
•
•
•
•
•
Low Output Voltage Noise
Stable with an Output Capacitor of 1µF
Output Current: 150mA
The device is available in DSBGA package and
WSON package. For other package options contact
your local TI sales office.
Fast Turn-on: 30µs (Typ.)
Fast Turn-off: 175µs (Typ.)
The device is available in fixed output voltages in the
ranges 1.5V to 3.3V. For availability, please contact
your local TI sales office.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
LP3995
SNVS179E –FEBRUARY 2003–REVISED MARCH 2013
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Typical Application Circuit
LP3995
1
VIN
Input
(C3)
6
VOUT
CIN
1.0 uF
(C1)
COUT
1.0 uF
Load
3
4
VEN
CBYPASS
Enable
(A1)
(A3)
GND
CBP
10 nF
2
(B2)
Block Diagram
VOUT
VIN
Vref
+
-
VEN
R1
R2
Fast Turn-
on
Turn-off
CBP
Over Current
Thermal Protn.
GND
PIN DESCRIPTION (5 PIN DSBGA and 6 PIN WSON)
Pin No.
Symbol
Name and Function
DSBGA
WSON
A1
3
VEN
Enable Input; Disables the Regulator when ≤ 0.4V.
Enables the regulator when ≥ 0.9V
B2
C1
C3
A3
2
6
1
4
GND
VOUT
Common Ground
Voltage output. Connect this output to the load circuit.
Voltage Supply Input
VIN
CBYPASS
Bypass Capacitor connection.
Connect a 0.01 µF capacitor for noise reduction.
5
N/C
No internal connection. There should not be any board connection to this pin.
Pad
GND
Ground connection.
Connect to ground plane for best thermal conduction.
2
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CONNECTION DIAGRAMS
CBYPASS
A3
VIN
C3
VIN
C3
CBYPASS
A3
A1
B2
C1
C1
B2
A1
VEN
GND
GND
VEN
V
OUT
V
OUT
Top View
Bottom View
5 Bump DSBGA Package
See Package Number YZR0005
V
IN
1
6 V
OUT
V
OUT
6
1 V
IN
Device
Code
GND 2
5 N/C
N/C 5
2 GND
V
3
4 C
C
4
3 V
EN
EN
BYPASS
BYPASS
PAD
PAD
GND
GND
Top View
Bottom View
6 Pin WSON Package (SOT-23 Footprint)
See Package Number NGD0006A
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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(1) (2)(3)
Absolute Maximum Ratings
Input Voltage (VIN
)
−0.3 to 6.5V
Output Voltage
−0.3 to (VIN + 0.3V)
to 6.5V (max)
Enable Input Voltage
Junction Temperature
Lead/Pad Temperature(4)
DSBGA
−0.3 to 6.5V
150°C
260°C
235°C
WSON
Storage Temperature
Continuous Power Dissipation(5)
−65 to +150°C
Internally Limited
(6)
ESD
Human Body Model
Machine Model
2 kV
200V
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits
and associated test conditions, see the Electrical Characteristics tables.
(2) All voltages are with respect to the potential at the GND pin.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for
availability and specifications.
(4) For information regarding the DSBGA package, see the TI AN-1112 Application Report (SNVA009). For information regarding the
WSON package, see the TI AN-1187 Application Report (SNOA401).
(5) In applications where high power dissipation and/or poor thermal resistance is present, the maximum ambient temperature may have to
be derated. Maximum ambient temperature (TA(max)) is dependant on the maximum operating junction temperature (TJ(max-op)), the
maximum power dissipation (PD(max)), and the junction to ambient thermal resistance in the application (θJA). This relationship is given
by:
TA(max) = TJ(max-op) − (PD(max) × θJA
)
(6) The human body model is an 100 pF discharge through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor
discharged directly into each pin.
(1)
Operating Ratings
Input Voltage (VIN
)
2.5 to 6.0V
0 to 6.0V
Enable Input Voltage
Junction Temperature
Ambient Temperature Range(2)
−40 to +125°C
-40 to 85°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits
and associated test conditions, see the Electrical Characteristics tables.
(2) In applications where high power dissipation and/or poor thermal resistance is present, the maximum ambient temperature may have to
be derated. Maximum ambient temperature (TA(max)) is dependant on the maximum operating junction temperature (TJ(max-op)), the
maximum power dissipation (PD(max)), and the junction to ambient thermal resistance in the application (θJA). This relationship is given
by:
TA(max) = TJ(max-op) − (PD(max) × θJA
)
Thermal Properties(1)
Junction to Ambient Thermal Resistance
θJA (WSON pkg.)
88°C/W
θJA (DSBGA pkg.)
255°C/W
(1) Junction to ambient thermal resistance is highly dependant on the application and board layout. In applications where high thermal
dissipation is possible, special care must be paid to thermal issues in the board design.
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Electrical Characteristics
Unless otherwise noted, VEN = 1.5, VIN = VOUT + 1.0V, CIN = 1 µF, IOUT = 1 mA, COUT = 1 µF, cBP = 0.01 µF. Typical values
and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the full temperature
(1) (2)
range for operation, −40 to +125°C.
Limit
Symbol
Parameter
Conditions
Typical
Units
Min
Max
VIN
Input Voltage
2.5
6.0
V
DEVICE OUTPUT: 1.5 ≤ VOUT < 1.8V
ΔVOUT
Output Voltage Tolerance
Line Regulation Error
IOUT = 1 mA
-50
50
mV
-75
75
VIN = (VOUT(NOM)+1.0V) to 6.0V,
IOUT = 1 mA
-3.5
3.5
75
mV/V
DSBGA
Load Regulation Error
IOUT = 1 mA to 150 mA
µV/mA
10
70
WSON
Load Regulation Error
Power Supply Rejection Ratio(3)
IOUT = 1 mA to 150 mA
µV/mA
dB
125
PSRR
f = 1 kHz, IOUT = 1 mA
f = 10 kHz, IOUT = 1 mA
55
53
DEVICE OUTPUT: 1.8 ≤ VOUT < 2.5V
ΔVOUT
Output Voltage Tolerance
IOUT = 1 mA
-50
50
mV
−75
75
DSBGA
Line Regulation Error
VIN = (VOUT(NOM)+1.0V) to 6.0V,
IOUT = 1 mA
−2.5
−3.5
2.5
3.5
75
mV/V
WSON
Line Regulation Error
VIN = (VOUT(NOM)+1.0V) to 6.0V,
IOUT = 1 mA
mV/V
DSBGA
Load Regulation Error
IOUT = 1 mA to 150 mA
µV/mA
10
80
WSON
Load Regulation Error
Power Supply Rejection Ratio(3)
IOUT = 1 mA to 150 mA
µV/mA
dB
125
PSRR
f = 1 kHz, IOUT = 1 mA
f = 10 kHz, IOUT = 1 mA
55
50
DEVICE OUTPUT: 2.5 ≤ VOUT ≤ 3.3V
ΔVOUT
Output Voltage Tolerance
IOUT = 1 mA
-2
2
% of
VOUT(NOM)
−3
3
Line Regulation Error
VIN = (VOUT(NOM)+1.0V) to 6.0V,
IOUT = 1 mA
−0.1
0.1
%/V
DSBGA
Load Regulation Error
IOUT = 1 mA to 150 mA
0.0004
0.002
0.002
0.005
%/mA
%/mA
WSON
Load Regulation Error
IOUT = 1 mA to 150 mA
Dropout Voltage
IOUT = 1 mA
0.4
60
60
50
2
mV
dB
IOUT = 150 mA
100
PSRR
Power Supply Rejection Ratio(3)
f = 1 kHz, IOUT = 1 mA
f = 10 kHz, IOUT = 1 mA
FULL VOUT RANGE
ILOAD Load Current
(3)
See (4) and
0
µA
(1) All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production at TJ = 25°C or
correlated using Statistical Quality Control methods. Operation over the temperature specification is guaranteed by correlating the
electrical characteristics to process and temperature variations and applying statistical process control.
(2) VOUT(NOM) is the stated output voltage option for the device.
(3) This electrical specification is guaranteed by design.
(4) The device maintains a stable, regulated output voltage without load.
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Electrical Characteristics (continued)
Unless otherwise noted, VEN = 1.5, VIN = VOUT + 1.0V, CIN = 1 µF, IOUT = 1 mA, COUT = 1 µF, cBP = 0.01 µF. Typical values
and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the full temperature
(1) (2)
range for operation, −40 to +125°C.
Limit
Symbol
Parameter
Quiescent Current
Conditions
Typical
Units
Min
Max
150
200
1.5
IQ
VEN = 1.5V, IOUT = 0 mA
VEN = 1.5V, IOUT = 150 mA
VEN = 0.4V
85
140
µA
0.003
450
ISC
EN
Short Circuit Current Limit
Output Noise Voltage(3)
mA
µVrms
°C
BW = 10 Hz to 100 kHz,
VIN = 4.2V, IOUT = 1mA
25
TSHUTDOWN
Thermal Shutdown
Temperature
Hysteresis
160
20
ENABLE CONTROL CHARACTERISTICS
IEN
Maximum Input Current at VEN
Input
VEN = 0.0V and VIN = 6.0V
0.001
µA
VIL
VIH
Low Input Threshold
High Input Threshold
0.4
V
V
0.9
TIMING CHARACTERISTICS
(3)
(3)
(5)
TON
Turn On Time
Turn Off Time
To 95% Level
30
µs
µs
(6)
TOFF
To 5% Level
175
(5) Time from VEN = 0.9V to VOUT = 95% (VOUT(NOM)
)
(6) Time from VEN = 0.4V to VOUT = 5% (VOUT(NOM)
)
Recommended Output Capacitor
Limit
Symbol
COUT
Parameter
Output Capacitor
Conditions
VALUE
Units
Min
0.70
5
Max
(1)
Capacitance
1.0
µF
ESR
500
mΩ
(1) The capacitor tolerance should be ±30% or better over the temperature range. The recommended capacitor type is X7R however,
dependant on the application X5R, Y5V, and Z5U can also be used.
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SNVS179E –FEBRUARY 2003–REVISED MARCH 2013
INPUT TEST SIGNALS
30 us
30 us
600 mV
VIN = VOUT(NOM) + 1V
600 us
4.6 ms
Figure 1. Line Transient Response Input Test Signal
50 mV
VIN = VOUT(NOM) + 1V
Figure 2. PSRR Input Test Signal
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified, CIN = COUT = 1.0 µF Ceramic, VIN = VOUT + 1.0V, TA = 25°C, Enable pin is tied to VIN.
Output Voltage Change vs Temperature
Ground Current vs Load Current (1.8V VOUT)
Figure 3.
Figure 4.
Ground Current vs Load Current (2.8V VOUT
)
Ground Current vs VIN @ 25°C
Figure 5.
Figure 6.
Ground Current vs VIN @ 125°C
Dropout vs Load Current
Figure 7.
Figure 8.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, CIN = COUT = 1.0 µF Ceramic, VIN = VOUT + 1.0V, TA = 25°C, Enable pin is tied to VIN.
Short Circuit Current
Line Transient Response (VOUT = 2.8V)
Figure 9.
Figure 10.
Ripple Rejection (VOUT = 1.8V)
Ripple Rejection (VOUT = 2.8V)
Figure 11.
Figure 12.
Enable Start-Up Time (VOUT = 2.8V)
Enable Start-Up Time (VOUT = 2.8V)
Figure 13.
Figure 14.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, CIN = COUT = 1.0 µF Ceramic, VIN = VOUT + 1.0V, TA = 25°C, Enable pin is tied to VIN.
Enable Start-Up Time (VOUT = 1.8V)
Enable Start-Up Time (VOUT = 1.8V)
Figure 15.
Figure 16.
Turn-Off Time (VOUT = 2.8V)
Turn-Off Time (VOUT = 1.8V)
Figure 17.
Figure 18.
Load Transient Response (VOUT = 2.8V)
Load Transient Response (VOUT = 1.8V)
Figure 19.
Figure 20.
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APPLICATION HINTS
POWER DISSIPATION AND DEVICE OPERATION
The permissible power dissipation for any package is a measure of the capability of the device to pass heat from
the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus the power
dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces
between the die and ambient air.
Thermal Resistance Figure
Re-stating the equation given in note 5 of the Absolute Maximum Ratings section:
TA(max) = TJ(max-op) − (PD(max) × θJA)
the allowable power dissipation for the device in a given package can be calculated:
(1)
With a θJA = 255°C/W, the device in the DSBGA package returns a value of 392 mW with a maximum junction
temperature of 125°C.
With a θJA = 88°C/W, the device in the WSON package returns a value of 1.136 mW with a maximum junction
temperature of 125°C.
The actual power dissipation across the device can be represented by the following equation:
PD = (VIN − VOUT) x IOUT
(2)
This establishes the relationship between the power dissipation allowed due to thermal consideration, the voltage
drop across the device, and the continuous current capability of the device. These two equations should be used
to determine the optimum operating conditions for the device in the application.
EXTERNAL CAPACITORS
In common with most regulators, the LP3995 requires external capacitors to ensure stable operation. The
LP3995 is specifically designed for portable applications requiring minimum board space and smallest
components. These capacitors must be correctly selected for good performance.
INPUT CAPACITOR
An input capacitor is required for stability. It is recommended that a 1.0 µF capacitor be connected between the
LP3995 input pin and ground (this capacitance value may be increased without limit).
This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean
analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-
impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input,
it must be guaranteed by the manufacturer to have a surge current rating sufficient for the application.
There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and
temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain
≅ 1.0 µF over the entire operating temperature range.
OUTPUT CAPACITOR
The LP3995 is designed specifically to work with very small ceramic output capacitors. A ceramic capacitor
(dielectric types Z5U, Y5V or X7R) in the 1.0 [to 10 µF] range, and with ESR between 5 mΩ to 500 mΩ, is
suitable in the LP3995 application circuit.
For this device the output capacitor should be connected between the VOUT pin and ground.
It may also be possible to use tantalum or film capacitors at the device output, VOUT, but these are not as
attractive for reasons of size and cost (see CAPACITOR CHARACTERISTICS).
The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR
value that is within the range 5 mΩ to 500 mΩ for stability.
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NO-LOAD STABILITY
The LP3995 will remain stable and in regulation with no external load. This is an important consideration in some
circuits, for example CMOS RAM keep-alive applications.
CAPACITOR CHARACTERISTICS
The LP3995 is designed to work with ceramic capacitors on the output to take advantage of the benefits they
offer. For capacitance values in the range of 1 µF to 4.7 µF, ceramic capacitors are the smallest, least expensive
and have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a
typical 1 µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for
stability for the LP3995.
The temperature performance of ceramic capacitors varies by type. Most large value ceramic capacitors
(≥ 2.2 µF) are manufactured with Z5U or Y5V temperature characteristics, which results in the capacitance
dropping by more than 50% as the temperature goes from 25°C to 85°C.
A better choice for temperature coefficient in a ceramic capacitor is X7R. This type of capacitor is the most stable
and holds the capacitance within ±15% over the temperature range. Tantalum capacitors are less desirable than
ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance
and voltage ratings in the 1 µF to 4.7 µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic
capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about
2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed.
NOISE BYPASS CAPACITOR
A bypass capacitor should be connected between the CBP pin and ground to significantly reduce the noise at the
regulator output. This device pin connects directly to a high impedance node within the bandgap reference
circuitry. Any significant loading on this node will cause a change on the regulated output voltage. For this
reason, DC leakage current through this pin must be kept as low as possible for best output voltage accuracy.
The use of a 0.01 µF bypass capacitor is strongly recommended to prevent overshoot on the output during start-
up.
The types of capacitors best suited for the noise bypass capacitor are ceramic and film. High quality ceramic
capacitors with NPO or COG dielectric typically have very low leakage. Polypropolene and polycarbonate film
capacitors are available in small surface-mount packages and typically have extremely low leakage current.
Unlike many other LDOs, the addition of a noise reduction capacitor does not effect the transient response of the
device.
ENABLE OPERATION
The LP3995 may be switched ON or OFF by a logic input at the ENABLE pin, VEN. A high voltage at this pin will
turn the device on. When the enable pin is low, the regulator output is off and the device typically consumes
3 nA. If the application does not require the shutdown feature, the VEN pin should be tied to VIN to keep the
regulator output permanently on. To ensure proper operation, the signal source used to drive the VEN input must
be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical
Characteristics section under VIL and VIH.
FAST TURN OFF AND ON
The controlled switch-off feature of the device provides a fast turn off by discharging the output capacitor via an
internal FET device. This discharge is current limited by the RDSon of this switch. Fast turn-on is guaranteed by
control circuitry within the reference block allowing a very fast ramp of the output voltage to reach the target
voltage.
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DSBGA MOUNTING
The DSBGA package requires specific mounting techniques that are detailed in TI's AN-1112 Application Report
(SNVA009). Referring to the section Surface Mount Assembly Considerations, it should be noted that the pad
style which must be used with the 5 pin package is NSMD (non-solder mask defined) type.
For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the
DSBGA device.
DSBGA LIGHT SENSITIVITY
Exposing the DSBGA device to direct sunlight will cause incorrect operation of the device. Light sources such as
halogen lamps can affect electrical performance if they are situated in proximity to the device.
Light with wavelengths in the red and infra-red part of the spectrum have the most detrimental effect thus the
fluorescent lighting used inside most buildings has very little effect on performance. Tests carried out on a
DSBGA test board showed a negligible effect on the regulated output voltage when brought within 1 cm of a
fluorescent lamp. A deviation of less than 0.1% from nominal output voltage was observed.
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REVISION HISTORY
Changes from Revision D (March 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 13
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PACKAGE OPTION ADDENDUM
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7-Oct-2013
PACKAGING INFORMATION
Orderable Device
LP3995ILD-1.5/NOPB
LP3995ILD-1.8/NOPB
LP3995ILD-2.8/NOPB
LP3995ILD-3.0/NOPB
LP3995ILDX-2.8/NOPB
LP3995ITL-1.5/NOPB
LP3995ITL-1.6/NOPB
LP3995ITL-1.8/NOPB
LP3995ITL-1.9/NOPB
LP3995ITL-2.1/NOPB
LP3995ITL-2.5/NOPB
LP3995ITL-2.7/NOPB
LP3995ITL-2.8/NOPB
LP3995ITL-2.85/NOPB
LP3995ITL-3.0/NOPB
LP3995ITLX-1.5/NOPB
LP3995ITLX-1.6/NOPB
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
WSON
WSON
WSON
WSON
WSON
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
NGD
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
1000
Green (RoHS
& no Sb/Br)
CU SN
CU SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
L020B
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NGD
NGD
NGD
NGD
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
1000
1000
1000
4500
250
Green (RoHS
& no Sb/Br)
L022B
Green (RoHS
& no Sb/Br)
CU SN
L026B
Green (RoHS
& no Sb/Br)
CU SN
L030B
Green (RoHS
& no Sb/Br)
CU SN
L026B
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
9
9
9
9
9
9
9
9
9
9
9
9
250
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
250
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
3000
3000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
LP3995ITLX-1.8/NOPB
LP3995ITLX-1.9/NOPB
LP3995ITLX-2.1/NOPB
LP3995ITLX-2.5/NOPB
LP3995ITLX-2.7/NOPB
LP3995ITLX-2.8/NOPB
LP3995ITLX-2.85/NOPB
LP3995ITLX-3.0/NOPB
ACTIVE
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
YZR
5
5
5
5
5
5
5
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
9
9
9
9
9
9
9
9
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
YZR
YZR
YZR
YZR
YZR
YZR
YZR
3000
3000
3000
3000
3000
3000
3000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
-40 to 125
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2013
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3995ILD-1.5/NOPB
LP3995ILD-1.8/NOPB
LP3995ILD-2.8/NOPB
LP3995ILD-3.0/NOPB
LP3995ILDX-2.8/NOPB
LP3995ITL-1.5/NOPB
LP3995ITL-1.6/NOPB
LP3995ITL-1.8/NOPB
LP3995ITL-1.9/NOPB
LP3995ITL-2.1/NOPB
LP3995ITL-2.5/NOPB
LP3995ITL-2.7/NOPB
LP3995ITL-2.8/NOPB
WSON
WSON
WSON
WSON
WSON
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
NGD
NGD
NGD
NGD
NGD
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
1000
1000
1000
1000
4500
250
178.0
178.0
178.0
178.0
330.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
12.4
12.4
12.4
12.4
12.4
8.4
3.6
3.6
3.2
3.2
1.0
1.0
8.0
8.0
8.0
8.0
8.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
12.0
12.0
12.0
12.0
12.0
8.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
3.6
3.2
1.0
3.6
3.2
1.0
3.6
3.2
1.0
1.09
1.09
1.09
1.09
1.09
1.09
1.09
1.09
1.09
1.09
1.09
1.09
1.09
1.55
1.55
1.55
1.55
1.55
1.55
1.55
1.55
1.55
1.55
1.55
1.55
1.55
0.76
0.76
0.76
0.76
0.76
0.76
0.76
0.76
0.76
0.76
0.76
0.76
0.76
250
8.4
8.0
250
8.4
8.0
250
8.4
8.0
250
8.4
8.0
250
8.4
8.0
250
8.4
8.0
250
8.4
8.0
LP3995ITL-2.85/NOPB DSBGA
LP3995ITL-3.0/NOPB DSBGA
250
8.4
8.0
250
8.4
8.0
LP3995ITLX-1.5/NOPB DSBGA
LP3995ITLX-1.6/NOPB DSBGA
LP3995ITLX-1.8/NOPB DSBGA
3000
3000
3000
8.4
8.0
8.4
8.0
8.4
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3995ITLX-1.9/NOPB DSBGA
LP3995ITLX-2.1/NOPB DSBGA
LP3995ITLX-2.5/NOPB DSBGA
LP3995ITLX-2.7/NOPB DSBGA
LP3995ITLX-2.8/NOPB DSBGA
LP3995ITLX-2.85/NOPB DSBGA
LP3995ITLX-3.0/NOPB DSBGA
YZR
YZR
YZR
YZR
YZR
YZR
YZR
5
5
5
5
5
5
5
3000
3000
3000
3000
3000
3000
3000
178.0
178.0
178.0
178.0
178.0
178.0
178.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
1.09
1.09
1.09
1.09
1.09
1.09
1.09
1.55
1.55
1.55
1.55
1.55
1.55
1.55
0.76
0.76
0.76
0.76
0.76
0.76
0.76
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP3995ILD-1.5/NOPB
LP3995ILD-1.8/NOPB
LP3995ILD-2.8/NOPB
LP3995ILD-3.0/NOPB
LP3995ILDX-2.8/NOPB
LP3995ITL-1.5/NOPB
LP3995ITL-1.6/NOPB
LP3995ITL-1.8/NOPB
LP3995ITL-1.9/NOPB
LP3995ITL-2.1/NOPB
WSON
WSON
WSON
WSON
WSON
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
NGD
NGD
NGD
NGD
NGD
YZR
YZR
YZR
YZR
YZR
6
6
6
6
6
5
5
5
5
5
1000
1000
1000
1000
4500
250
213.0
213.0
213.0
213.0
367.0
210.0
210.0
210.0
210.0
210.0
191.0
191.0
191.0
191.0
367.0
185.0
185.0
185.0
185.0
185.0
55.0
55.0
55.0
55.0
35.0
35.0
35.0
35.0
35.0
35.0
250
250
250
250
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP3995ITL-2.5/NOPB
LP3995ITL-2.7/NOPB
LP3995ITL-2.8/NOPB
LP3995ITL-2.85/NOPB
LP3995ITL-3.0/NOPB
LP3995ITLX-1.5/NOPB
LP3995ITLX-1.6/NOPB
LP3995ITLX-1.8/NOPB
LP3995ITLX-1.9/NOPB
LP3995ITLX-2.1/NOPB
LP3995ITLX-2.5/NOPB
LP3995ITLX-2.7/NOPB
LP3995ITLX-2.8/NOPB
LP3995ITLX-2.85/NOPB
LP3995ITLX-3.0/NOPB
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
250
250
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
250
250
250
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
Pack Materials-Page 3
MECHANICAL DATA
NGD0006A
www.ti.com
MECHANICAL DATA
YZR0005xxx
D
0.600±0.075
E
TLA05XXX (Rev C)
D: Max = 1.502 mm, Min =1.441 mm
E: Max = 1.045 mm, Min =0.984 mm
4215043/A
12/12
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
www.ti.com
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