LP3996SDX-3033/NOPB [TI]
LP3996 Dual Linear Regulator with 300 mA and 150 mA Outputs and Power-On-Reset;
| 型号： | LP3996SDX-3033/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LP3996 Dual Linear Regulator with 300 mA and 150 mA Outputs and Power-On-Reset 输出元件 调节器 |
| 文件： | 总22页 (文件大小：1204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP3996
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SNVS360D –NOVEMBER 2006–REVISED OCTOBER 2013
LP3996 Dual Linear Regulator with 300 mA and 150 mA Outputs and Power-On-Reset
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1
FEATURES
APPLICATIONS
2
•
2 LDO Outputs with Independent Enable
•
•
•
Cellular Handsets
PDAs
•
1.5% Accuracy at Room Temperature, 3% Over
Temperature
Wireless Network Adaptors
•
Power-On-Reset Function with Adjustable
Delay
DESCRIPTION
The LP3996 is a dual low dropout regulator with
power-on-reset circuit. The first regulator can source
150 mA, while the second is capable of sourcing 300
mA and has a power-on-reset function included.
•
•
Thermal Shutdown Protection
Stable with Ceramic Capacitors
KEY SPECIFICATIONS
The LP3996 provides 1.5% accuracy requiring an
ultra low quiescent current of 35 µA. Separate enable
pins allow each output of the LP3996 to be shut
down, drawing virtually zero current.
•
•
•
•
•
Input Voltage Range 2.0V to 6.0V
Low Dropout Voltage 210 mV at 300 mA
Ultra-Low IQ (Enabled) 35 µA
Virtually Zero IQ (Disabled) <10 nA
The LP3996 is designed to be stable with small
footprint ceramic capacitors down to 1 µF. An
external capacitor may be used to set the POR delay
time as required.
Package Available in Lead-Free Option
10-pin 3 mm x 3 mm
The LP3996 is available in fixed output voltages and
comes in a 10-pin, 3 mm x 3 mm package.
Typical Application Circuit
470 k:
LP3996
V
V
V
V
V
IN
OUT1
OUT1
IN
EN1
EN2
EN1
EN2
V
OUT2
POR
OUT2
POR
C
SET
BYP
1 PF
10 nF
1 PF
1 PF
GND
Sets delay
for POR
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LP3996
SNVS360D –NOVEMBER 2006–REVISED OCTOBER 2013
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Functional Block Diagram
LDO1
V
V
V
OUT1
IN
EN1
EN2
LDO2
OUT2
POR
POR
C
BYP
1 PA
+
-
V
REF
GND
SET
Pin Functions
Pin No
Symbol
VIN
Name and Function
1
2
Voltage Supply Input. Connect a 1 µF capacitor between this pin and GND.
EN1
Enable Input to Regulator 1. Active high input.
High = On. Low = OFF.
3
4
EN2
Enable Input to Regulator 2. Active high input.
High = On. Low = OFF.
CBYP
Internal Voltage Reference Bypass. Connect a 10nF capacitor from this pin to GND to reduce output
noise and improve line transient and PSRR.
This pin may be left open.
5
SET
Set Delay Input. Connect a capacitor between this pin and GND to set the POR delay time. If left open,
there will be no delay.
6
7
8
GND
N/C
Common Ground pin. Connect externally to exposed pad.
No Connection. Do not connect to any other pin.
POR
Power-On Reset Output. Open drain output. Active low indicates under-voltage output on Regulator 2.
A pull-up resistor is required for correct operation.
9
VOUT2
VOUT1
GND
Output of Regulator 2. 300 mA maximum current output. Connect a 1 µF capacitor between this pin
and GND.
10
Output of Regulator 1. 150 mA maximum current output. Connect a 1 µF capacitor between this pin
and GND.
Pad
Common Ground. Connect to Pin 6.
2
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Connection Diagram
POR
8
N/C
7
GND
VOUT1
V
OUT2
9
10
6
GND
1
2
3
4
5
EN1
EN2
SET
V
C
BYP
IN
Top View
Figure 1. WSON-10 Package
See Package Number DSC0010A
(1)
Table 1. Additional Device Information
VOUT1/VOUT2 (V)
0.8/3.3
ORDER NUMBER
LP3996SD/X-0833/NOPB
LP3996SD/X-1018/NOPB
LP3996SD/X-1525/NOPB
LP3996SD/X-1833/NOPB
LP3996SD/X-2533/NOPB
LP3996SD/X-2828/NOPB
LP3996SD/X-3030/NOPB
LP3996SD/X-3033/NOPB
LP3996SD/X-3308/NOPB
LP3996SD/X-3333/NOPB
1.0/1.8
1.5/2.5
1.8/3.3
2.5/3.3
2.8/2.8
3.0/3.0
3.0/3.3
3.3/0.8
3.3/3.3
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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ABSOLUTE MAXIMUM RATINGS(1)(2)
Input Voltage to GND
–0.3V to 6.5V
VOUT1, VOUT2 EN1 and EN2 Voltage to GND
–0.3V to (VIN + 0.3V) with 6.5V
(max)
POR to GND
–0.3V to 6.5V
150°C
Junction Temperature (TJ-MAX
)
Lead/Pad Temp(3)
235°C
Storage Temperature
–65°C to 150°C
Continuous Power Dissipation Internally Limited(4)
Human Body Model
Machine Model
2.0kV
200V
ESD Rating(5)
(1) All Voltages are with respect to the potential at the GND pin.
(2) Absolute Maximum Ratings are limits beyond which damage can occur. Recommended Operating Conditions are conditions under
which operation of the device is ensured. Recommended Operating Conditions do not imply ensured performance limits. For ensured
performance limits and associated test conditions, see the Electrical Characteristics tables.
(3) For detailed soldering specifications and information, please refer to Texas Instruments Application Note AN-1187, Leadless Leadframe
Package.
(4) Internal thermal shutdown circuitry protects the device from permanent damage.
(5) The human body model is 100 pF discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor
discharged directly into each pin.
RECOMMENDED OPERATING CONDITIONS(1)(2)
Input Voltage
2.0V to 6.0V
0 to (VIN + 0.3V) to 6.0V (max)
–40°C to 125°C
EN1, EN2, POR Voltage
Junction Temperature
Ambient Temperature TA Range(3)
–40°C to 85°C
(1) Absolute Maximum Ratings are limits beyond which damage can occur. Recommended Operating Conditions are conditions under
which operation of the device is ensured. Recommended Operating Conditions do not imply ensured performance limits. For ensured
performance limits and associated test conditions, see the Electrical Characteristics tables.
(2) All Voltages are with respect to the potential at the GND pin.
(3) The maximum ambient temperature (TA(max)) is dependant on the maximum operating junction temperature (TJ(max-op) = 125°C), the
maximum power dissipation of the device in the application (PD(max)), and the junction to ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max) = TJ(max-op) - (θJA × PD(max)).
THERMAL PROPERTIES(1)
Junction-To-Ambient Thermal Resistance(2)
θJA WSON-10 Package
55°C/W
(1) Absolute Maximum Ratings are limits beyond which damage can occur. Recommended Operating Conditions are conditions under
which operation of the device is ensured. Recommended Operating Conditions do not imply ensured performance limits. For ensured
performance limits and associated test conditions, see the Electrical Characteristics tables.
(2) Junction-to-ambient thermal resistance is dependant on the application and board layout. In applications where high maximum power
dissipation is possible; special care must be paid to thermal dissipation issues in board design.
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ELECTRICAL CHARACTERISTICS(1)(2)
Unless otherwise noted, VEN = 950 mV, VIN = VOUT + 1.0V, or 2.0V, whichever is higher, where VOUT is the higher of VOUT1 and
VOUT2. CIN = 1 µF, IOUT = 1 mA, COUT1 = COUT2 = 1.0 µF.
Typical values and limits appearing in normal type apply for TA = 25°C. Limits appearing in boldface type apply over the full
junction temperature range for operation, −40 to +125°C.
LIMIT
SYMBOL
PARAMETER
CONDITIONS
TYP
UNITS
MIN
MAX
VIN
Input Voltage
See(3)
2
6
V
ΔVOUT
Output Voltage Tolerance
IOUT = 1mA
1.5V < VOUT ≤ 3.3V
OUT ≤ 1.5V
–2.5
–3.75
+2.5
+3.75
%
V
–2.75
+2.75
–4
+4
Line Regulation Error
Load Regulation Error
VIN = (VOUT(NOM) + 1.0V) to 6.0V
0.03
85
0.3
%/V
IOUT = 1 mA to 150 mA
(LDO 1)
155
µV/mA
IOUT = 1 mA to 300 mA
(LDO 2)
26
110
210
35
85
VDO
Dropout Voltage(4)
Quiescent Current
IOUT = 1 mA to 150 mA
(LDO 1)
220
550
100
110
110
mV
IOUT = 1 mA to 300 mA
(LDO 2)
IQ
LDO 1 ON, LDO 2 ON
IOUT1= IOUT2 = 0 mA
LDO 1 ON, LDO 2 OFF
IOUT1 = 150 mA
45
µA
nA
LDO 1 OFF, LDO 2 ON
IOUT2 = 300 mA
45
LDO 1 ON, LDO 2 ON
IOUT1 = 150 mA, IOUT2 = 300 mA
70
170
10
VEN1 = VEN2 = 0.4V
0.5
(1) All Voltages are with respect to the potential at the GND pin.
(2) Min and Max limits are specified by design, test or statistical analysis. Typical numbers are not ensured, but do represent the most likely
norm.
(3) VIN(MIN) = VOUT(NOM) +0.5V, or 2.0V, whichever is higher.
(4) Dropout voltage is voltage difference between input and output at which the output voltage drops to 100 mV below its nominal value.
This parameter only for output voltages above 2.0V
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ELECTRICAL CHARACTERISTICS(1)(2) (continued)
Unless otherwise noted, VEN = 950 mV, VIN = VOUT + 1.0V, or 2.0V, whichever is higher, where VOUT is the higher of VOUT1 and
VOUT2. CIN = 1 µF, IOUT = 1 mA, COUT1 = COUT2 = 1.0 µF.
Typical values and limits appearing in normal type apply for TA = 25°C. Limits appearing in boldface type apply over the full
junction temperature range for operation, −40 to +125°C.
LIMIT
SYMBOL
ISC
PARAMETER
CONDITIONS
TYP
UNITS
mA
MIN
MAX
750
Short Circuit Current Limit
LDO 1
LDO 2
LDO 1
LDO 2
420
550
840
IOUT
Maximum Output Current
150
300
mA
PSRR
Power Supply Rejection Ratio(5)
f = 1kHz, IOUT
1mA to 150 mA
CBYP = 10 nF
=
LDO1
LDO2
58
70
45
dB
f = 20 kHz, IOUT LDO1
= 1mA to 150
mA
CBYP = 10 nF
LDO2
60
en
Output noise Voltage(5)
Thermal Shutdown
BW = 10 Hz to
100kHz
CBYP = 10 nF
VOUT = 0.8V
VOUT = 3.3V
36
75
µVRMS
TSHUTDOWN
Temperature
Hysteresis
160
20
°C
Enable Control Characteristics
IEN
Input Current at VEN1 or VEN2
VEN = 0.0V
VEN = 6V
0.005
2
0.1
5
µA
VIL
VIH
Low Input Threshold at VEN1 or
VEN2
0.4
V
V
High Input Threshold at VEN1 or
VEN2
0.95
POR Output Characteristics
VTH
Low Threshold % 0f VOUT2 (NOM)
Flag ON
88
%
High Threshold % 0f VOUT2 (NOM)
Leakage Current
Flag OFF
96
IPOR
VOL
Flag OFF, VPOR = 6.5V
ISINK = 250 µA
30
20
nA
Flag Output Low Voltage
mV
Timing Characteristics
TON
Turn On Time(5)
To 95% Level
CBYP = 10 nF
300
20
µs
Transient
Response
Line Transient Response
Trise = Tfall = 10 µs
δVIN = 1VCBYP = 10 nF
(5)
|δVOUT
|
Load Transient Response
Trise = Tfall = 1
µs
LDO 1
IOUT = 1 mA to 150
mA
(5)
|δVOUT
|
175
150
mV
(pk - pk)
LDO 2
IOUT = 1 mA to 300
mA
SET Input Characteristics
ISET
SET Pin Current Source
SET Pin Threshold Voltage
VSET = 0V
1.3
µA
V
VTH(SET)
POR = High
1.25
(5) This electrical specification is specified by design.
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OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
LIMIT
SYMBOL
COUT
PARAMETER
Output Capacitance
CONDITIONS
Capacitance(1)
ESR
NOM
UNITS
MIN
0.7
5
MAX
1.0
µF
500
mΩ
(1) The Capacitor tolerance should be 30% or better over temperature. The full operating conditions for the application should be
considered when selecting a suitable capacitor to ensure that the minimum value of capacitance is always met. Recommended
capacitor is X7R. However, depending on the application, X5R, Y5V and Z5U can also be used. (See Capacitor sections in
APPLICATION HINTS.)
Transient Test Conditions
Figure 2. PSRR Input Signal
V
OUT
tr
V
OUT
tolerance
tr
V
IN
t
= t = 10 Ps
fall
rise
Line Step = 1V
I
I
= 150 mA
LOAD(LDO1)
LOAD(LDO2)
= 300 mA
V
+ 1V
OUT(NOM)
Figure 3. Line Transient Input Test Signal
V
OUT
tr
V
OUT
tolerance
tr
V
IN
Load Step LDO1 = 1 mA to 150 mA
Load Step LDO2 = 1 mA to 300 mA
Load Rise Time = Fall = 1 Ps
Figure 4. Load Transient Input Signal
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified, CIN = 1.0 µF Ceramic, COUT1 = COUT2 = 1.0 µF Ceramic, CBYP = 10 nF, VIN = VOUT2(NOM) + 1.0V, TA
= 25°C, VOUT1(NOM) = 3.3V, VOUT2(NOM) = 3.3V, Enable pins are tied to VIN.
Output Voltage Change vs Temperature
Ground Current vs Load Current, LDO1
Figure 5.
Figure 6.
Ground Current vs Load Current, LDO2
Ground Current vs VIN. ILOAD = 1mA
Figure 7.
Figure 8.
Dropout Voltage vs ILOAD, LDO1
Dropout Voltage vs ILOAD, LDO2
Figure 9.
Figure 10.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, CIN = 1.0 µF Ceramic, COUT1 = COUT2 = 1.0 µF Ceramic, CBYP = 10 nF, VIN = VOUT2(NOM) + 1.0V, TA
= 25°C, VOUT1(NOM) = 3.3V, VOUT2(NOM) = 3.3V, Enable pins are tied to VIN.
Short Circuit Current, LDO1
Short Circuit Current, LDO2
Figure 11.
Figure 12.
Power Supply Rejection Ratio, LDO1
Power Supply Rejection Ratio, LDO2
Figure 13.
Figure 14.
Enable Start-up Time, CBYP=0
Enable Start-up Time, CBYP=10nF
Figure 15.
Figure 16.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, CIN = 1.0 µF Ceramic, COUT1 = COUT2 = 1.0 µF Ceramic, CBYP = 10 nF, VIN = VOUT2(NOM) + 1.0V, TA
= 25°C, VOUT1(NOM) = 3.3V, VOUT2(NOM) = 3.3V, Enable pins are tied to VIN.
Line Transient, CBYP=10nF
Line Transient, CBYP=0
Figure 17.
Figure 18.
Load Transient, LDO1
Load Transient, LDO2
Figure 19.
Figure 20.
Noise Density LDO1
Noise Density, LDO2
Figure 21.
Figure 22.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, CIN = 1.0 µF Ceramic, COUT1 = COUT2 = 1.0 µF Ceramic, CBYP = 10 nF, VIN = VOUT2(NOM) + 1.0V, TA
= 25°C, VOUT1(NOM) = 3.3V, VOUT2(NOM) = 3.3V, Enable pins are tied to VIN.
Power-on-Reset Start-up Operation
Power-on-Reset Shutdown Operation
Figure 23.
Figure 24.
POR Delay Time
Figure 25.
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APPLICATION HINTS
Operation Description
The LP3996 is a low quiescent current, power management IC, designed specifically for portable applications
requiring minimum board space and smallest components. The LP3996 contains two independently selectable
LDOs. The first is capable of sourcing 150 mA at outputs between 0.8V and 3.3V. The second can source 300
mA at an output voltage of 0.8V to 3.3V. In addition, LDO2 contains power good flag circuit, which monitors the
output voltage and indicates when it is within 8% of its nominal value. The flag will also act as a power-on-reset
signal and, by adding an external capacitor; a delay may be programmed for the POR output.
Input Capacitor
An input capacitor is required for stability. It is recommended that a 1.0 µF capacitor be connected between the
LP3996 input pin and ground (this capacitance value may be increased without limit).
This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean
analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-
impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input,
it must be ensured by the manufacturer to have a surge current rating sufficient for the application.
There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and
temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain
approximately 1.0 µF over the entire operating temperature range.
Output Capacitor
The LP3996 is designed specifically to work with very small ceramic output capacitors. A 1.0 µF ceramic
capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5 mΩ to 500 mΩ, is suitable in the LP3996
application circuit.
For this device the output capacitor should be connected between the VOUT pin and ground.
It is also possible to use tantalum or film capacitors at the device output, COUT (or VOUT), but these are not as
attractive for reasons of size and cost (see Capacitor Characteristics).
The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR
value that is within the range 5 mΩ to 500 mΩ for stability.
No-Load Stability
The LP3996 will remain stable and in regulation with no external load. This is an important consideration in some
circuits, for example CMOS RAM keep-alive applications.
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Capacitor Characteristics
The LP3996 is designed to work with ceramic capacitors on the output to take advantage of the benefits they
offer. For capacitance values in the range of 0.47 µF to 4.7 µF, ceramic capacitors are the smallest, least
expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The
ESR of a typical 1.0 µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR
requirement for stability for the LP3996.
For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure
correct device operation. The capacitor value can change greatly, depending on the operating conditions and
capacitor type.
In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the
specification is met within the application. The capacitance can vary with DC bias conditions as well as
temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging.
The capacitor parameters are also dependant on the particular case size, with smaller sizes giving poorer
performance figures in general. As an example, Figure 26 shows a typical graph comparing different capacitor
case sizes in a Capacitance vs. DC Bias plot. As shown in the graph, increasing the DC Bias condition can result
in the capacitance value falling below the minimum value given in the recommended capacitor specifications
table (0.7 µF in this case). Note that the graph shows the capacitance out of spec for the 0402 case size
capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’ specifications for
the nominal value capacitor are consulted for all conditions, as some capacitor sizes (that is, 0402) may not be
suitable in the actual application.
0603, 10V, X5R
100%
80%
60%
0402, 6.3V, X5R
40%_
20%
_
2.0
_
3.0
_
4.0
_
5.0
_
0
1.0
DC BIAS (V)
Figure 26. Graph Showing a Typical Variation in Capacitance vs DC Bias
The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a
temperature range of –55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R
has a similar tolerance over a reduced temperature range of –55°C to +85°C. Many large value ceramic
capacitors, larger than 1µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance
can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over
Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 0.47 µF to 4.7 µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic
capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about
2:1 as the temperature goes from 25°C down to –40°C, so some guard band must be allowed.
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Enable Control
The LP3996 features active high enable pins for each regulator, EN1 and EN2, which turns the corresponding
LDO off when pulled low. The device outputs are enabled when the enable lines are set to high. When not
enabled the regulator output is off and the device typically consumes 2nA.
If the application does not require the Enable switching feature, one or both enable pins should be tied to VIN to
keep the regulator output permanently on.
To ensure proper operation, the signal source used to drive the enable inputs must be able to swing above and
below the specified turn-on / off voltage thresholds listed in the Electrical Characteristics section under VIL and
VIH.
Power-On-Reset
The POR pin is an open-drain output which will be set to Low whenever the output of LDO2 falls out of regulation
to approximately 90% of its nominal value. An external pull-up resistor, connected to VOUT or VIN, is required on
this pin. During start-up, or whenever a fault condition is removed, the POR flag will return to the High state after
the output reaches approximately 96% of its nominal value. By connecting a capacitor from the SET pin to GND,
a delay to the rising condition of the POR flag may be introduced. The delayed signal may then be used as a
Power-on -Reset for a microprocessor within the user's application.
The duration of the delay is determined by the time to charge the delay capacitor to a threshold voltage of 1.25V
at 1.2 µA from the SET pin as in the formula below.
VTH(SET) X CSET
tDELAY
=
ISET
(1)
A 0.1 µF capacitor will introduce a delay of approximately 100 ms.
Bypass Capacitor
The internal voltage reference circuit of the LP3996 is connected to the CBYP pin via a high value internal resistor.
An external capacitor, connected to this pin, forms a low-pass filter which reduces the noise level on both outputs
of the device. There is also some improvement in PSSR and line transient performance. Internal circuitry ensures
rapid charging of the CBYP capacitor during start-up. A 10 nF, high quality ceramic capacitor with either NPO or
COG dielectric is recommended due to their low leakage characteristics and low noise performance.
Safe Area of Operation
Due consideration should be given to operating conditions to avoid excessive thermal dissipation of the LP3996
or triggering its thermal shutdown circuit. When both outputs are enabled, the total power dissipation will be
PD(LDO1) + PD(LDO2) Where PD = (VIN - VOUT) x IOUT for each LDO.
In general, device options which have a large difference in output voltage will dissipate more power when both
outputs are enabled, due to the input voltage required for the higher output voltage LDO. In such cases,
especially at elevated ambient temperature, it may not be possible to operate both outputs at maximum current
at the same time.
14
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3996
LP3996
www.ti.com
SNVS360D –NOVEMBER 2006–REVISED OCTOBER 2013
REVISION HISTORY
Changes from Revision B (March 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format; ......................................................................................................... 14
Changes from Revision C (March 2013) to Revision D
Page
•
Added Additional Device Table back to datasheet ............................................................................................................... 3
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: LP3996
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
LP3996SD-0833/NOPB
LP3996SD-1018/NOPB
LP3996SD-1525/NOPB
LP3996SD-1833/NOPB
LP3996SD-2533/NOPB
LP3996SD-2828/NOPB
LP3996SD-3030/NOPB
LP3996SD-3033/NOPB
LP3996SD-3308/NOPB
LP3996SD-3333/NOPB
LP3996SDX-0833/NOPB
LP3996SDX-1018/NOPB
LP3996SDX-1525/NOPB
LP3996SDX-1833/NOPB
LP3996SDX-2533/NOPB
LP3996SDX-2828/NOPB
LP3996SDX-3030/NOPB
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSC
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
1000
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
L167B
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
1000
1000
1000
1000
1000
1000
1000
1000
1000
4500
4500
4500
4500
4500
4500
4500
Green (RoHS
& no Sb/Br)
L227B
L168B
L228B
L229B
L171B
L172B
L170B
L188B
L173B
L167B
L227B
L168B
L228B
L229B
L171B
L172B
Green (RoHS
& no Sb/Br)
-40 to 85
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
-40 to 85
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
LP3996SDX-3033/NOPB
LP3996SDX-3308/NOPB
LP3996SDX-3333/NOPB
ACTIVE
WSON
WSON
WSON
DSC
10
10
10
4500
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
L170B
ACTIVE
ACTIVE
DSC
DSC
4500
4500
Green (RoHS
& no Sb/Br)
-40 to 85
L188B
L173B
Green (RoHS
& no Sb/Br)
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3996SD-0833/NOPB
LP3996SD-1018/NOPB
LP3996SD-1525/NOPB
LP3996SD-1833/NOPB
LP3996SD-2533/NOPB
LP3996SD-2828/NOPB
LP3996SD-3030/NOPB
LP3996SD-3033/NOPB
LP3996SD-3308/NOPB
LP3996SD-3333/NOPB
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
4500
4500
4500
4500
4500
4500
4500
4500
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
LP3996SDX-0833/NOPB WSON
LP3996SDX-1018/NOPB WSON
LP3996SDX-1525/NOPB WSON
LP3996SDX-1833/NOPB WSON
LP3996SDX-2533/NOPB WSON
LP3996SDX-2828/NOPB WSON
LP3996SDX-3030/NOPB WSON
LP3996SDX-3033/NOPB WSON
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2013
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3996SDX-3308/NOPB WSON
LP3996SDX-3333/NOPB WSON
DSC
DSC
10
10
4500
4500
330.0
330.0
12.4
12.4
3.3
3.3
3.3
3.3
1.0
1.0
8.0
8.0
12.0
12.0
Q1
Q1
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP3996SD-0833/NOPB
LP3996SD-1018/NOPB
LP3996SD-1525/NOPB
LP3996SD-1833/NOPB
LP3996SD-2533/NOPB
LP3996SD-2828/NOPB
LP3996SD-3030/NOPB
LP3996SD-3033/NOPB
LP3996SD-3308/NOPB
LP3996SD-3333/NOPB
LP3996SDX-0833/NOPB
LP3996SDX-1018/NOPB
LP3996SDX-1525/NOPB
LP3996SDX-1833/NOPB
LP3996SDX-2533/NOPB
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
4500
4500
4500
4500
4500
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
367.0
367.0
367.0
367.0
367.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
367.0
367.0
367.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2013
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP3996SDX-2828/NOPB
LP3996SDX-3030/NOPB
LP3996SDX-3033/NOPB
LP3996SDX-3308/NOPB
LP3996SDX-3333/NOPB
WSON
WSON
WSON
WSON
WSON
DSC
DSC
DSC
DSC
DSC
10
10
10
10
10
4500
4500
4500
4500
4500
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 3
MECHANICAL DATA
DSC0010A
SDA10A (Rev A)
www.ti.com
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