LP5009_V02 [TI]
LP50xx 9-, 12-Channel, 12-Bit PWM Ultra-low Quiescent Current I2C RGB LED Drivers;
| 型号： | LP5009_V02 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LP50xx 9-, 12-Channel, 12-Bit PWM Ultra-low Quiescent Current I2C RGB LED Drivers |
| 文件： | 总51页 (文件大小：2308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP5009, LP5012
SLVSEH2B – MAY 2019 – REVISED AUGUST 2020
LP50xx 9-, 12-Channel, 12-Bit PWM Ultra-low Quiescent Current
I2C RGB LED Drivers
1 Features
2 Applications
•
Operating voltage range:
LED lighting, indicator lights, and fun lights for:
– VCC range: 2.7 V to 5.5 V
– EN, SDA, and SCL pins compatible with
1.8-V, 3.3-V, and 5-V power rails
– Output maximum voltage: 6 V
12 Constant-current sinks with high precision
– 25.5 mA Maximum per channel with VCC in full
range
– 35 mA Maximum per channel when VCC ≥ 3.3 V
– Device-to-device error: ±5%; channel-to-
channel error: ±5%
•
•
•
•
•
•
•
•
Smart speaker (with voice assistant)
Smart home appliances
Video doorbell
Electronic smart lock
Smoke and heat detector
STB and DVR
•
Smart router
Handheld device
3 Description
•
•
Ultra-low quiescent current:
In smart homes and other applications that use
human-machine-interaction, high-performance RGB
LED drivers are required. LED animation effects such
as flashing, breathing and chasing that greatly
improves user experience, and minimal system noise
is essential.
– Shutdown mode: 1 µA (maximum) with EN low
– Power-saving mode: 10 µA (typical) with EN
high and all LEDs off for > 30 ms
Integrated 12-bit, 29-kHz PWM generator for each
channel:
– Independent color-mixing register per channel
– Independent brightness-control register per
RGB LED module
– Optional logarithmic- or linear-scale brightness
control
– Integrated 3-phase PWM-shifting scheme
3 Programmable banks (R, G, B) for easy software
control of each color
2 External hardware address pins allow connecting
up to 4 devices
Broadcast slave address allows configuring
multiple devices simultaneously
Auto-increment allows writing or reading
consecutive registers within one transmission
Up to 400-kHz fast-mode I2C speed
The LP50xx device is an 9- or 12-channel constant
current sink LED driver. The LP50xx device includes
integrated color mixing and brightness control, and
pre-configuration simplifies the software coding
process. Integrated 12-bit, 29-kHz PWM generators
for each channel enable smooth, vivid color for LEDs,
and eliminate audible noise.
•
•
•
•
•
Device Information
PART NUMBER(1)
LP5009
PACKAGE
BODY SIZE (NOM)
WQFN (20)
3.00 mm × 3.00 mm
LP5012
LP5009
TSSOP (24)
7.80 mm × 4.40 mm
LP5012
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VCC
CVCC
VMCU
VLED
VCC
OUT0
EN
OUT1
SDA
SCL
OUT2
ADDR0
MCU
LP5012
ADDR1
VCAP
OUT09
CVCAP
OUT10
OUT11
IREF
RIREF
GND
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP5009, LP5012
SLVSEH2B – MAY 2019 – REVISED AUGUST 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 7
7.1 Absolute Maximum Ratings........................................ 7
7.2 ESD Ratings............................................................... 7
7.3 Recommended Operating Conditions.........................7
7.4 Thermal Information....................................................7
7.5 Electrical Characteristics.............................................8
7.6 Timing Characteristics.................................................9
7.7 Typical Characteristics..............................................10
8 Detailed Description......................................................12
8.1 Overview...................................................................12
8.2 Functional Block Diagram.........................................12
8.3 Feature Description...................................................12
8.4 Device Functional Modes..........................................18
8.5 Programming............................................................ 19
8.6 Register Maps...........................................................23
9 Application and Implementation..................................35
9.1 Application Information............................................. 35
9.2 Typical Application.................................................... 35
10 Power Supply Recommendations..............................37
11 Layout...........................................................................37
11.1 Layout Guidelines................................................... 37
11.2 Layout Examples.....................................................38
12 Device and Documentation Support..........................40
12.1 Related Links.......................................................... 40
12.2 Receiving Notification of Documentation Updates..40
12.3 Support Resources................................................. 40
12.4 Trademarks.............................................................40
12.5 Electrostatic Discharge Caution..............................40
12.6 Glossary..................................................................40
13 Mechanical, Packaging, and Orderable
Information.................................................................... 40
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2019) to Revision B (August 2020)
Page
•
•
Updated the numbering format for tables, figures and cross-references throughout the document...................1
Added PW package option to data sheet .......................................................................................................... 1
Changes from Revision * (May 2019) to Revision A (July 2019)
Page
•
Changed from Advance Information to Production Data ................................................................................... 1
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5 Description (continued)
The LP50xx device controls each LED output with a 12-bit PWM resolution at 29-kHz switching frequency, which
helps achieve a smooth dimming effect and eliminates audible noise. The independent color mixing and intensity
control registers make the software coding straightforward. When targeting a fade-in, fade-out type breathing
effect, the global R, G, B bank control reduces the microcontroller loading significantly. The LP50xx device also
implements a PWM phase-shifting function to help reduce the input power budget when LEDs turn on
simultaneously.
The LP50xx device implements an automatic power-saving mode to achieve ultra-low quiescent current. When
channels are all off for 30 ms, the device total power consumption is down to 10 µA, which makes the LP50xx
device a potential choice for battery-powered end equipment.
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6 Pin Configuration and Functions
VCAP
OUT0
OUT1
OUT2
OUT3
1
2
3
4
5
15
14
13
12
11
ADDR1
ADDR0
NC
Thermal
Pad
NC
NC
Not to scale
Figure 6-1. LP5009 RUK Package 20-Pin WQFN With Exposed Thermal Pad Top View
VCAP
OUT0
OUT1
OUT2
OUT3
1
2
3
4
5
15
14
13
12
11
ADDR1
ADDR0
OUT11
OUT10
OUT9
Thermal
Pad
Not to scale
Figure 6-2. LP5012 RUK Package 20-Pin WQFN With Exposed Thermal Pad Top View
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ADDR0
NC
1
2
3
4
5
6
7
24
23
22
21
20
19
18
NC
AGND
ADDR1
VCC
NC
OUT8
OUT7
OUT6
DGND
OUT5
OUT4
OUT3
OUT2
OUT1
SDA
PGND
SCL
EN
8
9
17
16
IREF
VCAP
NC
10
11
12
15
14
13
OUT0
Figure 6-3. LP5009 PW Package 24-Pin TSSOP Top View
OUT11
OUT10
OUT9
OUT8
OUT7
OUT6
DGND
OUT5
OUT4
OUT3
OUT2
OUT1
ADDR0
AGND
ADDR1
VCC
1
2
3
4
5
6
7
24
23
22
21
20
19
18
SDA
PGND
SCL
EN
8
9
17
16
IREF
VCAP
NC
10
11
12
15
14
13
OUT0
Figure 6-4. LP5012 PW Package 24-Pin TSSOP Top View
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Pin Functions
PIN
RUK NO.
NAME
PW NO.
I/O
DESCRIPTION
LP5009 LP5012 LP5009 LP5012
ADDR0
ADDR1
EN
14
15
19
20
14
15
19
20
1
3
8
9
1
3
8
9
—
—
I
I2C slave-address selection pin. This pin must not be left floating.
I2C slave-address selection pin. This pin must not be left floating.
Chip enable input pin.
IREF
—
Output current-reference global-setting pin.
22, 23,
24
NC
11, 12, 13
—
—
—
No internal connection.
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
2
3
2
3
12
13
14
15
16
17
19
20
21
—
—
—
12
13
14
15
16
17
19
20
21
22
23
24
O
O
O
O
O
O
O
O
O
O
O
O
Current sink output 0. If not used, this pin can be left floating.
Current sink output 1. If not used, this pin can be left floating.
Current sink output 2. If not used, this pin can be left floating.
Current sink output 3. If not used, this pin can be left floating.
Current sink output 4. If not used, this pin can be left floating.
Current sink output 5. If not used, this pin can be left floating.
Current sink output 6. If not used, this pin can be left floating.
Current sink output 7. If not used, this pin can be left floating.
Current sink output 8. If not used, this pin can be left floating.
Current sink output 9. If not used, this pin can be left floating.
Current sink output 10. If not used, this pin can be left floating.
Current sink output 11. If not used, this pin can be left floating.
4
4
5
5
6
6
7
7
8
8
9
9
10
—
—
—
10
11
12
13
I2C bus clock line. If not used, this pin must be connected to GND
or VCC.
SCL
SDA
18
17
18
17
7
5
7
5
I
I2C bus data line. If not used, this pin must be connected to GND
or VCC.
I/O
Internal LDO output pin, this pin must be connected to a 1-µF
capacitor to GND. Place the capacitor as close to the device as
possible.
VCAP
1
1
10
10
—
VCC
GND
16
16
4
4
—
—
Power supply.
Thermal Thermal
pad
Exposed thermal pad also serves the ground pin for the WQFN
package.
—
—
pad
Analog circuits ground. AGND, PGND and DGND must be
conntected together.
AGND
PGND
DGND
—
—
2
6
2
6
—
—
—
Power ground. AGND, PGND and DGND must be conntected
together.
—
—
—
—
Digital circuits ground. AGND, PGND and DGND must be
conntected together.
18
18
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7 Specifications
7.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
Voltage on EN, IREF, OUTx, SCL, SDA, VCC
Voltage on ADDRx
6
VCC + 0.3
2
V
V
V
Voltage on VCAP
Continuous power dissipation
Junction temperature, TJ-MAX
Storage temperature, Tstg
Internally limited
–40
–65
125
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
2.7
0
MAX
5.5
5.5
5.5
85
UNIT
V
Input voltage on VCC
Voltage on OUTx
V
Voltage on ADDRx, EN, SDA, SCL
Operating ambient temperature, TA
0
V
–40
°C
7.4 Thermal Information
LP5009 or LP5012
THERMAL METRIC(1)
UNIT
RUK (QFN)
20 PINS
53.7
PW (TSSOP)
24 Pins
98.3
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
55.3
41.5
27.4
53.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.9
5.0
ψJB
27.4
53.1
RθJC(bot)
12.9
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
over operating ambient temperature range (–40°C < TA< 85°C) (unless otherwise noted)
PARAMETER
POWER SUPPLIES (VCC)
VVCC Supply voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.7
5.5
1
V
Shutdown supply current
Standby supply current
VEN = 0 V
0.2
6
µA
mA
VEN = 3.3 V, Chip_EN = 0 (bit)
10
6
Normal-mode supply current
With 10-mA LED current per OUTx
4
IVCC
VEN = 3.3 V, Chip_EN = 1 (bit),
Power_Save_EN = 1 (bit), all the LEDs off
duration > tPSM
Power-save mode supply current
6
10
µA
VUVR
Undervoltage restart
VVCC rising
VVCC falling
2.5
V
V
V
VUVF
Undervoltage shutdown
2
VUV_HYS
Undervoltage shutdown hysteresis
0.2
OUTPUT STAGE (OUTx)
Maximum sink current (OUT0–OUTx) (For VVCC in full range, Max_Current_Option =
25.5
35
LP5012, x = 11. For LP5009, x = 8.) 0 (bit), PWM = 100%
IMAX
mA
Maximum sink current (OUT0–OUTx) (For VVCC ≥ 3.3 V, Max_Current_Option = 1
LP5012, x = 11. For LP5009, x = 8.)
(bit), PWM = 100%
Internal sink current limit (OUT0–OUTx)
(For LP5012, x = 11. For LP5009, x = 8.) 0 (bit), VIREF = 0 V
VVCC in full range, Max_Current_Option =
35
40
55
75
85
ILIM
mA
µA
Internal sink current limit (OUT0–OUTx)
(For LP5012, x = 11. For LP5009, x = 8.) VIREF = 0 V
VVCC ≥ 3.3V, Max_Current_Option=1 (bit),
120
1
Leakage current (OUT0–OUTx) (For
PWM = 0%
Ilkg
0.1
LP5012, x = 11. For LP5009, x = 8.)
Channels' current are set to 10 mA. PWM
= 100% at 25°C. Already includes the
VIREF and KIREF tolerance
Device to device current error, IERR_DD
(IAVE - ISET)/ISET × 100%
=
IERR_DD
–5%
–5%
5%
5%
Channels' current are set to 10 mA. PWM
= 100% at 25°C. Already includes the
VIREF and KIREF tolerance
Channel to channel current error, IERR_CC
= (IOUTX - IAVE)/IAVE × 100%
IERR_CC
VIREF
KIREF
ƒPWM
IREF voltage
0.7
105
29
V
IREF ratio
PWM switching frequency
21
kHz
VVCC in full range, Max_Current_Option =
0 (bit), output current set to 20 mA, the
voltage when the LED current has
dropped 5%
0.25
0.3
0.35
0.4
VSAT
Output saturation voltage
V
VVCC ≥ 3.3 V, Max_Current_Option = 1
(bit), output current set to 20 mA, the
voltage when the LED current has
dropped 5%
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7.5 Electrical Characteristics (continued)
over operating ambient temperature range (–40°C < TA< 85°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC INPUTS (EN, SCL, SDA, ADDRx)
VIL
Low level input voltage
High level input voltage
Input current
0.4
V
V
VIH
1.4
–1
ILOGIC
VSDA
1
µA
V
SDA output low level
IPULLUP = 5 mA
0.4
PROTECTION CIRCUITS
T(TSD) Thermal-shutdown junction temperature
T(HYS) Thermal shutdown temperature hysteresis
160
15
°C
°C
7.6 Timing Characteristics
over operating ambient temperature range (-40°C < TA< 85°C) (unless otherwise noted)
PARAMETER
Internal oscillator frequency
Power save mode deglitch time
EN first rising edge until first I2C access
EN first falling edge until first I2C reset
I2C clock frequency
MIN
TYP
MAX
UNIT
ƒOSC
tPSM
15
MHz
ms
µs
20
30
40
500
3
tEN_H
tEN_L
ƒSCL
µs
400
kHz
µs
Hold time (repeated) START condition
Clock low time
0.6
1
2
1.3
µs
Clock high time
600
ns
3
Setup time for a repeated START condition
Data hold time
600
0
ns
4
ns
5
Data setup time
100
ns
6
Rise time of SDA and SCL
Fall time of SDA and SCL
20 + 0.1 Cb
15 + 0.1 Cb
600
300
300
ns
7
ns
8
Setup time for STOP condition
Bus free time between a STOP and a START condition
ns
9
1.3
µs
10
Capacitive load parameter for each bus line Load of 1 pF
corresponds to one nanosecond.
Cb
10
200
pF
Figure 7-1. I2C Timing Parameters
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7.7 Typical Characteristics
35
32.5
30
40
35
30
25
20
15
10
5
27.5
25
22.5
20
5mA-Average Current
10mA-Average Current
25.5mA-Average Current
35mA-Average Current
17.5
15
12.5
10
7.5
5
2.5
0
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
RIREF(kW)
-40 -30 -20 -10
0 10 20 30 40 50 60 70 80 90
Ambient Temperature (°C)
D005
D001
Figure 7-2. IOUT Target vs RIREF
VCC = 3.3 V
Figure 7-3. Output Current vs Temperature
40
35
30
25
20
15
10
5
2
Max in 5mA
Min in 5mA
Max in 10mA
Min in 10mA
Max in 25.5mA
Min in 25.5mA
1.6
1.2
0.8
0.4
0
5mA-Average Current
10mA-Average Current
25.5mA-Average Current
35mA-Average Current
-0.4
-0.8
-1.2
-1.6
-2
0
-40 -30 -20 -10
0 10 20 30 40 50 60 70 80 90
Ambient Temperature (°C)
-40 -30 -20 -10
0 10 20 30 40 50 60 70 80 90
Ambient Temperature (°C)
D002
D003
VCC = 5 V
VCC = 3.3 V
Figure 7-4. Output Current vs Temperature
Figure 7-5. Channel-to-Channel Current Accuracy
2
1.6
1.2
0.8
0.4
0.055
50-mA IREF
100-mA IREF
150-mA IREF
200-mA IREF
250-mA IREF
300-mA IREF
350-mA IREF
0.05
0.045
0.04
0.035
0.03
0.025
0.02
0.015
0.01
0.005
0
Max in 5mA
Min in 5mA
Max in 10mA
Min in 10mA
Max in 25.5mA
Min in 25.5mA
0
-0.4
-0.8
-1.2
-1.6
-2
-40 -30 -20 -10
0 10 20 30 40 50 60 70 80 90
Ambient Temperature (°C)
0
0.25 0.5 0.75
1
1.25 1.5 1.75
Output Pin Voltage (V)
2
2.25 2.5
D004
D006
VCC = 5 V
VCC = 3.3 V
Figure 7-6. Channel-to-Channel Current Accuracy
vs Temperature
Figure 7-7. OUT Pin Voltage vs Current
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0.055
0.05
0.045
0.04
0.035
0.03
0.025
0.02
0.015
0.01
0.005
0
50-mA IREF
100-mA IREF
150-mA IREF
200-mA IREF
250-mA IREF
300-mA IREF
350-mA IREF
0
0.25 0.5 0.75
1
1.25 1.5 1.75
Output Pin Voltage (V)
2
2.25 2.5
D007
VCC = 5 V
Figure 7-8. OUT Pin Voltage vs Output Current
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8 Detailed Description
8.1 Overview
The LP50xx device is an 9- or 12-channel constant-current-sink LED driver. The LP50xx device includes all
necessary power rails, an on-chip oscillator, and a two-wire serial I2C interface. The maximum constant-current
value of all channels is set by a single external resistor. Two hardware address pins allow up to four devices on
the same bus. An automatic power-saving mode is implemented to keep the total current consumption under 10
µA, which makes the LP50xx device a potential choice for battery-powered end equipment.
The LP50xx device is optimized for RGB LEDs regarding both live effects and software efforts. The LP50xx
device controls each LED output with 12-bit PWM resolution at 29-kHz switching frequency, which helps achieve
a smooth dimming effect and eliminates audible noise. The independent color-mixing and intensity-control
registers make the software coding straightforward. When targeting a fade-in, fade-out type breathing effect, the
global RGB bank control reduces the microcontroller loading significantly. The LP50xx device also implements a
PWM phase-shifting function to help reduce the input power budget when LEDs turn on simultaneously.
8.2 Functional Block Diagram
VCC
VLED
VCC
Bandgap
OUT0
OUT1
OUT2
V1P8
LDO
VCAP
12 Bits
29 kHz
PWM
Oscillator
15MHz
Generators
EN
SDA
SCL
OUT9
OUT10
OUT11
Digital
Interface
Digital Control
ADDR0
ADDR1
IREF
IREF Setting Current
Thermal Shutdown
GND
8.3 Feature Description
8.3.1 PWM Control for Each Channel
Most traditional LED drivers are designed for the single-color LEDs, in which the high-resolution PWM generator
is used for intensity control only. However, for RGB LEDs, both the color mixing and intensity control must be
addressed to achieve the target effect. With the traditional solution, the users must handle the color mixing and
intensity control simultaneously with a single PWM register. Several undesired effects occur: the limited dimming
steps, the complex software design and the color distortion when using a logarithmic scale control.
The LP50xx device is designed with independent color mixing and intensity control, which makes the RGB LED
effects fancy and the control experience straightforward. With the inputs of the color-mixing register and the
intensity-control register, the final PWM generator output for each channel is 12-bit resolution and 29-kHz
dimming frequency, which helps achieve a smooth dimming effect and eliminates audible noise. See Figure 8-1.
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Color-Mixing
Brightness-Control
PWM Generators
OUT0
8 Bits Color
8 Bits Color
8 Bits Color
12 Bits / 29KHz PWM
12 Bits / 29KHz PWM
12 Bits / 29KHz PWM
8 Bits Brightness
OUT1
OUT2
8 Bits Color
8 Bits Color
8 Bits Color
12 Bits / 29KHz PWM
12 Bits / 29KHz PWM
12 Bits / 29KHz PWM
OUT9
8 Bits Brightness
OUT10
OUT11
Figure 8-1. PWM Control Scheme for Each Channel
8.3.1.1 Independent Color Mixing Per RGB LED Module
Each output channel has its own individual 8-bit color-setting register (OUTx_COLOR). The device allows every
RGB LED module to achieve >16 million (256 × 256 × 256) color-mixing.
8.3.1.2 Independent Intensity Control Per RGB LED Module
When color is fixed, the independent intensity-control is used to achieve accurate and flexible dimming control
for every RGB LED module.
8.3.1.2.1 Intensity-Control Register Configuration
Every three consecutive output channels are assigned to their respective intensity-control register
(LEDx_BRIGHTNESS). For example, OUT0, OUT1, and OUT2 are assigned to LED0_BRIGHTNESS, so it is
recommended to connect the RGB LEDs in the sequence as shown in Table 8-1. The LP50xx device allows 256-
step intensity control for each RGB LED module, which helps achieve a smooth dimming effect.
Keeping FFh (default value) in the LED0_BRIGHTNESS register results in 100% dimming duty cycle. With this
setting, users can just configure the color mixing register by channel to achieve the target dimming effect in a
single-color LED application.
8.3.1.2.2 Logarithmic- or Linear-Scale Intensity Control
For human-eye-friendly visual performance, a logarithmic-scale dimming curve is usually implemented in LED
drivers. However, for RGB LEDs, if using a single register to achieve both color mixing and intensity control,
color distortion can be observed easily when using a logarithmic scale. The LP50xx device, with independent
color-mixing and intensity-control registers, implements the logarithmic scale dimming control inside the intensity
control function, which solves the color distortion issue effectively. See Figure 8-2. Also, the LP50xx device
allows users to configure the dimming scale either logarithmically or linearly through the global Log_Scale_EN
register. If a special dimming curve is desired, using the linear scale with software correction is the most flexible
approach. See Figure 8-3.
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Brightness Control
8 Bits Brightness
Linear OR Logarithmic
Log_Scale_EN
8 Bits Brightness
Linear OR Logarithmic
Figure 8-2. Logarithmic- or Linear-Scale Intensity Control
Linear Scale Dimming Curve
Logarithmic Scale Dimming Curve
100%
80%
60%
40%
20%
0%
100%
80%
60%
40%
20%
0%
0
0
32
64
96
128
160
192
224
255
32
64
96
128
160
192
224
255
LEDx_BRIGHTNESS Register Input
LEDx_BRIGHTNESS Register Input
Figure 8-3. Logarithmic vs Linear Dimming Curve
8.3.1.3 12-Bit, 29-kHz PWM Generator Per Channel
8.3.1.3.1 PWM Generator
With the inputs of the color mixing and the intensity control, the final output PWM duty cycle is defined as the
product obtained by multiplying the color-mixing register value by the related intensity-control register value. The
final output PWM duty cycle has 12 bits of control accuracy, which is achieved by a 9 bits of pure PWM
resolution and 3 bits of digital dithering control. For 3-bit dithering, every eighth pulse is made 1 LSB longer to
increase the average value by 1 / 8th. The LP50xx device allows users to enable or disable the dithering function
through the PWM_Dithering_EN register. When enabled (default), the output PWM duty-cycle accuracy is 12
bits. When disabled, the output PWM duty-cycle accuracy is 9 bits.
To eliminate the audible noise due to the PWM switching, the LP50xx device sets the PWM switching frequency
at 29 kHz, above the 20-kHz human hearing range.
8.3.1.4 PWM Phase-Shifting
A PWM phase-shifting scheme allows delaying the time when each LED driver is active. When the LED drivers
are not activated simultaneously, the peak load current from the pre-stage power supply is significantly
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decreased. The scheme also reduces input-current ripple and ceramic-capacitor audible ringing. LED drivers are
grouped into three different phases.
•
•
•
Phase 1—the rising edge of the PWM pulse is fixed. The falling edge of the pulse is changed when the duty
cycle changes. Phase 1 is applied to LED0, LED3, LED6, LED9.
Phase 2—the middle point of the PWM pulse is fixed. The pulse spreads in both directions when the PWM
duty cycle is increased. Phase 2 is applied to LED1, LED4, LED7, LED10.
Phase 3—the falling edge of the PWM pulse is fixed. The rising edge of the pulse is changed when the duty
cycle changes. Phase 3 is applied to LED2, LED5, LED8, LED11.
Cycle Time
LED0
LED3
Phase 1
LED9
LED1
LED4
Phase 2
LED10
LED2
LED5
Phase 3
LED11
Phase 1
Phase 2
Phase 3
Figure 8-4. PWM Phase-Shifting
8.3.2 LED Bank Control
For most LED-animation effects, like blinking and breathing, all the RGB LEDs have the same lighting pattern.
Instead of controlling the individual LED separately, which occupies the microcontroller resources heavily, the
LP50xx device provides an easy coding approach, the LED bank control.
Each channel can be configured as either independent control or bank control through the LEDx_Bank_EN
register. When LEDx_Bank_EN = 0 (default), the LED is controlled independently by the related color-mixing and
intensity-control registers. When LEDx_Bank_EN = 1, the LP50xx device drives the LEDs in LED bank-control
mode. The LED bank has its own independent PWM control scheme, which is the same structure as the PWM
scheme of each channel. See PWM Control for Each Channel for more details. When a channel is configured in
LED bank-control mode, the related color mixing and intensity control is governed by the bank control registers
(BANK_A_COLOR, BANK_B_COLOR, BANK_C_COLOR, and BANK_BRIGHTNESS) regardless of the inputs
on its own color-mixing and intensity-control registers.
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Bank Color-Mixing
Bank Brightness-Control
Bank PWM Generators
Bank A:
8 Bits Color
12 Bits / 29kHz PWM
Bank B:
Bank C:
8 Bits Color
8 Bits Color
8 Bits Brightness
12 Bits / 29kHz PWM
12 Bits / 29kHz PWM
Figure 8-5. Bank PWM Control Scheme
Table 8-1. Bank Number and LED Number Assignment
OUT NUMBER
BANK NUMBER
RGB LED MODULE NUMBER
OUT0
OUT1
Bank A
Bank B
LED0
LED1
LED2
LED3
OUT2
Bank C
Bank A
OUT3
OUT4
Bank B
OUT5
Bank C
Bank A
OUT6
OUT7
Bank B
OUT8
Bank C
Bank A
OUT9 (LP5012 only)
OUT10 (LP5012 only)
OUT11 (LP5012 only)
Bank B
Bank C
With the bank control configuration, the LP50xx device enables users to achieve smooth and live LED effects
globally with an ultrasimple software effort. Figure 8-6 shows an example using LED0 as an independent RGB
indicator and others with group breathing effect.
Bank A
CH3/6/9
Independent
CH0/1/2
Bank B
CH4/7/10
Bank C
CH5/8/11
Figure 8-6. Bank PWM Control Example
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8.3.3 Current Range Setting
The constant-current value (ISET) of all 12 channels is set by a single external resistor, RIREF. The value of RIREF
can be calculated by Equation 1.
V
IREF
RIREF = KIREF
ì
ISET
(1)
where:
•
•
KIREF = 105
VIREF = 0.7 V
With the IREF pin floating, the output current is close to zero. With the IREF pin shorted to GND, the LP50xx
device provides internal current-limit protection, and the output-channel maximum current is limited to ILIM
.
The LP50xx device supports two levels of maximum output current, IMAX
.
•
•
When VCC is in the range from 2.7 V to 5.5 V, and the Max_Current_Option (bit) = 0, IMAX = 25.5 mA.
When VCC is in the range from 3.3 V to 5.5 V, and the Max_Current_Option (bit) = 1, IMAX = 35 mA.
8.3.4 Automatic Power-Save Mode
When all the LED outputs are inactive, the LP50xx device is able to enter power-save mode automatically, thus
lowering idle-current consumption down to 10 μA (typical). Automatic power-save mode is enabled when register
bit Power_Save_EN = 1 (default) and all the LEDs are off for a duration of > 30 ms. Almost all analog blocks are
powered down in power-save mode. If any I2C command to the device occurs, the LP50xx device returns to
NORMAL mode.
8.3.5 Protection Features
8.3.5.1 Thermal Shutdown
The LP50xx device implements a thermal shutdown mechanism to protect the device from damage due to
overheating. When the junction temperature rises to 160°C (typical), the device switches into shutdown mode.
The LP50xx device releases thermal shutdown when the junction temperature of the device is reduced to 145°C
(typical).
8.3.5.2 UVLO
The LP50xx device has an internal comparator that monitors the voltage at VCC. When VCC is below VUVF, reset
is active and the LP50xx device is in the INITIALIZATION state.
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8.4 Device Functional Modes
VCC Power Up
EN = L
From all states
SHUTDOWN
EN = H
RESET = FF or UVLO = H
INITIALIZATION
From all states
STANDBY
Chip_EN = 1
Chip_EN = 0
I2C Command
TSD=H
TSD=L
THERMAL
SHUTDOWN
POWER SAVE
NORMAL
Power_Save_EN =1 and
All LEDs off > 30ms
Figure 8-7. Functional Modes
•
INITIALIZATION: The device enters into INITIALIZATION mode when EN = H. In this mode, all the registers
are reset. Entry can also be from any state, if the RESET (register) = FFh or UVLO is active.
NORMAL: The device enters the NORMAL mode when Chip_EN (register) = 1. ICC is 10 mA (typical).
POWER SAVE: The device automatically enters the POWER SAVE mode when Power_Save_EN (register) =
1 and all the LEDs are off for a duration of > 30 ms. In POWER SAVE mode, analog blocks are disabled to
minimize power consumption, but the registers retain the data and keep it available via I2C. ICC is 10 µA
(typical). In case of any I2C command to this device, it returns to the NORMAL mode.
•
•
•
•
SHUTDOWN: The device enters into SHUTDOWN mode from all states on VCC power up or when EN = L.
ICC is < 1 µA (maximum).
STANDBY: The device enters the STANDBY mode when Chip_EN (register) = 0. In this mode, all the OUTx
pins are shut down, but the registers retain the data and keep it available via I2C. STANDBY is the low-
power-consumption mode, when all circuit functions are disabled. ICC is 10 µA (typical).
THERMAL SHUTDOWN: The device automatically enters the THERMAL SHUTDOWN mode when the
junction temperature exceeds 160°C (typical). In this mode, all the OUTx outputs are shut down. If the
junction temperature decreases below 145°C (typical), the device returns to the NORMAL mode.
•
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8.5 Programming
8.5.1 I2C Interface
The I2C-compatible two-wire serial interface provides access to the programmable functions and registers on the
device. This protocol uses a two-wire interface for bidirectional communications between the devices connected
to the bus. The two interface lines are the serial data line (SDA) and the serial clock line (SCL). Every device on
the bus is assigned a unique address and acts as either a master or a slave depending on whether it generates
or receives the serial clock, SCL. The SCL and SDA lines must each have a pullup resistor placed somewhere
on the line and remain HIGH even when the bus is idle.
8.5.1.1 Data Validity
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state
of the data line can only be changed when the clock signal is LOW.
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 8-8. Data Validity
8.5.1.2 Start and Stop Conditions
START and STOP conditions classify the beginning and the end of the data transfer session. A START condition
is defined as the SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. A STOP condition is
defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The bus master always generates
START and STOP conditions. The bus is considered to be busy after a START condition and free after a STOP
condition. During data transmission, the bus master can generate repeated START conditions. First START and
repeated START conditions are functionally equivalent.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 8-9. Start and Stop Conditions
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8.5.1.3 Transferring Data
Every byte put on the SDA line must be eight bits long, with the most-significant bit (MSB) being transferred first.
Each byte of data must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated
by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The device pulls
down the SDA line during the ninth clock pulse, signifying an acknowledge. The device generates an
acknowledge after each byte has been received.
There is one exception to the acknowledge-after-every-byte rule. When the master is the receiver, it must
indicate to the transmitter an end of data by not acknowledging (negative acknowledge) the last byte clocked out
of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),
but the SDA line is not pulled down.
After the START condition, the bus master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE, and a 1
indicates a READ. The second byte selects the register to which the data is written. The third byte contains data
to write to the selected register.
Data Output
by Transmitter
NACK
Data Output
by Transmitter
ACK
SCL From
Master
1
2
8
9
Start
Condition
Clock Pulse for
Acknowledgment
Figure 8-10. Acknowledge and Not Acknowledge on I2C Bus
8.5.1.4 I2C Slave Addressing
The device slave address is defined by connecting GND or VCC to the ADDR0 and ADDR1 pins. A total of four
independent slave addresses can be realized by combinations when GND or VCC is connected to the ADDR0
and ADDR1 pins (see Table 8-2 and Table 8-3).
The device responds to a broadcast slave address regardless of the setting of the ADDR0 and ADDR1 pins.
Global writes to the broadcast address can be used for configuring all devices simultaneously. The device
supports global read using a broadcast address; however, the data read is only valid if all devices on the I2C bus
contain the same value in the addressed register.
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Table 8-2. Slave-Address Combinations
SLAVE ADDRESS
ADDR1
ADDR0
INDEPENDENT
BROADCAST
GND
GND
VCC
VCC
GND
VCC
GND
VCC
0010100
0010101
0010110
0010111
0001100
Table 8-3. Chip Address
SLAVE ADDRESS
R/ W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
ADDR1
0
Bit 1
ADDR0
0
Bit 0
1 or 0
1 or 0
Independent
Broadcast
0
0
0
0
1
0
0
1
1
1
8.5.1.5 Control-Register Write Cycle
•
•
•
•
•
•
•
•
The master device generates a start condition.
The master device sends the slave address (7 bits) and the data direction bit (R/ W = 0).
The slave device sends an acknowledge signal if the slave address is correct.
The master device sends the control register address (8 bits).
The slave device sends an acknowledge signal.
The master device sends the data byte to be written to the addressed register.
The slave device sends an acknowledge signal.
If the master device sends further data bytes, the control register address of the slave is incremented by 1
after the acknowledge signal. To reduce program load time, the device supports address auto incrementation.
The register address is incremented after each 8 data bits.
•
The write cycle ends when the master device creates a stop condition.
ack from slave
ack from slave
ack from slave
start MSB Chip Addr LSB
ack MSB Register Addr LSB ack MSB Data LSB ack stop
w
Figure 8-11. Write Cycle
8.5.1.6 Control-Register Read Cycle
•
•
•
•
•
•
•
•
•
•
The master device generates a start condition.
The master device sends the slave address (7 bits) and the data direction bit (R/ W = 0).
The slave device sends an acknowledge signal if the slave address is correct.
The master device sends the control register address (8 bits).
The slave device sends an acknowledge signal.
The master device generates a repeated-start condition.
The master device sends the slave address (7 bits) and the data direction bit (R/ W = 1).
The slave device sends an acknowledge signal if the slave address is correct.
The slave device sends the data byte from the addressed register.
If the master device sends an acknowledge signal, the control-register address is incremented by 1. The
slave device sends the data byte from the addressed register. To reduce program load time, the device
supports address auto incrementation. The register address is incremented after each 8 data bits.
The read cycle ends when the master device does not generate an acknowledge signal after a data byte and
generates a stop condition.
•
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ack from slave
ack from slave repeated start
ack from slave data from slave nack from master
start MSB Chip Addr LSB
MSB Register Addr LSB
rs MSB Chip Addr LSB
MSB Data LSB
stop
w
r
Figure 8-12. Read Cycle
8.5.1.7 Auto-Increment Feature
The auto-increment feature allows writing or reading several consecutive registers within one transmission. For
example, when an 8-bit word is sent to the device, the internal address index counter is incremented by 1, and
the next register is written. The auto-increment feature is enabled by default and can be disabled by setting the
Auto_Incr_EN bit = 0 in the DEVICE_CONFIG1 register. The auto-increment feature is applied for the full
register address from 0h to FFh.
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8.6 Register Maps
Table 8-4 lists the memory-mapped registers of the device.
Table 8-4. Register Maps
REGISTER
NAME
DEF-
AULT
ADDR TYPE
D7
D6
D5
D4
D3
D2
D1
D0
DEVICE_
CONFIG0
00h
01h
R/ W
R/ W
RESERVED
Chip_EN
RESERVED
00h
DEVICE_
CONFIG1
Power_Save_
EN
PWM_
Max_Current_
Option
RESERVED
Log_Scale_EN
Auto_Incr_EN
LED_Global Off
3Ch
Dithering_EN
LED3_Bank_EN
(Only for
LED_CONFIG0
02h
R/ W
RESERVED
LED2_Bank_EN LED1_Bank_EN LED0_Bank_EN 00h
LP5012)
BANK_
BRIGHTNESS
03h
04h
05h
06h
07h
08h
09h
0Ah
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
Bank_Brightness
FFh
00h
00h
00h
FFh
FFh
FFh
FFh
BANK_A_
COLOR
Bank_A_Color
Bank_B_Color
BANK_B_
COLOR
BANK_C_
COLOR
Bank_C_Color
LED0_
BRIGHTNESS
LED0_Brightness
LED1_Brightness
LED2_Brightness
LED1_
BRIGHTNESS
LED2_
BRIGHTNESS
LED3_
BRIGHTNESS
LED3_Brightness
(Only for LP5012)
OUT0_COLOR
OUT1_COLOR
OUT2_COLOR
OUT3_COLOR
OUT4_COLOR
OUT5_COLOR
OUT6_COLOR
OUT7_COLOR
OUT8_COLOR
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
OUT0_Color
OUT1_Color
OUT2_Color
OUT3_Color
OUT4_Color
OUT5_Color
OUT6_Color
OUT7_Color
OUT8_Color
00h
00h
00h
00h
00h
00h
00h
00h
00h
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Table 8-4. Register Maps (continued)
REGISTER
NAME
DEF-
AULT
ADDR TYPE
D7
D6
D5
D4
D3
D2
D1
D0
OUT9_Color
(Only for LP5012)
OUT9_COLOR
14h
15h
R/ W
R/ W
00h
00h
OUT10_Color
(Only for LP5012)
OUT10_COLOR
OUT11_Color
(Only for LP5012)
OUT11_COLOR
RESET
16h
17h
R/ W
W
00h
00h
Reset
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Table 8-5. Access Type Codes
ACCESS TYPE
CODE
DESCRIPTION
Read Type
R
R
Read
Write
Write Type
W
W
Reset or Default Value
Value after reset or the default
value
-n
8.6.1 DEVICE_CONFIG0 (Address = 0h) [reset = 0h]
DEVICE_CONFIG0 is shown in Figure 8-13 and described in Table 8-6.
Return to Table 8-4.
Figure 8-13. DEVICE_CONFIG0 Register
7
6
5
4
3
2
1
0
RESERVED
R/ W-0h
Chip_EN
R/ W-0h
RESERVED
R/ W-0h
Table 8-6. DEVICE_CONFIG0 Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
7
R/ W
0h
Reserved
1 = LP50xx enabled
0 = LP50xx not enabled
6
Chip_EN
R/ W
R/ W
0h
0h
5–0
RESERVED
Reserved
8.6.2 DEVICE_CONFIG1 (Address = 1h) [reset = 3Ch]
DEVICE_CONFIG1 is shown in Figure 8-14 and described in Table 8-7.
Return to Table 8-4.
Figure 8-14. DEVICE_CONFIG1 Register
7
6
5
4
3
2
1
0
Power_Save_E
N
PWM_Dithering Optional_Headr
RESERVED
R/ W-0h
Log_Scale_EN
R/ W-1h
Auto_Incr_EN
R/ W-1h
LED_Global Off
R/ W-0h
_EN
oom
R/ W-1h
R/ W-1h
R/ W-0h
Table 8-7. DEVICE_CONFIG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7–6
RESERVED
R/ W
0h
Reserved
1 = Logarithmic scale dimming curve enabled
0 = Linear scale dimming curve enabled
5
4
3
2
1
0
Log_Scale_EN
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
1h
1h
1h
1h
0h
0h
1 = Automatic power-saving mode enabled
0 = Automatic power-saving mode not enabled
Power_Save_EN
Auto_Incr_EN
1 = Automatic increment mode enabled
0 = Automatic increment mode not enabled
1 = PWM dithering mode enabled
0 = PWM dithering mode not enabled
PWM_Dithering_EN
Max_Current_Option
LED_Global Off
1 = Output maximum current IMAX = 35 mA.
0 = Output maximum current IMAX = 25.5 mA.
1 = Shut down all LEDs
0 = Normal operation
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8.6.3 LED_CONFIG0 (Address = 2h) [reset = 00h]
LED_CONFIG0 is shown in Figure 8-15 and described in Table 8-8.
Return to Table 8-4.
Figure 8-15. LED_CONFIG0 Register
7
6
5
4
3
2
1
0
LED0_Bank_E
N
RESERVED
R/ W-0h
LED3_Bank_EN LED2_Bank_EN LED1_Bank_EN
R/ W-0h R/ W-0h R/ W-0h
R/ W-0h
Table 8-8. LED_CONFIG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/ W
0h
Reserved
1 = LED3 bank control mode enabled
0 = LED3 Independent control mode enabled
3
2
1
0
LED3_Bank_EN
LED2_Bank_EN
LED1_Bank_EN
LED0_Bank_EN
R/ W
R/ W
R/ W
R/ W
0h
0h
0h
0h
1 = LED2 bank control mode enabled
0 = LED2 independent control mode enabled
1 = LED1 bank control mode enabled
0 = LED1 independent control mode enabled
1 = LED0 bank control mode enabled
0 = LED0 independent control mode enabled
8.6.4 BANK_BRIGHTNESS (Address = 3h) [reset = FFh]
BANK_BRIGHTNESS is shown in Figure 8-16 and described in Table 8-9.
Return to Table 8-4.
Figure 8-16. BANK_BRIGHTNESS Register
7
6
5
4
3
2
1
0
Bank_Brightness
R/ W-FFh
Table 8-9. BANK_BRIGHTNESS Register Field Descriptions
Bit
Field
Type
Reset
Description
FFh = 100% of full brightness
...
7–0
Bank_Brightness
R/ W
FFh
80h = 50% of full brightness
...
00h = 0% of full brightness
8.6.5 BANK_A_COLOR (Address = 4h) [reset = 00h]
BANK_A_COLOR is shown in Figure 8-17 and described in Table 8-10.
Return to Table 8-4.
Figure 8-17. BANK_A_COLOR Register
7
6
5
4
3
2
1
0
Bank_A_Color
R/ W-0h
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Table 8-10. BANK_A_COLOR Register Field Descriptions
Field
Type
Reset
Description
FFh = The color mixing percentage is 100%.
...
7–0
Bank_A_Color
R/ W
0h
80h = The color mixing percentage is 50%.
...
00h = The color mixing percentage is 0%.
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8.6.6 BANK_B_COLOR (Address = 5h) [reset = 00h]
BANK_B_COLOR is shown in Figure 8-18 and described in Table 8-11.
Return to Table 8-4.
Figure 8-18. BANK_B_COLOR Register
7
6
5
4
3
2
1
0
Bank_B_Color
R/ W-0h
Table 8-11. BANK_B_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
FFh = The color mixing percentage is 100%.
...
7–0
Bank_B_Color
R/ W
0h
80h = The color mixing percentage is 50%.
...
00h = The color mixing percentage is 0%.
8.6.7 BANK_C_COLOR (Address = 6h) [reset = 00h]
BANK_C_COLOR is shown in Figure 8-19 and described in Table 8-12.
Return to Table 8-4.
Figure 8-19. BANK_C_COLOR Register
7
6
5
4
3
2
1
0
Bank_C_Color
R/ W-0h
Table 8-12. BANK_C_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
FFh = The color mixing percentage is 100%.
...
7–0
Bank_C_Color
R/ W
0h
80h = The color mixing percentage is 50%.
...
00h = The color mixing percentage is 0%.
8.6.8 LED0_BRIGHTNESS (Address = 7h) [reset = FFh]
LED0_BRIGHTNESS is shown in Figure 8-20 and described in Table 8-13.
Return to Table 8-4.
Figure 8-20. LED0_BRIGHTNESS Register
7
6
5
4
3
2
1
0
LED0_Brightness
R/ W-FFh
Table 8-13. LED0_BRIGHTNESS Register Field Descriptions
Bit
Field
Type
Reset
Description
FFh = 100% of full intensity
...
7–0
LED0_Brightness
R/ W
FFh
80h = 50% of full intensity
...
00h = 0% of full intensity
8.6.9 LED1_BRIGHTNESS (Address = 8h) [reset = FFh]
LED1_BRIGHTNESS is shown in Figure 8-21 and described in Table 8-14.
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Return to Table 8-4.
Figure 8-21. LED1_BRIGHTNESS Register
7
6
5
4
3
2
1
1
1
0
0
0
LED1_Brightness
R/ W-FFh
Table 8-14. LED1_BRIGHTNESS Register Field Descriptions
Bit
Field
Type
Reset
Description
FFh = 100% of full intensity
...
7–0
LED1_Brightness
R/ W
FFh
80h = 50% of full intensity
...
00h = 0% of full intensity
8.6.10 LED2_BRIGHTNESS (Address = 9h) [reset = FFh]
LED2_BRIGHTNESS is shown in Figure 8-22 and described in Table 8-15.
Return to Table 8-4.
Figure 8-22. LED2_BRIGHTNESS Register
5
7
6
4
3
2
LED2_Brightness
R/ W-FFh
Table 8-15. LED2_BRIGHTNESS Register Field Descriptions
Bit
Field
Type
Reset
Description
FFh = 100% of full intensity
...
7–0
LED2_Brightness
R/ W
FFh
80h = 50% of full intensity
...
00h = 0% of full intensity
8.6.11 LED3_BRIGHTNESS (Address = 0Ah) [reset = FFh]
LED3_BRIGHTNESS is shown in Figure 8-23 and described in Table 8-16.
Return to Table 8-4.
Figure 8-23. LED3_BRIGHTNESS Register
5
7
6
4
3
2
LED3_Brightness
R/ W-FFh
Table 8-16. LED3_BRIGHTNESS Register Field Descriptions
Bit
Field
Type
Reset
Description
FFh = 100% of full intensity
...
7–0
LED3_Brightness
R/ W
FFh
80h = 50% of full intensity
...
00h = 0% of full intensity
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8.6.12 OUT0_COLOR (Address = 0Bh) [reset = 00h]
OUT0_COLOR is shown in Figure 8-24 and described in Table 8-17.
Return to Table 8-4.
Figure 8-24. OUT0_COLOR Register
7
6
5
4
3
2
1
0
OUT0_Color
R/ W-00h
Table 8-17. OUT0_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
FFh = The color mixing percentage is 0%.
...
7–0
OUT0_Color
R/ W
00h
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.13 OUT1_COLOR (Address = 0Ch) [reset = 00h]
OUT1_COLOR is shown in Figure 8-25 and described in Table 8-18.
Return to Table 8-4.
Figure 8-25. OUT1_COLOR Register
7
6
5
4
3
2
1
0
OUT1_Color
R/ W-00h
Table 8-18. OUT1_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
FFh = The color mixing percentage is 0%.
...
7–0
OUT1_Color
R/ W
00h
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.14 OUT2_COLOR (Address = 0Dh) [reset = 00h]
OUT2_COLOR is shown in Figure 8-26 and described in Table 8-19.
Return to Table 8-4.
Figure 8-26. OUT2_COLOR Register
7
6
5
4
3
2
1
0
OUT2_Color
R/ W-00h
Table 8-19. OUT2_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
FFh = The color mixing percentage is 0%.
...
7–0
OUT2_Color
R/ W
00h
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.15 OUT3_COLOR (Address = 0Eh) [reset = 00h]
OUT3_COLOR is shown in Figure 8-27 and described in Table 8-20.
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Return to Table 8-4.
Figure 8-27. OUT3_COLOR Register
7
6
5
4
3
2
1
0
0
0
OUT3_Color
R/ W-00h
Table 8-20. OUT3_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
FFh = The color mixing percentage is 0%.
...
7–0
OUT3_Color
R/ W
00h
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.16 OUT4_COLOR (Address = 0Fh) [reset = 00h]
OUT4_COLOR is shown in Figure 8-28 and described in Table 8-21.
Return to Table 8-4.
Figure 8-28. OUT4_COLOR Register
7
6
5
4
3
2
1
OUT4_Color
R/ W-00h
Table 8-21. OUT4_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
FFh = The color mixing percentage is 0%.
...
7–0
OUT4_Color
R/ W
00h
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.17 OUT5_COLOR (Address = 10h) [reset = 00h]
OUT5_COLOR is shown in Figure 8-29 and described in Table 8-22.
Return to Table 8-4.
Figure 8-29. OUT5_COLOR Register
7
6
5
4
3
2
1
OUT5_Color
R/ W-00h
Table 8-22. OUT5_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
FFh = The color mixing percentage is 0%.
...
7–0
OUT5_Color
R/ W
00h
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
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8.6.18 OUT6_COLOR (Address = 11h) [reset = 00h]
OUT6_COLOR is shown in Figure 8-30 and described in Table 8-23.
Return to Table 8-4.
Figure 8-30. OUT6_COLOR Register
7
6
5
4
3
2
1
0
OUT6_Color
R/ W-00h
Table 8-23. OUT6_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
FFh = The color mixing percentage is 0%.
...
7–0
OUT6_Color
R/ W
00h
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.19 OUT7_COLOR (Address = 12h) [reset = 00h]
OUT7_COLOR is shown in Figure 8-31 and described in Table 8-24.
Return to Table 8-4.
Figure 8-31. OUT7_COLOR Register
7
6
5
4
3
2
1
0
OUT7_Color
R/ W-00h
Table 8-24. OUT7_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
FFh = The color mixing percentage is 0%.
...
7–0
OUT7_Color
R/ W
00h
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.20 OUT8_COLOR (Address = 13h) [reset = 00h]
OUT8_COLOR is shown in Figure 8-32 and described in Table 8-25.
Return to Table 8-4.
Figure 8-32. OUT8_COLOR Register
7
6
5
4
3
2
1
0
OUT8_Color
R/ W-00h
Table 8-25. OUT8_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
FFh = The color mixing percentage is 0%.
...
7–0
OUT8_Color
R/ W
00h
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.21 OUT9_COLOR (Address = 14h) [reset = 00h]
OUT9_COLOR is shown in Figure 8-33 and described in Table 8-26.
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Return to Table 8-4.
Figure 8-33. OUT9_COLOR Register
7
6
5
4
3
2
1
0
0
0
0
OUT9_Color
R/ W-00h
Table 8-26. OUT9_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
FFh = The color mixing percentage is 0%.
...
7–0
OUT9_Color
R/ W
00h
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.22 OUT10_COLOR (Address = 15h) [reset = 00h]
OUT10_COLOR is shown in Figure 8-34 and described in Table 8-27.
Return to Table 8-4.
Figure 8-34. OUT10_COLOR Register
7
6
5
4
3
2
1
OUT10_Color
R/ W-00h
Table 8-27. OUT10_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
FFh = The color mixing percentage is 0%.
...
7–0
OUT10_Color
R/ W
00h
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.23 OUT11_COLOR (Address = 16h) [reset = 00h]
OUT11_COLOR is shown in Figure 8-35 and described in Table 8-28.
Return to Table 8-4.
Figure 8-35. OUT11_COLOR Register
7
6
5
4
3
2
1
OUT11_Color
R/ W-00h
Table 8-28. OUT11_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
FFh = The color mixing percentage is 0%.
...
7–0
OUT11_Color
R/ W
00h
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.24 RESET (Address = 17h) [reset = 00h]
RESET is shown in Figure 8-36 and described in Table 8-29.
Return to Table 8-4.
Figure 8-36. RESET Register
7
6
5
4
3
2
1
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Figure 8-36. RESET Register (continued)
Reset
W-00h
Table 8-29. OUT14_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
Reset
W
00h
FFh = Reset all the registers to default value.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The LP50xx device is a 9- or 12-channel constant-current-sink LED driver. The LP50xx device improves the user
experience in color mixing and intensity control, for both live effects and coding effort. The optimized
performance for RGB LEDs makes it a good choice for human-machine interaction applications.
9.2 Typical Application
The LP50xx design supports up to four devices in parallel with different configurations on the ADDR0 and
ADDR1 pins.
VCC
CVCC
VMCU
VLED
VC
C
OUT0
RPULLUP
RPULLUP
EN
OUT1
OUT2
SDA
SCL
ADDR
0
MCU
ADDR
1
LP5012
OUT9
VCAP
CVCAP
OUT10
OUT11
IREF
RIREF
GND
VCC
CVCC
VLED
VC
C
OUT0
EN
OUT1
OUT2
SDA
SCL
ADDR
0
ADDR
1
LP5012
OUT9
VCAP
CVCAP
OUT10
OUT11
IREF
RIREF
GND
Figure 9-1. Driving Dual LP5012 Application Example
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9.2.1 Design Requirements
Set the LED current to 15 mA using the RIREF resistor. Select the proper value for the other external
components, like VCAP pin capacitor and the SCL/SDA pullup resisters.
9.2.2 Detailed Design Procedure
LP50xx scales up the reference current (IREF) set by the external resistor (RIREF) to sink the output current (IOUT
at each output port. The following formula can be used to calculate the external resistor (RIREF):
)
VIREF
RIREF=KIREF
×
ISET
(2)
The SCL and SDA lines must each have a pullup resistor placed somewhere on the line (the pullup resistors are
normally located on the bus master). In typical applications, values of 1.8 kΩ to 4.7 kΩ are used.
VCAP is internal LDO output pin. This pin must be connected through a 1-µF capacitor to GND. Place the
capacitor as close to the device as possible.
TI recommends having a 1-µF capacitor between VCC and GND to ensure proper operation. Place the capacitor
as close to the device as possible.
9.2.3 Application Curves
The test condition for Figure 9-2 is that the testing under bank control, with the register’s (0x04, 0x05, 0x06)
value is 0xF0.
The test condition for Figure 9-3 is that the testing under bank control, with the register’s (0x04, 0x05, 0x06)
value is 0x0F.
Figure 9-3. Current Waveform of OUT0, OUT1,
OUT2 and OUT3
Figure 9-2. Current Waveform of OUT0, OUT1,
OUT2 and OUT3
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10 Power Supply Recommendations
The device is designed to operate from a VVCC input-voltage supply range from 2.7 V and 5.5 V. This input
supply must be well-regulated and able to withstand maximum input current and maintain stable voltage without
voltage drop even in a load-transition condition (start-up or rapid intensity change). The resistance of the input
supply rail must be low enough that the input-current transient does not cause a drop below a 2.7-V level in the
LP50xx VVCC supply voltage.
11 Layout
11.1 Layout Guidelines
To prevent thermal shutdown, the junction temperature, TJ, must be less than T(TSD). If the voltage drop across
the output channels is high, the device power dissipation can be large. The LP50xx device has very good
thermal performance because of the thermal pad design; however, the PCB layout is also very important to
ensure that the device has good thermal performance. Good PCB design can optimize heat transfer, which is
essential for the long-term reliability of the device.
Use the following guidelines when designing the device layout:
•
Place the CVCAP, CVCCand RIREF as close to the device as possible. Also, TI recommends putting the ground
plane as Figure 11-1 and Figure 11-2.
•
Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat
flow path from the package to the ambient is through copper on the PCB. Maximum copper density is
extremely important when no heat sinks are attached to the PCB on the other side from the package.
Add as many thermal vias as possible directly under the package ground pad to optimize the thermal
conductivity of the board.
•
•
Use either plated-shut or plugged and capped vias for all the thermal vias on both sides of the board to
prevent solder voids. To ensure reliability and performance, the solder coverage must be at least 85%.
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11.2 Layout Examples
GND
GND
VCAP
OUT0
OUT1
OUT2
OUT3
1
2
3
4
5
15
14
13
12
11
ADDR1
ADDR0
To LED
To LED
To LED
To LED
GND
GND
GND
Figure 11-1. LP5009RUK Layout Example
GND
GND
VCAP
OUT0
OUT1
OUT2
OUT3
1
2
3
4
5
15
14
13
12
11
ADDR1
To LED
To LED
To LED
To LED
ADDR0
OUT11
OUT10
OUT9
GND
To LED
To LED
To LED
GND
GND
Figure 11-2. LP5012RUK Layout Example
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ADDR0
1
2
3
4
5
6
7
24
23
22
21
20
19
18
AGND
ADDR1
VCC
CVCC
To LED
OUT8
To LED
SDA
OUT7
To LED
OUT6
PGND
SCL
GND
GND
DGND
To LED
OUT5
EN
8
9
17
16
RIREF
To LED
IREF
VCAP
NC
OUT4
CVCAP
To LED
10
11
12
15
14
13
OUT3
To LED
OUT2
To LED
To LED
OUT0
OUT1
Figure 11-3. LP5009PW Layout Example
OUT11
OUT10
OUT9
OUT8
OUT7
OUT6
DGND
OUT5
OUT4
OUT3
OUT2
OUT1
ADDR0
AGND
ADDR1
VCC
To LED
To LED
To LED
To LED
To LED
To LED
1
2
3
4
5
6
7
24
23
22
21
20
19
18
CVCC
SDA
PGND
SCL
GND
GND
EN
To LED
To LED
To LED
To LED
To LED
8
9
17
16
RIREF
IREF
VCAP
NC
CVCAP
10
11
12
15
14
13
OUT0
To LED
Figure 11-4. LP5012PW Layout Example
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 12-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
LP5009
LP5012
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
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16-Oct-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP5009PWR
LP5009RUKR
LP5012RUKR
PLP5012PWR
PREVIEW
TSSOP
WQFN
WQFN
TSSOP
PW
24
20
20
24
2000
3000
3000
2000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 85
-40 to 85
-40 to 85
-40 to 85
LP5009PWR
ACTIVE
ACTIVE
ACTIVE
RUK
RUK
PW
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
Call TI
LP5009
LP5012
Green (RoHS
& no Sb/Br)
TBD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Oct-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jul-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP5009RUKR
LP5012RUKR
WQFN
WQFN
RUK
RUK
20
20
3000
3000
330.0
330.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jul-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP5009RUKR
LP5012RUKR
WQFN
WQFN
RUK
RUK
20
20
3000
3000
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
B
13
0.30
24X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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