LP5890 [TI]
具有 16 位 PWM 调光和超低功耗的 48x16 LED 矩阵驱动器;
| 型号： | LP5890 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 16 位 PWM 调光和超低功耗的 48x16 LED 矩阵驱动器 驱动 驱动器 |
| 文件： | 总70页 (文件大小：3084K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP5890
ZHCSO29 –JULY 2021
LP5890 16 × 48 矩阵驱动器，具有超低功耗
– 去除上下重影
– 低灰度增强
1 特性
– 检测和消除LED 开路、短路和弱短路
• 支持分立式VCC 和VR/G/B 电源
– VCC 电压范围：2.5V 至5.5V
– VR/G/B 电压范围：2.5V 至5.5V
• 48 个电流源通道，范围为0.2mA 至20mA
2 应用
• LED 数字标牌
• 键盘、游戏附件
• 大型和智能家用电器
• 智能音箱、有线和无线音箱
• 混音器、DJ 设备和广播
• 接入设备、交换机和服务器
– 通道间精度：±0.5%（典型值），±2%（最大
值）；器件间精度：±0.5%（典型值），±2%
（最大值）
– 低膝点电压：当IOUT = 5mA 时为0.26V（最大
值）
3 说明
– 3 位（8 级）全局亮度控制
– 8 位（256 级）色彩亮度控制
– 最大16 位（65536 级）PWM 灰度控制
• 带190mΩRDS(ON) 的16 个扫描线开关
• 超低功耗
电子设备变得越来越智能，而且需要使用更多的 LED
提供动画效果和指示功能，因此需要使用高性能 LED
矩阵驱动器以小尺寸解决方案改善用户体验。
LP5890 是高度集成的共阴极矩阵 LED 显示驱动器，
有 48 个恒流源和 16 个扫描 FET。单个 LP5890 能驱
动 16 × 16 RGB LED 像素，两个 LP5890 堆叠后可驱
动 32 × 32 RGB LED 像素。为实现低功耗，该器件可
通过其共阴极结构为红色、绿色和蓝色 LED 提供分立
式电源。此外，通过超低的工作电压范围（Vcc 低至
2.5V） 和超低的工作电流（ Icc 低至 3.9mA） ，
LP5890 可显著降低运行功率。
– 低至2.5V 的独立VCC
– 超低ICC（低至3.9mA），具有50MHz GCLK
– 智能省电模式
• 内置SRAM 支持1 至32 路复用
– 单个器件可驱动多达16 × 48 个LED 或16 × 16
个RGB LED
– 两个器件堆叠后可驱动多达32 × 96 个LED 或
32 × 32 个RGB LED
• 高速和低EMI 连续时钟串行接口(CCSI)
器件信息
封装(1)
VQFN (76)
BGA (96)
封装尺寸（标称值）
9mm × 9mm
器件型号
LP5890
– 仅三条线：SCLK/SIN/SOUT
– 外部50MHz（最大值）SCLK
– 支持40MHz 至160MHz 范围GCLK 的内部倍
频器
6mm × 6mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 经优化的显示性能
单器件或双器件可堆叠连接的LP5890
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSGD5
LP5890
ZHCSO29 –JULY 2021
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................23
8.5 Continuous Clock Series Interface............................24
8.6 PWM Grayscale Control........................................... 29
8.7 Register Maps...........................................................32
9 Application and Implementation..................................46
9.1 Application Information............................................. 46
9.2 Typical Application.................................................... 46
10 Power Supply Recommendations..............................54
11 Layout...........................................................................55
11.1 Layout Guidelines................................................... 55
11.2 Layout Example...................................................... 55
12 Device and Documentation Support..........................59
12.1 接收文档更新通知................................................... 59
12.2 支持资源..................................................................59
12.3 Trademarks.............................................................59
12.4 Electrostatic Discharge Caution..............................59
12.5 术语表..................................................................... 59
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................2
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Timing Requirements..................................................9
7.7 Switching Characteristics............................................9
7.8 Typical Characteristics..............................................10
8 Detailed Description......................................................12
8.1 Overview...................................................................12
8.2 Functional Block Diagram.........................................12
8.3 Feature Description...................................................13
Information.................................................................... 60
4 Revision History
DATE
REVISION
NOTES
July 2021
*
Initial release.
5 说明（续）
LP5890 实现了一个高速传输接口，可支持高设备数菊花链和高刷新率，同时尽可能降低电磁干扰 (EMI)。该器件
支持高达 50MHz 的 SCLK 和高达 160MHz 的 GCLK（内部）。同时，该器件集成了增强电路和智能算法，能够
应对多种 LED 矩阵应用中的各种显示挑战：由 LED 开路或短路引起的上下重影、低灰度不均匀、耦合以及毛虫
问题(Caterpillar)，使LP5890 成为此类应用的理想选择。
LP5890 还可以在运行期间实现 LED 开路/弱短路/短路的检测和消除，并可以将这些信息报告给配套的数字处理
器。
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6 Pin Configuration and Functions
1
2
57
56
55
54
53
52
51
50
49
48
47
46
R0
G0
R15
G15
B15
R14
G14
B14
VG
3
B0
4
R1
5
G1
6
B1
7
GND
8
VCC
VR
VG
VB
VB
9
10
11
12
VR
R2
G2
GND
R13
G13
B13
13
45
B2
R3
G3
B3
R4
G4
14
15
16
17
18
44
43
42
41
40
R12
G12
B12
R11
G11
B11
19
39
B4
图6-1. LP5890 RRF Package 76-Pin VQFN With Exposed Thermal Pad Top View
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
SOU
T
SCL
K
L2
L1
R1
G1
B1
B0
G0
R0
NC
SIN
NC
GND
GND
R14
G14
B14
R13
G13
R12
R11
L14
L15
GND
VG
L0
GND
GND
GND
GND
R7
GND
GND
GND
GND
B8
GND
GND
GND
GND
B9
GND
R15
G15
B15
B10
GND
VCC
VR
GND
R2
GND
R3
VG
G
H
J
G2
B2
G3
VB
VR
B3
VB
IREF
G4
R4
B13
G12
B12
K
L
B4
R6
B5
G6
B6
G7
B7
G8
R8
G9
R9
G10
R10
B11
G11
R5
G5
图6-2. LP5890 ZXL Package 96-Pin BGA Top View
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表6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
RRF NO.
ZXL NO.
Pin for setting the maximum constant-current value. Connecting an external
resistor between IREF and GND sets the maximum current for each constant-
current output channel. When this pin is connected directly to GND, all outputs
are forced off. The external resistor should be placed close to the device.
IREF
20
J1
I
VCC
VR
8
F1
I
I
I
I
Device power supply.
9, 10
51, 50
49, 48
G1, H1
E11, F11
G11, H11
Red LED power supply.
Green LED power supply.
Blue LED power supply.
VG
VB
1, 4, 11, 14, B5, B2,F2, F4,
17, 21, 24, J2, L1, K3, H5,
27, 32, 35, L6, L7, L8, L10,
38, 41, 44, K10, H10, E10,
R0-R15
G0-G15
B0-B15
O
O
O
Red LED Constant-current output.
Green LED Constant-current output.
Blue LED Constant-current output.
47, 54, 57
E8
2, 5, 12, 15, B4, C2, G2, G4,
18, 22, 25, K1, L2, K4, K5,
28, 31, 34, K6, K7, K8, L9,
37, 40, 43, K11, J10, F10,
46, 53, 56
F8
3, 6, 13, 16, B3, D2, H2, H4,
19, 23, 26, K2, L3, L4, L5,
29, 30, 33, H6, H7, H8, K9,
36, 39, 42, L11, J11, G10,
45, 52, 55
G8
76, 75, 74,
73, 72, 71,
70, 69, 68,
67, 66, 65,
64, 63, 62,
61
D1, C1, B1, A1,
A2, A3, A4, A5,
A6, A7, A8, A9,
A10, A11, B11,
C11
LINE0-
LINE15
O
Scan Lines.
SCLK
SIN
60
59
58
B9
B8
B7
I
I
Clock-signal input pin.
Serial-data input pin.
Serial data output pin.
SOUT
O
C10, E1, E2,
D5, D6, D7, D8,
D10, D11,
E1,E2, E4, E5,
E6,E7, F5, F6,
F7,G5, G6, G7
GND
7
-
-
-
Power-ground reference.
Thermal
pad
-
The thermal pad and the GND pin must be connected together on the board.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–40
–55
MAX
UNIT
V
VCC
6
6
VR/G/B
V
Voltage
IREF, SCLK, SIN, SOUT, VSYNC
RX/GX/BX
6
V
6
V
LINE0 to LINE15
6
V
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.5
NOM
MAX
5.5
UNIT
V
VCC
Device supply voltage
VLEDR/G/B LED supply voltage
2.5
5.5
V
VIH
VIL
IOH
IOL
ICH
ILINE
TA
High level logic input voltage (SCLK, SIN, VSYNC)
0.7 × VCC
V
Low level logic input voltage (SCLK, SIN, VSYNC)
High level logic output current (SOUT)
Low level logic output current (SOUT)
Constant output source current
0.3 × VCC
V
mA
mA
mA
A
–2
2
0.2
0
20
2
Line scan switch load current
Ambient operating temperature
85
°C
–40
7.4 Thermal Information
LP5890
THERMAL METRIC(1)
RRF (VQFN)
76 PINS
22.2
ZXL (BGA)
UNIT
96 PINS
33.5
18.6
11.7
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
10.7
RθJB
ψJT
Junction-to-board thermal resistance
7.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.1
0.3
7.1
11.6
ψJB
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LP5890
THERMAL METRIC(1)
RRF (VQFN)
76 PINS
1.7
ZXL (BGA)
96 PINS
UNIT
RθJC(bot) Junction-to-case (bottom) thermal resistance
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
At VCC = VR = 2.8V, VG/B = 3.8V and TA = –40°C to +85°C; Typical values are at TA = 25°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC
VUVR
VUVF
Device supply voltage
Undervoltage restart
Undervoltage shutdown
2.5
5.5
V
V
V
VCC rising
2.3
VCC falling
2.0
Undervoltage shutdown
hysteresis
VUV(HYS)
0.1
2.4
V
SCLK/SIN = GND, internal
GCLK=0MHz, GSn = 0000h, BC =
2h, CCR/G/B = 63h, PS_EN= 1h,
VOUTn = floating, RIREF = 7.8 kΩ
mA
SCLK = 10 MHz, internal GCLK = 50
MHz, GSn = 1FFFh, BC = 2h,
CCR/G/B = 63h,VOUTn = floating,
RIREF = 7.8 kΩ, ICH = 2 mA
ICC
Device supply current
3.9
5
mA
mA
SCLK = 10 MHz, internal GCLK =
100 MHz, GSn = 1FFFh, BC = 2h,
CCR/G/B = 63h, VOUTn = floating,
RIREF = 7.8 kΩ, ICH = 2 mA
VR/G/B
VIH
LED supply voltage
2.5
5.5
V
V
High level input voltage (SCLK,
SIN)
0.7 × VCC
Low level input voltage (SCLK,
SIN)
VIL
0.3 × VCC
V
VOH
High level output voltage (SOUT)
VCC-0.4
-1
VCC
0.4
1
V
V
IOH = –2 mA at SOUT
VOL
Low level output voltage (SOUT) IOL = 2 mA at SOUT
ILOGIC
Logic pin current (SCLK, SIN)
SCLK/SIN = VCC or GND
VCC = 2.8 V, TA= 25°C
uA
Scan switches' on-state
resistance (LINE0 to LINE15)
RDS(ON)
190
0.8
mΩ
SCLK/SIN = GND, internal GCLK=
0MHz, GSn = 0000h, BC = 2h,
CCR/G/B = 63h, VOUTn = floating,
RIREF = 7.8 kΩ
VIREF
Reference voltage
V
VLEDR/G/B ≥2.8 V, all channel
outputs on, output current at 1 mA
0.25
0.26
0.3
V
V
V
VLEDR/G/B ≥2.8 V, all channel
outputs on, output current at 5 mA
VLEDR/G/B ≥2.8 V, all channel
outputs on, output current at 10 mA
Channel knee voltage (R0-R15 /
G0-G15 / B0-B15)
VKNEE
VLEDR/G/B ≥2.8 V, IMAX = 1b, all
channel outputs on, output current at
15 mA
0.37
0.41
V
V
VLEDR/G/B ≥2.8 V, IMAX=1b, all
channel outputs on, output current at
20 mA
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7.5 Electrical Characteristics (continued)
At VCC = VR = 2.8V, VG/B = 3.8V and TA = –40°C to +85°C; Typical values are at TA = 25°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Channel leakage current (R0-
R15 / G0-G15 / B0-B15)
ICH(LKG)
Channel voltage at 0 V
1
uA
All CHn = on, BC = 00h, CC = 31h,
VOUTn = (VLED-1)V, RIREF = 19.05
kΩ(ICH = 0.2-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±1
±2.5
±1.5
±1.5
±2
%
%
%
%
%
All CHn = on, BC = 00h, CC = 7Dh,
VOUTn = (VLED-1)V, RIREF = 19.05
kΩ(ICH = 0.5-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±0.5
±0.5
±0.5
±0.5
All CHn = on, BC = 00h, CC = FBh,
VOUTn = (VLED-1)V, RIREF = 19.05
kΩ(ICH = 1-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
Constant-current channel to
channel deviation (R0-R15 / G0-
G15 / B0-B15)(1)
ΔIERR(CC)
All CHn = on, BC = 2h, CC = FBh,
VOUTn = (VLED-1)V, RIREF = 7.8
kΩ(ICH = 5-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
All CHn = on, BC = 6h, CC = A7h,
VOUTn = (VLED-1)V, RIREF = 7.8
kΩ(ICH = 10-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±2
All CHn = on, BC = 7h, CC = FBh,
IMAX=1b, VOUTn = (VLED-1)V,
RIREF = 6.8 kΩ(ICH = 20-mA target),
TA = 25°C, includes the VIREF
tolerance, at same color grouped
outputs of R0-R15 / G0-G15 / B0-
B15
±0.5
±2.5
%
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7.5 Electrical Characteristics (continued)
At VCC = VR = 2.8V, VG/B = 3.8V and TA = –40°C to +85°C; Typical values are at TA = 25°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
All CHn = on, BC = 00h, CC = 31h,
VOUTn = (VLED-1)V, RIREF = 19.05
kΩ(ICH = 0.2-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±1
±2.5
%
All CHn = on, BC = 00h, CC = 7Dh,
VOUTn = (VLED-1)V, RIREF = 19.05
kΩ(ICH = 0.5-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±0.5
±0.5
±0.5
±0.5
±1.5
%
%
%
%
All CHn = on, BC = 00h, CC = FBh,
VOUTn = (VLED-1)V, RIREF = 19.05
kΩ(ICH = 1-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±1
Constant-current device to
device deviation (R0-R15 / G0-
G15 / B0-B15)(2)
ΔIERR(DD)
All CHn = on, BC = 2h, CC = FBh,
VOUTn = (VLED-1)V, RIREF = 7.8
kΩ(ICH = 5-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±1.5
All CHn = on, BC = 6h, CC = A7h,
VOUTn = (VLED-1)V, RIREF = 7.8
kΩ(ICH = 10-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±2
All CHn = on, BC = 7h, CC = FBh,
IMAX=1b, VOUTn = (VLED-1)V,
RIREF = 6.8 kΩ(ICH = 20-mA target),
TA = 25°C, includes the VIREF
tolerance, at same color grouped
outputs of R0-R15 / G0-G15 / B0-
B15
±0.5
±2
%
VLED = 2.5 to 5.5V, All CHn = on,
VOUTn = (VLED-1)V, at same color
grouped outputs of R0-R15 / G0-
G15 / B0-B15
Line regulation (R0-R15 / G0-
G15 / B0-B15)(3)
±1
±1
%/V
%/V
ΔIREG(LINE)
VOUTn = (VLED-1)V to (VLED-3)V,
VR=VG/B=VLED=3.8V, All CHn =
on, at same color grouped outputs of
R0-R15 / G0-G15 / B0-B15
Load regulation (R0-R15 / G0-
G15 / B0-B15)(4)
ΔIREG(LOAD)
TTSD
THYS
Thermal shutdown threshold
Thermal shutdown hysteresis
170
15
°C
°C
(1) The deviation of each output in same color group (OUTR0-15 or OUTG0-15 or OUTB0-15) from the average of same color group
+
:J
: ;
¿ % = N
F 1O × 100
+
:0 + +:1 + ® + +:14 + +:15
16
constant current. The deviation is calculated by the formula. (X = R or G or B, n = 0-15)
spacer
(2) The deviation of the average of constant-current in each color group from the ideal constant-current value. (X = R or G or B):
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+
:0
+ +:1 + ® + +:14 + +:15
16
F Ideal Output Current
: ;
¿ % =
N
O
× 100
Ideal Output Current
Ideal current is calculated by the following equation:
8
1 + %%_4(KN %%_) KN %%_$)
+4'(
+
=
× )#+0
×
+&'#._4(KN ) KN $)
($%)
4+4'(
256
spacer
(3) Line regulation is calculated by the following equation. (X = R or G or B, n = 0-15):
(+:J =P 8.'& = 5.58) F (+:J =P 8.'& = 2.58)
100
: ;
¿ %8 = [
] ×
(+:J =P 8.'& = 2.58)
5.58 F 2.58
spacer
(4) Load regulation is calculated by the following equation. (X = R or G or B, n = 0-15):
(I at V =1V ) -(I at V = 3V )
100
Xn
Xn
Xn
Xn
D(%V ) =[
]ì
(I at V = 3V )
3V -1V
Xn
Xn
spacer
7.6 Timing Requirements
At VCC = VR = 2.8 V, VG/B = 3.8V and TA = –40°C to +85°C; Typical values are at TA = 25°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
ns
fSCLK
tw(H0)
tw(L0)
tsu(0)
th(0)
Clock frequency (SCLK)
High level pulse duration (SCLK)
Low level pulse duration (SCLK)
Setup time
50
9
9
ns
10
2
ns
SIN to SCLK↑
SCLK↑to SIN↑↓
Hold time
ns
7.7 Switching Characteristics
At VCC = VR = 2.8 V, VG/B = 3.8V and TA = –40°C to +85°C; Typical values are at TA = 25°C (unless otherwise specified)
PARAMETER
Rise time (SOUT)
Fall time (SOUT)
TEST CONDITIONS
VCC = 3.3 V, CSOUT = 30 pF
VCC = 3.3 V, CSOUT = 30 pF
MIN
TYP
MAX
UNIT
tr
tf
2
10
ns
2
10
ns
SCLK↑to SOUT↑↓, full
temperature, CSOUT = 30 pF
tpd(0)
Propagation delay
3.5
14.2
ns
图7-1. Timing and Switching Diagram
(1). Input pulse rise and fall time is 2 ns typically.
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7.8 Typical Characteristics
0.016
0.014
0.012
0.01
0.016
0.014
0.012
0.01
0.2 mA
1 mA
5 mA
10mA
15 mA
0.2 mA
1 mA
5 mA
10 mA
15 mA
0.008
0.006
0.004
0.002
0
0.008
0.006
0.004
0.002
0
0
0.2 0.4 0.6 0.8
1
VLED-VCH (V)
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1
VLED-VCH (V)
1.2 1.4 1.6 1.8
2
D001
D002
D001_SLVSEJ1.grf
D002_SLVSEJ1.grf
Vcc = 2.8 V
Vcc = 5.5 V
图7-2. Channel Current vs (VLED-Vchannel) Voltage
图7-3. Channel Current vs (VLED-Vchannel) Voltage
0.011
1
-40 oC
25 oC
85 oC
0.01
0.8
0.6
0.009
0.008
0.007
0.006
0.005
0.004
0.003
0.002
0.001
-40oC Min
0.4
0.2
0
-0.2
-40oC Max
25oC Min
25oC Max
85oC Min
85oC Max
-0.4
-0.6
0
0.2 0.4 0.6 0.8
1
VLED-VCH (V)
1.2 1.4 1.6 1.8
2
0
2
4
6
8
10
12
Output Current (mA)
14
16
18
20
D003
D004
D003_SLVSEJ1.grf
D004_SLVSEJ1.grf
图7-4. Channel Current vs (VLED-Vchannel) Voltage
图7-5. Channel to Channel Accuracy vs Output Current
1
0.8
0.6
0.016
0.2 mA, BC=00h, REF=19.05K
0.014
0.012
0.01
1 mA, BC=02h, REF=7.8K
5 mA, BC=02h, REF=7.8K
10 mA, BC=06h, REF=7.8K
15 mA, BC=06h, REF=7.8K
-40oC Min
0.4
0.2
0
-0.2
-40oC Max
25oC Min
0.008
0.006
0.004
0.002
0
25oC Max
85oC Min
85oC Max
-0.4
-0.6
0
30
60
90
Color Control Code (Decimal)
120 150 180 210 240 270
0
2
4
6
8
10
12
Output Current (mA)
14
16
18
20
D005
D004
D005_SLVSEJ1.grf
D004_SLVSEJ1.grf
图7-7. Color Control Code vs Output Current
图7-6. Channel to Channel Accuracy vs Output Current
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7.8 Typical Characteristics (continued)
10.5
10
9.5
9
7.8
7.7
7.6
7.5
7.4
7.3
7.2
7.1
7
8.5
8
7.5
7
6.5
6
6.9
6.8
6.7
5.5
5
40
60
80
100
120
GCLK Frequency (MHz)
140
160
180
2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
Vcc voltage (V)
4
4.2 4.4 4.6
D006
D007
D006_SLVSEJ1.grf
D007_SLVSEJ1.grf
图7-8. Icc Current vs GCLK Frequency
GCLK = 83 MHz
图7-9. Icc Current vs Vcc Voltage
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8 Detailed Description
8.1 Overview
The LP5890 is a highly integrated RGB LED driver with 48 constant current sources and 16 scanning FETs. A
single LP5890 is capable of driving 16 × 16 RGB LED pixels while stacking two LP5890s can drive 32 × 32 RGB
LED pixels. To achieve low power consumption, the device supports separated power supplies for the red,
green, and blue LEDs by its common cathode structure. Furthermore, the operation power of the LP5890 is
significantly reduced by ultra-low operation voltage range (VCC down to 2.5 V) and ultra-low operation current
(ICC down to 3.9 mA).
The LP5890 supports per channel current from 0.2 mA to 20 mA, with typical 1% channel-to-channel current
deviation and typical 1% device-to-device current deviation. The DC current value of all 48 channels is set by an
external IREF resistor and can be adjusted by the 8-step global brightness control (BC) and the 256-step per-
color group brightness control (CCR/CCG/CCB).
The LP5890 implements a high speed transmission interface to support high device count daisy-chained and
high refresh rate while minimizing electrical-magnetic interference (EMI). The LP5890 supports up to 50-MHz
SCLK (external) and up to 160-MHz GCLK (internal). Meanwhile, the device integrates enhanced circuits and
intelligent algorithms to solve the various display challenges in Narrow Pixel Pitch(NPP) LED display applications
and Mini or Micro-LED products: Dim at the fist scan line, Upper and downside ghosting, Non-uniformity in low
grayscale, Coupling, Caterpillar caused by open or short LEDs, which make the LP5890 a perfect choice in such
applications.
The LP5890 also implements LED open/weak short/short detections and removals during operations and can
also report this information to the accompanying digital processor.
8.2 Functional Block Diagram
VB VG VR
VCC
Internal LDO
Bandgap
TSD
Power Save
R0
G0
B0
UVLO
IREF
GND
3-Bits
Brightness control
R/G/B 8-Bits
Color control
Channel
Drivers
Channel
Control
R15
G15
Frequency
Multiplier
Frame
Control
Digital
Core
SCLK
SIN
B15
Line
Control
Pre-discharge
LED Short Detection
SRAM
Low Grayscale
Compensation
LED Open Detection
Line Drivers
SOUT
Line Clamp
GND
LINE0
LINE15
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8.3 Feature Description
8.3.1 Independent and Stackable Mode
The LP5890 can operate in two different modes: independent or stackable. In independent mode, a single
LP5890 can drive a 16 × 16 RGB LED matrix, while in stackable mode, up to three LP5890s can be stacked
together, which means the line switches of one device can be shared to another. Stacking two LP5890s can
drive a 32 × 32 RGB LED matrix while stacking three LP5890s can drive a 32 × 48 RGB matrix. The mode can
be configured by the MOD_SIZE (For more details, see FC0).
8.3.1.1 Independent Mode
图 8-1 shows an implementation of a 16 × 32 RGB LED matrix using two LP5890s in independent mode. Each
device is responsible for its own 16 × 16 RGB LED matrix which means that all the data for section A is stored in
Device1 and the data for section B is stored in Device2.
图8-1. Two Devices in Independent Mode
The unused line must be assigned to the last several lines of the device. For example, if there are only 14
scanning lines, then the two unused lines should be assigned to 1_LS14 and 1_LS15.
8.3.1.2 Stackable Mode
While operating the LP5890 in stackable mode, as shown in 图 8-2 and 图 8-3, Device2 needs to be rotated
180o relative to Device1. This action allows the position of line switches to be near the center column of the LED
matrix for better routing. For Device1, the lines will be connected sequentially (line switch 0 connected to scan
line 1). However, on Device2, it is connected in reverse order, with the 16th scan line is connected to line switch
15 and the 32th scan line is connected to line switch 0.
图8-2 shows the connection between two LP5890 devices in stackable mode driving a 32 × 32 RGB LED pixels.
The MOD_SIZE should be configured to 00b/10b. Device1 supplies 16 line switches for the first 16 scan line,
and Device2 supplies 16 line switches for scan line 17-32. The data for matrix sections A and C are stored in
Deivce1, while matrix sections B and D data are stored in Device2.
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Physical Line0
A
B
1_LS0
Device1
1_LS15
Physical Line15
Physical Line16
C
D
2_LS15
Device2
2_LS0
Physical Line31
图8-2. Two Devices in Stackable Mode
图 8-3 shows the connection between three devices connected in stackable mode with MOD_SIZE bits set to
11b. In this configuration, Device1 supplies the line switches for the first 16 scan lines, Device2 supplies line
switches for scan lines 17-32, and the line switches of Device3 are not used. Matrix A and D's data are stored in
Device 1, matrix B and E's data are stored in Device2, and matrix C and F's data are stored in Device3.
Physical Line0 A
C
B
1_LS0
Device1
Device3
1_LS15
Physical Line15
Physical Line16 D
E
2_LS15
F
Device2
2_LS0
Physical Line31
图8-3. Three Devices in Stackable Mode
In order to make sure the scanning sequence is still from 1st line to 32nd line, the scan line switching order of the
second device needs to be reversed. This action can be configured by the SCAN_REV (For more details, see
FC4).
表 8-1 shows the pin assignment between the LED matrix physical lines and the LP5890 corresponding pins,
depending on the SCAN_REV.
表8-1. Stackable With Different SCAN_REV Value
LED Matrix Physical Line
Device Line Switch Pin (SCAN_REV = 1)
Device Line Switch Pin (SCAN_REV = 0)
L0
L1
L2
L3
L4
L5
1_LS0
1_LS1
1_LS2
1_LS3
1_LS4
1_LS5
1_LS0
1_LS1
1_LS2
1_LS3
1_LS4
1_LS5
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表8-1. Stackable With Different SCAN_REV Value (continued)
LED Matrix Physical Line
Device Line Switch Pin (SCAN_REV = 1)
Device Line Switch Pin (SCAN_REV = 0)
L6
L7
1_LS6
1_LS7
1_LS8
1_LS9
1_LS10
1_LS11
1_LS12
1_LS13
1_LS14
1_LS15
2_LS15
2_LS14
2_LS13
2_LS12
2_LS11
2_LS10
2_LS9
2_LS8
2_LS7
2_LS6
2_LS5
2_LS4
2_LS3
2_LS2
2_LS1
2_LS0
1_LS6
1_LS7
1_LS8
1_LS9
1_LS10
1_LS11
1_LS12
1_LS13
1_LS14
1_LS15
2_LS0
2_LS1
2_LS2
2_LS3
2_LS4
2_LS5
2_LS6
2_LS7
2_LS8
2_LS9
2_LS10
2_LS11
2_LS12
2_LS13
2_LS14
2_LS15
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
L27
L28
L29
L30
L31
When the LP5890 devices are used in stackable mode, if there are unused line switches, these unused line
switches must be the last line switches of the first or the second device. For example, if there are only 30
scanning lines, and if,
The unused line switches must be 2_LS14, 2_LS15 if SCAN_REV = '0'b, or 2_LS1, 2_LS0 if SCAN_REV = '1'b.
8.3.2 Current Setting
8.3.2.1 Brightness Control (BC) Function
The LP5890 device is able to adjust the output current of all constant-current outputs simultaneously. This
function is called global brightness control (BC). The global BC for all outputs is programmed with a 3-bit
register, thus all output currents can be adjusted in 8 steps for a given current-programming resistor, RIREF
.
When the 3-bit BC register changes, the gain of output current, GAINBC changes as 表8-2 below.
表8-2. Current Gain Versus BC Code
BC Register (BC)
000b
Current Gain (GAINBC)
24.17
30.57
49.49
86.61
103.94
129.92
001b
010b
011b (default)
100b
101b
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表8-2. Current Gain Versus BC Code (continued)
BC Register (BC)
Current Gain (GAINBC
)
110b
111b
148.48
173.23
The maximum output current per channel, IOUTSET, is determined by resistor, RIREF, and the GAINBC. The
voltage on IREF is typically 0.8 V. RIREF can be calculated by 方程式 1 below. For noise immunity purpose,
suggest RIREF < 40 kΩ.
8
+4'((8)
8
+4'((8)
4+4'( (G×) =
=
× )#+0($%)
++4'( (I#)
+1765'6 (I#)
(1)
8.3.2.2 Color Brightness Control (CC) Function
The LP5890 device is able to adjust the output current of each of the three color groups R0-R15, G0-G15, and
B0-B15 separately. This function is called color brightness control (CC). For each color, it has 8-bit data register,
CC_R, CC_G, or CC_B. Thus, all color group output currents can be adjusted in 256 steps from 0% to 100% of
the maximum output current, IOUTSET. The output current of each color, IOUT_R (or G or B), can be calculated by
Equation 2 below.
1 + %%_4(KN %%_) KN %%_$)
+
= +1765'6 ×
176_4(KN ) KN $)
256
(2)
Table 表8-3 shows the CC data versus the constant-current against IOUTSET
:
表8-3. CC Data vs Current Ratio
CC Register (CC_R or CC_G or
Ratio of IOUTSET
CC_B)
0000 0000b
0000 0001b
...
1/256
2/256
...
0.39%
0.78%
...
0111 1111b (default)
...
128/256
...
50%
...
1111 1110b
1111 1111b
255/256
256/256
99.61%
100%
8.3.2.3 Choosing BC/CC for a Different Application
BC is mainly used for global brightness adjustment to adapt to ambient brightness, such as between day and
night, indoor and outdoor.
Suggested BC is 3h or 4h, which is in the middle of the range, allowing flexible changes in brightness up and
down.
• If the current of one color group (usually R LEDs) is close to the output maximum current (10 mA or 20 mA),
choose the maximum BC value, 7h, to prevent the constant output current from exceeding the upper limit in
case a larger BC code is input accidentally.
• If the current of one color group (usually B LEDs) is close to the output minimum current (0.2 mA), choose the
minimum BC code, 0h, to prevent the constant output current from exceeding the lower limit in case a lower
BC code is input accidentally.
The CC can be used to fine tune the brightness in 256 steps. The CC is suitable for white balance adjustment
between RGB color group. To get a pure white color, the general requirement for the luminous intensity ratio of
R, G, B LED is 5:3:2. Depending on the characteristics of the LED (Electro-Optical conversion efficiency), the
current ratio of R, G, B LED will be much different from this ratio. Usually, the Red LED needs the largest
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current. Choose 255d (the maximum value) CC code for the color group that needs the largest initial current,
then choose proper CC code for the other two color groups according to the current ratio requirement of the LED
used.
8.3.3 Frequency Multiplier
The LP5890 has an internal frequency multiplier to generate the GCLK by SCLK. The GCLK frequency can be
configured by FREQ_MOD (for more details, see FC0) and FREQ_MUL (for more details, see FC0) from 40
MHz to 160 MHz. As 图8-4 shows, if the GCLK frequency is not higher than 80 MHz, the GCLK_MOD is set to 0
to disable the bypass switch (enable the ½ divider), while the GCLK frequency is higher than 80 MHz, the
GCLK_MOD is set to 1 to enable the bypass switch (disable the ½ divider).
GCLK_MUL
GCLK_MOD
SCLK
GCLK
1/2
图8-4. Frequency Multiplier Block Diagram
8.3.4 Line Transitioning Sequence
The LP5890 defines a timing sequence of scan line transition. T_SW is the total transitioning time.
表 8-4 is the relation between LINE_SWT bits and the line switch time (GCLK numbers) with different internal
GCLK frequency.
表8-4. Line Switch Time
LINE_SW
T
GCLK
numbers
T_SW (us, 40
MHZ GCLK)
T_SW (us, 60 MHZ T_SW (us, 100 MHZ T_SW (us, 120 MHZ T_SW(us, 160 MHZ
GCLK)
0.7515
1.002
1.503
2.004
2.505
3.006
3.507
4.008
4.509
5.01
GCLK)
0.45
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
GCLK)
0.3735
0.498
0.747
0.996
1.245
1.494
1.743
1.992
2.241
2.49
GCLK)
0.2835
0.378
0.567
0.756
0.945
1.134
1.323
1.512
1.701
1.89
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
45
1.125
1.5
60
90
2.25
3
120
150
180
210
240
270
300
330
360
390
420
450
480
3.75
4.5
5.25
6
6.75
7.5
8.25
9
5.511
6.012
6.513
7.014
7.515
8.016
3.3
3.6
3.9
4.2
4.5
4.8
2.739
2.988
3.237
3.486
3.735
3.984
2.079
2.268
2.457
2.646
2.835
3.024
9.75
10.5
11.25
12
T0 is set by the LINE_SW_T0 (see FC4 for more details). T2 constantly equals to 5 GCLKs.
T1 and T3 can be calculated by LINE_TIMEMODE (see FC0 for more details).
8.3.5 Protections and Diagnostics
8.3.5.1 Thermal Shutdown Protection
The Thermal Shutdown (TSD) function turns off all IC constant-current outputs when the junction temperature
(TJ) exceeds 170°C (typical). Normal operation resumes when TJ falls below 155°C (typical).
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8.3.5.2 IREF Resistor Short Protection
The IREF resistor short protection (ISP) function prevents unwanted large currents from flowing though the
constant-current output when the IREF resistor is shorted accidentally. The LP5890 device turns off all output
channels when the IREF pin voltage is lower than 0.19 V (typical). When the IREF pin voltage goes higher than
0.325 V (typical), the LP5890 device resumes normal operation.
8.3.5.3 LED Open Load Detection and Removal
8.3.5.3.1 LED Open Detection
The LED Open Detection (LOD) function detects faults caused by an open circuit in any LED, or a short from
OUTn to VLED with low impedance. LOD was realized by comparing the OUTn voltage to the LOD detection
threshold voltage level set by LODVTH_R/LODVTH_G/LODVTH_B (see FC3 for more details). If the OUTn
voltage is higher than the programmed voltage, the corresponding output LOD bit is set to 1 to indicate an open
LED. Otherwise, the output of that LOD bit is 0. LOD data output by the detection circuit are valid only during the
OUTn turning on period.
图8-5 shows the equivalent circuit of LED open detection.
VG
VB
VR
VR
VG
VB
LODVTH_G
LODVTH_B
LODVTH_R
LODVTH_G
LODVTH_R
LODVTH_G
+
+
+
+
+
+
œ
œ
œ
œ
œ
œ
Channel
Control
Channel
Control
Channel
Control
Channel
Control
Channel
Control
Channel
Control
LOD Detection
0b - Normal
1b - LED-short
48-bit LOD Data
READLOD
48-bit
LSB
MSB
SCLK
SIN
48-bit Common Shift Register
SOUT
图8-5. LED Open Detection Circuit
The LED open detection function records the position of the open LED, which contains the scan line number and
relevant channel number. The scan line order is stored in LOD_LINE_WARN register (for more details see
FC12), and the channel number is latched into the internal 48-bit LOD data register for more details see FC14)
at the end of each segment. 图8-6 shows the bit arrangement of the LOD data register.
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LOD Data Register
LSB
LOD Bit0 LOD Bit1 LOD Bit2 LOD Bit3 LOD Bit4 LOD Bit5 LOD Bit6 LOD Bit7 LOD Bit8 LOD Bit9 LOD Bit10 LOD Bit11 LOD Bit12 LOD Bit13 LOD Bit14 LOD Bit15
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
LOD Bit16 LOD Bit17 LOD Bit18 LOD Bit19 LOD Bit20 LOD Bit21 LOD Bit22 LOD Bit23 LOD Bit24 LOD Bit25 LOD Bit26 LOD Bit27 LOD Bit28 LOD Bit29 LOD Bit30 LOD Bit31
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
MSB
LOD Bit32 LOD Bit33 LOD Bit34 LOD Bit35 LOD Bit36 LOD Bit37 LOD Bit38 LOD Bit39 LOD Bit40 LOD Bit41 LOD Bit42 LOD Bit43 LOD Bit44 LOD Bit45 LOD Bit46 LOD Bit47
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
图8-6. Bit Arrangement in LOD Data Register
8.3.5.3.2 Read LED Open Information
The LOD readback function needs to be enabled before read LED open information. This function is enabled by
LOD_LSD_RB (for more details, see FC3).
图 8-7 shows the steps to read LED open information. Wait at least one sub-period time between Step2 and
Step3 command.
图8-7. Steps to Read LED Open Information
8.3.5.3.3 LED Open Caterpillar Removal
图 8-8 shows the caterpillar issue caused by open LED. Suppose the LED0-1 is an open LED. When line0 is
chosen and the OUT1 is turned on, the OUT1 voltage will be forced to approach to VLED because of the broken
path of the current source. However, the voltage of the un-chosen lines are below the Vclamp which is much
lower than VLED, causing all LEDs which connect to the channel OUT1 light unwanted.
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图8-8. LED Open Caterpillar
The LP5890 implements circuits that can eliminate the caterpillar issue caused by open LEDs. The LED open
caterpillar removal function is configured by LODRM_EN (fore more details, see FC0). When LODRM_EN is set
to 1b, the caterpillar removal function is enabled. The corresponding channel OUTn is turned off when scanning
to line with open LED. The caterpillar issue is eliminated until device resets or LODRM_EN is set to 0b.
The internal caterpillar elimination circuit can handle a maximum of three lines that have open LEDs fault
condition. If there are open LEDs located in three or fewer lines, the LP5890 is able to handle the open LEDs all
in these lines. If there are open LEDs in more than three lines, the caterpillar issue is solved for the lines where
the first three open LEDs were detected, but the open LEDs in the fourth and subsequent lines still cause the
caterpillar issue.
8.3.5.4 LED Short and Weak Short Circuitry Detection and Removal
8.3.5.4.1 LED Short and Weak Short Detection
The LED Short Detection (LSD) function detects faults caused by a short circuit in any LED. LSD was realized by
comparing the OUTn voltage to the LSD threshold voltage. If the OUTn voltage is lower than the threshold
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voltage, the corresponding output LSD bit is set to 1 to indicate an short LED, otherwise, the output of that LSD
bit is 0. LSD data output by the detection circuit are valid only during the OUTn turning on period.
LSD weak short can be detected by adjusting threshold voltage, which level is set by LSDVTH_R/LSDVTH_G/
LSDVTH_B (for more details, see FC3).
图8-9 shows the equivalent circuit of LED short detection.
VG
VB
VR
VR
VG
VB
LSDVTH_G
LSDVTH_B
LSDVTH_R
LSDVTH_G
LSDVTH_R
LSDVTH_G
+
+
+
+
+
+
œ
œ
œ
œ
œ
œ
Channel
Control
Channel
Control
Channel
Control
Channel
Control
Channel
Control
Channel
Control
LSD Detection
0b - Normal
1b - LED-short
48-bit LSD Data
READLSD
48-bit
LSB
MSB
SCLK
SIN
48-bit Common Shift Register
SOUT
图8-9. LED Short Detection Circuit
The LED short detection function records the position of the short LED, which contains the scan line order and
relevant channel number. The scan line order is stored LSD_LINE_WARN register (for more details, see FC13),
and the channel number is latched into the internal 48-bit LSD data register (fore more details see FC15) at the
end of each segment. 图8-10 shows the bit arrangement of the LSD data register.
LSD Data Register
LSB
LSD Bit0
R0
LSD Bit1
R1
LSD Bit2
R2
LSD Bit3
R3
LSD Bit4
R4
LSD Bit5
R5
LSD Bit6
R6
LSD Bit7
R7
LSD Bit8
R8
LSD Bit9 LSD Bit10 LSD Bit11 LSD Bit12 LSD Bit13 LSD Bit14 LSD Bit15
R9
R10
R11
R12
R13
R14
R15
LSD Bit16 LSD Bit17 LSD Bit18 LSD Bit19 LSD Bit20 LSD Bit21 LSD Bit22 LSD Bit23 LSD Bit24 LSD Bit25 LSD Bit26 LSD Bit27 LSD Bit28 LSD Bit29 LSD Bit30 LSD Bit31
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
MSB
LSD Bit32 LSD Bit33 LSD Bit34 LSD Bit35 LSD Bit36 LSD Bit37 LSD Bit38 LSD Bit39 LSD Bit40 LSD Bit41 LSD Bit42 LSD Bit43 LSD Bit44 LSD Bit45 LSD Bit46 LSD Bit47
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
图8-10. Bit Arrangement in the LSD Data Register
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8.3.5.4.2 Read LED Short Information
The LSD readback function needs to be enabled before reading LED Short information. This function is enabled
by LOD_LSD_RB (see FC3 for more details).
图 8-11 shows the steps to read LED Short information. Wait at least one sub-period time between Step2 and
Step3 command.
图8-11. Steps to Read LED Short Information
8.3.5.4.3 LSD Caterpillar Removal
图 8-12 shows the LSD caterpillar issue caused by short LED. Suppose the LED0-1 is a short LED. When it
scans to the line1 and the OUT1 is turned off, the OUT1 voltage is the same with scan line0 voltage because of
the short path of the LED0-1. At this time, there is a current path from the line0 to the GND through the LED1-1
and SW1-1, which causes LED1-1 light to be unwanted.
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图8-12. LED Short Caterpillar
The LP5890 device implements internal circuits that can eliminate the caterpillar issue by short LEDs. As is
shown in 图 8-12, the LED short caterpillar is caused by the voltage of the Vclamp on the line, so it can be
solved by adjusting the LSD_RM (see FC3 for more details) to let the voltage drop of the LED1-1 be smaller than
LED forward voltage.
8.4 Device Functional Modes
图8-13 lists the device functional modes.
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Vcc Power Up
Initialization
UVLO
From all states
ISPin
ISPout
IREF Resistor Short
Thermal Shutdown
PSin
Power Saving
Normal
PSout
TSDin
TSDout
图8-13. Functional Modes
• Initialization: The device enters into Initialization when Vcc goes down to UVLO voltage. In this mode, all the
registers are reset. Entry can also be from any state.
• Normal: The device enters the normal mode when Vcc is higher than UVLO threshold. The display process
is shown as below in normal mode.
• Power Saving: The device automatically enters and gets out from the power save mode when it detects the
condition PSin and PSout. In this mode, all channels will turn off. PSin: after the device detects that the
display data of the next frame all equal to zero, it will enter to power save mode when the VSYNC comes.
PSout: after the device detects that there is non-zero display data of the next frame, it will get out from power
save mode immediately.
• IREF Resistor Short Protection: The device automatically enters and gets out from the IREF Resistor Short
Protection mode when it detects the condition ISPin and ISPout. In this mode, all channels will turn off. ISPin:
the device detects that the reference voltage is smaller than 0.195 V. ISPout: the device detects that the
reference voltage is larger than 0.325 V.
• Thermal Shutdown: The device automatically enters and gets out from the Thermal Shutdown mode when it
detects the condition TSDin and TSDout. In this mode, all channels will turn off. TSDin: the device detects
that the junction temperature exceeds 170° C. TSDout: the device detects that the junction temperature is
below 155° C.
8.5 Continuous Clock Series Interface
The continuous Clock Series Interface (CCSI) provides access to the programmable functions and registers,
SRAM data of the device. The interface contains two input digital pins. The pins are the serial data input (SIN)
and serial clock (SCLK). Moreover, there is an another wire called serial data output (SOUT) as the output digital
signal of the device. The SIN is set to HIGH when device is in idle status and the SCLK needs to be existent and
continuous all the time considering it is the clock source of internal Frequency Multiplier. The SOUT is used to
transmit the data or read the data of internal registers.
This protocol can support up to 32 devices cascaded in a data chain. The devices will receive the chip index
command after power up. The chip index command will configure addresses of the devices from 0x00 up to
0x1F according to the sequence that receives the command. Then the controller can communicate with all the
devices through the broadcast way or particular device through non-broadcast way.
The broadcast is mainly used to transmit function control commands. All the devices in a data chain will receive
the same data in this way. The non-broadcast is mainly used to transmit function control commands or display
data, and each device receives its own data in this way. These two ways are distinguished by the command
identification.
8.5.1 Data Validity
The data on DIN wire must be stable at rising edges of the SCLK.
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8.5.2 CCSI Frame Format
图8-14 defines the format of the command and data transimission. There are four states in one frame.
• IDLE: SCLK is always existent and continuous, and DIN is always HIGH.
• START: DIN changes from HIGH to LOW after the IDLE states.
• DATA:
– Head_bytes: It is the command identifier, contains one 16-bit data and one check bit. It can be WRITE
COMMAND ID or READ COMMAND ID (see Register Maps for more details).
– Data_bytes_N: The Nth data-bytes, contains 3 × 17-bit data, each 17-bit data contains one 16-bit data
and one check bit. N is the number of devices cascaded in a data chain.
• END: The device recognizes continuous 18-bit HIGH on DIN, then returns to IDLE state.
• CHECK BIT: The check bit (17th bit) value is the NOT of 16th bit value, in order to avoid continuous 18-bit
HIGH (to distinguish with END).
SCLK
SIN
Y...
Head_bytes
Data_bytes_N
Data_bytes_1
End_bytes
IDLE START
DATA
END
IDLE
图8-14. CCSI Frame
The IDLE state is not the necessary. That means the START state of next frame can connect to the END state of
current frame.
8.5.3 Write Command
Take m devices cascaded in a data chain for example.
8.5.3.1 Chip Index Write Command
The chip index is used to set the identification of the device cascaded in a data chain. When the first device
receives the chip index command, Head_bytes1, it sets the current address to 00h and meanwhile changes the
chip index command, Head_bytes2, then sends to the next device. When the device receives the Head_bytes2,
it sets the address to 01h and meanwhile changes the chip index command, Head_bytes3, then sends to the
next device. Likewise, all the cascaded devices get their unique identifications.
SOUT
SCLK
Controller
SIN
Device_1
Device_...
Device_m
ST Head_bytes1
END
ST Head_bytes...
END
ST Head_bytesm
END
图8-15. Chip Index Write Command
8.5.3.2 VSYNC Write Command
The VSYNC is used to sync the display of each frame for the devices in a cascaded chain. The VSYNC is a
write-only command. The devices receive VSYNC command one time from the controller in each frame, and the
VSYNC command needs to be active for all devices at the same time.
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Since some devices receive the command earlier in the data chain, they need to wait until the last device
receives the command, then all the devices are active at that time. In order to realize such function, each device
needs to know its delay time from receiving VSYNC command to enabling VSYNC. The device uses some
register bits to restore the device number in a data chain. This number will minus the device identification, and
the result is the delay time of the device.
Since the sync function has been done by the device, the controller only needs to send the VSYNC command to
the first device in a data chain.
SOUT
SCLK
Controller
SIN
Device_1
Device_...
Device_m
ST Head_bytes
END
ST Head_bytes
END
ST Head_bytes
END
ST Head_bytes
END
图8-16. VSYNC Write Command
8.5.3.3 Soft_Reset Command
The Soft_Reset Command is used to reset all the function registers to the default value, except for SRAM data.
The format of this command is the same with VSYNC shown as VSYNC Write Command. The difference is the
headbytes.
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8.5.3.4 Data Write Command
The device implements two kinds of transmission formats, which are called broadcast and non-broadcast. With
broadcast way, the devices which are cascaded in a data chain receive the same data from the controller as
Data Write Command with Broadcast shows. With non-broadcast way, each device will receive its own data sent
from controller. The order of the data is the reverse of the order in which the device cascades as shown in Data
Write Command with Non-Broadcast.
For 48-bits RGB data, the Blue data is the first to be transmitted, then are the Green and the Red. Also, for all
bits in one frame, it is always the MSB transmitted first and the LSB transmitted last.
Here is the data write command with broadcast way. The devices copy to the internal registers after receiving the
data. Generally, it is used to write FC0-FC11 command and read LOD/LSD command.
SOUT
SCLK
Controller
SIN
Device_1
Device_...
Device_m
ST Head_bytes
Data
END
ST Head_bytes
Data
END
ST Head_bytes
Data
ST Head_bytes
END
Data
END
图8-17. Data Write Command With Broadcast
图8-18 shows the timing diagram of the data write command with broadcast.
图8-18. Data Write Command With Broadcast (Timing Diagram)
Here is the data write command with non-broadcast way. When the first device recognizes End_bytes, it cuts off
the last 51-bit (3×17-bit) data before End_bytes, and the left are shifted out from SOUT to the second device;
likewise, when the last device recognizes End_bytes from the former device, it cuts off the last 51-bit (3 × 17-bit)
data before End_bytes and the left are shifted out from SOUT. Generally, it is used for write SRAM command
(WRTGS), details about how to write a frame data into memory bank can be found in Write a Frame Data into
Memory Book.
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SOUT
SCLK
SIN
Controller
Device_1
Device_...
Device_m
Data_...
Data_m
ST Head_bytes
ST Head_bytes
Data_m
Data_1
Data_...
Data_m
ST Head_bytes
图8-19. Data Write Command With Non-Broadcast
END
ST Head_bytes
END
END
END
图8-20 shows the timing diagram of the Data Write Command with Non-Broadcast.
图8-20. Data Write Command with Non-Broadcast (Timing Diagram)
8.5.4 Read Command
The controller sends the read command. When the first device receives this command, it inserts its 48-bit data
before End_bytes, and meanwhile shifts out to the second device. When the second device receives this
command, it inserts its 48-bit data before End_bytes and meanwhile shifts out to the third device. The data of all
the device will be shifted out from the last device SOUT with this flow. The MSB is always transmitted first and
the LSB is transmitted last.
SOUT
SCLK
Controller
SIN
Device_1
Device_...
Device_m
ST Head_bytes
END
ST Head_bytes
Data_1
END
Data_1
ST Head_bytes
ST Head_bytes
Data_...
Data_1
END
Data_...
Data_m
END
图8-21. Data Read Command
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8.6 PWM Grayscale Control
8.6.1 Grayscale Data Storage and Display
8.6.1.1 Memory Structure Overview
The LP5890 implements a display memory unit to achieve high refresh rate and high contrast ratio in LED
display products. The internal display memory unit is divided into two BANKs: BANK A and BANK B. During the
normal operation, one BANK is selected to display the data of current frame, another is used to restore the data
of next frame. The BANK switcher is controlled by the BANK_SEL bit, which is an internal flag register bit.
After power on, BANK_SEL is initialized to 0, and BANK A is selected to restore the data of next frame.
Meanwhile, the data in BANK B is read out for display. When one frame has elapsed, the controller sends the
vertical synchronization (VSYNC) command to start the next frame. The BANK_SEL bit value is toggled and the
selection of the two BANKs reverses. Repeat this operation until all the frame images are displayed.
With this method, the LP5890 device can display the current frame image at a very high refresh rate. See 图
8-22 for more details about the BANK-selection exchange operation.
R0-R15/G0-G15/B0-B15
R0-R15/G0-G15/B0-B15
PWM Generator
Timing Control
PWM Generator
Timing Control
48-bit
48-bit
Memory
BANK A
Memory
BANK B
Memory
BANK A
Memory
BANK B
BANK_SEL=0
BANK_SEL=1
Write Grayscale Data
for Next Frame
Read Grayscale Data for
Current Frame
Read Grayscale Data for
Current Frame
Write Grayscale Data
for Next Frame
VSYNC
VSYNC
48-bit
MSB
48-bit
MSB
LSB
LSB
SIN
SIN
Common Shift Register
SOUT
Common Shift Register
SOUT
SCLK
SCLK
Select BANK A
Select BANK B
图8-22. Bank Selection Exchange Operation
8.6.1.2 Details of Memory Bank
Each memory BANK contains the frame-image grayscale data of all the 32 lines. Each line comprises sixteen
48-bit-width memory units. Each memory unit contains the grayscale data of the corresponding R/G/B channels.
Depending on the number of scan lines set in SCAN_NUM (FC0 bit 20 to bit 16), the total number of memory
units that must be written in one BANK is: 48 × the number of scan lines. For example, if the number of scan
lines is set to 32, then 1536 (32 × 48 = 1536) memory units must be written during each frame period.
图8-23 shows the detailed memory structure of the LP5890 device.
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LSB
MSB
SIN
Common Shift Register
SOUT
SCLK
48-bit
Memory Units
CHANNEL_COUNT
R
Bit2
G
B
LINE_COUNT
R0/G0/B0
R1/G1/B1
Bit0
Bit0
...
Bit1
Bit1
Bit15 Bit16 Bit17 Bit18
Bit31 Bit32 Bit33 Bit34
Bit47
Bit47
...
...
...
...
...
...
...
...
...
Bit2
Bit15 Bit16 Bit17 Bit18
Bit31 Bit32 Bit33 Bit34
Line0
Bit0
Bit1
Bit2
Bit15 Bit16 Bit17 Bit18
Bit31 Bit32 Bit33 Bit34
Bit47
...
...
...
R15/G15/B15
BANK_SEL
Bit0
Bit0
...
Bit1
Bit1
Bit2
Bit2
Bit15 Bit16 Bit17 Bit18
Bit15 Bit16 Bit17 Bit18
Bit31 Bit32 Bit33 Bit34
Bit31 Bit32 Bit33 Bit34
Bit47 R0/G0/B0
Bit47 R1/G1/B1
...
...
...
...
...
...
...
...
...
...
...
...
Line1
...
BANK A
Bit0
Bit1
Bit2
Bit15 Bit16 Bit17 Bit18
Bit31 Bit32 Bit33 Bit34
Bit47
R15/G15/B15
...
...
...
...
...
R0/G0/B0
R1/G1/B1
Bit0
Bit0
...
Bit1
Bit1
Bit2
Bit2
Bit15 Bit16 Bit17 Bit18
Bit15 Bit16 Bit17 Bit18
Bit31 Bit32 Bit33 Bit34
Bit31 Bit32 Bit33 Bit34
Bit47
Bit47
...
...
...
...
...
...
...
...
...
Line31
Bit0
Bit1
Bit2
Bit15 Bit16 Bit17 Bit18
Bit31 Bit32 Bit33 Bit34
Bit47
...
...
...
R15/G15/B15
Bit0
Bit0
...
Bit1
Bit1
Bit2
Bit2
Bit15 Bit16 Bit17 Bit18
Bit15 Bit16 Bit17 Bit18
Bit31 Bit32 Bit33 Bit34
Bit31 Bit32 Bit33 Bit34
Bit47 R0/G0/B0
Bit47 R1/G1/B1
...
...
...
...
...
...
...
...
...
...
...
...
Line0
Bit0
Bit1
Bit2
Bit15 Bit16 Bit17 Bit18
Bit31 Bit32 Bit33 Bit34
Bit47
R15/G15/B15
Bit0
Bit0
...
Bit1
Bit1
Bit2
Bit2
Bit15 Bit16 Bit17 Bit18
Bit15 Bit16 Bit17 Bit18
Bit31 Bit32 Bit33 Bit34
Bit31 Bit32 Bit33 Bit34
Bit47 R0/G0/B0
Bit47 R1/G1/B1
...
...
...
...
...
...
...
...
...
...
...
...
BANK B
Line1
...
Bit0
Bit1
Bit2
Bit15 Bit16 Bit17 Bit18
Bit31 Bit32 Bit33 Bit34
Bit47
R15/G15/B15
...
...
...
...
...
Bit0
Bit0
...
Bit1
Bit1
Bit2
Bit2
Bit15 Bit16 Bit17 Bit18
Bit15 Bit16 Bit17 Bit18
Bit31 Bit32 Bit33 Bit34
Bit31 Bit32 Bit33 Bit34
Bit47 R0/G0/B0
Bit47 R1/G1/B1
...
...
...
...
...
...
...
...
...
...
...
...
Line31
Bit0
Bit1
Bit2
Bit15 Bit16 Bit17 Bit18
Bit31 Bit32 Bit33 Bit34
Bit47
R15/G15/B15
图8-23. LP5890 Memory-unit Structure
8.6.1.3 Write a Frame Data into Memory Bank
After power on, the LP5890 internal flag BANK_SEL, and counters LINE_COUNT, CHANNEL_COUNT, are all
initialized to 0. Thus, the memory unit of channel R0/G0/B0, locating in line 0 of BANK A, is selected to restore
the data transimitted the first time after VSYNC command.
When the first WRTGS command is received, all the data in the common shift register is latched into the memory
unit of channel R0/G0/B0, locating in line 0 of BANK A. Then CHANNEL_COUNT increases by 1 and
LINE_COUNT stays the same. Thus, the memory unit of channel R1/G1/B1, locating in line 0 of BANK A, is
selected to restore the data transimitted the second time after VSYNC command.
When the second WRTGS command is received, all the data in the common shift register is latched into the
memory unit of channel R1/G1/B1, locating in line 0 of BANK A. Then CHANNEL_COUNT increases by 1 and
LINE_COUNT stays the same. Thus, the memory unit of channel R2/G2/B2, locating in line 0 of BANK A, is
selected to restore the data transimitted the third time after VSYNC command.
Repeat the grayscale-data-write operation until the 16th WRTGS command is received. Then
CHANNEL_COUNT is reset to 0 and LINE_COUNT increases by 1. Thus, the memory unit of channel
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R0/G0/B0, locating in line 1 of BANK A, is selected to restore the data transimitted the 17th time after VSYNC
command.
Repeat this operation for each line until the LINE_COUNT exceeds the number of scan lines set in the
SCAN_NUM (See FC0 register bit20-16 ) and all scan lines have been updated with new GS data, which means
one frame of GS data is restored into the memory BANK. Then the LINE_COUNT is reset to 0.
8.6.2 PWM Control for Display
In order to increase the refreash rate in time-multiplexing display system, an DS-PWM (Dynamic Spectrum-
Pulse Width Modulation) algorithm is proposed in this device. One frame is divided into many segments shown
as below. Note that one frame is divided into n sub-periods, n is set by SUBP_NUM (FC0 register bit23-21), and
each sub-period is divided into 32 segments for 32 scan lines. Each segment contains GS GCLKs time for
grayscale data display and T_SW GCLKs time for switching lines. GS is configured by the SEG_LENGTH (FC1
register bit9-0 in 表 8-8), and T_SW is the line switch time, which is configured by the LINE_SWT (see FC1
register bit 40-37 in 表8-8).
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Frame (display period)
SP1
Sub-period
SP0
SPn-1
ꢀꢀ
ꢀꢀ
Segment
SP0_L0
SP0_L1
SP0_L31
SP1_L0
SP1_L1
SP1_L31
SPn-1_L0
SPn-1_L1
SPn-1_L31
ꢀ
ꢀ
ꢀ
Grayscale data display (GS × GCLK)
Line switch (T_SW × GCLK)
Note that, SP0: Sub-period 0, L0: Scan line 0
图8-24. DS-PWM Algorithm with 32 Scan Lines
The DS-PWM can not only increse the refresh rate meanwhile keep the same frame rate, but also decrease the
brightness loss in low grayscale, which can smoothly increase the sub-period number when the grayscale data
increases.
In order to achieve ultra-low luminance, the LED driver should have the ability to output a very short current
pulse (1 GCLK time), however, because of the parasitic capacitor of the LEDs, such pulse could not turn on the
LEDs. And the larger GCLK frequency is, the harder to turn on LEDs.
DS-PWM algorithm has a parameter called subperiod threshold, which is used to calculate when to change
subperiod number according to the giving grayscale data. Subperiod threshold defines the LED minimum turn-on
time, so as to conquer the current loss caused by LED parasitic capacitor. Subperiod threshold is configured by
the SUBP_TH_R/G/B (FC1 register bit24-10 in 表8-8).
With DS-PWM algorithm, the brightness has smoothly increased with the gradient grayscale data.
8.7 Register Maps
表8-5. Register Maps
WRITE COMMAND READ COMMAND
REGISTER NAME
TYPE
DESCRIPTION
ID
ID
FC0
FC1
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
R
AA00h
AA01h
AA02h
AA03h
AA04h
AA0Ah
AA0Bh
AA60h
AA61h
AA62h
AA63h
AA64h
AA6Ah
AA6Bh
AA6Ch
AA6Dh
AA6Eh
AA6Fh
AA70h
Common configuration
Common configuration
FC2
Common configuration
FC3
Common configuration
FC4
Common configuration
FC10
FC11
FC12
FC13
FC14
FC15
Chip Index
VSYNC
Locate the line for LOD
Locate the line for LSD
Read the lines' warning of LOD
Read the lines' warning of LSD
Read the channel's warning of LOD
Read the channel's warning of LSD
Read/Write chip index
R
R
R
R/ W
W
AA10h
AAF0h
Write VSYNC command
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表8-5. Register Maps (continued)
WRITE COMMAND READ COMMAND
REGISTER NAME
TYPE
DESCRIPTION
ID
ID
Soft_Reset
SRAM
W
W
AA80h
AA30h
Reset the all the registers expect the SRAM
Write or read the SRAM data
表8-6. Access Type Codes
Access Type
Code
Description
Read Type
R
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
8.7.1 FC0
FC0 is shown in FC0 Register and described in FC0 Register Field Descriptions.
图8-25. FC0 Register
47
46
45
44
43
27
42
GRP_DLY_B
R/W-000b
26
41
40
39
GRP_DLY_G
R/W-000b
23
38
37
21
36
GRP_DLY_R
R/W-000b
20
35
19
34
33
32
16
MOD_SIZE
R/W-00b
RESERVED
R-01b
RESERVED
R-0b
18
R/W-00b
31
30
29
28
25
24
22
17
FREQ_MUL
FREQ_
MOD
RESERVED
SUBP_NUM
SCAN_NUM
R/W-0111b
R/
R-000b
R/W-000b
R/W-01111b
W-0b
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LODR
M_EN
PSP_MOD
PS_EN
RESERVED
PDC_E
N
RESERVED
CHIP_NUM
R/
R/W-00b
R/
R-000b
R/
R-000b
R/W-00111b
W-0b
W-0b
W-1b
表8-7. FC0 Register Field Descriptions
Bit
Field
Type
Reset
Description
4-0
CHIP_NUM
R/W
00111b
Set the device number
00000b: 1 device
...
01111b: 16 devices
...
11111b: 32 devices
7-5
8
RESERVED
PDC_EN
R
000b
1b
R/W
Enable or disable pre-discharge function
0b: disable
1b: enable
11-9
12
RESERVED
PS_EN
R
000b
0b
R/W
Enable or disable the power saving mode
0b: disable
1b: enable
14-13
PSP_MOD
R/W
00b
Set the powering saving plus mode
00b: disable
01b: save power at high level
10b: save power at middle level
11b: save power at low level
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表8-7. FC0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
15
LODRM_EN
R/W
0b
Enable or disable the LED open load removal function
0b: disable
1b: enable
20-16
23-21
SCAN_NUM
SUBP_NUM
R/W
R/W
01111b
000b
Set the scan line number
00000b: 1 line
...
01111b: 16 lines
...
11111b: 32 lines
Set the subperiod number
000b: 16
001b: 32
010b: 48
011b: 64
100b: 80
101b: 96
110b: 112
111b: 128
26-24
27
RESERVED
FREQ_MOD
R
000b
0b
R/W
Set the GCLK multiplier mode
0b: low frequency mode, 40MHz to 80MHz
1b: high frequency mode, 80MHz to 160MHz
31-28
FREQ_MUL
R/W
0111b
Set the GCLK multiplier frequency
0000b: 1 x SCLK frequency
...
0111b: 8 x SCLK frequency
...
1111b: 16 x SCLK frequency
34-32
37-35
RESERVED
GRP_DLY_R
R
000b
000b
R/W
Set the Red group delay, forward PWM mode only
000b: no delay
001b: 1 GCLK
010b: 2 GCLK
011b: 3 GCLK
100b: 4 GCLK
101b: 5 GCLK
110b: 6 GCLK
111b: 7 GCLK
40-38
43-41
45-44
GRP_DLY_G
GRP_DLY_B
RESERVED
R/W
R/W
R
000b
000b
01b
Set the Green group delay, forward PWM mode only
000b: no delay
001b: 1 GCLK
010b: 2 GCLK
011b: 3 GCLK
100b: 4 GCLK
101b: 5 GCLK
110b: 6 GCLK
111b: 7 GCLK
Set the Blue group delay, forward PWM mode only
000b: no delay
001b: 1 GCLK
010b: 2 GCLK
011b: 3 GCLK
100b: 4 GCLK
101b: 5 GCLK
110b: 6 GCLK
111b: 7 GCLK
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表8-7. FC0 Register Field Descriptions (continued)
Bit
Field
MOD_SIZE
Type
Reset
Description
47-46
R/W
00b
Set the module size
00b: 2 devices stackable operation
01b: 1 device non-stackable operation, SCAN_NUM must <=16
10b: 2 devices stackable operation
11b: 3 devices stackable operation
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8.7.2 FC1
FC1 is shown in FC1 Register and described in FC1 Register Field Descriptions.
图8-26. FC1 Register
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
32
RESE
RVED
BLK_ADJ
LINE_SWT
LG_ENH_B
LG_EN
H_G
R-0b
31
R/W-000000b
R/W-0111b
R/W-0000b
30
29
13
28
27
26
25
9
24
8
23
7
22
21
5
20
4
19
3
18
16
0
LG_ENH_G
R/W-0000b
14
LG_ENH_R
R/W-0000b
LG_STEP_B
R/W-01001b
6
LG_STEP_G
R/W-01001b
15
12
11
10
2
1
LG_ST
EP_G
LG_STEP_R
SEG_LENGTH
R/W-01001b
R/W-0'000'000'000b
表8-8. FC1 Register Field Descriptions
Bit
Field
Type
Reset
Description
9-0
SEG_LENGTH
LG_STEP_R
R/W
0'000'000'0 Set the GCLK number in each segment
00b
127d: 128 GCLK
...
1023d: 1024 GCLK
others: 128 GCLK
14-10
19-15
24-20
28-25
32-29
36-33
R/W
R/W
R/W
R/W
R/W
R/W
01001b
Adjust the smooth of the brightness in low grayscale
00000b: level 1
...
01111b: level 16
...
11111b: level 32
LG_STEP_G
LG_STEP_B
LG_ENH_R
LG_ENH_G
LG_ENH_B
01001b
01001b
0000b
0000b
0000b
Adjust the smooth of the brightness in low grayscale
00000b: level 1
...
01111b: level 16
...
11111b: level 32
Adjust the smooth of the brightness in low grayscale
00000b: level 1
...
01111b: level 16
...
11111b: level 32
Adjust low grayscale enhancement of red channels
0000b: level 0
...
0111b: level 7
...
1111b: level 15
Adjust low grayscale enhancement of green channels
0000b: level 0
...
0111b: level 7
...
1111b: level 15
Adjust low grayscale enhancement of blue channels
0000b: level 0
...
0111b: level 7
...
1111b: level 15
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表8-8. FC1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
40-37
LINE_SWT
R/W
0111b
Set the scan line switch time.
0000b: 45 GCLK
0001b: 2x30 GCLK
...
0111b: 8x30 GCLK
...
1111b: 16x30 GCLK
46-41
BLK_ADJ
R/W
000000b
Set the black field adjustment
000000b: 0 GCLK
...
011111b: 31 GCLK
...
111111b: 63 GCLK
47
RESERVED
R
0b
Reserved bit.
8.7.3 FC2
FC2 is shown in FC2 Register and described in FC2 Register Field Descriptions.
图8-27. FC2 Register
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
RESERVED
SUBP_ CH_B_ CH_G_ CH_R_
MAX_2 IMMU IMMU IMMU
RESERVED
LG_COLOR_B
56
NITY
NITY
NITY
R-000000b
29
R/
W-0b
R-111000b
R/W-0000b
31
15
30
28
12
27
11
26
25
24
23
7
22
21
20
4
19
3
18
17
16
0
LG_COLOR_G
R/W-0000b
LG_COLOR_R
R/W-0000b
DE_COUPLE1_B
R/W-0000b
DE_COUPLE1_G
R/W-0000b
14
13
10
9
8
6
5
2
1
DE_COUPLE1_R
R/W-0000b
V_PDC_B
R/W-0110b
V_PDC_G
R/W-0110b
V_PDC_R
R/W-0110b
表8-9. FC2 Register Field Descriptions
Bit
3-0
Field
Type
Reset
Description
V_PDC_R
R/W
0110b
Set the Red pre_discharge voltage, the voltage value must not
be higher than (VR-1.3V).
0000b: 0.1V
0001b: 0.2V
0010b: 0.3V
0011b: 0.4V
0100b: 0.5V
0101b: 0.6V
0110b: 0.7V
0111b: 0.8V
1000b: 0.9V
1001b: 1.0V
1010b: 1.1V
1011b: 1.3V
1100b: 1.5V
1101b: 1.7V
1110b: 1.9V
1111b: 2.1V
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表8-9. FC2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
7-4
V_PDC_G
R/W
0110b
Set the Green pre_discharge voltage, the voltage value must not
be higher than (VG-1.3V).
0000b: 0.1V
0001b: 0.2V
0010b: 0.3V
0011b: 0.4V
0100b: 0.5V
0101b: 0.6V
0110b: 0.7V
0111b: 0.8V
1000b: 0.9V
1001b: 1.0V
1010b: 1.1V
1011b: 1.3V
1100b: 1.5V
1101b: 1.7V
1110b: 1.9V
1111b: 2.1V
11-8
V_PDC_B
R/W
0110b
Set the Blue pre_discharge voltage, the voltage value must not
be higher than (VB-1.3V).
0000b: 0.1V
0001b: 0.2V
0010b: 0.3V
0011b: 0.4V
0100b: 0.5V
0101b: 0.6V
0110b: 0.7V
0111b: 0.8V
1000b: 0.9V
1001b: 1.0V
1010b: 1.1V
1011b: 1.3V
1100b: 1.5V
1101b: 1.7V
1110b: 1.9V
1111b: 2.1V
15-12
19-16
23-20
27-24
DE_COUPLE1_R
DE_COUPLE1_G
DE_COUPLE1_B
LG_COLOR_R
R/W
R/W
R/W
R/W
0000b
0000b
0000b
0000b
Set the Red decoupling level
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
Set the Green decoupling level
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
Set the Blue decoupling level
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
Set the Red brightness compensation level of the low grayscale
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
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表8-9. FC2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
31-28
LG_COLOR_G
R/W
0000b
Set the Red brightness compensation level of the low grayscale
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
35-32
LG_COLOR_B
R/W
0000b
Set the Red brightness compensation level of the low grayscale
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
38-36
39
RESERVED
R
111000b
1b
CH_R_IMMUNITY
R/W
Set the immunity of the Red channels group
0b: high immunity
1b: low immunity
40
41
42
CH_G_IMMUNITY
CH_B_IMMUNITY
SUBP_MAX_256
RESERVED
R/W
R/W
R/W
R
1b
Set the immunity of the Green channels group
0b: high immunity
1b: low immunity
1b
Set the immunity of the Blue channels group
0b: high immunity
1b: low immunity
0b
Set the maximum subperiod to 256.
0b: disable
1b: enable
47-43
00000b
8.7.4 FC3
FC3 is shown in FC3 Register and described in FC3 Register Field Descriptions.
图8-28. FC3 Register
47
31
15
46
45
29
13
44
28
43
LSDVTH_G
R/W-000b
27
42
26
10
41
25
9
40
39
23
7
38
22
6
37
LSD_RM
R/W-0111b
36
35
19
34
18
2
33
BC
32
16
0
LSDVTH_B
R/W-000b
30
LSDVTH_R
R/W-000b
24
R/W-011b
17
21
20
CC_B
CC_G
R/W-0111 1111b
R/W-0111 1111b
12 11
14
8
5
4
3
1
CC_R
R/W-0111 1111b
RESERVED
R-00000000b
表8-10. FC3 Register Field Descriptions
Bit
7-0
15-8
Field
Type
Reset
Description
RESERVED
CC_R
R
0000 0000b
R/W
0111 1111b Set the Red color brightness level
0000 0000b: level 0 (lowest)
...
0111 1111b: level 127 (middle)
...
1111 1111b: level 255 (highest)
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表8-10. FC3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
23-16
CC_G
R/W
0111 1111b Set the Green color brightness level
0000 0000b: level 0 (lowest)
...
0111 1111b: level 127 (middle)
...
1111 1111b: level 255 (highest)
31-24
34-32
38-35
CC_B
R/W
R/W
R/W
0111 1111b Set the Blue color brightness level
0000 0000b: level 0 (lowest)
...
0111 1111b: level 127 (middle)
...
1111 1111b: level 255 (highest)
BC
011b
Set the global brightness level
000b: level 0 (lowest)
...
011b: level 3 (middle)
...
111b: level 7 (highest)
LSD_RM
0111b
Set the LED short removal level
0000b: level 1
0001b: level 2
0010b: level 3
0011b: level 4
0100b: level 5
0101b: level 6
0110b: level 7
0111b: level 8
1000b: level 9
1001b: level 10
1010b: level 11
1011b: level 12
1100b: level 13
1101b: level 14
1110b: level 15
1111b: level 16
41-39
44-42
47-45
LSDVTH_R
LSDVTH_G
LSDVTH_B
R/W
R/W
R/W
000b
000b
000b
Set the Red LED short/weak short circuitry detection threshold
000b: 0.2 V
001b: 0.4 V
010b: 0.8 V
011b: 1.0 V
100b: 1.2 V
101b: 1.4 V
110b: 1.6 V
111b: 1.8 V
Set the Green LED short/weak short circuitry detection threshold
000b: 0.2 V
001b: 0.4 V
010b: 0.8 V
011b: 1.2 V
100b: 1.6 V
101b: 2 V
110b: 2.4 V
111b: 2.8 V
Set the Blue LED short/weak short circuitry detection threshold
000b: 0.2 V
001b: 0.4 V
010b: 0.8 V
011b: 1.2 V
100b: 1.6 V
101b: 2 V
110b: 2.4 V
111b: 2.8 V
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8.7.5 FC4
FC4 is shown in FC4 Register and described in FC4 Register Field Descriptions.
图8-29. FC4 Register
47
31
15
46
45
44
43
42
41
40
39
38
37
36
35
19
34
33
32
RESERVED
DE_COU
PLE3_EN
DE_COUPLE3
DE_COU
PLE2
FIRST_LINE_DIM
LG_CAU LG_CAU LG_CAU
RSE_B
R/W-0b
18
RSE_G
R/W-0b
17
RSE_R
R/W-0b
16
R-000b
30
R/W-0b
28
R/W-1000b
R/W-0b
23
R/W-0000b
29
27
26
SR_ON_B
25
SR_ON_G
24
22
21
20
RESERVED
SR_ON_R
SR_OFF SR_OFF SR_OFF LG_FINE LG_FINE LG_FINE
_B
R/W-0b
5
_G
R/W-0b
4
_R
R/W-0b
3
_B
R-000b
2
_G
_R
R-0000b
R/W-01b
R/W-01b
R/W-01b
14
13
12
11
10
9
8
7
6
1
0
RESERV SCAN_R
RESERVED
IMAX
RESERVED
ED
EV
R-0b
R/W-1b
R-00 0000 0000b
R/W-0b
R-000b
表8-11. FC4 Register Field Descriptions
Bit
Field
Type
Reset
000b
0b
Description
2-0
3
RESERVED
IMAX
R
R/W
Set the maximum current of each channel
0b: 10mA maximum
01b: 20 mA maximum
13-4
14
RESERVED
SCAN_REV
R
000000000
0b
R/W
1b
When 2 device stackable or 3 devices stackable, the scan lines
PCB layout is reversed. For the proper scan and SRAM read
sequence, SCAN_REV register is provided.
0b: the PCB layout sequence is L0-L15, L16-L31.
1b: the PCB layout sequence is L0-L15, L31-L16.
15
16
RESERVED
LG_FINE_R
R
0b
0b
R/W
Enable the Red brightness compensation level fine range
0b: disable
1b: enable
17
18
LG_FINE_G
LG_FINE_B
SR_OFF_R
SR_OFF_G
SR_OFF_B
SR_ON_R
R/W
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
01b
Enable the Green brightness compensation level fine range
0b: disable
1b: enable
Enable the Blue brightness compensation level fine range
0b: disable
1b: enable
19
Slew rate control function when Red turns off operation
0b: slow slew rate.
1b: fast slew rate.
20
Slew rate control function when Green turns off operation
0b: slow slew rate.
1b: fast slew rate.
21
Slew rate control function when Blue turns off operation
0b: slow slew rate.
1b: fast slew rate.
23-22
Slew rate control function when Red turns on operation
00b: the slower slew rate.
01b: slow slew rate.
10b: fast slew rate.
11b: the faster slew rate.
25-24
SR_ON_G
R/W
01b
Slew rate control function when Green turns on operation
00b: the slower slew rate.
01b: slow slew rate.
10b: fast slew rate.
11b: the faster slew rate.
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表8-11. FC4 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
27-26
SR_ON_B
R/W
01b
Slew rate control function when Blue turns on operation
00b: the slower slew rate.
01b: slow slew rate.
10b: fast slew rate.
11b: the faster slew rate.
31-28
32
RESERVED
R
0000b
0b
LG_CAURSE_R
R/W
Enable the Red brightness compensation level caurse range
0b: disable
1b: enable
33
34
LG_CAURSE_G
LG_CAURSE_B
FIRST_LINE_DIM
R/W
R/W
R/W
0b
Enable the Green brightness compensation level caurse range
0b: disable
1b: enable
0b
Enable the Blue brightness compensation level caurse range
0b: disable
1b: enable
38-35
0000b
Adjust the first line dim level
0000b: level 1
...
0111b: level 8
...
1111b: level 16
39
DE_COUPLE2
DE_COUPLE3
R/W
R/W
0b
Decoupling between ON and OFF channels
0b: disabled
1b: enabled
43-40
1000b
Set decoupling enhancement level
0000b: level 1
...
0111b: level 8
...
1111b: level 16
44
DE_COUPLE3_EN
RESERVED
R/W
R
0b
Enable decoupling enhancement
0b: disabled
1b: enabled
47-45
000b
8.7.6 FC10
FC10 is shown in FC10 Register and described in FC10 Register Field Descriptions.
图8-30. FC10 Register
47
31
15
46
30
14
45
29
13
44
28
12
43
27
11
42
26
41
25
9
40
39
38
22
6
37
21
5
36
20
4
35
19
3
34
18
2
33
17
1
32
16
0
RESERVED
R-0b
24
23
RESERVED
R-0b
10
8
7
RESERVED
R-0b
LOD_LINE_CMD
R/W-00000b
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表8-12. FC10 Register Field Descriptions
Bit
Field
Type
Reset
Description
4-0
LOD_LINE_CMD
R/W
00000b
Locate the line with LED open load warnings:
00000b: Line 0
...
01111b: Line 15
...
11111b: Line 31
47-5
RESERVED
R
0b
Reserved bits
8.7.7 FC11
FC11 is shown in FC11 Register and described in FC11 Register Field Descriptions.
图8-31. FC11 Register
47
31
15
46
30
14
45
29
13
44
28
12
43
27
11
42
26
41
25
9
40
39
38
22
6
37
21
5
36
20
4
35
19
3
34
18
2
33
17
1
32
16
0
RESERVED
R-0b
24
23
RESERVED
R-0b
10
8
7
RESERVED
R-0b
LSD_LINE_CMD
R/W-00000b
表8-13. FC11 Register Field Descriptions
Bit
Field
Type
Reset
Description
4-0
LSD_LINE_CMD
R/W
00000b
Locate the line with LED short circuitry warnings:
00000b: Line 0
...
01111b: Line 15
...
11111b: Line 31
47-5
RESERVED
R
0b
Reserved bits
8.7.8 FC12
FC12 is shown in FC12 Register and described in FC12 Register Field Descriptions.
图8-32. FC12 Register
47
31
15
46
30
14
45
29
13
44
28
12
43
27
11
42
26
10
41
25
9
40
39
38
22
6
37
21
5
36
20
4
35
19
3
34
18
2
33
17
1
32
16
0
RESERVED
R-0b
24
23
LOD_LINE_WARN
R-0b
8
7
LOD_LINE_WARN
R-0b
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表8-14. FC12 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
LOD_LINE_WARN
R
0b
Read the line with LED open load warnings:
Bit 0 = 0, Line 0 has no warning; Bit 0 = 1, Line 0 has warning
...
Bit 31 = 0, Line 31 has no warning; Bit 31 = 1, Line 31 has
warning
47-32
RESERVED
R
0b
Reserved bits
8.7.9 FC13
FC13 is shown in FC13 Register and described in FC13 Register Field Descriptions.
图8-33. FC13 Register
47
31
15
46
30
14
45
29
13
44
28
12
43
27
11
42
26
10
41
25
9
40
39
38
22
6
37
21
5
36
20
4
35
19
3
34
18
2
33
17
1
32
16
0
RESERVED
R-0b
24
23
LSD_LINE_WARN
R-0b
8
7
LSD_LINE_WARN
R-0b
表8-15. FC13 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
LSD_LINE_WARN
R
0b
Read the line with LED short circuitry warnings:
Bit 0 = 0, Line 0 has no warning; Bit 0 = 1, Line 0 has warning
...
Bit 31 = 0, Line 31 has no warning; Bit 31 = 1, Line 31 has
warning
47-32
RESERVED
R
0b
Reserved bits
8.7.10 FC14
FC14 is shown in FC14 Register and described in FC14 Register Field Descriptions.
图8-34. FC14 Register
47
31
15
46
30
14
45
29
13
44
28
12
43
27
11
42
26
10
41
25
9
40
LOD_CH
R-0b
39
38
22
6
37
21
5
36
20
4
35
19
3
34
18
2
33
17
1
32
16
0
24
23
LOD_CH
R-0b
8
7
LOD_CH
R-0b
表8-16. FC14 Register Field Descriptions
Bit
47-0
Field
LOD_CH
Type
Reset
Description
R
0b
Locate the LED open load channel:
Bit 0 = 0, CH 0 is normal; Bit 0 = 1, CH 0 is open load
...
Bit 47 = 0, CH 47 is normal; Bit 47 = 1, CH 47 is open load
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8.7.11 FC15
FC15 is shown in FC15 Register and described in FC15 Register Field Descriptions.
图8-35. FC15 Register
47
31
15
46
30
14
45
29
13
44
28
12
43
27
11
42
26
10
41
25
9
40
LSD_CH
R-0b
39
38
22
6
37
21
5
36
20
4
35
19
3
34
18
2
33
17
1
32
16
0
24
23
LSD_CH
R-0b
8
7
LSD_CH
R-0b
表8-17. FC15 Register Field Descriptions
Bit
47-0
Field
LSD_CH
Type
Reset
Description
R
0b
Locate the LED short circuitry channel:
Bit 0 = 0, CH 0 is normal; Bit 0 = 1, CH 0 is short circuitry
...
Bit 47 = 0, CH 47 is normal; Bit 47 = 1, CH 47 is short circuitry
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The LP5890 integrates 48 constant current sources and 16 scanning FETs. A single LP5890 is capable of
driving 16 × 16 RGB LED pixels while stacking two LP5890s can drive 32 × 32 RGB LED pixels. To achieve low
power consumption, the LP5890 supports separated power supplies for the red, green, and blue LEDs by its
common cathode structure.
The LP5890 implements a high speed rising-edge transmission interface (up to 50 MHz) to support high device
count daisy-chained and high refresh rate while minimizing electrical-magnetic interference (EMI). SCLK must be
continuous, no matter there are data on SIN or not, since SCLK is not only used to sample the data on SIN, but
also used as an clock source to generate GCLK by internal frequency multiplier. Based on CCSI protocol, all the
commands/FC registers/SRAM data are written from the SIN input terminal, and all the FC registers/ LED open
and short flag can be read out from the SOUT output terminal. Moreover, the device supports up to 160-MHz
GCLK frequency and can achieve 16-bit PWM resolution, with 3840 Hz or even higher refresh rate.
Meanwhile, the LP5890 integrates enhanced circuits and intelligent algorithms to solve the various display
challenges in Narrow Pixel Pitch (NPP) LED display applications and Mini and Micro-LED products: Dim at the
fist scan line, Upper and downside ghosting, Non-uniformity in low grayscale, Coupling, Caterpillar caused by
open or short LEDs, which make the LP5890 a perfect choice in such applications.
The LP5890 also implements LED open or weak short or short detections and removals during operations and
can also report those information out to the accompanying digital processor.
9.2 Typical Application
The LP5890 are typically connected in series in a daisy-chain to drive the LED matrix with only a few controller
ports. 图9-1 shows a typical application diagram with two LP5890 devices stackable connection to drive 32 × 32
RGB LED pixels.
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图9-1. LP5890 with Dual Devices Stackable Connection
9.2.1 Design Requirements
Taking 4K micro-LED elevation for example, the resolution of the screen is 3840 × 2160 and the screen consists
of many modules. The following sections show an example of how to build an LED display module with 240 ×
180 pixels.
The example uses the following values as the system design parameters.
表9-1. LP5890 Design Parameters
DESIGN PARAMETER
VCC and VR
EXAMPLE VALUE
2.8 V
VG and VB
3.8 V
Maximum current per LED
PWM resolution
IRED = 3 mA, IGREEN = 2 mA, IBLUE = 1 mA
14 bits
Frame rate
120 Hz
Refresh rate
3840 Hz
Display module size
cascaded devices number
devices number per LED display module
240 × 180 pixels
8
96
9.2.1.1 System Structure
To build an LED display module with 240 × 180 pixels, 96 LP5890s are required.
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240 Colume
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
180
Lines
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
图9-2. LED Display Module
As shown in 图 9-2, the total module can be divided into 48 30 × 30 matrix, each matrix includes 2 devices with
stackable connection.
Note
In order to achieve the best performance, TI suggests to distribute the redundant channels and lines
to each 32 × 32 matrix. For this case, two Red/Green/Blue channels and two lines are not used in
each matrix, and these unused pins can be floated. For the software, zero data is suggested to send
to the unused channels. There is no need to send the zero data to unused lines.
9.2.1.2 SCLK Frequency
The SCLK frequency is determined by the data volume of one frame and frame rate. In this application, the data
volume V_Data is 30 × 32 × 48 bits × 4 = 184.32 Kb, the frame rate is 120 Hz. Suppose the data transmission
efficiency is 0.8, the minimum frequency of SCLK should be: fSCLK = V_Data × fframe / 0.8. So the minimum
SCLK frequency is 27.65 MHz with rising-edge transmission.
9.2.1.3 Internal GCLK Frequency
The internal GCLK frequency is configured by the Frequency Multiplier (FREQ_MUL) and is determined by the
PWM resolution. The GCLK frequency can be calculated by the below equations:
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frefresh_ rate
Nsub_ period
=
f frame_ rate
GSmax = 2K
GSmax = NGCLK _ Seg ì Nsub_ period
N
≈
∆
«
’
1
GCLK _ Seg
=
+TSW ì NScan_line ì Nsub_ period +TBlank
÷
f frame_ rate
fGCLK
◊
(3)
where
• frefresh_rate means the refresh rate
• fframe_rate means the frame rate
• K means the PWM resolution
• Nsub_period means the sub-period numbers within one frame
• NGCLK_seg means the GCLK number per segment (line switch time excluded)
• fGCLK means GCLK frequency
• TSW means line switching time
• Nscan_line means the scan line number
• Tblank means the blank time in one frame, equals to 0 in ideal configuration
• GSmax means the maximum grayscale that the device can output in one frame
表9-2 gives the values based on the system configuration and equation.
表9-2. LP5890 Design Parameters for GCLK Frequency Calculation
DESIGN PARAMETER
Nsub_period
Nscan_line
TSW
EXAMPLE VALUE
32
30
1.5 µs
0
Tblank
NGCLK_seg
GSmax
512
16383
71.3 MHz
fGCLK
Considering SCLK frequency and FREQ_MUL, the SCLK can be 27.7 MHz and FREQ_MUL can be 0010b. So
the GCLK will be 83.1 MHz.
9.2.1.4 Line Switch Time
The line switch time is digitized with the GCLK number and can be set by the LINE_SWT (Bit 40-37 in FC1
register). In this application, it is 1.5us × 83.1 MHz = 125 GCLKs, so the LINE_SWT equals to 0011b (120
GCLKs), the actual line switch time is 1.44 us.
9.2.1.5 Blank Time Removal
The LP5890 has an algorithm to distribute the blank time into each subperiod in order to prevent the black field
when taking photos or video.
From Equation 3, 83.1-MHz GCLK frequency and 1.44-us line switch time, the calculated blank time is 1.0361
ms (86100 GCLK), which is too long and will bring black field.
Here are detailed steps of the algorithm:
Step1: Distribute blank time into each segment
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When the blank GCLK number is larger than Nsub_period × Nscan_line, it can be distributed into each segment.
In this application, the blank GCLK number is 86100 and Nsub_period × Nscan_line is 960, so the distributed GCLK
number in each segment is 86100/960 = 89...660. These 89 GCLKs can be used to increase PWM length or
extend line switch time. If used to increase PWM length, the GCLK number in each segment will be 512 + 89 =
601, so the SEG_LENGTH (Bit9-0 in FC1 register) will be 1001011001b.
Step2: Distribute blank time into each sub-period
If the left GCLK number is larger than Nsub_period, it can be distributed into each sub-period.
In this application, the left GCLK is 600 and the distributed GCLK number in each sub-period is 600/32=18...24.
The BLK_ADJ (Bit46-41 in FC1 register) is 010001b.
After distributing into each sub-period, the left GCLK number is 24, which is about 289 ns. This time is too short
to bring black field.
9.2.1.6 BC and CC
Select the reference current-setting resistor RIREF and configure a proper BC value to set the maximum current
of the RGB LEDs (see Brightness Control (BC) Function for more details). Here the maximum current is 3 mA,
BC value is 03h, according to equation 方程式1, the reference resistor value is 0.8V/3mA × 86.61 = 23 kΩ.
Configure the CC_R/CC_G/CC_B registers to set the current of Red/ Green/Blue LED current to 3 mA/2 mA/1
mA (see Color Birghtness Control (CC) Function for more details).
表9-3 shows the reference current setting resistor RIREF, BC and CC_R/CC_G/CC_B register value.
表9-3. Current Setting Value
DESIGN PARAMETER
EXAMPLE VALUE
23 kΩ
RIREF
BC
011 b
CC_R
CC_G
CC_B
11111110 b
10101001 b
01010100 b
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9.2.2 Detailed Design Procedure
图 9-3 gives an detail design procedure for LED display. After power on and digital signals are ready, the first
step for the controller is to send the chip index command to let the devices know their identifications. Then, it
sends the configuration data to the FC registers. After this, it sends the VSYNC at the beginning of each frame
and also sends the data to each device. The devices will display the data of last frame when the VSYNC comes
and meanwhile receive the data of current frame transmitted from controller. The registers can be read at
anytime of the frame.
Begin
Power Supply, SCLK/SIN
Ready
Write Chip Index
Configure the
register during
sending data
Write FC Registers
Write SRAM
Write next
frame SRAM
Data in normal
operation
Wait for the end of current
frame
Write VSYNC
Read registers
during each
time of the
frame
Read Chip Index/FC/LOD/LSD
图9-3. Design Procedure for LED Display
9.2.2.1 Chip Index Command
The chip index is used to distribute the address of the devices in a data chain. Each device gets its unique
address by this command. Details can be found in Chip Index Write Command.
9.2.2.2 FC Registers Settings
Some bits of FC0, FC1, FC3 registers must be configured properly before the devices work normally. In this
application, the register values can be:
表9-4. FC Registers Value
FC Registers
FC0
Register Value(BIN)
Register Value(HEX)
1000 283D 0107 h
2460 0094 A659 h
003B 54A9 FE00 h
0001 0000 0000 0000 0001 1000 0011 1101 0000 0001 0000 0111 b
0010 0100 0110 0000 0000 0000 1001 0100 1010 0110 0101 1001 b
0000 0000 0011 1011 0101 0100 1010 1001 1111 1110 0000 0000 b
FC1
FC3
The controller can configure the FC by the data write command with broadcast mode (see Data Write Command
for more details). The FC0, FC1 registers are updated after the VSYNC command comes, and the other FC
registers are updated right away regardless the VSYNC command.
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9.2.2.3 Grayscale Data Write
The channel grayscale data will be written to SRAM of the device by the data write command with non-broadcast
way, details can be found in Data Write Command and Write a Frame Data into Memory Book.
Data Write Flow is the data write flow for this application, P(i, j) is the data of pixel locating in i+1 row and j+1
column. Suppose channel R15/G15/B15 of each device is not used and not connected, but the channel
R14/G14/B14 is connected to P(i, 0), the channel R13/G13/B13 is connected to P(i, 1),…, and channel
R0/G0/B0 is connected to P(i, 14). The data of unused channel should be zero noting D_Zero in below figure,
and D_Zero = 00000000000000001 00000000000000001 00000000000000001b.
i=0
j=15
ST+HB+P(i, jx7)+P(i, jx6)+Y+P(i, jx1)+P(i,0)+END
j=j-1
Write one
line data
N
Write one
frame data
j=0
Y
ST+HB+D_Zero+D_Zero+Y+D_Zero+D_Zero+END
i=i+1
N
i=30
Y
图9-4. Data Write Flow
9.2.2.4 VSYNC Command
The VSYNC is used to sync the display of each frame for the devices in a cascaded chain. Details can be found
in VSYNC Write Command.
9.2.2.5 LED Open and Short Read
FC10, FC11, FC12, FC13, FC14, FC15 are the read commands for LOD/LSD information. Details can be found
in Read LED-open Information and Read LED-short Information.
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9.2.3 Application Curves
图9-5. Line and Channel Waveform in One Frame
图9-6. Line and Channel Waveform in One
(GSn=0xFFFFh)
Subperiod (GSn=0xFFFFh)
图9-8. Line and Channel Waveform in One Frame
图9-7. Line and Channel Waveform in One Frame
(GSn=0x0001h)
(GSn=0x0001h)
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10 Power Supply Recommendations
Decouple the VCC power supply voltage by placing a 0.1-μF ceramic capacitor close to VCC pin and GND
plane. Depending on panel size, several electrolytic capacitors must be placed on the board equally distributed
to get well regulated LED supply voltage VR/VG/VB. The ripple of the LED supply voltage must be less than 5%
of their nominal value. Generally, the green and blue LEDs have the similar forward voltage and can be supplied
by the same power rail.
Furthermore, the VR > Vf(R) + 0.35 V (10-mA constant current example), the VG = VB > Vf(G/B) + 0.35 V (10-
mA constant current example), and here Vf(R), Vf(G/B) are representative for the maximum forward voltage of
red, green/blue LEDs.
Also in order to simplify the power design, VCC can be connected to VR power rail.
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11 Layout
11.1 Layout Guidelines
• Place the decoupling capacitor near the VCC/VR, VG/VB pins and GND plane.
• Place the current programming resistor RIREF close to IREFpin and GND plane.
• Route the GND thermal pad as widely as possible for large GND currents. Maximum GND current is
approximately 2 A for two devices (96-CH × 20 mA = 1.92 A).
• The Thermal pad must be connected to GND plane because the pad is used as power ground pin internally.
There is a large current flow through this pad when all channels turn on. Furthermore, this pad should be
connected to a heat sink layer by thermal via to reduce device temperature. For more information about
suggested thermal via pattern and via size, see the PowerPAD™ Thermally Enhanced Package Application
Report.
• Routing between the LED Anode side and the device OUTXn pin should be as short and straight as possible
to reduce wire inductance.
• The line switch pins should be located in the middle of the matrix, which should be laid out as symmetrically
as possible.
11.2 Layout Example
In order to simplify the system power rails design, we suggest that VR, VCC use one power rail, and VG, VB use
another power rail. 图11-1 gives an example for power rails routing.
Connect the GND pin to thermal pad on board with the shortest wire and the thermal pad is connected to GND
plane with the vias, as many as possible to help the power dissipation.
32 RGB LEDs
VR/VCC
C
C
GND
GND
GND
GND
C
GND
C
32 Lines
VG/VB
C
C
GND
GND
T
GND
GND
C
GND
C
VR/VCC
图11-1. Power Rails Routing Suggestion
图 11-2 gives an example for line routing. Connect the line switch to the center of the line bus, so as to uniform
the current flowing from the line switch to the left side and right side LEDs in white grayscale. With this
connection, the unbalance of the parasitic inductor from the routing will be the smallest and the display
performance will be better, especially in low grayscale condition.
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图11-2. Line Routing Suggestion
图11-3 gives an example for channel routing with the shortest wire. With this connection, the channel to the LED
path is the shortest, which can reduce the wire inductance, and be a benefit to the performance. However, the
data transmission sequence should be adjusted to follow the pins routing map. For example, R0 connects to
column 15 (LED15 ). The first data should be column 15 (LED15) rather than column 0 (LED0).
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图11-3. Channel Routing Suggestion with Shortest Wire
图 11-4 gives an example for channel routing with pin number sequence. With this connection, the data
transmission sequence will be the same with pin number sequence. For example, R0 connects to column 0
(LED0 ). The first data will be column 0 (LED0). However, with this connection, the inductance for each channel
may be different, which might bring a slight difference for the worst case.
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图11-4. Channel Routing Suggestion with Channel Order Sequence
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12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2021 Texas Instruments Incorporated
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LP5890
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www.ti.com.cn
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
19-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP5890RRFR
LP5890ZXLR
ACTIVE
ACTIVE
VQFN
RRF
ZXL
76
96
2000 RoHS & Green
2500 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
LP5890
LP5890
NFBGA
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Mar-2022
Addendum-Page 2
PACKAGE OUTLINE
NFBGA - 1.08 mm max height
PLASTIC BALL GRID ARRAY
ZXL0096A
A
6.1
5.9
B
BALL A1 CORNER
6.1
5.9
1.08 MAX
C
SEATING PLANE
0.08 C
0.25
0.19
BALL TYP
5 TYP
SYMM
(0.5) TYP
(0.5) TYP
L
K
J
H
G
SYMM
5
TYP
F
E
D
C
0.35
0.25
96X Ø
0.15
0.05
C A B
C
B
A
0.5 TYP
1
2
3
4
5
6
7
8
9
10 11
0.5 TYP
4225828/A 03/2020
NanoFree is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
NFBGA - 1.08 mm max height
PLASTIC BALL GRID ARRAY
ZXL0096A
(0.5) TYP
1
2
3
4
5
6
7
8
9
10
11
A
B
(0.5) TYP
C
D
E
SYMM
F
G
H
J
K
L
96X (Ø 0.25)
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.05 MAX
ALL AROUND
0.05 MIN
EXPOSED
METAL
EXPOSED
METAL
ALL AROUND
(Ø 0.25)
SOLDER MASK
OPENING
(Ø 0.25)
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225828/A 03/2020
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments
Literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
NFBGA - 1.08 mm max height
PLASTIC BALL GRID ARRAY
ZXL0096A
(0.5) TYP
1
2
3
4
5
6
7
8
9
10
11
A
B
(0.5) TYP
C
D
E
SYMM
F
G
H
J
(R0.05) TYP
K
L
96X (☐ 0.25)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 15X
4225828/A 03/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
RRF0076A
VQFN - 1 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
A
9.1
8.9
B
PIN 1 INDEX AREA
9.1
8.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2X 7.2
SYMM
EXPOSED
THERMAL PAD
(0.1) TYP
38
20
19
39
SYMM
77
2X 7.2
6.3 0.1
1
57
72X 0.4
0.25
0.15
76X
76
58
PIN 1 ID
0.1
C A B
0.6
0.4
76X
0.05
4224965/A 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RRF0076A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(6.3)
SYMM
SEE SOLDER MASK
DETAIL
58
76
76X (0.7)
76X (0.2)
1
57
72X (0.4)
(1.1) TYP
(R0.05) TYP
(1.2) TYP
(0.6) TYP
SYMM
77
(8.7)
(
0.2) TYP
VIA
39
19
38
20
(0.6)
TYP
(1.2)
TYP
(1.1)
TYP
(8.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224965/A 04/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RRF0076A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
25X ( 1)
(1.2) TYP
58
76
76X (0.7)
76X (0.2)
1
57
72X (0.4)
(R0.05) TYP
(1.2) TYP
SYMM
77
(8.7)
19
39
38
20
SYMM
(8.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 77
63% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224965/A 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
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