LP590712QDQNRQ1 [TI]

具有低 IQ 和使能功能的汽车类 250mA、低噪声、高 PSRR、超低压降稳压器 | DQN | 4 | -40 to 125;


型号：	LP590712QDQNRQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有低 IQ 和使能功能的汽车类 250mA、低噪声、高 PSRR、超低压降稳压器 \| DQN \| 4 \| -40 to 125 光电二极管输出元件稳压器调节器
文件：	总33页 (文件大小：1461K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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LP5907-Q1

ZHCSD11D –SEPTEMBER 2014–REVISED DECEMBER 2018

LP5907-Q1 汽车 250mA 超低噪声、低 I_QLDO

1 特性

3 说明

•

符合汽车应用要求

具有符合 AEC-Q100 标准的下列结果：

LP5907-Q1 是一款能提供 250mA 输出电流的低噪声

LDO。LP5907-Q1 符合射频和模拟电路要求，可提供

低噪声、高 PSRR、低静态电流以及低线路或负载瞬

态响应系数。LP5907-Q1 采用创新的设计技术，无需

噪声旁路电容便可提供出色的噪声性能，并且支持远距

离安置输出电容。

–

器件温度 1 级：–40°C 至 125°C 的环境工作温

度范围

–

器件 HBM ESD 分类等级 2

器件 CDM ESD 分类等级 C6

•

输入电压范围：2.2V 至 5.5V

输出电压范围：1.2V 至 4.5V

与 1µF 陶瓷输入和输出电容搭配使用，性能稳定

无需噪声旁路电容

此器件可与 1µF 输入和 1µF 输出陶瓷电容搭配使用

（无需独立的噪声旁路电容）。

其固定输出电压介于 1.2V 至 4.5V 之间（阶跃为

25mV）。如需特定的电压选项，请联系德州仪器 (TI)

销售代表。

支持输出电容远端布置

热过载保护和短路保护

输出电流：250mA

器件信息⁽¹⁾

输出电压噪声低：小于 6.5µV_RMS

电源抑制比 (PSRR)：1kHz 频率时为 82dB

输出电压容差：±2%

器件型号

LP5907-Q1

封装

SOT-23 (5)

X2SON (4)⁽²⁾

封装尺寸（标称值）

2.90mm × 1.60mm

1.00mm x 1.00mm

几乎没有 I_Q（已禁用）：< 1µA

极低 I_Q（使能时）：12µA

启动时间：80µs

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

(2) 预览器件。

低压降：120mV（典型值）

运行结温范围：–40°C 到 125°C

2 应用

•

ADAS 摄像机和雷达

汽车信息娱乐系统

车载通讯系统

导航系统

简化原理图

INPUT

OUT

OUTPUT

1 mF

LP5907-Q1

ENABLE

GND

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSA34

LP5907-Q1

ZHCSD11D –SEPTEMBER 2014–REVISED DECEMBER 2018

www.ti.com.cn

7.3 Feature Description................................................. 12

7.4 Device Functional Modes........................................ 13

Application and Implementation ........................ 14

8.1 Application Information............................................ 14

8.2 Typical Application .................................................. 14

Power Supply Recommendations...................... 17

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Output and Input Capacitors..................................... 6

6.7 Typical Characteristics.............................................. 7

Detailed Description ............................................ 11

7.1 Overview ................................................................. 11

7.2 Functional Block Diagram ....................................... 11

10 Layout................................................................... 18

10.1 Layout Guidelines ................................................. 18

10.2 Layout Examples................................................... 18

11 器件和文档支持 ..................................................... 19

11.1 接收文档更新通知 ................................................. 19

11.2 社区资源................................................................ 19

11.3 商标....................................................................... 19

11.4 静电放电警告......................................................... 19

11.5 术语表 ................................................................... 19

12 机械、封装和可订购信息....................................... 19

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision C (May 2018) to Revision D

Page

•

已添加向文档添加了 DQN (X2SON) 封装（预览版） ........................................................................................................... 1

Added Layout Example for the DQN Package figure........................................................................................................... 18

Changes from Revision B (September 2016) to Revision C

Page

•

已添加向特性部分中添加了 ESD 分类级别子项目................................................................................................................ 1

Changed DBV values in Thermal Information table .............................................................................................................. 4

Deleted footnote 1 from Thermal Information table ............................................................................................................... 4

Added Overshoot on start-up with EN row to Electrical Characteristics table ...................................................................... 6

Changed Device Comparison table: changed table title, added new rows and new data, moved to new sub-section ...... 12

Changes from Revision A (June 2016) to Revision B

Page

•

已更改标题措辞...................................................................................................................................................................... 1

已更改将“低输出电压噪声：小于 10µV_RMS”更改成了“低输出电压噪声：小于 6.5µV_RMS” ...................................................... 1

已更改更改了“应用”中所列的项目 ......................................................................................................................................... 1

已更改更改了说明中第一个句子的措辞 ................................................................................................................................. 1

Changes from Original (September 2014) to Revision A

Page

•

已添加特性项目修改：汽车 ................................................................................................................................................... 1

已添加 TI 设计的顶部导航图标 ............................................................................................................................................... 1

已更改 “线性稳压器”更改为“LDO”........................................................................................................................................... 1

Changed storage temperature from Handling Ratings to Abs Max table; replaced Handling Ratings with ESD

Ratings per new format ......................................................................................................................................................... 4

LP5907-Q1

www.ti.com.cn

ZHCSD11D –SEPTEMBER 2014–REVISED DECEMBER 2018

5 Pin Configuration and Functions

DBV Package

5-Pin SOT-23

Top View

DQN Package (Preview)

4-Pin X2SON

Bottom View

OUT GND

GND

OUT

N/C

Pin Functions

I/O

DESCRIPTION

NAME

SOT23-5

X2SON-4

Enable input. A low voltage (< V_IL) on this pin turns the regulator off and

discharges the output pin to GND through an internal 230-Ω pulldown resistor. A

high voltage (> V_IH) on this pin enables the regulator output. This pin has an

internal 1-MΩ pulldown resistor to hold the regulator off by default.

GND

–

Common ground

Input voltage supply. Connect a 1-µF capacitor at this input.

No internal electrical connection.

N/C

—

–

Regulated output voltage. Connect a minimum 1-µF low-ESR capacitor to this

pin. Connect this output to the load circuit. An internal 230-Ω (typical) pulldown

resistor prevents a charge remaining on V_OUTwhen the regulator is in the

shutdown mode (V_ENlow).

OUT

LP5907-Q1

ZHCSD11D –SEPTEMBER 2014–REVISED DECEMBER 2018

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

–0.3

MAX

UNIT

V_IN

Input voltage

(3)

V_OUT

V_EN

Output voltage

See

Enable input voltage

Continuous power dissipation⁽⁴⁾

Junction temperature

Storage temperature

Internally limited

T_JMAX

T_stg

150

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the GND pin.

(3) Abs Max V_OUTis the V_IN+ 0.3 V or 6 V, whichever is less.

(4) Internal thermal shutdown circuitry protects the device from permanent damage.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per AEC

Q100-002⁽¹⁾

All pins

±2000

V_(ESD)

Electrostatic discharge

Corner pins (1,3,4,5)

Other pin (2)

±1000

Charged-device model (CDM), per AEC

Q100-011

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

MAX

5.5

UNIT

V_IN

Input supply voltage

Enable input voltage

Output current

2.2

V_EN

5.5

I_OUT

250

125

°C

T_J-MAX-OP

Operating junction temperature⁽³⁾

–40

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the GND pin.

(3) T_J-MAX-OP= [T_A(MAX)+ (P_D(MAX)× R_θJA)].

6.4 Thermal Information

LP5907-Q1

THERMAL METRIC⁽¹⁾

DBV (SOT-23)

5 PINS

186.9

DQN (X2SON-4)

4-PINS

198.4

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

112.3

109.3

52.3

128.3

Junction-to-top characterization parameter

Junction-to-board characterization parameter

27.5

2.6

ψ_JB

51.8

128.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

LP5907-Q1

www.ti.com.cn

ZHCSD11D –SEPTEMBER 2014–REVISED DECEMBER 2018

6.5 Electrical Characteristics

V_IN= V_OUT(NOM)+ 1 V, V_EN= 1.2 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF (unless otherwise noted)^(1)(2)(3)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

GENERAL

V_IN

Input voltage

T_A= 25°C

2.2

–2

5.5

V_IN= (V_OUT(NOM)+ 1 V) to 5.5 V,

I_OUT= 1 mA to 250 mA, V_OUT≥ 1.8 V

Output voltage tolerance

Line regulation

%V_OUT

V_IN= (V_OUT(NOM)+ 1 V) to 5.5 V,

I_OUT= 1 mA to 250 mA, V_OUT< 1.8 V

–3

ΔV_OUT

V_IN= (V_OUT(NOM)+ 1 V) to 5.5 V,

I_OUT= 1 mA

0.02

%/V

Load regulation

I_OUT= 1 mA to 250 mA

0.001

%/mA

I_LOAD

Output load current

250

V_EN= 1.2 V, I_OUT= 0 mA

V_EN= 1.2 V, I_OUT= 250 mA

V_EN= 0.3 V (Disabled)

V_EN= 1.2 V, I_OUT= 0 mA

I_OUT= 100 mA

250

0.2

I_Q

Quiescent current⁽⁴⁾

425

µA

I_G

Ground current⁽⁵⁾

µA

V_DO

I_SC

Dropout voltage⁽⁶⁾

Short-circuit current limit

I_OUT= 250 mA

T_A= 25°C⁽⁷⁾

250

500

f = 100 Hz, I_OUT= 20 mA

f = 1 kHz, I_OUT= 20 mA

f = 10 kHz, I_OUT= 20 mA

f = 100 kHz, I_OUT= 20 mA

PSRR

Power-supply rejection ratio⁽⁸⁾

I_OUT= 1 mA

I_OUT= 250 mA

e_N

Output noise voltage⁽⁸⁾

BW = 10 Hz to 100 kHz

µV_RMS

6.5

Output automatic discharge

pulldown resistance

R_AD

T_SD

V_EN< V_IL(output disabled)

230

Thermal shutdown

Thermal hysteresis

T_Jrising

160

°C

T_Jfalling from shutdown

LOGIC INPUT THRESHOLDS

V_IN= 2.2 V to 5.5 V,

V_ENfalling until the output is disabled

V_IL

V_IH

Low input threshold

High input threshold

0.4

V_IN= 2.2 V to 5.5 V,

V_ENrising until the output is enabled

1.2

V_EN= 5.5 V and V_IN= 5.5 V

V_EN= 0 V and V_IN= 5.5 V

5.5

I_EN

Input current at EN pin⁽⁹⁾

µA

0.001

(1) All voltages are with respect to the device GND terminal, unless otherwise stated.

(2) Minimum and maximum limits are ensured through test, design, or statistical correlation over the junction temperature (T_J) range of

–40°C to 125°C, unless otherwise stated. Typical values represent the most likely parametric norm at T_A= 25°C, and are provided for

reference purposes only.

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP

125°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the

part/package in the application R_θJA), as given by the following equation: T_A-MAX= T_J-MAX-OP– (R_θJA× P_D-MAX). See Application and

Implementation.

(4) Quiescent current is defined here as the difference in current between the input voltage source and the load at V_OUT

(5) Ground current is defined here as the total current flowing to ground as a result of all input voltages applied to the device.

(6) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its

nominal value.

(7) Short-circuit current (I_SC) for the LP5907-Q1 is equivalent to current limit. To minimize thermal effects during testing, I_SCis measured

with V_OUTpulled to 100 mV below its nominal voltage.

(8) This specification is verified by design.

(9) There is a 1-MΩ resistor between EN and ground on the device.

LP5907-Q1

ZHCSD11D –SEPTEMBER 2014–REVISED DECEMBER 2018

www.ti.com.cn

Electrical Characteristics (continued)

V_IN= V_OUT(NOM)+ 1 V, V_EN= 1.2 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF (unless otherwise noted)^(1)(2)(3)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TRANSIENT CHARACTERISTICS

V_IN= (V_OUT(NOM)+ 1 V) to

(V_OUT(NOM) + 1.6 V) in 30 µs

–1

Line transient⁽⁸⁾

V_IN= (V_OUT(NOM)+ 1.6 V) to

(V_OUT(NOM) + 1.6 V) in 30 µs

I_OUT= 1 mA to 250 mA in 10 µs

–40

Load transient⁽⁸⁾

ΔV_OUT

I_OUT= 250 mA to 1 mA in 10 µs

Overshoot on start-up⁽⁸⁾

Stated as a percentage of V_OUT(NOM)

Stated as a percentage of V_OUT(NOM), V_IN

V_OUT+ 1 V to 5.5 V, 0.7 µF < C_OUT< 10 µF, 0

mA < I_OUT< 250 mA, EN rising until the output

is enabled

Overshoot on start-up with EN⁽⁸⁾

From V_EN> V_IHto V_OUT= 95% of V_OUT(NOM)

T_A= 25°C

t_ON

Turnon time

150

µs

6.6 Output and Input Capacitors

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN⁽¹⁾

TYP

MAX

UNIT

µF

C_IN

Input capacitance⁽²⁾

Output capacitance⁽²⁾

Output/input capacitance⁽²⁾

0.7

Capacitance for stability

C_OUT

ESR

500

mΩ

(1) The minimum capacitance should be greater than 0.5 μF over the full range of operating conditions. The capacitor tolerance should be

30% or better over the full temperature range. The full range of operating conditions for the capacitor in the application should be

considered during device selection to ensure this minimum capacitance specification is met. X7R capacitors are recommended however

capacitor types X5R, Y5V and Z5U may be used with consideration of the application and conditions.

(2) This specification is verified by design.

LP5907-Q1

www.ti.com.cn

ZHCSD11D –SEPTEMBER 2014–REVISED DECEMBER 2018

6.7 Typical Characteristics

V_IN= 3.7 V, V_OUT= 2.8 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, T_A= 25°C (unless otherwise noted)

0.9

0.8

0.7

0.6

0.5

VIH Rising

VIL Falling

2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8

(V)

2.5

3.5

4.5

5.5

VIN (V)

D001

SVA-30180569

Figure 2. V_ENThresholds vs V_IN

Figure 1. Quiescent Current vs Input Voltage

1.4

1.2

4.5

3.5

0.8

0.6

0.4

0.2

2.5

1.5

RLOAD = 1.2 kW

RLOAD = 4.8 W

RLOAD = 4.5 kW

RLOAD = 18 W

0.5

1.5

2.5

VIN (V)

D002

D003

V_OUT= 1.2 V, V_EN= V_IN

V_OUT= 4.5 V, V_EN= V_IN

Figure 4. V_OUTvs V_IN

Figure 3. V_OUTvs V_IN

350

300

250

200

150

100

2.900

2.875

2.850

2.825

2.800

2.775

2.750

2.725

2.700

= 3.6V

VIN = 3.0V

VIN = 3.8V

VIN = 4.2V

VIN = 5.5V

-40°C

90°C

25°C

50 100 150 200 250 300

(mA)

100

LOAD (mA)

150

200

250

OUT

SVA-30180567

SVA-30180571

Figure 6. Load Regulation

Figure 5. Ground Current vs Output Current

LP5907-Q1

ZHCSD11D –SEPTEMBER 2014–REVISED DECEMBER 2018

www.ti.com.cn

Typical Characteristics (continued)

V_IN= 3.7 V, V_OUT= 2.8 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, T_A= 25°C (unless otherwise noted)

2.900

2V/DIV

Load = 10 mA

2.875

2.850

2.825

2.800

2.775

2.750

2.725

2.700

OUT

IN = EN

-40°C

90°C

25°C

1A/DIV

2 ms/DIV

3.0

3.5

4.0

4.5

(V)

5.0

5.5

SVA-30180568

SVA-30180509

Figure 7. Line Regulation

Figure 8. Inrush Current

10 mV/

DIV

10 mV/

DIV

OUT

(AC Coupled)

1V/DIV

10 ꢀs/DIV

SVA-30180511

SVA-30180510

V_IN= 3.2 V ↔ 4.2 V, load = 250 mA

V_IN= 3.2 V ↔ 4.2 V, load = 1 mA

Figure 10. Line Transient

Figure 9. Line Transient

OUT

100 mV/DIV

LOAD

200 mA/DIV

SVA-30180513

200 mA/DIV

SVA-30180512

LOAD

100 ꢀs/DIV

Load = 0 mA ↔ 250 mA, 90°C

Load = 0 mA ↔ 250 mA, –40°C

Figure 12. Load Transient

Figure 11. Load Transient

LP5907-Q1

www.ti.com.cn

ZHCSD11D –SEPTEMBER 2014–REVISED DECEMBER 2018

Typical Characteristics (continued)

V_IN= 3.7 V, V_OUT= 2.8 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, T_A= 25°C (unless otherwise noted)

1V/DIV

100 mV/DIV

OUT

1V/DIV

LOAD

200 mA/DIV

SVA-30180514

100 ꢀs/DIV

20 ꢀs/DIV

SVA-30180515

0 mA

Load = 0 mA ↔ 250 mA, 25°C

Figure 14. Start-Up

Figure 13. Load Transient

1V/DIV

OUT

1V/DIV

20 ꢀs/DIV

SVA-30180516

250 mA

Figure 15. Start-Up

Figure 16. Noise Density Test

140

120

100

250 mA

200 mA

150 mA

100 mA

50 mA

-20

-40

20 mA

-60

-80

Dropout Voltage

-100

100

150

200

250

-120

LOAD CURRENT (mA)

0.1

100

SVA-30180573

FREQUENCY (kHz)

D004

Figure 17. Dropout Voltage vs Load Current

Figure 18. PSRR Loads Averaged 100 Hz To 100 KHz

LP5907-Q1

ZHCSD11D –SEPTEMBER 2014–REVISED DECEMBER 2018

www.ti.com.cn

Typical Characteristics (continued)

V_IN= 3.7 V, V_OUT= 2.8 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, T_A= 25°C (unless otherwise noted)

-20

-40

-60

250 mA

200 mA

150 mA

-80

100 mA

50 mA

20 mA

-100

-120

0.01

0.1

100

1000

10000

FREQUENCY (kHz)

D005

Figure 19. PSRR Loads Averaged 10 Hz To 10 MHz

LP5907-Q1

www.ti.com.cn

ZHCSD11D –SEPTEMBER 2014–REVISED DECEMBER 2018

7 Detailed Description

7.1 Overview

Designed to meet the needs of sensitive RF and analog circuits, the LP5907-Q1 provides low noise, high PSRR,

low quiescent current, as well as low line and load transient response figures. Using new innovative design

techniques, the LP5907-Q1 offers class leading noise performance without the need for a separate noise filter

capacitor.

The LP5907-Q1 is designed to perform with a single 1-µF input capacitor and a single 1-µF ceramic output

capacitor. With a reasonable PCB layout, the single 1-µF ceramic output capacitor can be placed up to 10 cm

away from the LP5907-Q1 package.

7.2 Functional Block Diagram

OUT

POR

1.20V

1 Mꢀ

V_IH

GND

LP5907-Q1

ZHCSD11D –SEPTEMBER 2014–REVISED DECEMBER 2018

www.ti.com.cn

7.3 Feature Description

7.3.1 LP5907-Q1 Voltage Options

Table 1 lists the available voltage options for the LP5907-Q1 SOT-23 package.

Table 1. Voltage Options

SOT-23 PACKAGE ORDER NUMBER

LP5907QMFX-1.2Q1

—

VOLTAGE OPTION (V)

1.2

1.3

1.5

1.8

2.5

2.8

2.85

2.9

3.0

3.3

3.8

4.5

—

LP5907QMFX-1.8Q1

LP5907QMFX-2.5Q1

LP5907QMFX-2.8Q1

LP5907QMFX-3.0Q1

LP5907QMFX-3.3Q1

LP5907QMFX-3.8Q1

LP5907QMFX-4.5Q1

7.3.2 Enable (EN)

The LP5907-Q1 EN pin is internally held low by a 1-MΩ resistor to GND. The EN pin voltage must be higher than

the V_IHthreshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage

must be lower than the V_ILthreshold to ensure that the device is fully disabled and the automatic output

discharge is activated.

7.3.3 Low Output Noise

Any internal noise at the LP5907-Q1 reference voltage is reduced by a first order low-pass RC filter before it is

passed to the output buffer stage. The low-pass RC filter has a –3 dB cut-off frequency of approximately 0.1 Hz.

7.3.4 Output Automatic Discharge

The LP5907-Q1 output employs an internal 230-Ω (typical) pulldown resistance to discharge the output when the

EN pin is low, and the device is disabled.

7.3.5 Remote Output Capacitor Placement

The LP5907-Q1 requires at least a 1-µF capacitor at the OUT pin, but there are no strict requirements about the

location of the capacitor in regards the OUT pin. In practical designs, the output capacitor may be located up to

10 cm away from the LDO.

7.3.6 Thermal Overload Protection (T_SD

)

Thermal shutdown disables the output when the junction temperature rises to approximately 160°C which allows

the device to cool. When the junction temperature cools to approximately 145°C, the output circuitry enables.

Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may

cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a

result of overheating.

The thermal shutdown circuitry of the LP5907-Q1 has been designed to protect against temporary thermal

overload conditions. The thermal shutdown circuitry was not intended to replace proper heat-sinking.

Continuously running the LP5907-Q1 device into thermal shutdown may degrade device reliability.

LP5907-Q1

www.ti.com.cn

ZHCSD11D –SEPTEMBER 2014–REVISED DECEMBER 2018

7.4 Device Functional Modes

7.4.1 Enable (EN)

The LP5907-Q1 Enable (EN) pin is internally held low by a 1-MΩ resistor to GND. The EN pin voltage must be

higher than the V_IHthreshold to ensure that the device is fully enabled under all operating conditions.

When the EN pin is pulled low, and the output is disabled, the output automatic discharge circuitry is activated.

Any charge on the OUT pin is discharged to GND through the internal 230-Ω (typical) pull-down resistance.

7.4.2 Minimum Operating Input Voltage (V_IN)

The LP5907-Q1 does not include any dedicated undervoltage lockout circuitry. The LP5907-Q1 internal circuitry

is not fully functional until V_INis at least 2.2 V. The output voltage is not regulated until V_INhas reached at least

the greater of 2.2 V or (V_OUT+ V_DO).

LP5907-Q1

ZHCSD11D –SEPTEMBER 2014–REVISED DECEMBER 2018

www.ti.com.cn

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

Figure 20 shows the typical application circuit for the LP5907-Q1. Input and output capacitances may need to be

increased above the 1 µF minimum for some applications.

8.2 Typical Application

INPUT

OUT

OUTPUT

1 mF

LP5907-Q1

ENABLE

GND

Figure 20. LP5907-Q1 Typical Application

8.2.1 Design Requirements

DESIGN PARAMETER

EXAMPLE VALUE

2.2 to 5.5 V

1.8 V

Input voltage range

Output voltage

Output current

200 mA

Output capacitor range

Input/output capacitor ESR range

0.7 to 10 µF

5 to 500 mΩ

8.2.2 Detailed Design Procedure

To begin the design process, determine the following:

•

Available input voltage range

Output voltage needed

Output current needed

Input and Output capacitors

8.2.2.1 Power Dissipation and Device Operation

The permissible power dissipation for any package is a measure of the capability of the device to pass heat from

the power source, the junctions of the device, to the ultimate heat sink, the ambient environment. Thus, the

power dissipation is dependent on the ambient temperature and the thermal resistance across the various

interfaces between the die junction and ambient air.

LP5907-Q1

www.ti.com.cn

ZHCSD11D –SEPTEMBER 2014–REVISED DECEMBER 2018

The maximum allowable power dissipation for the device in a given package can be calculated using Equation 1:

P_D-MAX= ((T_J-MAX– T_A) / R_θJA

)

(1)

The actual power being dissipated in the device can be represented by Equation 2:

P_D= (V_IN- V_OUT) × I_OUT

(2)

Equation 1 and Equation 2 establish the relationship between the maximum power dissipation allowed due to

thermal consideration, the voltage drop across the device, and the continuous current capability of the device.

These two equations should be used to determine the optimum operating conditions for the device in the

application.

In applications where lower power dissipation (P_D) and/or excellent package thermal resistance (R_θJA) is present,

the maximum ambient temperature (T_A-MAX) may be increased.

In applications where high power dissipation and/or poor package thermal resistance is present, the maximum

ambient temperature (T_A-MAX) may have to be derated. T_A-MAXis dependent on the maximum operating junction

temperature (T_J-MAX-OP= 125°C), the maximum allowable power dissipation in the device package in the

application (P_D-MAX), and the junction-to ambient thermal resistance of the part/package in the application (R_θJA),

as given by Equation 3:

T_A-MAX= (T_J-MAX-OP– (R_θJA× P_D-MAX))

(3)

Alternately, if T_A-MAXcan not be derated, the P_Dvalue must be reduced. This can be accomplished by reducing

V_INin the V_IN– V_OUTterm as long as the minimum V_INis met, or by reducing the I_OUTterm, or by some

combination of the two.

8.2.2.2 External Capacitors

Like most LDOs, the LP5907-Q1 requires external capacitors for regulator stability. The device is specifically

designed for portable applications requiring minimum board space and smallest components. These capacitors

must be correctly selected for good performance.

8.2.2.3 Input Capacitor

An input capacitor is required for stability. The input capacitor should be at least equal to, or greater than, the

output capacitor for good load transient performance. At least a 1-µF capacitor has to be connected between the

LP5907-Q1 input pin and ground for stable operation over full load current range. Basically, it is acceptable to

have more output capacitance than input, as long as the input is at least 1 µF.

The input capacitor must be located a distance of not more than 1 cm from the IN pin and returned to a clean

analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.

Important: To ensure stable operation it is essential that good PCB practices are employed to minimize ground

impedance and keep input inductance low. If these conditions cannot be met, or if long leads are to be used to

connect the battery or other power source to the LP5907-Q1, TI recommends increasing the input capacitor to at

least 10 µF. Also, tantalum capacitors can suffer catastrophic failures due to surge current when connected to a

low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the

input, it must be verified by the manufacturer to have a surge current rating sufficient for the application. The

initial tolerance, applied voltage de-rating, and temperature coefficient must all be considered when selecting the

input capacitor to ensure the actual capacitance is never less than 0.7 µF over the entire operating range.

8.2.2.4 Output Capacitor

The LP5907-Q1 is designed specifically to work with a very small ceramic output capacitor, typically 1 µF. A

ceramic capacitor (dielectric types X5R or X7R) in the 1-µF to 10-µF range, and with equivalent series resistance

(ESR) between 5 mΩ to 500 mΩ, is suitable in the LP5907-Q1 application circuit. For this device connect the

output capacitor between the OUT pin and a good connection back to the GND pin.

It may also be possible to use tantalum or film capacitors at the device output, V_OUT, but these are not as

attractive for reasons of size and cost (see Capacitor Characteristics).

The output capacitor must meet the requirement for the minimum value of capacitance and have an ESR value

that is within the range 5 mΩ to 500 mΩ for stability. Like the input capacitor, the initial tolerance, applied voltage

de-rating, and temperature coefficient must all be considered when selecting the input capacitor to ensure the

actual capacitance is never less than 0.7 µF over the entire operating range.

LP5907-Q1

ZHCSD11D –SEPTEMBER 2014–REVISED DECEMBER 2018

www.ti.com.cn

8.2.2.5 Capacitor Characteristics

The LP5907-Q1 is designed to work with ceramic capacitors on the input and output to take advantage of the

benefits they offer. For capacitance values in the range of 1 µF to 10 µF, ceramic capacitors are the smallest,

least expensive, and have the lowest ESR values, thus making them best for eliminating high frequency noise.

The ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR

requirement for stability for the LP5907-Q1.

A better choice for temperature coefficient in a ceramic capacitor is X7R. This type of capacitor is the most stable

and holds the capacitance within ±15% over the temperature range. Tantalum capacitors are less desirable than

ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance

and voltage ratings in the 1 µF to 10 µF range.

Another important consideration is that tantalum capacitors have higher ESR values than equivalent size

ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the

stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic

capacitor with the same ESR value. The ESR of a typical tantalum increases about 2:1 as the temperature goes

from 25°C down to –40°C, so some guard band must be allowed.

8.2.2.6 Remote Capacitor Operation

The LP5907-Q1 requires at least a 1-µF capacitor at the OUT pin, but there are no strict requirements about the

location of the capacitor in regards to the pin. In practical designs the output capacitor may be located up to 10

cm away from the LDO. This means that there is no need to have a special capacitor close to the output pin if

there is already respective capacitors in the system (like a capacitor at the input of supplied part). The remote

capacitor feature helps user to minimize the number of capacitors in the system.

As a good design practice, keep the wiring parasitic inductance at a minimum, which means to use as wide as

possible traces from the LDO output to the capacitors, keeping the LDO output trace layer as close as possible

to ground layer and avoiding vias on the path. If there is a need to use vias, implement as many as possible vias

between the connection layers. The recommendation is to keep parasitic wiring inductance less than 35 nH. For

the applications with fast load transients, it is recommended to use an input capacitor equal to or larger to the

sum of the capacitance at the output node for the best load transient performance.

8.2.2.7 No-Load Stability

The LP5907-Q1 remains stable, and in regulation, with no external load.

8.2.2.8 Enable Control

The LP5907-Q1 may be switched ON or OFF by a logic input at the EN pin. A voltage on this pin greater than

V_IHturns the device on, while a voltage less than V_ILturns the device off.

When the EN pin is low, the regulator output is off and the device typically consumes less than 1 µA.

Additionally, an output pulldown circuit is activated which ensures that any charge stored on C_OUTis discharged

to ground.

If the application does not require the use of the shutdown feature, the EN pin can be tied directly to the IN pin to

keep the regulator output permanently on.

An internal 1-MΩ pulldown resistor ties the EN input to ground, ensuring that the device remains off if the EN pin

is left open circuit. To ensure proper operation, the signal source used to drive the EN pin must be able to swing

above and below the specified turnon or turnoff voltage thresholds listed in the Electrical Characteristics under

V_ILand V_IH.

LP5907-Q1

www.ti.com.cn

ZHCSD11D –SEPTEMBER 2014–REVISED DECEMBER 2018

8.2.3 Application Curves

1V/DIV

100 mV/DIV

200 mA/DIV

OUT

1V/DIV

LOAD

100 ꢀs/DIV

20 ꢀs/DIV

SVA-30180514

SVA-30180515

Figure 22. Load Transient Response

Figure 21. Start-Up

9 Power Supply Recommendations

This device is designed to operate from an input supply voltage range of 2.2 V to 5.5 V. The input supply must

be well regulated and free of spurious noise. To ensure that the LP5907-Q1 output voltage is well regulated and

dynamic performance is optimum, the input supply must be at least V_OUT+ 1 V. A minimum capacitor value of

1 µF is required to be within 1 cm of the IN pin.

LP5907-Q1

ZHCSD11D –SEPTEMBER 2014–REVISED DECEMBER 2018

www.ti.com.cn

10 Layout

10.1 Layout Guidelines

The dynamic performance of the LP5907-Q1 is dependant on the layout of the PCB. PCB layout practices that

are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5907-Q1.

Best performance is achieved by placing C_INand C_OUTon the same side of the PCB as the LP5907-Q1, and as

close as is practical to the package. The ground connections for C_INand C_OUTmust be back to the LP5907-Q1

ground pin using as wide and short copper traces as are practical.

Avoid connections using long trace lengths, narrow trace widths, and/or connections through vias. These add

parasitic inductances and resistance that results in inferior performance especially during transient conditions

10.2 Layout Examples

OUT

GND

Enable

N/C

Figure 23. LP5907MF-x.x (SOT-23) Typical Layout

OUT

C_OUT

C_IN

GND PLANE

Represents via used for application

specific connections

Figure 24. Layout Example for the DQN Package

LP5907-Q1

www.ti.com.cn

ZHCSD11D –SEPTEMBER 2014–REVISED DECEMBER 2018

11 器件和文档支持

11.1 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.2 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.3 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.5 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

23-Jun-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LP590712QDQNRQ1

LP590713QDQNRQ1

LP590715QDQNRQ1

LP590718QDQNRQ1

LP590722QDQNRQ1

LP590725QDQNRQ1

LP5907285QDQNRQ1

LP590728QDQNRQ1

LP590729QDQNRQ1

LP590730QDQNRQ1

LP590733QDQNRQ1

LP590738QDQNRQ1

LP590745QDQNRQ1

LP5907QMFX-1.2Q1

LP5907QMFX-1.8Q1

LP5907QMFX-2.5Q1

LP5907QMFX-2.8Q1

LP5907QMFX-3.0Q1

LP5907QMFX-3.3Q1

LP5907QMFX-3.8Q1

ACTIVE

X2SON

SOT-23

DQN

DBV

3000 RoHS & Green

NIPDAUAG

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

-40 to 125

Samples

NIPDAUAG

RAFQ

RAGQ

RAJQ

RAKQ

RALQ

RAHQ

RAMQ

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

23-Jun-2023

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LP5907QMFX-4.5Q1

ACTIVE

SOT-23

DBV

3000 RoHS & Green

Call TI | SN

Level-1-260C-UNLIM

-40 to 125

RAIQ

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LP5907-Q1 :

Catalog : LP5907

•

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

23-Jun-2023

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LP590712QDQNRQ1

LP590713QDQNRQ1

LP590715QDQNRQ1

LP590718QDQNRQ1

LP590722QDQNRQ1

LP590725QDQNRQ1

LP5907285QDQNRQ1

LP590728QDQNRQ1

LP590729QDQNRQ1

LP590730QDQNRQ1

LP590733QDQNRQ1

LP590738QDQNRQ1

LP590745QDQNRQ1

LP5907QMFX-1.2Q1

LP5907QMFX-1.8Q1

LP5907QMFX-2.5Q1

X2SON

SOT-23

DQN

DBV

3000

180.0

178.0

8.4

1.16

3.2

1.16

3.2

0.63

1.4

4.0

8.0

3.2

1.4

3.2

1.4

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LP5907QMFX-2.8Q1

LP5907QMFX-3.0Q1

LP5907QMFX-3.3Q1

LP5907QMFX-3.8Q1

LP5907QMFX-4.5Q1

SOT-23

DBV

3000

178.0

8.4

3.2

1.4

4.0

8.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LP590712QDQNRQ1

LP590713QDQNRQ1

LP590715QDQNRQ1

LP590718QDQNRQ1

LP590722QDQNRQ1

LP590725QDQNRQ1

LP5907285QDQNRQ1

LP590728QDQNRQ1

LP590729QDQNRQ1

LP590730QDQNRQ1

LP590733QDQNRQ1

LP590738QDQNRQ1

LP590745QDQNRQ1

LP5907QMFX-1.2Q1

LP5907QMFX-1.8Q1

LP5907QMFX-2.5Q1

LP5907QMFX-2.8Q1

LP5907QMFX-3.0Q1

X2SON

SOT-23

DQN

DBV

3000

213.0

208.0

191.0

35.0

Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LP5907QMFX-3.3Q1

LP5907QMFX-3.8Q1

LP5907QMFX-4.5Q1

SOT-23

DBV

3000

208.0

191.0

35.0

Pack Materials-Page 4

PACKAGE OUTLINE

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

3.0

2.6

0.1 C

1.75

1.45

0.90

PIN 1

INDEX AREA

(0.1)

2X 0.95

1.9

3.05

2.75

1.9

(0.15)

0.5

0.3

0.15

0.00

(1.1)

TYP

0.2

C A B

NOTE 5

0.25

GAGE PLANE

0.22

0.08

TYP

0.6

0.3

TYP

SEATING PLANE

4214839/G 03/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.25 mm per side.

5. Support pin may differ or may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

5X (0.6)

SYMM

(1.9)

2X (0.95)

(R0.05) TYP

(2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214839/G 03/2023

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

5X (0.6)

SYMM

(1.9)

2X(0.95)

(R0.05) TYP

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4214839/G 03/2023

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

X2SON - 0.4 mm max height

DQN0004A

PLASTIC SMALL OUTLINE - NO LEAD

1.05

0.95

1.05

0.95

PIN 1

INDEX AREA

0.4 MAX

SEATING PLANE

0.08

NOTE 6

+0.12

-0.1

0.05

0.00

0.48

(0.05) TYP

NOTE 6

EXPOSED

THERMAL PAD

2X 0.65

(0.07) TYP

NOTE 5

0.28

PIN 1 ID

(OPTIONAL)

NOTE 4

0.15

(0.11)

0.3

0.2

0.1

C A B

0.05

0.30

0.15

4215302/E 12/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.

5. Shape of exposed side leads may differ.

6. Number and location of exposed tie bars may vary.

www.ti.com

EXAMPLE BOARD LAYOUT

X2SON - 0.4 mm max height

DQN0004A

PLASTIC SMALL OUTLINE - NO LEAD

(0.86)

SYMM

SEE DETAIL

4X (0.36)

(0.03)

4X (0.21)

SYMM

(0.65)

4X (0.18)

(

0.48)

(0.22) TYP

EXPOSED METAL

CLEARANCE

LAND PATTERN EXAMPLE

SCALE: 40X

0.05 MIN

ALL AROUND

SOLDER MASK

OPENING

EXPOSED METAL

METAL UNDER

SOLDER MASK

DEFINED

SOLDER MASK DETAIL

4215302/E 12/2016

NOTES: (continued)

7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271)

8. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

X2SON - 0.4 mm max height

DQN0004A

PLASTIC SMALL OUTLINE - NO LEAD

(0.9)

SYMM

4X (0.4)

4X (0.03)

4X (0.21)

SYMM

(0.65)

SOLDER MASK

EDGE

4X (0.22)

(

0.45)

4X (0.235)

SOLDER PASTE EXAMPLE

BASED ON 0.075 - 0.1mm THICK STENCIL

EXPOSED PAD

88% PRINTED SOLDER COVERAGE BY AREA

SCALE: 60X

4215302/E 12/2016

NOTES: (continued)

9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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