LP5912-0.9DRVT [TI]

具有反向电流保护功能的 500mA、低噪声、低 IQ、低压降稳压器 | DRV | 6 | -40 to 125;


型号：	LP5912-0.9DRVT
厂家：	TEXAS INSTRUMENTS
描述：	具有反向电流保护功能的 500mA、低噪声、低 IQ、低压降稳压器 \| DRV \| 6 \| -40 to 125 光电二极管输出元件稳压器调节器
文件：	总36页 (文件大小：2841K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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LP5912

ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016

LP5912 500mA 低噪声、低 I_QLDO

1 特性

3 说明

•

输入电压范围：1.6V 至 6.5V

LP5912 是一款能提供高达 500mA 输出电流的低噪声

LDO。LP5912 器件专为满足射频 (RF) 和模拟电路的

要求而设计，具备低噪声、高 PSRR、低静态电流以

及低线路或负载瞬态响应等特性。LP5912 无需噪声旁

路电容便可提供出色的噪声性能，并且支持远距离安置

输出电容。

输出电压范围：0.8V 至 5.5V

输出电流最高达 500 mA

低输出电压噪声：12µV_RMS典型值

1kHz 时的电源抑制比 (PSRR)：75dB（典型值）

输出电压容差 (V_OUT≥ 3.3V)：±2%

低 I_Q（使能时，无负载）：30µA（典型值）

此器件适合与 1µF 输入和 1µF 输出陶瓷电容搭配使用

（无需独立的噪声旁路电容）。

低压降 (V_OUT≥ 3.3V)：500mA 负载时典型值为

95mV

其固定输出电压介于 0.8V 和 5.5V 之间（以 25mV 为

单位增量）。如需特定的电压选项，请联系德州仪器

(TI) 销售代表。

•

与 1µF 陶瓷输入和输出电容搭配使用，性能稳定

热过载保护和短路保护

反向电流保护

无需噪声旁路电容

器件信息⁽¹⁾

自动输出放电实现快速关断

电源正常状态输出具有 140µs 典型延迟

内部软启动限制浪涌电流

器件型号

LP5912

封装

WSON (6)

封装尺寸（标称值）

2.00mm x 2.00mm

(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录

(POA)。

–40°C 至 +125°C 的运行结温范围

空白

2 应用

•

摄像机模块

传感器

HiFi 音频无线电收发器

锁相环 (PLL)/合成器，定时

中等电流，噪声敏感应用

空格

简化电路原理图

V_IN

V_OUT

OUT

C_IN

LP5912

C_OUT

GND

R_PG

V_EN

V_PG

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNVSA77

LP5912

ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016

www.ti.com.cn

8.3 Feature Description................................................. 17

8.4 Device Functional Modes........................................ 19

Applications and Implementation ...................... 20

9.1 Application Information............................................ 20

9.2 Typical Application .................................................. 20

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Voltage Options ..................................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ..................................... 4

7.2 ESD Ratings.............................................................. 4

7.3 Recommended Operating Conditions ...................... 4

7.4 Thermal Information.................................................. 4

7.5 Electrical Characteristics........................................... 5

7.6 Output and Input Capacitors..................................... 7

7.7 Typical Characteristics.............................................. 8

Detailed Description ............................................ 17

8.1 Overview ................................................................. 17

8.2 Functional Block Diagram ....................................... 17

10 Power Supply Recommendations ..................... 23

11 Layout................................................................... 24

11.1 Layout Guidelines ................................................. 24

11.2 Layout Example .................................................... 24

12 器件和文档支持 ..................................................... 25

12.1 相关文档ꢀ ........................................................... 25

12.2 接收文档更新通知 ................................................. 25

12.3 社区资源................................................................ 25

12.4 商标....................................................................... 25

12.5 静电放电警告......................................................... 25

12.6 Glossary................................................................ 25

13 机械、封装和可订购信息....................................... 25

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision C (September 2016) to Revision D

Page

•

已添加封装图 ........................................................................................................................................................................ 1

Changes from Revision B (June 2016) to Revision C

Page

•

已更改数据表标题的措辞 ...................................................................................................................................................... 1

已更改的第一句的措辞说明.................................................................................................................................................... 1

Changes from Revision A (April 2016) to Revision B

Page

•

已更改 "第 1 页的“线性稳压器”改为“LDO” .............................................................................................................................. 1

LP5912

www.ti.com.cn

ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016

5 Voltage Options

This device is capable of providing fixed output voltages from 0.8 V to 5.5 V in 25-mV steps. For all available

package and voltage options, see the POA at the end of this datasheet. Contact Texas Instruments Sales for

specific voltage option needs.

6 Pin Configuration and Functions

DRV Package

6-Pin WSON With Thermal Pad

Top View

OUT

GND

Pin Functions

I/O

DESCRIPTION

NUMBER

NAME

OUT

—

Regulated output voltage

No internal connection. Leave open, or connect to ground.

Power-good indicator. Requires external pullup.

Enable input. Logic high = device is ON, logic low = device is OFF, with internal 3-MΩ

pulldown.

GND

Ground

Unregulated input voltage

Connect to copper area under the package to improve thermal performance. The use of

thermal vias to transfer heat to inner layers of the PCB is recommended. Connect the

thermal pad to ground, or leave floating. Do not connect the thermal pad to any potential

other than ground.

Exposed

thermal pad

—

LP5912

ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

–0.3

-0.3

–0.3

MAX

UNIT

V_IN

Input voltage

V_OUT

V_EN

V_PG

T_J

Output voltage

Enable input voltage

Power Good (PG) pin OFF voltage

Junction temperature

Continuous power dissipation⁽³⁾

Storage temperature

150

°C

P_D

Internally Limited

–65

T_stg

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the GND pin.

(3) Internal thermal shutdown circuitry protects the device from permanent damage.

7.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process..

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

1.6

0.8

MAX

6.5

UNIT

V_IN

Input supply voltage

Output voltage

V_OUT

V_EN

5.5

Enable input voltage

PG pin OFF voltage

Output current

V_IN

V_PG

6.5

I_OUT

500

125

°C

T_J-MAX-OP

Operating junction temperature⁽²⁾

–40

(1) All voltages are with respect to the GND pin.

(2) T_J-MAX-OP= (T_A(MAX)+ (P_D(MAX)× R_θJA)).

7.4 Thermal Information

LP5912

DRV (WSON)

6 PINS

71.2⁽³⁾

93.7

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance, High-K⁽²⁾

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

40.7

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

2.5

ψ_JB

41.1

R_JC(bot)

11.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) Thermal resistance value R_θJAis based on the EIA/JEDEC High-K printed circuit board defined by: JESD51-7 - High Effective Thermal

Conductivity Test Board for Leaded Surface Mount Packages.

(3) The PCB for the WSON (DRV) package R_θJAincludes two (2) thermal vias under the exposed thermal pad per EIA/JEDEC JESD51-5.

LP5912

www.ti.com.cn

ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016

7.5 Electrical Characteristics

V_IN= V_OUT(NOM)+ 0.5 V or 1.6 V, whichever is greater; V_EN= 1.3 V, C_IN= 1 µF, C_OUT= 1 µF, I_OUT= 1 mA (unless otherwise

stated).^(1)(2)(3)

PARAMETER

OUTPUT VOLTAGE

TEST CONDITIONS

MIN

TYP

MAX

UNIT

For V_OUT(NOM)≥ 3.3 V:

V_OUT(NOM)+ 0.5 V ≤ V_IN≤ 6.5 V,

–2%

I_OUT= 1 mA to 500 mA

For 1.1 V ≤ V_OUT(NOM)< 3.3 V:

V_OUT(NOM)+ 0.5 V ≤ V_IN≤ 6.5 V,

I_OUT= 1 mA to 500 mA

Output voltage tolerance

–3%

For V_OUT(NOM)< 1.1 V:

1.6 V ≤ V_IN≤ 6.5 V,

ΔV_OUT

I_OUT= 1 mA to 500 mA

For V_OUT(NOM)≥ 1.1V:

V_OUT(NOM)+ 0.5 V ≤ V_IN≤ 6.5 V

Line regulation

Load regulation

0.8

%/V

For V_OUT(NOM)< 1.1V :

1.6 V ≤ V_IN≤ 6.5 V

I_OUT= 1 mA to 500 mA

0.0022

%/mA

CURRENT LEVELS

I_SCShort-circuit current limit

I_RO

T_J= 25°C, see⁽⁴⁾

Reverse leakage current⁽⁵⁾V_EN= V_IN= 0 V, V_OUT= 5.5 V

700

900

1100

150

µA

V_EN= 1.3 V, I_OUT= 0 mA

Quiescent current⁽⁶⁾

I_Q

µA

V_EN= 1.3 V, I_OUT= 500 mA

400

600

V_EN= 0 V

0.2

1.5

Quiescent current,

–40°C ≤ T_J≤ 85°C

I_Q(SD)

µA

shutdown mode⁽⁶⁾

V_EN= 0 V

0.2

I_G

VDO DROPOUT VOLTAGE

Ground current⁽⁷⁾

V_EN= 1.3 V, I_OUT= 0 mA

I_OUT= 500 mA, 1.6 V ≤ V_OUT(NOM)< 3.3 V

I_OUT= 500 mA, 3.3 V ≤ V_OUT(NOM)≤ 5.5 V

170

250

180

V_DO

Dropout voltage⁽⁸⁾

(1) All voltages are with respect to the device GND pin, unless otherwise stated.

(2) Minimum and maximum limits are ensured through test, design, or statistical correlation over the junction temperature (T_J) range of

–40°C to +125°C, unless otherwise stated. Typical values represent the most likely parametric norm at T_A= 25°C, and are provided for

reference purposes only.

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP

125°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the

part/package in the application (R_θJA), as given by the following equation: T_A-MAX= T_J-MAX-OP– (R_θJA× P_D-MAX).

(4) Short-circuit current (I_SC) is equivalent to current limit. To minimize thermal effects during testing, I_SCis measured with V_OUTpulled to

100 mV below its nominal voltage.

(5) Reverse current (I_RO) is measured at the IN pin.

(6) Quiescent current is defined here as the difference in current between the input voltage source and the load at V_OUT

(7) Ground current is defined here as the total current flowing to ground as a result of all input voltages applied to the device.

(8) Dropout voltage (V_DO) is the voltage difference between the input and the output at which the output voltage drops to 150 mV below its

nominal value when V_IN= V_OUT+ 0.5 V. Dropout voltage is not a valid condition for output voltages less than 1.6 V as compliance with

the minimum operating voltage requirement cannot be assured.

LP5912

ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016

www.ti.com.cn

Electrical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.5 V or 1.6 V, whichever is greater; V_EN= 1.3 V, C_IN= 1 µF, C_OUT= 1 µF, I_OUT= 1 mA (unless otherwise

stated).^(1)(2)(3)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIN to VOUT RIPPLE REJECTION

ƒ = 100 Hz, V_OUT≥ 1.1 V, I_OUT= 20 mA

ƒ = 1 kHz, V_OUT≥ 1.1 V, I_OUT= 20 mA

ƒ = 10 kHz, V_OUT≥ 1.1 V, I_OUT= 20 mA

ƒ = 100 kHz, V_OUT≥ 1.1 V, I_OUT= 20 mA

ƒ = 100 Hz, 0.8 V < V_OUT< 1.1 V, I_OUT= 20 mA

ƒ = 1 kHz, 0.8 V < V_OUT< 1.1 V, I_OUT= 20 mA

ƒ = 10 kHz, 0.8 V < V_OUT< 1.1 V, I_OUT= 20 mA

ƒ = 100 kHz, 0.8 V < V_OUT< 1.1 V, I_OUT= 20 mA

Power Supply Rejection

PSRR

Ratio⁽⁹⁾

OUTPUT NOISE VOLTAGE

I_OUT= 1 mA, BW = 10 Hz to 100 kHz

I_OUT= 500 mA, BW = 10 Hz to 100 kHz

e_N

Noise voltage

µV_RMS

THERMAL SHUTDOWN

Thermal shutdown

temperature

T_SD

160

°C

Thermal shutdown

hysteresis

T_HYS

LOGIC INPUT THRESHOLDS

V_IN= 1.6 V to 6.5 V

V_ENfalling until device is disabled

V_EN(OFF)

V_EN(ON)

OFF Threshold

ON Threshold

0.3

1.6 V ≤ V_IN≤ 6.5 V

V_ENrising until device is enabled

1.3

V_EN= 6.5 V, V_IN= 6.5 V

V_EN= 0 V, V_IN= 3.3 V

2.5

I_EN

Input current at EN pin⁽¹⁰⁾

PG high threshold (% of

µA

0.001

PG_HTH

PG_LTH

V_OL(PG)

94%

90%

nominal V_OUT

PG low threshold (% of

nominal V_OUT

)

PG pin low-level output

voltage

V_OUT< PG_LTH, sink current = 1 mA

100

I_lKG(PG)

t_PGD

PG pin leakage current

PG delay time

V_OUT< PG_HTH, V_PG= 6.5 V

µA

µs

Time from V_OUT> PG threshold to PG toggling

140

(9) This specification is ensured by design.

(10) There is a 3-MΩ pulldown resistor between the EN pin and GND pin on the device.

LP5912

www.ti.com.cn

ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016

Electrical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.5 V or 1.6 V, whichever is greater; V_EN= 1.3 V, C_IN= 1 µF, C_OUT= 1 µF, I_OUT= 1 mA (unless otherwise

stated).^(1)(2)(3)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TRANSITION CHARACTERISTICS

For V_IN↑ and V_OUT(NOM)≥ 1.1 V:

V_IN= (V_OUT(NOM)+ 0.5 V) to (V_OUT(NOM)+ 1.1 V)

V_INt_rise= 30 µs

For V_IN↑ and V_OUT(NOM)< 1.1 V:

V_IN= 1.6 V to 2.2 V

V_INt_rise= 30 µs

Line transients⁽⁹⁾

For V_IN↓ and V_OUT(NOM) ≥ 1.1 V

V_IN= (V_OUT(NOM)+ 1.1 V) to (V_OUT(NOM)+ 0.5 V)

V_INt_fall= 30 µs

ΔV_OUT

–1

For V_IN↓ and V_OUT(NOM) < 1.1 V:

V_IN= 2.2 V to 1.6 V

V_INt_fall= 30 µs

I_OUT= 5 mA to 500 mA

I_OUTt_rise= 10 µs

–45

Load transients⁽⁹⁾

I_OUT= 500 mA to 5 mA

I_OUTt_fall= 10 µs

Overshoot on start-up⁽⁹⁾

Stated as a percentage of V_OUT(NOM)

Time from V_EN> V_EN(ON)to V_OUT= 95% of

V_OUT(NOM)

t_ON

Turnon time

200

100

µs

OUTPUT AUTO DISCHARGE RATE

Output discharge pull-down

resistance

R_AD

V_EN= 0 V, V_IN= 3.6 V

7.6 Output and Input Capacitors

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Input capacitance⁽²⁾

Output capacitance⁽²⁾

Output voltage⁽²⁾

TEST CONDITIONS

MIN⁽¹⁾

TYP

MAX

UNIT

µF

C_IN

0.7

Capacitance for stability

C_OUT

ESR

µF

500

mΩ

(1) The minimum capacitance must be greater than 0.5 μF over full range of operating conditions. The capacitor tolerance must be 30% or

better over the full temperature range. The full range of operating conditions for the capacitor in the application must be considered

during device selection to ensure this minimum capacitance specification is met. X7R capacitors are recommended however capacitor

types X5R, Y5V, and Z5U may be used with consideration of the application conditions.

(2) This specification is verified by design.

LP5912

ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016

www.ti.com.cn

7.7 Typical Characteristics

Unless otherwise stated: V_IN= V_OUT+ 0.5 V, V_EN= V_IN, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, T_J= 25°C, unless otherwise

stated.

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

-0.1

V_OUTat I_OUT= 1mA

V_PGat I_OUT= 1mA

V_OUTat I_OUT= 500 mA

V_PGat I_OUT= 500 mA

V_EN(ON)

V_EN(OFF)

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Input Voltage (V)

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Input Voltage (V)

D001

D002

Figure 1. V_ENThresholds vs Input Voltage

Figure 2. LP5912-0.9 Output Voltage, V_PGvs Input Voltage

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

3.5

V_OUTat I_OUT=1 mA

V_PGat I_OUT=1 mA

V_OUTat I_OUT= 500 mA

V_PGat I_OUT= 500 mA

V_OUTat I_OUT= 1mA

V_PGat I_OUT= 1mA

V_OUTat I_OUT= 500 mA

V_PGat I_OUT= 500mA

3.0

2.5

2.0

1.5

1.0

0.5

0.0

-0.5

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

Input Voltage (V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Input Voltage (V)

D003

D004

Figure 3. LP5912-1.8 Output Voltage, V_PGvs Input Voltage

Figure 4. LP5912-3.3 Output Voltage, V_PGvs Input Voltage

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

0.4

0.2

0.0

V_IN

V_OUT

V_PG

V_IN

V_OUT

V_PG

50 100 150 200 250 300 350 400 450 500

Time (ms)

D005

D006

V_IN= 0 V to 1.6 V

I_OUT= 1 mA

V_IN= 0 V to 1.6 V

I_OUT= 500 mA

Figure 5. LP5912-0.9 Power Up

Figure 6. LP5912-0.9 Power Up

LP5912

www.ti.com.cn

ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016

Typical Characteristics (continued)

Unless otherwise stated: V_IN= V_OUT+ 0.5 V, V_EN= V_IN, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, T_J= 25°C, unless otherwise

stated.

3.0

2.5

2.0

1.5

1.0

0.5

0.0

3.0

2.5

2.0

1.5

1.0

0.5

0.0

V_IN

V_OUT

V_PG

V_IN

V_OUT

V_PG

50 100 150 200 250 300 350 400 450 500

Time (ms)

D007

D008

V_IN= 0 V to 2.3 V

I_OUT= 1 mA

V_IN= 0 V to 2.3 V

I_OUT= 500 mA

Figure 7. LP5912-1.8 Power Up

Figure 8. LP5912-1.8 Power Up

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

V_IN

V_OUT

V_PG

V_IN

V_OUT

V_PG

50 100 150 200 250 300 350 400 450 500

Time (ms)

D009

D010

V_IN= 0 V to 3.8 V

I_OUT= 1 mA

V_IN= 0 V to 3.8 V

I_OUT= 500 mA

Figure 9. LP5912-3.3 Power Up

Figure 10. LP5912-3.3 Power Up

T_A= +125°C

T_A= +85°C

T_A= +25°C

T_A= -40°C

T_A= +125°C

T_A= +85°C

T_A= +25°C

T_A= -40°C

0.5

1.5

2.5

3.5

4.5

5.5

6.5

0.5

1.5

2.5

3.5

4.5

5.5

6.5

V_IN(V)

D051

D052

I_OUT= 0 mA

Figure 12. LP5912-1.8 I_Q(No Load) vs V_IN

Figure 11. LP5912-0.9 I_Q(No Load) vs V_IN

LP5912

ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016

www.ti.com.cn

Typical Characteristics (continued)

Unless otherwise stated: V_IN= V_OUT+ 0.5 V, V_EN= V_IN, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, T_J= 25°C, unless otherwise

stated.

T_A= +125°C

T_A= +85°C

T_A= +25°C

T_A= -40°C

0.5

1.5

2.5

3.5

4.5

5.5

6.5

V_IN(V)

D053

I_OUT= 0 mA

V_EN= 0 V

Figure 14. LP5912-0.9 I_Q(SD)vs V_IN

Figure 13. LP5912-3.3 I_Q(No Load) vs V_IN

V_EN= 0 V

Figure 15. LP5912-1.8 I_Q(SD)vs V_IN

V_EN= 0 V

Figure 16. LP5912-3.3 I_Q(SD)vs V_IN

500

450

400

350

300

250

200

150

100

500

450

400

350

300

250

200

150

100

T_A= -40°C

T_A= +25°C

T_A= +85°C

T_A= +125°C

T_A= +25°C

T_A= +85°C

T_A= +125°C

50 100 150 200 250 300 350 400 450 500

I_OUT(mA)

50 100 150 200 250 300 350 400 450 500

I_OUT(mA)

D057

D058

V_IN= 1.6 V

Figure 17. LP5912-0.9 I_GNDvs I_OUT

Figure 18. LP5912-1.8 I_GNDvs I_OUT

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Typical Characteristics (continued)

Unless otherwise stated: V_IN= V_OUT+ 0.5 V, V_EN= V_IN, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, T_J= 25°C, unless otherwise

stated.

500

450

400

350

300

250

200

150

100

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

T_A= -40°C

T_A= +25°C

T_A= +85°C

T_A= +125°C

50 100 150 200 250 300 350 400 450 500

I_OUT(mA)

10 20

100

1000

10000 100000 1000000 1E+7

Frequency (Hz)

D059

D011

V_IN= 1.6 V

I_OUT= 20 mA

Figure 19. LP5912-3.3 I_GNDvs I_OUT

Figure 20. LP5912-0.9 PSRR vs Frequency

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

I_OUT= 1 mA

I_OUT= 10 mA

I_OUT= 100 mA

I_OUT= 500 mA

-20

-40

-60

-80

-100

-120

10 20

100

1000

10000 100000 1000000 1E+7

10 20

100

1000

10000 100000 1000000 1E+7

Frequency (Hz)

D012

D013

V_IN= 1.6 V

I_OUT= 20 mA

Figure 21. LP5912-0.9 PSRR vs Frequency

Figure 22. LP5912-1.8 PSRR vs Frequency

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

I_OUT= 1 mA

I_OUT= 10 mA

I_OUT= 100 mA

I_OUT= 500 mA

10 20

100

1000

10000 100000 1000000 1E+7

10 20

100

1000

10000 100000 1000000 1E+7

Frequency (Hz)

D014

D015

I_OUT= 20 mA

Figure 23. LP5912-1.8 PSRR vs Frequency

Figure 24. LP5912-3.3 PSRR vs Frequency

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Typical Characteristics (continued)

Unless otherwise stated: V_IN= V_OUT+ 0.5 V, V_EN= V_IN, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, T_J= 25°C, unless otherwise

stated.

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

0.8

0.6

0.4

0.2

2.4

2.3

2.2

2.1

I_OUT= 1 mA

D V_OUT(mV)

V_IN(V)

I_OUT= 10 mA

I_OUT= 100 mA

I_OUT= 500 mA

1.9

1.8

1.7

1.6

1.5

1.4

-0.2

-0.4

-0.6

-0.8

-1

10 20

100

1000

10000 100000 1000000 1E+7

50 100 150 200 250 300 350 400 450 500

Time (µs)

Frequency (Hz)

D016

D017

V_IN= 1.6 V to 2.2 V

t_rise= 30 µs

Figure 25. LP5912-3.3 PSRR vs Frequency

Figure 26. LP5912-0.9 Line Transient

0.8

0.6

0.4

0.2

2.4

0.8

0.6

0.4

0.2

3.1

DV_OUT(mV)

V_IN(V)

D V_OUT(mV)

V_IN(V)

2.3

2.2

2.1

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

1.9

1.8

1.7

1.6

1.5

1.4

-0.2

-0.4

-0.6

-0.8

-1

-0.2

-0.4

-0.6

-0.8

-1

50 100 150 200 250 300 350 400 450 500

Time (µs)

Time (ms)

D018

D019

V_IN= 2.2 V to 1.6 V

t_fall= 30 µs

V_IN= 2.3 V to 2.9 V

t_rise= 30 µs

Figure 27. LP5912-0.9 Line Transient

Figure 28. LP5912-1.8 Line Transient

0.8

0.6

0.4

0.2

3.1

0.8

0.6

0.4

0.2

4.6

4.5

4.4

4.3

4.2

4.1

D V_OUT(mV)

V_IN(V)

D V_OUT(mV)

V_IN(V)

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

-0.2

-0.4

-0.6

-0.8

-1

-0.2

-0.4

-0.6

-0.8

-1

3.9

3.8

3.7

3.6

50 100 150 200 250 300 350 400 450 500

Time (µs)

50 100 150 200 250 300 350 400 450 500

Time (µs)

D020

D021

V_IN= 2.9 V to 2.3 V

t_fall= 30 µs

V_IN= 3.8 V to 4.4 V

t_rise= 30 µs

Figure 29. LP5912-1.8 Line Transient

Figure 30. LP5912-3.3 Line Transient

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Typical Characteristics (continued)

Unless otherwise stated: V_IN= V_OUT+ 0.5 V, V_EN= V_IN, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, T_J= 25°C, unless otherwise

stated.

0.8

0.6

0.4

0.2

4.6

4.5

4.4

4.3

4.2

4.1

600

500

400

300

200

100

D V_OUT(mV)

V_IN(V)

D V_OUT(mV)

I_OUT(mA)

-0.2

-0.4

-0.6

-0.8

-1

-20

-40

-60

3.9

3.8

3.7

3.6

50 100 150 200 250 300 350 400 450 500

Time (µs)

80 100 120 140 160 180 200

Time (µs)

D022

D023

V_IN= 4.4 V to 3.8 V

t_fall= 30 µs

V_IN= 1.6 V

I_OUT= 5 mA to 500 mA

t_rise= 10 µs

Figure 31. LP5912-3.3 Line Transient

Figure 32. LP5912-0.9 Load Transient Response

600

500

400

300

200

100

600

D V_OUT(mV)

I_OUT(mA)

D V_OUT(mV)

I_OUT(mA)

500

400

300

200

100

-20

-40

-60

-20

-40

-60

80 100 120 140 160 180 200

Time (µs)

80 100 120 140 160 180 200

Time (µs)

D024

D025

V_IN= 1.6 V

I_OUT= 500 mA to 5 mA

t_fall= 10 µs

I_OUT= 5 mA to 500 mA

t_rise= 10 µs

Figure 33. LP5912-0.9 Load Transient Response

Figure 34. LP5912-1.8 Load Transient Response

600

D V_OUT(mV)

I_OUT(mA)

D V_OUT(mV)

I_OUT(mA)

500

400

300

200

100

500

400

300

200

100

-20

-40

-60

-20

-40

-60

80 100 120 140 160 180 200

Time (µs)

80 100 120 140 160 180 200

Time (µs)

D026

D027

I_OUT= 500 mA to 5 mA

t_fall= 10 µs

I_OUT= 5 mA to 500 mA

t_rise= 10 µs

Figure 35. LP5912-1.8 Load Transient Response

Figure 36. LP5912-3.3 Load Transient Response

LP5912

ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016

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Typical Characteristics (continued)

Unless otherwise stated: V_IN= V_OUT+ 0.5 V, V_EN= V_IN, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, T_J= 25°C, unless otherwise

stated.

2.5

600

500

400

300

200

100

V_EN(V)

V_OUT(V)

V_PG(V)

D V_OUT(mV)

I_OUT(mA)

1.5

-20

-40

-60

0.5

80 100 120 140 160 180 200

Time (µs)

50 100 150 200 250 300 350 400 450 500

Time (µs)

D028

D031

I_OUT= 500 mA to 5 mA

t_fall= 10 µs

I_OUT= 0 mA

C_OUT= 1 µF

Figure 37. LP5912-3.3 Load Transient Response

Figure 38. LP5912-1.8 V_OUTvs V_EN(ON)

2.5

V_EN(V)

V_OUT(V)

V_PG(V)

V_EN(V)

V_OUT(V)

V_PG(V)

1.5

0.5

50 100 150 200 250 300 350 400 450 500

Time (µs)

50 100 150 200 250 300 350 400 450 500

Time (µs)

D032

D033

I_OUT= 0 mA

C_OUT= 1 µF

I_OUT= 1 mA

C_OUT= 1 µF

Figure 40. LP5912-1.8 V_OUTvs V_EN(ON)

Figure 39. LP5912-1.8 V_OUTvs V_EN(OFF)

2.5

V_EN(V)

V_OUT(V)

V_PG(V)

V_EN(V)

V_OUT(V)

V_PG(V)

1.5

0.5

50 100 150 200 250 300 350 400 450 500

Time (µs)

50 100 150 200 250 300 350 400 450 500

Time (µs)

D034

D035

I_OUT= 1 mA

C_OUT= 1 µF

Figure 41. LP5912-1.8 V_OUTvs V_EN(OFF)

I_OUT= 500 mA

C_OUT= 1 µF

Figure 42. LP5912-1.8 V_OUTvs V_EN(ON)

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ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016

Typical Characteristics (continued)

Unless otherwise stated: V_IN= V_OUT+ 0.5 V, V_EN= V_IN, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, T_J= 25°C, unless otherwise

stated.

225

200

175

150

125

100

2.2

V_EN(V)

V_OUT(V)

V_PG(V)

1.8

1.6

1.4

1.2

0.8

0.6

0.4

0.2

-40°C

25°C

85°C

125°C

Time (µs)

50 100 150 200 250 300 350 400 450 500

I_OUT(mA)

D036

D041

I_OUT= 500 mA

C_OUT= 1 µF

Figure 43. LP5912-1.8 V_OUTvs V_EN(OFF)

Figure 44. LP5912-1.8 Dropout Voltage (V_DO) vs I_OUT

225

200

175

150

125

100

1.2

-40°C

1 mA

500 mA

25°C

85°C

125°C

0.8

0.6

0.4

0.2

50 100 150 200 250 300 350 400 450 500

I_OUT(mA)

100

1000

Frequency (Hz)

10000

100000

1000000

D042

D043

V_IN= 1.6 V

Figure 45. LP5912-3.3 Dropout Voltage (V_DO) vs I_OUT

Figure 46. LP5912-0.9 Noise vs Frequency

1.2

1 mA

500 mA

1 mA

500 mA

0.8

0.6

0.4

0.2

0.8

0.6

0.4

0.2

100

1000

10000

100000

1000000

100

1000

10000

100000

1000000

Frequency (Hz)

D044

D045

Figure 47. LP5912-1.8 Noise vs Frequency

Figure 48. LP5912-3.3 Noise vs Frequency

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Typical Characteristics (continued)

Unless otherwise stated: V_IN= V_OUT+ 0.5 V, V_EN= V_IN, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, T_J= 25°C, unless otherwise

stated.

500

400

300

200

100

300

280

260

240

220

200

180

160

140

120

100

V_EN(V)

V_OUT(V)

I_IN(mA)

-50

50 100 150 200 250 300 350 400 450

-50

-25

100

125

Time (ms)

D061

Junction Temperature (°C)

D060

C_IN= Open

I_OUT= 500 mA

C_OUT= 1 µF

I_OUT= 0 mA (No Load)

Figure 49. LP5912-3.3 Turnon Time vs Junction

Temperature

Figure 50. LP5912-3.3 In-Rush Current

4.5

100

1.5

V_EN(V)

V_OUT(V)

I_IN(mA)

V_EN(V)

V_OUT(V)

I_IN(A)

4.5

1.35

1.2

3.5

1.05

0.9

2.5

0.75

0.6

1.5

0.45

0.3

0.5

0.15

-50

50 100 150 200 250 300 350 400 450

-50

50 100 150 200 250 300 350 400 450

Time (ms)

D062

D063

C_IN= Open

I_OUT= 1 mA

C_OUT= 1 µF

C_IN= Open

I_OUT= 500 mA

C_OUT= 10 µF

Figure 51. LP5912-3.3 In-Rush Current

Figure 52. LP5912-3.3 In-Rush Current

1.5

V_EN(V)

V_OUT(V)

I_IN(A)

4.5

1.35

1.2

3.5

1.05

0.9

2.5

0.75

0.6

1.5

0.45

0.3

0.5

0.15

-50

50 100 150 200 250 300 350 400 450

Time (ms)

D064

C_IN= Open

I_OUT= 1 mA

C_OUT= 10 µF

Figure 53. LP5912-3.3 In-Rush Current

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ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016

8 Detailed Description

8.1 Overview

The LP5912 is a low-noise, high PSRR, LDO capable of sourcing a 500-mA load. The LP5912 can operate down

to 1.6-V input voltage and 0.8-V output voltage. This combination of low noise, high PSRR, and low output

voltage makes the device an ideal low dropout (LDO) regulator to power a multitude of loads from noise-sensitive

communication components to battery-powered system.

The LP5912 Functional Block Diagram contains several features, including:

•

Internal output resistor divider feedback;

Small size and low-noise internal protection circuit current limit;

Reverse current protection;

Current limit and in-rush current protection;

Thermal shutdown;

Output auto discharge for fast turnoff; and

Power-good output, with fixed 140-µs typical delay.

8.2 Functional Block Diagram

Current

Limit

OUT

R_AD

100 ꢀ

45 kꢀ

V_IN

Output

Discharge

V_BG

Control

140-µs

DELAY

3 Mꢀ

GND

8.3 Feature Description

8.3.1 Enable (EN)

The LP5912 EN pin is internally held low by a 3-MΩ resistor to GND. The EN pin voltage must be higher than the

V_EN(ON)threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage

must be lower than the V_EN(OFF)threshold to ensure that the device is fully disabled and the automatic output

discharge is activated.

When the device is disabled the output stage is disabled, the PG output pin is low, and the output automatic

discharge is ON.

LP5912

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Feature Description (continued)

8.3.2 Output Automatic Discharge (R_AD

)

The LP5912 output employs an internal 100-Ω (typical) pulldown resistance to discharge the output when the EN

pin is low. Note that if the LP5912 EN pin is low (the device is OFF) and the OUT pin is held high by a secondary

supply, current flows from the secondary supply through the automatic discharge pulldown resistor to ground.

8.3.3 Reverse Current Protection (I_RO

)

The LP5912 input is protected against reverse current when output voltage is higher than the input. In the event

that extra output capacitance is used at the output, a power-down transient at the input would normally cause a

large reverse current through a conventional regulator. The LP5912 includes a reverse voltage detector that trips

when V_INdrops below V_OUT, shutting off the regulator and opening the PMOS body diode connection, preventing

any reverse current from the OUT pin from flowing to the IN pin.

If the LP5912 EN pin is low (the LP5912 is OFF) and the OUT pin is held high by a secondary supply, current

flows from the secondary supply through the automatic discharge pulldown resistor to ground. This is not reverse

current, this is automatic discharge pulldown current.

Note that reverse current (I_RO) is measured at the IN pin.

8.3.4 Internal Current Limit (I_SC

)

The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The

LDO is not designed to operate continuously at the I_SCcurrent limit. During a current-limit event, the LDO

sources constant current. Therefore, the output voltage falls when load impedance decreases. Note also that if a

current limit occurs and the resulting output voltage is low, excessive power may be dissipated across the LDO,

resulting in a thermal shutdown of the output.

8.3.5 Thermal Overload Protection (T_SD

)

Thermal shutdown disables the output when the junction temperature rises to approximately 160°C, which allows

the device to cool. When the junction temperature cools to approximately 145°C, the output circuitry enables.

Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may

cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a

result of overheating.

8.3.6 Power-Good Output (PG)

The LP5912 device has a power-good function that works by toggling the state of the PG output pin. When the

output voltage falls below the PG threshold voltage (PG_LTH), the PG pin open-drain output engages (low

impedance to GND). When the output voltage rises above the PG threshold voltage (PGV_HTH), the PG pin

becomes high impedance. By connecting a pullup resistor to an external supply, any downstream device can

receive PG as a logic signal. Make sure that the external pullup supply voltage results in a valid logic signal for

the receiving device or devices. Use a pullup resistor from 10 kΩ to 100 kΩ for best results.

The input supply, V_IN, must be no less than the minimum operating voltage of 1.6 V to ensure that the PG pin

output status is valid. The PG pin output status is undefined when V_INis less than 1.6 V.

In power-good function, the PG output pin being pulled high is typically delayed 140 µs after the output voltage

rises above the PG_HTHthreshold voltage. If the output voltage rises above the PG_HTHthreshold and then falls

below the PG_LTHthreshold voltage the PG pin falls immediately with no delay time.

If the PG function is not needed, the pullup resistor can be eliminated, and the PG pin can be either connected to

ground or left floating.

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8.4 Device Functional Modes

8.4.1 Enable (EN)

The LP5912 EN pin is internally held low by a 3-MΩ resistor to GND. The EN pin voltage must be higher than the

V_EN(ON)threshold to ensure that the device is fully enabled under all operating conditions. When the EN pin

voltage is lower than the V_EN(OFF)threshold, the output stage is disabled, the PG pin goes low, and the output

automatic discharge circuit is activated. Any charge on the OUT pin is discharged to ground through the internal

100-Ω (typical) output auto discharge pulldown resistance.

8.4.2 Minimum Operating Input Voltage (V_IN)

The LP5912 device does not include any dedicated UVLO circuit. The device internal circuit is not fully functional

until V_INis at least 1.6 V. The output voltage is not regulated until V_INhas reached at least the greater of 1.6 V or

(V_OUT+ V_DO).

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9 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers must

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LP5912 is designed to meet the requirements of RF and analog circuits, by providing low noise, high PSRR,

low quiescent current, and low line or load transient response. The device offers excellent noise performance

without the need for a noise bypass capacitor and is stable with input and output capacitors with a value of 1 μF.

The device delivers this performance in an industry standard WSON package, which for this device is specified

with an operating junction temperature (T_J) of –40°C to +125°C.

9.2 Typical Application

Figure 54 shows the typical application circuit for the LP5912. Input and output capacitances may need to be

increased above the 1-μF minimum for some applications.

V_IN

V_OUT

OUT

C_IN

LP5912

C_OUT

GND

R_PG

V_EN

V_PG

Figure 54. LP5912 Typical Application

9.2.1 Design Requirements

For typical RF linear regulator applications, use the parameters listed in Table 1.

Table 1. Design Parameters

DESIGN PARAMETER

Input voltage

EXAMPLE VALUE

1.6 to 6.5 V

0.8 to 5.5 V

500 mA

Output voltage

Output current

Output capacitor

1 to 10 µF

Input/output capacitor ESR range

5 mΩ to 500 mΩ

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ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016

9.2.2 Detailed Design Procedure

9.2.2.1 External Capacitors

Like most low-dropout regulators, the LP5912 requires external capacitors for regulator stability. The device is

specifically designed for portable applications requiring minimum board space and smallest components. These

capacitors must be correctly selected for good performance.

9.2.2.2 Input Capacitor

An input capacitor is required for stability. The input capacitor must be at least equal to, or greater than, the

output capacitor for good load-transient performance. A capacitor of at least 1 µF must be connected between

the LP5912 IN pin and ground for stable operation over full load-current range. It is acceptable to have more

output capacitance than input, as long as the input is at least 1 µF.

The input capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean

analog ground. Any good-quality ceramic, tantalum, or film capacitor may be used at the input.

NOTE

To ensure stable operation it is essential that good PCB practices are employed to

minimize ground impedance and keep input inductance low. If these conditions cannot be

met, or if long leads are to be used to connect the battery or other power source to the

LP5912, increasing the value of the input capacitor to at least 10 µF is recommended.

Also, tantalum capacitors can suffer catastrophic failures due to surge current when

connected to a low-impedance source of power (such as a battery or a very large

capacitor). If a tantalum capacitor is used at the input, it must be verified by the

manufacturer to have a surge current rating sufficient for the application. There are no

requirements for the equivalent series resistance (ESR) on the input capacitor, but

tolerance and temperature coefficient must be considered when selecting the capacitor to

ensure the capacitance remains 1 μF ±30% over the entire operating temperature range.

9.2.2.3 Output Capacitor

The LP5912 is designed specifically to work with a very small ceramic output capacitor, typically 1 µF. A ceramic

capacitor (dielectric types X5R or X7R) in the 1-µF to 10-µF range, and with an ESR from 5 mΩ to 500 mΩ, is

suitable in the LP5912 application circuit. For this device the output capacitor must be connected between the

OUT pin with a good connection back to the GND pin.

Tantalum or film capacitors may also be used at the device output, V_OUT, but these are not as attractive for

reasons of size and cost (see Capacitor Characteristics).

The output capacitor must meet the requirement for the minimum value of capacitance and have an ESR value

that is within the range 5 mΩ to 500 mΩ for stability.

9.2.2.4 Capacitor Characteristics

The LP5912 is designed to work with ceramic capacitors on the input and output to take advantage of the

benefits they offer. For capacitance values in the range of 1 µF to 10 µF, ceramic capacitors are the smallest,

least expensive, and have the lowest ESR values, thus making them best for eliminating high frequency noise.

The ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR

requirement for stability for the LP5912.

The preferred choice for temperature coefficient in a ceramic capacitor is X7R. This type of capacitor is the most

stable and holds the capacitance within ±15% over the temperature range. Tantalum capacitors are less

desirable than ceramic for use as output capacitors because they are more expensive when comparing

equivalent capacitance and voltage ratings in the 1-µF to 10-µF range.

Another important consideration is that tantalum capacitors have higher ESR values than equivalent size

ceramics. While it may be possible to find a tantalum capacitor with an ESR value within the stable range, it

would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the

same ESR value. Also, the ESR of a typical tantalum increases about 2:1 as the temperature goes from 25°C

down to –40°C, so some guard band must be allowed.

LP5912

ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016

www.ti.com.cn

9.2.2.5 Remote Capacitor Operation

To ensure stability the LP5912 requires at least a 1-μF capacitor at the OUT pin. There is no strict requirement

about the location of the output capacitor in regards to the LDO OUT pin; the output capacitor may be located 5

to 10 cm away from the LDO. This means that there is no need to have a special capacitor close to the OUT pin

if there are already respective capacitors in the system. This placement flexibility requires that the output

capacitor be connected directly between the LP5912 OUT pin and GND pin with no vias. This remote capacitor

feature can help users to minimize the number of capacitors in the system.

As a good design practice, keep the wiring parasitic inductance at a minimum, which means using as wide as

possible traces from the LDO output to the capacitors, keeping the LDO output trace layer as close to ground

layer as possible, avoiding vias on the path. If there is a need to use vias, implement as many as possible vias

between the connection layers. Keeping parasitic wiring inductance less than 35 nH is recommended. For

applications with fast load transients use an input capacitor equal to, or larger than, the sum of the capacitance

at the output node for the best load-transient performance.

9.2.2.6 Power Dissipation

Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is

critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and

load conditions and can be calculated with Equation 1.

P_D(MAX)= (V_IN(MAX)– V_OUT) × I_OUT

(1)

Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available

voltage drop option that is greater than the dropout voltage (V_DO). However, keep in mind that higher voltage

drops result in better dynamic (that is, PSRR and transient) performance.

On the WSON (DRV) package, the primary conduction path for heat is through the exposed power pad into the

PCB. To ensure the device does not overheat, connect the exposed pad, through thermal vias, to an internal

ground plane with an appropriate amount of copper PCB area.

Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance

(R_θJA) of the combined PCB and device package and the temperature of the ambient air (T_A), according to

Equation 2 or Equation 3:

T_J(MAX)= T_A(MAX)+ (R_θJA× P_D(MAX)

P_D= (T_J(MAX)– T_A(MAX)) / R_θJA

)

(2)

(3)

Unfortunately, this R_θJAis highly dependent on the heat-spreading capability of the particular PCB design, and

therefore varies according to the total copper area, copper weight, and location of the planes. The R_θJArecorded

in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copper-

spreading area, and is to be used only as a relative measure of package thermal performance. For a well-

designed thermal layout, R_θJAis actually the sum of the package junction-to-case (bottom) thermal resistance

(R_θJCbot) plus the thermal resistance contribution by the PCB copper area acting as a heat sink.

LP5912

www.ti.com.cn

ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016

9.2.2.7 Estimating Junction Temperature

The EIA/JEDEC standard recommends the use of psi (Ψ) thermal characteristics to estimate the junction

temperatures of surface mount devices on a typical PCB board application. These characteristics are not true

thermal resistance values, but rather package specific thermal characteristics that offer practical and relative

means of estimating junction temperatures. These psi metrics are determined to be significantly independent of

copper-spreading area. The key thermal characteristics (Ψ_JTand Ψ_JB) are given in Thermal Information and are

used in accordance with Equation 4 or Equation 5.

T_J(MAX)= T_TOP+ (Ψ_JT× P_D(MAX)

)

where

•

P_D(MAX)is explained in Equation 3

T_TOPis the temperature measured at the center-top of the device package.

(4)

T_J(MAX)= T_BOARD+ (Ψ_JB× P_D(MAX)

)

where

•

P_D(MAX)is explained in Equation 3.

T_BOARDis the PCB surface temperature measured 1 mm from the device package and centered on the

package edge.

(5)

For more information about the thermal characteristics Ψ_JTand Ψ_JB, see Semiconductor and IC Package Thermal

Metrics ; for more information about measuring T_TOPand T_BOARD, see Using New Thermal Metrics ; and for more

information about the EIA/JEDEC JESD51 PCB used for validating R_θJA, see the TI Application Report Thermal

Characteristics of Linear and Logic Packages Using JEDEC PCB Designs. These application notes are available

at www.ti.com.

9.2.3 Application Curves

2.5

2.0

1.5

1.0

0.5

0.0

2.5

2.0

1.5

1.0

0.5

0.0

V_EN(V)

V_OUT(V)

V_PG(V)

V_EN(V)

V_OUT(V)

V_PG(V)

50 100 150 200 250 300 350 400 450 500

Time (µs)

D029

D030

V_IN= 2.3 V

I_OUT= 500 mA

C_OUT= 1 µF

V_IN= 2.3 V

I_OUT= 500 mA (3.6 Ω)

C_OUT= 1 µF

Figure 55. LP5912-1.8 V_OUTvs V_EN(ON)

Figure 56. LP5912-1.8 V_OUTvs V_EN(OFF)

10 Power Supply Recommendations

This device is designed to operate from an input supply voltage range of 1.6 V to 6.5 V. The input supply must

be well regulated and free of spurious noise. To ensure that the LP5912 output voltage is well regulated and

dynamic performance is optimum, the input supply must be at least V_OUT+ 0.5 V. A minimum capacitor value of

1 µF is required to be within 1 cm of the IN pin.

LP5912

ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

The dynamic performance of the LP5912 is dependant on the layout of the PCB. PCB layout practices that are

adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5912.

Best performance is achieved by placing C_INand C_OUTon the same side of the PCB as the LP5912, and as

close to the package as is practical. The ground connections for C_INand C_OUTmust be back to the LP5912

ground pin using as wide and as short of a copper trace as is practical.

Connections using long trace lengths, narrow trace widths, or connections through vias must be avoided. Such

connections add parasitic inductances and resistance that result in inferior performance especially during

transient conditions.

11.2 Layout Example

Thermal Vias (2)

OUT

C_OUT

C_IN

GND

R_PG

Figure 57. LP5912 Typical Layout

LP5912

www.ti.com.cn

ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016

12 器件和文档支持

12.1 相关文档ꢀ

更多信息，请参见以下文档：

•

《AN1187 无引线框架封装 (LLP)》

半导体和集成电路 (IC) 封装热度量

《使用新的热指标》

《采用 JEDEC PCB 设计的线性和逻辑封装散热特性》

12.2 接收文档更新通知

如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册

后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。

12.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LP5912-0.9DRVR

LP5912-0.9DRVT

LP5912-1.0DRVR

LP5912-1.0DRVT

LP5912-1.1DRVR

LP5912-1.1DRVT

LP5912-1.2DRVR

LP5912-1.2DRVT

LP5912-1.5DRVR

LP5912-1.5DRVT

LP5912-1.8DRVR

LP5912-1.8DRVT

LP5912-2.5DRVR

LP5912-2.5DRVT

LP5912-2.8DRVR

LP5912-2.8DRVT

LP5912-3.0DRVR

LP5912-3.0DRVT

LP5912-3.3DRVR

LP5912-3.3DRVT

ACTIVE

WSON

DRV

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

12-A

1NPU

12-H

12-B

12-C

12-D

1NQU

12-E

12-G

12-F

NIPDAU

-40 to 125

250

RoHS & Green

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LP5912-5.0DRVR

LP5912-5.0DRVT

ACTIVE

WSON

DRV

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

12-I

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

10-Dec-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LP5912-0.9DRVR

LP5912-0.9DRVT

LP5912-1.0DRVR

LP5912-1.0DRVT

LP5912-1.1DRVR

LP5912-1.1DRVT

LP5912-1.2DRVR

LP5912-1.2DRVT

LP5912-1.5DRVR

LP5912-1.5DRVT

WSON

DRV

3000

250

180.0

8.4

2.3

1.15

4.0

8.0

250

3000

250

3000

250

3000

250

3000

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

10-Dec-2022

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LP5912-1.8DRVR

LP5912-1.8DRVT

LP5912-2.5DRVR

LP5912-2.5DRVT

LP5912-2.8DRVR

LP5912-2.8DRVT

LP5912-3.0DRVR

LP5912-3.0DRVT

LP5912-3.3DRVR

LP5912-3.3DRVT

LP5912-5.0DRVR

LP5912-5.0DRVT

WSON

DRV

3000

250

180.0

8.4

2.3

1.15

4.0

8.0

250

3000

250

3000

250

3000

250

3000

250

3000

250

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

10-Dec-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LP5912-0.9DRVR

LP5912-0.9DRVT

LP5912-1.0DRVR

LP5912-1.0DRVT

LP5912-1.1DRVR

LP5912-1.1DRVT

LP5912-1.2DRVR

LP5912-1.2DRVT

LP5912-1.5DRVR

LP5912-1.5DRVT

LP5912-1.8DRVR

WSON

DRV

3000

250

182.0

210.0

182.0

210.0

182.0

210.0

182.0

210.0

182.0

210.0

182.0

210.0

182.0

210.0

182.0

185.0

182.0

185.0

182.0

185.0

182.0

185.0

182.0

185.0

182.0

185.0

182.0

185.0

20.0

35.0

20.0

35.0

20.0

35.0

20.0

35.0

20.0

35.0

20.0

35.0

20.0

35.0

250

3000

250

3000

250

3000

250

3000

250

3000

Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

10-Dec-2022

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LP5912-1.8DRVT

LP5912-2.5DRVR

LP5912-2.5DRVT

LP5912-2.8DRVR

LP5912-2.8DRVT

LP5912-3.0DRVR

LP5912-3.0DRVT

LP5912-3.3DRVR

LP5912-3.3DRVT

LP5912-5.0DRVR

LP5912-5.0DRVT

WSON

DRV

250

182.0

210.0

182.0

210.0

182.0

210.0

182.0

210.0

182.0

210.0

182.0

185.0

182.0

185.0

182.0

185.0

182.0

185.0

182.0

185.0

20.0

35.0

20.0

35.0

20.0

35.0

20.0

35.0

20.0

35.0

3000

250

3000

250

3000

250

3000

250

3000

250

Pack Materials-Page 4

GENERIC PACKAGE VIEW

DRV 6

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4206925/F

PACKAGE OUTLINE

DRV0006A

WSON - 0.8 mm max height

SCALE 5.500

PLASTIC SMALL OUTLINE - NO LEAD

2.1

1.9

PIN 1 INDEX AREA

2.1

1.9

0.8

0.7

SEATING PLANE

0.08 C

(0.2) TYP

0.05

0.00

0.1

EXPOSED

THERMAL PAD

1.3

1.6 0.1

4X 0.65

0.35

0.25

PIN 1 ID

(OPTIONAL)

0.3

0.2

0.1

C A

0.05

4222173/B 04/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DRV0006A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

6X (0.45)

6X (0.3)

(1)

SYMM

(1.6)

(1.1)

4X (0.65)

SYMM

(1.95)

(R0.05) TYP

(

0.2) VIA

TYP

LAND PATTERN EXAMPLE

SCALE:25X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222173/B 04/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.

www.ti.com

EXAMPLE STENCIL DESIGN

DRV0006A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

SYMM

6X (0.45)

METAL

6X (0.3)

(0.45)

SYMM

4X (0.65)

(0.7)

(R0.05) TYP

(1)

(1.95)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD #7

88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:30X

4222173/B 04/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

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您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LP5912-0.9DRVT [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E