LP5912-2.5DRVT [TI]
具有反向电流保护功能的 500mA、低噪声、低 IQ、低压降稳压器 | DRV | 6 | -40 to 125;型号: | LP5912-2.5DRVT |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有反向电流保护功能的 500mA、低噪声、低 IQ、低压降稳压器 | DRV | 6 | -40 to 125 稳压器 |
文件: | 总36页 (文件大小:2841K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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LP5912
ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016
LP5912 500mA 低噪声、低 IQ LDO
1 特性
3 说明
1
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输入电压范围:1.6V 至 6.5V
LP5912 是一款能提供高达 500mA 输出电流的低噪声
LDO。LP5912 器件专为满足射频 (RF) 和模拟电路的
要求而设计,具备低噪声、高 PSRR、低静态电流以
及低线路或负载瞬态响应等特性。LP5912 无需噪声旁
路电容便可提供出色的噪声性能,并且支持远距离安置
输出电容。
输出电压范围:0.8V 至 5.5V
输出电流最高达 500 mA
低输出电压噪声:12µVRMS 典型值
1kHz 时的电源抑制比 (PSRR):75dB(典型值)
输出电压容差 (VOUT ≥ 3.3V):±2%
低 IQ(使能时,无负载):30µA(典型值)
此器件适合与 1µF 输入和 1µF 输出陶瓷电容搭配使用
(无需独立的噪声旁路电容)。
低压降 (VOUT ≥ 3.3V):500mA 负载时典型值为
95mV
其固定输出电压介于 0.8V 和 5.5V 之间(以 25mV 为
单位增量)。如需特定的电压选项,请联系德州仪器
(TI) 销售代表。
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与 1µF 陶瓷输入和输出电容搭配使用,性能稳定
热过载保护和短路保护
反向电流保护
无需噪声旁路电容
器件信息(1)
自动输出放电实现快速关断
电源正常状态输出具有 140µs 典型延迟
内部软启动限制浪涌电流
器件型号
LP5912
封装
WSON (6)
封装尺寸(标称值)
2.00mm x 2.00mm
(1) 要了解所有可用封装,请参见数据表末尾的封装选项附录
(POA)。
–40°C 至 +125°C 的运行结温范围
空白
空白
空白
空白
空白
2 应用
•
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摄像机模块
传感器
HiFi 音频无线电收发器
锁相环 (PLL)/合成器,定时
中等电流,噪声敏感 应用
空格
空格
简化电路原理图
VIN
VOUT
IN
OUT
NC
CIN
LP5912
COUT
GND
RPG
VEN
VPG
EN
PG
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNVSA77
LP5912
ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016
www.ti.com.cn
目录
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 19
Applications and Implementation ...................... 20
9.1 Application Information............................................ 20
9.2 Typical Application .................................................. 20
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Voltage Options ..................................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ..................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions ...................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Output and Input Capacitors..................................... 7
7.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 17
8.1 Overview ................................................................. 17
8.2 Functional Block Diagram ....................................... 17
9
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 器件和文档支持 ..................................................... 25
12.1 相关文档ꢀ ........................................................... 25
12.2 接收文档更新通知 ................................................. 25
12.3 社区资源................................................................ 25
12.4 商标....................................................................... 25
12.5 静电放电警告......................................................... 25
12.6 Glossary................................................................ 25
13 机械、封装和可订购信息....................................... 25
8
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision C (September 2016) to Revision D
Page
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已添加 封装图 ........................................................................................................................................................................ 1
Changes from Revision B (June 2016) to Revision C
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已更改 数据表标题的措辞 ...................................................................................................................................................... 1
已更改 的第一句的措辞说明.................................................................................................................................................... 1
Changes from Revision A (April 2016) to Revision B
Page
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已更改 "第 1 页的“线性稳压器”改为“LDO” .............................................................................................................................. 1
2
Copyright © 2015–2016, Texas Instruments Incorporated
LP5912
www.ti.com.cn
ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016
5 Voltage Options
This device is capable of providing fixed output voltages from 0.8 V to 5.5 V in 25-mV steps. For all available
package and voltage options, see the POA at the end of this datasheet. Contact Texas Instruments Sales for
specific voltage option needs.
6 Pin Configuration and Functions
DRV Package
6-Pin WSON With Thermal Pad
Top View
1
2
3
6
5
4
IN
OUT
NC
GND
EN
PG
Pin Functions
PIN
I/O
DESCRIPTION
NUMBER
NAME
OUT
NC
1
2
3
O
—
O
Regulated output voltage
No internal connection. Leave open, or connect to ground.
Power-good indicator. Requires external pullup.
PG
Enable input. Logic high = device is ON, logic low = device is OFF, with internal 3-MΩ
pulldown.
4
EN
I
5
6
GND
IN
G
I
Ground
Unregulated input voltage
Connect to copper area under the package to improve thermal performance. The use of
thermal vias to transfer heat to inner layers of the PCB is recommended. Connect the
thermal pad to ground, or leave floating. Do not connect the thermal pad to any potential
other than ground.
Exposed
thermal pad
—
—
Copyright © 2015–2016, Texas Instruments Incorporated
3
LP5912
ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
–0.3
–0.3
-0.3
–0.3
MAX
UNIT
V
VIN
Input voltage
7
7
VOUT
VEN
VPG
TJ
Output voltage
V
Enable input voltage
Power Good (PG) pin OFF voltage
Junction temperature
Continuous power dissipation(3)
Storage temperature
7
V
7
V
150
°C
W
°C
PD
Internally Limited
–65
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the GND pin.
(3) Internal thermal shutdown circuitry protects the device from permanent damage.
7.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process..
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
1.6
0.8
0
MAX
6.5
UNIT
VIN
Input supply voltage
Output voltage
VOUT
VEN
5.5
V
Enable input voltage
PG pin OFF voltage
Output current
VIN
VPG
0
6.5
IOUT
0
500
125
mA
°C
TJ-MAX-OP
Operating junction temperature(2)
–40
(1) All voltages are with respect to the GND pin.
(2) TJ-MAX-OP = (TA(MAX) + (PD(MAX) × RθJA )).
7.4 Thermal Information
LP5912
DRV (WSON)
6 PINS
71.2(3)
93.7
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance, High-K(2)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
40.7
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.5
ψJB
41.1
RJC(bot)
11.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Thermal resistance value RθJA is based on the EIA/JEDEC High-K printed circuit board defined by: JESD51-7 - High Effective Thermal
Conductivity Test Board for Leaded Surface Mount Packages.
(3) The PCB for the WSON (DRV) package RθJA includes two (2) thermal vias under the exposed thermal pad per EIA/JEDEC JESD51-5.
4
Copyright © 2015–2016, Texas Instruments Incorporated
LP5912
www.ti.com.cn
ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016
7.5 Electrical Characteristics
VIN = VOUT(NOM) + 0.5 V or 1.6 V, whichever is greater; VEN = 1.3 V, CIN = 1 µF, COUT = 1 µF, IOUT = 1 mA (unless otherwise
stated).(1)(2)(3)
PARAMETER
OUTPUT VOLTAGE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
For VOUT(NOM) ≥ 3.3 V:
VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.5 V,
–2%
2%
IOUT = 1 mA to 500 mA
For 1.1 V ≤ VOUT(NOM) < 3.3 V:
VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.5 V,
IOUT = 1 mA to 500 mA
Output voltage tolerance
–3%
3%
For VOUT(NOM) < 1.1 V:
1.6 V ≤ VIN ≤ 6.5 V,
ΔVOUT
IOUT = 1 mA to 500 mA
For VOUT(NOM) ≥ 1.1V:
VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.5 V
Line regulation
Load regulation
0.8
%/V
For VOUT(NOM) < 1.1V :
1.6 V ≤ VIN ≤ 6.5 V
IOUT = 1 mA to 500 mA
0.0022
%/mA
CURRENT LEVELS
ISC Short-circuit current limit
IRO
TJ = 25°C, see(4)
Reverse leakage current(5) VEN = VIN = 0 V, VOUT = 5.5 V
700
900
10
1100
150
55
mA
µA
VEN = 1.3 V, IOUT = 0 mA
Quiescent current(6)
30
IQ
µA
VEN = 1.3 V, IOUT = 500 mA
400
600
VEN = 0 V
0.2
1.5
5
Quiescent current,
–40°C ≤ TJ ≤ 85°C
IQ(SD)
µA
µA
shutdown mode(6)
VEN = 0 V
0.2
35
IG
VDO DROPOUT VOLTAGE
Ground current(7)
VEN = 1.3 V, IOUT = 0 mA
IOUT = 500 mA, 1.6 V ≤ VOUT(NOM) < 3.3 V
IOUT = 500 mA, 3.3 V ≤ VOUT(NOM) ≤ 5.5 V
170
95
250
180
mV
mV
VDO
Dropout voltage(8)
(1) All voltages are with respect to the device GND pin, unless otherwise stated.
(2) Minimum and maximum limits are ensured through test, design, or statistical correlation over the junction temperature (TJ) range of
–40°C to +125°C, unless otherwise stated. Typical values represent the most likely parametric norm at TA = 25°C, and are provided for
reference purposes only.
(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP
=
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
(4) Short-circuit current (ISC) is equivalent to current limit. To minimize thermal effects during testing, ISC is measured with VOUT pulled to
100 mV below its nominal voltage.
(5) Reverse current (IRO) is measured at the IN pin.
(6) Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT
.
(7) Ground current is defined here as the total current flowing to ground as a result of all input voltages applied to the device.
(8) Dropout voltage (VDO) is the voltage difference between the input and the output at which the output voltage drops to 150 mV below its
nominal value when VIN = VOUT + 0.5 V. Dropout voltage is not a valid condition for output voltages less than 1.6 V as compliance with
the minimum operating voltage requirement cannot be assured.
Copyright © 2015–2016, Texas Instruments Incorporated
5
LP5912
ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016
www.ti.com.cn
Electrical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V or 1.6 V, whichever is greater; VEN = 1.3 V, CIN = 1 µF, COUT = 1 µF, IOUT = 1 mA (unless otherwise
stated).(1)(2)(3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN to VOUT RIPPLE REJECTION
ƒ = 100 Hz, VOUT ≥ 1.1 V, IOUT = 20 mA
ƒ = 1 kHz, VOUT ≥ 1.1 V, IOUT = 20 mA
80
75
65
40
65
65
65
40
ƒ = 10 kHz, VOUT ≥ 1.1 V, IOUT = 20 mA
ƒ = 100 kHz, VOUT ≥ 1.1 V, IOUT = 20 mA
ƒ = 100 Hz, 0.8 V < VOUT < 1.1 V, IOUT = 20 mA
ƒ = 1 kHz, 0.8 V < VOUT < 1.1 V, IOUT = 20 mA
ƒ = 10 kHz, 0.8 V < VOUT < 1.1 V, IOUT = 20 mA
ƒ = 100 kHz, 0.8 V < VOUT < 1.1 V, IOUT = 20 mA
Power Supply Rejection
PSRR
dB
Ratio(9)
OUTPUT NOISE VOLTAGE
IOUT = 1 mA, BW = 10 Hz to 100 kHz
IOUT = 500 mA, BW = 10 Hz to 100 kHz
12
12
eN
Noise voltage
µVRMS
THERMAL SHUTDOWN
Thermal shutdown
temperature
TSD
160
15
°C
°C
Thermal shutdown
hysteresis
THYS
LOGIC INPUT THRESHOLDS
VIN = 1.6 V to 6.5 V
VEN falling until device is disabled
VEN(OFF)
VEN(ON)
OFF Threshold
ON Threshold
0.3
V
1.6 V ≤ VIN ≤ 6.5 V
VEN rising until device is enabled
1.3
VEN = 6.5 V, VIN = 6.5 V
VEN = 0 V, VIN = 3.3 V
2.5
IEN
Input current at EN pin(10)
PG high threshold (% of
µA
0.001
PGHTH
PGLTH
VOL(PG)
94%
90%
nominal VOUT
PG low threshold (% of
nominal VOUT
)
)
PG pin low-level output
voltage
VOUT < PGLTH, sink current = 1 mA
100
1
mV
IlKG(PG)
tPGD
PG pin leakage current
PG delay time
VOUT < PGHTH, VPG = 6.5 V
µA
µs
Time from VOUT > PG threshold to PG toggling
140
(9) This specification is ensured by design.
(10) There is a 3-MΩ pulldown resistor between the EN pin and GND pin on the device.
6
Copyright © 2015–2016, Texas Instruments Incorporated
LP5912
www.ti.com.cn
ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016
Electrical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V or 1.6 V, whichever is greater; VEN = 1.3 V, CIN = 1 µF, COUT = 1 µF, IOUT = 1 mA (unless otherwise
stated).(1)(2)(3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TRANSITION CHARACTERISTICS
For VIN ↑ and VOUT(NOM) ≥ 1.1 V:
VIN = (VOUT(NOM) + 0.5 V) to (VOUT(NOM) + 1.1 V)
VIN trise = 30 µs
1
For VIN ↑ and VOUT(NOM) < 1.1 V:
VIN = 1.6 V to 2.2 V
VIN trise = 30 µs
Line transients(9)
mV
For VIN ↓ and VOUT(NOM) ≥ 1.1 V
VIN = (VOUT(NOM) + 1.1 V) to (VOUT(NOM) + 0.5 V)
VIN tfall = 30 µs
ΔVOUT
–1
For VIN ↓ and VOUT(NOM) < 1.1 V:
VIN = 2.2 V to 1.6 V
VIN tfall = 30 µs
IOUT = 5 mA to 500 mA
IOUT trise = 10 µs
–45
Load transients(9)
mV
IOUT = 500 mA to 5 mA
IOUT tfall = 10 µs
45
Overshoot on start-up(9)
Stated as a percentage of VOUT(NOM)
5%
Time from VEN > VEN(ON) to VOUT = 95% of
VOUT(NOM)
tON
Turnon time
200
100
µs
OUTPUT AUTO DISCHARGE RATE
Output discharge pull-down
resistance
RAD
VEN = 0 V, VIN = 3.6 V
Ω
7.6 Output and Input Capacitors
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input capacitance(2)
Output capacitance(2)
Output voltage(2)
TEST CONDITIONS
MIN(1)
TYP
MAX
UNIT
µF
CIN
0.7
0.7
5
1
1
Capacitance for stability
COUT
ESR
10
µF
500
mΩ
(1) The minimum capacitance must be greater than 0.5 μF over full range of operating conditions. The capacitor tolerance must be 30% or
better over the full temperature range. The full range of operating conditions for the capacitor in the application must be considered
during device selection to ensure this minimum capacitance specification is met. X7R capacitors are recommended however capacitor
types X5R, Y5V, and Z5U may be used with consideration of the application conditions.
(2) This specification is verified by design.
Copyright © 2015–2016, Texas Instruments Incorporated
7
LP5912
ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016
www.ti.com.cn
7.7 Typical Characteristics
Unless otherwise stated: VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C, unless otherwise
stated.
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
VOUT at IOUT = 1mA
VPG at IOUT = 1mA
VOUT at IOUT = 500 mA
VPG at IOUT = 500 mA
VEN(ON)
VEN(OFF)
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Input Voltage (V)
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Input Voltage (V)
D001
D002
Figure 1. VEN Thresholds vs Input Voltage
Figure 2. LP5912-0.9 Output Voltage, VPG vs Input Voltage
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
3.5
VOUT at IOUT =1 mA
VPG at IOUT =1 mA
VOUT at IOUT = 500 mA
VPG at IOUT = 500 mA
VOUT at IOUT = 1mA
VPG at IOUT = 1mA
VOUT at IOUT = 500 mA
VPG at IOUT = 500mA
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
Input Voltage (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Input Voltage (V)
D003
D004
Figure 3. LP5912-1.8 Output Voltage, VPG vs Input Voltage
Figure 4. LP5912-3.3 Output Voltage, VPG vs Input Voltage
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.4
0.2
0.0
VIN
VOUT
VPG
VIN
VOUT
VPG
0
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
Time (ms)
Time (ms)
D005
D006
VIN = 0 V to 1.6 V
IOUT = 1 mA
VIN = 0 V to 1.6 V
IOUT = 500 mA
Figure 5. LP5912-0.9 Power Up
Figure 6. LP5912-0.9 Power Up
8
Copyright © 2015–2016, Texas Instruments Incorporated
LP5912
www.ti.com.cn
ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016
Typical Characteristics (continued)
Unless otherwise stated: VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C, unless otherwise
stated.
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VIN
VOUT
VPG
VIN
VOUT
VPG
0
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
Time (ms)
Time (ms)
D007
D008
VIN = 0 V to 2.3 V
IOUT = 1 mA
VIN = 0 V to 2.3 V
IOUT = 500 mA
Figure 7. LP5912-1.8 Power Up
Figure 8. LP5912-1.8 Power Up
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VIN
VOUT
VPG
VIN
VOUT
VPG
0
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
Time (ms)
Time (ms)
D009
D010
VIN = 0 V to 3.8 V
IOUT = 1 mA
VIN = 0 V to 3.8 V
IOUT = 500 mA
Figure 9. LP5912-3.3 Power Up
Figure 10. LP5912-3.3 Power Up
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
VIN (V)
VIN (V)
D051
D052
IOUT = 0 mA
IOUT = 0 mA
Figure 12. LP5912-1.8 IQ (No Load) vs VIN
Figure 11. LP5912-0.9 IQ (No Load) vs VIN
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Typical Characteristics (continued)
Unless otherwise stated: VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C, unless otherwise
stated.
50
TA = +125°C
TA = +85°C
45
TA = +25°C
TA = -40°C
40
35
30
25
20
15
10
5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
VIN (V)
D053
IOUT = 0 mA
VEN = 0 V
Figure 14. LP5912-0.9 IQ(SD) vs VIN
Figure 13. LP5912-3.3 IQ (No Load) vs VIN
VEN = 0 V
Figure 15. LP5912-1.8 IQ(SD) vs VIN
VEN = 0 V
Figure 16. LP5912-3.3 IQ(SD) vs VIN
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
TA = -40°C
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
TA = +25°C
TA = +85°C
TA = +125°C
0
0
0
50 100 150 200 250 300 350 400 450 500
IOUT (mA)
0
50 100 150 200 250 300 350 400 450 500
IOUT (mA)
D057
D058
VIN = 1.6 V
Figure 17. LP5912-0.9 IGND vs IOUT
Figure 18. LP5912-1.8 IGND vs IOUT
10
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Typical Characteristics (continued)
Unless otherwise stated: VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C, unless otherwise
stated.
500
450
400
350
300
250
200
150
100
50
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
0
0
50 100 150 200 250 300 350 400 450 500
IOUT (mA)
10 20
100
1000
10000 100000 1000000 1E+7
Frequency (Hz)
D059
D011
VIN = 1.6 V
IOUT = 20 mA
Figure 19. LP5912-3.3 IGND vs IOUT
Figure 20. LP5912-0.9 PSRR vs Frequency
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
IOUT = 1 mA
IOUT = 10 mA
IOUT = 100 mA
IOUT = 500 mA
-20
-40
-60
-80
-100
-120
10 20
100
1000
10000 100000 1000000 1E+7
10 20
100
1000
10000 100000 1000000 1E+7
Frequency (Hz)
Frequency (Hz)
D012
D013
VIN = 1.6 V
IOUT = 20 mA
Figure 21. LP5912-0.9 PSRR vs Frequency
Figure 22. LP5912-1.8 PSRR vs Frequency
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
IOUT = 1 mA
IOUT = 10 mA
IOUT = 100 mA
IOUT = 500 mA
10 20
100
1000
10000 100000 1000000 1E+7
10 20
100
1000
10000 100000 1000000 1E+7
Frequency (Hz)
Frequency (Hz)
D014
D015
IOUT = 20 mA
Figure 23. LP5912-1.8 PSRR vs Frequency
Figure 24. LP5912-3.3 PSRR vs Frequency
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Typical Characteristics (continued)
Unless otherwise stated: VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C, unless otherwise
stated.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
1
0.8
0.6
0.4
0.2
0
2.4
2.3
2.2
2.1
2
IOUT = 1 mA
D VOUT (mV)
VIN (V)
IOUT = 10 mA
IOUT = 100 mA
IOUT = 500 mA
1.9
1.8
1.7
1.6
1.5
1.4
-0.2
-0.4
-0.6
-0.8
-1
10 20
100
1000
10000 100000 1000000 1E+7
0
50 100 150 200 250 300 350 400 450 500
Time (µs)
Frequency (Hz)
D016
D017
VIN = 1.6 V to 2.2 V
trise = 30 µs
Figure 25. LP5912-3.3 PSRR vs Frequency
Figure 26. LP5912-0.9 Line Transient
1
0.8
0.6
0.4
0.2
0
2.4
1
0.8
0.6
0.4
0.2
0
3.1
3
DVOUT (mV)
VIN (V)
D VOUT (mV)
VIN (V)
2.3
2.2
2.1
2
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
1.9
1.8
1.7
1.6
1.5
1.4
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
0
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
Time (µs)
Time (ms)
D018
D019
VIN = 2.2 V to 1.6 V
tfall = 30 µs
VIN = 2.3 V to 2.9 V
trise = 30 µs
Figure 27. LP5912-0.9 Line Transient
Figure 28. LP5912-1.8 Line Transient
1
0.8
0.6
0.4
0.2
0
3.1
3
1
0.8
0.6
0.4
0.2
0
4.6
4.5
4.4
4.3
4.2
4.1
4
D VOUT (mV)
VIN (V)
D VOUT (mV)
VIN (V)
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
3.9
3.8
3.7
3.6
0
50 100 150 200 250 300 350 400 450 500
Time (µs)
0
50 100 150 200 250 300 350 400 450 500
Time (µs)
D020
D021
VIN = 2.9 V to 2.3 V
tfall = 30 µs
VIN = 3.8 V to 4.4 V
trise = 30 µs
Figure 29. LP5912-1.8 Line Transient
Figure 30. LP5912-3.3 Line Transient
12
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Typical Characteristics (continued)
Unless otherwise stated: VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C, unless otherwise
stated.
1
0.8
0.6
0.4
0.2
0
4.6
4.5
4.4
4.3
4.2
4.1
4
60
600
500
400
300
200
100
0
D VOUT (mV)
VIN (V)
D VOUT (mV)
IOUT (mA)
40
20
0
-0.2
-0.4
-0.6
-0.8
-1
-20
-40
-60
3.9
3.8
3.7
3.6
0
50 100 150 200 250 300 350 400 450 500
Time (µs)
0
20
40
60
80 100 120 140 160 180 200
Time (µs)
D022
D023
VIN = 4.4 V to 3.8 V
tfall = 30 µs
VIN = 1.6 V
IOUT = 5 mA to 500 mA
trise = 10 µs
Figure 31. LP5912-3.3 Line Transient
Figure 32. LP5912-0.9 Load Transient Response
60
40
600
500
400
300
200
100
0
60
40
600
D VOUT (mV)
IOUT (mA)
D VOUT (mV)
IOUT (mA)
500
400
300
200
100
0
20
20
0
0
-20
-40
-60
-20
-40
-60
0
20
40
60
80 100 120 140 160 180 200
Time (µs)
0
20
40
60
80 100 120 140 160 180 200
Time (µs)
D024
D025
VIN = 1.6 V
IOUT = 500 mA to 5 mA
tfall = 10 µs
IOUT = 5 mA to 500 mA
trise = 10 µs
Figure 33. LP5912-0.9 Load Transient Response
Figure 34. LP5912-1.8 Load Transient Response
60
40
600
60
40
600
D VOUT (mV)
IOUT (mA)
D VOUT (mV)
IOUT (mA)
500
400
300
200
100
0
500
400
300
200
100
0
20
20
0
0
-20
-40
-60
-20
-40
-60
0
20
40
60
80 100 120 140 160 180 200
Time (µs)
0
20
40
60
80 100 120 140 160 180 200
Time (µs)
D026
D027
IOUT = 500 mA to 5 mA
tfall = 10 µs
IOUT = 5 mA to 500 mA
trise = 10 µs
Figure 35. LP5912-1.8 Load Transient Response
Figure 36. LP5912-3.3 Load Transient Response
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Typical Characteristics (continued)
Unless otherwise stated: VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C, unless otherwise
stated.
3
2.5
2
60
600
500
400
300
200
100
0
VEN (V)
VOUT (V)
VPG (V)
D VOUT (mV)
IOUT (mA)
40
20
1.5
1
0
-20
-40
-60
0.5
0
0
20
40
60
80 100 120 140 160 180 200
Time (µs)
0
50 100 150 200 250 300 350 400 450 500
Time (µs)
D028
D031
IOUT = 500 mA to 5 mA
tfall = 10 µs
IOUT = 0 mA
COUT = 1 µF
Figure 37. LP5912-3.3 Load Transient Response
Figure 38. LP5912-1.8 VOUT vs VEN(ON)
2.5
2
3
2.5
2
VEN (V)
VOUT (V)
VPG (V)
VEN (V)
VOUT (V)
VPG (V)
1.5
1
1.5
1
0.5
0
0.5
0
0
50 100 150 200 250 300 350 400 450 500
Time (µs)
0
50 100 150 200 250 300 350 400 450 500
Time (µs)
D032
D033
IOUT = 0 mA
COUT = 1 µF
IOUT = 1 mA
COUT = 1 µF
Figure 40. LP5912-1.8 VOUT vs VEN(ON)
Figure 39. LP5912-1.8 VOUT vs VEN(OFF)
2.5
2
3
2.5
2
VEN (V)
VOUT (V)
VPG (V)
VEN (V)
VOUT (V)
VPG (V)
1.5
1
1.5
1
0.5
0
0.5
0
0
50 100 150 200 250 300 350 400 450 500
Time (µs)
0
50 100 150 200 250 300 350 400 450 500
Time (µs)
D034
D035
IOUT = 1 mA
COUT = 1 µF
Figure 41. LP5912-1.8 VOUT vs VEN(OFF)
IOUT = 500 mA
COUT = 1 µF
Figure 42. LP5912-1.8 VOUT vs VEN(ON)
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Typical Characteristics (continued)
Unless otherwise stated: VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C, unless otherwise
stated.
225
200
175
150
125
100
75
2.2
VEN (V)
VOUT (V)
VPG (V)
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-40°C
25°C
85°C
50
25
125°C
0
0
5
10
15
20
25
Time (µs)
30
35
40
45
50
0
50 100 150 200 250 300 350 400 450 500
IOUT (mA)
D036
D041
IOUT = 500 mA
COUT = 1 µF
Figure 43. LP5912-1.8 VOUT vs VEN(OFF)
Figure 44. LP5912-1.8 Dropout Voltage (VDO) vs IOUT
225
200
175
150
125
100
75
1.2
1
-40°C
1 mA
500 mA
25°C
85°C
125°C
0.8
0.6
0.4
0.2
0
50
25
0
0
50 100 150 200 250 300 350 400 450 500
IOUT (mA)
10
100
1000
Frequency (Hz)
10000
100000
1000000
D042
D043
VIN = 1.6 V
Figure 45. LP5912-3.3 Dropout Voltage (VDO) vs IOUT
Figure 46. LP5912-0.9 Noise vs Frequency
1.2
1
1.2
1
1 mA
500 mA
1 mA
500 mA
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
10
100
1000
10000
100000
1000000
10
100
1000
10000
100000
1000000
Frequency (Hz)
Frequency (Hz)
D044
D045
Figure 47. LP5912-1.8 Noise vs Frequency
Figure 48. LP5912-3.3 Noise vs Frequency
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Typical Characteristics (continued)
Unless otherwise stated: VIN = VOUT + 0.5 V, VEN = VIN, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TJ = 25°C, unless otherwise
stated.
5
4
3
2
1
0
500
400
300
200
100
0
300
280
260
240
220
200
180
160
140
120
100
VEN (V)
VOUT (V)
IIN (mA)
-50
0
50 100 150 200 250 300 350 400 450
-50
-25
0
25
50
75
100
125
Time (ms)
D061
Junction Temperature (°C)
D060
CIN = Open
IOUT = 500 mA
COUT = 1 µF
IOUT = 0 mA (No Load)
Figure 49. LP5912-3.3 Turnon Time vs Junction
Temperature
Figure 50. LP5912-3.3 In-Rush Current
5
4.5
4
100
5
1.5
VEN (V)
VOUT (V)
IIN (mA)
VEN (V)
VOUT (V)
IIN (A)
90
80
70
60
50
40
30
20
10
0
4.5
4
1.35
1.2
3.5
3
3.5
3
1.05
0.9
2.5
2
2.5
2
0.75
0.6
1.5
1
1.5
1
0.45
0.3
0.5
0
0.5
0
0.15
0
-50
0
50 100 150 200 250 300 350 400 450
-50
0
50 100 150 200 250 300 350 400 450
Time (ms)
Time (ms)
D062
D063
CIN = Open
IOUT = 1 mA
COUT = 1 µF
CIN = Open
IOUT = 500 mA
COUT = 10 µF
Figure 51. LP5912-3.3 In-Rush Current
Figure 52. LP5912-3.3 In-Rush Current
5
1.5
VEN (V)
VOUT (V)
IIN (A)
4
4.5
1.35
1.2
3.5
3
1.05
0.9
2.5
2
0.75
0.6
1.5
1
0.45
0.3
0.5
0
0.15
0
-50
0
50 100 150 200 250 300 350 400 450
Time (ms)
D064
CIN = Open
IOUT = 1 mA
COUT = 10 µF
Figure 53. LP5912-3.3 In-Rush Current
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8 Detailed Description
8.1 Overview
The LP5912 is a low-noise, high PSRR, LDO capable of sourcing a 500-mA load. The LP5912 can operate down
to 1.6-V input voltage and 0.8-V output voltage. This combination of low noise, high PSRR, and low output
voltage makes the device an ideal low dropout (LDO) regulator to power a multitude of loads from noise-sensitive
communication components to battery-powered system.
The LP5912 Functional Block Diagram contains several features, including:
•
•
•
•
•
•
•
Internal output resistor divider feedback;
Small size and low-noise internal protection circuit current limit;
Reverse current protection;
Current limit and in-rush current protection;
Thermal shutdown;
Output auto discharge for fast turnoff; and
Power-good output, with fixed 140-µs typical delay.
8.2 Functional Block Diagram
Current
Limit
IN
OUT
RAD
100 ꢀ
45 kꢀ
VIN
EA
Output
Discharge
+
VBG
œ
PG
EN
Control
EN
140-µs
DELAY
3 Mꢀ
Copyright © 2016, Texas Instruments Incorporated
GND
8.3 Feature Description
8.3.1 Enable (EN)
The LP5912 EN pin is internally held low by a 3-MΩ resistor to GND. The EN pin voltage must be higher than the
VEN(ON) threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage
must be lower than the VEN(OFF) threshold to ensure that the device is fully disabled and the automatic output
discharge is activated.
When the device is disabled the output stage is disabled, the PG output pin is low, and the output automatic
discharge is ON.
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Feature Description (continued)
8.3.2 Output Automatic Discharge (RAD
)
The LP5912 output employs an internal 100-Ω (typical) pulldown resistance to discharge the output when the EN
pin is low. Note that if the LP5912 EN pin is low (the device is OFF) and the OUT pin is held high by a secondary
supply, current flows from the secondary supply through the automatic discharge pulldown resistor to ground.
8.3.3 Reverse Current Protection (IRO
)
The LP5912 input is protected against reverse current when output voltage is higher than the input. In the event
that extra output capacitance is used at the output, a power-down transient at the input would normally cause a
large reverse current through a conventional regulator. The LP5912 includes a reverse voltage detector that trips
when VIN drops below VOUT, shutting off the regulator and opening the PMOS body diode connection, preventing
any reverse current from the OUT pin from flowing to the IN pin.
If the LP5912 EN pin is low (the LP5912 is OFF) and the OUT pin is held high by a secondary supply, current
flows from the secondary supply through the automatic discharge pulldown resistor to ground. This is not reverse
current, this is automatic discharge pulldown current.
Note that reverse current (IRO) is measured at the IN pin.
8.3.4 Internal Current Limit (ISC
)
The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The
LDO is not designed to operate continuously at the ISC current limit. During a current-limit event, the LDO
sources constant current. Therefore, the output voltage falls when load impedance decreases. Note also that if a
current limit occurs and the resulting output voltage is low, excessive power may be dissipated across the LDO,
resulting in a thermal shutdown of the output.
8.3.5 Thermal Overload Protection (TSD
)
Thermal shutdown disables the output when the junction temperature rises to approximately 160°C, which allows
the device to cool. When the junction temperature cools to approximately 145°C, the output circuitry enables.
Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a
result of overheating.
8.3.6 Power-Good Output (PG)
The LP5912 device has a power-good function that works by toggling the state of the PG output pin. When the
output voltage falls below the PG threshold voltage (PGLTH), the PG pin open-drain output engages (low
impedance to GND). When the output voltage rises above the PG threshold voltage (PGVHTH), the PG pin
becomes high impedance. By connecting a pullup resistor to an external supply, any downstream device can
receive PG as a logic signal. Make sure that the external pullup supply voltage results in a valid logic signal for
the receiving device or devices. Use a pullup resistor from 10 kΩ to 100 kΩ for best results.
The input supply, VIN, must be no less than the minimum operating voltage of 1.6 V to ensure that the PG pin
output status is valid. The PG pin output status is undefined when VIN is less than 1.6 V.
In power-good function, the PG output pin being pulled high is typically delayed 140 µs after the output voltage
rises above the PGHTH threshold voltage. If the output voltage rises above the PGHTH threshold and then falls
below the PGLTH threshold voltage the PG pin falls immediately with no delay time.
If the PG function is not needed, the pullup resistor can be eliminated, and the PG pin can be either connected to
ground or left floating.
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8.4 Device Functional Modes
8.4.1 Enable (EN)
The LP5912 EN pin is internally held low by a 3-MΩ resistor to GND. The EN pin voltage must be higher than the
VEN(ON) threshold to ensure that the device is fully enabled under all operating conditions. When the EN pin
voltage is lower than the VEN(OFF) threshold, the output stage is disabled, the PG pin goes low, and the output
automatic discharge circuit is activated. Any charge on the OUT pin is discharged to ground through the internal
100-Ω (typical) output auto discharge pulldown resistance.
8.4.2 Minimum Operating Input Voltage (VIN)
The LP5912 device does not include any dedicated UVLO circuit. The device internal circuit is not fully functional
until VIN is at least 1.6 V. The output voltage is not regulated until VIN has reached at least the greater of 1.6 V or
(VOUT + VDO).
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers must
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LP5912 is designed to meet the requirements of RF and analog circuits, by providing low noise, high PSRR,
low quiescent current, and low line or load transient response. The device offers excellent noise performance
without the need for a noise bypass capacitor and is stable with input and output capacitors with a value of 1 μF.
The device delivers this performance in an industry standard WSON package, which for this device is specified
with an operating junction temperature (TJ) of –40°C to +125°C.
9.2 Typical Application
Figure 54 shows the typical application circuit for the LP5912. Input and output capacitances may need to be
increased above the 1-μF minimum for some applications.
VIN
VOUT
IN
OUT
NC
CIN
LP5912
COUT
GND
RPG
VEN
VPG
EN
PG
Copyright © 2016, Texas Instruments Incorporated
Figure 54. LP5912 Typical Application
9.2.1 Design Requirements
For typical RF linear regulator applications, use the parameters listed in Table 1.
Table 1. Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
1.6 to 6.5 V
0.8 to 5.5 V
500 mA
Output voltage
Output current
Output capacitor
1 to 10 µF
Input/output capacitor ESR range
5 mΩ to 500 mΩ
20
Copyright © 2015–2016, Texas Instruments Incorporated
LP5912
www.ti.com.cn
ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016
9.2.2 Detailed Design Procedure
9.2.2.1 External Capacitors
Like most low-dropout regulators, the LP5912 requires external capacitors for regulator stability. The device is
specifically designed for portable applications requiring minimum board space and smallest components. These
capacitors must be correctly selected for good performance.
9.2.2.2 Input Capacitor
An input capacitor is required for stability. The input capacitor must be at least equal to, or greater than, the
output capacitor for good load-transient performance. A capacitor of at least 1 µF must be connected between
the LP5912 IN pin and ground for stable operation over full load-current range. It is acceptable to have more
output capacitance than input, as long as the input is at least 1 µF.
The input capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean
analog ground. Any good-quality ceramic, tantalum, or film capacitor may be used at the input.
NOTE
To ensure stable operation it is essential that good PCB practices are employed to
minimize ground impedance and keep input inductance low. If these conditions cannot be
met, or if long leads are to be used to connect the battery or other power source to the
LP5912, increasing the value of the input capacitor to at least 10 µF is recommended.
Also, tantalum capacitors can suffer catastrophic failures due to surge current when
connected to a low-impedance source of power (such as a battery or a very large
capacitor). If a tantalum capacitor is used at the input, it must be verified by the
manufacturer to have a surge current rating sufficient for the application. There are no
requirements for the equivalent series resistance (ESR) on the input capacitor, but
tolerance and temperature coefficient must be considered when selecting the capacitor to
ensure the capacitance remains 1 μF ±30% over the entire operating temperature range.
9.2.2.3 Output Capacitor
The LP5912 is designed specifically to work with a very small ceramic output capacitor, typically 1 µF. A ceramic
capacitor (dielectric types X5R or X7R) in the 1-µF to 10-µF range, and with an ESR from 5 mΩ to 500 mΩ, is
suitable in the LP5912 application circuit. For this device the output capacitor must be connected between the
OUT pin with a good connection back to the GND pin.
Tantalum or film capacitors may also be used at the device output, VOUT, but these are not as attractive for
reasons of size and cost (see Capacitor Characteristics).
The output capacitor must meet the requirement for the minimum value of capacitance and have an ESR value
that is within the range 5 mΩ to 500 mΩ for stability.
9.2.2.4 Capacitor Characteristics
The LP5912 is designed to work with ceramic capacitors on the input and output to take advantage of the
benefits they offer. For capacitance values in the range of 1 µF to 10 µF, ceramic capacitors are the smallest,
least expensive, and have the lowest ESR values, thus making them best for eliminating high frequency noise.
The ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR
requirement for stability for the LP5912.
The preferred choice for temperature coefficient in a ceramic capacitor is X7R. This type of capacitor is the most
stable and holds the capacitance within ±15% over the temperature range. Tantalum capacitors are less
desirable than ceramic for use as output capacitors because they are more expensive when comparing
equivalent capacitance and voltage ratings in the 1-µF to 10-µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. While it may be possible to find a tantalum capacitor with an ESR value within the stable range, it
would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the
same ESR value. Also, the ESR of a typical tantalum increases about 2:1 as the temperature goes from 25°C
down to –40°C, so some guard band must be allowed.
Copyright © 2015–2016, Texas Instruments Incorporated
21
LP5912
ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016
www.ti.com.cn
9.2.2.5 Remote Capacitor Operation
To ensure stability the LP5912 requires at least a 1-μF capacitor at the OUT pin. There is no strict requirement
about the location of the output capacitor in regards to the LDO OUT pin; the output capacitor may be located 5
to 10 cm away from the LDO. This means that there is no need to have a special capacitor close to the OUT pin
if there are already respective capacitors in the system. This placement flexibility requires that the output
capacitor be connected directly between the LP5912 OUT pin and GND pin with no vias. This remote capacitor
feature can help users to minimize the number of capacitors in the system.
As a good design practice, keep the wiring parasitic inductance at a minimum, which means using as wide as
possible traces from the LDO output to the capacitors, keeping the LDO output trace layer as close to ground
layer as possible, avoiding vias on the path. If there is a need to use vias, implement as many as possible vias
between the connection layers. Keeping parasitic wiring inductance less than 35 nH is recommended. For
applications with fast load transients use an input capacitor equal to, or larger than, the sum of the capacitance
at the output node for the best load-transient performance.
9.2.2.6 Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is
critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and
load conditions and can be calculated with Equation 1.
PD(MAX) = (VIN(MAX) – VOUT) × IOUT
(1)
Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available
voltage drop option that is greater than the dropout voltage (VDO). However, keep in mind that higher voltage
drops result in better dynamic (that is, PSRR and transient) performance.
On the WSON (DRV) package, the primary conduction path for heat is through the exposed power pad into the
PCB. To ensure the device does not overheat, connect the exposed pad, through thermal vias, to an internal
ground plane with an appropriate amount of copper PCB area.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(RθJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to
Equation 2 or Equation 3:
TJ(MAX) = TA(MAX) + (RθJA × PD(MAX)
PD = (TJ(MAX) – TA(MAX)) / RθJA
)
(2)
(3)
Unfortunately, this RθJA is highly dependent on the heat-spreading capability of the particular PCB design, and
therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded
in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copper-
spreading area, and is to be used only as a relative measure of package thermal performance. For a well-
designed thermal layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal resistance
(RθJCbot) plus the thermal resistance contribution by the PCB copper area acting as a heat sink.
22
Copyright © 2015–2016, Texas Instruments Incorporated
LP5912
www.ti.com.cn
ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016
9.2.2.7 Estimating Junction Temperature
The EIA/JEDEC standard recommends the use of psi (Ψ) thermal characteristics to estimate the junction
temperatures of surface mount devices on a typical PCB board application. These characteristics are not true
thermal resistance values, but rather package specific thermal characteristics that offer practical and relative
means of estimating junction temperatures. These psi metrics are determined to be significantly independent of
copper-spreading area. The key thermal characteristics (ΨJT and ΨJB) are given in Thermal Information and are
used in accordance with Equation 4 or Equation 5.
TJ(MAX) = TTOP + (ΨJT × PD(MAX)
)
where
•
•
PD(MAX) is explained in Equation 3
TTOP is the temperature measured at the center-top of the device package.
(4)
TJ(MAX) = TBOARD + (ΨJB × PD(MAX)
)
where
•
•
PD(MAX) is explained in Equation 3.
TBOARD is the PCB surface temperature measured 1 mm from the device package and centered on the
package edge.
(5)
For more information about the thermal characteristics ΨJT and ΨJB, see Semiconductor and IC Package Thermal
Metrics ; for more information about measuring TTOP and TBOARD, see Using New Thermal Metrics ; and for more
information about the EIA/JEDEC JESD51 PCB used for validating RθJA, see the TI Application Report Thermal
Characteristics of Linear and Logic Packages Using JEDEC PCB Designs. These application notes are available
at www.ti.com.
9.2.3 Application Curves
2.5
2.0
1.5
1.0
0.5
0.0
2.5
2.0
1.5
1.0
0.5
0.0
VEN (V)
VOUT (V)
VPG (V)
VEN (V)
VOUT (V)
VPG (V)
0
50 100 150 200 250 300 350 400 450 500
Time (µs)
0
5
10
15
20
25
Time (µs)
D029
D030
VIN = 2.3 V
IOUT = 500 mA
COUT = 1 µF
VIN = 2.3 V
IOUT = 500 mA (3.6 Ω)
COUT = 1 µF
Figure 55. LP5912-1.8 VOUT vs VEN (ON)
Figure 56. LP5912-1.8 VOUT vs VEN (OFF)
10 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 1.6 V to 6.5 V. The input supply must
be well regulated and free of spurious noise. To ensure that the LP5912 output voltage is well regulated and
dynamic performance is optimum, the input supply must be at least VOUT + 0.5 V. A minimum capacitor value of
1 µF is required to be within 1 cm of the IN pin.
Copyright © 2015–2016, Texas Instruments Incorporated
23
LP5912
ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
The dynamic performance of the LP5912 is dependant on the layout of the PCB. PCB layout practices that are
adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5912.
Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5912, and as
close to the package as is practical. The ground connections for CIN and COUT must be back to the LP5912
ground pin using as wide and as short of a copper trace as is practical.
Connections using long trace lengths, narrow trace widths, or connections through vias must be avoided. Such
connections add parasitic inductances and resistance that result in inferior performance especially during
transient conditions.
11.2 Layout Example
Thermal Vias (2)
IN
1
2
3
6
5
4
OUT
NC
COUT
CIN
GND
EN
PG
RPG
Figure 57. LP5912 Typical Layout
24
版权 © 2015–2016, Texas Instruments Incorporated
LP5912
www.ti.com.cn
ZHCSEY5D –DECEMBER 2015–REVISED NOVEMBER 2016
12 器件和文档支持
12.1 相关文档ꢀ
更多信息,请参见以下文档:
•
•
•
•
《AN1187 无引线框架封装 (LLP)》
半导体和集成电路 (IC) 封装热度量
《使用新的热指标》
《采用 JEDEC PCB 设计的线性和逻辑封装散热特性》
12.2 接收文档更新通知
如需接收文档更新通知,请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后,即可每周定期收到已更改的产品信息。有关更改的详细信息,请查阅已修订文档中包含的修订历史记录。
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
版权 © 2015–2016, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP5912-0.9DRVR
LP5912-0.9DRVT
LP5912-1.0DRVR
LP5912-1.0DRVT
LP5912-1.1DRVR
LP5912-1.1DRVT
LP5912-1.2DRVR
LP5912-1.2DRVT
LP5912-1.5DRVR
LP5912-1.5DRVT
LP5912-1.8DRVR
LP5912-1.8DRVT
LP5912-2.5DRVR
LP5912-2.5DRVT
LP5912-2.8DRVR
LP5912-2.8DRVT
LP5912-3.0DRVR
LP5912-3.0DRVT
LP5912-3.3DRVR
LP5912-3.3DRVT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
12-A
12-A
1NPU
1NPU
12-H
12-H
12-B
12-B
12-C
12-C
12-D
12-D
1NQU
1NQU
12-E
12-E
12-G
12-G
12-F
12-F
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
250
RoHS & Green
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP5912-5.0DRVR
LP5912-5.0DRVT
ACTIVE
ACTIVE
WSON
WSON
DRV
DRV
6
6
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
12-I
12-I
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Dec-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP5912-0.9DRVR
LP5912-0.9DRVR
LP5912-0.9DRVT
LP5912-0.9DRVT
LP5912-1.0DRVR
LP5912-1.0DRVT
LP5912-1.1DRVR
LP5912-1.1DRVR
LP5912-1.1DRVT
LP5912-1.1DRVT
LP5912-1.2DRVR
LP5912-1.2DRVT
LP5912-1.5DRVR
LP5912-1.5DRVR
LP5912-1.5DRVT
LP5912-1.5DRVT
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
3000
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
250
3000
250
3000
3000
250
250
3000
250
3000
3000
250
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Dec-2022
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP5912-1.8DRVR
LP5912-1.8DRVR
LP5912-1.8DRVT
LP5912-1.8DRVT
LP5912-2.5DRVR
LP5912-2.5DRVT
LP5912-2.8DRVR
LP5912-2.8DRVR
LP5912-2.8DRVT
LP5912-2.8DRVT
LP5912-3.0DRVR
LP5912-3.0DRVR
LP5912-3.0DRVT
LP5912-3.0DRVT
LP5912-3.3DRVR
LP5912-3.3DRVT
LP5912-5.0DRVR
LP5912-5.0DRVT
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
3000
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
250
3000
250
3000
3000
250
250
3000
3000
250
250
3000
250
3000
250
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Dec-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP5912-0.9DRVR
LP5912-0.9DRVR
LP5912-0.9DRVT
LP5912-0.9DRVT
LP5912-1.0DRVR
LP5912-1.0DRVT
LP5912-1.1DRVR
LP5912-1.1DRVR
LP5912-1.1DRVT
LP5912-1.1DRVT
LP5912-1.2DRVR
LP5912-1.2DRVT
LP5912-1.5DRVR
LP5912-1.5DRVR
LP5912-1.5DRVT
LP5912-1.5DRVT
LP5912-1.8DRVR
LP5912-1.8DRVR
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
3000
3000
250
182.0
210.0
182.0
210.0
210.0
210.0
182.0
210.0
182.0
210.0
182.0
182.0
210.0
182.0
210.0
182.0
182.0
210.0
182.0
185.0
182.0
185.0
185.0
185.0
182.0
185.0
182.0
185.0
182.0
182.0
185.0
182.0
185.0
182.0
182.0
185.0
20.0
35.0
20.0
35.0
35.0
35.0
20.0
35.0
20.0
35.0
20.0
20.0
35.0
20.0
35.0
20.0
20.0
35.0
250
3000
250
3000
3000
250
250
3000
250
3000
3000
250
250
3000
3000
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Dec-2022
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP5912-1.8DRVT
LP5912-1.8DRVT
LP5912-2.5DRVR
LP5912-2.5DRVT
LP5912-2.8DRVR
LP5912-2.8DRVR
LP5912-2.8DRVT
LP5912-2.8DRVT
LP5912-3.0DRVR
LP5912-3.0DRVR
LP5912-3.0DRVT
LP5912-3.0DRVT
LP5912-3.3DRVR
LP5912-3.3DRVT
LP5912-5.0DRVR
LP5912-5.0DRVT
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
250
250
182.0
210.0
210.0
210.0
210.0
182.0
210.0
182.0
210.0
182.0
210.0
182.0
182.0
182.0
210.0
210.0
182.0
185.0
185.0
185.0
185.0
182.0
185.0
182.0
185.0
182.0
185.0
182.0
182.0
182.0
185.0
185.0
20.0
35.0
35.0
35.0
35.0
20.0
35.0
20.0
35.0
20.0
35.0
20.0
20.0
20.0
35.0
35.0
3000
250
3000
3000
250
250
3000
3000
250
250
3000
250
3000
250
Pack Materials-Page 4
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1
0.1
EXPOSED
THERMAL PAD
3
4
6
2X
7
1.3
1.6 0.1
1
4X 0.65
0.35
0.25
6X
PIN 1 ID
(OPTIONAL)
0.3
0.2
6X
0.1
C A
C
B
0.05
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
6X (0.3)
(1)
1
7
6
SYMM
(1.6)
(1.1)
4X (0.65)
4
3
SYMM
(1.95)
(R0.05) TYP
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
7
6X (0.45)
METAL
1
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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