LP591209MDRVREP [TI]

Enhanced-product, 500-mA, low-noise, low-IQ, low-dropout regulator with reverse current protection | DRV | 6 | -55 to 125;


型号：	LP591209MDRVREP
厂家：	TEXAS INSTRUMENTS
描述：	Enhanced-product, 500-mA, low-noise, low-IQ, low-dropout regulator with reverse current protection \| DRV \| 6 \| -55 to 125
文件：	总31页 (文件大小：3657K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LP5912-EP

ZHCSOW8 –JULY 2022

LP5912-EP 500mA、低噪声、低I_Q增强型LDO 产品

1 特性

3 说明

• 输入电压范围：1.6V 至6.5V

• 输出电压范围：0.8V 至5.5V

• 输出电流：高达500 mA

• 低输出电压噪声：12μV_RMS（典型值）

• 1kHz 下的PSRR：75 dB (typ)

• 输出电压容差(V_OUT≥3.3V)：±2%

• 低I_Q（使能时，无负载）：30μA（典型值）

• 低压降(V_OUT≥3.3V)：

500mA 负载下为95mV（典型值）

• 与1µF 陶瓷输入和输出电容搭配使用，性能稳定

• 具备热过载和短路保护功能

• 反向电流保护

• 无需噪声旁路电容

LP5912-EP 是一款能提供高达 500mA 输出电流的低

噪声低压降稳压器 (LDO)。LP5912-EP 符合射频和模

拟电路要求，可提供低噪声、高 PSRR、低静态电流

以及低线路和负载瞬态响应。LP5912-EP 无需噪声旁

路电容器便可提供出色的噪声性能，并且支持远距离安

置输出电容。

该器件可与 1µF 输入和 1µF 输出陶瓷电容搭配使用

（无需独立的噪声旁路电容）。

其固定输出电压介于 0.8V 和 5.5V 之间（以 25mV 为

单位增量）。有关特定的电压选项要求，请联系德州仪

器(TI) 销售办事处。

封装信息⁽¹⁾

• 输出自动放电以实现快速关断

• 电源正常状态输出，具有140µs（典型值）延迟

• 内部软启动，可限制浪涌电流

• 工作结温：–55°C 至+125°C

• 支持国防、航空航天和医疗应用：

封装尺寸（标称值）

器件型号

LP5912-EP

封装

WSON (6)

2.00mm × 2.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

– 受控基线

– 一个组装和测试基地

– 一个制造基地

– 延长了产品生命周期

– 延长了产品变更通知

– 产品可追溯性

2 应用

• 监控系统

• 惯性导航

• 陆地移动无线电

• 全球定位系统接收器

• 数据集中器单元

V_IN

V_OUT

OUT

C_IN

LP5912-EP

C_OUT

GND

R_PG

V_EN

V_PG

简化版原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSC57

LP5912-EP

ZHCSOW8 –JULY 2022

www.ti.com.cn

Table of Contents

7.3 Feature Description...................................................16

7.4 Device Functional Modes..........................................18

8 Applications and Implementation................................19

8.1 Application Information............................................. 19

8.2 Typical Application.................................................... 19

8.3 Power Supply Recommendations.............................23

8.4 Layout....................................................................... 23

9 Device and Documentation Support............................24

9.1 Documentation Support............................................ 24

9.2 接收文档更新通知..................................................... 24

9.3 支持资源....................................................................24

9.4 Trademarks...............................................................24

10 Electrostatic Discharge Caution................................ 24

11 术语表............................................................................24

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................4

6.5 Electrical Characteristics.............................................5

6.6 Output and Input Capacitors.......................................6

6.7 Typical Characteristics................................................7

7 Detailed Description......................................................16

7.1 Overview...................................................................16

7.2 Functional Block Diagram.........................................16

Information.................................................................... 24

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

July 2022

Initial Release

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5 Pin Configuration and Functions

OUT

GND

图5-1. DRV Package, 6-Pin WSON With Thermal Pad (Top View)

表5-1. Pin Functions

TYPE

DESCRIPTION

NO.

NAME

OUT

Regulated output voltage.

No internal connection. Leave open, or connect to ground.

Power-good indicator. Requires an external pullup resistor.

—

Enable input. Logic high = device is on, logic low = device is off, with an internal 3-MΩ

pulldown resistor.

GND

Ground.

Unregulated input voltage.

Connect this pad to the copper area under the package to improve thermal performance.

Use thermal vias to transfer heat to inner layers of the printed circuit board (PCB).

Connect the thermal pad to ground, or leave floating. Do not connect the thermal pad to

any potential other than ground.

Thermal pad

—

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

–0.3

MAX

UNIT

V_IN

IN pin voltage

V_OUT

V_EN

V_PG

T_J

OUT pin voltage

-0.3

EN pin voltage

–0.3

PG pin voltage

–0.3

Junction temperature

Continuous power dissipation⁽³⁾

Storage temperature

150

°C

–55

P_DISS

T_stg

Internally Limited

–65

150

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltages are with respect to the potential at the GND pin.

(3) Internal thermal shutdown circuitry protects the device from permanent damage.

6.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.6

0.8

NOM

MAX

6.5

UNIT

V_IN

Input voltage

V_OUT

V_EN

Output voltage

5.5

EN input voltage

PG pin off voltage

Output current

V_IN

V_PG

6.5

I_OUT

500

125

°C

T_J-MAX-OP

Operating junction temperature

–55

6.4 Thermal Information

LP5912-EP

THERMAL METRIC⁽¹⁾

DRV (WSON)

6 PINS

75.8

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

°C/W

R_θJC(top)

R_θJB

92.6

Junction-to-board thermal resistance

40.0

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

3.3

ψ_JT

40.0

ψ_JB

R_θJC(bot)

15.4

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application

report.

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6.5 Electrical Characteristics

V_IN= V_OUT(NOM)+ 0.5 V or 1.6 V, whichever is greater; V_EN= 1.35 V, C_IN= 1 μF, C_OUT= 1 μF, I_OUT= 1 mA (unless

otherwise stated).^{(1) (2) (3)}

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT VOLTAGE AND REGULATION

For V_OUT(NOM)≥3.3 V,

-2

V_OUT(NOM)+ 0.5 V ≤V_IN≤6.5 V,

I_OUT= 1 mA to 500 mA

For 1.1 V ≤V_OUT(NOM)< 3.3 V,

V_OUT(NOM)+ 0.5 V ≤V_IN≤6.5 V,

I_OUT= 1 mA to 500 mA

Output voltage tolerance

-3

For V_OUT(NOM)< 1.1 V,

1.6 V ≤V_IN≤6.5 V,

I_OUT= 1 mA to 500 mA

ΔV_OUT

For V_OUT(NOM)≥1.1V,

V_OUT(NOM)+ 0.5 V ≤V_IN≤6.5 V

Line regulation

0.8

%/V

For V_OUT(NOM)< 1.1 V,

1.6 V ≤V_IN≤6.5 V

Load regulation

For I_OUT= 1mA to 500 mA

0.0022

%/mA

CURRENT LEVELS

I_SC

I_RO

Short-circuit current limit

T_J= 25°C, ⁽⁴⁾

700

900

1100

150

µA

Reverse leakage current ⁽⁵⁾

V_IN< V_OUT

V_EN= 1.35 V, I_OUT= 0 mA

V_EN= 1.35 V, I_OUT= 500 mA

I_Q

Quiescent current ⁽⁶⁾

µA

400

600

V_EN= 0 V,

–55°C ≤T_J≤85°C

0.2

1.5

Quiescent current

shutdown mode ⁽⁶⁾

I_Q(SD)

µA

V_EN= 0 V

0.2

I_G

Ground-current ⁽⁷⁾

V_EN= 1.35 V, I_OUT= 0 mA

VDO DROPOUT VOLTAGE

V_DO

Dropout voltage ⁽⁸⁾

V_INto V_OUTRIPPLE REJECTION

170

250

180

I_OUT= 500 mA, 1.6 V ≤V_OUT(NOM)< 3.3 V

I_OUT= 500 mA, 3.3 V ≤V_OUT(NOM)≤5.5 V

f = 100 Hz, V_OUT≥1.1 V, I_OUT= 20 mA

f = 1 kHz, V_OUT≥1.1 V, I_OUT= 20 mA

f = 10 kHz, V_OUT≥1.1 V, I_OUT= 20 mA

f = 100 kHz, V_OUT≥1.1 V, I_OUT= 20 mA

f = 100 Hz, 0.8V ≤V_OUT< 1.1 V, I_OUT= 20 mA

f = 1 kHz, 0.8V ≤V_OUT< 1.1 V, I_OUT= 20 mA

f = 10 kHz, 0.8V ≤V_OUT< 1.1 V, I_OUT= 20 mA

f = 100 kHz, 0.8V ≤V_OUT< 1.1 V, I_OUT= 20 mA

PSRR

Power-supply rejection ratio ⁽⁹⁾

OUTPUT NOISE VOLTAGE

I_OUT= 1 mA, BW = 10 Hz to 100 kHz

I_OUT= 500 mA, BW = 10 Hz to 100 kHz

e_N

Noise voltage

μV_RMS

THERMAL SHUTDOWN

Thermal shutdown

temperature

T_SD

160

°C

T_HYS

Thermal shutdown hysteresis

LOGIC INPUT THRESHOLDS

V_EN(OFF)

V_EN(ON)

Off threshold

On threshold

0.25

1.35

V_IN= 6 V, V_EN= 6 V

V_IN= 3.3 V, V_EN= 0 V

µA

Input current at EN

terminal ⁽¹⁰⁾

I_EN

0.001

PG threshold hysteresis (% of

PG_HYS

nominal V_OUT

)

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6.5 Electrical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.5 V or 1.6 V, whichever is greater; V_EN= 1.35 V, C_IN= 1 μF, C_OUT= 1 μF, I_OUT= 1 mA (unless

otherwise stated).^{(1) (2) (3)}

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PG low threshold (% of

PG_LTH

nominal V_OUT

)

V_OL(PG)

I_LKG(PG)

PG pin low-level output voltage V_OUT< PG_LTH, sink current = 1 mA

400

µA

PG pin leakage current

V_OUT< PG_HTH, V_PG= 6 V

TRANSITION CHARACTERISTICS

For V_IN↑and V_OUT(NOM)≥1.1 V,

V_IN= (V_OUT(NOM)+ 0.5 V) to (V_OUT(NOM)+ 1.1 V),

V_INtrise = 30 µs

For V_IN↑and V_OUT(NOM)< 1.1 V,

V_IN= 1.6 V to 2.2 V,

V_INtrise = 30 µs

Line transients ⁽⁹⁾

For V_IN↓and V_OUT(NOM)≥1.1 V,

V_IN= (V_OUT(NOM)+ 0.5 V) to (V_OUT(NOM)+ 1.1 V),

V_INtrise = 30 µs

ΔV_OUT

-1

For V_IN↓and V_OUT(NOM)< 1.1 V,

V_IN= 1.6 V to 2.2 V,

V_INtrise = 30 µs

I_OUT= 5 mA to 500 mA,

I_OUTt_RISE= 10 μs

-45

Load transients ⁽⁹⁾

I_OUT= 500 mA to 5 mA,

I_OUTt_FALL= 10 μs

Overshoot on start-up ⁽⁹⁾

t_ON

Turnon time

From V_EN> V_EN(ON)to V_OUT= 95% of V_OUT(NOM)

200

100

µs

OUTPUT AUTO DISCHARGE RATE

Output discharge pulldown

resistance

R_AD

V_EN= 0 V, V_IN= 3.6 V

Ω

(1) All voltages are with respect to the device GND pin, unless otherwise stated.

(2) Minimum and maximum limits are specified through test, design, or statistical correlation over the junction temperature (T_J) range of

–55°C to +125°C, unless otherwise stated. Typical values represent the most likely parametric norm at T_A= 25°C, and are provided

for reference purposes only.

(3) In applications where high power dissipation and poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP

= 125°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to-ambient thermal resistance of

the part/package in the application (R_θJA), as given by the following equation: T_A-MAX= T_J-MAX-OP–(R_θJA× P_D-MAX).

(4) Short-circuit current (I_SC) is equivalent to current limit. To minimize thermal effects during testing, I_SCis measured with V_OUTpulled to

100 mV below its nominal voltage.

(5) Reverse current (I_RO) is measured at the IN pin.

(6) Quiescent current is defined here as the difference in current between the input voltage source and the load at V_OUT

(7) Ground current is defined here as the total current flowing to ground as a result of all input voltages applied to the device (I_Q+ I_EN).

(8) Dropout voltage (V_DO) is the voltage difference between the input and the output at which the output voltage drops to 150 mV below its

nominal value when V_IN= V_OUT+ 0.5 V. Dropout voltage is not a valid condition for output voltages less than 1.6 V as compliance with

the minimum operating voltage requirement cannot be assured.

(9) This specification is specified by design.

(10) There is a 3-MΩpulldown resistor between the EN pin and GND pin on the device.

6.6 Output and Input Capacitors

over operating free-air temperature range (unless otherwise noted)

PARAMETERS

TEST CONDITIONS

Capacitance for stability

MIN

0.7

NOM

MAX

UNIT

µF

C_IN

Input capacitance ⁽¹⁾

Output capacitance ⁽¹⁾

Output voltage ⁽¹⁾

C_OUT

ESR

µF

500

mΩ

(1) This specification is verified by design.

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6.7 Typical Characteristics

V_IN= V_OUT+ 0.5 V, V_EN= V_IN, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_J= 25°C (unless otherwise noted)

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

-0.1

V_OUTat I_OUT= 1mA

V_PGat I_OUT= 1mA

V_OUTat I_OUT= 500 mA

V_PGat I_OUT= 500 mA

V_EN(ON)

V_EN(OFF)

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Input Voltage (V)

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Input Voltage (V)

D002

D001

图6-2. LP5912-0.9 Output Voltage (V_PG) vs Input Voltage

图6-1. V_ENThresholds vs Input Voltage

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

3.5

V_OUTat I_OUT=1 mA

V_PGat I_OUT=1 mA

V_OUTat I_OUT= 500 mA

V_PGat I_OUT= 500 mA

V_OUTat I_OUT= 1mA

V_PGat I_OUT= 1mA

V_OUTat I_OUT= 500 mA

V_PGat I_OUT= 500mA

3.0

2.5

2.0

1.5

1.0

0.5

0.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

Input Voltage (V)

3.0

3.5

4.0

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

Input Voltage (V)

D004

D003

图6-4. LP5912-3.3 Output Voltage (V_PG) vs Input Voltage

图6-3. LP5912-1.8 Output Voltage (V_PG) vs Input Voltage

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

0.4

0.2

0.0

V_IN

V_OUT

V_PG

V_IN

V_OUT

V_PG

50 100 150 200 250 300 350 400 450 500

Time (ms)

50 100 150 200 250 300 350 400 450 500

Time (ms)

D005

D006

V_IN= 0 V to 1.6 V, I_OUT= 1 mA

V_IN= 0 V to 1.6 V, I_OUT= 500 mA

图6-5. LP5912-0.9 Power Up

图6-6. LP5912-0.9 Power Up

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6.7 Typical Characteristics (continued)

V_IN= V_OUT+ 0.5 V, V_EN= V_IN, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_J= 25°C (unless otherwise noted)

3.0

2.5

2.0

1.5

1.0

0.5

0.0

3.0

2.5

2.0

1.5

1.0

0.5

0.0

V_IN

V_OUT

V_PG

V_IN

V_OUT

V_PG

50 100 150 200 250 300 350 400 450 500

Time (ms)

50 100 150 200 250 300 350 400 450 500

Time (ms)

D007

D008

V_IN= 0 V to 2.3 V, I_OUT= 1 mA

V_IN= 0 V to 2.3 V, I_OUT= 500 mA

图6-8. LP5912-1.8 Power Up

图6-7. LP5912-1.8 Power Up

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

V_IN

V_OUT

V_PG

V_IN

V_OUT

V_PG

50 100 150 200 250 300 350 400 450 500

Time (ms)

50 100 150 200 250 300 350 400 450 500

Time (ms)

D009

D010

V_IN= 0 V to 3.8 V, I_OUT= 1 mA

V_IN= 0 V to 3.8 V, I_OUT= 500 mA

图6-9. LP5912-3.3 Power Up

图6-10. LP5912-3.3 Power Up

T_A= +125°C

T_A= +85°C

T_A= +25°C

T_A= -40°C

T_A= +85°C

T_A= +25°C

T_A= -40°C

0.5

1.5

2.5

3 3.5

V_IN(V)

4.5

5.5

6.5

0.5

1.5

2.5

3 3.5

V_IN(V)

4.5

5.5

6.5

D051

D052

I_OUT= 0 mA

图6-11. LP5912-0.9 I_Q(No Load) vs V_IN

I_OUT= 0 mA

图6-12. LP5912-1.8 I_Q(No Load) vs V_IN

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6.7 Typical Characteristics (continued)

V_IN= V_OUT+ 0.5 V, V_EN= V_IN, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_J= 25°C (unless otherwise noted)

T_A= +125°C

T_A= +85°C

T_A= +25°C

T_A= -40°C

0.5

1.5

2.5

3 3.5

V_IN(V)

4.5

5.5

6.5

D053

I_OUT= 0 mA

V_EN= 0 V

图6-13. LP5912-3.3 I_Q(No Load) vs V_IN

图6-14. LP5912-0.9 I_Q(SD)vs V_IN

V_EN= 0 V

图6-15. LP5912-1.8 I_Q(SD)vs V_IN

图6-16. LP5912-3.3 I_Q(SD)vs V_IN

500

450

400

350

300

250

200

150

100

500

450

400

350

300

250

200

150

100

T_A= -40°C

T_A= +25°C

T_A= +85°C

T_A= +125°C

T_A= -40°C

T_A= +25°C

T_A= +85°C

T_A= +125°C

50 100 150 200 250 300 350 400 450 500

I_OUT(mA)

50 100 150 200 250 300 350 400 450 500

I_OUT(mA)

D057

D058

V_IN= 1.6 V

图6-17. LP5912-0.9 I_Q(SD)vs I_OUT

图6-18. LP5912-1.8 I_Q(SD)vs I_OUT

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6.7 Typical Characteristics (continued)

V_IN= V_OUT+ 0.5 V, V_EN= V_IN, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_J= 25°C (unless otherwise noted)

500

450

400

350

300

250

200

150

100

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

T_A= -40°C

T_A= +25°C

T_A= +85°C

T_A= +125°C

10 20

100

1000

10000 100000 1000000 1E+7

50 100 150 200 250 300 350 400 450 500

I_OUT(mA)

Frequency (Hz)

D011

D059

V_IN= 1.6 V, I_OUT= 20 mA

图6-20. LP5912-0.9 PSRR vs Frequency

图6-19. LP5912-3.3 I_Q(SD)vs I_OUT

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

I_OUT= 1 mA

I_OUT= 10 mA

I_OUT= 100 mA

I_OUT= 500 mA

-20

-40

-60

-80

-100

-120

10 20

100

1000

10000 100000 1000000 1E+7

10 20

100

1000

10000 100000 1000000 1E+7

Frequency (Hz)

D012

D013

V_IN= 1.6 V

I_OUT= 20 mA

图6-22. LP5912-1.8 PSRR vs Frequency

图6-21. LP5912-0.9 PSRR vs Frequency

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

I_OUT= 1 mA

I_OUT= 10 mA

I_OUT= 100 mA

I_OUT= 500 mA

10 20

100

1000

10000 100000 1000000 1E+7

10 20

100

1000

10000 100000 1000000 1E+7

Frequency (Hz)

D014

D015

I_OUT= 20 mA

图6-24. LP5912-3.3 PSRR vs Frequency

图6-23. LP5912-1.8 PSRR vs Frequency

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6.7 Typical Characteristics (continued)

V_IN= V_OUT+ 0.5 V, V_EN= V_IN, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_J= 25°C (unless otherwise noted)

0.8

0.6

0.4

0.2

2.4

2.3

2.2

2.1

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

D V_OUT(mV)

V_IN(V)

I_OUT= 1 mA

I_OUT= 10 mA

I_OUT= 100 mA

I_OUT= 500 mA

1.9

1.8

1.7

1.6

1.5

1.4

-0.2

-0.4

-0.6

-0.8

-1

50 100 150 200 250 300 350 400 450 500

Time (µs)

10 20

100

1000

10000 100000 1000000 1E+7

D017

Frequency (Hz)

D016

V_IN= 1.6 V to 2.2 V, t_r= 30 µs

图6-26. LP5912-0.9 Line Transient

图6-25. LP5912-3.3 PSRR vs Frequency

0.8

0.6

0.4

0.2

2.4

2.3

2.2

2.1

0.8

0.6

0.4

0.2

3.1

DV_OUT(mV)

V_IN(V)

D V_OUT(mV)

V_IN(V)

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

1.9

1.8

1.7

1.6

1.5

1.4

-0.2

-0.4

-0.6

-0.8

-1

-0.2

-0.4

-0.6

-0.8

-1

50 100 150 200 250 300 350 400 450 500

Time (ms)

50 100 150 200 250 300 350 400 450 500

Time (µs)

D018

D019

V_IN= 2.2 V to 1.6 V, t_f= 30 µs

V_IN= 2.3 V to 2.9 V, t_r= 30 µs

图6-27. LP5912-0.9 Line Transient

图6-28. LP5912-1.8 Line Transient

0.8

0.6

0.4

0.2

3.1

0.8

0.6

0.4

0.2

4.6

4.5

4.4

4.3

4.2

4.1

D V_OUT(mV)

V_IN(V)

D V_OUT(mV)

V_IN(V)

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

-0.2

-0.4

-0.6

-0.8

-1

-0.2

-0.4

-0.6

-0.8

-1

3.9

3.8

3.7

3.6

50 100 150 200 250 300 350 400 450 500

Time (µs)

50 100 150 200 250 300 350 400 450 500

Time (µs)

D020

D021

V_IN= 2.9 V to 2.3 V, t_f= 30 µs

V_IN= 3.8 V to 4.4 V, t_r= 30 µs

图6-29. LP5912-1.8 Line Transient

图6-30. LP5912-3.3 Line Transient

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6.7 Typical Characteristics (continued)

V_IN= V_OUT+ 0.5 V, V_EN= V_IN, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_J= 25°C (unless otherwise noted)

0.8

0.6

0.4

0.2

4.6

4.5

4.4

4.3

4.2

4.1

600

500

400

300

200

100

D V_OUT(mV)

V_IN(V)

D V_OUT(mV)

I_OUT(mA)

-0.2

-0.4

-0.6

-0.8

-1

-20

-40

-60

3.9

3.8

3.7

3.6

50 100 150 200 250 300 350 400 450 500

Time (µs)

80 100 120 140 160 180 200

Time (µs)

D022

D023

V_IN= 4.4 V to 3.8 V, t_f= 30 µs

V_IN= 1.6 V, I_OUT= 5 mA to 500 mA, t_r= 10 µs

图6-31. LP5912-3.3 Line Transient

图6-32. LP5912-0.9 Load Transient Response

600

500

400

300

200

100

600

500

400

300

200

100

D V_OUT(mV)

I_OUT(mA)

D V_OUT(mV)

I_OUT(mA)

-20

-40

-60

-20

-40

-60

80 100 120 140 160 180 200

Time (µs)

80 100 120 140 160 180 200

Time (µs)

D024

D025

V_IN= 1.6 V, I_OUT= 500 mA to 5 mA, t_f= 10 µs

I_OUT= 5 mA to 500 mA, t_r= 10 µs

图6-33. LP5912-0.9 Load Transient Response

图6-34. LP5912-1.8 Load Transient Response

600

500

400

300

200

100

600

D V_OUT(mV)

I_OUT(mA)

D V_OUT(mV)

I_OUT(mA)

500

400

300

200

100

-20

-40

-60

-20

-40

-60

80 100 120 140 160 180 200

Time (µs)

80 100 120 140 160 180 200

Time (µs)

D026

D027

I_OUT= 500 mA to 5 mA, t_f= 10 µs

图6-35. LP5912-1.8 Load Transient Response

I_OUT= 5 mA to 500 mA, t_r= 10 µs

图6-36. LP5912-3.3 Load Transient Response

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6.7 Typical Characteristics (continued)

V_IN= V_OUT+ 0.5 V, V_EN= V_IN, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_J= 25°C (unless otherwise noted)

600

500

400

300

200

100

2.5

D V_OUT(mV)

I_OUT(mA)

V_EN(V)

V_OUT(V)

V_PG(V)

1.5

-20

-40

-60

0.5

80 100 120 140 160 180 200

Time (µs)

D028

50 100 150 200 250 300 350 400 450 500

Time (µs)

I_OUT= 500 mA to 5 mA, t_f= 10 µs

图6-37. LP5912-3.3 Load Transient Response

D031

I_OUT= 0 mA, C_OUT= 1 µF

图6-38. LP5912-1.8 V_OUTvs V_EN(ON)

2.5

V_EN(V)

V_OUT(V)

V_PG(V)

V_EN(V)

V_OUT(V)

V_PG(V)

1.5

0.5

50 100 150 200 250 300 350 400 450 500

Time (µs)

50 100 150 200 250 300 350 400 450 500

Time (µs)

D032

D033

I_OUT= 0 mA, C_OUT= 1 µF

I_OUT= 1 mA, C_OUT= 1 µF

图6-39. LP5912-1.8 V_OUTvs V_EN(OFF)

图6-40. LP5912-1.8 V_OUTvs V_EN(ON)

2.5

V_EN(V)

V_OUT(V)

V_PG(V)

V_EN(V)

V_OUT(V)

V_PG(V)

1.5

0.5

50 100 150 200 250 300 350 400 450 500

Time (µs)

50 100 150 200 250 300 350 400 450 500

Time (µs)

D034

D035

I_OUT= 1 mA, C_OUT= 1 µF

I_OUT= 500 mA, C_OUT= 1 µF

图6-41. LP5912-1.8 V_OUTvs V_EN(OFF)

图6-42. LP5912-1.8 V_OUTvs V_EN(ON)

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6.7 Typical Characteristics (continued)

V_IN= V_OUT+ 0.5 V, V_EN= V_IN, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_J= 25°C (unless otherwise noted)

2.2

225

200

175

150

125

100

V_EN(V)

V_OUT(V)

V_PG(V)

1.8

1.6

1.4

1.2

0.8

0.6

0.4

0.2

-40°C

25°C

85°C

125°C

50 100 150 200 250 300 350 400 450 500

I_OUT(mA)

Time (µs)

D041

D036

I_OUT= 500 mA, C_OUT= 1 µF

图6-43. LP5912-1.8 V_OUTvs V_EN(OFF)

图6-44. LP5912-1.8 Dropout Voltage (V_DO) vs I_OUT

225

200

175

150

125

100

1.2

-40°C

25°C

85°C

125°C

1 mA

500 mA

0.8

0.6

0.4

0.2

100

1000 10000

Frequency (Hz)

100000

1000000

50 100 150 200 250 300 350 400 450 500

I_OUT(mA)

D043

D042

V_IN= 1.6 V

图6-46. LP5912-0.9 Noise vs Frequency

图6-45. LP5912-3.3 Dropout Voltage (V_DO) vs I_OUT

1.2

1 mA

500 mA

1 mA

500 mA

0.8

0.6

0.4

0.2

0.8

0.6

0.4

0.2

100

1000 10000

Frequency (Hz)

100000

1000000

100

1000 10000

Frequency (Hz)

100000

1000000

D044

D045

图6-47. LP5912-1.8 Noise vs Frequency

图6-48. LP5912-3.3 Noise vs Frequency

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6.7 Typical Characteristics (continued)

V_IN= V_OUT+ 0.5 V, V_EN= V_IN, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_J= 25°C (unless otherwise noted)

500

400

300

200

100

300

280

260

240

220

200

180

160

140

120

100

V_EN(V)

V_OUT(V)

I_IN(mA)

-50

50 100 150 200 250 300 350 400 450

Time (ms)

-50

-25

Junction Temperature (°C)

100

125

D061

D060

C_IN= open, I_OUT= 500 mA, C_OUT= 1 µF

图6-50. LP5912-3.3 Inrush Current

I_OUT= 0 mA (no load)

图6-49. LP5912-3.3 Turn-On Time vs Junction Temperature

4.5

100

4.5

1.5

V_EN(V)

V_OUT(V)

I_IN(mA)

V_EN(V)

V_OUT(V)

I_IN(A)

1.35

1.2

3.5

1.05

0.9

3.5

2.5

0.75

0.6

2.5

1.5

0.45

0.3

1.5

0.5

0.15

0.5

-50

50 100 150 200 250 300 350 400 450

Time (ms)

-50

50 100 150 200 250 300 350 400 450

Time (ms)

D063

D062

C_IN= open, I_OUT= 500 mA, C_OUT= 10 µF

C_IN= open, I_OUT= 1 mA, C_OUT= 1 µF

图6-52. LP5912-3.3 Inrush Current

图6-51. LP5912-3.3 Inrush Current

1.5

V_EN(V)

V_OUT(V)

I_IN(A)

4.5

1.35

1.2

3.5

1.05

0.9

2.5

0.75

0.6

1.5

0.45

0.3

0.5

0.15

-50

50 100 150 200 250 300 350 400 450

Time (ms)

D064

C_IN= open, I_OUT= 1 mA, C_OUT= 10 µF

图6-53. LP5912-3.3 Inrush Current

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7 Detailed Description

7.1 Overview

The LP5912-EP is a low-noise, high PSRR, low-dropout regulator (LDO) capable of sourcing a 500-mA load.

The LP5912-EP can operate down to a 1.6-V input voltage and a 0.8-V output voltage. With this combination of

low noise, high PSRR, and low output voltage, the device is designed to power a multitude of loads from noise-

sensitive communication components to battery-powered systems.

The LP5912-EP contains several features, as shown in the Functional Block Diagram:

• Internal output resistor divider feedback

• Small size and low-noise internal protection circuit current limit

• Reverse current protection

• Current limit and inrush current protection

• Thermal shutdown

• Output auto discharge for fast turnoff

• Power-good output, with a fixed 140-µs typical delay

7.2 Functional Block Diagram

Current

Limit

OUT

R_AD

100 ꢀ

45 kꢀ

V_IN

Output

Discharge

V_BG

Control

140-µs

DELAY

3 Mꢀ

GND

7.3 Feature Description

7.3.1 Enable (EN)

The LP5912-EP enable (EN) pin is internally held low by a 3-MΩ resistor to GND. The EN pin voltage must be

higher than the V_EN(ON)threshold to ensure that the device is fully enabled under all operating conditions. The

EN pin voltage must be lower than the V_EN(OFF)threshold to ensure that the device is fully disabled and the

automatic output discharge is activated.

When the device is disabled the output stage is disabled, the PG output pin is low, and the output automatic

discharge is on.

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7.3.2 Output Automatic Discharge (R_AD

)

The LP5912-EP output employs an internal 100-Ω (typical) pulldown resistance to discharge the output when the

EN pin is low. If the LP5912-EP EN pin is low (the device is off) and the OUT pin is held high by a secondary

supply, current flows from the secondary supply through the automatic discharge pulldown resistor to ground.

7.3.3 Reverse Current Protection (I_RO

)

The LP5912-EP input is protected against reverse current when the output voltage is higher than the input

voltage. In the event that extra output capacitance is used at the output, a power-down transient at the input

normally causes a large reverse current through a conventional regulator. The LP5912-EP includes a reverse

voltage detector that trips when V_INdrops below V_OUT, shutting off the regulator and opening the p-channel

metal-oxide-semiconductor field effect transistor (PMOS) body diode connection, preventing any reverse current

from the OUT pin from flowing to the IN pin.

If the LP5912-EP EN pin is low (the LP5912-EP is off) and the OUT pin is held high by a secondary supply,

current flows from the secondary supply through the automatic discharge pulldown resistor to ground. This

scenario is not reverse current, but is instead automatic discharge pulldown current.

Reverse current (I_RO) is measured at the IN pin.

7.3.4 Internal Current Limit (I_SC

)

The internal current limit circuit protects the LDO against high-load current faults or shorting events. The LDO is

not designed to operate continuously at the I_SCcurrent limit. During a current-limit event, the LDO sources

constant current. Therefore, the output voltage falls when load impedance decreases. If a current limit occurs

and the resulting output voltage is low, excessive power may be dissipated across the LDO, resulting in a

thermal shutdown of the output.

7.3.5 Thermal Overload Protection (T_SD

)

Thermal shutdown disables the output when the junction temperature rises to approximately 160°C, which

allows the device to cool. When the junction temperature cools to approximately 145°C, the output circuitry

enables. Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit

may cycle on and off. This thermal cycling limits the dissipation of the regulator, thus protecting the regulator

from damage as a result of overheating.

7.3.6 Power-Good Output (PG)

The LP5912-EP has a power-good function that works by toggling the state of the PG output pin. When the

output voltage falls below the PG threshold voltage (PG_LTH), the PG pin open-drain output engages (low

impedance to GND). When the output voltage rises above the PG threshold voltage (PGV_HTH), the PG pin

becomes high impedance. By connecting a pullup resistor to an external supply, any downstream device can

receive PG as a logic signal. Make sure that the external pullup supply voltage results in a valid logic signal for

the receiving device or devices. Use a pullup resistor from 10 kΩ to 100 kΩ for best results.

The input supply, V_IN, must be no less than the minimum operating voltage of 1.6 V to ensure that the PG pin

output status is valid. The PG pin output status is undefined when V_INis less than 1.6 V.

In the power-good function, the PG output pin being pulled high is typically delayed 140 µs after the output

voltage rises above the PG_HTHthreshold voltage. If the output voltage rises above the PG_HTHthreshold and then

falls below the PG_LTHthreshold voltage, the PG pin falls immediately with no delay time.

If the PG function is not needed, the pullup resistor can be eliminated, and the PG pin can be either connected

to ground or left floating.

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7.4 Device Functional Modes

7.4.1 Enable (EN)

The LP5912-EP EN pin is internally held low by a 3-MΩ resistor to GND. The EN pin voltage must be higher

than the V_EN(ON)threshold to ensure that the device is fully enabled under all operating conditions. When the EN

pin voltage is lower than the V_EN(OFF)threshold, the output stage is disabled, the PG pin goes low, and the

output automatic discharge circuit is activated. Any charge on the OUT pin is discharged to ground through the

internal 100-Ω (typical) output auto discharge pulldown resistance.

7.4.2 Minimum Operating Input Voltage (V_IN)

The LP5912-EP does not include a dedicated undervoltage lockout (UVLO) circuit. The device internal circuit is

not fully functional until V_INis at least 1.6 V. The output voltage is not regulated until V_INhas reached at least the

greater of 1.6 V or (V_OUT+ V_DO).

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8 Applications and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The LP5912-EP is designed to meet the requirements of RF and analog circuits by providing low noise, high

PSRR, low quiescent current, and low line or load transient response. The device offers excellent noise

performance without the need for a noise bypass capacitor and is stable with input and output capacitors with a

value of 1 μF. The device delivers this performance in an industry standard WSON package, which for this

device is specified with an operating junction temperature (T_J) of –55°C to +125°C.

8.2 Typical Application

图 8-1 shows a typical application circuit for the LP5912-EP. Input and output capacitances may need to be

increased above the 1-μF minimum for some applications.

V_IN

V_OUT

OUT

C_IN

LP5912-EP

C_OUT

GND

R_PG

V_EN

V_PG

图8-1. LP5912-EP Typical Application

8.2.1 Design Requirements

Use the parameters listed in 表8-1 for typical RF linear regulator applications.

表8-1. Design Parameters

DESIGN PARAMETER

Input voltage

EXAMPLE VALUE

1.6 V to 6.5 V

0.8 V to 5.5 V

500 mA

Output voltage

Output current

Output capacitor

1 µF to 10 µF

5 mΩ to 500 mΩ

Input and output capacitor ESR range

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8.2.2 Detailed Design Procedure

8.2.2.1 External Capacitors

As with most low-dropout regulators, the LP5912-EP requires external capacitors for regulator stability. The

device is specifically designed for portable applications requiring minimum board space and the smallest

possible components. These capacitors must be correctly selected for good performance.

8.2.2.2 Input Capacitor

An input capacitor is required for stability. The input capacitor must be at least equal to, or greater than, the

output capacitor for good load-transient performance. A capacitor of at least 1 µF must be connected between

the LP5912-EP IN pin and ground for stable operation over full load-current range. Having more output than

input capacitance is acceptable, as long as the input is at least 1 µF.

The input capacitor must be located no more than 1 cm from the input pin and returned to a clean analog

ground. Any good-quality ceramic, tantalum, or film capacitor can be used at the input.

备注

To ensure stable operation, good PCB practices must be employed to minimize ground impedance

and keep input inductance low. If these conditions cannot be met, or if long leads connect the battery

or other power source to the LP5912-EP, increase the value of the input capacitor to at least 10 µF.

Also, tantalum capacitors can suffer catastrophic failures resulting from surge current when connected

to a low-impedance source of power (such as a battery or a very large capacitor). If a tantalum

capacitor is used at the input, the capacitor must be verified by the manufacturer to have a surge

current rating sufficient for the application. There are no requirements for the equivalent series

resistance (ESR) on the input capacitor, but tolerance and temperature coefficient must be considered

when selecting the capacitor to ensure the capacitance remains at 1 μF ±30% over the entire

operating temperature range.

8.2.2.3 Output Capacitor

The LP5912-EP is designed specifically to work with a very small ceramic output capacitor, typically 1 µF. Use a

ceramic capacitor (dielectric types of X5R or X7R) in the 1-µF to 10-µF range, and with an ESR from 5 mΩ to

500 mΩ, in the LP5912-EP application circuit. For this device, the output capacitor must be connected between

the OUT pin with a good connection back to the GND pin.

Tantalum or film capacitors can also be used at the device output, V_OUT, but these components are not as

attractive for reasons of size and cost (see the Capacitor Characteristics section).

The output capacitor must meet the requirement for the minimum value of capacitance and have an ESR value

that is within the range of 5 mΩ to 500 mΩ for stability.

8.2.2.4 Capacitor Characteristics

The LP5912-EP is designed to work with ceramic capacitors on the input and output to take advantage of the

benefits they offer. For capacitance values in the range of 1 µF to 10 µF, ceramic capacitors are the smallest,

least expensive, and have the lowest ESR values, thus making them best for eliminating high-frequency noise.

The ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR

stability requirement for the LP5912-EP.

The preferred choice for temperature coefficient in a ceramic capacitor is X7R. This type of capacitor is the most

stable and holds the capacitance within ±15% over the temperature range. Tantalum capacitors are less

desirable than ceramic for use as output capacitors because they are more expensive when comparing

equivalent capacitance and voltage ratings in the 1-µF to 10-µF range.

Another important consideration is that tantalum capacitors have higher ESR values than equivalent size

ceramics. Although a tantalum capacitor can possibly be found with an ESR value within the stable range, low

ESR tantalum capacitors are offered with larger capacitance (which means bigger and more costly) than a

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ceramic capacitor with the same ESR value. Also, the ESR of a typical tantalum increases at approximately 2:1

as the temperature goes from 25°C down to –40°C, so some guard band must be allowed.

8.2.2.5 Remote Capacitor Operation

To ensure stability, the LP5912-EP requires at least a 1-μF capacitor at the OUT pin. There is no strict

requirement for the location of the output capacitor in regards to the LDO OUT pin; the output capacitor can be

located 5 cm to 10 cm away from the LDO. This flexibility means that there is no need to have a special

capacitor close to the OUT pin if there are already respective capacitors in the system. This placement flexibility

requires that the output capacitor be connected directly between the LP5912-EP OUT pin and GND pin with no

vias. This remote capacitor feature can help designers minimize the number of capacitors in the system.

As a good design practice, keep the wiring parasitic inductance at a minimum. Thus, use traces that are as wide

as possible from the LDO output to the capacitors, keeping the LDO output trace layer as close to ground layer

as possible and avoiding vias on the path. If there is a need to use vias, implement as many vias as possible

between the connection layers. Keep parasitic wiring inductance less than 35 nH. For applications with fast load

transients, use an input capacitor equal to (or larger than) the sum of the capacitance at the output node for the

best load-transient performance.

8.2.2.6 Power Dissipation

Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is

critical to ensuring reliable operation. Device power dissipation can be calculated with 方程式 1, and depends on

input voltage, output voltage, and load conditions of the design.

P_D(MAX)= (V_IN(MAX)–V_OUT) × I_OUT

(1)

Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available

voltage drop option that is greater than the dropout voltage (V_DO). However, keep in mind that higher voltage

drops result in better dynamic (that is, PSRR and transient) performance.

On the WSON (DRV) package, the primary conduction path for heat is through the exposed power pad into the

PCB. To ensure the device does not overheat, connect the exposed pad (through thermal vias) to an internal

ground plane with an appropriate amount of copper PCB area.

According to 方程式 2 or 方程式 3, power dissipation and junction temperature are most often related by the

junction-to-ambient thermal resistance (R_θJA) of the combined PCB and device package and the temperature of

the ambient air (T_A):

T_J(MAX)= T_A(MAX)+ (R_θJA× P_D(MAX)

)

(2)

(3)

P_D= (T_J(MAX)–T_A(MAX)) / R_θJA

Unfortunately, this R_θJAis highly dependent on the heat-spreading capability of the particular PCB design, and

therefore varies according to the total copper area, copper weight, and location of the planes. The R_θJA

recorded in the Thermal Information table is determined by the specific EIA/JEDEC JESD51-7 standard for PCB

and copper-spreading area, and is to be used only as a relative measure of package thermal performance. For a

well-designed thermal layout, R_θJAis actually the sum of the package junction-to-case (bottom) thermal

resistance (R_θJCbot) plus the thermal resistance contribution by the PCB copper area acting as a heat sink.

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8.2.2.7 Estimating Junction Temperature

The EIA/JEDEC standard recommends the use of psi (Ψ) thermal characteristics to estimate the junction

temperatures of surface-mount devices on a typical PCB board application. These characteristics are not true

thermal resistance values, but rather package-specific thermal characteristics that offer practical and relative

means of estimating junction temperatures. These psi metrics are determined to be significantly independent of

copper-spreading area. The key thermal characteristics (Ψ_JTand Ψ_JB) are used in accordance with 方程式 4 or

方程式5 and are given in the Thermal Information table.

T_J(MAX)= T_TOP+ (Ψ_JT× P_D(MAX)

)

(4)

where:

• P_D(MAX)is explained in 方程式3

• T_TOPis the temperature measured at the center-top of the device package

T_J(MAX)= T_BOARD+ (Ψ_JB× P_D(MAX)

)

(5)

where:

• P_D(MAX)is explained in the Power Dissipation section

• T_BOARDis the PCB surface temperature measured 1 mm from the device package and centered on the

package edge

For more information about the thermal characteristics Ψ_JTand Ψ_JB, see the Semiconductor and IC Package

Thermal Metrics application note; for more information about measuring T_TOPand T_BOARD, see the Using New

Thermal Metrics application note; and for more information about the EIA/JEDEC JESD51 PCB used for

validating R_θJA, see the Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs

application note. These application notes are available at www.ti.com.

8.2.3 Application Curves

2.5

2.0

1.5

1.0

0.5

0.0

2.5

2.0

1.5

1.0

0.5

0.0

V_EN(V)

V_OUT(V)

V_PG(V)

V_EN(V)

V_OUT(V)

V_PG(V)

50 100 150 200 250 300 350 400 450 500

Time (µs)

D029

D030

V_IN= 2.3 V, I_OUT= 500 mA, C_OUT= 1 µF

V_IN= 2.3 V, I_OUT= 500 mA (3.6 Ω), C_OUT= 1 µF

图8-2. LP5912-1.8 V_OUTvs V_EN(On)

图8-3. LP5912-1.8 V_OUTvs V_EN(Off)

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8.3 Power Supply Recommendations

This device is designed to operate from an input supply voltage range of 1.6 V to 6.5 V. The input supply must

be well regulated and free of spurious noise. To ensure that the LP5912-EP output voltage is well regulated and

dynamic performance is optimum, the input supply must be at least V_OUT+ 0.5 V. A minimum capacitor value of

1 µF is required to be within 1 cm of the IN pin.

8.4 Layout

8.4.1 Layout Guidelines

The dynamic performance of the LP5912-EP is dependent on the layout of the PCB. PCB layout practices that

are adequate for typical LDOs can degrade the PSRR, noise, or transient performance of the LP5912-EP.

Best performance is achieved by placing C_INand C_OUTon the same side of the PCB as the LP5912-EP, and as

close to the package as practical. The ground connections for C_INand C_OUTmust route back to the LP5912-EP

ground pin using as wide and as short of a copper trace as practical.

Connections using long trace lengths, narrow trace widths, or connections through vias must be avoided. Such

connections add parasitic inductances and resistance that result in inferior performance, especially during

transient conditions.

8.4.2 Layout Example

Thermal Vias (2)

OUT

C_OUT

C_IN

GND

R_PG

图8-4. LP5912-EP Layout Example

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9 Device and Documentation Support

9.1 Documentation Support

9.1.1 Related Documentation

For additional information, see the following:

• Texas Instruments, AN1187 Leadless Leadframe Package (LLP) application note

• Texas Instruments, Semiconductor and IC Package Thermal Metrics application report

• Texas Instruments, Using New Thermal Metrics application report

• Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs

application report

9.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

9.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

10 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com

21-Jul-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LP591209MDRVREP

LP591212MDRVREP

LP591218MDRVREP

LP591225MDRVREP

LP591230MDRVREP

LP591233MDRVREP

LP591250MDRVREP

V62/22601-04XE

ACTIVE

WSON

DRV

3000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-55 to 125

2VC5

12MB

12MD

2VD5

12MG

12MF

2VE5

12MB

12MD

2VD5

12MG

12MF

2VE5

Samples

NIPDAU

V62/22601-06XE

V62/22601-07XE

V62/22601-09XE

V62/22601-10XE

V62/22601-11XE

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

21-Jul-2023

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LP5912-EP :

Catalog : LP5912

•

Automotive : LP5912-Q1

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

GENERIC PACKAGE VIEW

DRV 6

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4206925/F

PACKAGE OUTLINE

DRV0006A

WSON - 0.8 mm max height

SCALE 5.500

PLASTIC SMALL OUTLINE - NO LEAD

2.1

1.9

PIN 1 INDEX AREA

2.1

1.9

0.8

0.7

SEATING PLANE

0.08 C

(0.2) TYP

0.05

0.00

0.1

EXPOSED

THERMAL PAD

1.3

1.6 0.1

4X 0.65

0.35

0.25

PIN 1 ID

(OPTIONAL)

0.3

0.2

0.1

C A

0.05

4222173/B 04/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DRV0006A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

6X (0.45)

6X (0.3)

(1)

SYMM

(1.6)

(1.1)

4X (0.65)

SYMM

(1.95)

(R0.05) TYP

(

0.2) VIA

TYP

LAND PATTERN EXAMPLE

SCALE:25X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222173/B 04/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.

www.ti.com

EXAMPLE STENCIL DESIGN

DRV0006A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

SYMM

6X (0.45)

METAL

6X (0.3)

(0.45)

SYMM

4X (0.65)

(0.7)

(R0.05) TYP

(1)

(1.95)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD #7

88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:30X

4222173/B 04/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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LP591209MDRVREP [TI]

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