LP8340CDT-3.3/NOPB [TI]
3.3V FIXED POSITIVE LDO REGULATOR, 1V DROPOUT, PSSO2, DPAK-3;
| 型号： | LP8340CDT-3.3/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3V FIXED POSITIVE LDO REGULATOR, 1V DROPOUT, PSSO2, DPAK-3 输出元件 调节器 |
| 文件： | 总18页 (文件大小：1323K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP8340
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SNVS221D –FEBRUARY 2003–REVISED APRIL 2013
LP8340 Low Dropout, Low IQ, 1.0A CMOS Linear Regulator
Check for Samples: LP8340
1
FEATURES
DESCRIPTION
The LP8340 low-dropout CMOS linear regulator is
available in 5V, 3.3V, 2.5V, 1.8V and adjustable
output versions. Packaged in the 6ld WSON package
and 3ld PFM. The LP8340 can deliver up to 1.0A
output current.
2
•
•
•
•
•
•
•
•
•
•
±1.5% Typical VOUT Tolerance
420mV Typical Dropout @ 1.0A (VO = 5V)
Wide Operating Range 2.7V to 10V
Internal 1.0A PMOS Output Transistor
19µA Typical Quiescent Current
Thermal Overload Limiting
Typical dropout voltage is 420mV at 1.0A for the 5.0V
version, 540mV at 1.0A for the 3.3V version, 670mV
at 1.0A for the 2.5V version and 680mV at 800mA for
the 1.8V version.
Foldback Current Limiting
Zener Trimmed Bandgap Reference
Space Saving WSON package
Temperature Range
The LP8340 includes a zener trimmed bandgap
voltage reference, foldback current limiting and
thermal overload limiting.
–
–
LP8340C 0°C to 125°C
The LP8340 features a PMOS output transistor which
unlike PNP type low dropout regulators requires no
base drive current. This allows the device ground
current to remain less than 50µA over operating
temperature, supply voltage and irrespective of the
load current.
LP8340I −40°C to 125°C
APPLICATIONS
•
•
•
•
Hard Disk Drives
Notebook Computers
Battery Powered Electronics
Portable Instrumentation
Typical Applications
V
OUT
V
IN
V
V
IN
OUT
1.0µF
Ceramic
1.0µF
Ceramic
V
Sense
OUT
(LLP only)
GND
Figure 1. Fixed VOUT
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
LP8340
SNVS221D –FEBRUARY 2003–REVISED APRIL 2013
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3.3V
1.5V
V
V
OUT
IN
1.0µF
Ceramic
1.0µF
Ceramic
25k
ADJ
125k
GND
Figure 2. Adjustable VOUT
Connection Diagrams
Bottom View
Bottom View
V
1
V
1
N/C
3
GND
2
N/C
3
IN
IN
GND
2
PIN 1 ID
PIN 1 ID
HEATSINK
is GND
HEATSINK
is GND
6
5
4
6
5
4
V
V
ADJ
IN
OUT
V
V
V
OUT
IN
OUT
Sense
Figure 3. 6-Pin WSON Package
Fixed Output Voltage
See Package Number NGD0006A
Figure 4. 6-Pin WSON Package
Adjustable Output Voltage
See Package Number NGD0006A
NOTE
VIN Pins (Pin 1 & 6) must be connected together externally for full 1 amp operation
(500mA max per pin).
VOUT Sense (Pin 5) must be connected to VOUT (Pin 4).
Top View
Figure 5. PFM Package
See Package Number NDP0003B
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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SNVS221D –FEBRUARY 2003–REVISED APRIL 2013
Absolute Maximum Ratings(1)(2)(3)
VIN, VOUT, VOUT Sense, ADJ
Storage Temperature Range
Junction Temperature (TJ)
−0.3V to 12V
−65°C to 160°C
150°C
Power Dissipation
See(4)
ESD Rating
Human Body Model(5)
Machine Model
2kV
200V
(1) Absolute Maximum ratings indicate limits beyond which damage may occur. Electrical specifications do not apply when operating the
device outside of its rated operating conditions.
(2) All voltages are with respect to the potential at the ground pin.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
T
- T
A
J(MAX)
P
D
=
q
JA
(4) Maximum Power dissipation for the device is calculated using the following equations:
where TJ(MAX) is the maximum
junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. The value of the θJA for the
WSON package is specifically dependant on the PCB trace area, trace material, and the number of layers and thermal vias. For
improved thermal resistance and power dissipation for the WSON package, refer to Application Note AN-1187 (SNOA401).
(5) Human body model 1.5kΩ in series with 100pF.
Operating Ratings(1)(2)
Supply Voltage
Temperature Range
LP8340C
2.7 to 10V
0°C to 125°C
LP8340I
−40°C to 125°C
(1) Absolute Maximum ratings indicate limits beyond which damage may occur. Electrical specifications do not apply when operating the
device outside of its rated operating conditions.
(2) All voltages are with respect to the potential at the ground pin.
LP8340C Electrical Characteristics
Unless otherwise specified all limits ensured for VIN = VO+ 1V, CIN = COUT = 10μF, TJ = 25°C. Boldface limits apply over the
full operating temperature range of TJ = 0°C to 125°C
Symbol
VIN
Parameter
Input Voltage
Conditions
Min(1)
2.7
Typ(2)
Max(1)
Units
LP8340-ADJ,1.8, 2.5
LP8340-3.3, 5.0
10
10
V
VOUT
Output Voltage
LP8340-ADJ, ADJ = OUT
IOUT = 10mA, VIN = 2.7V, TJ = 25°C
100μA ≤IOUT≤ 800mA, 3.0V ≤VIN≤VOUT +4V
800mA <IOUT ≤1.0A, 3.2V ≤VIN ≤VOUT +4V
1.231
1.213
1.213
1.269
1.288
1.288
1.250
1.800
V
V
LP8340-1.8
IOUT = 10mA, VIN = 2.8V, TJ = 25°C
100μA ≤IOUT ≤800mA, 3.2V ≤VIN≤6V
800mA <IOUT ≤1.0A, 3.4V ≤VIN ≤6V
1.773
1.746
1.746
1.827
1.854
1.854
LP8340-2.5
IOUT = 10mA, VIN = 3.8V, TJ = 25°C
100μA ≤IOUT ≤1.0A, 3.8V ≤VIN ≤6.5V
2.463
2.425
2.500
3.300
5.000
2.538
2.575
V
V
V
LP8340-3.3
IOUT = 10mA, VIN = 4.3V TJ = 25°C
100μA ≤IOUT ≤1.0A, 4.3V ≤VIN ≤7.5V
3.250
3.201
3.350
3.399
LP8340-5.0
IOUT = 10mA, VIN = 6V, TJ = 25°C
100μA ≤IOUT ≤1.0A, 6V ≤VIN ≤9V
4.925
4.850
5.075
5.150
(1) All limits are specified by testing or statistical analysis.
(2) Typical Values represent the most likely parametric norm.
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LP8340C Electrical Characteristics (continued)
Unless otherwise specified all limits ensured for VIN = VO+ 1V, CIN = COUT = 10μF, TJ = 25°C. Boldface limits apply over the
full operating temperature range of TJ = 0°C to 125°C
Symbol
Parameter
Load Regulation
Conditions
Min(1)
Typ(2)
Max(1)
25
Units
ΔVO
LP8340-ADJ, ADJ=OUT
IOUT = 1mA to 1.0A, VIN = 3.2V
6
8
LP8340-1.8
IOUT = 1mA to 1.0A, VIN = 3.4V
30
LP8340-2.5
IOUT = 1mA to 1.0A, VIN = 3.5V
mV
15
20
50
LP8340-3.3
IOUT = 1mA to 1.0A, VIN = 4.3V
75
LP8340-5.0
IOUT = 1mA to 1.0A, VIN = 6V
VOUT + 0.5V ≤VIN ≤10V, IOUT = 25mA(3)
25
4
100
15
ΔVO
Line Regulation
mV
V
IN − VO Dropout Voltage(3)(4)
LP8340-1.8
IOUT = 800mA
680
550
670
420
540
330
1400
1000
1300
800
LP8340-2.5
IOUT = 800mA
LP8340-2.5
IOUT = 1.0A
LP8340-3.3
LP8340-ADJ, VOUT = 3.3V, IOUT = 800mA
mV
LP8340-3.3
LP8340-ADJ, IOUT = 1.0A
1000
650
LP8340-5.0
IOUT = 800mA
LP8340-5.0
IOUT = 1.0A
420
19
800
50
IQ
Quiescent Current
V
V
V
V
IN ≤10V
μA
μA
Minimum Load Current
Foldback Current Limit
IN − VOUT ≤4V
IN − VOUT >5V
IN − VOUT <4V
100
ILIMIT
450
1600
55
mA
dB
Ripple Rejection Ratio
VIN (dc) = VOUT + 2V
48
VIN (ac) = 1 VP-P @ 120Hz
TSD
Thermal Shutdown Temp.
Thermal Shutdown Hyst.
160
10
°C
nA
ADJ Input Leakage Current VADJ = 1.5V or 0V
±0.01
±100
VOUT Leakage Current
LP8340-ADJ
ADJ = OUT, VOUT = 2V, VIN = 10V
10
10
10
10
10
LP8340-1.8, VOUT = 2.5V, VIN = 10V
LP8340-2.5, VOUT = 3.5V, VIN = 10V
LP8340-3.3, VOUT = 4V, VIN = 10V
LP8340-5.0, VOUT = 6V, VIN = 10V
10Hz to 10kHz, RL = 1kΩ, COUT = 10μF
μA
en
Output Noise
250
μVrms
(3) Condition does not apply to input voltages below 2.7V since this is the minimum input operating voltage.
(4) Dropout voltage is measured by reducing VIN until VO drops 100mV from its normal value.
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LP8340I Electrical Characteristics
Unless otherwise specified all limits ensured for VIN = VO+ 1V, CIN = COUT = 10μF, TJ = 25°C. Boldface limits apply over the
full operating temperature range of TJ = −40°C to 125°C
Symbol
VIN
Parameter
Input Voltage
Conditions
Min(1)
Typ(2)
Max(1)
Units
LP8340-ADJ,1.8, 2.5
LP8340-3.3, 5.0
2.7
10
10
V
VOUT
Output Voltage
LP8340-ADJ, ADJ = OUT
IOUT = 10mA, VIN = 2.7V, TJ = 25°C
100μA ≤IOUT≤ 800mA, 3.0V ≤VIN≤VOUT +4V
800mA <IOUT ≤1.0A, 3.2V ≤VIN ≤VOUT +4V
1.231
1.213
1.213
1.269
1.288
1.288
1.250
1.800
V
V
LP8340-1.8
IOUT = 10mA, VIN = 2.8V, TJ = 25°C
100μA ≤IOUT ≤800mA, 3.2V ≤VIN≤6V
800mA <IOUT ≤1.0A, 3.4V ≤VIN ≤6V
1.773
1.746
1.746
1.827
1.854
1.854
LP8340-2.5
IOUT = 10mA, VIN = 3.8V, TJ = 25°C
100μA ≤IOUT ≤1.0A, 3.8V ≤VIN ≤6.5V
2.463
2.425
2.500
3.300
5.000
2.538
2.575
V
V
V
LP8340-3.3
IOUT = 10mA, VIN = 4.3V TJ = 25°C
100μA ≤IOUT ≤1.0A, 4.3V ≤VIN ≤7.5V
3.250
3.201
3.350
3.399
LP8340-5.0
IOUT = 10mA, VIN = 6V, TJ = 25°C
100μA ≤IOUT ≤1.0A, 6V ≤VIN ≤9V
4.925
4.850
5.075
5.150
ΔVO
Load Regulation
LP8340-ADJ, ADJ=OUT
IOUT = 1mA to 1.0A, VIN = 3.2V
6
8
25
30
50
75
LP8340-1.8
IOUT = 1mA to 1.0A, VIN = 3.4V
LP8340-2.5
IOUT = 1mA to 1.0A, VIN = 3.5V
mV
mV
15
20
LP8340-3.3
IOUT = 1mA to 1.0A, VIN = 4.3V
LP8340-5.0
IOUT = 1mA to 1.0A, VIN = 6V
VOUT + 0.5V ≤VIN ≤10V, IOUT = 25mA(3)
25
4
100
15
ΔVO
Line Regulation
V
IN − VO Dropout Voltage(3)(4)
LP8340-1.8
IOUT = 800mA
680
550
670
420
540
330
1400
1000
1300
800
LP8340-2.5
IOUT = 800mA
LP8340-2.5
IOUT = 1.0A
LP8340-3.3
LP8340-ADJ, VOUT = 3.3V, IOUT = 800mA
mV
LP8340-3.3
LP8340-ADJ, IOUT = 1.0A
1000
650
LP8340-5.0
IOUT = 800mA
LP8340-5.0
IOUT = 1.0A
420
19
800
50
IQ
Quiescent Current
V
V
V
V
IN ≤10V
μA
μA
Minimum Load Current
Foldback Current Limit
IN − VOUT ≤4V
IN − VOUT >5V
IN − VOUT <4V
100
ILIMIT
450
1600
55
mA
dB
Ripple Rejection Ratio
VIN (dc) = VOUT + 2V
48
VIN (ac) = 1 VP-P @ 120Hz
(1) All limits are specified by testing or statistical analysis.
(2) Typical Values represent the most likely parametric norm.
(3) Condition does not apply to input voltages below 2.7V since this is the minimum input operating voltage.
(4) Dropout voltage is measured by reducing VIN until VO drops 100mV from its normal value.
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LP8340I Electrical Characteristics (continued)
Unless otherwise specified all limits ensured for VIN = VO+ 1V, CIN = COUT = 10μF, TJ = 25°C. Boldface limits apply over the
full operating temperature range of TJ = −40°C to 125°C
Symbol
Parameter
Conditions
Min(1)
Typ(2)
Max(1)
Units
TSD
Thermal Shutdown Temp.
Thermal Shutdown Hyst.
160
10
°C
ADJ Input Leakage Current VADJ = 1.5V or 0V
±0.01
±100
nA
VOUT Leakage Current
LP8340-ADJ
ADJ = OUT, VOUT = 2V, VIN = 10V
LP8340-1.8, VOUT = 2.5V, VIN = 10V
LP8340-2.5, VOUT = 3.5V, VIN = 10V
LP8340-3.3, VOUT = 4V, VIN = 10V
LP8340-5.0, VOUT = 6V, VIN = 10V
10Hz to 10kHz, RL = 1kΩ, COUT = 10μF
10
10
10
10
10
μA
en
Output Noise
250
μVrms
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Typical Performance Characteristics
Unless otherwise specified, VIN = VO + 1.5V, CIN = COUT = 10μF X7R ceramic, TJ = 25°C
Output Voltage Change vs. Temperature
1.50
Dropout Voltage vs. Load Current
800
700
600
1.00
0.50
3.3V
500
400
300
2.5V
0.00
-0.50
-1.00
-1.50
200
5.0V
100
0
25
75
100
125
0
0
400
600
800
1000
200
50
LOAD CURRENT (mA)
TEMPERATURE (°C)
Figure 6.
Figure 7.
Ground Current vs. Temperature (ILOAD = 1A)
Ground Current vs. Load Current
20
19
18
17
16
15
19
18.5
0°C
25°C
18
17.5
17
125°C
0
200
400
600
800
1000
0
25
50
75
100
125
LOAD CURRENT (mA)
TEMPERATURE (°C)
Figure 8.
Figure 9.
Ground Current vs. Input Voltage
Ripple Rejection Ratio vs. Frequency
22
21
20
19
18
60
50
40
30
20
10
0
17
16
1k
2.5
5
7.5
10
12.5
10
100
10k
100k
INPUT VOLTAGE (V)
FREQUENCY (Hz)
Figure 10.
Figure 11.
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Typical Performance Characteristics (continued)
Unless otherwise specified, VIN = VO + 1.5V, CIN = COUT = 10μF X7R ceramic, TJ = 25°C
LP8340-1.8V Min VIN
LP8340-ADJ Min VIN
3.6
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
3.4
3.2
125°C
125°C
25°C
0°C
3.0
2.8
25°C
2.6
2.4
0°C
900 1000
500
600
700
800
(mA)
900
1000
500
600
700
800
(mA)
I
LOAD
I
LOAD
Figure 12.
Figure 13.
Line Transient Response (ILOAD = 10mA)
Load Transient Response
V
OUT
(100mV/DIV)
V
(100mV/DIV)
OUT
I
(10mA to 1.0A)
OUT
V
IN
(4.0V to 5.0V)
200µs/DIV
200µs/DIV
Figure 14.
Figure 15.
Start-up Response
Minimum Input Voltage Rise Time
10
1
C
= 1µF
OUT
V
OUT
(2V/DIV)
C
OUT
= 4.3µF
C
= 10µF
OUT
0.1
V
V
= 10V
IN
OUT
= 1µF
V
(0 to 5.0V)
IN
= 1.25V
C
IN
OVERSHOOT < 5%
10
100
0.01
1
50µs/DIV
0.1
I
(mA)
LOAD
Figure 16.
Figure 17.
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Typical Performance Characteristics (continued)
Unless otherwise specified, VIN = VO + 1.5V, CIN = COUT = 10μF X7R ceramic, TJ = 25°C
Minimum Input Voltage Rise Time
Minimum Input Voltage Rise Time
10
10
V
V
= 10V
IN
OUT
= 1µF
C
OUT
= 1µF
= 2.5V
C
IN
OVERSHOOT < 5%
C
OUT
= 1µF
C
OUT
= 4.3µF
1
1
C
OUT
= 10µF
C
= 10µF
OUT
0.1
0.01
0.1
0.01
V
V
= 10V
IN
OUT
= 1µF
C
OUT
= 4.3µF
= 1.8V
C
IN
OVERSHOOT < 5%
1
10
0.1
100
1
10
0.1
100
I (mA)
LOAD
I
(mA)
LOAD
Figure 18.
Figure 19.
Minimum Input Voltage Rise Time
Minimum Input Voltage Rise Time
10
1
10
1
V
V
= 10V
V
V
= 10V
IN
OUT
= 1µF
IN
= 3.3V
= 5V
OUT
C
C
IN
= 1µF
IN
OVERSHOOT < 5%
C
OUT
= 1µF
OVERSHOOT < 5%
C
OUT
= 1µF
C
= 10µF
OUT
C
OUT
= 10µF
C
OUT
= 4.3µF
0.1
0.1
C
OUT
= 4.3µF
0.01
0.01
1
10
1
10
0.1
100
0.1
100
I
(mA)
I
(mA)
LOAD
LOAD
Figure 20.
Figure 21.
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APPLICATIONS SECTION
GENERAL INFORMATION
The LP8340 is a low-dropout, low quiescent current linear regulator. As shown in Figure 22 it consists of a 1.25V
reference, error amplifier, MOSFET driver, PMOS pass transistor and for the fixed output versions, an internal
feedback network (R1/R2). In addition, the device is protected from overload by a thermal shutdown circuit and a
foldback current limit circuit
The 1.25V reference is connected to the inverting input of the error amplifier. Regulation of the output voltage is
achieved by means of negative feedback to the non-inverting input of the error amplifier. Feedback resistors R1
and R2 are either internal or external to the device, depending on whether it is a fixed voltage version or the
adjustable version. The negative feedback and high open loop gain of the error amplifier cause the two inputs of
the error amp to be virtually equal in voltage. If the output voltage changes due to load changes, the error
amplifier and MOSFET driver provide the appropriate drive to the pass transistor to maintain the error amplifier’s
inputs as virtually equal.
V
IN
P
-
MOSFET
DRIVER
ERROR
AMP
P
+
FOLDBACK CURRENT
LIMIT
V
OUT
DPAK Only
V
OUT
SENSE
R
1
Fixed V
OUT
R
2
1.25V
REFERENCE
THERMAL SHUTDOWN
Adjustable
Version
GND
ADJ
Figure 22. LP8340 Functional Block Diagram
EXTERNAL CAPACITOR
An Input capacitor of 1μF or greater is required between the LP8340 VIN pin and ground. While 1μF will provide
adequate bypassing of the VIN supply larger values of input capacitor (i.e. 10μF) can provide improved bypassing
of power supply noise.
Stable operation can be achieved with an output capacitor of 1μF or greater, either ceramic X7R dielectric or
aluminum/tantalum electrolytic. While the minimum capacitor value is 1μF, the typical output capacitor values
selected range from 1μF to 10μF. The larger values provide improved load-transient response, power supply
rejection and stability.
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OUTPUT VOLTAGE SETTING (ADJ VERSION ONLY)
The output voltage is set according to the amount of negative feedback (Note that the pass transistor inverts the
feedback signal). This feedback is determined by R1 and R2 with the resulting output voltage represented by the
following equation:
R
1
1
V
=
V
O
+
REF
R
2
(1)
Use the following equation to determine the values of R1 and R2 for a desired VOUT (R2 = 100kΩ is
recommended).
V
O
1
R
=
2
-
R
1
1.25V
(2)
MINIMUM LOAD CURRENT
A minimum load of 100μA is required for regulation and stability over the entire operating temperature range. If
actual load current fall below 100μA it is recommended that a resistor of value RL = VO/100μA be placed
between VO and ground.
START UP CONSIDERATIONS
Under certain operating conditions, overshoot of VOUT at start-up can occur. The observed overshoot is a
function of rise time of VIN waveform, COUT, start-up load current, and VIN−VOUT differential. The relationship
between these conditions is shown in the Typical Performance Characteristics curves (Minimum Input Voltage
Rise Time). VIN rise times above the curve result in <5% overshoot.
Customers are encouraged to check the suitability of LP8340 in their specific application.
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: LP8340
LP8340
SNVS221D –FEBRUARY 2003–REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
12
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Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LP8340
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
4500
4500
(1)
(2)
(6)
(3)
(4/5)
LP8340ILDX-ADJ
NRND
ACTIVE
WSON
WSON
NGD
6
6
TBD
Call TI
CU SN
Call TI
0 to 125
0 to 125
L078B
L078B
LP8340ILDX-ADJ/NOPB
NGD
Green (RoHS
& no Sb/Br)
Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP8340ILDX-ADJ
WSON
NGD
NGD
6
6
4500
4500
330.0
330.0
12.4
12.4
3.6
3.6
3.2
3.2
1.0
1.0
8.0
8.0
12.0
12.0
Q1
Q1
LP8340ILDX-ADJ/NOPB WSON
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP8340ILDX-ADJ
WSON
WSON
NGD
NGD
6
6
4500
4500
367.0
367.0
367.0
367.0
35.0
35.0
LP8340ILDX-ADJ/NOPB
Pack Materials-Page 2
MECHANICAL DATA
NGD0006A
www.ti.com
IMPORTANT NOTICE
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
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