LP8501TMX/NOPB_技术文档

LP8501

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SNVS548D –SEPTEMBER 2008–REVISED AUGUST 2013

LP8501 Multi-Purpose 9-Output LED Driver

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1

FEATURES

DESCRIPTION

The LP8501 is an LED driver with 9 outputs,

designed to produce versatile lighting effects for

mobile devices. The device is equipped with an

internal program memory, which allows operation

without processor control. Internal program memory

is used by three independent program execution

engines to produce user-defined lighting effects for

the outputs.

2

•

Three Independent Program Execution

Engines for User-defined Programs with Large

SRAM Memory for Storing Lighting Programs

•

9 Programmable Source (High Side) Driver

Outputs with 25.5 mA Full-Scale Current, 8-bit

Current Setting Resolution and 12-Bit PWM

Control Resolution

•

Flexible Grouping Possibility for All 9 Outputs

Including GPO into Three Groups with Group

PWM and Fade-In/ Fade-Out Controls

A high-efficiency charge pump enables LED driving

over full Li-Ion battery voltage range. The excellent

efficiency over a wide operating range is achieved by

autonomously selecting the best charge pump gain

based on LED forward voltage requirements. The

LP8501 is able to automatically enter power-save

mode when LED outputs are not active, thus lowering

idle current consumption down to 10 µA (typ.)

•

Built-in LED Test

Adaptive Charge Pump with 1x and 1.5x Gain

Provides up to 95% LED Drive Efficiency, with

Soft Start and Overcurrent/Short Circuit

Protection

C

1

C

2

•

Automatic Power Save Mode; I_VDD= 10 µA

(typ.)

0.47 PF

C

OUT

1 PF

C2+ C2-

C1+ C1-

VDD

VOUT

•

Two Wire, I²C-Compatible, Control Interface

V

= 2.7V TO 5.5V

IN

R

G

Small Application Circuit

C

IN

D7

D1

D2

1 PF

Pin-configured LED Powering for LEDs 1 to 6

and for LEDs 7 to 9

Solution Area <18 mm²

V

OUT

B

VDD1_6

VDD7_9

•

R

G

D8

D3

D4

GPO

INT

APPLICATIONS

LP8501

B

•

Fun Lights and Indicator Lights

SCL

SDA

EN

LED Backlighting and Color Keypad Lighting

Programmable Current Source

MCU

R

G

D9

D5

D6

CLK

Haptic Feedback Driver and GPIO Expander

TRIG

GND

B

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LP8501

SNVS548D –SEPTEMBER 2008–REVISED AUGUST 2013

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DESCRIPTION (CONTINUED)

The device has a flexible General Purpose Output (GPO) (which can be used, for example, as a digital control

pin for other devices), an INT pin (interrupt function), which can be used to notify the processor, and a Trigger

input interface, which allows program execution start without I²C write.

The device requires only four small and low-cost ceramic capacitors. The LP8501 is available in a tiny 25-bump

2.26 mm x 2.26 mm x 0.60 mm DSBGA package (0.4 mm pitch).

Typical Application Circuits

C

1

C

2

0.47 PF

C

OUT

1 PF

C2+

C1+

C2-

C1-

VOUT

V

IN

= 2.7V TO 5.5V

VDD

C

IN

1 PF

D1

D2

D3

V

OUT

Main Display

VDD1_6

VDD7_9

D4

GPO

INT

LP8501

D5

D6

Sub Display

SCL

SDA

EN

MCU

D7

D8

D9

CLK

RGB or KeyLEDs

TRIG

GND

2

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C

1

C

2

0.47 PF

C

OUT

1 PF

C2+

C1+

C2-

C1-

VOUT

V

IN

= 2.7V TO 5.5V

VDD

C

IN

1 PF

D1

D2

V

OUT

VDD1_6

VDD7_9

D3

D4

Main Display

GPO

INT

LP8501

D5

D6

SCL

SDA

EN

MCU

D7

CLK

RGB or KeyLEDs

D8

D9

TRIG

GND

C

1

C

2

0.47 PF

C

OUT

1 PF

C2+

C1+

C2-

C1-

VOUT

V

IN

= 2.7V TO 5.5V

VDD

C

IN

1 PF

D1

D2

V

OUT

Main Display

VDD1_6

VDD7_9

D3

D4

GPO

INT

LP8501

D5

D6

SCL

SDA

EN

RGB LEDs,

KeyLEDs,

Indicators

MCU

D7

D8

D9

CLK

TRIG

GND

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C

1

C

2

0.47 PF

C

OUT

1 PF

C2+

C1+

C2-

C1-

VOUT

V

IN

= 2.7V TO 5.5V

VDD

C

IN

1 PF

D1

D2

V

OUT

VDD1_6

VDD7_9

D3

D4

GPO

INT

Main Display

LP8501

D5

D6

SCL

SDA

EN

MCU

D7

CLK

D8

D9

TRIG

GND

Connection Diagrams

Thin DSBGA 25-bump package, 2.26 x 2.26 x 0.60 mm body size, 0.4 mm pitch, Package Number YFQ0025

5

4

3

2

5

4

3

2

1

C

A

E

D

B

A

B

C

D

E

Figure 1. Top View

Figure 2. Bottom View

4

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SNVS548D –SEPTEMBER 2008–REVISED AUGUST 2013

PIN DESCRIPTIONS⁽¹⁾

A1

A2

A3

A4

A5

B1

B2

B3

B4

B5

C1

C2

C3

C4

C5

D1

D2

D3

D4

D5

E1

E2

E3

E4

E5

Name

D1

Type

Description

A

Current source output 1

Current source output 2

Charge pump output

D2

A

VOUT

C2-

A

Flying capacitor 2 negative terminal

C2+

D3

A

Flying capacitor 2 positive terminal

Current source output 3

A

D4

A

Current source output 4

VDD1_6

C1-

P

Power for D1 to D6 drivers

Flying capacitor 1 negative terminal

Flying capacitor 1 positive terminal

Current source output 5

A

C1+

D5

A

D6

A

Current source output 6

VDD7_9

EN

P

Power for D7 to D9 drivers

Enable

I

VDD

D7

P

Input power supply

A

Current source output 7.

D8

A

Current source output 8.

INT

OD/O

Interrupt for microcontroller unit. Leave unconnected if not used

32 kHz clock input; connect to ground if not used.

Ground

CLK

GND

D9

I

G

A

Current source output 9.

GPO

TRIG

SDA

SCL

O

General purpose output. Leave unconnected if not used.

Trigger; connect to ground if not used.

Serial interface data

I/OD

I

Serial interface clock

(1) A: Analog Pin, G: Ground Pin, P: Power Pin, I: Input Pin, I/O Input/Output Pin, O: Output Pin, OD: Open Drain Pin

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

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SNVS548D –SEPTEMBER 2008–REVISED AUGUST 2013

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ABSOLUTE MAXIMUM RATINGS^(1)(2)(3)

VDD

−0.3V to +6.0V

−0.3V to + 6.0V

Voltage on D1 to D9, C1−, C1+, C2−, C2+,

VOUT

Voltage on Logic Pins (Input or Output Pins)

−0.3V to V_DD+0.3V

with 6.0V max

Continuous Power Dissipation⁽⁴⁾

Internally Limited

125°C

Junction Temperature (T_J-MAX

)

Storage Temperature Range

−65°C to +150°C

See⁽⁵⁾

Maximum Lead Temperature (Soldering)

ESD Rating

Human Body Model: D1 to D9

Human Body Model: All Other Pins

Machine Model: All Pins

4 kV⁽⁶⁾

2.5 kV⁽⁶⁾

250V⁽⁷⁾

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of

device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or

other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating

Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.

(2) All voltages are with respect to the potential at the GND pins.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(4) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J= 150°C (typ.) and

disengages at T_J= 130°C (typ.).

(5) For detailed soldering specifications and information, please refer to Texas Instruments Application Note AN1112 : DSBGA Wafer Level

Chip Scale Package.

(6) Human Body Model, applicable standard JESD22-A114C

(7) Machine Model, applicable standard JESD22-A115-A

OPERATING RATINGS⁽¹⁾⁽²⁾

V_DDInput Voltage Range

2.7V to 5.5V

0 to V_DD

Voltage on Logic Pins (Input or Output Pins)

Recommended Charge Pump Load Current

Junction Temperature (T_J) Range

Ambient Temperature (T_A) Range⁽³⁾

0 mA to 100 mA

−30°C to +125°C

−30°C to +85°C

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of

device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or

other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating

Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.

(2) All voltages are with respect to the potential at the GND pins.

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP

=

125°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the

part/package in the application (θ_JA), as given by the following equation: T_A-MAX= T_J-MAX-OP– (θ_JA× P_D-MAX).

THERMAL PROPERTIES

(1)

Junction-to-Ambient Thermal Resistance (θ_JA

)

,

Thermal Package

87°C/W

YFQ0025 Package⁽²⁾

(1) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J= 150°C (typ.) and

disengages at T_J= 130°C (typ.).

(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

6

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SNVS548D –SEPTEMBER 2008–REVISED AUGUST 2013

ELECTRICAL CHARACTERISTICS^(1)(2)(3)

Limits in standard typeface are for T_A= 25°C. Limits in boldface type apply over the operating ambient temperature range

(−30°C < T_A< +85°C). Unless otherwise noted, specifications apply to the LP8501 Block Diagram with: V_DD= 3.6V, V_EN

=

1.65V, C_OUT= 1 µF, C_IN= 1 µF, C_1–2= 0.47 µF.⁽⁴⁾

Symbol

Parameter

Condition

Min

Typ

Max

1

Units

VEN = 0V, CHIP_EN=0 (bit),

external 32 kHz clock running or

not running

0.2

µA

Standby supply current

CHIP_EN=0 (bit), external 32 kHz

clock not running

0.7

1.4

µA

CHIP_EN=0 (bit), external 32 kHz

clock running

External 32 kHz clock running,

charge pump and current source

outputs disabled

0.6

0.8

1.8

mA

I_VDD

Charge pump in 1x mode, no

Normal Mode Supply Current load, current source outputs

disabled

Charge pump in 1.5x mode, no

load, current source outputs

disabled

External 32 kHz clock running

Internal oscillator running

11

µA

Power Save Mode Supply

Current

0.6

mA

Internal Oscillator Frequency

Accuracy

−4

−7

+4

+7

f_OSC

%

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Conditions except as otherwise modified

or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured.

(2) All voltages are with respect to the potential at the GND pins.

(3) Min and Max limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most

likely norm.

(4) Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

CHARGE PUMP ELECTRICAL CHARACTERISTICS

Symbol

Parameter

Charge Pump Output Resistance

Switching Frequency

Condition

Min

Typ

Max

Units

Ω

Gain = 1.5x

Gain = 1x

3.5

1

R_OUT

f_SW

I_GND

t_ON

1.25

MHz

mA

µs

Gain = 1.5x

Gain = 1x

1.2

0.3

Ground Current

V_OUTTurn-On Time⁽¹⁾

V_DD= 3.6V, I_OUT= 60 mA

100

(1) Turn-on time is measured from the moment the charge pump is activated until the V_OUTcrosses 90% of its target value.

LED DRIVER ELECTRICAL CHARACTERISTICS

Symbol

I_LEAKAGE

I_MAX

Parameter

Condition

Min

Typ

0.1

Max

Units

µA

Leakage Current (outputs D1 to D9)

Maximum Source Current

1

Outputs D1 to D9

25.5

mA

−4

−5

+4

+5

I_OUT

Output Current Accuracy⁽¹⁾

Output current set to 17.5 mA

%

I_MATCH

f_LED

Matching⁽¹⁾

1

%

Hz

mV

LED Switching Frequency

Saturation Voltage⁽²⁾

312

60

V_SAT

Output current set to 17.5 mA

100

(1) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current.

Matching is the maximum difference from the average. For the constant current outputs on the part (D1 to D9), the following are

determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG).

Two matching numbers are calculated: (MAX-AVG)/AVG and (AVG-MIN)/AVG. The largest number of the two (worst case) is

considered the matching figure. The typical specification provided is the most likely norm of the matching figure for all parts. Note that

some manufacturers have different definitions in use.

(2) Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at V_OUT– 1V.

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LED TEST ELECTRICAL CHARACTERISTICS

Symbol

Parameter

Condition

Min

Typ

30

Max

±4

5

Units

mV

LSB

ms

LSB

Least Significant Bit

Total Unadjusted Error⁽¹⁾

Conversion Time

DC Voltage Range

E_ABS

V_{IN_TEST}= 0V to V_DD

<±3

2.7

t_CONV

V_{IN_TEST}

0

V

(1) Total unadjusted error includes offset, full-scale and linearity errors.

LOGIC INTERFACE CHARACTERISTICS

V_EN= 1.65 to V_DDunless otherwise noted.

Symbol

Parameter

Condition

Min

Typ

Max

0.5

Units

Logic input EN

V_IL

Input Low Level

V

V_IH

I_I

Input High Level

Input Current

Input Delay⁽¹⁾

1.2

–1.0

1.0

µA

µs

t_DELAY

2

Logic input SCL, SDA, TRIG, CLK

V_IL

V_IH

I_I

Input Low Level

Input High Level

Input Current

0.2xV_EN

1.0

V

0.8xV_EN

-1.0

µA

Logic output SDA, TRIG, INT

V_OL

I_L

Output Low Level

I_OUT= 3 mA (pullup current)

V_OUT= 2.8V

0.3

0.5

1.0

V

Output Leakage Current

µA

Logic output GPO

V_OL

V_OH

I_L

Output Low Level

I_OUT= 3 mA

I_OUT= -2 mA

V_OUT= 2.8V

0.3

0.5

1.0

V

Output High Level

V_DD−0.5

V

_DD−0.3

Output Leakage Current

µA

(1) The I²C host should allow at least 500 µs before sending data to the LP8501 after the rising edge of the EN pin.

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(1) (2)

RECOMMENDED EXTERNAL CLOCK SOURCE CONDITIONS

Symbol

Parameter

Condition

Min

Typ

Max

Units

Logic input CLK

ƒ_CLK

t_CLKH

t_CLKL

t_r

Clock Frequency

High Time

32.7

kHz

µs

6

Low Time

µs

Clock Rise Time

Clock Fall Time

10% to 90%

90% to 10 %

2

µs

t_ƒ

µs

(1) Specified by design. V_EN= 1.65V to V_DD

.

(2) The ideal external clock signal for the LP8501 is a 0V to V_EN, 25% to 75% duty-cycle square wave. At frequencies above 32.7 kHz,

program execution will be faster and at frequencies below 32.7 kHz program execution will be slower.

SERIAL BUS TIMING PARAMETERS (SDA, SCL)⁽¹⁾

Limit

Symbol

Parameter

Units

Min

Max

ƒ_SCL

1

Clock Frequency

400

kHz

µs

ns

µs

Hold Time (repeated) START Condition

Clock Low Time

0.6

1.3

2

3

Clock High Time

600

4

Setup Time for a Repeated START Condition

Data Hold Time

600

5

50

6

Data Setup Time

100

7

Rise Time of SDA and SCL

Fall Time of SDA and SCL

20+0.1 C_b

15+0.1 C_b

600

300

8

9

Set-up Time for STOP condition

Bus Free Time between a STOP and a START Condition

10

1.3

Capacitive Load Parameter for Each Bus Line

Load of One Picofarad Corresponds to One Nanosecond

C_b

10

200

ns

(1) Specified by design. V_EN= 1.65V to V_DD

.

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TYPICAL PERFORMANCE CHARACTERISTICS

LED Current vs. Current Register Code

26.0

LED Current vs. Supply Voltage

18.0

17.9

17.8

17.7

17.6

17.5

17.4

17.3

17.2

17.1

17.0

20.8

15.6

10.4

5.2

0.0

2.5

3.1

3.7

4.3

4.9

5.5

0

51

102

153

204

255

V

DD

CURRENT CODE (DEC)

Figure 3.

Figure 4.

LED Drive Efficiency vs. Input Voltage Automatic Gain

Change

Charge Pump Efficiency vs. Load Current 1.5x Mode

100

0.92

V

= 3.6V

LED

V

= 3.0V

DD

90

0.89

0.86

0.83

0.81

0.78

0.75

V

= 2.7V

DD

80

70

60

V

DD

= 3.3V

V

= 3.3V

LED

50

40

30

V

= 3V

LED

V

DD

= 3.6V

I

= 45 mA

OUT

0.01

0.04

0.07

0.09

0.12

0.15

2.6

3.1

3.6

4.0

4.5

5.0

LOAD CURRENT (A)

V

DD

Figure 5.

Figure 6.

Charge Pump Efficiency vs. Input Voltage 1.5x Mode

100

Charge Pump Output Voltage 1.5x Mode vs. Load Current

4.50

I

= 30 mA

OUT

V

= 3.6V

V

DD

4.24

3.98

3.72

= 3.3V

DD

I

= 60 mA

OUT

80

V

= 3.0V

DD

I

= 10 mA

OUT

3.46

3.20

V

DD

= 2.7V

60

2.5

3.0

3.5

4.0

(V)

4.5

5.0

0.01

0.04

0.07

0.09

0.12

0.15

V

DD

LOAD CURRENT (A)

Figure 7.

Figure 8.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Charge Pump Automatic Gain Change with Different

Charge Pump Startup in 1x and 1.5x Modes

Hysteresis

4.5

4.6

400 mV

Startup to 1.5x mode

3.7

4.2

300 mV

200 mV

3.9

2.8

Startup to 1x mode

100 mV

3.5

1.8

0.9

3.2

2.9

0.0

2.7

3.0

3.3

3.6

3.9

4.2

TIME (200 Ps/DIV)

V

DD

Figure 9.

Figure 10.

Charge Pump Automatic Gain Change with Different LED

Charge Pump Automatic Gain Change Hysteresis with 400

Forward Voltages

mV Setting

4.5

V

increasing

DD

4.3

4.2

3.8

3.5

3.1

2.8

V

= 3.6V

= 3.3V

LED

4.1

3.8

3.6

3.4

V

decreasing

DD

V

LED

V

I

= 3V

LED

= 45 mA

OUT

(9*5 mA)

3.3

2.7

3.0

3.6

3.9

4.2

2.7

3.0

3.3

3.6

3.9

4.2

V

DD

Figure 11.

Figure 12.

Line Transient and Charge Pump Automatic Gain Change

(1x to 1.5x)

(1.5x to 1x)

with 9 LED Outputs at 1mA 100% PWM

4.6

with 9 LED Outputs at 1mA 100% PWM

VDD

3.6V

2.8V

4.2

3.8

3.5

3.1

2.7

VOUT

4.2V

3.6V

VOUT

VDD

TIME (2 ms/DIV)

Figure 14.

TIME (10 ms/DIV)

Figure 13.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Current Consumption in Power Save Mode with Different

Clocks

Current Consumption with Different Charge Pump Modes

(LED Outputs Off)

(Charge Pump in 1x Mode, LED Outputs Off)

2.00

29

25

21

16

12

8

1.0

0.9

0.8

0.7

0.6

0.5

1.66

Chargepump 1.5x mode

1.32

Internal clock, left scale

Chargepump 1x mode

0.98

0.64

External clock, right scale

4.0 4.5 5.0 5.5

Chargepump off

0.30

2.70

3.0

3.5

3.26

3.82

4.38

4.94

V

DD

V

DD

Figure 15.

Figure 16.

Current Consumption with Different Temperatures

(Charge Pump in 1x Mode, LED Outputs Off)

1.2

85^oC

1.0

-40^oC

25^oC

0.8

0.7

0.5

0.3

2.7

3.3

3.8

4.4

4.9

V

DD

Figure 17.

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SNVS548D –SEPTEMBER 2008–REVISED AUGUST 2013

FUNCTIONAL OVERVIEW

The LP8501 is a fully integrated lighting management unit (LMU) designed for producing lighting effects for

mobile devices. The LP8501 includes all necessary power management, high-side current sources, two-wire

control interface and programmable execution engines. The overall maximum current for each driver is set by an

8-bit register.

The LP8501 controls LED luminance with a pulse width modulation (PWM) scheme with a resolution of 12 bits.

Programming

The LP8501 provides flexibility and programmability for dimming and sequencing control. Each LED can be

controlled directly and independently through the serial bus. LED drivers can also be freely grouped together.

The LED drivers may be grouped into a maximum of three groups. Each of the three groups' PWM can be

controlled through the serial bus.

The LP8501 has three independent program execution engines, so it is possible to form three independently

programmable LED banks. LED drivers can be grouped based on their function so that, for example, the first

bank of drivers can be assigned to the keypad illumination, the second bank to the “fun lights” and the third

group to the indicator LED(s). Each bank can contain 1 to 9 LED driver outputs. Instructions for program

execution engines are stored in the program memory. The total amount of the program memory is 96

instructions, and the user can allocate the memory as required by the engines.

LED Error Detection

The LP8501 has built-in LED error detection. Error detection both detects open and short circuits, and provides

an opportunity to measure the forward voltages of the LEDs. The test is activated by serial interface write, and

the result can be read through the serial interface during the next cycle. This can be used for general purpose

measurements such as checking the supply voltages and charge pump output voltage.

Energy Efficiency

When charge pump automatic mode selection is enabled, the LP8501 monitors the voltage over the drivers

which are powered from the charge pump (V_OUT) so that the device can select the best charge pump gain and

maintain good efficiency over the whole operating voltage range. In RGB LED applications the red LED element

typically has a forward voltage of about 2V. For that reason, the outputs D7, D8 and D9 can be powered by V_DD

since battery voltage is high enough to drive red LEDs over the whole operating range. This allows driving of

three RGB LEDs with good efficiency because the red LEDs don't load the charge pump.

The LP8501 is able to automatically enter power-save mode, when LED outputs are not active, thus lowering idle

current consumption down to 10 µA (typ.). Also, during the "down time" of the PWM cycle (constant current

output status is low), additional power savings can be achieved under certain conditions.

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LP8501 Block Diagram

C

2

1

0.47 PF

C2-

C1+

C1- C2+

VDD

VOUT

C

IN

1.25 MHz

OSC

1 PF

C

OUT

CHARGE PUMP

1X/1.5X

1 PF

VDD1_6

VDD7_9

PWM PATTERN

GENERATOR

PROGRAM

MEMORY

50H TO 6FH;

PWM PATTERN

GENERATOR

96 INSTRUCTIONS

VREF

BIAS

PWM PATTERN

GENERATOR

VDD1_6

12 BIT PWM

PATTERN

CONTROL

CTRL

REG

SERIAL

DATA

D1

D2

SCL

SDA

8 BIT

INT

MAXIMUM

D6

CONTROL

TRIG

CURRENT

CONTROL

D/A

VDD7_9

EN

POR

CLK

D7

D8

D9

GPO

IDAC AND

HIGH SIDE

LED DRIVERS

THERMAL

SHUTDOWN

GND

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Modes of Operation

RESET In the RESET mode all the internal registers are reset to the default values. Reset is entered always if

FFh is written to Reset Register (3Dh) or internal Power-On Reset (POR) is active. POR will activate

during the chip startup or when the supply voltage V_DDfall below 1.5V (typ.). Once V_DDrises above 1.5V

(typ.), POR will deactivate, and the chip will continue to the STANDBY mode. The CHIP_EN control bit is

low after POR by default.

STANDBY: The STANDBY mode is entered if the register bit CHIP_EN or the EN pin is LOW, and Reset is not

active. This is the low-power consumption mode, when all circuit functions are disabled. Registers can be

written in this mode if the EN pin is raised to high state so that control bits will be effective right after the

start up.

STARTUP: When CHIP_EN bit is written high and the EN pin is high, the INTERNAL STARTUP SEQUENCE

powers up all the needed internal blocks (VREF, Bias, Oscillator etc.). Startup delay is 500 μs. If the chip

temperature rises too high, the Thermal Shutdown (TSD) disables the chip operation, and chip waits in

STARTUP mode until no thermal shutdown event is present.

NORMAL: During NORMAL mode the user controls the chip using the Control Registers.

POWER SAVE:In POWER SAVE mode analog blocks are disabled to minimize power consumption. See Power

Saving for further information.

POR

RESET

Write FFh to Reset

Register 3Dh

or

POR=H

STANDBY

EN=H (pin) and

CHIP_EN=H (bit)

EN=L (pin) or

CHIP_EN=L (bit)

INTERNAL

STARTUP

SEQUENCE

TSD = H

TSD = L

NORMAL MODE

Exit power save

Enter power save

POWER SAVE

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Charge Pump Operational Description

Overview

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The LP8501 includes a pre-regulated switched-capacitor charge pump with a programmable voltage

multiplications of 1 and 1.5x. The 1.5x mode combines the principles of a switched-capacitor charge pump and a

linear regulator, generating a regulated 4.5V output from Li-Ion input voltage range. A two-phase non-overlapping

clock generated internally controls the operation of the charge pump. During the charge phase, both flying

capacitors (C1 and C2) are charged from input voltage. In the pump phase that follows, the flying capacitors are

discharged to output. A traditional switched capacitor charge pump operating in this manner will use switches

with very low on-resistance, ideally 0Ω, to generate an output voltage that is 1.5x the input voltage. The LP8501

regulates the output voltage by controlling the resistance of the input-connected pass-transistor switches in the

charge pump.

Output Resistance

At lower input voltages, the charge pump output voltage may degrade due to effective output resistance (R_OUT) of

the charge pump. The expected voltage drop can be calculated by using a simple model for the charge pump

illustrated in Figure 18 below.

R

OUT

,

V

IN

V

OUT

1.5 x V

V

1.5X

REG

Figure 18. Charge Pump Output Resistance Model

The model shows a linear pre-regulation block (REG), a voltage multiplier (1.5x), and an output resistance

(R_OUT). Output resistance models the output voltage drop that is inherent to switched capacitor converters. The

output resistance is 3.5Ω (typ.), and it is a function of switching frequency, input voltage, flying capacitors’

capacitance value, internal resistances of the switches and ESR of the flying capacitors. When the output voltage

is in regulation, the regulator in the model controls the voltage V’ to keep the output voltage equal to 4.5V (typ).

With increased output current, the voltage drop across R_OUTincreases. To prevent a drop in output voltage, the

voltage drop across the regulator is reduced, V’ increases, and V_OUTremains at 4.5V. When the output current

increases to the point that there is zero voltage drop across the regulator, V’ equals the input voltage, and the

output voltage is “on the edge” of regulation. Additional output current causes the output voltage to fall out of

regulation, so that the operation is similar to a basic open-loop 1.5x charge pump. In this mode, output current

results in output voltage drop proportional to the output resistance of the charge pump. The out-of-regulation

output voltage can be approximated by: V_OUT= 1.5 x V_IN– I_OUTx R_OUT

.

Controlling the Charge Pump

The c harge pump is controlled with two CP_MODE bits in CONFIG register (address 36h). When both of the bits

are low, charge pump is disabled and output voltage is pulled down with an internal 300 kΩ (typ.) resistor. The

charge pump can be forced to bypass mode, so that the battery voltage is connected directly to the current

sources; in 1.5x mode output voltage is boosted to 4.5V. In automatic mode, charge pump operation mode is

defined by current source outputs saturation as described in the next section.

LED Forward Voltage Monitoring

When the charge-pump automatic mode selection is enabled, voltages over LED drivers connected to charge

pump are monitored. If the drivers do not have enough headroom, the charge pump gain is set to 1.5x. Driver

saturation monitor does not have a fixed voltage limit, since saturation voltage is a function of temperature and

current. Charge pump gain is set to 1x when battery voltage is high enough to supply all LEDs. Note that in order

to get the automatic gain change work correctly, power config bits in register 05H must be set according to where

the VDD1_6 and VDD7_9 are connected.

In automatic gain change mode, the charge pump is switched to bypass mode (1x) when LEDs are inactive for

over 50 ms.

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Gain Change Hysteresis

Charge pump gain control utilizes digital filtering to prevent supply voltage disturbances (for example, the

transient voltage on the power supply during the GSM burst) from triggering unnecessary gain changes.

Hysteresis is provided to prevent periodic gain changes, which would occur due to LED driver and charge pump

voltage drops in 1x mode. The hysteresis of the gain change can be configured by the user; default setting is

factory programmable. Flexible configuration ensures that hysteresis can be minimized or set to desired level in

each application.

LED Driver Operational Description

Overview

The LP8501 LED drivers are constant current sources. Output current can be programmed with an I²C register

up to 25.5 mA. The overall maximum current is set by 8-bit output current control registers with 100 μA step size.

Each of the 9 LED drivers has a separate output current control register. See table below for current control.

CURRENT bits

00000000

00000001

00000010

...

Output Current

0.0 mA

0.1 mA

0.2 mA

...

17.5 mA default setting

....

10101111

....

11111110

11111111

25.4 mA

25.5 mA

The LED luminance pattern (dimming) is controlled with PWM (pulse width modulation) technique, which has

internal resolution of 12 bits (8-bit control can be seen by user). PWM frequency is 312 Hz. See Figure 19.

12-BIT PWM

PATTERN

CONTROL

0% TO 100 %

PWM FREQUENCY = 312Hz

8-BIT CURRENT

SETTING

0 mA TO 25.5 mA

TIME

Figure 19. LED Pattern and Current Control Principle

For LED dimming a logarithmic or linear scale can be applied — see the figure below (Figure 20). Logarithmic or

linear scheme can be set for both the program execution engine control and direct PWM control. By using a

logarithmic PWM scale, the visual effect looks linear to the human eye.

100

80

60

40

20

0

0,0

6644,0

112288,0

19129,20

225566,0

DIMMING CONTROL (DEC)

Figure 20. Logarithmic vs Linear Dimming

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Powering LEDs

The power for the LEDs is supplied via VDD1_6 (outputs D1 to D6) and VDD7_9 pins (outputs D7 and D9).

Powering LEDs this way allows flexibility since the pins can be connected to the V_DDor to the V_OUT(or to another

application power source, for example, an external DC/DC converter may be used), depending on the

application.

In the case of LEDs which have forward voltages around 2 volts, LEDs can be powered directly from V_DD. If all

the LEDs are powered from V_DDor an external power source and V_OUTis not used the charge pump can be left

unconnected and charge pump capacitors can be left uninstalled. When the forward voltage of the LEDs is

around 3.6V, V_DDmay not be high enough. In this case the LEDs should be powered from the V_OUT

.

Note that the power supply must be correctly defined in the LP8501 register settings (register 05h 'Power

Config').

Controlling the PWM of High-Side LED Drivers

1. Direct PWM Control

–

All LP8501 LED drivers, D1 to D9, can be controlled independently through the two-wire serial I²C

compatible interface. For each high-side driver there is a PWM control register. Direct PWM control is

active by default.

2. Controlling by Program Execution Engines

–

Engine control is used when the user wants to create programmed sequences. Th program execution

engine has higher priority than direct control registers. Therefore, if the user has set a certain value to the

PWM register, it will be automatically overridden when the program execution engine controls the driver.

LED control and program execution engine operation is described later on in this document.

3. Group Fader Control

–

In addition to LED-by-LED PWM register control, the LP8501 is equipped with group fader control, which

allows the user to fade in or fade out multiple LEDs by writing to only one register. This is a useful

function to minimize serial bus traffic between the MCU and the LP8501. The LP8501 has three group

fader registers, so it is possible to form three fader groups.

–

With the LP8501 it is also possible to set fade-in and fade-out times. These times control the time when

ramping up or down the group PWM value. Time can be set with 4-bits according to the following table.

FADE IN/FADE OUT

0000

Time (s)

0.0

0001

0.05

0.1

0010

0011

0.2

0100

0.3

0101

0.4

0110

0.5

0111

0.6

1000

0.7

1001

0.8

1010

0.9

1011

1.0

1100

1.5

1101

2.0

1110

3.0

1111

4.0

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–

When the LP8501 is shut down (through chip_en), the fading off can be achieved. When “fade-to-off” bit

(in register 36h) is set to 1, the group fade times have effect, and the LEDs fade off according to the time

set in the register.

Examples of Controlling LED Drivers

1. Direct PWM Control Example —Start up the device:

–

Supply, e.g., 3.6V to V_DD

Supply, e.g., 1.8V to EN.

Write 40h (0100 0000b) to address 00h (enable LP8501).

.

Wait 500 µs (startup delay).

Check LED powering

–

Suppose LED outputs from 1 to 6 are connected to V_DDand LED outputs 7 to 9 are connected to V_OUT

.

–

Write 01h (0000 0001b) to address 05h (VDD1_6 powered from V_DDand VDD7_9 powered from V_OUT

.

Enable charge pump to AUTO mode and use internal clock

Write 19h (0001 1001b) to address 36h.

Write PWM values:

–

Write 80h (1000 0000b) to address 16h (LED output 1 PWM duty cycle to 50%).

Write C0h (1100 0000b) to address 1Ah (LED output 5 PWM duty cycle to 75%).

Write FFh (1111 1111b) to address 1Eh (LED output 9 PWM duty cycle to 100%).

LED outputs are turned on after PWM values are written. Changes to the PWM value registers are reflected

immediately to the LED brightness. Default LED output current (17.5 mA) is used for LED outputs, if no other

values are written.

2. Controlling by Program Execution Engines Example —Start up device and configure device to SRAM

write mode:

–

Supply e.g. 3.6V to V_DD

Supply e.g. 1.8V to EN.

Generate 32 kHz clock signal to CLK pin.

Write 40h (0100 0000b) to address 00h.

Wait 500 µs (startup delay).

.

Write 14h (0001 0100b) to address 01h (configure engines 1 and 2 to Load mode).

Check LED powering

–

Suppose LED outputs from 1 to 6 are connected to V_OUTand LED outputs 7 to 9 are connected to V_DD

.

–

Write 02h (0000 0010b) to address 05h (VDD1_6 powered from V_OUTand VDD7_9 powered from V_DD

.

Program load to SRAM

–

Write 00h (0000 0000b) to register 4Fh (select memory page 0).

Write 9Dh (1001 1101b) to register 50h (select LED output 1 for engine 1 MSB, instruction part).

Write 01h (0000 0001b) to register 51h (select LED output 1 for engine 1 LSB, output selection part).

Write 40h (0100 0000b) to register 52h (set PWM value to full FFh MSB, instruction part).

Write FFh (1111 1111b) to register 53h (set PWM value to full FFh LSB, PWM value part).

Write 7Eh (0111 1110b) to register 54h (wait for 0.48s (maximum) MSB, instruction part).

Write 00h (0000 0000b) to register 55h (wait for 0.48s LSB).

Write 40h (0100 0000b) to register 56h (set PWM value to zero MSB, instruction part).

Write 00h (0000 0000b) to register 57h (set PWM value to zero LSB, PWM value part).

Write 7Eh (0111 1110b) to register 58h (wait for 0.48s MSB, instruction part).

Write 00h (0000 0000b) to register 59h (wait for 0.48s LSB).

Write A2h (1010 0010b) to register 5Ah (branch instruction with loop count 4 MSB, instruction part).

Write 01h (0000 0001b) to register 5Bh (branch instruction with loop count 4 LSB sets program counter

value to '1', i.e., program continues execution in this case from setting PWM value).

–

Write C0h (1100 0000b) to register 5Ch (end instruction MSB, instruction part).

Write 00h (0000 0000b) to register 5Dh (end instruction LSB).

Write 9Dh (1001 1101b) to register 5Eh (select LED output 3 for engine 2MSB, instruction part).

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–

Write 03h (0000 0011b) to register 5Fh (select LED output 3for engine 2LSB, output selection part).

Write 40h (0100 0000b) to register 60h (set PWM value to full FFh MSB, instruction part).

Write FFh (1111 1111b) to register 61h (set PWM value to full FFh LSB, PWM value part).

Write 7Eh (0111 1110b) to register 62h (wait for 0.48s (maximum) MSB, instruction part).

Write 00h (0000 0000b) to register 63h (wait for 0.48s LSB).

Write 40h (0100 0000b) to register 64h (set PWM value to zero MSB, instruction part).

Write 00h (0000 0000b) to register 65h (set PWM value to zero LSB, PWM value part).

Write 7Eh (0111 1110b) to register 66h (wait for 0.48s MSB, instruction part).

Write 00h (0000 0000b) to register 67h (wait for 0.48s LSB).

Write A2h (1010 0010b) to register 68h (branch instruction with loop count 4 MSB, instruction part).

Write 01h (0000 0001b) to register 69h (branch instruction with loop count 4 LSB sets program counter

value to '1', i.e., program continues execution in this case from setting PWM value).

–

Write C0h (1100 0000b) to register 6Ah (end instruction MSB, instruction part).

Write 00h (0000 0000b) to register 6Bh (end instruction LSB).

Set start address

–

Write 00h (0000 0000b) to register 4Ch (set engine 1 start address to 0).

Write 07h (0000 0111b) to register 4Dh (set engine 2 start address to 7, 7^th16–bit write, 15^thI²C write).

Optional: Write 00h (0000 0000b) to register 37h (set program counter of engine 1 to 0).

Optional: Write 00h (0000 0000b) to register 38h (set program counter of engine 2 to 0).

Enable powersave, set charge pump to auto mode and select external clock:

Write 38h (0011 1000b) to register 36h.

Run program:

–

Write 28h (0010 1000b) to register 01h (set engines 1 and 2 to Run mode).

Write 68h (0110 1000b) to register 00h (set program execution from Hold to Run and keep device

enabled).

LP8501 will now generate five 0.48 second long blinks to LED outputs 1 and 3.

3. Group Fader ControlStart up the device:

–

Supply, e.g., 3.6V to V_DD

Supply, e.g., 1.8V to EN.

Write 40h (0100 0000b) to address 00h (enable the device).

.

Wait 500 µs (startup delay).

Check LED powering

–

Suppose LED outputs from 1 to 9 are connected to V_OUT

Write 03h (0000 0011b) to address 05h (VDD1_6 and VDD7_9 powered from V_OUT

.

Enable charge pump 1.5x mode and use internal clock:

Write 11h (0001 0001b) to register 36h.

Select LED outputs 1, 3 and 7 to Fader Group 1:

–

Write 40h (0100 0000b) to address 06h (LED output 1 to group 1).

Write 40h (0100 0000b) to address 08h (LED output 3 to group 1).

Write 40h (0100 0000b) to address 0Ch (LED output 7 to group 1).

Set group 1 fader times:

Write CFh (1100 1111b) to register 02h (group 1 Fade IN time to 1.5 s and Fade OUT time to 4s).

Set group PWM value:

–

Write FFh (1111 1111b) to register 48h (group 1 PWM duty cycle to 100%, all three LED outputs fades

on in 1.5s)

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LP8501 Engine Programming

The LP8501 has three independent programmable lighting engines. All the lighting engines have their own

program memory block allocated by the user. Note that in order to access program memory the operation mode

needs to be LOAD Program, at least for one of the three lighting engines. Also note that one should not change

from RUN —mode directly to LOAD program. Correct sequence would be RUN (10) –> DISABLED (00) –>

LOAD (01).

Program execution is clocked with 32 768Hz clock. This clock can be generated internally, or an external 32 kHz

clock can be connected to CLK pin. Using external clock enables synchronization of LED timing to this clock

rather than to the internal clock.

The engines have different priorities; thus when more than one engine is controlling the same LED output: the

LED engine 1 has the highest priority, LED engine 2 second highest and LED engine 3 third highest.

Supported instruction set is listed in the tables below:

Table 1. LP8501 LED Driver Instructions

Inst.

Bit [15] Bit

[14]

Bit

[13]

Bit

[12]

Bit

[11]

Bit

[10]

Bit [9] Bit [8] Bit [7] Bit [6] Bit Bit [4] Bit [3] Bit

Bit

[1]

Bit

[0]

[5]

[2]

pres

Ramp

0

cale

Step time

0

Sign

0

# of increments

PWM value

Set PWM

1

0

pres

cale

Wait

0

Time

0

Table 2. LP8501 LED Mapping Instructions

Inst.

Bit Bit

[15 [14]

]

Bit

[13]

Bit

[12]

Bit

[11]

Bit

[10]

Bit [9] Bit [8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] Bit [0]

mux_ld

_start

1

0

1

0

1

0

1

0

SRAM address 0–95

LED select

mux_ld

_end

1

mux_se

l

1

mux_clr

1

0

1

0

1

0

1

0

mux_in

c

mux_de

c

1

0

1

0

1

0

mux_se

t

SRAM address 0–95

Table 3. LP8501 Branch Instructions

Inst.

Bit [15]

Bi t

[14]

Bit

[13]

Bit [12]

Bit

[11]

Bit Bit [9] Bit [8] Bit [7] Bit [6] Bit

Bit Bit [3] Bit

Bit

[1]

Bit

[0]

[10]

[5]

[4]

[2]

Go to

Start

0

Branch

Int

1

0

1

0

1

Loop count

Step number

0

1

0

End

Int

Reset

X

Trigger

Wait for a trigger

ENGI ENGI ENGI

NE3 NE2 NE1

Send a trigger

X

Ext. trig

X

Ext.

trig

X

ENGI ENG ENG

NE3 INE2 INE1

X

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RAMP

This is the instruction useful for smoothly changing from one PWM value into another PWM value on the D1 to

D9 outputs; in other words, generating ramps (with a negative or positive slope). The LP8501 allows

programming of very fast and very slow ramps.

Ramp instruction generates a PWM ramp, using the effective PWM value as a starting value. At each ramp step

the output is incremented/decremented by one unit, unless the step time span is 0 or number of increments is 0.

Time span for one ramp step is defined with prescale (bit [14]) and step time (bits [13:9]). Prescale = 0 sets 0.49

ms cycle time and prescale = 1 sets 15.6 ms cycle time; so the minimum time span for one step is 0.49 ms

(prescale * step time span = 0.49ms x 1) and the maximum time span is 15.6 ms x 31 = 484ms/step. Note: if all

the step time bits [13:9] are set to zero, instruction is treated as Set PWM instruction.

The number of increment define how many steps will be taken during one ramp instruction; maximum increment

value is 255d, which corresponds to incrementing from zero to the maximum value. If PWM reaches

minimum/maximum value (0/255) during the ramp instruction, ramp instruction will be executed to the end

regardless of saturation. This enables ramp instruction to be used as a combined ramp & wait instruction. Note:

Ramp instruction is the wait instruction when the increment bits [7:0] are set to zero.

Setting bit LOG_EN high/low sets logarithmic (1) or linear ramp (0) (bit 5 in registers 06h — 0Eh and in register

15h for GPO). By using the logarithmic ramp setting the visual effect appears like a linear ramp, because the

human eye behaves in a logarithmic way.

Name

prescale

Value (d)

Description

Divides master clock (32 768 Hz) by 16 = 2048 Hz → 0.488 ms cycle time

Divides master clock (32 768 Hz) by 512 = 64 Hz → 15.625 ms cycle time

Increase PWM output

0

1

0

sign

1

Decrease PWM output

step time

1 - 31

0 - 255

One ramp increment done in (step time) x (prescale). Note: 0 means Set PWM instruction

# of increments

The number of increment/decrement cycles Note: Value 0 takes the same time as increment by 1, but

it is the wait instruction.

RAMP INSTRUCTION APPLICATION EXAMPLE

Let's say that the LED dimming is controlled according to the linear scale and effective PWM value at the

moment t=0 is 140d (~55%,), as shown in Figure 21 below, and we want to reach a PWM value of 148d (~58%)

at the moment t = 1.5s. The parameters for the RAMP instruction will be:

•

Prescale = 1 → 15.625 ms cycle time

Step time = 12 → step time span will be 12*15.625 ms = 187.5 ms

Sign = 0 → increase PWM output

# of increments = 8 → take 8 steps

DIMMING

CONTROL

148

147

STEP TIME

SPAN =

146

187.5 ms

145

144

143

142

141

140

RAMP INSTRUCTION

1500

8

TIME ELAPSED (ms)

STEP COUNT

375

0

750

1125

0

1

2

3

4

5

6

7

Figure 21. Example of Ramp Instruction

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SET_PWM

This instruction is used for setting the PWM value on the outputs D1 to D9 without any ramps. Set PWM output

value from 0 to 255 with PWM value bits [7:0]. Instruction execution takes sixteen 32 kHz clock cycles (=488 µs).

Name

Value (d)

Description

PWM value

0 to 255

PWM output duty cycle 0 to 100%

WAIT

When a wait instruction is executed, the engine is set in a wait status, and the PWM values on the outputs are

frozen.

Name

Value (d)

Description

prescale

0

1

Divide master clock (32 768 Hz) by 16 which

means 0.488 ms cycle time

Divide master clock (32 768 Hz) by 512

which means 15.625 ms cycle time

time

1 — 31

Total wait time will be = (time) x (prescale).

Maximum 484 ms, minimum 0.488 ms

LED MAPPING INSTRUCTIONS

These commands define the engine-to-LED mapping. The mapping information is stored in a table, which is

stored in the SRAM (program memory of the LP8501). Mapping information can be located anywhere in SRAM

memory. LP8501 has three lighting engines (Engines) which can be mapped to 9 LED drivers or to one GPO pin.

One engine can control one or multiple LED drivers. There are totally seven commands for the engine-to-LED

driver control: mux_ld_start, mux_ld_end, mux_sel, mux_clr, mux_inc, mux_dec, mux_set. Note: the LED

mapping instructions do not update PWM values to LED outputs. PWM values are updated after ramp or

set_pwm instructions.

MUX_LD_START; MUX_LD_END

Mux_ld_start and mux_ld_ end define the mapping table location in the memory. With mux_ld_start instruction

the mapped row can be activated at the same time by setting map = 1.

Name

Value (d)

Description

map

0

1

Mapped row inactive

Set the mapped row active. MUX_LD_START only

Mapping table start/end address

SRAM address

0 - 95

MUX_SEL

With mux_sel instruction one, and only one, LED driver (or the GPO pin) can be connected to a lighting engine.

Connecting multiple LEDs to one engine is done with the mapping table. After the mapping has been released

from an LED, the PWM register value will still control the LED brightness. If the mapping is released from the

GPO pin, serial bus control takes over the GPO state.

Name

Value (d)

Description

LED select

0 - 16

0 = no drivers selected

1 = LED1 selected

2 = LED2 selected

...

9 = LED9 selected

16 = GPO

MUX _CLR

Mux_clr clears engine-to-driver mapping. After the mapping has been released from an LED, the PWM register

value will still control the LED brightness. If the mapping is released from the GPO pin, serial bus control takes

over the GPO state.

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MUX_INC

A mux_inc instruction sets the next row active in the mapping table each time it is called. For example, if the 2^nd

row is active after a mux_inc instruction is called, the 3^rdrow will be active. If the mapping table end is reached,

activation will roll to the mapping table start address next time when the mux_inc instruction is called. The engine

will not push a new PWM value to the LED driver output before a SET_PWM or RAMP instruction is executed. If

the mapping has been released from an LED, the value in the PWM register will still control the LED brightness.

If the mapping is released from the GPO pin, serial bus control takes over the GPO state.

MUX_DEC

A mux_dec instruction sets the previous row active in the mapping table each time it is called. For example, if the

3^rdrow is active, after mux_dec instruction is called, the 2^ndrow will be active. If the mapping table start address

is reached, activation will roll to the mapping table end address the next time the mux_dec instruction is called.

The engine will not push a new PWM value to the LED driver output before a SET_PWM or RAMP instruction is

executed. If the mapping has been released from an LED, the value in the PWM register will still control the LED

brightness. If the mapping is released from the GPO pin, serial bus control takes over the GPO state.

MUX_SET

Mux_set sets the index pointer to point the mapping table row defined by bits [6:0] and sets the row active. The

engine will not push a new PWM value to the LED driver output before a SET_PWM or RAMP instruction is

executed. If the mapping has been released from an LED, the value in the PWM register will still control the LED

brightness. If the mapping is released from the GPO pin, serial bus control takes over the GPO state.

Name

Value (d)

Description

SRAM address

0 to 95

Any SRAM address containing mapping data

GO-TO-START

A go-to-start command resets the Program Counter register (address 37h 38h or 39h) and continues executing

the program from the I²C register program start address defined in 4Ch-4Eh. Command takes sixteen 32 kHz

clock cycles. Note that default value for all program memory registers is 00h, which is “Go-to-Start” command.

BRANCH

Branch instruction is mainly indented for repeating a portion of the program code several times. Step number

parameter defines how many steps loop start point is relative to the engine Start Address. The loop count

parameter defines how many times the instructions inside the loop are repeated. The LP8501 supports nested

looping, i.e., loop inside loop. The number of nested loops is not limited. Instruction takes sixteen 32 kHz clock

cycles.

Name

Value (d)

Description

loop count

step number

0 to 63

The number of loops to be done. 0 means an infinite loop.

How many steps loop start point is from engine Start Address.

0- to 95

INT

Sends interrupt to processor by pulling the INT pin down and setting the corresponding status bit high. Interrupt

can be cleared by reading interrupt bits in STATUS/INTERRUPT register at address 3Ah. With this instruction

program execution continues.

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END

Ends program execution and resets the PC. Instruction takes sixteen 32 kHz clock cycles. An end instruction can

have two parameters, INT and RESET. These parameters are described in tables below. Execution engine bits

(Register 00h bits [5:0]) are set to zero, i.e., hold mode.

Name

Value

Description

int

0

No interrupt will be sent. PWM registers values will remain intact. Program

counter value is set to 0.

1

Reset program counter value to 0 and send interrupt to processor by pulling

the INT pin down and setting corresponding status bit high to notify that

program has ended. PWM register values will remain intact. Interrupt can

be cleared by reading interrupt bits in STATUS/INTERRUPT register at

address 3Ah

Name

Value

Description

reset

0

Reset program counter value to 0 and hold. PWM register values remain

intact.

1

Reset program counter value to 0 and hold. PWM register values of the

non-mapped drivers will remain. PWM register values of the mapped drivers

will be set to '0000 0000'.

TRIGGER

Wait or send triggers can be used to synchronize operation between the program execution engines. A send

trigger instruction takes sixteen 32 kHz clock cycles and a wait-for trigger takes at least sixteen 32 kHz clock

cycles. The receiving engine stores the triggers which have been sent. Received triggers are cleared by wait for

trigger instruction. Wait for trigger instruction is executed until all the defined triggers have been received (note:

several triggers can be defined in the same instruction).

An external trigger input signal must stay low for at least two 32 kHz clock cycles to be executed. A trigger output

signal is three 32 kHz clock cycles long. An external trigger signal is active low, i.e. when trigger is send/received

the pin is pulled to GND. Sent external trigger is masked, i.e,. the device which has sent the trigger will not

recognize it. If send and wait external triggers are used on the same instruction, the send external trigger is

executed first, then the wait external trigger.

Name

Value (d)

Description

wait for a trigger

0 to 31

Wait for a trigger from the engine(s). Several triggers can be defined in the

same instruction. Bit [7] engages engine 1, bit [8] engages engine 2, bit [9]

engages engine 3 and bit [6] is for external trigger I/O. Bits [4] and [5] are

not in use.

send a trigger

0 to 31

Send a trigger to the engine(s). Several triggers can be defined in the same

instruction. Bit [1] engages engine 1, bit [2] engages engine 2, bit [3]

engages engine 3 and bit [6] is for external trigger I/O. Bits [4] and [5] are

not in use.

Power Saving

Automatic Power Save Mode

Automatic power save mode is enabled when the POWERSAVE_EN bit in register address 36h is ‘1’. Almost all

analog blocks are powered down in power save if an external clock signal is used. Only the charge pump

protection circuits remain active. However, if the internal clock has been selected, only the charge pump and

LED drivers are disabled during the power save; the digital part of the LED controller needs to stay active. In

both cases the charge pump enters the weak 1x mode. In this mode the charge pump utilizes a passive current

limited keep-alive switch, which keeps the output voltage at the battery level. During the program execution

LP8501 can enter power save if there is no PWM activity in any of the LED driver outputs. To prevent short

power save sequences during program execution, LP8501 has an instruction look-ahead filter. During program

execution engine 1, engine 2 and engine 3 instructions are constantly analyzed, and if there are time slots with

no PWM activity on LED driver outputs for 50 ms, the device will enter power save. In power save mode program

execution continues uninterruptedly. When an instruction that requires PWM activity is executed, a fast internal

startup sequence will be started automatically.

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PWM Cycle Power Save Mode

PWM cycle power save mode is enabled when the PWM_POWERSAVE bit in register 36h is set to '1'. In PWM

power save mode analog blocks are powered down during the down time of the PWM cycle. Blocks are powered

down depending upon whether an external or an internal clock is used. While the Automatic Power-Save Mode

saves energy when there is no PWM activity, the PWM Power-Save mode saves energy during PWM cycles.

Like the Automatic Power-Save Mode, PWM Power-Save Mode works also during program execution.

Powersave mode if

brightness = 0

longer than 50 ms

LED brightness

(adjusted with PWM

duty cycle)

POWER

POWERSAVE

SAVE

Time

Chip current consumption

(LED current not included)

Time

Figure 22. The Effect of Power-Save mode during a Lighting Sequence

Powersave mode if

brightness = 0

longer than 50 ms

LED brightness

(adjusted with PWM

duty cycle)

POWER

POWERSAVE

SAVE

Time

Chip current consumption

(LED current not included)

Time

Additional power

savings from PWM

powersave mode

Figure 23. The effect of Powersave and PWM Powersave modes during a lighting sequence

Logic Interface Operational Description

The LP8501 features a flexible logic interface for connecting to processor and peripheral devices.

Communication is done with and I²C-compatible interface; different logic input/output pins makes it possible to,

for example, trigger program execution or enable power saving for the device.

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IO LEVELS

I²C interface, CLK and TRIG pin input levels are defined by the EN pin. Using the EN pin as voltage reference for

logic inputs simplifies PWR routing and eliminates the need for a dedicated V_IOpin. In the following block

diagram EN pin connections are illustrated.

VDD

Input

Buffer

EN

Level

Shifter

SDA

Level

Shifter

SCL

Figure 24. Using EN Pin As Digital IO Voltage Reference

GPO/INT Pins

The LP8501 has one General Purpose Output pin (GPO); the INT pin also can be configured as a GPO pin. The

GPO pin level is defined by V_DDvoltage. It also has its own PWM control register. GPO can be configured into

fader groups, and it can be used in LED engine programming. When INT is configured as GPO, its level is

defined by the V_DD. State of the pins can be controlled with GPO register (3Bh). GPO pins are digital CMOS

outputs, and no pull-up/down resistors are needed.

When the INT pin GPO function is disabled, it operates as an open drain pin. The INT signal is active low, i.e.,

when interrupt signal is sent, the pin is pulled to GND. External pull-up resistor is needed for proper functionality.

Table 4. GPO register (3Bh)

Name

Bit

Description

INT_CONF

2

Enable INT pin GPO function

0 = INT pin functions as a INT pin

1 = INT pin functions as a GPO pin

GPO

1

0

0 = GPO pin state is low

1 = GPO pin state is high

GPO_INT

0 = INT pin state is low (INT_CONF=1)

1 = INT pin state is high (INT_CONF=0)

TRIG Pin

The TRIG pin can function as an external trigger input or output. The external trigger signal is active low if, when

trigger is sent/received, the pin is pulled to GND. TRIG is an open drain pin, and an external pull-up resistor is

needed for trigger line. The external trigger input signal must be at least two 32 kHz clock cycles long to be

recognized. Trigger output signal is three 32 kHz clock cycles long. If TRIG pin is not used on application, it

should be connected to GND to prevent floating of this pin and extra current consumption.

CLK Pin

The CLK pin is used for connecting an external 32 kHz clock to the LP8501. Using an external clock can improve

automatic power-save mode efficiency because the internal clock can be switched off automatically when the

device has entered powersave mode with an external clock present. The device can be used without the external

clock. If an external clock is not used on the application, the CLK pin should be connected to GND to prevent

floating of this pin and extra current consumption.

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I²C-Compatible Control Interface

The I²C compatible synchronous serial interface provides access to the programmable functions and registers on

the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected

to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). Every device

on the bus is assigned a unique address and acts as either a Master or a Slave depending on whether it

generates or receives the serial clock SCL. The SCL and SDA lines should each have a pull-up resistor placed

somewhere on the line and remain HIGH even when the bus is idle. Note: CLK pin is not used for serial bus data

transfer.

Data Validity

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of

the data line can only be changed when clock signal is LOW.

SCL

SDA

data

change

allowed

data

change

allowed

data

valid

data

change

allowed

data

valid

Figure 25. Data Validity Diagram

Start and Stop Conditions

START and STOP conditions classify the beginning and the end of the data transfer session. A START condition

is defined as the SDA signal transitions from HIGH to LOW while SCL line is HIGH. A STOP condition is defined

as the SDA transitions from LOW to HIGH while SCL is HIGH. The bus master always generates START and

STOP conditions. The bus is considered to be busy after a START condition and free after a STOP condition.

During data transmission, the bus master can generate repeated START conditions. First START and repeated

START conditions are equivalent, function-wise.

Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP8501 pulls

down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP8501 generates an

acknowledge after each byte has been received.

There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must

indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked

out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the

master), but the SDA line is not pulled down.

After the START condition, the bus master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a “0” indicates a WRITE and a “1”

indicates a READ. The second byte selects the register to which the data will be written. The third byte contains

data to write to the selected register.

I²C-Compatible Chip Address

LP8501 serial bus address is 32h.

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MSB

ADR6

bit7

ADR5

bit6

ADR4

bit5

ADR3

bit4

ADR2

bit3

ADR1

bit2

ADR0

bit1

R/W

bit0

0

1

0

1

0

2

I C Slave Address (chip address)

Figure 26. LP8501 Chip Address

ack from slave

MSB Data LSB ack stop

ack from slave

start

MSB Chip Addr LSB

w

ack MSB Register Addr LSB ack

SCL

SDA

start

id = 32h

w

ack

addr = 40h

ack

address 40h data

ack stop

Figure 27. Write cycle (w = write; SDA = “0”) id = chip address = 32h for LP8501

ack from slave

ack from slave repeated start

ack from slave data from slave nack from maste

start

MSB Chip Addr LSB

w

MSB Register Addr LSB

rs

MSB Chip Address LSB

r

MSB Data LSB

stop

SCL

SDA

start

id =32h

w

ack

address = 3Fh

ack rs

id = 32h

r

ack

address 3Fh data

nack stop

When a READ function is to be accomplished, a WRITE function must precede the READ function, as show above.

Figure 28. Read cycle (r = read; SDA = "1"), id = chip address = 32h for LP8501

Control Register Write Cycle

•

Master device generates start condition.

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

Slave device sends acknowledge signal if the slave address is correct

Master sends control register address (8 bits).

Slave sends acknowledge signal.

Master sends data byte to be written to the addressed register.

Slave sends acknowledge signal.

If master will send further data bytes, the slave’s control register address will be incremented by one after

acknowledge signal. In order to reduce program load time LP8501 supports address auto increment. Register

address is incremented after each 8 data bits. For example, the whole program memory page can be written

in one serial bus write sequence. Note: serial bus address auto increment is not supported for register

addresses from 16H to 1EH.

•

Write cycle ends when the master creates stop condition.

Control Register Read Cycle

Master device generates a start condition.

•

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•

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

Slave device sends acknowledge signal if the slave address is correct

Master sends control register address (8 bits).

Slave sends acknowledge signal.

Master device generates repeated start condition.

Master sends the slave address (7 bits) and the data direction bit (r/w = 1).

Slave sends acknowledge signal if the slave address is correct.

Slave sends data byte from addressed register.

If the master device sends acknowledge signal, the control register address will be incremented by one. Slave

device sends data byte from addressed register.

•

Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop

condition

Auto Increment Feature

The auto increment feature allows writing several consecutive registers within one transmission. Every time an 8-

bit word is sent to the LP8501, the internal address index counter will be incremented by one and the next

register will be written. The table below shows writing sequence to two consecutive registers. The auto increment

feature is enabled by writing the EN_AUTO_INCR bit high in the MISC register (address 36h). Note that the

serial bus address auto increment is not supported for register addresses from 16h to 1Eh (PWM registers).

MASTER START

CHIP

WRITE

REG

DATA

STOP

ADDR =

32H

ADDR

LP8501

ACK

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LP8501 Registers

The LP8501 is controlled by a set of registers through the two-wire serial interface port. Some register bits are

reserved for future use. The table below lists device registers, their addresses, and their abbreviations. A more

detailed description is given in section.

Table 5. Control Register Map

Hex

Register Name

Bit(s)

Read/Wr Default Value

Bit Mnemonic and Description

Address

ite

After Reset

00

ENABLE / ENGINE

CNTRL1

[6]

R/W

x0xxxxxx

CHIP_EN

0 = LP8501 not enabled

1 = LP8501 enabled

[5:4]

[3:2]

[1:0]

[5:4]

[3:2]

[1:0]

[7:4]

[3:0]

[7:4

[3:0]

[7:4

[3:0]

[1]

R/W

xx00xxxx

xxxx00xx

xxxxxx00

xx00xxxx

xxxx00xx

xxxxxx00

0000xxxx

xxxx0000

0000xxxx

xxxx0000

0000xxxx

xxxx0000

xxxxxx0x

xxxxxxx0

00xxxxxx

xx0xxxxx

00xxxxxx

ENGINE1_EXEC

Engine 1 program execution control

ENGINE2_EXEC

Engine 2 program execution control

ENGINE3_EXEC

Engine 3 program execution control

01

ENGINE CNTRL2

ENGINE1_MODE

ENGINE 1 mode control

ENGINE2_MODE

ENGINE 2 mode control

ENGINE3_MODE

ENGINE 3 mode control

02

03

04

05

06

GROUP 1 FADING

GROUP 2 FADING

GROUP 3 FADING

POWER CONFIG

D1 CONTROL

FADE_IN

Fade-in time for group 1 fader

FADE_OUT

Fade-in time for group 1 fader

FADE_IN

Fade-in time for group 2 fader

FADE_OUT

Fade-in time for group 2 fader

FADE_IN

Fade-in time for group 3 fader

FADE_OUT

Fade-in time for group 3 fader

CHP_CON_1_6

D1 to D6 power selection

[0]

CHP_CON_7_9

D7 to D9 power selection

[7:6]

[5]

GROUP_SELECT

Fader group selection for D1 output

LOG_EN

Logarithmic dimming control for D1

07

08

D2 CONTROL

D3 CONTROL

[7:6]

GROUP_SELECT

Fader group selection for D2 output

[5]

R/W

xx0xxxxx

00xxxxxx

Logarithmic dimming control for D2 output

[7:6]

GROUP_SELECT

Fader group selection for D3 output

[5]

[7:6]

[5]

R/W

xx0xxxxx

00xxxxxx

xx0xxxxx

00xxxxxx

xx0xxxxx

LOG_EN

Logarithmic dimming control for D3 output

09

0A

D4 CONTROL

D5 CONTROL

GROUP_SELECT

Fader group selection for D4 output

LOG_EN

Logarithmic dimming control for D4 output

[7:6]

[5]

GROUP_SELECT

Fader group selection for D5 output

LOG_EN

Logarithmic dimming control for D5 output

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Table 5. Control Register Map (continued)

Hex

Address

Register Name

D6 CONTROL

Bit(s)

[7:6]

[5]

Read/Wr Default Value

Bit Mnemonic and Description

ite

After Reset

0B

0C

0D

0E

R/W

00xxxxxx

GROUP_SELECT

Fader group selection for D6 output

R/W

xx0xxxxx

00xxxxxx

xx0xxxxx

00xxxxxx

xx0xxxxx

00xxxxxx

xx0xxxxx

LOG_EN

Logarithmic dimming control for D6 output

D7 CONTROL

D8 CONTROL

D9 CONTROL

[7:6]

[5]

GROUP_SELECT

Fader group selection for D7 output

LOG_EN

Logarithmic dimming control for D7 output

[7:6]

[5]

GROUP_SELECT

Fader group selection for D8 output

LOG_EN

Logarithmic dimming control for D8 output

[7:6]

[5]

GROUP_SELECT

Fader group selection for D9 output

LOG_EN

Logarithmic dimming control for D9 output

0F TO 14 RESERVED

[7:0]

[7:6]

RESERVED FOR FUTURE USE

15

GPO CONTROL

R/W

00xxxxxx

xx0xxxxx

00000000

GROUP_SELECT

Fader group selection for GPO

[5]

LOG_EN

Logarithmic dimming control for GPO

16

17

18

19

1A

1B

1C

1D

1E

D1 PWM

D2 PWM

D3 PWM

D4 PWM

D5 PWM

D6 PWM

D7 PWM

D8 PWM

D9 PWM

[7:0]

PWM

PWM duty cycle control for D1

PWM

PWM duty cycle control for D2

PWM

PWM duty cycle control for D3

PWM

PWM duty cycle control for D4

PWM

PWM duty cycle control for D5

PWM

PWM duty cycle control for D6

PWM

PWM duty cycle control for D7

PWM

PWM duty cycle control for D8

PWM

PWM duty cycle control for D9

1F TO 24 RESERVED

[7:0]

RESERVED FOR FUTURE USE

25

GPO PWM

R/W

00000000

10101111

PWM

PWM duty cycle control for GPO

26

D1 CURRENT CONTROL

[7:0]

CURRENT

D1 output current control register. Default 17.5 mA

(typ.)

27

28

29

D2 CURRENT CONTROL

D3 CURRENT CONTROL

D4 CURRENT CONTROL

R/W

10101111

CURRENT

D2 output current control register. Default 17.5 mA

(typ.)

CURRENT

D3 output current control register. Default 17.5 mA

(typ.)

CURRENT

D4 output current control register. Default current is

17.5 mA (typ.)

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Table 5. Control Register Map (continued)

Hex

Register Name

Bit(s)

Read/Wr Default Value

Bit Mnemonic and Description

Address

ite

After Reset

2A

2B

2C

2D

2E

D5 CURRENT CONTROL

[7:0]

R/W

10101111

CURRENT

D5 output current control register. Default current is

17.5 mA (typ.)

D6 CURRENT CONTROL

D7 CURRENT CONTROL

D8 CURRENT CONTROL

D9 CURRENT CONTROL

[7:0]

R/W

10101111

CURRENT

D6 output current control register. Default current is

17.5 mA (typ.)

CURRENT

D7 output current control register. Default current is

17.5 mA (typ.)

CURRENT

D8 output current control register. Default current is

17.5 mA (typ.)

CURRENT

D9 output current control register. Default current is

17.5 mA (typ.)

2F TO 35 RESERVED FOR FUTURE

USE

[7:0]

[7]

RESERVED FOR FUTURE USE

36

CONFIG

R/W

R

0xxxxx0x

x1xxxx0x

xx0xxx0x

xxx00x0x

xxxxx00x

xxxxxx0x

xxxxxx00

x0000000

0xxxxxxx

x1xxxxxx

PWM_POWERSAVE

Enables PWM powersave option

[6]

EN_AUTO_INCR

Serial bus address auto increment enable

[5]

POWERSAVE_EN

Powersave mode enable

[4:3]

[2]

CP_MODE

Charge pump gain selection

FADE_TO_OFF

Automatic fade out enable

[1]

RESERVED Note that this bit should always be set

to zero when writing register.

[0]

INT_CLK_EN

LED Clock source selection

37

38

39

3A

ENGINE1 PC

[6:0]

[7]

PC

Program counter for engine 1

ENGINE2 PC

PC

Program counter for engine 2

ENGINE3 PC

PC

Program counter for engine 3

STATUS/INTERRUPT

LED_TEST_MEASUREMENT_DONE

Indicates when the LED test measurement is done.

[6]

R

MASK_BUSY

Mask bit for interrupt generated by START_UP

BUSY or ENGINE_BUSY

[5]

[4]

R

xx0xxxxx

xxx0xxxx

START_UP BUSY

This bit indicates that the start-up sequence is

running

ENGINE_BUSY

This bit indicates that a program execution engine is

clearing internal registers

[3]

[2]

[1]

[0]

R

xxxx0xxx

xxxxx0xx

xxxxxx0x

xxxxxxx0

EXT_CLK_USED

Indicates when external clock signal bit is set

ENG1_INT

Interrupt bit for program execution engine 1

ENG2_INT

Interrupt bit for program execution engine 2

ENG3_INT

Interrupt bit for program execution engine 3

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Table 5. Control Register Map (continued)

Hex

Register Name

Bit(s)

Read/Wr Default Value

Bit Mnemonic and Description

Address

ite

After Reset

3B

GPO

[2]

R/W

xxxxx0xx

INT_CONF

INT pin can be configured to function as a GPO with

this bit.

[1]

[0]

R/W

xxxxxx0x

xxxxxxx0

GPO

GPO pin control

INT_GPO

GPO pin control for INT pin (when INT_CONF is set

to '1')

3D

41

RESET

[7:0]

R/W

00000000

RESET

Writing 11111111 into this register resets the LP8501

LED TEST CONTROL

[7]

[6]

[5]

R/W

0xxxxxxx

x0xxxxxx

xx0xxxxx

EN_LED_TEST_ADC

EN_LED_TEST_INT

LED_TEST_CONTINUOUS_CONV

Continuous LED test measurement selection

[4:0]

[7:0]

R/W

R

xxx00000

N/A

LED_TEST_CTRL

Control bits for LED test

42

LED TEST ADC

LED_TEST_ADC

LED test result

48

49

4A

4C

GROUP FADER1

GROUP FADER2

GROUP FADER3

[7:0]

[6:0]

R/W

00000000

x0000000

GROUP FADER

ADDR

ENG1 PROG START

ADDR

4D

4E

4F

ENG2 PROG START

ADDR

[6:0]

[2:0]

R/W

x0001000

x0010000

xxxxx000

ADDR

ENG3 PROG START

ADDR

PROG MEM PAGE SEL

PAGE_SEL

34

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Table 5. Control Register Map (continued)

Hex

Register Name

Bit(s)

Read/Wr Default Value

Bit Mnemonic and Description

Address

ite

After Reset

00000000

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

PROGRAM MEMORY

00h/10h/20h/30h/40h/50h

[15:8]

[7:0]

R/W

PROGRAM MEMORY

01h/11h/21h/31h/41h/51h

[15:8]

[7:0]

PROGRAM MEMORY

02h/12h/22h/32h/42h/52h

[15:8]

[7:0]

PROGRAM MEMORY

03h/13h/23h/33h/43h/53h

[15:8]

[7:0]

PROGRAM MEMORY

04h/14h/24h/34h/44h/54h

[15:8]

[7:0]

PROGRAM MEMORY

05h/15h/25h/35h/45h/55h

[15:8]

[7:0]

PROGRAM MEMORY

06h/16h/26h/36h/46h/56h

[15:8]

[7:0]

CMD

Every Instruction is 16-bit wide.

The LP8501 can store 96 instructions. Each

instruction consists of 16 bits. Because one register

has only 8 bits, one instruction requires two register

addresses. In order to reduce program load time the

LP8501 supports address auto-incrementation.

Register address is incremented after each 8 data

bits. Thus the whole program memory page can be

written in one serial bus write sequence.

PROGRAM MEMORY

07H/17H/27H/37H/47H/57H

[15:8]

[7:0]

PROGRAM MEMORY

08h/18h/28h/38h/48h/58h

[15:8]

[7:0]

PROGRAM MEMORY

09h/19h/29h/39h/49h/59h

[15:8]

[7:0]

PROGRAM MEMORY

0Ah/1Ah/2Ah/3Ah/4Ah/5Ah

[15:8]

[7:0]

PROGRAM MEMORY

0Bh/1Bh/2Bh/3Bh/4Bh/5Bh

[15:8]

[7:0]

PROGRAM MEMORY

0Ch/1Ch/2Ch/3Ch/4Ch/5Ch

[15:8]

[7:0]

PROGRAM MEMORY

0Dh/1Dh/2Dh/3Dh/4Dh/5Dh

[15:8]

[7:0]

PROGRAM MEMORY

0Eh/1Eh/2Eh/3Eh/4Eh/5Eh

[15:8]

[7:0]

PROGRAM MEMORY

0FH/1FH/2FH/3FH/4FH/5F

H

[15:8]

[7:0]

76

GAIN CHANGE CONTROL

[7:6]

R/W

000xxxxx

THRESHOLD

Threshold voltage (typ.)

00 — 400 mV

01 — 300 mV

10 — 200 mV

11 — 100 mV

[5]

R/W

xx0xxxxx

xx000xxx

RESERVED BIT

When writing to register, write always '0'

[4:3]

TIMER

00 — 5 ms

01 — 10 ms

10 — 50 ms

11 — infinite

FORCE_1x

[2]

R/W

xx0xx0xx

Activates 1.5x to 1x timer

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LP8501 Control Register Details

00 ENABLE/ ENGINE CONTROL1

•

00 - Bit [6] CHIP_EN

–

1 = internal startup sequence powers up all the needed internal blocks and the device enters normal mode

0 = standby mode is entered. Control registers can be written or read (writing into PWM and Channel1–3

PC registers and to register 00h ENGINE1–3_EXEC bits is not possible).

•

00 — Bits [5:4] ENGINE1_EXEC

–

Engine 1 program execution control. Execution register bits define how the program is executed. Program

start address can be programmed to Program Counter (PC) register 37h.

00 = Hold: Hold causes the execution engine to finish the current instruction and then stop. Program

counter (PC) can be read or written only in this mode.

01 = Step: Execute the instruction at the location pointed by the PC, increment the PC by one and then

reset ENG1_EXEC bits to 00 (i.e. enter hold).

–

10 = Free Run: Start program execution from the instruction pointed by the PC.

11 = Execute Once: Execute the instruction pointed by the current PC value and reset ENG1_EXEC to 00

(i.e. enter hold). The difference between step and executeonce is that executeonce does not increment

the PC.

•

00 — Bits [3:2] ENGINE2_EXEC

–

Engine 2 program execution control. Equivalent to above definition of control bits. Program start address

can be programmed to Program Counter (PC) register 38h.

00 — Bits [1:0] ENGINE3_EXEC

–

Engine 3 program execution control. Equivalent to engine 1 control bits. Program start address can be

programmed to Program Counter (PC) register 39h.

01 ENGINE CONTROL2

•

Operation modes are defined in this register.

–

Disabled: Engines can be configured to disabled mode separately.

Load Program: Writing to program memory is allowed only when the engine is in load program operation

mode and engine busy bit (3Ah) is not set. Serial bus master should check the busy bit before writing to

program memory. All the three engines are in hold while one or more engines are in load program mode.

PWM values are frozen, also. Program execution continues when all the engines are out of load program

mode. Load program mode resets the program counter of the respective engine. Loadprogram mode can

be entered from the disabledmode only. Entering loadprogram mode from the runprogram mode is not

allowed.

–

Run Program: Run program mode executes the instructions stored in the program memory. Execution

register (ENG1_EXEC etc.) bits define how the program is executed (hold, step, freerun or executeonce).

Program start address can be programmed to Program Counter (PC) register. The Program Counter is

reset to zero when the PC’s upper limit value is reached.

Halt: Instruction execution aborts immediately and engine operation halts.

•

01 — Bit [5:4] ENGINE1_MODE

–

00 = disabled

01 = load program to SRAM, reset engine 1 PC

10 = run program as defined by ENGINE1_EXEC bits

11 = halt, halts program execution. Current command execution stopped

01 — Bits [3:2] ENGINE2_MODE

–

00 = disabled

01 = load program to SRAM, reset engine 2 PC

10 = run program as defined by ENGINE2_EXEC bits

11 = halt, halts program execution. Current command execution stopped

•

01 — Bits [1:0] ENGINE3_MODE

–

00 = disabled

01 = load program to SRAM, reset engine 3 PC

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–

10 = run program as defined by ENGINE3_EXEC bits

11 = halt, halts program execution. Current command execution stopped

•

Note that changing mode from Run to Load is not allowed. Preferred sequence is 10 –> 00 –> 01.

02 GROUP 1 FADING

•

This is the register used to assign fade-in and fade-out times for group 1. Time can be set with 4 bits.

02 — Bits [7:4] FADE_IN

02 — Bits [3:0] FADE_OUT

FADE_IN/FADE_OUT

Time, s

0.0

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0.05

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.5

2.0

3.0

4.0

03 GROUP 2 FADING

•

See GROUP 1 FADING

04 GROUP 3 FADING

See GROUP 1 FADING

05 POWER CONFIG

•

05 — Bit [0] CHP_CON_7_9

–

1 = VDD7_9 should be connected to V_OUT

0 = VDD7_9 should be connected to V_DD

•

05 — Bit [1] CHP_CON_1_6

–

1 = VDD1_6 should be connected to V_OUT

0 = VDD1_6 should be connected to V_DD

06 D1 CONTROL

•

This is the register used to assign the D1 output to the GROUP FADER group 1, 2, or 3, or none of them.

This register selects between linear and logarithmic PWM brightness adjustment. By using logarithmic PWM

scale the visual effect looks like linear. Logarithmic adjustment converts internally an 8-bit PWM value to a

logarithmic 12-bit value.

•

06 — Bit [7:6] GROUP_SELECT

–

00 = No group fader set, clears group fader set for D1. Default setting.

01 = Fader group 1 controls the D1 driver. The user can set the overall output of the group by the GROUP

1 FADER register at the address 48h and the fade-in/fade-out time by the GROUP 1 FADING register at

the address 02h.

–

10 = Fader group 2 controls the D1 driver. The user can set the overall output of the group by the GROUP

2 FADER register at the address 49h and the fade-in/fade-out time by the GROUP 2 FADING register at

the address 03h.

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–

11 = Fader group 3 controls the D1 driver. The user can set the overall output of the group by the GROUP

3 FADER register at the address 4Ah and the fade-in/fade-out time by the GROUP 3 FADING register at

the address 04h.

•

06 — Bit [5] LOG_EN

–

0 = linear adjustment.

1 = logarithmic adjustment.

This bit is effective for both the program execution engine control and direct PWM control.

07 D2 CONTROL to 0E D9 CONTROL

The control registers and control bits for D2 output to D9 output are similar to that given to D1.

15 GPO CONTROL

The control register and control bits for GPO output are similar to that given to D1.

16 D1 PWM

•

This is the PWM duty cycle control for D1 output. D1 PWM register is effective during direct control operation

- direct PWM control is active after power up by default. Note: serial bus address auto increment is not

supported for register addresses from 16 to 1E.

•

16 — Bits [7:0] PWM

–

16 - Bits [7:0] PWM These bits set the D1 output PWM as shown in Figure 29 below.

100

75

50

25

0

00000000

10000000

PWM Bits

11111111

Figure 29.

17 D2 PWM to 1E D9 PWM

•

PWM duty cycle control for outputs D2 to D9. The control registers and control bits for D2 output to D9 output

are similar to that given to D1.

25 GPO PWM

PWM duty cycle control for GPO. The control register and control bits for GPO are similar to that given to D1.

26 D1 OUTPUT CURRENT CONTROL

•

D1 LED driver current control register. The resolution is 8-bits and step size is 100 μA. .

CURRENT bits

00000000

00000001

00000010

...

Output Current

0.0 mA

0.1 mA

0.2 mA

...

17.5 mA default setting

....

10101111

....

11111110

11111111

25.4 mA

25.5 mA

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27 D2 CURRENT CONTROL to 2E D9 CURRENT CONTROL

•

The control registers and control bits for D2 output up to D9 output are similar to that given to D1 output.

36 CONFIG

•

This register contains miscellaneous control bits.

36 — Bit [7] PWM_POWERSAVE

–

1 = PWM powersave ON

0 = PWM powersave OFF

See the Power Saving section for further details.

•

36 — Bit [6] EN_AUTO_INCR

–

The automatic increment feature of the serial bus address enables a quick memory write of successive

registers within one transmission.

–

1 = serial bus address automatic increment is enabled.

0 = serial bus address automatic increment is disabled.

•

36 — Bit [5] POWERSAVE_EN

–

1 = power save mode is enabled.

0 = power save mode is disabled. See the Power Saving section for further details.

36 — Bits [4:3] CP_MODE

–

Charge pump operation mode

00 = OFF

01 = forced to bypass mode (1x)

10 = forced to 1.5x mode; output voltage is boosted to 4.5V.

11 = automatic mode selection

•

36 — Bit [2] FADE_TO_OFF

–

Enables group fading when device is shut down through CHIP_EN.

1 = Group fading ON.

0 = Group fading OFF.

•

36 — Bit [1] RESERVED

This bit is reserved and should be written to zero.

36 — Bits [0] Clock selection bit

–

Program execution is clocked with internal 32 kHz clock or with external clock. Clocking is controlled with

bits [1:0] n the following way:

–

0 = external clock source (CLK pin)

1 = internal clock

External clock can be used if a clock signal is present on CLK-pin. External clock frequency must be 32

kHz for correct operation. If a higher or a lower frequency is used, it will affect on the program engine

operation speed.

–

If external clock is not used in the application, CLK pin should be connected to GND to avoid oscillation on

this pin and extra current consumption.

37 ENGINE1 PC

37 — Bits [6:0] PC

•

–

Program counter starting value for program execution engine 1; A value from 0000000 to 1100000. The

maximum value depends on program memory allocation between the three program execution engines.

38 ENGINE2 PC

38 — Bits [6:0] PC

Program counter starting value for program execution engine 2; A value from 0000000 to 1100000.

39 ENGINE3 PC

39 — Bits [6:0] PC

Program counter starting value for program execution engine 3; A value from 0000000 to 1100000.

•

–

•

–

3A STATUS/INTERRUPT

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•

3A — Bit [7] LED_TEST_MEASUREMENT_DONE

–

This bit indicates when the LED test is done, and the result is written to the LED TEST ADC register.

Typically the conversion takes 2.7 milliseconds to complete.

–

1 = LED test done

0 = LED test not done

This bit is a read-only bit, and it is cleared (to “0”) automatically after a read operation.

•

3A — Bit [6] MASK_BUSY

–

Mask bit for interrupts generated by STARTUP_BUSY or ENGINE_BUSY.

1 = Interrupt events will be masked i.e. no external interrupt will be generated from STARTUP_BUSY or

ENGINE_BUSY event (default).

–

0 = External interrupt will be generated when STARTUP_BUSY or ENGINE_BUSY condition is no longer

true. Reading the register 3Ah clears the status bits [5:4] and releases INT pin to high state.

•

3A — Bit [5] STARTUP_BUSY

–

A status bit which indicates that the device is running the internal start-up sequence. See Modes of

Operation for details.

–

1 = internal start-up sequence running. Note: STARTUP_BUSY = 1 always when CHIP_EN bit is '0'

0 = internal start-up sequence completed

3A — Bit[4] ENGINE_BUSY

–

A status bit which indicates that a program execution engine is clearing internal registers. Serial bus

master should not write or read program memory or registers 00h, 01h, 37h to 39h or 4Ch to 4Eh, when

this bit is set to '1'.

–

1 = at least one of the engines is clearing internal registers

0 = engine ready

•

3A — Bit [3] EXT_CLK_USED

–

1 = external clock bit is set

0 = external clock bit is not set

This bit is high when external clock signal on CLK pin is set from register. Does not detect automatically

the external clock, only the bit selection from register 36h.

3A — Bits [2:0] ENG1_INT, ENG2_INT, ENG3_INT

–

1 = interrupt set

0 = interrupt not set/clear

Interrupt bits for program execution engine 1, 2 and 3, respectively. These bits are set by END instruction.

Reading the interrupt bit clears the interrupt.

3B GPO

•

LP8501 has one General Purpose Output pin (GPO). Status of the pin can be controlled with this register.

Also, INT pin can be configured to function as a GPO by setting the bit INT_CONF. When INT is configured

to function as a GPO, output level is defined by the V_DDvoltage.

•

3B — Bit [2] INT_CONF

–

1 = INT pin is set to function as an interrupt pin (default).

0 = INT pin is configured to function as a GPO.

•

3B — Bit [1] GPO

–

0 =GPO pin state is low.

1 = GPO pin state is high.

GPO pins are digital CMOS outputs, and no pull-up/down resistors are needed.

3B — Bit [0] GPO_INT

–

0 = INT pin state is low (if INT_CONF = 1).

1 = INT pin state is high (if INT_CONF = 1).

When INT pin’s GPO function is disabled, it operates as an open drain pin. INT signal is active low, i.e.

when interrupt signal is send, the pin is pulled to GND. External pull-up resistor is needed for proper

functionality.

3D RESET

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•

3D — Bits [7:0] RESET

–

Writing 11111111 into this register resets the LP8501. Internal registers are reset to the default values.

Reading RESET register returns 00000000.

41 LED TEST CONTROL

•

LED test control register

41 — Bit [7] EN_LEDTEST_ADC

–

Writing this bit high (1) starts single LED test conversation. LED test measurement cycle is 2.7

milliseconds.

•

41 — Bit [6] EN_LEDTEST_INT

–

1 = interrupt signal will be send to the INT pin when the LED test is accomplished.

0 = no interrupt signal will be send to the INT pin when the LED test is accomplished.

Interrupt can be cleared by reading STATUS/INTERRUPT register 3Ah.

•

41 — Bit [5] CONTINUOUS_CONV

–

1 = Continuous LED test measurement. Not active in powersave mode.

0 = Continuous conversion is disabled.

41 — Bits [4:0] LED__TEST_CTRL

–

These bits are used for choosing the LED driver output to be measured. V_DD, INT-pin and charge-pump

output voltage can also be measured.

LED_TEST_CTRL bits

00000

Measurement

D1

00001

D2

D3

00010

00011

D4

00100

D5

00101

D6

00110

D7

000111

D8

01000

D9

01001 to 01110

01111

Reserved

V_OUT

10000

V_DD

10001

INT-pin voltage

VDD1_6

VDD7_9

N/A

10010

10011

10010 to 11111

42 LED TEST ADC

42 — Bits [7:0} LED_TEST_ADC

•

–

This is used to store the LED test result. Read-only register. LED test ADC least significant bit

corresponds to 30 mV. The measured voltage V (typ.) is calculated as follows: V = (RESULT(DEC) x 0.03

-1.478 V. For example, if the result is 10100110 = 166(DEC), the measured voltage is 3.50V (typ.). See

Figure 30 below.

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5

4

3

2

1

0

40

90

140

190

RESULT (DEC)

Figure 30.

48 GROUP FADER1

•

48 — Bits [7:0] GROUP_FADER

–

An 8-bit register to control all the LED-drivers mapped to GROUP FADER1. Group fader allows the user

to control dimming of multiple LEDs with a single serial bus write. This is a faster method to control the

dimming of multiple LEDs compared to the dimming done with the PWM registers (address 16h to 1Eh),

which would need multiple writes.

49 GROUP FADER2

49 — Bits [7:0] GROUP_FADER

See GROUP FADER1 description.

4A GROUP FADER3

4A — Bits [7:0]GROUP_FADER

See GROUP FADER1 description.

4C ENGINE1 PROG START ADDR

•

–

•

–

•

Program memory allocation for program execution engines is defined with PROG START ADDR registers.

4C — Bits [6:0] — ADDR

–

Engine 1 program start address.

4D ENG2 PROG START ADDR

4D — Bits [6:0] — ADDR

Engine 2 program start address.

4E ENG3 PROG START ADDR

4E — Bits [6:0] — ADDR

Engine 3 program start address.

4F PROG MEM PAGE SELECT

4F — Bits [2:0] — PAGE_SEL

•

–

•

–

•

–

These bits select the program memory page. The program memory is divided into six pages of 16

instructions; thus the total amount of the program memory is 96 instructions.

76 — GAIN CHANGE CONTROL

Note that these controls have effect only in automatic mode.

•

76 — Bits [7:6] — THRESHOLD

–

Threshold voltage (typ.) pre-setting. Bits set the threshold voltage at which the charge pump gain changes

from 1.5x to 1x. The threshold voltage is defined as the voltage difference between highest voltage output

(D1 to D6) and input voltage V_DD: V_THRESHOLD= V_DD— MAX (voltage on D1 to D6).

–

If V_THRESHOLDis larger than the set value (100 mV to 400 mV), the charge pump is in 1x mode.

00 = 400 mV

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–

01 = 300 mV

10 = 200 mV

11 = 100 mV

Note: Values above are typical and should not be used as product specification.

Note: Writing to THRESHOLD [7:6] bits by the user overrides factory settings. Factory settings are not

user accessible.

–

76 — Bit [5] — RESERVED

–

This bit is reserved for future use. When writing to register 76h, this bit should be written '0'.

76 — Bits [4:3] — TIMER

–

Automatic mode change from 1.5x to 1x is attempted at the interval specified with these bits. After the

specified interval time mode change to 1x is allowed if there is enough voltage over the LED drivers to

ensure proper operation. If FORCE_1x is set to '1' after the specified interval time 1x mode is always

tested.

–

00 = 5 ms

01 = 10 ms

10 = 50 ms

11 = infinite. The charge pump switches gain from 1x mode to 1.5x mode only. The gain reset back to

1x is enabled under certain conditions, for example in the powersave mode.

–

76 — Bit [2] — FORCE_1x

–

Activates forced mode change. In forced mode charge pump mode change from 1.5x to 1x is

attempted at the interval specified with the TIMER bits.

–

1 = forced mode changes enabled

0 = forced mode changes disabled

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APPLICATIONS INFORMATION

Recommended External Components

The LP8501 requires 4 external capacitors for proper operation. Surface-mount multi-layer ceramic capacitors

are recommended. Tantalum and aluminium capacitors are not recommended because of their high ESR. For

the flying capacitors (C1 and C2) multi-layer ceramic capacitors should always be used. These capacitors are

small, inexpensive and have very low equivalent series resistance (ESR <20 mΩ typ.). Ceramic capacitors with

X7R or X5R temperature characteristic are preferred for use with the LP8501. These capacitors have tight

capacitance tolerance (as good as ±10%) and hold their value over temperature (X7R: ±15% over −55°C to

125°C; X5R: ±15% over −55°C to 85°C). Capacitors with Y5V or Z5U temperature characteristic are generally

not recommended for use with the LP8501. Capacitors with these temperature characteristics typically have wide

capacitance tolerance (+80%, −20%) and vary significantly over temperature (Y5V: +22%, -82% over −30°C to

+85°C range; Z5U: +22%, −56% over +10°C to +85°C range). Under some conditions, a nominal 1 μF Y5V or

Z5U capacitor could have a capacitance of only 0.1μF. Such detrimental deviation is likely to cause Y5V and

Z5U capacitors to fail to meet the minimum capacitance requirements of the LP8501.

For proper operation it is necessary to have at least 0.24 µF of effective capacitance for each of the flying

capacitors under all operating conditions. The output capacitor C_OUTdirectly affects the magnitude of the output

ripple voltage. In general, the higher the value of C_OUT, the lower the output ripples magnitude. For proper

operation it is necessary to have at least 0.50 µF of effective capacitance for C_INand C_OUTunder all operating

conditions. The voltage rating of all four capacitors should be 6.3V; 10V is recommended.

The table below lists recommended external components from some leading ceramic capacitor manufacturers. It

is strongly recommended that the LP8501 circuit be thoroughly evaluated early in the design-in process with the

mass-production capacitors of choice. This will help ensure that any variability in capacitance does not negatively

impact circuit performance.

Model

1 µF for COUT and CIN

C1005X5R1A105K

LMK105BJ105KV-F

ECJ0EB1A105M

Type

Vendor

Voltage Rating

Package Size

Ceramic X5R

TDK

10V

0402

0504

Taiyo Yuden

Panasonic

ECJUVBPA105M

Ceramic X5R, array

of two

470 nF for C1 and C2

C1005X5R1A474K

LMK105BJ474KV-F

ECJ0EB0J474K

LEDs

Ceramic X5R

TDK

10V

6.3V

0402

Taiyo Yuden

Panasonic

User defined.

44

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Product Folder Links: LP8501

LP8501

www.ti.com

SNVS548D –SEPTEMBER 2008–REVISED AUGUST 2013

REVISION HISTORY

Changes from Revision C (May 2013) to Revision D

Page

•

Changed layout of National Data Sheet to TI format; publish full data sheet to replace product brief .............................. 44

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45

Product Folder Links: LP8501

MECHANICAL DATA

YFQ0025xxx

D

0.600

±0.075

E

TMD25XXX (Rev C)

D: Max = 2.29 mm, Min = 2.23 mm

E: Max = 2.29 mm, Min = 2.23 mm

4215084/A

12/12

A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

NOTES:

www.ti.com

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LP8501TMX/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	多功能 9 输出 LED 驱动器 \| YFQ \| 25 \| -30 to 85 驱动接口集成电路驱动器
文件：	总51页 (文件大小：1645K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LP8501TMX/NOPB [TI]

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