LP875701-Q1_技术文档

LP875701-Q1

ZHCSJ52A –DECEMBER 2019 –REVISED AUGUST 2021

具有集成开关的LP875701-Q1 四相、3MHz、1V、10A 直流/直流降压转换器

1 特性

3 说明

• 符合汽车应用要求

• 具有符合AEC-Q100 标准的下列特性：

LP875701-Q1 器件旨在满足各种汽车电源应用中新型

处理器和平台的电源管理要求。该器件包含 4 个降压

直流/直流转换器内核，这些内核配置为采用强制PWM

模式的四相输出。该器件由I²C 兼容串行接口和使能信

号进行控制。

– 器件温度等级1：–40°C 至+125°C 环境工作

温度范围

– 器件HBM ESD 分类等级2

– 器件CDM ESD 分类等级C4B

• 输入电压：2.8V 至5.5V

• 输出电压：1.0V

• 四个高效降压直流/直流转换器内核：

LP875701-Q1 支持对多相位输出的远程差分电压感

应，可补偿稳压器输出与负载点 (POL) 之间的 IR 压

降，从而提高输出电压的精度。可以强制开关时钟进入

PWM 模式并将其与外部时钟同步，从而更大程度地降

低干扰。

– 最大输出电流：10A（2.5A/相）

• 开关频率：3MHz

• 扩频模式和相位交错

LP875701-Q1 器件支持负载电流测量，无需添加外部

电流感应电阻器。LP875701-Q1 器件还支持与使能信

号同步的可编程启动与关断延迟和序列。这些序列可能

还包括用于控制外部稳压器、负载开关和处理器复位的

GPIO 信号。在启动期间，该器件会对输出压摆率进行

控制，从而最大限度地减小输出电压过冲和浪涌电流。

• 可配置通用I/O (GPIO)

• I²C 兼容接口，支持标准(100kHz)、快速

(400kHz)、快速+ (1MHz) 和高速(3.4MHz) 模式

• 具有可编程屏蔽的中断功能

• 可编程电源正常信号(PGOOD)

• 输出短路和过载保护

器件信息⁽¹⁾

• 过热警告和保护

• 过压保护(OVP) 和欠压锁定(UVLO)

封装尺寸（标称值）

器件型号

封装

LP875701-Q1

VQFN-HR (26)

4.50mm × 4.00mm

2 应用

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 汽车信息娱乐系统

• 仪表组

• 雷达

• 摄像头电源应用

V_IN

100

90

80

70

60

VIN_B0

VIN_B1

VIN_B2

VIN_B3

VANA

SW_B0

SW_B1

SW_B2

SW_B3

V_OUT

LOAD

NRST

SDA

SCL

FB_B0

FB_B1

nINT

PGOOD

FB_B2

FB_B3

CLKIN

50

V_IN= 3.3 V

V_IN= 5.0 V

EN1 (GPIO1)

EN2 (GPIO2)

EN3 (GPIO3)

GNDs

40

0.01

0.1

1

10

Current (A)

D140

简化版原理图

效率与输出电流间的关系

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSA05

LP875701-Q1

ZHCSJ52A –DECEMBER 2019 –REVISED AUGUST 2021

www.ti.com.cn

Table of Contents

7.5 Programming............................................................ 31

7.6 Register Maps...........................................................34

8 Application and Implementation..................................56

8.1 Application Information............................................. 56

8.2 Typical Application.................................................... 56

9 Power Supply Recommendations................................61

10 Layout...........................................................................62

10.1 Layout Guidelines................................................... 62

10.2 Layout Example...................................................... 63

11 Device and Documentation Support..........................64

11.1 接收文档更新通知................................................... 64

11.2 支持资源..................................................................64

11.3 Trademarks............................................................. 64

11.4 Electrostatic Discharge Caution..............................64

11.5 术语表..................................................................... 64

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................6

6.5 Electrical Characteristics.............................................6

6.6 I²C Serial Bus Timing Requirements........................ 10

6.7 Typical Characteristics..............................................12

7 Detailed Description......................................................13

7.1 Overview...................................................................13

7.2 Functional Block Diagram.........................................14

7.3 Feature Descriptions.................................................14

7.4 Device Functional Modes..........................................30

Information.................................................................... 64

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (December 2019) to Revision A (August 2021)

Page

• 更新了整个文档中的表、图和交叉参考的编号格式.............................................................................................1

2

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5 Pin Configuration and Functions

26

25

24

23

22

FB_B2

FB_B3

1

21

EN3

NRST

nINT

2

20

19

18

17

16

15

CLKIN

3

AGND

VANA

AGND

PGOOD

EN2

4

AGND

SCL

5

SDA

6

EN1

7

FB_B0

FB_B1

8

14

9

10

11

12

13

图5-1. RNF Package 26-Pin VQFN-HR With Thermal Pad Top View

表5-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NO.

NAME

1

FB_B2

A

D/I/O

D/I

Output voltage feedback (positive) for the BUCK2 converter.

Programmable enable signal for the buck regulators (can be also configured to select between

two buck output-voltage levels). This pin functions alternatively as GPIO3.

2

3

EN3

CLKIN

AGND

External clock input. Connect this pin to ground if the external clock is not used.

Ground

4, 17,

Thermal Pad

G

5

6

SCL

SDA

D/I

Serial interface clock input for I²C access. Connect this pin to a pullup resistor.

D/I/O Serial interface data input and output for I²C access. Connect this pin to a pullup resistor.

Programmable enable signal for the buck regulators (can be also configured to select between

two buck output voltage levels). This pin functions alternatively as GPIO1.

7

8

EN1

D/I/O

FB_B0

A

P

Output voltage feedback (positive) for the BUCK0 converter.

Input for the BUCK0 converter. The separate power pins, VIN_Bx, are not connected together

internally. The VIN_Bx pins must be connected together in the application and be locally

bypassed.

9

VIN_B0

SW_B0

10

11

12

A

G

A

BUCK0 switch node

PGND_B01

SW_B1

Power ground for the BUCK0 and BUCK1 converters

BUCK1 switch node

Input for the BUCK1 converter. The separate power pins, VIN_Bx, are not connected together

internally. The VIN_Bx pins must be connected together in the application and be locally

bypassed.

13

VIN_B1

P

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表5-1. Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NO.

NAME

Output voltage feedback (positive) for the BUCK1 converter. This pin functions alternatively as the

output ground feedback (negative) for the BUCK0 converter.

14

FB_B1

A

Programmable enable signal for the buck regulators (can be also configured to select between

two buck output voltage levels). This pin functions alternatively as GPIO2.

15

16

18

EN2

PGOOD

VANA

D/I/O

D/O

P

Power-good indication signal

Supply voltage for the analog and digital blocks. This pin must be connected to the same node as

VIN_Bx.

19

20

nINT

D/O

D/I

Open-drain interrupt output. This pin is active low.

Reset signal for the device

NRST

Output voltage feedback (positive) for the BUCK3 converter. This pin functions alternatively as the

output ground feedback (negative) for the BUCK2 converter.

21

22

FB_B3

A

P

Input for the BUCK3 converter. The separate power pins, VIN_Bx, are not connected together

internally. The VIN_Bx pins must be connected together in the application and be locally

bypassed.

VIN_B3

SW_B3

23

24

25

A

G

A

BUCK3 switch node

PGND_B23

SW_B2

Power ground for the BUCK2 and BUCK3 converters

BUCK2 switch node

Input for the BUCK2 converter. The separate power pins, VIN_Bx, are not connected together

internally. The VIN_Bx pins must be connected together in the application and be locally

bypassed.

26

VIN_B2

P

(1) A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

MAX

UNIT

Voltage on power connections

Voltage on buck switch nodes

VIN_Bx, VANA

SW_Bx

6

V

–0.3

(VIN_Bx + 0.3 V)

with 6 V

V

–0.3

maximum

(VANA + 0.3 V)

with 6 V

maximum

Voltage on buck voltage sense nodes

Voltage on NRST input

FB_Bx

NRST

6

V

–0.3

SDA, SCL, nINT, CLKIN

(VANA + 0.3 V)

with 6 V

maximum

Voltage on logic pins (input or output pins)

EN1 (GPIO1), EN2 (GPIO2), EN3

(GPIO3), PGOOD

V

–0.3

Maximum lead temperature (soldering, 10 sec.)

Junction temperature, T_J-MAX

260

150

°C

–40

–65

Storage temperature, T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltage values are with respect to network ground.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

Electrostatic

discharge

V_(ESD)

All pins

V

Corner pins (1, 8, 14, and 21)

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

MAX UNIT

INPUT VOLTAGE

Voltage on power connections

Voltage on NRST

VIN_Bx, VANA

NRST

2.8

1.65

0

5.5

V

VANA with

5.5 V maximum

Voltage on logic pins (input or output pins)

nINT, CLKIN

ENx, PGOOD

5.5

VANA with

5.5 V maximum

Voltage on I²C interface, standard (100 kHz), fast (400

khz), fast+ (1 MHz), and high-speed (3.4 MHz) modes

SCL, SDA

1.65

3.1

1.95

V

Voltage on I²C interface, standard (100 kHz), fast (400

kHz), and fast+ (1 MHz) modes

VANA with

3.6 V maximum

TEMPERATURE

Junction temperature, T_J

Ambient temperature, T_A

140

125

°C

–40

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6.4 Thermal Information

LP875701-Q1

THERMAL METRIC⁽¹⁾

RNF (VQFN-HR)

UNIT

26 PINS

34.6

16.5

4.7

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.6

ψ_JT

4.7

ψ_JB

R_θJC(bot)

1.4

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

–40°C ≤T_J≤+140°C, C_POL= 122 µF/phase, specified V_VANA, V_{VIN_Bx}, V_NRST, V_{VOUT_Bx}, and I_OUTrange, unless otherwise

noted. Typical values are at T_J= 25°C, V_VANA= V_{VIN_Bx}= 3.7 V, and V_OUT= 1.0 V, unless otherwise noted.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

EXTERNAL COMPONENTS

C_IN

Input filtering capacitance Connected from VIN_Bx to PGND_Bx

1.9

10

22

µF

Output filtering capacitance

per phase, local

C_OUT

Point-of-load (POL)

capacitance per phase

C_POL

122

µF

Total output capacitance⁽²⁾

4-phase output

C_OUT-TOTAL

400

1500 µF

(local and POL)

ESR of the input and

1 MHz ≤f ≤10 MHz

output capacitor

ESR_C

2

10

mΩ

0.33

µH

Inductor value and

tolerance of the inductor

L

30%

–30%

DCR_L

Inductor DCR

20

mΩ

BUCK REGULATOR

V_{VIN_Bx}Input voltage range

2.8

5.5

10

V

Output current⁽³⁾The

maximum output current

from device is 10A

4-phase output, V_IN≥3 V

I_OUT

A

V

7.2

4-phase output, 2.8 V ≤V_IN< 3 V

regardless of device phase

configurations.

Input and output voltage

difference

Minimum voltage between

VIN_x and V_OUTto fulfill

the electrical

0.5

characteristics

DC output voltage and

accuracy, includes voltage mode, forced 4-phase operation, f_SW= 3

V_IN= 3.3 V +/- 5% , 5 V +/- 5%, forced PWM

V_{VOUT_DC}

reference, DC load and

line regulations, process,

and temperature

MHz +/- 10% (either through internal or

external clock), in case external clock is

used: spread-spectrum disabled

0.985

1

1.015

4-phase output, forced PWM mode, ESR_C

2 mΩ, L = 0.33 µH

<

Ripple voltage

3

0.1

mV_p-p

%/V

DC_LNR

DC_LDR

DC line regulation

I_OUT= I_OUT(max)

DC load regulation in PWM

mode

0.01

%/A

0 A ≤I_OUT≤I_OUT(max)

6

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6.5 Electrical Characteristics (continued)

–40°C ≤T_J≤+140°C, C_POL= 122 µF/phase, specified V_VANA, V_{VIN_Bx}, V_NRST, V_{VOUT_Bx}, and I_OUTrange, unless otherwise

noted. Typical values are at T_J= 25°C, V_VANA= V_{VIN_Bx}= 3.7 V, and V_OUT= 1.0 V, unless otherwise noted.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_IN= 5 V +/- 5%, f_SW= 3 MHz +/- 10%

(either through internal or external clock), in

case external clock is used: spread-

spectrum disabled, forced 4-phase

operation, forced PWM mode

±12

1.5 A ≤I_OUT≤7.5 A, t_r= t_f= 1 µs, C_OUT

=

22 µF/phase, L = 0.33 µH, C_POL= 122 µF/

phase

Transient load step

response in PWM mode

TR_LDSR

mV

V_IN= 3.3 V +/- 5%, f_SW= 3 MHz +/- 10%

(either through internal or external clock), in

case external clock is used: spread-

spectrum disabled, forced 4-phase

operation, forced PWM mode

±15

1.5 A ≤I_OUT≤7.5 A, t_r= t_f= 1 µs, C_OUT

=

22 µF/phase, L = 0.33 µH, C_POL= 122 µF/

phase

V_{VIN_Bx}stepping 3.15 V ↔ 3.4 V, t_r= t_f= 10

µs, I_OUT= I_OUT(max)

TR_LNSR

Transient line response

±2

mV

V

_{VIN_Bx}≥3 V

3.3

2.8

1.6

3.8

4.2

Forward current limit for each phase set to

3.5A (ILIMx[2:0]=4h)

Forward current limit for

each phase (peak for each

switching cycle)

I_{LIM FWD}

A

2.8 V ≤V_{VIN_Bx}< 3 V

Forward current limit for each phase set to

3.5A (ILIMx[2:0]=4h)

3.8

2

4.2

Negative current limit per

phase (peak for each

switching cycle)

I_{LIM NEG}

2.4

A

R_{DS(ON) HS}On-resistance, high-side

Each phase, between VIN_Bx and SW_Bx

pins, I = 1 A

29

17

3

65

35

mΩ

FET

R_{DS(ON) LS}On-resistance, low-side

Each phase, between SW_Bx and

PGND_Bx pins, I = 1 A

FET

Switching frequency, PWM

mode

f_SW

2.7

3.3 MHz

10%

Current balancing for

multiphase outputs

Current mismatch between phases, I_OUT> 1

A/phase

From ENx to V_OUT= 0.35 V (slew-rate

control begins), C_{OUT_TOTAL}= 144 µF/phase

Start-Up time (soft start)

200

µs

Output voltage slew-rate⁽⁴⁾

3.23

160

3.8

4.4 mV/µs

Output pulldown resistance Regulator disabled

Overvoltage monitoring (compared to DC

output-voltage level, V_{VOUT_DC}

Undervoltage monitoring (compared to DC

output-voltage level, V_{VOUT_DC}

Output voltage monitoring Deglitch time during regulator enable

230

300

64

Ω

39

–53

4

50

–40

7

)

mV

–29

)

10 µs

13 ms

10 µs

for PGOOD pin

PGOOD_SET_DELAY = 0h

Deglitch time during regulator enable

PGOOD_SET_DELAY = 1h

10

11

Deglitch time during operation and after

voltage change

4

7

Power-good threshold for Rising ramp voltage, enable or voltage

interrupt BUCKx_PG_INT, change

difference from final

Falling ramp voltage, voltage change

voltage

–20

–14

–8

20

mV

8

14

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6.5 Electrical Characteristics (continued)

–40°C ≤T_J≤+140°C, C_POL= 122 µF/phase, specified V_VANA, V_{VIN_Bx}, V_NRST, V_{VOUT_Bx}, and I_OUTrange, unless otherwise

noted. Typical values are at T_J= 25°C, V_VANA= V_{VIN_Bx}= 3.7 V, and V_OUT= 1.0 V, unless otherwise noted.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

mV

Power-good threshold for

status bit

BUCKx_PG_STAT

During operation, status signal is forced to

0h during voltage change

–20

–14

–8

EXTERNAL CLOCK AND PLL

Nominal frequency of the

external input clock

1

24 MHz

MHz

Nominal frequency step

size of the external input

clock

1

Required accuracy from

nominal frequency of the

external input clock

10%

–30%

Delay time for missing

external clock detection

1.8 µs

20 µs

Delay and debounce time

for external clock detection

Clock change delay

(internal to external)

delay from valid clock

detection to use of external

clock

600

300

µs

Cycle-to-cycle PLL output

clock jitter

ps, p-

p

PROTECTION FUNCTIONS

Temperature rising, TDIE_WARN_LEVEL =

0h

115

127

125

137

135

147

Thermal warning

°C

Temperature rising, TDIE_WARN_LEVEL =

1h

Thermal warning

hysteresis

20

150

20

Thermal shutdown

Temperature rising

140

160 °C

°C

Thermal shutdown

hysteresis

Voltage rising

Voltage falling

5.6

5.8

6.1

V

5.96

VANA_OVP

VANA overvoltage

5.45

5.73

VANA overvoltage

hysteresis

40

mV

Voltage rising

Voltage falling

2.51

2.5

2.63

2.6

2.75

V

2.7

VANA undervoltage

lockout

VANA_UVLO

LOAD CURRENT MEASUREMENT

Current measurement

range

Output current for maximum code

20.47

A

Resolution

Measurement accuracy

Measurement time

LSB

20

<10%

4

mA

I_OUT> 1 A

PWM mode

µs

CURRENT CONSUMPTION

Shutdown current

consumption

From VANA and VIN_Bx pins, NRST = 0 V,

VANA = VIN_Bx = 3.7 V

1.4

6.7

µA

From VANA and VIN_Bx pins, NRST = 1.8

V, VANA = VIN_Bx = 3.7 V, regulators

disabled

Standby current

consumption

8

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6.5 Electrical Characteristics (continued)

–40°C ≤T_J≤+140°C, C_POL= 122 µF/phase, specified V_VANA, V_{VIN_Bx}, V_NRST, V_{VOUT_Bx}, and I_OUTrange, unless otherwise

noted. Typical values are at T_J= 25°C, V_VANA= V_{VIN_Bx}= 3.7 V, and V_OUT= 1.0 V, unless otherwise noted.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Total current for forced 4-phase operation,

V_IN= 3.3 V

70

Active current consumption

during PWM operation

mA

Total current for forced 4-phase operation,

V_IN= 5 V

103

2

Additional current consumption when

internal RC oscillator, clock detector and

PLL are enabled

PLL and clock detector

current consumption

mA

DIGITAL INPUT SIGNALS: NRST, EN1, EN2, EN3, EN4, SCL, SDA, GPIO1, GPIO2, GPIO3, CLKIN

V_IL

V_IH

Input low level

Input high level

0.4

V

1.2

10

Hysteresis of Schmitt

trigger inputs

V_HYS

77

200 mV

ENx pulldown resistance

ENx_PD = 1h

500

kΩ

NRST pulldown resistance Always present

DIGITAL OUTPUT SIGNALS: nINT

650

1150

1700

0.4

kΩ

V_OL

R_P

Output low level

I_SOURCE= 2 mA

To VIO supply

V

External pullup resistor

10

kΩ

DIGITAL OUTPUT SIGNALS: SDA

V_OLOutput low level

I_SOURCE= 10 mA

0.4

V

DIGITAL OUTPUT SIGNALS: PGOOD, GPIO1, GPIO2, GPIO3

V_OL

V_OH

Output low level

I_SOURCE= 2 mA

I_SINK= 2 mA

0.4

V

Output high level,

configured to push-pull

V_VANA

V

_VANA–0.4

Supply voltage for external

pull-up resistor, configured

to open-drain

V_PU

V_VANA

V

External pullup resistor,

configured to open-drain

R_PU

10

kΩ

ALL DIGITAL INPUTS

I_LEAKInput current

All logic inputs over pin voltage range

(except NRST)

1

µA

−1

(1) All voltage values are with respect to network ground.

(2) The output voltage slew-rate setting limits the maximum output capacitance.

(3) The maximum output current can be limited by the forward current limit I_{LIM FWD}and by the junction temperature. The power dissipation

inside the die depends on the length of the current pulse and efficiency and the junction temperature may increase to thermal

shutdown level if the board and ambient temperatures are high.

(4) Output capacitance, forward and negative current limits and load current may limit the maximum and minimum slew rates.

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MAX UNIT

6.6 I²C Serial Bus Timing Requirements

These specifications are ensured by design. V_{IN_Bx}= 3.7 V, unless otherwise noted.

MIN

Standard mode

Fast mode

100

kHz

400

Serial clock frequency

Fast mode+

1

ƒ_SCL

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

3.4 MHz

1.7

4.7

1.3

0.5

160

320

4

Fast mode

µs

ns

µs

ns

t_LOW

SCL low time

Fast mode+

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

Fast mode

0.6

0.26

60

t_HIGH

SCL high time

Data setup time

Data hold time

Fast mode+

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

120

250

100

50

Fast mode

t_SU;DAT

t_HD;DAT

t_SU;STA

ns

Fast mode+

High-speed mode

Standard mode

10

3450

Fast mode

10

900

ns

Fast mode+

10

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

10

70

10

150

4.7

0.6

0.26

160

4

Fast mode

µs

ns

µs

ns

µs

Setup time for a start or a repeated

start condition

Fast mode+

High-speed mode

Standard mode

Fast mode

0.6

0.26

160

4.7

1.3

0.5

4

Hold time for a start or a repeated

start condition

t_HD;STA

Fast mode+

High-speed mode

Standard mode

Bus free time between a stop and

start condition

t_BUF

Fast mode

Fast mode+

Standard mode

Fast mode

0.6

0.26

160

µs

ns

t_SU;STO

Setup time for a stop condition

Fast mode+

High-speed mode

Standard mode

1000

300

120

80

Fast mode

20

t_rDA

Rise time of SDA signal

Fast mode+

ns

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

10

20

160

10

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These specifications are ensured by design. V_{IN_Bx}= 3.7 V, unless otherwise noted.

MIN

MAX UNIT

Standard mode

Fast mode

300

20 × (V_DD

/

300

5.5 V)

t_fDA

Fall time of SDA signal

20 × (V_DD

/

ns

Fast mode+

120

5.5 V)

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

10

80

160

30

1000

300

Fast mode

20

t_rCL

Rise time of SCL signal

Fast mode+

120

40

ns

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

High-speed mode, C_b= 100 pF

10

20

10

80

Rise time of SCL signal after a

repeated start condition and after

an acknowledge bit

80

t_rCL1

High-speed mode, C_b= 400 pF

Standard mode

20

160

300

20 × (V_DD

/

Fast mode

300

120

5.5 V)

t_fCL

Fall time of a SCL signal

20 × (V_DD

/

ns

Fast mode+

5.5 V)

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

10

40

80

20

Capacitive load for each bus line

(SCL and SDA)

C_b

400

50

pF

ns

Pulse width of spike suppressed

(SCL and SDA spikes that are less

than the indicated width are

suppressed)

Standard mode, fast mode and fast mode+

High-speed mode

t_SP

10

t_BUF

SDA

SCL

t_HD;STA

t_rCL

t_fDA

t_rDA

t_SP

t_LOW

t_fCL

t_HD;STA

t_SU;STA

t_SU;STO

t_HIGH

t_HD;DAT

S

t_SU;DAT

S

RS

P

START

REPEATED

START

STOP

START

图6-1. I²C Timing

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6.7 Typical Characteristics

Unless otherwise specified: T_A= 25°C, V_IN= 3.7 V, V_OUT= 1 V, V_(NRST)= 1.8 V, ƒ_SW= 3 MHz, L = 0.33 µH (Murata

DFE252012PD-R33M), C_OUT= 22 µF / phase, C_POL= 122 µF / phase.

4

3.5

3

10

9

8

7

6

5

4

3

2

1

0

2.5

2

1.5

1

0.5

0

2.5

3

3.5

4

Input Voltage (V)

4.5

5

5.5

2.5

3

3.5

4

Input Voltage (V)

4.5

5

5.5

D045

D046

V_(NRST)= 0 V

V_(NRST)= 1.8 V Regulators disabled

图6-2. Shutdown Current Consumption vs Input Voltage

图6-3. Standby Current Consumption vs Input Voltage

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7 Detailed Description

7.1 Overview

TheLP875701-Q1 is a high-efficiency, high-performance power supply device with four step-down DC/DC

converter cores for automotive applications. 表7-1 lists the output characteristics of the regulators.

表7-1. Regulator Outputs

OUTPUT

SUPPLY

V_OUTRANGE

RESOLUTION

I_MAXMAXIMUM OUTPUT CURRENT

BUCK0, BUCK1, BUCK2, BUCK3 in one 4-

phase output

1.0 V

Not Applicable

2.5 A per phase

The LP875701-Q1 also supports switching clock synchronization to an external clock. The nominal frequency of

the external clock can be from 1 MHz to 24 MHz with 1-MHz steps.

Additional features include:

• Soft start

• Input voltage protection:

– Undervoltage lockout

– Overvoltage protection

• Output voltage monitoring and protection:

– Overvoltage monitoring

– Undervoltage monitoring

– Overload protection

• Thermal warning

• Thermal shutdown

Three enable signals can be multiplexed to general purpose I/O (GPIO) signals. The direction and output type

(open-drain or push-pull) are programmable for the GPIOs.

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7.2 Functional Block Diagram

VANA

Buck0

nINT

Interrupts

Enable,

ILIM Det

Pwrgood Det

Overload and SC Det

Iload ADC

EN1 (GPIO1)

EN2 (GPIO2)

EN3 (GPIO3)

Slew-Rate

Control

Buck1

ILIM Det

Pwrgood Det

SDA

SCL

I2C

Overload and SC Det

Iload ADC

OTP

EPROM

PGOOD

Registers

Buck2

ILIM Det

Pwrgood Det

Digital

Logic

Overload and SC Det

Iload ADC

UVLO

Thermal

Monitor

NRST

Buck3

ILIM Det

Pwrgood Det

Ref &

Bias

SW

Reset

Oscillator

Overload and SC Det

Iload ADC

CLKIN

7.3 Feature Descriptions

7.3.1 Multi-Phase DC/DC Converters

7.3.1.1 Overview

The LP875701-Q1 includes four step-down DC/DC converter cores which are configured as a 4-phase single

output.

TheLP875701-Q1 has the following features:

• Optional external clock input to minimize crosstalk

• Optional spread spectrum technique to decrease EMI

• Phase control for optimized EMI

• Synchronous rectification

• Current mode loop with PI compensator

• Soft start

• Power Good flag with maskable interrupt

• Power Good signal (PGOOD) with selectable sources

• Average output current sensing (for load current measurement)

• Current balancing between the phases of the converter

• Differential voltage sensing from point of the load for multiphase output

The following parameters can be programmed via registers:

• Forced multiphase operation for multiphase outputs (forces also the PWM operation)

• Enable and disable delays for regulators and GPIOs controlled by ENx pins

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The 4 buck converters in the LP875701-Q1 operate in forced multiphase configuration as one 4-phase

converter, which offers several advantages over one power stage converter. For application processor power

delivery, lower ripple on the input and output currents and faster transient response to load steps are the most

significant advantages. Also, because the load current is evenly shared among multiple channels in multiphase

output configuration, the heat generated is greatly decreased for each channel due to the fact that power loss is

proportional to square of current. The physical size of the output inductor shrinks significantly due to this heat

reduction. 图7-1 shows a block diagram of a single core.

Interleaving switching action of the 4-phase converter is shown in 图 7-2. The 4-phase converter switches each

channel 90° apart. As a result, the 4-phase converter has an effective ripple frequency four times greater than

the switching frequency of a one phase converter

PMOS

Current

Sense

Differential to Single-

Ended

FBP

FBN

+

-

VIN

POS

Current

Limit

œ

Slave

Phase

Control

Ramp

Generator

V_OUT

œ

Gate

Control

Error

Amp

+

SW

Loop

Comp

Voltage

Setting

Slew Rate

Control

NEG

Current

Limit

Power

Good

+

-

VDAC

Zero

Cross

Detect

NMOS

Current

Sense

Programmable

Parameters

Master

Interface

Control

Block

Slave

Interface

IADC

GND

图7-1. Detailed Block Diagram Showing One Core

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I_{L_TOT_4PH}

I_L0

I_L1

I_L2

I_L3

0

90

180

270

360

450

540

630

720

PWM₀

PWM₁

PWM₂

PWM₃

Switching Cycle 360º

0

90

180

270

360

450

540

630

720

Phase (Degrees)

A. Graph is not in scale and is for illustrative purposes only.

图7-2. Example of PWM Timings, Inductor Current Waveforms, and Total Output Current in 4-Phase

Configuration.

7.3.1.2 Multiphase Switcher Configurations

In single 4-phase output configuration the BUCK0 is master for the BUCK0, BUCK1, BUCK2, BUCK3 output.

In the multiphase configuration the control of the multiphase regulator settings is done using the control registers

of the master buck. The following slave registers are ignored:

• BUCKx_CTRL1 register, except EN_RDISx bit

• BUCKx_DELAY register

• interrupt bits related to the slave buck, except BUCKx_ILIM_INT

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7.3.1.3 Buck Converter Load-Current Measurement

Buck load current can be monitored through I²C registers. The monitored buck converter is selected with the

LOAD_CURRENT_BUCK_SELECT[1:0] bits in SEL_I_LOAD register. A write to this selection register starts a

current measurement sequence. The measurement sequence is 50 µs long, maximum. The LP875701-Q1

device can be configured to give out an interrupt (I_LOAD_READY bit in INT_TOP1 register) after the load

current measurement sequence is finished. Load current measurement interrupt can be masked with

I_LOAD_READY_MASK bit (TOP_MASK1 register). The measurement result can be read from registers

I_LOAD_1 and I_LOAD_2. Register I_LOAD_1 bits BUCK_LOAD_CURRENT[7:0] give out the LSB bits and

register I_LOAD_2 bits BUCK_LOAD_CURRENT[9:8] the MSB bits. The measurement result

BUCK_LOAD_CURRENT[9:0] LSB is 20 mA, and maximum value of the measurement corresponds to 20.46 A.

If the selected buck regulator is a master phase, the measured current is the total value of the master and slave

phases. If the selected buck regulator is a slave phase, the measured current is the output current of the

selected phase.

7.3.1.4 Spread-Spectrum Mode

Systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband

frequencies (the switching frequency and its harmonics). The usual solution to decrease noise coupling is to add

EMI filters and shields to the boards. The LP875701-Q1 device has register selectable spread-spectrum mode

which minimizes the need for output filters, ferrite beads, or chokes. In spread-spectrum mode, the switching

frequency varies around the center frequency, reducing the EMI emissions radiated by the converter and

associated passive components and PCB traces (see 图 7-3). This feature is available only when internal RC

oscillator is used (PLL_MODE[1:0] = 00 in PLL_CTRL register), and it is enabled with the EN_SPREAD_SPEC

bit (PIN_FUNCTION register), and it affects all the buck cores.

Frequency

Where a fixed-frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread-spectrum

architecture of the LP875701-Q1 spreads that energy over a large bandwidth.

图7-3. Spread-Spectrum Modulation

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7.3.2 Sync Clock Functionality

The LP875701-Q1 device contains a CLKIN input to synchronize switching clock of the buck regulator with the

external clock. The block diagram of the clocking and PLL module is shown in 图 7-4. Depending on the

PLL_MODE[1:0] bits (in PLL_CTRL register) and the external clock availability, the external clock is selected and

interrupt is generated as shown in 表 7-2. The interrupt can be masked with SYNC_CLK_MASK bit in

TOP_MASK1 register. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[4:0] bits (in

PLL_CTRL register) and it can be from 1 MHz to 24 MHz with 1-MHz steps. The external clock must be inside

accuracy limits (–30%/+10%) for valid clock detection.

The NO_SYNC_CLK interrupt (in INT_TOP1 register) is also generated in cases the external clock is expected

but it is not available. These cases are start-up (read OTP-to-STANDBY transition) when PLL_MODE[1:0] = 01

and regulator enable (STANDBY-to-ACTIVE transition) when PLL_MODE[1:0] = 10.

24-MHz

RC

Oscillator

Internal

24-MHz

clock

CLKIN

Detector

Divider

“EXT_CLK_

FREQ“

Clock Select

Logic

CLKIN

1MHz

24MHz

PLL

“PLL_MODE“

1MHz

Divider

24

图7-4. Clock and PLL Module

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表7-2. PLL Operation

DEVICE

OPERATION MODE

PLL AND CLOCK

DETECTOR STATE

INTERRUPT FOR

EXTERNAL CLOCK

PLL_MODE[1:0]

CLOCK

STANDBY

ACTIVE

0h

Disabled

No

Internal RC

Disabled

When external clock

appears or disappears

Automatic change to external

clock when available

STANDBY

1h

Enabled

When external clock

appears or disappears

Automatic change to external

clock when available

ACTIVE

STANDBY

ACTIVE

1h

2h

Enabled

Disabled

Enabled

No

Internal RC

When external clock

appears or disappears

Automatic change to external

clock when available

STANDBY

ACTIVE

3h

Reserved

7.3.3 Power-Up

The power-up sequence for the LP875701-Q1 is as follows:

• VANA (and VIN_Bx) reach minimum recommended level (V_VANA> VANA_UVLO).

• NRST is set to high level (or shorted to VANA). This initiates power-on-reset (POR), OTP reading and

enables the system I/O interface. The I²C host must wait at least 1.2 ms before applying signals to ENx pins

or writing or reading data to the LP875701-Q1.

• Device goes to the STANDBY-mode .

• The host can change the default register setting by I²C if needed.

• The regulator(s) can be enabled/disabled by ENx pin(s) and by I²C interface.

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7.3.4 Regulator Control

7.3.4.1 Enabling and Disabling Regulators

One or more regulators can be enabled when the device is in STANDBY or ACTIVE state. There are two ways

for enable and disable the regulators:

• Using EN_BUCK0 bit in BUCK0_CTRL1 register (EN_PIN_CTRL0 register bit is 0h)

• Using EN1, EN2, EN3 control pins (EN_BUCK0 bit is 1h AND EN_PIN_CTRL0 register bit is 1 in

BUCK0_CTRL1 register)

If the EN1, EN2, EN3 control pins are used for enable and disable then the control pin is selected with

BUCK0_EN_PIN_SELECT[1:0] bits (in BUCK0_CTRL1 register). The delay from the control signal rising edge to

enabling of the regulator is set by BUCK0_STARTUP_DELAY[3:0] bits and the delay from control signal falling

edge to disabling of the regulator is set by BUCK0_SHUTDOWN_DELAY[3:0] bits in BUCK0_DELAY register.

The delays are valid only for EN1, EN2, EN3 signal control. The control with EN_BUCK0 bit is immediate without

the delays.

The control of the regulator (with 0-ms delays) is shown in 表7-3.

备注

The control of the regulator cannot be changed from one ENx pin to a different ENx pin because the

control is ENx signal edge sensitive. The control from ENx pin to register bit and back to the original

ENx pin can be done during operation.

表7-3. Regulator Control

CONTROL

METHOD

EN_PIN_CTRL BUCK0_EN_PI

BUCKx

OUTPUT VOLTAGE

EN_BUCK0

EN1 PIN

EN2 PIN

EN3 PIN

0

Don't Care

0h

N_SELECT[1:0]

Enable and disable

control with

EN_BUCK0 bit

0h

1h

Don't Care

Disabled

1.0 Volt

Don't Care

Enable and disable

control with EN1

1h

0h

Low

Don't Care

Disabled

1.0 Volt

High

Enable and disable

control with EN2

1h

Don't Care

Low

Don't Care

Disabled

1.0 Volt

High

Enable and disable

control with EN3

1h

2h

Don't Care

Low

Disabled

1.0 Volt

High

The regulator is enabled by the ENx pin or by I²C writing as shown in 图 7-5. The soft-start circuit limits the in-

rush current during start-up. When the output voltage rises to 0.35-V level, the output voltage becomes slew-rate

controlled . If there is a short circuit at the output and the output voltage does not increase above 0.35-V level in

1 ms, the regulator is disabled, and interrupt is set. When the output voltage reaches the Power-Good threshold

level the BUCKx_PG_INT interrupt flag (in INT_BUCK_x register) is set. The Power-Good interrupt flag can be

masked using BUCKx_PG_MASK bit (in BUCKx_MASK register).

The ENx input pins have integrated pulldown resistors. The pulldown resistors are enabled by default, and the

host can disable those with ENx_PD bits (in CONFIG register).

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Voltage decrease because of load

Voltage

No new Powergood interrupt

1 Volt

Powergood

Ramp 3.8 mV/ms

0.6V

0.35V

Time

Resistive pull-down

(if enabled)

Soft start

Enable

BUCK_x_STAT(BUCKx_STAT)

BUCK_x_STAT(BUCKx_PG_STAT)

INT_BUCK_x(BUCKx_PG_INT)

nINT

0

1

0

1

0

1

0

Powergood

interrupt

Host clears

interrupt

图7-5. Regulator Enable and Disable

7.3.5 Enable and Disable Sequences

The LP875701-Q1 device supports start-up and shutdown sequencing with programmable delay for the

regulator output using one EN1, EN2, or EN3 control signal. The regulator is selected for delayed control with:

• EN_BUCK0 = 1 (in BUCK0_CTRL1 register)

• EN_PIN_CTRL0 = 1 (in BUCK0_CTRL1 register)

• The ENABLE pin for control is selected with BUCK0_EN_PIN_SELECT[1:0] (in BUCK0_CTRL1 register)

• The delay from rising edge of ENx signal to the regulator enable is set by BUCK0_STARTUP_DELAY[3:0]

bits (in BUCK0_DELAY register) and

• The delay from falling edge of ENx signal to the regulator disable is set by BUCK0_SHUTDOWN_DELAY[3:0]

bits (in BUCK0_DELAY register)

There are four time steps available for start-up and shutdown sequences. The delay times are selected with

DOUBLE_DELAY bit in CONFIG register and HALF_DELAY bit in PGOOD_CTRL2 register as shown in 表7-4.

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表7-4. Start-Up and Shutdown Delays

0_STARTUP_DELAY or

0_SHUTDOWN_DELAY

DOUBLE_DELAY = 0h

DOUBLE_DELAY = 1h

DOUBLE_DELAY = 0h

DOUBLE_DELAY = 1h

HALF_DELAY = 0h

HALF_DELAY = 1h

HALF_DELAY = 0h

0h

1h

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

dh

Eh

Fh

0 ms

1 ms

0 ms

0.32 ms

0.64 ms

0.96 ms

1.28 ms

1.6 ms

0.64 ms

1.28 ms

1.92 ms

2.56 ms

3.2 ms

2 ms

4 ms

3 ms

6 ms

4 ms

8 ms

5 ms

10 ms

12 ms

14 ms

16 ms

18 ms

20 ms

22 ms

24 ms

26 ms

28 ms

30 ms

1.92 ms

2.24 ms

2.56 ms

2.88 ms

3.2 ms

3.84 ms

4.48 ms

5.12 ms

5.76 ms

6.4 ms

6 ms

7 ms

8 ms

9 ms

10 ms

11 ms

12 ms

13 ms

14 ms

15 ms

3.52 ms

3.84 ms

4.16 ms

4.48 ms

4.8 ms

7.04 ms

7.68 ms

8.32 ms

8.96 ms

9.6 ms

An example of start-up and shutdown sequences is shown in 图 7-6 and 图 7-7. The start-up and shutdown

delays for the master buck regulator BUCK0 regulator is 1 ms and 4 ms . The delay settings are used only for

enable/disable control with EN1, EN2, EN3 signals

ENx

EN_BUCK0

1ms

4ms

图7-6. Typical Start-Up and Shutdown Sequencing

ENx

Startup cntr

Shutdown cntr

EN_BUCK0

0

1

0

1

2

3

4

5

6

0

2

0

1

0

1

0

1

2

3

4

5

1ms

4ms

图7-7. Start-Up and Shutdown Sequencing With Short ENx Low and High Periods

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7.3.6 Device Reset Scenarios

There are three reset methods implemented on the LP875701-Q1:

• Software reset with SW_RESET register bit (in RESET register)

• POR from rising edge of NRST signal

• Undervoltage lockout (UVLO) reset from VANA supply

A SW-reset occurs when SW_RESET bit is written 1. The bit is automatically cleared after writing. This event

disables all the regulators immediately, resets all the register bits to the default values and OTP bits are loaded

(see 图7-11). I²C interface is not reset during software reset. The host must wait at least 1.2 ms after writing SW

reset until making a new I²C read or write to the device.

If VANA supply voltage falls below UVLO threshold level or NRST signal is set low then all the regulators are

disabled immediately, and all the register bits are reset to the default values. When the VANA supply voltage

rises above UVLO threshold level AND NRST signal rises above threshold level an internal power-on reset

(POR) occurs. OTP bits are loaded to the registers and a start-up is initiated according to the register settings.

The host must wait at least 1.2 ms after POR until reading or writing to I²C interface.

7.3.7 Diagnosis and Protection Features

The LP875701-Q1 is capable of providing four levels of protection features:

• Information of valid regulator output voltage which sets interrupt or PGOOD signal;

• Warnings for diagnosis which sets interrupt;

• Protection events which are disabling the regulators affected; and

• Faults which are causing the device to shutdown.

The LP875701-Q1 sets the flag bits indicating what protection or warning conditions have occurred, and the

nINT pin is pulled low. nINT is released again after a clear of flags is complete. The nINT signal stays low until all

the pending interrupts are cleared.

When a fault is detected, it is indicated by a RESET_REG interrupt flag (in INT2_TOP register) after next start-

up.

表7-5. Summary of Interrupt Signals

INTERRUPT REGISTER AND

RECOVERY/INTERRUPT

CLEAR

EVENT

RESULT

INTERRUPT MASK

STATUS BIT

BIT

Write 1 to BUCKx_ILIM_INT bit

Interrupt is not cleared if

current limit is active

Current limit triggered

(20-µs debounce)

INT_BUCKx = 1

BUCKx_ILIM_INT = 1

Interrupt

BUCKx_ILIM_MASK

BUCKx_ILIM_STAT

Short circuit (V_VOUT

0.35 V at 1 ms after

enable) or overload

(V_VOUTdecreasing

below 0.35 V during

operation, 1 ms

<

Regulator disable and

interrupt

INT_BUCKx = 1

BUCKx_SC_INT = 1

N/A

Write 1 to BUCKx_SC_INT bit

debounce)

Write 1 to TDIE_WARN bit

Interrupt is not cleared if

temperature is above thermal

warning level

Thermal warning

Interrupt

TDIE_WARN = 1

TDIE_WARN_MASK

TDIE_WARN_STAT

TDIE_SD_STAT

Write 1 to TDIE_SD bit

Interrupt is not cleared if

temperature is above thermal

shutdown level

All regulators disabled

and Output GPIOx set to TDIE_SD = 1

low and interrupt

Thermal shutdown

VANA overvoltage

N/A

Write 1 to INT_OVP bit

Interrupt is not cleared if VANA

voltage is above VANA OVP

level

All regulators disabled

and Output GPIOx set to INT_OVP

low and interrupt

N/A

OVP_STAT

(VANA_OVP

)

Power Good, output

voltage reaches the

programmed value

INT_BUCKx = 1

Interrupt

BUCKx_PG_MASK

BUCKx_PG_STAT

Write 1 to BUCKx_PG_INT bit

BUCKx_PG_INT = 1

GPIO

Interrupt

INT_GPIO

GPIO_MASK

GPIO_IN register

SYNC_CLK_STAT

Write 1 to INT_GPIO bit

External clock appears

or disappears

NO_SYNC_CLK⁽¹⁾

SYNC_CLK_MASK

Write 1 to NO_SYNC_CLK bit

Load current

measurement ready

Interrupt

I_LOAD_READY = 1

I_LOAD_READY_MASK

N/A

Write 1 to I_LOAD_READY bit

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表7-5. Summary of Interrupt Signals (continued)

INTERRUPT REGISTER AND

RECOVERY/INTERRUPT

CLEAR

EVENT

RESULT

INTERRUPT MASK

STATUS BIT

BIT

Device ready for

operation, registers reset

to default values and

interrupt

Start-Up (NRST rising

edge)

RESET_REG = 1

RESET_REG_MASK

N/A

Write 1 to RESET_REG bit

Immediate shutdown

followed by power up,

registers reset to default

values and interrupt

Glitch on supply voltage

and UVLO triggered

(VANA falling and rising)

RESET_REG_MASK

Immediate shutdown

followed by power up,

registers reset to default

values and interrupt

Software requested

reset

(1) Interrupt is generated during clock detector operation and in case clock is not available when clock detector is enabled.

7.3.7.1 Power-Good Information (PGOOD pin)

In addition to the interrupt based indication of current limit and Power-Good level the LP875701-Q1 device

supports the indication with PGOOD signal. Either voltage and current monitoring or a voltage monitoring only

can be selected for PGOOD indication. This selection is individual for all buck regulators (select master phase

for multiphase regulator) and is set by PGx_SEL[1:0] bits (in PGOOD_CTRL1 register). When both voltage and

current are monitored, PGOOD signal active indicates that regulator output is inside the Power-Good voltage

window and that load current is below I_{LIM FWD}. If only voltage is monitored, then the current monitoring is

ignored for the PGOOD signal. When a regulator is disabled, the monitoring is automatically masked to prevent it

forcing PGOOD inactive. This allows connecting PGOOD signals from various devices together when open-drain

outputs are used. When regulator voltage is transitioning from one target voltage to another, the voltage

monitoring PGOOD signal is set inactive. The monitoring from all the output rails are combined, and PGOOD is

active only if all the sources shows active status. The status from all the voltage rails are summarized in 表7-6.

If the PGOOD signal is inactive or it changes the state to inactive, the source for the state can be read from

PGOOD_FLT register. During reading all the PGx_FLT bit are cleared that are not driving the PGOOD inactive.

When PGOOD signal goes active, the host must read the PGOOD_FLT register to clear all the bits. The PGOOD

signal follows the status of all the monitored outputs.

The PGOOD signal can be also configured so that it stays in the inactive state even when the monitored outputs

are valid but there are PGx_FLT bits pending clearance in PGOOD_FLT register. This mode of operation is

selected by setting EN_PGFLT_STAT bit to 1 (in PGOOD_CTRL2 register).

The type of output voltage monitoring for PGOOD signal is selected by PGOOD_WINDOW bit (in

PGOOD_CTRL2 register). If the bit is 0, only undervoltage is monitored; if the bit is 1, both undervoltage and

overvoltage are monitored.

The polarity and the output type (push-pull or open-drain) are selected by PGOOD_POL and PGOOD_OD bits in

PGOOD_CTRL2 register.

The filtering time for invalid output voltage is always typically 7 µs and for valid output voltage the filtering time is

selected with PGOOD_SET_DELAY bit (in PGOOD_CTRL2 register). The Power-Good waveforms are shown in

图7-9.

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ILIM

Buck0

Buck1

Buck2

Buck3

MUX

Power Good

PG0_SEL[1:0]

ILIM

MUX

Power Good

PG1_SEL[1:0]

PGOOD

ILIM

MUX

Power Good

PG2_SEL[1:0]

ILIM

MUX

Power Good

PG3_SEL[1:0]

图7-8. PGOOD Block Diagram

表7-6. PGOOD Operation

STATUS / USE CASE

CONDITION

INPUT TO PGOOD SIGNAL

PGx_SEL = 00 (in PGOOD_CTRL1

register)

Buck not selected for PGOOD monitoring

Buck disabled

Active

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表7-6. PGOOD Operation (continued)

STATUS / USE CASE

CONDITION

INPUT TO PGOOD SIGNAL

BUCK SELECTED FOR PGOOD MONITORING

Buck start-up delay

Inactive

Buck soft start

V_OUT< 0.35 V

Buck voltage ramp-up

0.35 V < V_OUT< V_SET

Output voltage within window limits after

start-up

Must be inside limits longer than debounce

time

Active

Output voltage inside voltage window and

current limit active

Current limit active longer than debounce

time

Active (if only voltage monitoring selected)

Inactive (if also current monitoring selected)

Output voltage spikes (overvoltage or

undervoltage)

If spikes are outside voltage window longer

than debounce time

Inactive

Active

Voltage setting change, output voltage

ramp

Output voltage within window limits after

voltage change

Must be inside limits longer than debounce

time

Buck shutdown delay

Active

Buck output voltage ramp down

Buck disabled by thermal shutdown and

interrupt pending

Inactive

Buck disabled by overvoltage and interrupt

pending

Buck disabled by short-circuit detection

and interrupt pending

Voltage

Powergood window

1 Volt

Time

ENx

7us/11ms

PGOOD_SET_DELAY

PGOOD

图7-9. PGOOD Waveforms (PGOOD_POL=0)

7.3.7.2 Warnings for Diagnosis (Interrupt)

7.3.7.2.1 Output Power Limit

The regulators have output peak current limits. The peak current limits are described in Electrical Characteristic

Table. If the load current is increased so that the current limit is triggered, the regulator continues to regulate to

the limit current level (current peak regulation, peak on each switching cycle). The voltage may decrease if the

load current is higher than the average output current. If the current regulation continues for 20 µs, the

LP875701-Q1 device sets the BUCKx_ILIM_INT bit (in INT_BUCKx register) and pulls the nINT pin low. The

host processor can read BUCKx_ILIM_STAT bits (in BUCKx_STAT register) to see if the regulator is still in peak

current regulation mode.

If the load is so high that the output voltage decreases below a 350-mV level, the LP875701-Q1 device disables

the regulator and sets the BUCKx_SC_INT bit (in INT_BUCKx register). In addition the BUCKx_STAT bit (in

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BUCKx_STAT register) is set to 0. The interrupt is cleared when the host processor writes 1 to BUCKx_SC_INT

bit. The overload situation is shown in 图7-10.

Regulator

disabled by digital

New start-up if

enable is valid

Voltage

VOUTx

350 mV

Resistive

pulldown

1 ms

Time

Current

ILIMx

Time

20 ms

INT_BUCKx

(BUCKx_ILIM_INT)

0

1

0

INT_BUCK

(BUCKx_SC_INT)

1

0

1

BUCKx_STAT

(BUCKx_STAT)

nINT

Host clearing the interrupt by writing to flags

图7-10. Overload Situation

7.3.7.2.2 Thermal Warning

The LP875701-Q1 device includes a monitoring feature against overtemperature by setting an interrupt for host

processor. The threshold level of the thermal warning is selected with TDIE_WARN_LEVEL bit (in CONFIG

register).

If the LP875701-Q1 device temperature increases above thermal warning level the device sets TDIE_WARN bit

(in INT_TOP1 register) and pulls nINT pin low. The status of the thermal warning can be read from

TDIE_WARN_STAT bit (in TOP_STAT register), and the interrupt is cleared by writing 1 to TDIE_WARN bit.

7.3.7.3 Protection (Regulator Disable)

If the regulator is disabled because of protection or fault (short-circuit protection, overload protection, thermal

shutdown, overvoltage protection, or UVLO), the output power FETs are set to high-impedance mode, and the

output pulldown resistor is enabled (if enabled with EN_RDISx bits in BUCKx_CTRL1 register). The turnoff time

of the output voltage is defined by the output capacitance, load current, and the resistance of the integrated

pulldown resistor. The pulldown resistors are active as long as VANA voltage is above approximately a 1.2-V

level.

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7.3.7.3.1 Short-Circuit and Overload Protection

A short-circuit protection feature lets the LP875701-Q1 device protect itself and external components against

short circuit at the output or against overload during start-up. The fault threshold is 350 mV, the protection is

triggered, and the regulator is disabled if the output voltage is below the threshold level 1 ms after the regulator

is enabled.

In a similar way the overload situation is protected during normal operation. If the voltage on the feedback pin of

the regulator falls to less than 0.35 V and stays lower the threshold level for 1 ms, the regulator is disabled.

In the short-circuit and overload situations the BUCKx_SC_INT (in INT_BUCKx register) and the INT_BUCKx

bits (in INT_TOP1 register) are set to 1, the BUCKx_STAT bit (in BUCKx_STAT register) is set to 0, and the nINT

signal is pulled low. The host processor clears the interrupt by writing 1 to the BUCKx_SC_INT bit. After clearing

the interrupt the regulator makes a new start-up attempt if the regulator is in enabled state.

7.3.7.3.2 Overvoltage Protection

The LP875701-Q1 device monitors the input voltage from the VANA pin in standby and active operation modes.

If the input voltage rises above VANA_OVPvoltage level, all the regulators are disabled, pulldown resistors

discharge the output voltages (if EN_RDISx = 1 in BUCKx_CTRL1 register), GPIOs that are configured to

outputs are set to logic low level, nINT signal is pulled low, INT_OVP bit (in INT_TOP1 register) is set to 1, and

BUCKx_STAT bits (in BUCK_x_STAT register) are set to 0. The host processor clears the interrupt by writing 1

to the INT_OVP bit. If the input voltage is above the overvoltage detection level the interrupt is not cleared. The

host can read the status of the overvoltage from the OVP_STAT bit (in TOP_STAT register). Regulators cannot

be enabled as long as the input voltage is above overvoltage detection level or the overvoltage interrupt is

pending.

7.3.7.3.3 Thermal Shutdown

The LP875701-Q1 has an overtemperature protection function that operates to protect the device from short-

term misuse and overload conditions. When the junction temperature exceeds around 150°C, the regulators are

disabled, the TDIE_SD bit (in INT_TOP1 register) is set to 1, the nINT signal is pulled low, and the device goes

to the STANDBY state. The nINT pin is cleared by writing 1h to the TDIE_SD bit. If the temperature is above

thermal shutdown level the interrupt is not cleared. The host can read the status of the thermal shutdown from

the TDIE_SD_STAT bit (in TOP_STAT register). Regulators cannot be enabled as long as the junction

temperature is above thermal shutdown level or the thermal shutdown interrupt is pending.

7.3.7.4 Fault (Power Down)

7.3.7.4.1 Undervoltage Lockout

When the input voltage falls below VANA_UVLOat the VANA pin, the buck converters are disabled immediately,

and the output capacitors are discharged using the pulldown resistor, and the LP875701-Q1 device goes to the

SHUTDOWN state. When the VANA voltage is greater than the UVLO threshold level and NRST signal is high,

the device powers up to STANDBY state.

If the reset interrupt is unmasked by default (RESET_REG_MASK = 0 in TOP_MASK2 register) the

RESET_REG interrupt (in INT_TOP2 register) indicates that the device has been in SHUTDOWN. The host

processor must clear the interrupt by writing 1 to the RESET_REG bit. If the host processor reads the

RESET_REG flag after detecting an nINT low signal, it knows that the input supply voltage has been below

UVLO level (or the host has requested reset), and the registers are reset to default values.

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7.3.8 GPIO Signal Operation

The LP875701-Q1 device supports up to 3 GPIO signals. The GPIO signals are multiplexed with enable signals.

The selection between enable and GPIO function is set with GPIOx_SEL bits in PIN_FUNCTION register. The

GPIOs are mapped to EN signals so that:

• EN1 is multiplexed with GPIO1

• EN2 is multiplexed with GPIO2

• EN3 is multiplexed with GPIO3

When the pin is selected for GPIO function, additional bits defines how the GPIO operates:

• GPIOx_DIR defines the direction of the GPIO, input or output (GPIO_CONFIG register)

• GPIOx_OD defines the type of the output when the GPIO is set to output, either push-pull with VANA level or

open-drain (GPIO_CONFIG register)

When the GPIOx is defined as output, the logic level of the pin is set by GPIOx_OUT bit (in GPIO_OUT register).

When the GPIOx is defined as input, the logic level of the pin can be read from GPIOx_IN bit (in GPIO_IN

register).

The control of the GPIOs configured to outputs can be included to start-up and shutdown sequences. The GPIO

control for a sequence with ENx signal is selected by EN_PIN_CTRL_GPIOx and EN_PIN_SELECT_GPIOx bits

(in

PIN_FUNCTION

register).

The

delays

during

start-up

and

shutdown

are

set

by

GPIOx_STARTUP_DELAY[3:0] and GPIOx_SHUTDOWN_DELAY[3:0] bits (in GPIOx_DELAY register) in the

same way as control of the regulators.

The GPIOx signals have a selectable pulldown resistor. The pulldown resistors are selected by ENx_PD bits (in

CONFIG register).

备注

The control of the GPIOx pin cannot be changed from one ENx pin to a different ENx pin because the

control is ENx signal edge sensitive. The control from ENx pin to register bit and back to the original

ENx pin can be done during operation.

7.3.9 Digital Signal Filtering

The digital signals have a debounce filtering. The signal/supply is sampled with a clock signal and a counter.

This results as an accuracy of one clock period for the debounce window.

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表7-7. Digital Signal Filtering

FALLING EDGE DEBOUNCE

TIME

EVENT

SIGNAL/SUPPLY

RISING EDGE DEBOUNCE TIME

Enable and disable for BUCKx

VANA UVLO

EN1

EN2

3 µs ⁽¹⁾

EN3

3 µs ⁽¹⁾

VANA

20 µs (VANA voltage rising)

Immediate (VANA voltage falling)

VANA overvoltage

VANA

20 µs (VANA voltage rising)

20 µs (VANA voltage falling)

Thermal warning

TDIE_WARN

TDIE_SD

VOUTx_ILIM

20 µs

Thermal shutdown

Current limit

FB_B0, FB_B1, FB_B2,

FB_F3

Overload

1 ms

20 µs

FB_B0, FB_B1, FB_B2,

FB_F3

Power-good interrupt

20 µs

PGOOD pin (voltage

monitoring)

PGOOD / FB_B0, FB_B1,

FB_B2, FB_F3

4-8 µs (start-up debounce time during

start-up)

4 to 8 µs

20 µs

PGOOD pin (current

monitoring)

PGOOD

20 µs

(1) No glitch filtering, only synchronization.

7.4 Device Functional Modes

7.4.1 Modes of Operation

SHUTDOWN: The NRST voltage is below threshold level. All switch, reference, control, and bias circuitry of the

LP875701-Q1 device are turned off.

READ OTP: The primary supply voltage VANA is above VANA_UVLOlevel and NRST voltage is above

threshold level. The regulators are disabled and the reference and bias circuitry of the

LP875701-Q1 are enabled. The OTP bits are loaded to registers.

STANDBY:

The primary supply voltage VANA is above VANA_UVLOlevel and NRST voltage is above

threshold level. The regulators are disabled and the reference, control and bias circuitry of the

LP875701-Q1 are enabled. All registers can be read or written by the host processor via the

system serial interface. The regulators can be enabled if needed.

ACTIVE:

The primary supply voltage VANA is above VANA_UVLOlevel and NRST voltage is above

threshold level. At least one regulated DC/DC converter is enabled. All registers can be read or

written by the host processor via the system serial interface.

The operating modes and transitions between the modes are shown in 图7-11.

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SHUTDOWN

NRST low

OR

V_VANA< VANA_UVLO

NRST high

AND

V_VANA> VANA_UVLO

From any state except

SHUTDOWN

READ

OTP

REGISTER

RESET

STANDBY

I²C RESET

REGULATOR

ENABLED

REGULATORS

DISABLED

ACTIVE

图7-11. Device Operation Modes

7.5 Programming

7.5.1 I²C-Compatible Interface

The I²C-compatible synchronous serial interface provides access to the programmable functions and registers

on the device. This protocol uses a two-wire interface for bidirectional communications between the devices

connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). Each

device on the bus is assigned a unique address and acts as either a master or a slave depending on whether it

generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor placed

somewhere on the line and stays HIGH even when the bus is idle. Note: CLK pin is not used for serial bus data

transfer. The LP875701-Q1 supports standard mode (100 kHz), fast mode (400 kHz), fast mode+ (1 MHz), and

high-speed mode (3.4 MHz).

7.5.1.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the

state of the data line can only be changed when clock signal is LOW.

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SCL

SDA

data

change

allowed

data

change

allowed

data

change

allowed

data

valid

data

valid

图7-12. Data Validity Diagram

7.5.1.2 Start and Stop Conditions

The LP875701-Q1 is controlled through the an I²C-compatible interface. START and STOP conditions classify

the beginning and end of the I²C session. A START condition is defined as SDA transitions from HIGH to LOW

while SCL is HIGH. A STOP condition is defined as SDA transition from LOW to HIGH while SCL is HIGH. The

I²C master always generates the START and STOP conditions.

SDA

SCL

S

P

START

STOP

Condition

图7-13. Start and Stop Sequences

The I²C bus is considered busy after a START condition and free after a STOP condition. During data

transmission the I²C master can generate repeated START conditions. A START and a repeated START

condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock

signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. 图 7-14 shows the SDA

and SCL signal timing for the I²C-compatible bus.

t_BUF

SDA

t_HD;STA

t_rCL

t_fDA

t_rDA

t_SP

t_LOW

t_fCL

SCL

t_HD;STA

t_SU;STA

t_SU;STO

t_HIGH

t_HD;DAT

S

t_SU;DAT

S

RS

P

START

REPEATED

START

STOP

START

图7-14. I²C-Compatible Timing

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7.5.1.3 Transferring Data

Each byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP875701-Q1

pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP875701-Q1 generates an

acknowledge after each byte has been received.

There is one exception to the acknowledge after each byte rule. When the master is the receiver, it must indicate

to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out of the

slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the

SDA line is not pulled down.

备注

If the NRST signal is low during I²C communication the LP875701-Q1 device does not drive SDA line.

The ACK signal and data transfer to the master is disabled at that time.

After the START condition, the bus master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE and a 1

indicates a READ. The second byte selects the register to which the data will be written. The third byte contains

data to write to the selected register.

ACK from slave

START MSB Chip Address LSB

W

ACK MSB Register Address LSB ACK

MSB Data LSB

ACK STOP

SCL

SDA

START

id = 0x60

W

ACK

address = 0x40

ACK

address 0x40 data

ACK STOP

图7-15. Write Cycle (w = write; SDA = 0), id = Device Address = 0x60 for LP875701-Q1

ACK from slave

ACK from slave REPEATED START

ACK from slave Data from slave NACK from master

START MSB Chip Address LSB

W

MSB Register Address LSB

RS

MSB Chip Address LSB

R

MSB Data LSB

STOP

SCL

SDA

START

ACK

NACK

STOP

id = 0x60

W

address = 0x3F

RS

id = 0x60

R

address 0x3F data

When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.

图7-16. Read Cycle ( r = read; SDA = 1), id = Device Address = 0x60 for LP875701-Q1

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7.5.1.4 I²C-Compatible Chip Address

备注

The device address for the LP875701-Q1 is defined in the Technical Reference Manual (TRM).

After the START condition, the I²C master sends the 7-bit address followed by an eighth bit, read or write (R/W).

R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The second byte following the device address

selects the register address to which the data will be written. The third byte contains the data for the selected

register.

MSB

LSB

1

Bit 7

1

Bit 6

0

Bit 5

0

Bit 4

0

Bit 3

0

Bit 2

0

Bit 1

R/W

Bit 0

I²C Slave Address (chip address)

A. Here device address is 1100000Bin = 60Hex.

图7-17. Example Device Address

7.5.1.5 Auto-Increment Feature

The auto-increment feature allows writing several consecutive registers within one transmission. Each time an 8-

bit word is sent to the device, the internal address index counter is incremented by one and the next register is

written. 表 7-8 below shows writing sequence to two consecutive registers. Note that auto increment feature

does not work for read.

表7-8. Auto-Increment Example

DEVICE

ADDRESS =

0x60

MASTER

ACTION

REGISTER

ADDRESS

START

WRITE

DATA

STOP

LP875701-Q1

ACK

7.6 Register Maps

7.6.1 Register Descriptions

The LP875701-Q1 is controlled by a set of registers through the I²C-compatible interface. The device registers,

their addresses, and their abbreviations are listed in 表 7-9. A more detailed description is given in 节 7.6.1.2

through 节7.6.1.30.

备注

This register map describes the default values for bits which are not read from OTP memory. The

orderable code and the default register bit values are defined in part number specific Technical

Reference Manual.

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7.6.1.1 DEV_REV

Address: 0x00

D7

D6

D5

D4

D3

D2

METAL_LAYER[3:0]

Description

D1

D0

DEVICE_ID[1:0]

ALL_LAYER[1:0]

Bits

7:6

Field

Type

R

Default

DEVICE_ID[1:0]

ALL_LAYER[1:0]

X

Device specific ID code.

5:4

R

1h

Shows the all layer version of the device:

0h = First all layer version (ES1.0 silicon)

1h = Second all layer version (ES2.x silicon)

2h = Third all layer version

3h = Fourth all layer version

3:0

METAL_LAYER

[3:0]

R

2h

Shows the metal layer version of the device:

0h = All layer version

1h = First metal layer spin

Fh = 15th metal layer spin

7.6.1.2 OTP_REV

Address: 0x01

D7

D6

D5

D4

D3

D2

D1

D0

OTP_ID[7:0]

Bits

Field

Type

Default

Description

7:0

OTP_ID[7:0]

R

X

Identification code of the OTP EPROM version

7.6.1.3 BUCK0_CTRL1

Address: 0x02

D7

D6

D5

D4

D3

D2

D1

D0

EN_BUCK0

EN_PIN_CTRL BUCK0_EN_PIN_SELECT[1:0]

0

Reserved

EN_RDIS0

Reserved

Bits

Field

Type

Default

Description

7

EN_BUCK0

R/W

X

This bit enables the BUCK0 regulator

0h = BUCK0 regulator is disabled

1h = BUCK0 regulator is enabled

6

EN_PIN_CTRL0

R/W

X

This bit enables the EN1, EN2, EN3 pin control for the BUCK0 regulator

0h = Only the EN_BUCK0 bit controls the BUCK0 regulator

1h = EN_BUCK0 bit AND ENx pin control the BUCK0 regulator

5:4 BUCK0_EN_PIN_S

ELECT[1:0]

This bit enables the EN1, EN2, EN3 pin control for the BUCK0 regulator

0h = EN_BUCK0 bit AND EN1 pin control BUCK0

1h = EN_BUCK0 bit AND EN2 pin control BUCK0

2h = EN_BUCK0 bit AND EN3 pin control BUCK0

3h = Reserved

3

2

Reserved

R/W

0h

1h

Reserved, do not use

EN_RDIS0

This bit enables the output of the discharge resistor when the BUCK0 regulator is

disabled

0h = Discharge resistor disabled

1h = Discharge resistor enabled

1

0

Reserved

R/W

X

Reserved, do not use

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7.6.1.4 BUCK0_DELAY

Address: 0x12

D7

D6

D5

D4

D3

D2

D1

D0

BUCK0_SHUTDOWN_DELAY[3:0]

BUCK0_STARTUP_DELAY[3:0]

Bits

Field

Type

Default

Description

7:4 BUCK0_SHUTDOW

N_DELAY[3:0]

R/W

X

Shutdown delay of the BUCK0 regulator from the falling edge of the ENx signal (the

DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is

set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up

and Shutdown Delays table.

0h = 0 ms

1h = 1 ms

Fh = 15 ms

3:0 BUCK0_STARTUP_

DELAY[3:0]

R/W

X

Start-Up delay the of the BUCK0 regulator from the rising edge of the ENx signal (the

DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is

set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up

and Shutdown Delays table.

0h = 0 ms

1h = 1 ms

Fh = 15 ms

7.6.1.5 GPIO2_DELAY

Address: 0x16

D7

D6

D5

D4

D3

D2

D1

D0

GPIO2_SHUTDOWN_DELAY[3:0]

GPIO2_STARTUP_DELAY[3:0]

Bits

Field

Type

Default

Description

7:4 GPIO2_SHUTDOW

N_DELAY[3:0]

R/W

X

Delay for the GPIO2 falling edge from the falling edge of the ENx signal (the

DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is

set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up

and Shutdown Delays table.

0h = 0 ms

1h = 1 ms

Fh = 15 ms

3:0 GPIO2_STARTUP_

DELAY[3:0]

R/W

X

Delay for the GPIO2 rising edge from the rising edge of the ENx signal (the

DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is

set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up

and Shutdown Delays table.

0h = 0 ms

1h = 1 ms

Fh = 15 ms

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7.6.1.6 GPIO3_DELAY

Address: 0x17

D7

D6

D5

D4

D3

D2

D1

D0

GPIO3_SHUTDOWN_DELAY[3:0]

GPIO3_STARTUP_DELAY[3:0]

Bits

Field

Type

Default

Description

7:4 GPIO3_SHUTDOW

N_DELAY[3:0]

R/W

X

Delay for the GPIO3 falling edge from the falling edge of the ENx signal (the

DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is

set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up

and Shutdown Delays table.

0h = 0 ms

1h = 1 ms

Fh = 15 ms

3:0 GPIO3_STARTUP_

DELAY[3:0]

R/W

X

Delay for GPIO3 rising edge from rising edge of ENx signal (the DOUBLE_DELAY bit

is set to 0h in the CONFIG register and the HALF_DELAY bit is set to 0h in the

PGOOD_CTRL2 register). For other delay options, see the Start-Up and Shutdown

Delays table.

0h = 0 ms

1h = 1 ms

. Fh = 15 ms

7.6.1.7 RESET

Address: 0x18

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

SW_RESET

Bits

7:1

0

Field

Type

R/W

Default

0h

Description

Reserved

SW_RESET

0h

Software commanded reset. When this bit is written to 1h, the registers are reset to

the default values, OTP memory is read, and the I²C interface is reset.

The bit is automatically cleared.

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7.6.1.8 CONFIG

Address: 0x19

D7

D6

D5

D4

D3

D2

D1

D0

DOUBLE_DEL

AY

CLKIN_PD

Reserved

EN3_PD

TDIE_WARN_

LEVEL

EN2_PD

EN1_PD

Reserved

Bits

Field

DOUBLE_DELAY

Type

Default

Description

7

R/W

X

Start-Up and shutdown delays from the ENx signals

0h = 0 ms to 15 ms with 1-ms steps

1h = 0 ms to 30 ms with 2-ms steps

6

CLKIN_PD

R/W

X

This bit selects the pulldown resistor on the CLKIN input pin.

0h = Pulldown resistor is disabled

1h = Pulldown resistor is enabled

5

4

Reserved

EN3_PD

R/W

0h

X

This bit selects the pulldown resistor on the EN3 (GPIO3) input pin.

0h = Pulldown resistor is disabled

1h = Pulldown resistor is enabled

3

2

1

0

TDIE_WARN_LEVE

L

R/W

X

Thermal warning threshold level

0h = 125°C

1h = 137°C

EN2_PD

EN1_PD

Reserved

This bit selects the pulldown resistor on the EN2 (GPIO2) input pin.

0h = Pulldown resistor is disabled

1h = Pulldown resistor is enabled

X

This bit selects the pulldown resistor on the EN1 (GPIO1) input pin.

0h = Pulldown resistor is disabled

1h = Pulldown resistor is enabled

0h

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7.6.1.9 INT_TOP1

Address: 0x1A

D7

D6

INT_BUCK23

D5

D4

D3

D2

D1

D0

Reserved

INT_BUCK01 NO_SYNC_CL

K

TDIE_SD

TDIE_WARN

INT_OVP

I_LOAD_READ

Y

Bits

Field

Type

Default

0h

Description

7

6

Reserved

R/W

R

INT_BUCK23

0h

Interrupt indicating that the output of the BUCK3 regulator,BUCK2 regulator, or both

regulators has a pending interrupt. The reason for the interrupt is indicated in the

INT_BUCK_2_3 register.

This bit is cleared automatically when the INT_BUCK_2_3 register is cleared to 0x00.

5

INT_BUCK01

R

0h

Interrupt indicating that the output of the BUCK1 regulator, BUCK0 regulator, or both

regulators has a pending interrupt. The reason for the interrupt is indicated in the

INT_BUCK_0_1 register.

This bit is cleared automatically when the INT_BUCK_0_1 register is cleared to 0x00.

4

3

NO_SYNC_CLK

TDIE_SD

R/W1C

0h

Latched status bit indicating that the external clock is not valid.

Write this bit to 1h to clear the interrupt.

Latched status bit indicating that the die junction temperature is greater than the

thermal shutdown level. The regulators are disabled if previously enabled. The

regulators cannot be enabled if this bit is active. The actual status of the thermal

warning condition is indicated by the TDIE_SD_STAT bit in the TOP_STAT register.

Write this bit to 1h to clear the interrupt.

2

1

0

TDIE_WARN

INT_OVP

R/W1C

0h

Latched status bit indicating that the die junction temperature is greater than the

thermal warning level. The actual status of the thermal warning condition is indicated

by the TDIE_WARN_STAT bit in the TOP_STAT register.

Write this bit to 1h to clear the interrupt.

Latched status bit indicating that the input voltage is greater than the overvoltage-

detection level. The actual status of the overvoltage condition is indicated by the

OVP_STAT bit in the OP_STAT register.

Write this bit to 1h to clear the interrupt.

I_LOAD_READY

Latched status bit indicating that the load-current measurement result is available in

the I_LOAD_1 and I_LOAD_2 registers.

Write this bit to 1h to clear the interrupt.

7.6.1.10 INT_TOP2

Address: 0x1B

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

RESET_REG

Bits

7:1

0

Field

Type

R/W

Default

0h

Description

Reserved

RESET_REG

R/W1C

0h

Latched status bit indicating that either start-up (NRST rising edge) is done, VANA

supply voltage is less than the undervoltage threshold level, or the host has

requested a reset (the SW_RESET bit in the RESET register). The regulators are

disabled, the registers are reset to default values, and the normal start-up procedure

is done.

Write this bit to 1h to clear the interrupt.

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7.6.1.11 INT_BUCK_0_1

Address: 0x1C

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

BUCK1_PG

_INT

BUCK1_SC

_INT

BUCK1_ILIM

_INT

Reserved

BUCK0_PG

_INT

BUCK0_SC

_INT

BUCK0_ILIM

_INT

Bits

Field

Type

Default

Description

7

6

Reserved

R/W

0h

BUCK1_PG_INT

R/W1C

0h

Latched status bit indicating that the BUCK1 output voltage reached the power-good-

threshold level.

Write this bit to 1h to clear.

5

BUCK1_SC_INT

BUCK1_ILIM_INT

R/W1C

0h

Latched status bit indicating that the BUCK1 output voltage has fallen to less than the

0.35-V level during operation or the BUCK1 output did not reach the 0.35-V level in 1

ms from enable.

Write this bit to 1h to clear.

4

R/W1C

0h

Latched status bit indicating that output current limit is active.

Write this bit to 1h to clear.

3

2

Reserved

R/W

0h

BUCK0_PG_INT

R/W1C

Latched status bit indicating that the BUCK0 output voltage reached power-good-

threshold level.

Write this bit to 1h to clear.

1

0

BUCK0_SC_INT

BUCK0_ILIM_INT

R/W1C

0h

Latched status bit indicating that the BUCK0 output voltage has fallen to less than the

0.35-V level during operation or the BUCK0 output did not reach the 0.35-V level in 1

ms from enable.

Write this bit to 1h to clear.

Latched status bit indicating that output current limit is active.

Write this bit to 1h to clear.

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7.6.1.12 INT_BUCK_2_3

Address: 0x1D

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

BUCK3_PG

_INT

BUCK3_SC

_INT

BUCK3_ILIM

_INT

Reserved

BUCK2_PG

_INT

BUCK2_SC

_INT

BUCK2_ILIM

_INT

Bits

Field

Type

Default

Description

7

6

Reserved

R/W

0h

BUCK3_PG_INT

R/W1C

0h

Latched status bit indicating that the BUCK3 output voltage reached the power-good-

threshold level.

Write this bit to 1h to clear.

5

BUCK3_SC_INT

BUCK3_ILIM_INT

R/W1C

0h

Latched status bit indicating that the BUCK3 output voltage has fallen to less than the

0.35-V level during operation or the BUCK3 output did not reach the 0.35-V level in 1

ms from enable.

Write this bit to 1h to clear.

4

R/W1C

0h

Latched status bit indicating that the output current limit is active.

Write this bit to 1h to clear.

3

2

Reserved

R/W

0h

BUCK2_PG_INT

R/W1C

Latched status bit indicating that the BUCK2 output voltage reached the power-good-

threshold level.

Write this bit to 1h to clear.

1

0

BUCK2_SC_INT

BUCK2_ILIM_INT

R/W1C

0h

Latched status bit indicating that the BUCK2 output voltage has fallen to less than the

0.35-V level during operation or the BUCK2 output did not reach the 0.35-V level in 1

ms from enable.

Write this bit to 1h to clear.

Latched status bit indicating that the output current limit is active.

Write this bit to 1h to clear.

7.6.1.13 TOP_STAT

Address: 0x1E

D7

D6

Reserved

D5

D4

D3

D2

D1

D0

SYNC_CLK

_STAT

TDIE_SD

_STAT

TDIE_WARN

_STAT

OVP_STAT

Reserved

Bits

7:5

4

Field

Reserved

Type

R

Default

0h

Description

SYNC_CLK_STAT

TDIE_SD_STAT

TDIE_WARN_STAT

OVP_STAT

R

0h

Status bit indicating the status of the external clock (CLKIN).

0h = External clock frequency is valid

1h = External clock frequency is not valid

3

2

1

0

R

0h

Status bit indicating the status of the thermal shutdown condition.

0h = Die temperature is less than the thermal shutdown level

1h = Die temperature is greater than the thermal shutdown level

Status bit indicating the status of thermal warning condition.

0h = Die temperature is less than the thermal warning level

1h = Die temperature is greater than the thermal warning level

Status bit indicating the status of input overvoltage monitoring.

0h = Input voltage is less than the overvoltage threshold level

1h = Input voltage is greater than the overvoltage threshold level

Reserved

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7.6.1.14 BUCK_0_1_STAT

Address: 0x1F

D7

D6

D5

D4

D3

D2

D1

D0

BUCK1_STAT

BUCK1_PG

_STAT

Reserved

BUCK1_ILIM

_STAT

BUCK0_STAT

BUCK0_PG

_STAT

Reserved

BUCK0_ILIM

_STAT

Bits

Field

BUCK1_STAT

Type

Default

Description

7

R

0

Status bit indicating the enable or disable status of the BUCK1 regulator.

0h = BUCK1 regulator is disabled

1h = BUCK1 regulator is enabled

6

BUCK1_PG_STAT

R

0

Status bit indicating the validity of the BUCK1 output voltage (raw status).

0h = BUCK1 output is less than the power-good-threshold level

1h = BUCK1 output is greater than the power-good-threshold level

5

4

Reserved

R

0

BUCK1_ILIM_STAT

Status bit indicating the BUCK1 current limit status (raw status).

0h = BUCK1 output current is less than the current limit level

1h = BUCK1 output current limit is active

3

2

BUCK0_STAT

R

0

Status bit indicating the enable or disable status of the BUCK0 regulator.

0h = BUCK0 regulator is disabled

1h = BUCK0 regulator is enabled

BUCK0_PG_STAT

Status bit indicating the validity of the BUCK0 output voltage (raw status).

0h = BUCK0 output is less than the power-good-threshold level

1h = BUCK0 output is greater than the power-good-threshold level

1

0

Reserved

R

0

BUCK0_ILIM_STAT

Status bit indicating the BUCK0 current limit status (raw status).

0h = BUCK0 output current is less than the current limit level

1h = BUCK0 output current limit is active

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7.6.1.15 BUCK_2_3_STAT

Address: 0x20

D7

D6

D5

D4

D3

D2

D1

D0

BUCK3_STAT

BUCK3_PG

_STAT

Reserved

BUCK3_ILIM

_STAT

BUCK2_STAT

BUCK2_PG

_STAT

Reserved

BUCK2_ILIM

_STAT

Bits

Field

BUCK3_STAT

Type

Default

Description

7

R

0

Status bit indicating the enable or disable status of the BUCK3 regulator.

0h = BUCK3 regulator is disabled

1h = BUCK3 regulator is enabled

6

BUCK3_PG_STAT

R

0

Status bit indicating the validity of the BUCK3 output voltage (raw status).

0h = BUCK3 output is less than the power-good-threshold level

1h = BUCK3 output is greater than the power-good-threshold level

5

4

Reserved

R

0

BUCK3_ILIM_STAT

Status bit indicating the BUCK3 current limit status (raw status).

0h = BUCK3 output current is less than the current limit level

1h = BUCK3 output current limit is active

3

2

BUCK2_STAT

R

0

Status bit indicating the enable or disable status of the BUCK2 regulator.

0h = BUCK2 regulator is disabled

1h = BUCK2 regulator is enabled

BUCK2_PG_STAT

Status bit indicating the validity of the BUCK2 output voltage (raw status)

0h = BUCK2 output is less than the power-good-threshold level

1h = BUCK2 output is greater than the power-good-threshold level

1

0

Reserved

R

0

BUCK2_ILIM_STAT

Status bit indicating the BUCK2 current limit status (raw status).

0h = BUCK2 output current is less than the current limit level

1h = BUCK2 output current limit is active

7.6.1.16 TOP_MASK1

Address: 0x21

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

SYNC_CLK

_MASK

Reserved

TDIE_WARN

_MASK

Reserved

I_LOAD_

READY_MASK

Bits

Field

Type

R/W

Default

Description

7

6:5

4

Reserved

1h

0h

X

SYNC_CLK_MASK

Masking for the external clock detection interrupt (the NO_SYNC_CLK bit in the

INT_TOP1 register)

0h = Interrupt generated

1h = Interrupt not generated

3

2

Reserved

R/W

0h

X

TDIE_WARN_MAS

K

Masking for the thermal warning interrupt (the TDIE_WARN bit in the INT_TOP1

register)

This bit does not affect TDIE_WARN_STAT status bit in the TOP_STAT register.

0h = Interrupt generated

1h = Interrupt not generated

1

0

Reserved

R/W

0

I_LOAD_READY_M

ASK

X

Masking for the load-current measurement-ready interrupt (the I_LOAD_READY bit in

the INT_TOP register).

0h = Interrupt generated

1h = Interrupt not generated

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7.6.1.17 TOP_MASK2

Address: 0x22

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

RESET_REG

_MASK

Bits

7:1

0

Field

Type

R/W

Default

Description

Reserved

0h

X

RESET_REG_MAS

K

Masking for the register reset interrupt (the RESET_REG bit in the INT_TOP2

register)

0h = Interrupt generated

1h = Interrupt not generated

7.6.1.18 BUCK_0_1_MASK

Address: 0x23

D7

D6

D5

Reserved

D4

D3

D2

D1

D0

Reserved

BUCK1_PG

_MASK

BUCK1_ILIM

_MASK

Reserved

BUCK0_PG

_MASK

Reserved

BUCK0_ILIM

_MASK

Bits

Field

Type

R/W

Default

Description

7

6

Reserved

0h

X

BUCK1_PG_MASK

Masking for the BUCK1 power-good interrupt (the BUCK1_PG_INT bit in the

INT_BUCK_0_1 register)

This bit does not affect BUCK1_PG_STAT status bit in BUCK_0_1_STAT register.

0h = Interrupt generated

1h = Interrupt not generated

5

4

Reserved

R

0h

X

BUCK1_ILIM_MAS

K

R/W

Masking for the BUCK1 current-limit-detection interrupt (the BUCK1_ILIM_INT bit in

the INT_BUCK_0_1 register)

This bit does not affect the BUCK1_ILIM_STAT status bit in the BUCK_0_1_STAT

register.

0h = Interrupt generated

1h = Interrupt not generated

3

2

Reserved

R/W

0h

X

BUCK0_PG_MASK

Masking for the BUCK0 power-good interrupt (the BUCK0_PG_INT bit in the

INT_BUCK_0_1 register)

This bit does not affect the BUCK0_PG_STAT status bit in the BUCK_0_1_STAT

register.

0h = Interrupt generated

1h = Interrupt not generated

1

0

Reserved

R

0h

X

BUCK0_ILIM_MAS

K

R/W

Masking for the BUCK0 current-limit-detection interrupt (the BUCK0_ILIM_INT bit in

the INT_BUCK_0_1 register)

This bit does not affect the BUCK0_ILIM_STAT status bit in the BUCK_0_1_STAT

register.

0h = Interrupt generated

1h = Interrupt not generated

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7.6.1.19 BUCK_2_3_MASK

Address: 0x24

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

BUCK3_PG

_MASK

Reserved

BUCK3_ILIM

_MASK

Reserved

BUCK2_PG

_MASK

Reserved

BUCK2_ILIM

_MASK

Bits

Field

Type

R/W

Default

Description

7

6

Reserved

0h

X

BUCK3_PG_MASK

Masking for the BUCK3 power-good interrupt (the BUCK3_PG_INT bit in the

INT_BUCK_2_3 register)

This bit does not affect the BUCK3_PG_STAT status bit in the BUCK_2_3_STAT

register.

0h = Interrupt generated

1h = Interrupt not generated

5

4

Reserved

R

0h

X

BUCK3_ILIM_MAS

K

R/W

Masking for the BUCK3 current-limit-detection interrupt (the BUCK3_ILIM_INT bit in

the INT_BUCK_2_3 register)

This bit does not affect the BUCK3_ILIM_STAT status bit in the BUCK_2_3_STAT

register.

0h = Interrupt generated

1h = Interrupt not generated

3

2

Reserved

R/W

0h

X

BUCK2_PG_MASK

Masking for the BUCK2 power-good interrupt (the BUCK2_PG_INT bit in the

INT_BUCK_2_3 register)

This bit does not affect the BUCK2_PG_STAT status bit in the BUCK_2_3_STAT

register.

0h = Interrupt generated

1h = Interrupt not generated

1

0

Reserved

R

0h

X

BUCK2_ILIM_MAS

K

R/W

Masking for the BUCK2 current limit-detection interrupt (the BUCK2_ILIM_INT bit in

the INT_BUCK_2_3 register)

This bit does not affect the BUCK2_ILIM_STAT status bit in the BUCK_2_3_STAT

register.

0h = Interrupt generated

1h = Interrupt not generated

7.6.1.20 SEL_I_LOAD

Address: 0x25

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

LOAD_CURRENT_BUCK

_SELECT[1:0]

Bits

Field

Type

R/W

Default

0h

Description

7:2

Reserved

1:0 LOAD_CURRENT_

0h

This bit starts the current measurement on the selected regulator.

BUCK_SELECT[1:0

]

One measurement is started when the register is written.

If the selected buck is a master, the measurement result is the sum of the current of

both the master and slave bucks.

If the selected buck is a slave, the measurement result is the current of the selected

slave bucks.

0h = BUCK0

1h = BUCK1

2h = BUCK2

3h = BUCK3

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7.6.1.21 I_LOAD_2

Address: 0x26

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

BUCK_LOAD_CURRENT[9:8]

Bits

Field

Type

R

Default

Description

7:2

Reserved

0h

1:0 BUCK_LOAD_CUR

RENT[9:8]

R

This register describes the three MSB bits of the average load current on the selected

regulator with a resolution of 20 mA per LSB and maximum code corresponding to a

20.47-A current.

7.6.1.22 I_LOAD_1

Address: 0x27

D7

D6

D5

D4

D3

D2

D1

D0

BUCK_LOAD_CURRENT[7:0]

Bits

Field

Type

Default

Description

7:0 BUCK_LOAD_CUR

RENT[7:0]

R

0x00

This register describes the eight LSB bits of the average load current on the selected

regulator with a resolution of 20 mA per LSB and maximum code corresponding to a

20.47-A current.

7.6.1.23 PGOOD_CTRL1

Address: 0x28

D7

D6

D5

D4

D3

D2

D1

D0

PG3_SEL[1:0]

PG2_SEL[1:0]

PG1_SEL[1:0]

PG0_SEL[1:0]

Bits

Field

Type

Default

Description

7:6

PG3_SEL[1:0]

PG2_SEL[1:0]

PG1_SEL[1:0]

PG0_SEL[1:0]

R/W

X

PGOOD signal source control from the BUCK3 regulator

0h = Masked

1h = Power-good-threshold voltage

2h = Reserved, do not use

3h = Power-good-threshold voltage AND current limit

5:4

3:2

1:0

R/W

X

PGOOD signal source control from the BUCK2 regulator

0h = Masked

1h = Power-good-threshold voltage

2h = Reserved, do not use

3h = Power-good threshold voltage AND current limit

PGOOD signal source control from the BUCK1 regulator

0h = Masked

1h = Power-good-threshold voltage

2h = Reserved, do not use

3h = Power-good-threshold voltage AND current limit

PGOOD signal source control from the BUCK0 regulator

0h = Masked

1h = Power-good-threshold voltage

2h = Reserved, do not use

3h = Power-good-threshold voltage AND current limit

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7.6.1.24 PGOOD_CTRL2

Address: 0x29

D7

D6

D5

D4

D3

D2

D1

D0

HALF_DELAY

EN_PG0

_NINT

PGOOD_SET

_DELAY

EN_PGFLT

_STAT

Reserved

PGOOD_

WINDOW

PGOOD_OD

PGOOD_POL

Bits

Field

HALF_DELAY

Type

Default

Description

7

R/W

X

This bit elects the time step for the start-up and shutdown delays.

0h = Start-Up and shutdown delays have 0.5-ms or 1-ms time steps, based on the

DOUBLE_DELAY bit in the CONFIG register.

1h = Start-Up and shutdown delays have 0.32-ms or 0.64-ms time steps, based on

the DOUBLE_DELAY bit in the CONFIG register.

6

5

4

EN_PG0_NINT

R/W

X

This bit combines theBUCK0 PGOOD signal with the nINT signal

0h = BUCK0 PGOOD signal not included with the nINT signal

1h = BUCK0 PGOOD signal included with the nINT signal. If the nINT OR the BUCK0

PGOOD signal is low then the nINT signal is low.

PGOOD_SET_DEL

AY

Debounce time of the output voltage monitoring for the PGOOD signal (only when the

PGOOD signal goes valid)

0h = 4-10 µs

1h = 11 ms

EN_PGFLT_STAT

Operation mode for PGOOD signal

0h = Indicates live status of monitored voltage outputs

1h = Indicates status of the PGOOD_FLT register, inactive if at least one of the

PGx_FLT bit is inactive

3

2

Reserved

R/W

0h

X

PGOOD_WINDOW

Voltage monitoring method for the PGOOD signal

0h = Only undervoltage monitoring

1h = Overvoltage and undervoltage monitoring

1

0

PGOOD_OD

PGOOD_POL

R/W

X

PGOOD signal type

0h = Push-pull output (VANA level)

1h = Open-drain output

PGOOD signal polarity

0h = PGOOD signal high when monitored outputs are valid

1h = PGOOD signal low when monitored outputs are valid

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7.6.1.25 PGOOD_FLT

Address: 0x2A

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

PG3_FLT

PG2_FLT

Description

PG1_FLT

PG0_FLT

Bits

7:4

3

Field

Type

R/W

R

Default

Reserved

PG3_FLT

0x0

0

Source for the PGOOD inactive signal

0h = BUCK3 has not set the PGOOD signal inactive.

1h = BUCK3 has set the PGOOD signal inactive. This bit can be cleared by reading

this register when the BUCK3 output is valid.

2

1

0

PG2_FLT

PG1_FLT

PG0_FLT

R

0

Source for the PGOOD inactive signal

0h = BUCK2 has not set the PGOOD signal inactive.

1h = BUCK2 has set the PGOOD signal inactive. This bit can be cleared by reading

this register when the BUCK2 output is valid.

Source for the PGOOD inactive signal

0h = BUCK1 has not set the PGOOD signal inactive.

1h = BUCK1 has set the PGOOD signal inactive. This bit can be cleared by reading

this register when the BUCK1 output is valid.

Source for the PGOOD inactive signal

0h = BUCK0 has not set the PGOOD signal inactive.

1h = BUCK0 has set the PGOOD signal inactive. This bit can be cleared by reading

this register when the BUCK0 output is valid.

7.6.1.26 PLL_CTRL

Address: 0x2B

D7

D6

D5

Reserved

Default

D4

D3

D2

D1

D0

PLL_MODE[1:0]

EXT_CLK_FREQ[4:0]

Bits

Field

Type

Description

7:6

PLL_MODE[1:0]

R/W

X

This bit selects the external clock and PLL operation.

0h = Forced to internal RC oscillator (PLL is disabled).

1h = PLL is enabled in the STANDBY and ACTIVE states. Automatic external clock

use when available, interrupt generated if external clock appears or disappears.

2h = PLL is enabled only in the ACTIVE state. Automatic external clock use when

available, interrupt generated if external clock appears or disappears.

3h = Reserved

5

Reserved

R/W

0

4:0 EXT_CLK_FREQ[4:

0]

X

Frequency of the external clock (CLKIN). For the input clock frequency tolerance see

the Electrical Characteristics table. Settings 18h through 1Fh are reserved and must

not be used.

0x00h = 1 MHz

0x01h = 2 MHz

2h = 3 MHz

16h = 23 MHz

17h = 24 MHz .

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7.6.1.27 PIN_FUNCTION

Address: 0x2C

D7

D6

D5

D4

D3

D2

D1

D0

EN_SPREAD_ EN_PIN_CTRL EN_PIN_SELE EN_PIN_CTRL EN_PIN_SELE

GPIO3_SEL

GPIO2_SEL

GPIO1_SEL

SPEC

_GPIO3

CT_GPIO3

_GPIO2

CT_GPIO2

Bits

Field

Type

Default

Description

7

EN_SPREAD_SPE

C

R/W

X

This bit enables the spread-spectrum feature.

0h = Disabled

1h = Enabled

6

EN_PIN_CTRL_GPI

O3

R/W

X

This bit enables EN1 and EN2 pin control for GPIO3 (the GPIO3_SEL bit is set to 1h

AND the GPIO3_DIR bit is set to 1h).

0h = Only GPIO3_OUT bit controls GPIO3

1h = GPIO3_OUT bit AND ENx pin control GPIO3

5

4

EN_PIN_SELECT_

GPIO3

R/W

X

This bit enables EN1 and EN2 pin control for GPIO3.

0h = GPIO3_SEL bit AND EN1 pin control GPIO3

1h = GPIO3_SEL bit AND EN2 pin control GPIO3

EN_PIN_CTRL_GPI

O2

This bit enables EN1 and EN3 pin control for GPIO2 (the GPIO2_SEL bit is set to 1h

AND the GPIO2_DIR bit is set to 1h).

0h = Only GPIO2_OUT bit controls GPIO2

1h = GPIO2_OUT bit AND ENx pin control GPIO2

3

2

1

0

EN_PIN_SELECT_

GPIO2

R/W

X

This bit enables EN1 and EN3 pin control for GPIO2

0h = GPIO2_SEL bit AND EN1 pin control GPIO2

1h = GPIO2_SEL bit AND EN3 pin control GPIO2

GPIO3_SEL

GPIO2_SEL

GPIO1_SEL

This bit selects the EN3 pin function

0h = EN3

1h = GPIO3

This bit selects the EN2 pin function

0h = EN2

1h = GPIO2

This bit selects the EN1 pin function

0h = EN1

1h = GPIO1

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7.6.1.28 GPIO_CONFIG

Address: 0x2D

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

GPIO3_OD

GPIO2_OD

GPIO1_OD

Reserved

GPIO3_DIR

Description

GPIO2_DIR

GPIO1_DIR

Bits

Field

Type

R

Default

7

6

Reserved

0h

X

GPIO3_OD

R/W

GPIO3 signal type when configured as an output

0h = Push-pull output (VANA level)

1h = Open-drain output

5

4

GPIO2_OD

GPIO1_OD

R/W

X

GPIO2 signal type when configured as an output

0h = Push-pull output (VANA level)

1h = Open-drain output

GPIO1 signal type when configured as an output

0h = Push-pull output (VANA level)

1h = Open-drain output

3

2

Reserved

R

0h

X

GPIO3_DIR

R/W

GPIO3 signal direction

0h = Input

1h = Output

1

0

GPIO2_DIR

GPIO1_DIR

R/W

X

GPIO2 signal direction

0h = Input

1h = Output

GPIO1 signal direction

0h = Input

1h = Output

7.6.1.29 GPIO_IN

Address: 0x2E

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

GPIO3_IN

Description

GPIO2_IN

GPIO1_IN

Bits

7:3

2

Field

Type

R

Default

0h

Reserved

GPIO3_IN

R

0h

State of the GPIO3 signal

0h = Logic-low level

1h = Logic high level

1

0

GPIO2_IN

GPIO1_IN

R

0h

State of the GPIO2 signal

0h = Logic-low level

1h = Logic-high level

State of the GPIO1 signal

0h = Logic-low level

1h = Logic-high level

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7.6.1.30 GPIO_OUT

Address: 0x2F

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

GPIO3_OUT

Description

GPIO2_OUT

GPIO1_OUT

Bits

7:3

2

Field

Type

R/W

Default

Reserved

GPIO3_OUT

0h

X

Control for theGPIO3 signal when configured as the GPIO output

0h = Logic-low level

1h = Logic-high level

1

0

GPIO2_OUT

GPIO1_OUT

R/W

X

Control for the GPIO2 signal when configured as the GPIO output

0h = Logic-low level

1h = Logic-high level

0h

Control for theGPIO1 signal when configured as the GPIO output

0h = Logic-low level

1h = Logic-high level

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The LP875701-Q1 is a multiphase step-down converter with four switcher cores, which is configured as a single

output 4-phase regulator.

8.2 Typical Application

R₀

V_IN

C₀

C₁

C₂

C₃

L₀

L₁

L₂

L₃

VIN_B0

VIN_B1

VIN_B2

VIN_B3

VANA

SW_B0

SW_B1

SW_B2

C_IN0C_IN1C_IN2C_IN3

R₁

R₂

R₃

V_OUT0

C_OUT0C_OUT1C_OUT2C_OUT3

LOAD

C_VANA

NRST

SDA

C_POL0

SCL

nINT

CLKIN

PGOOD

EN1 (GPIO1)

EN2 (GPIO2)

EN3 (GPIO3)

SW_B3

FB_B0

FB_B1

FB_B2

FB_B3

GNDs

图8-1. 4-Phase Configuration

8.2.1 Design Requirements

8.2.1.1 Inductor Selection

The inductors are L₀, L₁, L₂, and L₃are shown in 节 8.2. The inductance and DCR of the inductor affects the

control loop of the buck regulator. TI recommends using inductors similar to those listed in 表 8-1. Pay attention

to the saturation current and temperature rise current of the inductor. Check that the saturation current is higher

than the peak current limit and the temperature rise current is higher than the maximum expected rms output

current. The minimum effective inductance to make sure performance is good is 0.22 μH at maximum peak

output current over the operating temperature range. DC resistance of the inductor must be less than 0.05 Ω for

good efficiency at high-current condition. The inductor AC loss (resistance) also affects conversion efficiency.

Higher Q factor at switching frequency usually gives better efficiency at light load to middle load. Shielded

inductors are preferred as they radiate less noise.

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表8-1. Recommended Inductors

DCR typical /

maximum

(mΩ)

RATED DC CURRENT,

I_SATmaximum (typical) / I_TEMP

maximum (typical) (A)

DIMENSIONS

L × W × H (mm)

MANUFACTURER

PART NUMBER

VALUE

6.0 (–) / 4.6 (–)⁽¹⁾

Murata

DFE252012PD-R33M 0.33 µH (20%)

2.5 × 2 × 1.2

- / 23

(1) Operating temperature range is up to 125°C including self temperature rise.

8.2.1.2 Input Capacitor Selection

The input capacitors C_IN0, C_IN1, C_IN2, and C_IN3are shown in 节 8.2. A ceramic input bypass capacitor of 10 μF

is required for each phase of the regulator. Place the input capacitor as close as possible to the VIN_Bx pin and

PGND_Bx pin of the device. A larger value or higher voltage rating improves the input voltage filtering. Use X7R

type of capacitors, not Y5V or F. DC bias characteristics capacitors must be considered. The minimum effective

input capacitance to make sure performance is good is 1.9 μF for each buck input at the maximum input voltage

including tolerances and ambient temperature range. This value assumes that at least 22 μF of additional

capacitance is common for all the power input pins on the system power rail. See 表8-2.

The input filter capacitor supplies current to the high-side FET switch in the first half of each cycle and decreases

voltage ripple imposed on the input power source. A ceramic capacitor's low ESR provides the best noise

filtering of the input voltage spikes due to this rapidly changing current. Select an input filter capacitor with

sufficient ripple current rating. In addition ferrite can be used in front of the input capacitor to decrease the EMI.

表8-2. Recommended Input Capacitors (X7R Dielectric)

DIMENSIONS L × W × H VOLTAGE RATING

MANUFACTURER

PART NUMBER

VALUE

CASE SIZE

(mm)

(V)

Murata

GCM21BR71A106KE22

10 µF (10%)

0805

2 × 1.25 × 1.25

10 V

8.2.1.3 Output Capacitor Selection

The output capacitors C_OUT0, C_OUT1, C_OUT2, and C_OUT3are shown in 节 8.2. A ceramic local output capacitor of

22 μF is required per phase. Use ceramic capacitors, X7R or X7T types; do not use Y5V or F. DC bias voltage

characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out current flow

from the inductor to the load, helps keep a steady output voltage during transient load changes and decreases

output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR and

ESL to do these functions. The minimum effective output capacitance to make sure performance is good is 10

μF for each phase including the DC voltage roll-off, tolerances, aging and temperature effects.

The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its

R_ESR. The R_ESRis frequency dependent (as well as temperature dependent); make sure the value used for

selection process is at the switching frequency of the part. See 表8-3.

POL capacitor (C_POL0) needs to be used to maintain output voltage stability and improve load transient

performance and to decrease the ripple voltage. Note that the output capacitor may be the limiting factor in the

output voltage ramp and the maximum total output capacitance listed in electrical characteristics must not be

exceeded. At shutdown the output voltage is discharged to 0.6 V level using forced-PWM operation. This can

increase the input voltage if the load current is small and the output capacitor is large. Below 0.6 V level the

output capacitor is discharged by the internal discharge resistor and with large capacitor more time is required to

settle V_OUTdown as a consequence of the increased time constant.

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表8-3. Recommended Output Capacitors (X7R or X7T Dielectric)

DIMENSIONS L × W × H VOLTAGE RATING

MANUFACTURER

PART NUMBER

VALUE

CASE SIZE

(mm)

(V)

Murata

GCM31CR71A226KE02

22 µF (10%)

1206

3.2 × 1.6 × 1.6

10

8.2.1.4 Snubber Components

If the input voltage for the regulators is above 4 V, snubber components are needed at the switching nodes to

decrease voltage spiking in the switching node and to improve EMI. The snubber capacitors C₀, C₁, C₂, and C₃

and the snubber resistors R₀, R₁, R₂, and R₃are shown in 图 8-1. The recommended components are shown in

表 8-4 and these component values give good performance on LP875701-Q1 EVM. The optimal resistance and

capacitance values finally depend on the PCB layout.

表8-4. Recommended Snubber Components

DIMENSIONS L × W x H VOLTAGE / POWER

MANUFACTURER

PART NUMBER

VALUE

CASE SIZE

(mm)

RATING

62 mW

50 V

Vishay-Dale

Murata

CRCW04023R90JNED

GCM1555C1H391JA16

0402

1 × 0.5 × 0.4

1 × 0.5 × 0.5

3.9 Ω(5%)

390 pF (5%)

8.2.1.5 Supply Filtering Components

The VANA input is used to supply analog and digital circuits in the device. See 表 8-5 for recommended

components for VANA input supply filtering.

表8-5. Recommended Supply Filtering Components

DIMENSIONS L × W × H VOLTAGE RATING

MANUFACTURER

PART NUMBER

VALUE

CASE SIZE

(mm)

(V)

16

Murata

GCM155R71C104KA55

GCM188R71C104KA37

100 nF (10%)

0402

0603

1.0 × 0.5 × 0.5

1.6 × 0.8 × 0.8

8.2.2 Detailed Design Procedure

The performance of the LP875701-Q1 device depends greatly on the care taken in designing the printed circuit

board (PCB). The use of low-inductance and low serial-resistance ceramic capacitors is strongly recommended,

while correct grounding is crucial. Attention must be given to decoupling the power supplies. Decoupling

capacitors must be connected close to the device and between the power and ground pins to support high peak

currents being drawn from system power rail during turnon of the switching MOSFETs. Keep input and output

traces as short as possible, because trace inductance, resistance, and capacitance can easily become the

performance limiting items. The separate power pins VIN_Bx are not connected together internally. Connect the

VIN_Bx power connections together outside the package using power plane construction.

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8.2.3 Application Curves

100

90

80

70

60

50

40

100

90

80

70

60

50

40

V_IN= 3.3 V

10

V_IN= 5.0 V

0.01

0.1

1

0.01

0.1

1

10

Current (A)

D142

D144

V_OUT= 1.0 Volt

图8-2. Efficiency in Forced-PWM-Four-Phase

图8-3. Efficiency in Forced-PWM-Four-Phase Mode

mode

1.02

1.016

1.012

1.008

1.004

1

1.02

1.016

1.012

1.008

1.004

1

0.996

0.992

0.988

0.996

0.992

0.988

V_IN= 3.3 V

V_IN= 5.0 V

V_IN= 3.3 V

V_IN= 5.0 V

0.984

0.98

0.984

0.98

0

2

4

6

8

10

-40

-20

0

20

40

60

80

100

120

Current (A)

Temperature (èC)

D146

D148

V_OUT= 1.0 Volt

V_OUT= 1.0 Volt I_LOAD= 1 A / phase

(4 A total)

图8-4. Output Voltage vs Load Current in Forced-

PWM-Four-Phase Mode

图8-5. Output Voltage vs Temperature

V_(EN1)(1V/div)

V_OUT(200mV/div)

I_LOAD(1A/div)

V_{(SW_B0)}(2V/div)

Time (100 µs/div)

V_OUT= 1.0 Volt

Slew-Rate =3.8

mV / µs

I_LOAD= 0 A

V_OUT= 1.0 Volt

Slew-Rate =3.8

mV / µs

R_LOAD= 0.25 Ω

图8-6. Start-Up With EN1, Forced-PWM-Four-

图8-7. Start-Up With EN1, Forced-PWM-Four-

Phase Mode

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V_(EN1)(1V/div)

V_OUT(200mV/div)

I_LOAD(1A/div)

V_OUT(1mV/div)

V_{(SW_B0)}(2V/div)

Time (100 µs/div)

Time (200 ns/div)

V_OUT= 1.0 Volt

Slew-Rate =3.8

mV / µs

R_LOAD= 0.25 Ω

V_OUT= 1.0 Volt, V_IN

= 3.3 V

I_LOAD= 200 mA

Internal Clock,

Spread-Spectrum

Enabled

图8-8. Shutdown With EN1, Forced-PWM-Four-

Phase Mode

图8-9. Output Voltage Ripple, Forced-PWM-Four-

Phase Mode

I_LOAD(2A/div)

V_OUT(1mV/div)

V_OUT(10mV/div)

V_{(SW_B0)}(2V/div)

Time (40 µs/div)

Time (200 ns/div)

V_OUT= 1.0 Volt, V_IN

= 3.3 V

t_R= t_F= 1 µs

I_OUT= 1.5 A →7.5

A →1.5 A

V_OUT= 1.0 Volt, V_IN

= 5.0 V

I_LOAD= 200 mA

Internal Clock,

Spread-Spectrum

Enabled

图8-11. Transient Load Step Response, Forced-

PWM-Four-Phase Mode, T_A=+25^oC

图8-10. Output Voltage Ripple, Forced-PWM-Four-

Phase Mode

I_LOAD(2A/div)

V_OUT(10mV/div)

Time (40 µs/div)

V_OUT(10mV/div)

Time (40 µs/div)

V_OUT= 1.0 Volt, V_IN

= 3.3 V

t_R= t_F= 1 µs

I_OUT= 1.5 A →7.5

A →1.5 A

V_OUT= 1.0 Volt, V_IN

= 3.3 V

t_R= t_F= 1 µs

I_OUT= 1.5 A →7.5

A →1.5 A

图8-12. Transient Load Step Response, Forced-

图8-13. Transient Load Step Response, Forced-

PWM-Four-Phase Mode, T_A=-40^oC

PWM-Four-Phase Mode, T_A=+125^oC

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I_LOAD(2A/div)

V_OUT(10mV/div)

Time (40 µs/div)

V_OUT= 1.0 Volt, V_IN

= 5.0 V

t_R= t_F= 1 µs

V_OUT= 1.0 Volt, V_IN

= 5.0 V

t_R= t_F= 1 µs

I_OUT= 1.5 A →7.5

A →1.5 A

I_OUT= 1.5 A →7.5

A →1.5 A

图8-15. Transient Load Step Response, Forced-

图8-14. Transient Load Step Response, Forced-

PWM-Four-Phase Mode, T_A=-40^oC

PWM-Four-Phase Mode, T_A=+25^oC

I_LOAD(2A/div)

V_OUT(10mV/div)

Time (40 µs/div)

V_OUT= 1.0 Volt, V_IN= 5.0 V

t_R= t_F= 1 µs

I_OUT= 1.5 A →7.5 A →1.5 A

图8-16. Transient Load Step Response, Forced-PWM-Four-Phase Mode, T_A=+125^oC

9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range from 2.8 V and 5.5 V. This input supply

must be well regulated and can withstand maximum input current and keep a stable voltage without voltage drop

even at load transition condition. The resistance of the input supply rail must be low enough that the input

current transient does not cause too high drop in the LP875701-Q1 supply voltage that can cause false UVLO

fault triggering. If the input supply is located more than a few inches from the LP875701-Q1 additional bulk

capacitance may be required in addition to the ceramic bypass capacitors.

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10 Layout

10.1 Layout Guidelines

The high frequency and large switching currents of the LP875701-Q1 make the choice of layout important. Good

power supply results only occur when care is given to correct design and layout. Layout affects noise pickup and

generation and can cause a good design to perform with less-than-expected results. With a range of output

currents from milliamps to 10 A and over, good power supply layout is much more difficult than most general

PCB design. Use the following steps as a reference to make sure the device is stable and keeps correct voltage

and current regulation across its intended operating voltage and current range.

• Place C_INas close as possible to the VIN_Bx pin and the PGND_Bxx pin. Route the V_INtrace wide and thick

to avoid IR drops. The trace between the positive node of the input capacitor and the VIN_Bx pin(s) of

LP875701-Q1 , as well as the trace between the negative node of the input capacitor and power PGND_Bxx

pin(s), must be kept as short as possible. The input capacitance provides a low-impedance voltage source for

the switching converter. The inductance of the connection is the most important parameter of a local

decoupling capacitor —parasitic inductance on these traces must be kept as small as possible for correct

device operation. The parasitic inductance can be decreased by using a ground plane as close as possible to

top layer by using thin dielectric layer between top layer and ground plane.

• The output filter, consisting of COUT and L, converts the switching signal at SW_Bx to the noiseless output

voltage. It must be placed as close as possible to the device keeping the switch node small, for best EMI

behavior. Route the traces between the LP875701-Q1 output capacitors and the load direct and wide to avoid

losses due to the IR drop.

• Input for analog blocks (VANA and AGND) must be isolated from noisy signals. Connect VANA directly to a

quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling

capacitor as close as possible to the VANA pin.

• If the processor load supports remote voltage sensing, connect the feedback pins FB_Bx of the LP875701-

Q1 device to the respective sense pins on the processor. The sense lines are susceptible to noise. They must

be kept away from noisy signals such as PGND_Bxx, VIN_Bx, and SW_Bx, as well as high bandwidth signals

such as the I²C. Avoid both capacitive and inductive coupling by keeping the sense lines short, direct, and

close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground

plane if possible. Running the signal as a differential pair is recommended for multiphase outputs. If series

resistors are used for load current measurement, place them after connection of the voltage feedback.

Connect feedback pin FB_B0 to supply terminal of the point-of-load, and feedback pin FB_B1 to the GND of

the point-of-load.

• PGND_Bxx, VIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers,

which are cannot withstand interference from noisy PGND_Bxx, VIN_Bx and SW_Bx.

• If the input voltage is above 4 V, place snubber components (capacitor and resistor) between SW_Bx and

ground on all four phases. The components can be also placed to the other side of the board if there are area

limitations and the routing traces can be kept short.

Due to the small package of this converter and the overall small solution size, the thermal performance of the

PCB layout is important. Many system-dependent parameters such as thermal coupling, airflow, added heat

sinks and convection surfaces, and the presence of other heat-generating components affect the power

dissipation limits of a given component. Correct PCB layout, focusing on thermal performance, results in lower

die temperatures. Wide and thick power traces can sink dissipated heat. This can be improved further on multi-

layer PCB designs with vias to different planes. This results in decreased junction-to-ambient (R_θJA) and

junction-to-board (R_θJB) thermal resistances and thereby decreases the device junction temperature, T_J. TI

strongly recommends doing a careful system-level 2D or full 3D dynamic thermal analysis at the beginning

product design process, by using a thermal modeling analysis software.

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10.2 Layout Example

Below example is an illustrative example only. For an exact PCB layout example, please refer to the EVM

Manual

Via to GND plane

Via to VIN plane

Bottom side component

V_OUT1

V_OUT0

L₀

L₁

C_OUT1

C_OUT0

GND

C_IN0

C_IN1

V_IN

13 1211 10 9

V_IN

R₀

R₁

C₁

14

15

16

17

8

FB_B1

EN2

FB_B0

C₀

EN1 7

GND

PGOOD

AGND

6

SDA

27

SCL 5

AGND

C_VANA

18

19

GND

4

3

2

1

VANA GND

nINT

AGND

CLKIN

EN3

V_IN

20 NRST

FB_B3

C₃

FB_B2

21

C₂

R₂

R₃

22 23 24 25 26

V_IN

C_IN3

C_IN2

GND

C_OUT3

C_OUT2

L₃

L₂

V_OUT3

V_OUT2

A. The output voltage rails are shorted together based on the configuration as shown in 节8.2.

图10-1. Board Layout

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11 Device and Documentation Support

11.1 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知

识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。

TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI

提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Feb-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LP875701ARNFRQ1

LP875701ARNFTQ1

VQFN-

HR

RNF

26

3000

250

330.0

12.4

4.25

4.75

1.2

8.0

12.0

Q1

VQFN-

HR

180.0

12.4

4.25

4.75

1.2

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Feb-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LP875701ARNFRQ1

LP875701ARNFTQ1

VQFN-HR

RNF

26

3000

250

346.0

200.0

346.0

183.0

35.0

25.0

Pack Materials-Page 2

PACKAGE OUTLINE

RNF0026B

VQFN-HR - 0.9 mm max height

SCALE 2.800

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

A

B

PIN 1 INDEX AREA

4.6

4.4

C

0.9 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X

2

0.3

0.2

10X

8X 0.5

4X (0.35)

4X (0.575)

(0.2) TYP

4X (0.4)

9

13

4X (0.625)

14

8

7

1.72

1.52

10X

SYMM

27

2X

2.5

0.66 0.1

0.3

0.2

10X 0.5

12X

0.5

21

1

0.1

C A B

C

26

22

PIN 1 ID

THERMAL PAD

0.05

SYMM

12X

0.3

2.24 0.1

4222978/C 04/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RNF0026B

VQFN-HR - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

8X (0.5)

10X (0.25)

22

12X (0.6)

26

1

21

10X (1.82)

12X (0.25)

SYMM

(3.08)

27

(0.66)

2X (3.65)

10X (0.5)

(

0.2) TYP

VIA

8

4X (0.4)

14

4X (0.825)

(R0.05)

TYP

9

13

4X (0.35)

(0.87)

(2.24)

4X (0.775)

2X (3.2)

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

EXPOSED

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

SOLDER MASK

DEFINED

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAIL

NOT TO SCALE

4222978/C 04/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RNF0026B

VQFN-HR - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.575) TYP

(0.5)

10X

EXPOSED METAL

SYMM

TYP

12X (0.6)

26

22

1

21

12X (0.25)

(1.01) TYP

(1.775)

TYP

(1.035) TYP

10X (0.5)

SYMM

2X (0.98)

27

2X (0.66)

(0.59)

(R0.05) TYP

EXPOSED METAL

4X (0.3)

20X (0.81)

4X (0.825)

8

14

13

9

4X (0.3)

20X (0.25)

4X (0.775)

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

PADS 1, 8, 14 & 21: 87% - PADS 9-13 & 22-26: 88% - THERMAL PAD 27: 87%

SCALE:25X

4222978/C 04/2018

NOTES: (continued)

6. For alternate stencil design recommendations, see IPC-7525 or board assembly site preference.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LP875701-Q1
厂家：	TEXAS INSTRUMENTS
描述：	适用于 Mobileye EyeQ4 的汽车类多相 1V、10A 降压转换器转换器
文件：	总73页 (文件大小：3151K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LP875701-Q1 [TI]

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