LP8764-Q1_技术文档

LP8764-Q1

ZHCSQ47 –MARCH 2022

LP8764-Q1 具有集成开关的四相20A 降压转换器

1 特性

2 应用

• 具有符合AEC-Q100 标准的下列特性：

• 高级驾驶辅助系统(ADAS)

• 前置摄像头

• 环视系统ECU

• 远距离雷达

• 传感器融合

– 输入电压：2.8 V 至5.5V

– 器件温度等级1：–40°C 至+125°C 环境工作

温度范围

– 器件HBM ESD 分类等级2

– 器件CDM ESD 分类等级C4B

• 符合功能安全标准

• 域控制器

3 说明

– 专为功能安全应用开发

– 有助于使ISO 26262 系统设计符合ASIL-D 要求

的文档

– 有助于使IEC 61508 系统设计符合SIL-3 要求

的文档

– 系统可满足ASIL D 级要求

– 硬件完整性高达ASIL-D 级

– 窗口式电压和过流监控器

– 具有可选触发/Q&A 模式的看门狗

– 电平或PWM 错误信号监控(ESM)

– 具有高温警告和热关断功能的温度监测

– 对配置寄存器和非易失性存储器的位完整性

(CRC) 错误检测

LP8764-Q1 器件旨在满足各种安全相关的汽车和工业

应用中新型处理器和平台的电源管理要求。该器件具有

4 个降压直流/直流转换器内核，可配置为从 1 个四相

输出到 4 个单相输出的五种不同相位配置。该器件设

置可通过兼容 I²C 的串行接口或 SPI 串行接口进行更

改。

自动 PFM/PWM（AUTO 模式）操作与自动相位增加

和相位减少相结合，可在较宽输出电流范围内最大限度

地提高效率。LP8764-Q1 器件支持对多相位输出的远

程差分电压检测，可补偿稳压器输出与负载点 (POL)

之间的 IR 压降，从而提高输出电压的精度。开关时钟

可以强制进入PWM 模式，并且相位会交错。可以将开

关与外部时钟同步并启用展频模式，以最大限度地降低

干扰。

• 4 个高效降压直流/直流转换器：

– 输出电压：0.3V 至3.34V（多相位输出的电压

为0.3V 至1.9V）

器件信息⁽¹⁾

– 最大输出电流：每相位5A，四相配置最高可达

封装尺寸（标称值）

器件型号

LP8764-Q1

封装

20A

VQFN-HR (32)

5.50 mm × 5.00 mm

– 可编程输出电压压摆率：0.5 mV/µs 至33

mV/µs

– 开关频率：2.2 MHz 或4.4 MHz

• 10 个可配置通用I/O (GPIO)

• SPMI 接口支持多个PMIC 同步

• 输入过压监控(OVP) 和欠压锁定(UVLO)

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

95

90

85

80

75

.

Configurable

multi-phase

70

V_IN

2.2 MHz, 0.8 V

4.4 MHz, 0.8 V

2.2 MHz, 1.2 V

4.4 MHz, 1.2 V

2.2 MHz, 1.8 V

4.4 MHz, 1.8 V

PVIN_B1

PVIN_B2

PVIN_B3

PVIN_B4

VCCA

SW_B1

SW_B2

SW_B3

SW_B4

65

1 - 4

Outputs

60

55

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

FB_B1

FB_B2

FB_B3

FB_B4

Output current (A)

V_IO

VIO

nINT

效率与输出电流间的关系（单相）

VOUT_LDO

SCL_I2C1/SCK_SPI

SDA_I2C1/SDI_SPI

GPIO1...10

GNDs

简化版原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSAZ9

LP8764-Q1

ZHCSQ47 –MARCH 2022

www.ti.com.cn

Table of Contents

8.4 Device State Machine...............................................39

8.5 Power Resources......................................................62

8.6 Residual Voltage Checking.......................................71

8.7 Output Voltage Monitor and PGOOD Generation.....72

8.8 General-Purpose I/Os (GPIO Pins)...........................79

8.9 Thermal Monitoring...................................................80

8.10 Interrupts.................................................................82

8.11 Control Interfaces....................................................88

8.12 Multi-PMIC Synchronization....................................96

8.13 NVM Configurable Registers................................ 102

8.14 Watchdog (WD).....................................................105

8.15 Error Signal Monitor (ESM)...................................125

8.16 Register Map.........................................................141

9 Application and Implementation................................282

9.1 Application Information........................................... 282

9.2 Typical Applications................................................ 282

10 Power Supply Recommendations............................300

11 Layout.........................................................................301

11.1 Layout Guidelines................................................. 301

11.2 Layout Example.................................................... 302

12 Device and Documentation Support........................303

12.1 接收文档更新通知................................................. 303

12.2 支持资源................................................................303

12.3 Trademarks...........................................................303

12.4 Electrostatic Discharge Caution............................303

12.5 术语表................................................................... 303

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

5.1 Digital Signal Descriptions.......................................... 8

6 Specifications................................................................ 14

6.1 Absolute Maximum Ratings...................................... 14

6.2 ESD Ratings............................................................. 14

6.3 Recommended Operating Conditions.......................15

6.4 Thermal Information..................................................15

6.5 Internal Low Drop-Out Regulators (LDOVINT)......... 16

6.6 BUCK1, BUCK2, BUCK3, and BUCK4 Regulators...16

6.7 Reference Generator (REFOUT)..............................23

6.8 Monitoring Functions ................................................23

6.9 Clocks, Oscillators, and DPLL.................................. 26

6.10 Thermal Monitoring and Shutdown.........................27

6.11 System Control Thresholds.....................................27

6.12 Current Consumption..............................................28

6.13 Digital Input Signal Parameters.............................. 29

6.14 Digital Output Signal Parameters............................29

6.15 I/O Pullup and Pulldown Resistance.......................30

6.16 I²C Interface............................................................30

6.17 Serial Peripheral Interface (SPI)............................. 31

7 Typical Characteristics................................................. 34

8 Detailed Description......................................................36

8.1 Overview...................................................................36

8.2 Functional Block Diagram.........................................37

8.3 Input Voltage Monitor................................................38

Information.................................................................. 303

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

March 2022

*

Initial Release

2

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5 Pin Configuration and Functions

32

31

30

28

27

26

GPIO1

GPIO8

1

25

GPIO2

GPIO3

VIO

2

3

4

5

6

7

8

24

FB_B3

23

SCL_I2C1/SCK_SPI

SDA_I2C1/SDI_SPI

FB_B2

FB_B4

22

AGND2

21

VOUT_LDO

20

FB_B1

AGND1

19

GPIO4

VCCA

18

nINT

GPIO7

9

17

10

11

12

13

14

15

16

图5-1. RQK Package 32-Pin VQFN-HR Top View

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表5-1. Pin Functions

CONNECTION IF

NOT USED

I/O

TYPE

DESCRIPTION

NO.

NAME

Primary function: General Purpose Input/Output signal. When configured as

an output pin, it can be included as part of the power sequencer output signal

to enable an external regulator.

Input: Ground,

Output: Floating

I/O

Digital

Alternative programmable function: EN_DRV - Enable Drive output pin to

indicate the device entering safe state (set low when ENABLE_DRV bit is '0').

O

I

Digital

Floating

Ground

Alternative programmable function: nRSTOUT_SOC - System reset or power

on reset output (low = reset).

1

GPIO1

Alternative programmable function: PGOOD - Programmable Power Good

indication pin.

Alternative programmable function: nSLEEP1 or nSLEEP2, which are the

sleep request signals for the device to go to lower power states (Active Low).

Alternative programmable function: WKUP1 or WKUP2, which are the wake-

up request signals for the device to go to higher power states.

I

Primary function: General Purpose Input/Output signal. When configured as

an output pin, it can be included as part of the power sequencer output signal

to enable an external regulator.

Input: Ground,

Output: Floating

I/O

Digital

Alternative programmable function: SCL_I2C2 - Serial interface clock input for

I2C access.

I

Digital

Ground

Alternative programmable function: CS_SPI - Serial interface Chip Select

signal for SPI access.

2

GPIO2

Alternative programmable function: TRIG_WDOG - Trigger signal for trigger

mode watchdog.

Alternative programmable function: nSLEEP1 or nSLEEP2, which are the

sleep request signals for the device to go to lower power states (Active Low).

Alternative programmable function: WKUP1 or WKUP2, which are the wake-

up request signals for the device to go to higher power states.

Primary function: General Purpose Input/Output signal. When configured as

an output pin, it can be included as part of the power sequencer output signal

to enable an external regulator.

Input: Ground,

Output: Floating

I/O

Digital

Alternative programmable function: SDA_I2C2 - Serial interface data input and

output for I2C access.

I/O

Digital

Ground

Floating

Ground

3

GPIO3

Alternative programmable function: SDO_SPI - Serial interface data output

signal for SPI access.

O

I

Alternative programmable function: nSLEEP1 or nSLEEP2, which are the

sleep request signals for the device to go to lower power states (Active Low).

Alternative programmable function: WKUP1 or WKUP2, which are the wake-

up request signals for the device to go to higher power states.

I

Digital

If SPI is not used: SCL_I2C1 - Serial interface clock input for I2C access.

If SPI is used: SCK_SPI - Serial interface clock input for SPI access.

Ground

SCL_I2C1/

SCK_SPI

4

5

If SPI is not used: SDA_I2C1 - Serial interface data input and output for I2C

access.

I/O

I

Digital

Analog

Ground

SDA_I2C1/

SDI_SPI

If SPI is used: SDI_SPI - Serial interface data input signal for SPI access.

Output voltage feedback (positive) for BUCK2. Alternatively ground feedback

for BUCK1 in multiphase configuration.

6

7

FB_B2

FB_B1

—

Analog Output voltage feedback (positive) for BUCK1.

4

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表5-1. Pin Functions (continued)

CONNECTION IF

NOT USED

I/O

TYPE

DESCRIPTION

NO.

NAME

Primary function: General Purpose Input/Output signal. When configured as

an output pin, it can be included as part of the power sequencer output signal

to enable an external regulator.

Input: Ground,

Output: Floating

I/O

Digital

I

Digital

Alternative programmable function: ENABLE - External power-on control.

Ground

Alternative programmable function: TRIG_WDOG - Trigger signal for trigger

mode watchdog.

8

GPIO4

Alternative programmable function: BUCK1_VMON - Voltage monitoring input

for BUCK1 regulator.

Analog

Digital

Ground

—

Alternative programmable function: nSLEEP1 or nSLEEP2, which are the

sleep request signals for the device to go to lower power states (Active Low).

I

Alternative programmable function: WKUP1 or WKUP2, which are the wake-

up request signals for the device to go to higher power states.

I

Digital

Ground

Floating

9

nINT

O

Open-drain interrupt output, active LOW.

Primary function: General Purpose Input/Output signal. When configured as

an output pin, it can be included as part of the power sequencer output signal

to enable an external regulator.

Input: Ground,

Output: Floating

I/O

Digital

Alternative programmable function: SYNCCLKIN - External switching clock

input for Buck regulators.

I

Digital

Ground

Floating

Ground

Alternative programmable function: SYNCCLKOUT - Switching clock output for

external regulators.

O

I

10

GPIO5

Alternative programmable function: nRSTOUT_SOC - System reset or power

on reset output (low = reset).

Alternative programmable function: nSLEEP1 or nSLEEP2, which are the

sleep request signals for the device to go to lower power states (Active Low).

Alternative programmable function: WKUP1 or WKUP2, which are the wake-

up request signals for the device to go to higher power states.

I

Ground

Floating

11

12

13

14

15

SW_B1

PVIN_B1

PGND

Analog BUCK1 switch node.

—

Power input for BUCK1. The separate power pins PVIN_Bx are not connected

together internally –PVIN_Bx and VCCA pins must be connected together in

the application and be locally bypassed.

Power

System supply

Ground

—

Ground Power ground for Buck regulators.

Power input for BUCK2. The separate power pins PVIN_Bx are not connected

together internally –PVIN_Bx and VCCA pins must be connected together in

the application and be locally bypassed.

PVIN_B2

SW_B2

Power

System supply

Floating

Analog BUCK2 switch node.

Primary function: General Purpose Input/Output signal. When configured as

—

Input: Ground,

Output: Floating

I/O

Digital

an output pin, it can be included as part of the power sequencer output signal

to enable an external regulator.

Alternative programmable function: nERR_MCU - System error count down

input signal from the MCU.

I

O

I

Digital

Floating

Ground

Alternative programmable function: SYNCCLKOUT - Switching clock output for

external regulators.

16

GPIO6

Alternative programmable function: PGOOD - Programmable Power Good

indication pin.

Alternative programmable function: nSLEEP1 or nSLEEP2, which are the

sleep request signals for the device to go to lower power states (Active Low).

Alternative programmable function: WKUP1 or WKUP2, which are the wake-

up request signals for the device to go to higher power states.

I

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表5-1. Pin Functions (continued)

CONNECTION IF

NOT USED

I/O

TYPE

DESCRIPTION

NO.

NAME

Primary function: General Purpose Input/Output signal. When configured as

an output pin, it can be included as part of the power sequencer output signal

to enable an external regulator.

Input: Ground,

Output: Floating

I/O

Digital

Alternative programmable function: nERR_MCU - System error count down

input signal from the MCU.

I

O

I

Floating

Ground

Analog Alternative programmable function: REFOUT - Buffered bandgap output.

17

GPIO7

Alternative programmable function: VMON1 - External voltage monitoring

Analog

input.

Alternative programmable function: nSLEEP1 or nSLEEP2, which are the

Digital

I

Ground

sleep request signals for the device to go to lower power states (Active Low).

Alternative programmable function: WKUP1 or WKUP2, which are the wake-

Digital

up request signals for the device to go to higher power states.

Supply voltage for internal LDO. VCCA and PVIN_Bx pins must be connected

together in the application and be locally bypassed.

18

VCCA

Power

System supply

Ground

—

19

20

21

AGND1

VOUT_LDO

AGND2

Ground Ground

—

Power

Ground Ground

Output voltage feedback (positive) for BUCK4. Alternatively ground feedback

for BUCK3 in dualphase configuration.

Analog Output voltage feedback (positive) for BUCK3.

LDO regulator filter node. LDO is used for internal purposes.

—

Ground

22

FB_B4

Analog

Ground

—

23

24

FB_B3

VIO

Ground

—

Power

Supply voltage for selected digital outputs.

Primary function: General Purpose Input/Output signal. When configured as

an output pin, it can be included as part of the power sequencer output signal

to enable an external regulator.

Input: Ground,

Output: Floating

I/O

Digital

Alternative programmable function: SCLK_SPMI - Multi-PMIC SPMI serial

interface clock signal. This pin is an output pin for the master SPMI device,

and an input pin for the slave SPMI device.

Digital

Ground

25

GPIO8

Alternative programmable function: VMON2 - External voltage monitoring

input.

I

Analog

Digital

Ground

Alternative programmable function: nSLEEP1 or nSLEEP2, which are the

sleep request signals for the device to go to lower power states (Active Low).

Alternative programmable function: WKUP1 or WKUP2, which are the wake-

up request signals for the device to go to higher power states.

Primary function: General Purpose Input/Output signal. When configured as

an output pin, it can be included as part of the power sequencer output signal

to enable an external regulator.

Input: Ground,

Output: Floating

I/O

Digital

Alternative programmable function: SDATA_SPMI - Multi-PMIC SPMI serial

interface bidirectional data signal

I/O

Digital

Floating

Ground

Alternative programmable function: PGOOD - Programmable Power Good

indication pin.

O

I

26

GPIO9

Alternative programmable function: SYNCCLKIN - External switching clock

input for Buck regulators.

Alternative programmable function: nSLEEP1 or nSLEEP2, which are the

sleep request signals for the device to go to lower power states (Active Low).

I

Alternative programmable function: WKUP1 or WKUP2, which are the wake-

up request signals for the device to go to higher power states.

I

Ground

Floating

27

28

SW_B3

Analog BUCK3 switch node.

—

Power input for BUCK3. The separate power pins PVIN_Bx are not connected

together internally –PVIN_Bx and VCCA pins must be connected together in

PVIN_B3

Power

System supply

—

the application and be locally bypassed.

6

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表5-1. Pin Functions (continued)

CONNECTION IF

NOT USED

I/O

TYPE

DESCRIPTION

NO.

NAME

Power input for BUCK4. The separate power pins PVIN_Bx are not connected

together internally –PVIN_Bx and VCCA pins must be connected together in

the application and be locally bypassed.

30

PVIN_B4

SW_B4

Power

System supply

Floating

—

31

Analog BUCK4 switch node.

—

Primary function: General Purpose Input/Output signal. When configured as

an output pin, it can be included as part of the power sequencer output signal

to enable an external regulator.

Input: Ground,

Output: Floating

I/O

Digital

Alternative programmable function: nRSTOUT - System reset or power on

reset output (low = reset).

O

I

Digital

Floating

Ground

32

GPIO10

Alternative programmable function: nRSTOUT_SOC - System reset or power

on reset output (low = reset).

Alternative programmable function: nSLEEP1 or nSLEEP2, which are the

sleep request signals for the device to go to lower power states (Active Low).

Alternative programmable function: WKUP1 or WKUP2, which are the wake-

up request signals for the device to go to higher power states.

I

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGNDx ground of the device.

(1)

POS

M1.1

MIN

MAX UNIT

Voltage on supply input pin

VCCA

6

V

–0.3

Voltage on all buck supply voltage input

pins

M1.2

M1.3

M1.4a

PVIN_Bx

–0.3

–0.5

-0.3

Voltage difference between supply input

pins

Between VCCA and each PVIN_Bx

SW_Bx pins

0.5

V

V_{PVIN_Bx}+ 0.3 V,

up to 6 V

Voltage on all buck switch nodes

M1.4b

M1.5

Voltage on all buck switch nodes

Voltage on all buck voltage sense nodes

Voltage on all buck power ground pins

Voltage on internal LDO output pin

Voltage on I/O supply pin

SW_Bx pins, 10-ns transient

FB_Bx

10

4

V

–2

–0.3

M1.6

PGND

0.3

2

M1.7

VOUT_LDO

M1.8

VIO

6

M1.9

Voltage on logic pins (input or output)

I²C and SPI pins, nINT pin, and all GPIO pins

VCCA, PVIN_Bx (voltage below 2.7 V)

VIO (only when VCCA < 2 V)

All pins other than power resources

6

M1.13a

M1.13b

M1.10a

60

20

Voltage rise slew-rate on input supply pins

Peak output current

mV/µs

mA

A

Buck regulators: PVIN_Bx, SW_Bx, and PGNDx per

phase

M1.10b

M1.10c

M1.10d

7

3

8

GPIOx pins, source current

GPIO1/3/5/8/9/10, SDA_I2C1/SDI_SPI and nINT

pins, sink current

mA

Average output current, 100 k hour, T_J=

125℃

M1.10e

M1.10f

M1.11

M1.12

GPIO2/4/6/7 pins, sink current

Buck regulators

3

3.5

A

Junction temperature, T_J

Storage temperature, T_stg

160

150

°C

–45

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, they do not imply functional operation of the device at conditions beyond those indicated under Recommended Operating

Conditions. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

POS

VALUE

UNIT

Electrostatic

discharge

M1.13

V_(ESD)

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

±2000

V

Electrostatic

discharge

M1.14

±500

V

(1) AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

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6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGNDx ground of the device.

POS

MIN

2.8

–0.2

0

NOM

MAX UNIT

R1.1

Voltage on supply input pin

VCCA

3.3

5.5

V

R1.2

R1.3

R1.4

R1.5

R1.6

R1.7

R1.8a

Voltage on all buck supply input pins

Voltage difference between supply input pins

Voltage on all buck switch nodes

PVIN_Bx

3.3

5.5

Between VCCA and each PVIN_Bx

SW_Bx pins

0.2

5.5

Voltage on all buck voltage sense nodes

Voltage on all buck power ground pins

Voltage on internal LDO output pin

FB_Bx

0

V_{OUT(BUCKx)max}

Between PGND and AGNDx

VOUT_LDO

0

1.65

1.7

1.95

1.9

V_VIO= 1.8 V

1.8

3.3

Voltage on I/O supply pin

V

V_VCCA, up to

3.465V

R1.8b

R1.9

V_VIO= 3.3 V

3.135

Voltage on logic pins (input) ⁽²⁾

0

5.5

Voltage on logic pins (output, push-pull) in VIO

domain ⁽²⁾

R1.10a

V_VIO

V

Voltage on logic pins (output, push-pull) in

LDOVINT domain ⁽²⁾

R1.10b

0

V_{VOUT_LDO}

R1.10c

R1.11

R1.12

R1.13

R1.14

Voltage on logic pins (output, open-drain) ⁽²⁾

0

5.5

Voltage on logic pins (output) in VCCA domain EN_DRV

V_VCCA

V

Voltage on AGND ground pins

Operating free-air temperature⁽¹⁾

Junction temperature, T_J

AGND1 and AGND2

0

25

125

150

°C

–40

Operational

(1) Additional cooling strategies may be necessary to keep junction temperature at recommended limits.

(2) Internal pull-up resistor is disabled if pin voltage is above V_{VOUT_LDO}(LDOVINT domain pins) or V_VIO(VIO domain pins)

6.4 Thermal Information

LP876x-Q1

THERMAL METRIC⁽¹⁾

RQK (VQFN-HR)

UNIT

32 PINS

30.5

9.0

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

6.0

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JT

5.8

ψ_JB

R_θJC(bot)

7.5

(1) For more information about traditional and new thermal metrics, see the Semiconductor and ICPackage Thermal Metrics application

report.

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6.5 Internal Low Drop-Out Regulators (LDOVINT)

Over operating free-air temperature range, V_VCCA= 3.3 V (unless otherwise noted). Voltage level refers to the AGNDx

ground of the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics

2.1

2.3

2.7

C_OUT(LDOVINT)Output filtering capacitance⁽¹⁾

V_OUT(LDOVINT)LDOVINT output voltage

Connected from VOUT_LDO to AGNDx

1

2.2

1.8

3

4

µF

V

I_Qon(LDOVINT)

R_DIS(LDOVINT)

Quiescent current, on mode

LDOVINT under valid operating condition, I_LOAD= 0 mA

Off mode, pulldown enabled and LDO disabled

10

µA

Pulldown discharge resistance

at LDOVINT output

2.8

60

125

190

Ω

(1) When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above

therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the

capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of

regulators.

6.6 BUCK1, BUCK2, BUCK3, and BUCK4 Regulators

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGNDx ground of the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics - Output Voltage

3.1a

3.1b

20

5

0.3 V ≤V_{VOUT_Bx}< 0.6 V

0.6 V ≤V_{VOUT_Bx}< 1.1 V

1.1 V ≤V_{VOUT_Bx}< 1.66 V

1.66 V ≤V_{VOUT_Bx}≤3.34 V

V_{VOUT_Bx_Ste}Output voltage programmable

mV

V

step size

p

3.1c

3.1d

10

20

Minimum voltage between PVIN_Bx and

VOUT_Bx to fulfill the electrical

characteristics

Input and output voltage

difference

3.3

0.7

3.4a

3.4b

3.4c

3.4d

3.4e

3.4f

BUCKn_SLEW_RATE[2:0] = 000b

BUCKn_SLEW_RATE[2:0] = 001b

BUCKn_SLEW_RATE[2:0] = 010b

BUCKn_SLEW_RATE[2:0] = 011b

BUCKn_SLEW_RATE[2:0] = 100b

BUCKn_SLEW_RATE[2:0] = 101b

BUCKn_SLEW_RATE[2:0] = 110b

BUCKn_SLEW_RATE[2:0] = 111b

26.6

17

33.3

20

36.6

22

9

10

11

4.5

2.25

1.12

5

5.5

V_{VOUT_Bx_Sle}Output voltage slew-rate

mV/µs

2.75

programmable range^{(5) (7) (9)}

w_Rate

2.5

1.25

1.38

0.69

3.4g

3.4h

0.56 0.625

0.281 0.3125 0.344

Electrical Characteristics - Output Current, Limits and Thresholds

3.6a

3.6b

3.6c

3.6d

1-phase

2-phase

3-phase

4-phase

5

10

15

20

I_{OUT_Bx}

Output current^{(3) (4)}

A

Mismatch between phase current and

average phase current, I_{OUT_Bx}> 1 A /

phase

Current balancing for multi-phase

output

3.7

20%

Forward current limit (peak

during each switching cycle)

Programmable range

I_{LIM FWD}

3.8

3.9

2.5

7.5

A

PEAK Range

I_{LIM FWD}

Forward current limit step Size

1

PEAK Step

16

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6.6 BUCK1, BUCK2, BUCK3, and BUCK4 Regulators (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGNDx ground of the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

I_LIM= 2.5 A, 3.5 A, 4.5 A, 3.0 V ≤

3.10a

-0.55

0.55

10%

2.6

A

V

_{PVIN_Bx}≤5.5 V

I_LIM= 5.5 A, 6.5 A or 7.5 A 4.5 V ≤

_{PVIN_Bx}≤5.5 V

I_LIM= 5.5 A, 6.5 A or 7.5 A 3.0 V ≤

_{PVIN_Bx}≤4.5 V

I_{LIM FWD}

3.10b

3.10c

3.11

Forward current limit accuracy

–10%

V

PEAK Accuracy

–15%

V

Negative current limit (peak

during each switching cycle)

I_{LIM NEG}

1.5

2

A

3.15a

3.15b

3.15c

3.16a

3.16b

3.16c

3.16d

3.16e

3.16f

From 1-phase to 2-phase

2.0

3.6

5.5

1.4

2.5

3.3

0.6

1.4

2.5

Phase adding level (multi-phase

rails)

I_ADD

From 2-phase to 3-phase

From 3-phase to 4-phase

From 2-phase to 1-phase

Phase shedding level (multi-

phase rails)

I_SHED

From 3-phase to 2-phase

A

From 4-phase to 3-phase

Hysteresis from 2-phase to 1-phase

Hysteresis from 3-phase to 2-phase

Hysteresis from 4-phase to 3-phase

Phase shedding hysteresis

(multi-phase rails)

I_{SHED_Hyst}

Electrical Characteristics - Current Consumption, On Resistance, and Output Pulldown Resistance

Shutdown current, BUCKx

disabled

3.17

I_off

1

µA

I_{OUT_Bn}= 0 mA, not switching, first single

phase or primary phase in multi-phase

configuration, T_J= 25°C

3.18a

90

I_{OUT_Bn}= 0 mA, not switching, additional

single phase or primary phase in multi-

phase

3.18b

3.18c

I_{Q_AUTO}

Auto mode quiescent current

60

30

configuration, T_J= 25°C

I_{OUT_Bn}= 0 mA, not switching, secondary/

tertiary/quaternary phase in multi-phase

configuration, T_J= 25°C

R_{DS(ON) HS}

3.19

3.20

On-resistance, high-side FET

On-resistance, low-side FET

I_{OUT_Bx}= 1 A

26

16

65

35

mΩ

FET

R_{DS(ON) LS}

FET

Regulator disabled, per phase,

BUCKx_PLDN = 1, between SW_Bx and

PGND pins

Output pulldown discharge

resistance

3.21

R_{DIS_Bx}

50

100

150

Ω

Threshold voltage for Short

Circuit and Residual Voltage

Detection

V_{TH_SC_RV_B}

3.21b

3.22

140

3

150

5

160 mV

x

Resistance threshold for Short

circuit detection at the SW pin

R_{SW_SC}

25

Ω

Electrical Characteristics - 4.4MHz Single-Phase and Multi-Phase Configuration

3.23

3.24

3.25

3.26a

V_{PVIN_Bx}

V_{VOUT_Bx}

C_{IN_Bx}

Input voltage range

3.0

0.3

3

3.3

5.5

1.9

V

Output voltage programmable

range

Input filtering capacitance^{(1) (2)}

22

µF

C_OUT-

Output capacitance, local⁽²⁾

Per phase

10

Local(Buckx)

C_OUT-

Output capacitance, total (local

and POL)⁽²⁾

3.27b

50

250

µF

TOTAL_Bx

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6.6 BUCK1, BUCK2, BUCK3, and BUCK4 Regulators (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGNDx ground of the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

220

10

MAX UNIT

3.28a

Inductance

DCR

154

286

nH

mΩ

mA

L_Bx

Power inductor

3.28b

3.29

I_{Q_PWM}

PWM mode Quiescent current

I_{OUT_Bx}= 0 mA

20

3.160a

3.160b

3.160c

V_{VOUT_Bx}< 1 V, PWM mode

10 mV

1%

–10

–1%

–20

DC output voltage accuracy,

includes voltage reference, DC

load and line regulations and

temperature

V

_{VOUT_Bx}≥1 V, PWM mode

V_{OUT_DC_Bx}

V_{VOUT_Bx}< 1 V, PFM mode

25 mV

-1% -

10 mV

1% +

15 mV

3.160d

3.31a

3.31b

3.31c

3.32

V

_{VOUT_Bx}≥1 V, PFM mode

0.3 V ≤V_{VOUT_Bx}< 0.6 V, I_{OUT_Bx}= 1 mA

to 400 mA / phase, t_r= t_f= 1 µs, PWM

mode

15

mV

0.6 V ≤V_{VOUT_Bx}< 1.5 V, I_{OUT_Bx}= 1 mA

to 2 A / phase, t_r= t_f= 1 µs, PWM mode

T_{LDSR_MP}

Transient load step response⁽⁸⁾

Transient line response

1.5 V ≤V_{VOUT_Bx}≤1.9 V, I_{OUT_Bx}= 1

mA to 2 A / phase, t_r= t_f= 1 µs, PWM

mode

1.5%

±5

V_{PVIN_Bx}stepping from 3 V to 3.5 V, t_r= t_f

= 10 µs, I_{OUT_Bx}= I_OUT(max)

T_LNSR

-20

20 mV

3.33a

3.33b

PWM mode, 1-phase

PFM mode

3

mV_PP

V_{OUT_Ripple}Ripple voltage⁽⁸⁾

15

25 mV_PP

PFM to PWM switch current

3.120

3.121

3.122

I_PFM-PWM

I_PWM-PFM

Auto mode

600

300

200

mA

threshold⁽⁶⁾

PWM to PFM switch current

threshold⁽⁶⁾

I_PWM-

PWM to PFM switch current

hysteresis

PFM_HYST

Electrical Characteristics - 2.2MHz Single-Phase Configuration for DDR Termination

3.34

3.35

V_{PVIN_Bx}

I_{OUT_Bx_SINK}Current sink

Output voltage programmable

Input voltage range

2.8

1

3.3

5.5

0.7

V

A

3.36

3.37

3.38a

V_{VOUT_Bx}

0.5

3

V

range

C_{IN_Bx}

Input filtering capacitance^{(1) (2)}

22

µF

C_OUT-

Output capacitance, local⁽²⁾

10

Local(Buckx)

C_OUT-

Output capacitance, total (local

and POL)⁽²⁾

3.38b

25

50

µF

TOTAL_Bx

3.39a

3.39b

3.40

Inductance

329

470

10

611

nH

mΩ

mA

L_Bx

Power inductor

DCR

I_{Q_PWM}

PWM mode Quiescent current

I_{OUT_Bx}= 0 mA

V_{VOUT_Bx}< 1 V, PWM mode

13

DC output voltage accuracy,

includes voltage reference, DC

load and line regulations and

temperature

3.161a

10 mV

–10

V_{OUT_DC_Bx}

3.161b

3.42

1%

V

_{VOUT_Bx}≥1 V, PWM mode

–1%

0.5 V ≤V_{VOUT_Bx}≤0.7 V, I_{OUT_Bx}= -1

mA to -1000 mA, t_r= t_f= 1 µs, PWM

mode

T_LDSR

Transient load step response⁽⁸⁾

15

mV

V_{PVIN_Bx}stepping from 3 V to 3.5 V, t_r= t_f

= 10 µs, I_{OUT_Bx}= I_{OUT_Bx(max)}

3.43

3.44

T_LNSR

Transient line response

-20

±5

3

20 mV

V_{OUT_Ripple}Ripple voltage⁽⁸⁾

PWM mode

6 mV_PP

Electrical Characteristics - 4.4MHz Single-Phase Configuration Low Output Voltage

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6.6 BUCK1, BUCK2, BUCK3, and BUCK4 Regulators (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGNDx ground of the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

3.45

V_{PVIN_Bx}

V_{VOUT_Bx}

C_{IN_Bx}

Input voltage range

3.0

3.3

5.5

1.9

V

Output voltage programmable

range

3.46

3.47

3.48a

0.3

3

Input filtering capacitance^{(1) (2)}

22

µF

C_OUT-

Output capacitance, local⁽²⁾

10

Local(Buckx)

C_OUT-

Output capacitance, total (local

and POL)⁽²⁾

3.48b

25

100

286

µF

TOTAL_Bx

3.49a

3.49b

3.50

Inductance

DCR

154

220

10

nH

mΩ

mA

L_Bx

Power inductor

I_{Q_PWM}

PWM mode Quiescent current

I_{OUT_Bx}= 0 mA

19

3.162a

3.162b

3.162c

V_{VOUT_Bx}< 1 V, PWM mode

10 mV

1%

–10

–1%

–20

DC output voltage accuracy,

includes voltage reference, DC

load and line regulations and

temperature

V

_{VOUT_Bx}≥1 V, PWM mode

V_{OUT_DC_Bx}

V_{VOUT_Bx}< 1 V, PFM mode

35 mV

-1% -

10 mV

1% +

25 mV

3.162d

3.52a

3.52b

3.52c

3.53

V

_{VOUT_Bx}≥1 V, PFM mode

0.3 V ≤V_{VOUT_Bx}< 0.6 V, I_{OUT_Bx}= 1 mA

to 200 mA, t_r= t_f= 1 µs, PWM mode

15

mV

0.6 V ≤V_{VOUT_Bx}< 1.5 V, I_{OUT_Bx}= 1 mA

to 1 A, t_r= t_f= 1 µs, PWM mode

T_LDSR

Transient load step response⁽⁸⁾

Transient line response

1.5 V ≤V_{VOUT_Bx}≤1.9 V, I_{OUT_Bx}= 1

mA to 1 A, t_r= t_f= 1 µs, PWM mode

1.5%

±5

V_{PVIN_Bxx}stepping from 3 V to 3.5 V, t_r= t_f

= 10 µs, I_{OUT_Bx}= I_{OUT_Bx(max)}

T_LNSR

-20

20 mV

mV_PP

3.54a

3.54b

PWM mode

PFM mode

5

8

V_{OUT_Ripple}Ripple voltage⁽⁸⁾

15

50 mV_PP

mA

PFM to PWM switch current

Auto mode, V_{PVIN_Bx}= 3.3 V, V_{VOUT_Bx}

1.0 V

=

3.123

3.124

3.125

I_PFM-PWM

I_PWM-PFM

600

300

200

threshold⁽⁶⁾

PWM to PFM switch current

threshold⁽⁶⁾

Auto mode, V_{PVIN_Bx}= 3.3 V, V_{VOUT_Bx}

1.0 V

mA

I_PWM-

PWM to PFM switch current

hysteresis

Auto mode, V_{PVIN_Bx}= 3.3 V, V_{VOUT_Bx}

1.0 V

PFM_HYST

Electrical Characteristics - 4.4MHz Single-Phase Configuration High Output Voltage

3.55

3.56

V_{PVIN_Bx}

Input voltage range

Output current

4.5

1.7

5

5.5

2.5

V

A

I_{OUT_Bx_4.4_H}

VOUT

Output voltage programmable

range

3.57

V_{VOUT_Bx}

C_{IN_Bx}

3.34

V

3.58

Input filtering capacitance^{(1) (2)}

3

22

µF

3.59a

C_{OUT-Local_Bx}Output capacitance, local⁽²⁾

10

C_OUT-

Output capacitance, total (local

and POL)⁽²⁾

3.59b

50

150

611

µF

TOTAL_Bx

3.60a

3.60b

3.61

Inductance

DCR

329

470

10

nH

mΩ

mA

L_Bx

Power inductor

I_{Q_PWM}

PWM mode Quiescent current

I_{OUT_Bx}= 0 mA

29

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6.6 BUCK1, BUCK2, BUCK3, and BUCK4 Regulators (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGNDx ground of the device.

POS

PARAMETER

TEST CONDITIONS

MIN

–10

–1%

–20

TYP

MAX UNIT

10 mV

1%

3.163a

V_{VOUT_Bx}< 1 V, PWM mode

DC output voltage accuracy,

includes voltage reference, DC

load and line regulations and

temperature

3.163b

3.163c

V

_{VOUT_Bx}≥1 V, PWM mode

V_{OUT_DC_Bx}

V_{VOUT_Bx}< 1 V, PFM mode

25 mV

-1% -

10 mV

1% +

15 mV

3.163d

3.63

V

_{VOUT_Bx}≥1 V, PFM mode

1.7 V ≤V_{VOUT_Bx}≤3.34 V, I_{OUT_Bx}= 1

mA to 1 A, t_r= t_f= 1 µs, PWM mode

T_{LDSR_SP}

T_LNSR

Transient load step response⁽⁸⁾

Transient line response

1.5%

±5

V_{PVIN_Bxx}stepping from 4.7 V to 5.2 V, t_r=

t_f= 10 µs, I_{OUT_Bx}= I_{OUT_Bx(max)}

3.64

-20

20 mV

3.65a

3.65b

PWM mode

PFM mode

3

7 mV_PP

V_{OUT_Ripple}Ripple voltage⁽⁸⁾

15

25 mV_PP

mA

PFM to PWM switch current

Auto mode, V_{PVIN_Bx}= 5 V, V_{VOUT_Bx}

1.8 V

=

3.126

3.127

3.128

I_PFM-PWM

I_PWM-PFM

400

260

140

threshold⁽⁶⁾

PWM to PFM switch current

threshold⁽⁶⁾

Auto mode, V_{PVIN_Bx}= 5 V, V_{VOUT_Bx}

1.8 V

mA

I_PWM-

PWM to PFM switch current

hysteresis

Auto mode, V_{PVIN_Bx}= 5 V, V_{VOUT_Bx}

1.8 V

PFM_HYST

Electrical Characteristics - 2.2MHz Single-Phase Configuration with 5.0V VIN

3.66

3.67

V_{PVIN_Bx}

V_{VOUT_Bx}

C_{IN_Bx}

Input voltage range

4.5

0.3

5

5.5

V

Output voltage programmable

range

3.34

3.68

Input filtering capacitance^{(1) (2)}

3

22

µF

3.69a

C_{OUT-Local_Bx}Output capacitance, local⁽²⁾

10

C_OUT-

Output capacitance, total (local

and POL)⁽²⁾

3.69b

100

700

1000

1300

µF

TOTAL_Bx

3.70a

3.70b

3.71

Inductance

1000

10

nH

mΩ

mA

L_Bx

Power inductor

DCR

I_{Q_PWM}

PWM mode Quiescent current

I_{OUT_Bx}= 0 mA

V_{VOUT_Bx}< 1 V, PWM mode

14

3.164a

3.164b

3.164c

10 mV

1%

–10

–1%

–20

DC output voltage accuracy,

includes voltage reference, DC

load and line regulations and

temperature

V

_{VOUT_Bx}≥1 V, PWM mode

V_{OUT_DC_Bx}

V_{VOUT_Bx}< 1 V, PFM mode

25 mV

-1% -

10 mV

1% +

15 mV

3.164d

3.73a

3.73b

3.73c

3.74

V

_{VOUT_Bx}≥1 V, PFM mode

0.3 V ≤V_{VOUT_Bx}< 0.6 V, I_{OUT_Bx}= 1 mA

to 400 mA, t_r= t_f= 1 µs, PWM mode

15

mV

0.6 V ≤V_{VOUT_Bx}< 1.5 V, I_{OUT_Bx}= 1 mA

to 2 A, t_r= t_f= 1 µs, PWM mode

T_{LDSR_SP}

Transient load step response⁽⁸⁾

Transient line response

1.5 V ≤V_{VOUT_Bx}≤3.34 V, I_{OUT_Bx}= 1

mA to 2 A, t_r= t_f= 1 µs, PWM mode

1.5%

±5

V_{PVIN_Bx}stepping from 4.7 V to 5.2 V, t_r=

t_f= 10 µs, I_{OUT_Bx}= I_{OUT_Bx(max)}

T_LNSR

-20

20 mV

3.75a

3.75b

PWM mode

PFM mode

3

7.5 mV_PP

25 mV_PP

V_{OUT_Ripple}Ripple voltage⁽⁸⁾

15

PFM to PWM switch current

Auto mode, V_{PVIN_Bx}= 5 V, V_{VOUT_Bx}

1.0V

=

3.129

3.130

3.131

I_PFM-PWM

I_PWM-PFM

400

200

mA

threshold⁽⁶⁾

PWM to PFM switch current

threshold⁽⁶⁾

Auto mode, V_{PVIN_Bx}= 5 V, V_{VOUT_Bx}

1.0V

I_PWM-

PWM to PFM switch current

hysteresis

Auto mode, V_{PVIN_Bx}= 5 V, V_{VOUT_Bx}

1.0V

PFM_HYST

20

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6.6 BUCK1, BUCK2, BUCK3, and BUCK4 Regulators (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGNDx ground of the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics - 2.2MHz Single-Phase and Multi-Phase Configuration

3.76

3.77

V_{PVIN_Bx}

V_{VOUT_Bx}

C_{IN_Bx}

Input voltage range

3.0

0.3

3.3

5.5

1.9

V

Output voltage programmable

range

3.78

Input filtering capacitance^{(1) (2)}

3

22

µF

3.79a

C_{OUT-Local_Bx}Output capacitance, local⁽²⁾

Per phase

10

C_OUT-

Output capacitance, total (local

and POL)⁽²⁾

3.79b

100

329

1000

611

µF

TOTAL_Bx

3.80a

3.80b

3.81

Inductance

470

10

nH

mΩ

mA

LBx

Power inductor

DCR

I_{Q_PWM}

PWM mode Quiescent current

I_{OUT_Bx}= 0 mA

V_{VOUT_Bx}< 1 V, PWM mode

13

3.165a

3.165b

3.165c

10 mV

1%

–10

–1%

–20

DC output voltage accuracy,

includes voltage reference, DC

load and line regulations and

temperature

V

_{VOUT_Bx}≥1 V, PWM mode

V_{OUT_DC_Bx}

V_{VOUT_Bx}< 1 V, PFM mode

25 mV

-1% -

10 mV

1% +

15 mV

3.165d

3.83a

3.83b

3.83c

3.84

V

_{VOUT_Bx}≥1 V, PFM mode

0.3 V ≤V_{VOUT_Bx}< 0.6 V, I_{OUT_Bx}= 1 mA

to 400 mA / phase, t_r= t_f= 1 µs, PWM

mode

5

15

mV

0.6 V ≤V_{VOUT_Bx}< 1.5 V, I_{OUT_Bx}= 1 mA

to 2 A / phase, t_r= t_f= 1 µs, PWM mode

T_{LDSR_MP}

Transient load step response⁽⁸⁾

Transient line response

1.5 V ≤V_{VOUT_Bx}≤1.9 V, I_{OUT_Bx}= 1

mA to 2 A / phase, t_r= t_f= 1 µs, PWM

mode

1%

±5

V_{PVIN_Bx}stepping from 3 V to 3.5 V, t_r= t_f

= 10 µs, I_{OUT_Bx}= I_{OUT_Bx(max)}

T_LNSR

-20

20 mV

mV_PP

3.85a

3.85b

PWM mode, 1-phase

PFM mode

3

5

V_{OUT_Ripple}Ripple voltage⁽⁸⁾

15

25 mV_PP

mA

PFM to PWM switch current

Auto mode, V_{PVIN_Bx}= 3.3 V, V_{VOUT_Bx}

1.0V

=

3.132

3.133

3.134

I_PFM-PWM

I_PWM-PFM

500

440

60

threshold⁽⁶⁾

PWM to PFM switch current

threshold⁽⁶⁾

Auto mode, V_{PVIN_Bx}= 3.3 V, V_{VOUT_Bx}

1.0V

mA

I_PWM-

PWM to PFM switch current

hysteresis

Auto mode, V_{PVIN_Bx}= 3.3 V, V_{VOUT_Bx}

1.0V

PFM_HYST

Electrical Characteristics - 2.2MHz Single-Phase Generic Configuration

3.86

3.87

V_{PVIN_Bx}

V_{VOUT_Bx}

C_{IN_Bx}

Input voltage range

2.8

0.3

3.3

5.5

V

Output voltage programmable

range

3.34

3.88

Input filtering capacitance^{(1) (2)}

3

22

µF

3.89a

C_{OUT-Local_Bx}Output capacitance, local⁽²⁾

10

C_OUT-

Output capacitance, total (local

and POL)⁽²⁾

3.89b

100

700

500

µF

TOTAL_Bx

3.90a

3.90b

3.91

Inductance

DCR

1000

10

1300

nH

mΩ

mA

L_Bx

Power inductor

I_{Q_PWM}

PWM mode Quiescent current

I_{OUT_Bx}= 0 mA

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6.6 BUCK1, BUCK2, BUCK3, and BUCK4 Regulators (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGNDx ground of the device.

POS

PARAMETER

TEST CONDITIONS

MIN

–10

–1%

–20

TYP

MAX UNIT

10 mV

1%

3.166a

V_{VOUT_Bx}< 1 V, PWM mode

DC output voltage accuracy,

includes voltage reference, DC

load and line regulations and

temperature

3.166b

3.166c

V

_{VOUT_Bx}≥1 V, PWM mode

V_{OUT_DC_Bx}

V_{VOUT_Bx}< 1 V, PFM mode

25 mV

-1% -

10 mV

1% +

15 mV

3.166d

3.93a

3.93b

3.93c

3.94

V

_{VOUT_Bx}≥1 V, PFM mode

0.3 V ≤V_{VOUT_Bx}< 0.6 V, I_{OUT_Bx}= 1 mA

to 400 mA, t_r= t_f= 1 µs, PWM mode

35

17

mV

0.6 V ≤V_{VOUT_Bx}< 1.0 V, I_{OUT_Bx}= 1 mA

to 2 A, t_r= t_f= 1 µs, PWM mode

T_{LDSR_SP}

Transient load step response⁽⁸⁾

Transient line response

1.0 V ≤V_{VOUT_Bx}≤3.34 V, I_{OUT_Bx}= 1

mA to 2 A, t_r= t_f= 1 µs, PWM mode

3.5%

±5

V_{PVIN_Bx}stepping from 3 V to 3.5 V, t_r= t_f

= 10 µs, I_{OUT_Bx}= I_{OUT_Bx(max)}

T_LNSR

-20

20 mV

3.95a

3.95b

PWM mode

PFM mode

3

7.5 mV_PP

25 mV_PP

V_{OUT_Ripple}Ripple voltage⁽⁸⁾

15

PFM to PWM switch current

Auto mode, V_{PVIN_Bx}= 3.3 V, V_{VOUT_Bx}

1.0V

=

3.135

3.136

3.137

I_PFM-PWM

I_PWM-PFM

300

150

mA

threshold⁽⁶⁾

PWM to PFM switch current

threshold⁽⁶⁾

Auto mode, V_{PVIN_Bx}= 3.3 V, V_{VOUT_Bx}

1.0V

I_PWM-

PWM to PFM switch current

hysteresis

Auto mode, V_{PVIN_Bx}= 3.3 V, V_{VOUT_Bx}

1.0V

PFM_HYST

Timing Requirements

From end of voltage ramp to V_OUTwithin

15 mV from V_{OUT_DC_Bx}

3.108

3.109

Settling time after voltage scaling

Start-up delay

105

200

7

µs

(10)

From enable to start of output voltage rise

100

19

150

Peak current limit triggering during every

switching cycle

3.110

3.111

3.112

t_{delay_OC}

Over-current detection delay

Digital deglitch time for detected signal.

Time duration to filter out short positive

and negative pulses

Over-current detection signal

deglitch time

t_{deglitch_OC}

23

30

µs

Over-current signal latency time Total delay from over-current detection to

t_{latency_OC}

from detection

interrupt or PFSM trigger

Switching Characteristics

3.106a

3.106b

2.2 MHz setting, internal clock

4.4 MHz setting, internal clock

2

4

2.2

4.4

2.4

4.8

2.2 MHz setting, internal clock, spread

spectrum enabled

3.106d

1.8

3.5

1.8

3.5

2.2

4.4

2.2

4.4

2.2

2.6

5.3

2.6

5.3

Switching frequency, PWM mode

NVM programmable

4.4 MHz setting, internal clock, spread

spectrum enabled

f_SW

MHz

3.106e

3.106g

3.106h

3.107b

2.2 MHz setting, synchronized to external

clock

4.4 MHz setting, synchronized to external

clock

Automatic maximum switching

frequency scaling in PWM mode

f_{SW_max}

0.3 V ≤V_{VOUT_Bx}< 0.6 V

(1) Input capacitors must be placed as close as possible to the device pins.

(2) When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above

therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the

capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of

regulators.

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(3) The maximum output current can be limited by the forward current limit I_{LIM FWD}. The maximum output current is also limited by the

junction temperature and maximum average current over lifetime. The power dissipation inside the die increases the junction

temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient temperature.

(4) Advance thermal design is required to avoid thermal shutdown.

(5) SLEW_RATEx[2:0] register default comes from NVM memory, and can be re-programed by software. Output capacitance, forward and

negative current limits and load current may limit the maximum and minimum slew rates.

(6) The PFM-to-PWM and PWM-to-PFM switchover current can be affected by the input and the output voltage, temperature, the inductor

and the capacitor values.

(7) A high slew-rate setting can generate over and undershoot during voltage change. See Application Section for more information.

(8) Please refer to the applications section of the datasheet regarding the power delivery network (PDN) used for the transient load step

and output ripple test conditions. All ripple specs are defined across POL capacitor in the described PDN.

(9) Slew-rate is measured from 10% to 90% of the voltage ramp with voltage step ≥500 mV.

(10) Voltage ramp is calculated using slew-rate from minimum column.

6.7 Reference Generator (REFOUT)

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGNDx ground of the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics

4.1

Max capacitance for REFOUT signal Capacitance between REFOUT signal and ground

100

pF

V

4.2

Output voltage

Start-up time

Measured at the REFOUT signal

1.17

1.2

30

1.23

Timing Requirements

From REFOUT_EN=1 to the time REFOUT voltage

settles

4.4

t_{SU_REF}

µs

6.8 Monitoring Functions

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGNDx ground of the device.

POS

Electrical Characteristics: BUCK REGULATORS OUTPUT, VMONx INPUT

BUCKn_OV_THR / VMONn_OV_THR = 0x0,

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

5.1a

5.1b

5.1c

5.1d

5.1e

5.1f

2%

3%

4%

VMONn_RANGE_SEL = 0

BUCKn_OV_THR / VMONn_OV_THR = 0x1,

VMONn_RANGE_SEL = 0

2.5% 3.5% 4.5%

BUCKn_OV_THR / VMONn_OV_THR = 0x2,

VMONn_RANGE_SEL = 0

3%

4%

5%

6%

7%

4%

5%

6%

7%

8%

5%

6%

Overvoltage monitoring for

buck output and VMONx pin

input, programable threshold

BUCKn_OV_THR / VMONn_OV_THR = 0x3,

VMONn_RANGE_SEL = 0

V_{BUCK_OV_TH}

V_{VMON_OV_TH}

,

BUCKn_OV_THR / VMONn_OV_THR = 0x4,

VMONn_RANGE_SEL = 0

accuracy, V_{OUT_Bx}/ V_VMONx

>

7%

1 V⁽¹⁾

BUCKn_OV_THR / VMONn_OV_THR = 0x5,

VMONn_RANGE_SEL = 0

8%

BUCKn_OV_THR / VMONn_OV_THR = 0x6,

VMONn_RANGE_SEL = 0

5.1g

5.1h

9%

BUCKn_OV_THR / VMONn_OV_THR = 0x7,

VMONn_RANGE_SEL = 0

9% 10%

11%

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6.8 Monitoring Functions (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGNDx ground of the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

BUCKn_OV_THR / VMONn_OV_THR = 0x0,

VMONn_RANGE_SEL = 0

5.2a

20

30

35

40

45

BUCKn_OV_THR / VMONn_OV_THR = 0x1,

VMONn_RANGE_SEL = 0

5.2b

5.2c

5.2d

5.2e

5.2f

25

30

40

50

60

70

90

BUCKn_OV_THR / VMONn_OV_THR = 0x2,

VMONn_RANGE_SEL = 0

40

50

Overvoltage monitoring for

buck output and VMONx pin

input, programable threshold

BUCKn_OV_THR / VMONn_OV_THR = 0x3,

VMONn_RANGE_SEL = 0

V_{BUCK_OV_TH_}

50

60

,

mv

mV

V_{VMON_OV_TH_}

BUCKn_OV_THR / VMONn_OV_THR = 0x4,

VMONn_RANGE_SEL = 0

accuracy, V_{OUT_Bx}

_VMONx≤1 V⁽¹⁾

/

60

70

mv

V

BUCKn_OV_THR / VMONn_OV_THR = 0x5,

VMONn_RANGE_SEL = 0

70

80

BUCKn_OV_THR / VMONn_OV_THR = 0x6,

VMONn_RANGE_SEL = 0

5.2g

5.2h

5.3a

5.3b

5.3c

5.3d

5.3e

5.3f

80

90

BUCKn_OV_THR / VMONn_OV_THR = 0x7,

VMONn_RANGE_SEL = 0

100

110

BUCKn_UV_THR / VMONn_UV_THR = 0x0,

VMONn_RANGE_SEL = 0

–4% –3% –2%

BUCKn_UV_THR / VMONn_UV_THR = 0x1,

VMONn_RANGE_SEL = 0

–

4.5% 3.5% 2.5%

BUCKn_UV_THR / VMONn_UV_THR = 0x2,

VMONn_RANGE_SEL = 0

–5% –4% –3%

Undervoltage monitoring for

buck output and VMONx pin

input, programable threshold

BUCKn_UV_THR / VMONn_UV_THR = 0x3,

VMONn_RANGE_SEL = 0

–6% –5% –4%

–7% –6% –5%

–8% –7% –6%

V_{BUCK_UV_TH}

V_{VMON_UV_TH}

,

BUCKn_UV_THR / VMONn_UV_THR = 0x4,

VMONn_RANGE_SEL = 0

accuracy, V_{OUT_Bx}/ V_VMONx

>

1 V⁽¹⁾

BUCKn_UV_THR / VMONn_UV_THR = 0x5,

VMONn_RANGE_SEL = 0

BUCKn_UV_THR / VMONn_UV_THR = 0x6,

VMONn_RANGE_SEL = 0

5.3g

5.3h

5.4a

5.4b

5.4c

5.4d

5.4e

5.4f

–9% –8% –7%

BUCKn_UV_THR / VMONn_UV_THR = 0x7,

VMONn_RANGE_SEL = 0

–

10%

–11%

–9%

BUCKn_UV_THR / VMONn_UV_THR = 0x0,

VMONn_RANGE_SEL = 0

–40 –30 –20

–45 –35 –25

–50 –40 –30

–60 –50 –40

–70 –60 –50

–80 –70 –60

–90 –80 –70

–110 –100 –90

BUCKn_UV_THR / VMONn_UV_THR = 0x1,

VMONn_RANGE_SEL = 0

BUCKn_UV_THR / VMONn_UV_THR = 0x2,

VMONn_RANGE_SEL = 0

Undervoltage monitoring for

buck output and VMONx pin

input, programable threshold

BUCKn_UV_THR / VMONn_UV_THR = 0x3,

VMONn_RANGE_SEL = 0

V_{BUCK_UV_TH_}

,

mv

mV

V_{VMON_UV_TH_}

BUCKn_UV_THR / VMONn_UV_THR = 0x4,

VMONn_RANGE_SEL = 0

accuracy, V_{OUT_Bx}

_VMONx≤1 V⁽¹⁾

/

mv

V

BUCKn_UV_THR / VMONn_UV_THR = 0x5,

VMONn_RANGE_SEL = 0

BUCKn_UV_THR / VMONn_UV_THR = 0x6,

VMONn_RANGE_SEL = 0

5.4g

5.4h

BUCKn_UV_THR / VMONn_UV_THR = 0x7,

VMONn_RANGE_SEL = 0

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6.8 Monitoring Functions (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGNDx ground of the device.

POS

5.5a

5.5b

5.5c

5.5d

5.5e

5.5f

PARAMETER

TEST CONDITIONS

MIN

100

125

150

200

250

300

350

450

TYP MAX UNIT

VMONn_OV_THR = 0x0, VMONn_RANGE_SEL = 1

VMONn_OV_THR = 0x1, VMONn_RANGE_SEL = 1

VMONn_OV_THR = 0x2, VMONn_RANGE_SEL = 1

VMONn_OV_THR = 0x3, VMONn_RANGE_SEL = 1

VMONn_OV_THR = 0x4, VMONn_RANGE_SEL = 1

VMONn_OV_THR = 0x5, VMONn_RANGE_SEL = 1

VMONn_OV_THR = 0x6, VMONn_RANGE_SEL = 1

VMONn_OV_THR = 0x7, VMONn_RANGE_SEL = 1

VMONn_UV_THR = 0x0, VMONn_RANGE_SEL = 1

VMONn_UV_THR = 0x1, VMONn_RANGE_SEL = 1

VMONn_UV_THR = 0x2, VMONn_RANGE_SEL = 1

VMONn_UV_THR = 0x3, VMONn_RANGE_SEL = 1

VMONn_UV_THR = 0x4, VMONn_RANGE_SEL = 1

VMONn_UV_THR = 0x5, VMONn_RANGE_SEL = 1

VMONn_UV_THR = 0x6, VMONn_RANGE_SEL = 1

VMONn_UV_THR = 0x7, VMONn_RANGE_SEL = 1

150

175

200

250

300

350

400

500

200

225

250

300

350

400

450

550

Overvoltage monitoring for

V_{VMON_OV_TH2}VMONx pin input with

extended range⁽¹⁾

mV

5.5g

5.5h

5.6a

5.6b

5.6c

5.6d

5.6e

5.6f

-200 -150 -100

-225 -175 -125

-250 -200 -150

-300 -250 -200

-350 -300 -250

-400 -350 -300

-450 -400 -350

-550 -500 -450

Undervoltage monitoring for

V_{VMON_UV_TH2}VMONx pin input with

extended range⁽¹⁾

mV

5.6g

5.6h

Threshold voltage for

V_{TH_RV(VMON)}Residual Voltage Detection at

VMONx pins

5.6i

140

150

160 mV

Electrical Characteristics: VCCA INPUT

5.7a

5.7b

5.7c

VCCA_OV_THR = 0x0

VCCA_OV_THR = 0x1

VCCA_OV_THR = 0x2

VCCA_OV_THR = 0x3

VCCA_OV_THR = 0x4

VCCA_OV_THR = 0x5

VCCA_OV_THR = 0x6

VCCA_OV_THR = 0x7

VCCA_UV_THR = 0x0

VCCA_UV_THR = 0x1

VCCA_UV_THR = 0x2

VCCA_UV_THR = 0x3

VCCA_UV_THR = 0x4

VCCA_UV_THR = 0x5

VCCA_UV_THR = 0x6

VCCA_UV_THR = 0x7

2%

3%

4%

2.5% 3.5% 4.5%

3%

4%

5%

6%

7%

4%

5%

6%

7%

8%

5%

6%

Overvoltage monitoring for

5.7d

5.7e

5.7f

VCCA_{OV_TH}

VCCA input, programable

threshold accuracy⁽²⁾

7%

8%

5.7g

5.7h

5.8a

5.8b

5.8c

5.8d

5.8e

5.8f

9%

9% 10%

-4% -3%

11%

-2%

-4.5% -3.5% -2.5%

-5%

-6%

-7%

-8%

-9%

-4%

-5%

-6%

-7%

-8%

-3%

-4%

-5%

-6%

-7%

-9%

Undervoltage monitoring for

VCCA input, programable

threshold accuracy⁽²⁾

VCCA_{UV_TH}

5.8g

5.8h

-11% -10%

Timing Requirements

BUCK and VMON OV/UV

detection delay

Detection delay with 5mV (V_in≤1 V) or 0.5% (V_in

1 V) over/underdrive

>

5.9a

5.9b

t_{delay_OV_UV}

8

µs

t_{delay_VCCA_OV}

VCCA OV/UV detection delay Detection delay with 30mV over/underdrive

_UV

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6.8 Monitoring Functions (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGNDx ground of the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

VMON_DEGLITCH_SEL is 0.5 µs: Digital deglitch

time for detected signal

5.10a t_{deglitch0_OV_UV}

0.5

3.8

20

1

VCCA, BUCK and VMON

OV/UV signal deglitch time

VMON_DEGLITCH_SEL is 4 µs: Digital deglitch time

for detected signal

5.10b t_{deglitch1_OV_UV}

5.10c t_{deglitch2_OV_UV}

3.4

18

4.2 µs

22

VMON_DEGLITCH_SEL is 20 µs: Digital deglitch

time for detected signal

VMON_DEGLITCH_SEL is 0.5 µs: Total delay

from 5mV (V_in≤1 V) or 0.5% (V_in> 1 V) over/

underdrive to interrupt or PFSM trigger

5.11a t_{latency0_OV_UV}

5.11b t_{latency1_OV_UV}

5.11c t_{latency2_OV_UV}

9

VMON_DEGLITCH_SEL is 4 µs: Total delay

from 5mV (V_in≤1 V) or 0.5% (V_in> 1 V) over/

underdrive to interrupt or PFSM trigger

BUCK and VMON OV/UV

signal latency time

13 µs

VMON_DEGLITCH_SEL is 20 µs: Total delay

from 5mV (V_in≤1 V) or 0.5% (V_in> 1 V) over/

underdrive to interrupt or PFSM trigger

30

t_{latency0_VCCA_}

VMON_DEGLITCH_SEL is 0.5 µs: Total delay from

30mV over/underdrive to interrupt or PFSM trigger

5.11d

9

OV_UV

t_{latency1_VCCA_}VCCA OV/UV signal latency VMON_DEGLITCH_SEL is 4 µs: Total delay from

5.11e

5.11f

13 µs

30

time

30mV over/underdrive to interrupt or PFSM trigger

OV_UV

t_{latency2_VCCA_}

VMON_DEGLITCH_SEL is 20 µs: Total delay from

30mV over/underdrive to interrupt or PFSM trigger

OV_UV

t_{deglitch_PGOOD}

5.12a

5.12b

Input signal transition from invalid to valid

Input signal transition from valid to invalid

9.5

10.5

_rise

PGOOD signal additional

deglitch time

µs

t_{deglitch_PGOOD}

0

_fall

(1) The default values of BUCKn_OV_THR, BUCKn_UV_THR, VMONn_OV_THR and VMONn_UV_THR registers come from the NVM

memory, and can be re-programmed by software.

(2) The default values of VCCA_OV_THR and VCCA_UV_THR registers come from the NVM memory, and can be re-programmed by

software.

6.9 Clocks, Oscillators, and DPLL

Over operating free-air temperature range (unless otherwise noted).

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Switching Characteristics: 20-MHz and 128-kHz RC OSCILLATOR CLOCK

20 MHz RC Oscillator output

frequency

6.2

19

20

21 MHz

135 kHz

128 kHz RC Oscillator output

frequency

6.4

121

128

Switching Characteristics: DPLL, SYNCCLKIN, and SYNCCLKOUT

6.6a

6.6b

6.6c

6.6d

6.7a

6.7b

6.7c

EXT_CLK_FREQ = 0x0

EXT_CLK_FREQ = 0x1

EXT_CLK_FREQ = 0x2

EXT_CLK_FREQ = 0x3

SS_DEPTH = 0x0 (Spread-spectrum disabled)

SS_DEPTH = 0x1

1.1

2.2

4.4

8.8

External input clock nominal

frequency

MHz

18%

10%

8%

–18%

–10%

–8%

External input clock required

accuracy from nominal

frequency

SS_DEPTH = 0x2

Logic low time for SYNCCLKIN

clock

6.8a

6.8b

6.9a

40

ns

Logic high time for

SYNCCLKIN clock

External clock detection delay

for missing clock detection

1.8

µs

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6.9 Clocks, Oscillators, and DPLL (continued)

Over operating free-air temperature range (unless otherwise noted).

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Clock change delay (internal to

external)

6.10

Delay from valid clock detection to use of external clock

600

µs

6.11a

6.11b

6.11c

6.12

SYNCCLKOUT_FREQ_SEL = 0x1

SYNCCLKOUT_FREQ_SEL = 0x2

SYNCCLKOUT_FREQ_SEL = 0x3

Cycle-to-cycle

1.1

2.2

SYNCCLKOUT clock nominal

frequency

MHz

4.4

SYNCCLKOUT duty-cycle

40%

5

50%

60%

SYNCCLKOUT output buffer

external load

6.13

T_J= 25°C

35

50

pF

6.15a

6.15b

SS_DEPTH = 0x1

SS_DEPTH = 0x2

±6.3%

±8.4%

Spread spectrum variation

from nominal frequency

Timing Requirements: Clock Monitors

6.17a

Failure on 20 MHz system clock

10

40

µs

Clock Monitor Failure signal

latency from detection

t_{latency_CLKfail}

6.17b

6.18

6.19

6.20

Failure on 128 kHz monitoring clock

Clock Monitor Drift signal

latency from detection

t_{latency_CLKdrift}

f_sysclk

115

µs

Internal system clock

19

20

21 MHz

20%

Threshold for internal system

clock frequency drift detection

CLKdrift_TH

-20%

Threshold for internal system

clock stuck at high or stuck at

low detection

6.21

CLKfail_TH

10 MHz

6.10 Thermal Monitoring and Shutdown

Over operating free-air temperature range (unless otherwise noted).

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics

7.1a

7.1b

7.2a

7.2b

7.2c

7.2d

T_{WARN_0}

TWARN_LEVEL = 0

120

130

135

130

140

145

10

140

°C

Thermal warning threshold (no

hysteresis)

T_{WARN_1}

TWARN_LEVEL = 1

150

T_{SD_orderly_0}

T_{SD_orderly_1}

TSD_ORD_LEVEL = 0

TSD_ORD_LEVEL = 1

TSD_ORD_LEVEL = 0

TSD_ORD_LEVEL = 1

150

°C

155

Thermal orderly shutdown

rising threshold

Thermal orderly shutdown

hysteresis

°C

5

Thermal immediate shutdown

rising threshold

7.3a

7.3b

T_{SD_imm}

140

150

5

160

425

°C

Thermal immediate shutdown

hysteresis

Timing Requirements

TSD signal latency from

detection

7.4

t_{latency_TSD}

µs

6.11 System Control Thresholds

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGNDx ground of the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics

VCCA UVLO/POR falling

threshold

8.1a

8.1b

V_{POR_Falling}

V_{POR_Rising}

Measured on VCCA pin, trimmed

2.7

2.75

2.8

3

V

VCCA UVLO/POR rising

threshold

Measured on VCCA pin, untrimmed

Measured on VCCA pin, trimmed

8.1c

8.2a

8.2b

V_{POR_Hyst}

V_{OVP_Rising}

V_{OVP_Hyst}

VCCA UVLO/POR hysteresis

VCCA OVP rising threshold

VCCA OVP hysteresis

100

5.7

50

mV

V

5.6

5.8

mV

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6.11 System Control Thresholds (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGNDx ground of the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Timing Requirements

t_{latency_VCCAOV}VCCA_OVP signal latency

8.3

8.6

8.8

15

10

12

µs

from detection

P

t_{latency_VCCAUVL}VCCA_UVLO signal latency

from detection

O

LDOVINT OVP and UVLO

t_{latency_VINT}

With 25-mV over/underdrive

signal latency from detection

Device initialization time to

t_{INIT_REF_CLK_L}

8.12a

start up references, LDOVINT From NO SUPPLY state

and EEPROM LDO

2.2

ms

DO

Device initialization time to

8.12b t_{INIT_LDO}

start up references and

EEPROM LDO

From LP_STANDBY state

0.95

Device initialization time to

t_{INIT_NVM_ANAL}load default values for NVM

8.13

0.6

ms

programmable registers and

OG

use trimmed values

8.11

8.10

t_LBISTrun

t_ABISTrun

Run time for LBIST

Run time for ABIST

FAST_BIST=0

1.4

ms

Stand-alone device⁽¹⁾

0.25

(1) SPMI BIST is part of ABIST and can increase the time for devices in multi-PMIC platforms.

6.12 Current Consumption

Over operating free-air temperature range (unless otherwise noted).

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics

From VCCA and PVIN_Bx pins. VCCA OV/UV

monitoring disabled. VCCA = PVIN_Bx = 3.3 V. VIO =

0V. T_J= 25℃

9.2a

9.2b

I_{STANDBY_3V3}

34

36

Standby current consumption

µA

From VCCA and PVIN_Bx pins. VCCA OV/UV

monitoring disabled. VCCA = PVIN_Bx = 5.0 V. VIO =

0V. T_J= 25℃

I_{STANDBY_5V0}

From VCCA and PVIN_Bx pins. One buck regulator

enabled in PFM/PWM mode. Buck and VCCA OV/UV

monitoring enabled. VCCA = PVIN_Bx = VIO = 3.3 V.

T_J= 25℃

9.3a

9.3b

9.4a

9.4b

I_{SLEEP_3V3}

310

315

82

Sleep current consumption

µA

From VCCA and PVIN_Bx pins. One buck regulator

enabled in PFM/PWM mode. Buck and VCCA OV/UV

monitoring enabled. VCCA = PVIN_Bx = 5.0 V. VIO =

3.3V. T_J= 25℃

I_{SLEEP_5V0}

From VCCA and PVIN_Bx pins. VCCA = PVIN_Bx =

VIO = 3.3 V. Fsw = 4.4 MHz. All buck regulators are

enabled in forced PWM mode with no load. All buck and

VCCA OV/UV monitoring enabled. T_J= 25℃

I_{ACTIVE_3V3_4M4}

Active current consumption

during PWM operation

mA

From VCCA and PVIN_Bx pins. VCCA = PVIN_Bx =

5.0 V. VIO = 3.3V. Fsw = 4.4 MHz. All buck regulators

are enabled in forced PWM mode with no load. All buck

and VCCA OV/UV monitoring enabled. T_J= 25℃

I_{ACTIVE_5V0_4M4}

110

From VCCA and PVIN_Bx pins. VCCA = PVIN_Bx =

VIO = 3.3 V. Fsw = 2.2 MHz. 4-phase configuration.

Buck regulator is enabled in forced PWM mode with no

load. Buck and VCCA OV/UV monitoring enabled. T_J=

25℃

9.4c

9.4d

I_{ACTIVE_3V3_2M2}

15

19

Active current consumption

during PWM operation

mA

From VCCA and PVIN_Bx pins. VCCA = PVIN_Bx =

5.0 V. VIO = 3.3 V. Fsw = 2.2 MHz. 4-phase

configuration. Buck regulator is enabled in forced PWM

mode with no load. Buck and VCCA OV/UV monitoring

enabled. T_J= 25℃

I_{ACTIVE_5V0_2M2}

28

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6.13 Digital Input Signal Parameters

Over operating free-air temperature range, VIO refers to the VIO pin, VCCA refers to the VCCA pin (unless otherwise noted).

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics: All Digital Input Signals in GPIOx, SCL_I2C1, SDA_I2C1, SCK_SPI, SDI_SPI

10.1

10.2

10.3

V_IL

V_IH

Low-level input voltage

High-level input voltage

Hysteresis

0.54

V

1.26

150

mV

Timing Requirements: ENABLE

10.4

10.5

t_{degl_ENABLE}

t_{degl_nSLEEPx}

ENABLE signal deglitch time

nSLEEPx signal deglitch time

GPIOx_DEGLITCH_EN = 1

6

8

10

µs

Timing Requirements: GPIOx

10.6

10.7

t_{degl_ESMx}

t_{WD_pulse}

nERR signal deglitch time

13

24

15

30

17

36

µs

TRIG_WDOG input signal

deglitch time

GPIx, WKUPx signal deglitch

time

10.8

10.9

t_{degl_GPIx}

GPIOx_DEGLITCH_EN = 1

GPIOx_DEGLITCH_EN = 0

6

8

10

µs

ns

Minimum pulse width for GPIx,

WKUPx

t_{no_degl_PW}

200

6.14 Digital Output Signal Parameters

Over operating free-air temperature range, VIO refers to the VIO pin, VLDO refers to the LDO_VOUT pin, VCCA refers to the

VCCA pin (unless otherwise noted).

POS

Electrical Characteristics: nINT, SDA_I2Cx

11.1 V_{OL_20mA}Low-level output voltage

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

I_OL= 20 mA

0

0.4

V

Electrical Characteristics: EN_DRV(GPIO1), PGOOD(GPIO1), nRSTOUT_SOC(GPIO1), SDO_SPI, nRSTOUT_SOC(GPIO5), SYNCCLKOUT(GPIO5),

nRSTOUT(GPIO10) and GPIO Output Signals through GPIO1, GPIO3, GPIO5 and GPIO10 pins

Low-level output voltage, push-

pull and open-drain

11.2

11.3

V_{OL_20mA}

V_OH(VIO)

I_OL= 20 mA

I_OH= 3 mA

0

0.4

V

High-level output voltage,

push-pull

VIO

VIO –0.4

Electrical Characteristics: PGOOD(GPIO6), SYNCCLKOUT(GPIO6) and GPIO Output Signals through GPIO2, GPIO6 pins

Low-level output voltage, push-

pull and open-drain

11.4

11.5

V_{OL_3mA}

V_OH(VIO)

I_OL= 3 mA

I_OH= 3 mA

0

0.4

V

High-level output voltage,

push-pull

VIO

VIO –0.4

Electrical Characteristics: SCLK_SPMI(GPIO8), SDATA_SPMI(GPIO9), PGOOD(GPIO9) and GPIO Output Signals through GPIO8 and GPIO9 pins

Low-level output voltage, push-

pull and open-drain

11.6

11.7

V_{OL_20mA}

V_OH(VINT)

I_OL= 20 mA

I_OH= 3 mA

0

0.4

V

High-level output voltage,

push-pull

1.4

VLDO

Electrical Characteristics: GPIO Output Signals through GPIO4 and GPIO7 pins

Low-level output voltage, push-

pull

11.8

11.9

V_{OL_3mA}

I_OL= 3 mA

I_OH= 3 mA

0

0.4

VLDO

VCCA

V

High-level output voltage,

push-pull

V_OH(VINT)

1.4

High-level output voltage,

push-pull

VCCA -

0.4

EN_DRV pin, 10 kΩ internal pull-up, 3.135 V < V_VIO

V_VCCAno load

≤

11.9b V_OH(VCCA)

Timing Requirements

11.10 t_{gate_readback}

Gating time for readback

monitor

Signal level change or GPIO selection (GPIOn_SEL)

8.3

10.3

µs

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6.15 I/O Pullup and Pulldown Resistance

Over operating free-air temperature range, VIO refers to the VIO_IN pin, VCCA refers to the VCCA pin (unless otherwise

noted).

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics

GPIO4, GPIO7, GPIO8 and GPIO9 pins with internal

pullup to VOUT_LDO

12.2

R_{PU_GPIO}

IO signals pullup resistance

280

400

520

kΩ

GPIO1, GPIO2, GPIO3, GPIO5, GPIO6 and GPIO10

pins with internal pullup to VIO

12.3

12.4

12.5

R_{PU_GPIO}

R_{PD_GPIO}

280

8

400

10

520

12

kΩ

IO signals pulldown resistance GPIO1 - 10 pins with internal pulldown to ground

Internal pullup to VIO supply when output driven high in

push-pull configuration

R_{PU_NRSTOUT}nRSTOUT pullup resistance

R_{PU_NRSTOUT_}nRSTOUT_SOC pullup

Internal pullup to VIO supply when output driven high in

push-pull configuration

12.6

12.7

8

10

12

kΩ

resistance

SOC

R_{PU_EN_DRV}

EN_DRV pullup resistance

Internal pullup to VCCA supply when output driven high

6.16 I²C Interface

Over operating free-air temperature range (unless otherwise noted). Device supports standard mode (100 kHz), fast mode

(400 kHz), and fast mode+ (1 MHz) when VIO is 3.3 V or 1.8 V, and high-speed mode (3.4 MHz) only when VIO is 1.8 V.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Electrical Characteristics

Capacitive load for SDA

and SCL

13.1

C_B

400

pF

Timing Requirements

13.2a

13.2b

Standard mode

100

400

1

kHz

Fast mode

13.2c

13.2d

13.2e

13.3a

13.3b

Serial clock frequency

Fast mode+

ƒ_SCL

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

3.4

1.7

MHz

4.7

1.3

0.5

160

320

4

Fast mode

µs

ns

µs

ns

13.3c t_LOW

13.3d

SCL low time

Fast mode+

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

13.3e

13.4a

13.4b

Fast mode

0.6

0.26

60

13.4c t_HIGH

13.4d

SCL high time

Data setup time

Data hold time

Fast mode+

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

13.4e

120

250

100

50

13.5a

13.5b

Fast mode

t_SU;DAT

ns

13.5c

Fast mode+

13.5d

High-speed mode

Standard mode

10

13.6a

10

3450

900

13.6b

Fast mode

10

ns

13.6c t_HD;DAT

13.6d

Fast mode+

10

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

10

70

13.6e

10

150

13.7a

4.7

0.6

0.26

160

Setup time for a start or

a REPEATED START

condition

13.7b

t_SU;STA

13.7c

Fast mode

µs

ns

Fast mode+

13.7d

High-speed mode

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6.16 I²C Interface (continued)

Over operating free-air temperature range (unless otherwise noted). Device supports standard mode (100 kHz), fast mode

(400 kHz), and fast mode+ (1 MHz) when VIO is 3.3 V or 1.8 V, and high-speed mode (3.4 MHz) only when VIO is 1.8 V.

POS

13.8a

13.8b

13.8c

13.8d

13.9a

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Standard mode

4

Hold time for a start or a

REPEATED START

condition

Fast mode

0.6

0.26

160

4.7

1.3

0.5

4

µs

t_HD;STA

Fast mode+

High-speed mode

Standard mode

Fast mode

ns

Bus free time between a

STOP and START

condition

13.9b t_BUF

13.9c

µs

Fast mode+

13.10a

Standard mode

Fast mode

13.10b

0.6

0.26

160

µs

ns

Setup time for a STOP

condition

t_SU;STO

13.10c

Fast mode+

13.10d

High-speed mode

Standard mode

Fast mode

13.11a

1000

300

120

80

13.11b

20

13.11c t_rDA

13.11d

Rise time of SDA signal Fast mode+

High-speed mode, C_b= 100 pF

ns

10

20

13.11e

High-speed mode, C_b= 400 pF

Standard mode

160

300

120

80

13.12a

13.12b

Fast mode

6.5

10

13.12c t_fDA

13.12d

Fall time of SDA signal Fast mode+

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

13.12e

13

160

1000

300

120

40

13.13a

13.13b

Fast mode

20

13.13c t_rCL

13.13d

Rise time of SCL signal Fast mode+

ns

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

10

20

10

13.13e

80

13.14a

Rise time of SCL signal High-speed mode, C_b= 100 pF

after a repeated start

condition and after an

acknowledge bit

Standard mode

Fast mode

80

t_rCL1

13.14b

High-speed mode, C_b= 400 pF

20

160

13.15a

300

120

40

13.15b

6.5

10

13.15c t_fCL

13.15d

Fall time of SCL signal

Fast mode+

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

13.15e

20

80

Pulse width of spike

suppressed (SCL and

SDA spikes that are less

than the indicated width

are suppressed)

Standard mode, fast mode, and fast

mode+

13.16a

50

10

t_SP

ns

13.16b

High-speed mode, C_b= 400 pf

6.17 Serial Peripheral Interface (SPI)

These specifications are ensured by design, V_VIO= 1.8 V or 3.3 V(unless otherwise noted).

POS

PARAMETERS

TEST CONDITIONS

MIN

NOM

MAX UNIT

Electrical Characteristics

15.1

Capacitive load on pin SDO

30

pF

Timing Requirements

15.2

15.3

15.4

1

2

3

Cycle time

200

150

ns

Enable lead time

Enable lag time

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These specifications are ensured by design, V_VIO= 1.8 V or 3.3 V(unless otherwise noted).

POS

15.5

15.6

15.7

15.8

15.9

PARAMETERS

TEST CONDITIONS

MIN

60

15

4

NOM

MAX UNIT

4

5

6

7

8

Clock low time

ns

Clock high time

Data setup time

Data hold time

Output data valid after SCLK falling

15.1

0a

V_VIO= 1.8 V

V_VIO= 3.3 V

60

ns

60

9

New output data valid after SCLK falling

15.1

0b

15.1

1

10

11

Disable time

30

ns

15.1

2

CS inactive time

100

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t_BUF

SDA

t_HD;STA

t_rCL

t_fDA

t_rDA

t_SP

t_LOW

t_fCL

SCL

t_HD;STA

t_SU;STA

t_SU;STO

t_HIGH

t_HD;DAT

S

t_SU;DAT

S

RS

P

START

REPEATED

START

STOP

START

图7-1. I²C Timing

11

CS

2

1

5

3

SCLK

4

6

7

MOSI

8

9

10

MISO Hi-Z

Hi-Z

图7-2. SPI Timing

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7 Typical Characteristics

Unless otherwise specified: T_A= 25°C, V_IN= 3.3 V, V_OUT= 1 V.

40

39

38

37

36

35

34

33

32

31

30

4

3

2

1

0

2.2MHz, Shedding

2.2MHz, Adding

4.4MHz, Shedding

4.4MHz, Adding

2.8

3.1

3.4

3.7

4

4.3

4.6

4.9

5.2

5.5

0

1

2

3

4

5

6

7

VCCA (V)

I_OUT(A)

图7-1. Quiescent Current Consumption vs Input Voltage

图7-2. Buck Phase Adding and Shedding

EN (1V/div)

V

_OUT200 mV/div

V

_OUT200 mV/div

Time (100 µs/div)

I_LOAD= 4A

图7-3. Buck Startup, 4-Phase 2.2 MHz Mode

I_LOAD= 4A

图7-4. Buck Shutdown, 4-Phase 2.2 MHz Mode

1.6

1.4

1.2

1

1.6

1.4

1.2

1

33 mV/µs

20 mV/µs

10 mV/µs

5 mV/µs

2.5 mV/µs

1.25 mV/µs

0.625 mV/µs

0.3125 mV/µs

33 mV/µs

20 mV/µs

10 mV/µs

5 mV/µs

2.5 mV/µs

1.25 mV/µs

0.625 mV/µs

0.3125 mV/µs

0.8

0.6

0.4

0.8

0.6

0.4

0

0.5

1

1.5

2

2.5

3

3.5

4

0

0.5

1

1.5

2

2.5

3

3.5

4

Time (ms)

No load

图7-5. Buck Ramp-up Slew Rate

图7-6. Buck Ramp-down Slew Rate

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7 Typical Characteristics (continued)

Unless otherwise specified: T_A= 25°C, V_IN= 3.3 V, V_OUT= 1 V.

1.6

1.4

1.2

1

1.6

1.4

1.2

1

no load

0.6ohm

0.8

0.6

0.4

0.6

no load

0.6ohm

0.4

0

0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2

Time (ms)

0

0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2

Time (ms)

Slew Rate 33mV/µs

图7-7. Buck Ramp-up Slew Rate

Slew Rate 33mV/µs

图7-8. Buck Ramp-down Slew Rate

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8 Detailed Description

8.1 Overview

The LP8764-Q1 device is a power-management integrated circuit (PMIC), available in a 32-pin, 0.5-mm pitch,

5.5-mm × 5-mm QFN HotRod package. The device is designed for powering embedded systems or system on

chip (SoC) in Automotive or Industrial applications. The device provides four configurable buck converter rails,

with ability to combine outputs in multi-phase mode. All converters can support up to 5-A per phase resulting up

to 20-A in four-phase configuration, 15-A in 3-phase configuration, and 10-A in dual-phase configuration. All

buck converters have the capability to sink up to 1 A, and support dynamic voltage scaling. Double buffered

voltage scaling registers enable each BUCK to transition to a different voltages during operation by SPI, I²C or

state transition. A DPLL enables the BUCK converters to synchronizing to an external clock input, with phase

delays between the output rails.

Two I²C interface channels or one SPI channel can be used to configure the power rails and the power state of

the LP8764-Q1 device. I²C channel 1 (I2C1) is the main channel with access to the registers that control the

configurable power sequencer, the states and the outputs of power rails, and the device operating states. I²C

channel 2 (I2C2), which is available through GPIO2 and GPIO3 pins, is dedicated for accessing the Q&A

Watchdog communication registers. When the SPI is configured instead of the two I²C interfaces, the SPI can

access all of the registers, including the Q&A Watchdog registers. An NVM option is available to enable I2C1 to

access all of the registers as well, including the Q&A Watchdog registers.

The LP8764-Q1 device includes an internal RC oscillator to sequence all resources during power up and power

down. An internal LDO (LDOVINT) generates the supply for the entire digital circuitry of the device as soon as

the external input supply is available through the VCCA input.

LP8764-Q1 device has ten GPIOs each with multiple functions and configurable features. All of the GPIOs, when

configured as a general purpose output pin, can be included in the power-up and power-down sequence and

used as enable signals for external resources. In addition, each GPIO can be configured as a wake-up input or a

sleep mode trigger. The default configuration of the GPIO port comes from the NVM memory, and can be re-

configured by software if the external connection permits.

The LP8764-Q1 device includes a Q&A watchdog to monitor software lockup, and a system error monitoring

input (nERR_MCU) with fault injection option to monitor the lock-step signal of the attached MCU. The device

includes protection and diagnostic mechanisms such as short-circuit protection, thermal monitoring and

shutdown. The PMIC can notify the processor of these events through the interrupt signal, allowing the

processor to take action in response.

An SPMI interface is included in the LP8764-Q1 device to distribute power state information to at most five

satellite PMICs, thus enabling synchronous power state transition across multiple PMICs in the application

system. This feature allows the consolidation of IO control signals from up to six PMICs powering the system into

one primary LP8764-Q1 PMIC.

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8.2 Functional Block Diagram

VCCA

VIO

ENABLE

Control

EN_DRV

Interface

Voltage monitoring

Windowed

Power-Good

Monitor

PGOOD

LDOVINT

SCL_I2C1/SCK_SPI

SDA_I2C1/SDI_SPI

SCL_I2C2, CS_SPI

VINT

_CCinternal

supply

I²C CNTRL,

or SPI

SYNCCLKOUT

V

Single or

Multi-Phase

SDA_I2C2, SDO_SPI

PVIN_B1

SW_B1

FB_B1

PGND

VCCA

Internal

Interrupt

events

EN

nINT

BUCK1

(AVS)

VSEL

RAMP

CLK1

RC

Oscillator

DPLL

(Phase

synchronization

and dither)

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

SYNCCLKIN

PVIN_B2

SW_B2

FB_B2

PGND

EN

VSEL

RAMP

CLK2

BUCK2

(AVS)

DFT

NVM Controller

NVM Memory

Registers

VCCA

VCCA_UVLO

VCCA

Pre-Configurable

Power Sequencer

Controller

PVIN_B3

SW_B3

FB_B3

PGND

EN

VSEL

RAMP

CLK3

BUCK3

(AVS)

VCCA_OVP

ECO

PWM

DVS

GPIO7

GPIO8

GPIO9

GPIO10

WKUPn

nSLEEPn

Default NVM Settings

PVIN_B4

SW_B4

FB_B4

PGND

EN

VSEL

RAMP

CLK4

BUCK4

(AVS)

Thermal

Monitoring and

Shutdown

Hot die detection

I2C2

SPI

Q&A WDT

nERR_MCU

Error Monitor

AGND1

AGND2

Internal supply

Reference

and Bias

REFOUT

Quiet Ground

Pins are shared with BUCK converters

图8-1. LP8764-Q1 Functional Block Diagram

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8.3 Input Voltage Monitor

The comparator module that monitors the voltage on the VCCA pins controls the power state machine of the

LP8764-Q1 device. The 图 8-2 shows a block diagram of the VCCA input voltage monitoring. VCCA voltage

detection outputs determine the power states of the device as following:

VCCA_UVLO When the voltage on the VCCA pin rises above VCCA_UVLO during initial power up, the

LP8764-Q1 device transitions from the NO SUPPLY state to the INIT state.

When the supply at the VCCA pin falls below the VCCA_UVLO threshold, the device returns to

the NO SUPPLY state and is completely shut down.

VCCA_OVP While the LP8764-Q1 device is in operation, if the voltage on VCCA pin rises above the

VCCA_OVP threshold, the device clears the ENABLE_DRV bit and start the immediate

shutdown sequence using pull-down resistors at the buck regulator outputs to protect itself from

over-voltage input condition.

When VCCA is expected to be 5 V or 3.3 V, a separate voltage comparator can be enabled to monitor whether

or not the VCCA voltage is within the expected range. Please refer to for additional detail on the operation of the

VCCA OV/UV monitor function.

VCCA

VSYS

Preregulator

External Protection

Safety

Band Gap

+

VCCA_UVLO

VCCA_OVP

œ

+

VCCA OVP and UVLO

Monitor

图8-2. VCCA Monitor

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8.4 Device State Machine

The LP8764-Q1 device integrates a finite state machine (FSM) engine that manages the state of the device

during operating state transitions. The device supports NVM-configurable mission states with configurable input

triggers for transitions between states. Any resources, including the 4 BUCK regulators, the VMONx voltage

monitors and all of the digital IO pins including the 10 GPIO pins on the device can be controlled during power

sequencing. When a resource is not controlled or configured through a power sequence, the resource is left in

the default state as pre-configured by the NVM.

Each resource can be pre-configured through the NVM configuration, or re-configured through register bits.

Therefore, the user can statically control the resource through the control interfaces (I²C or SPI), or the FSM can

automatically control the resource during state sequences.

The FSM is powered by an internal LDO that is automatically enabled when VCCA supply is available to the

device. Ensuring that the VCCA supply is the first supply available to the device is important to ensure proper

operation of all the power resources as well as the control interface and device IOs.

There are 3 parts of the FSM that control the operational modes of the LP8764-Q1 device:

• Fixed Device Power Finite State Machine (FFSM)

• Pre-configurable Finite State Machine (PFSM) for Mission States (ACTIVE, MCU_ONLY, S2R,

DEEP_SLEEP)

• Error Handling Operations

The PFSM provides configurable rail and voltage monitoring sequencing utilizing instructions in configuration

memory. This flexibility enables customers to alter power-up sequences on a platform basis. The FFSM handles

the majority of fixed functionality that is internally mandated and common to all platforms.

8.4.1 Fixed Device Power FSM

The Fixed Device Power portion of the FSM engine manages the power up of the device before the power rails

are fully enabled and ready to power external loadings, and the power down of the device when in the event of

insufficient power supply or device or system error conditions. While the device is in one of the Hardware Device

Powers states, the ENABLE_DRV bit remains low.

The definitions and transition triggers of the Device Power States are fixed and cannot be reconfigured.

Following are the definitions of the Device Power states:

NO SUPPLY

The device is not powered by a valid energy source on the system power rail. The device is

completely powered off.

LP_STANDBY The device can enter this state from a mission state after receiving a valid OFF request by

ENABLE pin or I2C trigger and the LP_STANDBY_SEL = 1. The internal LDO (LDOVINT) is

enabled and VCCA monitoring is disabled to minimize power dissipation. As the accurate

VCCA monitoring is disabled, the VCCA voltage must be above 1.7 V during LP_STANDBY

state, or stay below 1.7 V for minimum 20 ms to ensure that the digital is reset correctly. If this

requirement for VCCA cannot be met, STANDBY state must be used instead of

LP_STANDBY. The wake-up from LP_STANDBY state can be initiated by active edge on

ENABLE signal or by WKUPx pins.

INIT

The device is powered by a valid supply on the system power rail (VCCA ≥VCCA_UV). If the

device was previously in LP_STANDBY state, it has received an external wake-up signal at

the WKUP1/2 pins, or an On Request from the ENABLE pin. Device digital and monitor

circuits are powered up. The PMIC reads its internal NVM memory in this state and configures

default values to registers, IO configuration and FSM accordingly.

BOOT BIST

The device is running the built-in self-test routine that includes both the LBIST and the ABIST/

CRC. An option is available to shorten the device power up time from the NO_SUPPLY state

by setting the NVM bit FAST_BOOT_BIST = '1' to skip the LBIST. Software can also set the

FAST_BIST = '1' to skip LBIST after the device wakes up from the LP STANDBY state. When

the device arrives at this state from the SAFE_RECOVERY state, LBIST is automatically

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skipped if it has not previously failed. If LBIST failed, but passed after multiple re-tries before

exceeding the recovery counter limit, the device powers up normally. The following NVM bits

are additional options that can be set to disable parts of the ABIST/CRC tests if further

sequence time reduction is required:

• REG_CRC_EN = '0': disables the register map and SRAM CRC check

• VMON_ABIST_EN = '0': disables the ABIST for the VMON OV/UV function

备注

Note: the BIST tests are executed as parallel processes, and the longest process

determines the total BIST duration

RUNTIME BIST A request was received from the MCU to exercise a run-time built-in self-test

(RUNTIME_BIST) on the device. No rails are modified and all external signals, including all

I²C or SPI interface communications, are ignored during BIST. If the device passed BIST, it

resumes the previous operation. If the device failed BIST, it shuts down all of the regulator

outputs and proceed to the SAFE RECOVERY state. In order to avoid a register CRC error, all

register writes must be avoided after the request for the BIST operation until the device pulls

the nINT pin low to indicate the completion of BIST. The results of the BIST are indicated by

the BIST_PASS_INT or the BIST_FAIL_INT bits.

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SAFE

RECOVERY

The device meets the qualified error condition for immediate or ordered shutdown request. If

the error is recovered within the recovery time interval or meets the restart condition, the

device increments the recovery counter, and returns to INIT state if the recovery counter value

does not exceed the threshold value. Until a supply power cycle occurs, the device stays in

the SAFE RECOVERY state if one of the following conditions occur:

• the recovery counter exceeds the threshold value

• the die temperature cannot be reduced to less than T_WARNlevel

• VCCA stays above OVP threshold

When multiple system conditions occur simultaneously that demand power state arbitration, the device goes to

the higher priority state according to the following priority order:

1. NO SUPPLY

2. SAFE_RECOVERY

3. LP_STANDBY

4. MISSION STATES

图8-3 shows the power transition states of the FSM engine.

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NO

VCCA < VCCA_UVLO

SUPPLY

or LDOVINT UVLO Condi on

All States

VCCA > VCCA_UV

LP STANDBY

LP_STANDBY_SEL = 1 and

Valid WAKE request¹

no valid WAKE request¹

INIT

INIT done and

no error detected

Error recovered or

meets restart condi on

O

request and

All States

Recovery

counter exceeded

LP_STANDBY_SEL = 1

Thermal Shutdown or

VCCA OVP

Error Condi ons

(recovery cnt +1)

SAFE

RECOVERY

BOOT

BIST

BOOT BIST error

(recovery cnt +1)

Orderly shutdown

Condi on

(recovery cnt +1)

BOOT BIST success

Severe or Moderate

PFSM Errors

(recovery cnt +1)

Mission States

RUNTIME BIST request

RUNTIME BIST complete

RUNTIME

BIST

¹A valid WAKE request consist of:

ꢀꢁENABLE high level if the device arrived the LP_STANDBY state through a low level at the

ENABLE pin, or

ꢀꢁLWKUP1 or WKUP2 detec on if the device arrived the LP_STANDBY state through wri ng to a

TRIGGER_I2C_0 bit, or

ꢀꢁSPMI wake-up event

图8-3. State Diagram for Device Power States

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8.4.1.1 Register Resets and EEPROM read at INIT state

When the device transitions from LP_STANDBY to INIT state, the registers are reset and EEPROM is read

based on FIRST_STARTUP_DONE and SKIP_LP_STANDBY_EE_READ bits. At the transition from SAFE

RECOVERY to INIT, the SKIP_LP_STANDBY_EE_READ bit is ignored as shown in the table.

表8-1. Register resets and EEPROM read at INIT state

SKIP_LP_STANDBY_EE

State transition

FIRST_STARTUP_DONE

conf_registers

No changes

other registers

_READ

Don't care

1

0

No changes

LP_STANDBY →INIT

Reset and defaults

read from EEPROM

0

1

0

Reset and defaults read

from EEPROM

Reset and defaults

read from EEPROM

LP_STANDBY →INIT

SAFE RECOVERY →INIT

Don't care

Reset and defaults

read from EEPROM

No changes

Reset and defaults read

from EEPROM

Reset and defaults

read from EEPROM

The conf_registers are:

• ENABLE_POL bit in the ENABLE_CONF register

• FSD_MASK, ENABLE_MASK bits in the MASK_STARTUP register

• FIRST_STARTUP_DONE, STARTUP_DEST, FAST_BIST, LP_STANDBY_SEL, and

SKIP_LP_STANDBY_EE_READ bits in the STARTUP_CTRL register

• SCRATCH_PAD_x bits in the SCRATCH_PAD_REG_x registers

• PFSM_DELAYx bits in the PFSM_DELAY_REG_x registers

8.4.2 Pre-Configurable Mission States

When the device arrives at a mission state, all rail sequencing is controlled by the pre-configurable FSM engine

(PFSM) through the configuration memory. The configuration memory allows configurations of the triggers and

the operation states that together form the configurable sub state machine within the scope of mission states.

This sub state machine can be used to control and sequence the different voltage outputs as well as any GPIO

outputs that can be used as enable for external rails. When the device is in a mission state, it has the capacity to

supply the processor and other platform modules depending on the power rail configuration. The definitions and

transition triggers of the mission states are configurable through the NVM configuration. Unlike the user

registers, the PFSM definition stored in the NVM cannot be modified during normal operation. When the PMIC

determines that a transition to another operation state is necessary, it reads the configuration memory to

determine what sequencing is needed for the state transition.

表 8-5 shows how the trigger signals for each state transition can come from a variety of interface or GPIO

inputs, or potential error sources. 图8-4 shows how the device processes all of the possible error sources inside

the PFSM engine, a hierarchical mask system is applied to filter out the common errors that can be handled by

interrupt only, and categorize the other error sources as Severe Global Error, Moderate Global Error, and so

forth. The filtered and categorized triggers are sent into the PFSM engine, that then determines the entry and

exit condition for each configured mission state.

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All Potential Error (Interrupt) Sources

INTERRUPT

is given

First level mask to filter out non-error interrupts vs. interrupts which require error handling

VCCA BUCK1 BUCK2 BUCK3 BUCK4 VMON1 VMON2

Recovery Counter Limit to FSM

OR

function

WD error to FSM

Severe Global

Error

MCU Rail Group

SoC Rail Group

Other Rail Group

MCU Error Monitor to FSM

Mask

Moderate Global

Error

IMMEDIATE

SHUTDOWN trigger

input to FSM

Immediate Shutdown Trigger Mask

ORDERLY

SHUTDOWN trigger

input to FSM

Orderly Shutdown Trigger Mask

MCU Power Error Trigger Mask

SoC Power Error Trigger Mask

MCU Power

Error Signal

SoC Power

Error Signal

图8-4. Error Source Hierarchical Mask System

图 8-6 shows an example of how the PFSM engine utilizes instructions to execute the configured device state

and sequence transitions of the mission state-machine. 表8-2 provides the instruction set and usage description

of each instruction in the following sections. 节 8.4.2.2 describes how the instructions are stored in the NVM

memory.

表8-2. Configurable FSM Instruction set

Command Opcode

"0000"

Command

REG_WRITE_MASK_PAGE0_IMM

REG_WRITE_IMM

Command Description

Write the specified data, except the masked bits, to the specified

page 0 register address.

"0001"

Write the specified data to the specified register address.

Write the specified data, except the masked bits, to the specified

register address.

"0010"

REG_WRITE_MASK_IMM

Write the target voltage of a specified regulator after a specified

delay.

"0011"

"0100"

"0101"

"0110"

REG_WRITE_VOUT_IMM

REG_WRITE_VCTRL_IMM

REG_WRITE_MASK_SREG

SREG_READ_REG

Write the operation mode of a specified regulator after a specified

delay.

Write the data from a scratch register, except the masked bits, to

the specified register address.

Write scratch register (REG0-3) with data from a specified

address.

Execution is paused until the specified type of the condition is met

or timed out.

"0111"

"1000"

"1001"

WAIT

DELAY_IMM

DELAY_SREG

Delay the execution by a specified time.

Delay the execution by a time value stored in the specified scratch

register.

Set a trigger destination address for a given input signal or

condition.

"1010"

TRIG_SET

"1011"

"1100"

TRIG_MASK

END

Sets a trigger mask that determines which triggers are active.

Mark the final instruction in a sequential task.

Write the specified data to the BIT_SEL location of the specified

page 0 register address.

"1101"

REG_WRITE_BIT_PAGE0_IMM

Write the specified data to the SHIFT location of the specified

page 0 register address.

"1110"

"1111"

REG_WRITE_WIN_PAGE0_IMM

SREG_WRITE_IMM

Write the specified data to the scratch register (REG0-3).

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8.4.2.1 PFSM Commands

Following section describes each PFSM command in detail and provides example usage codes. More

information on example NVM configuration, available device options and documentations can be found at Fully

Customizable Integrated Power.

8.4.2.1.1 REG_WRITE_IMM Command

Description: Write the specified data to the specified register address

Assembly command: REG_WRITE_IMM [ADDR=]<Address> [DATA=]<Data>

Address and Data can be in any literal integer format (decimal, hex, and so forth).

'ADDR=' and 'DATA=' are optional. When included, the parameters can be in any order.

Examples:

• REG_WRITE_IMM 0x1D 0x55 —Write value 0x55 to address 0x1D

• REG_WRITE_IMM ADDR=0x10 DATA=0xFF —Write value 0xFF to address 0x10

• REG_WRITE_IMM DATA=0xFF ADDR=0x10 —Write value 0xFF to address 0x10

8.4.2.1.2 REG_WRITE_MASK_IMM Command

Description: Write the specified data, except the masked bits, to the specified register address

Assembly command: REG_WRITE_MASK_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask>

Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth).

'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order.

Examples:

• REG_WRITE_MASK_IMM 0x1D 0x80 0xF0 —Write 0b1000 to the upper 4 bits of the register at address

0x1D

• REG_WRITE_MASK_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 —Write 0b1111 to the lower 4 bits of the

register at address 0x10

• REG_WRITE_MASK_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 —Write 0b1111 to the lower 4 bits of the

register at address 0x10

8.4.2.1.3 REG_WRITE_MASK_PAGE0_IMM Command

Description: Write the specified data, except the masked bits, to the specified page 0 register address

Assembly

command:

REG_WRITE_MASK_PAGE0_IMM

[ADDR=]<Address>

[DATA=]<Data>

[MASK=]<Mask>

Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth).

'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order.

Examples:

• REG_WRITE_MASK_PAGE0_IMM 0x1D 0x80 0xF0 —Write 0b1000 to the upper 4 bits of the register at

address 0x1D

• REG_WRITE_MASK_PAGE0_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 —Write 0b1111 to the lower 4

bits of the register at address 0x10

• REG_WRITE_MASK_PAGE0_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 —Write 0b1111 to the lower 4

bits of the register at address 0x10

8.4.2.1.4 REG_WRITE_BIT_PAGE0_IMM Command

Description: Write the specified data to the BIT_SEL location of the specified page 0 register address

Assembly command: REG_WRITE_BIT_PAGE0_IMM [ADDR=]<Address> [BIT=]<Bit> [DATA=]<Data>

Address, Bit, and Data can be in any literal integer format (decimal, hex, and so forth).

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'ADDR=', 'BIT=', and 'DATA=' are optional. When included, the parameters can be in any order.

Examples:

• REG_WRITE_BIT_PAGE0_IMM 0x1D 7 0 —Write '0' to bit 7 of the register at address 0x1D

• REG_WRITE_BIT_PAGE0_IMM ADDR=0x10 BIT=3 DATA=1 —Write 0b1 to bit 3 of the register at address

0x10

8.4.2.1.5 REG_WRITE_WIN_PAGE0_IMM Command

Description: Write the specified data to the SHIFT location of the specified page 0 register address

Assembly command: REG_WRITE_WIN_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask>

[SHIFT=]<Shift>

Address, Data, Mask, and Shift can be in any literal integer format (decimal, hex, and so forth).

'ADDR=', 'DATA=', 'MASK=', and 'SHIFT=' are optional. When included, the parameters can be in any order.

Examples:

• REG_WRITE_WIN_PAGE0_IMM ADDR=0x1D DATA=0x8 MASK=0x13 SHIFT=2 —Write bits 5:4 to 0b10

to the register at address 0x1D. Data and mask give 5-bit value 0bx10xx. These two bits are then left shifted

2 bit-positions to give full byte value of 0bxx10xxxx, hence sets bits 5:4 to 0b10.

8.4.2.1.6 REG_WRITE_VOUT_IMM Command

Description: Write the target voltage of a specified regulator after a specified delay. This command is a spin-off of

the REG_WRITE_IMM command with the intention to save instruction bits.

Assembly

command:

REG_WRITE_VOUT_IMM

[REGULATOR=]<Regulator

ID>

[SEL=]<VSEL>

[VOUT=]<Vout> [DELAY=]<Delay>

'REGULATOR=', ''SEL=', 'VOUT=', and 'DELAY=' are options. When included, the parameters can be in any

order.

Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4.

VSEL selects the BUCKn_VSET1 or BUCKn_VSET2 bits which the command writes to if Regulator ID is

BUCK1-4. VSEL is defined as: '0': BUCKn_VSET1, '1': BUCKn_VSET2, '2': Currently Active BUCKn_VSET, '3':

Currently Inactive BUCKn_VSET.

VOUT = output voltage in mV or V. Unit must be listed.

DELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63,

which becomes the threshold count for the counter running a step size specified in the register

PFSM_DELAY_STEP. The delay value is rounded to the nearest achievable delay time based on the current

step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous

command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the

delay.

Examples:

• REG_WRITE_VOUT_IMM BUCK3 2 1.05 V 100 µs —Sets BUCK3 to 1.05 V by updating the active

BUCK3_VSET register after 100 µs

8.4.2.1.7 REG_WRITE_VCTRL_IMM Command

Description: Write the operation mode of a specified regulator after a specified delay. This command is a spin-off

of the REG_WRITE_IMM command with the intention to save instruction bits.

Assembly command: REG_WRITE_VCTRL_IMM [REGULATOR=]<Regulator ID> [VCTRL=]<VCTRL>

[MASK=]<Mask> [DELAY=]<Delay> [DELAY_MODE=]<Delay Mode>

'REGULATOR=', 'VCTRL=', 'MASK=', and 'DELAY=' are options. When included, the parameters can be in any

order.

Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4.

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VCTRL = 0-15, in hex, decimal, or binary format. Data to write to the following regulator control fields:

• BUCKs: BUCKn_PLDN, BUCKn_VMON_EN, BUCKn_VSEL, BUCKn_FPWM_MP, BUCKn_FPWM, and

BUCKn_EN

DELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63,

which becomes the threshold count for the counter running a step size specified in the register

PFSM_DELAY_STEP. Delay value is be rounded to the nearest achievable delay time based on the current step

size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in

the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay.

Delay Mode must be one of the below options: MATCH_EN = 0 (Delay if VCTRL enable bit mismatches)

MATCH_ALL = 1 (Delay if any VCTRL bits mismatch) ALWAYS = 2 (Delay always)

Examples:

• REG_WRITE_VCTRL_IMM BUCK3 0x00 0xE0 100 µs —Sets BUCK3 to OFF (VCTRL bits = 0b00000)

after 100 µs

8.4.2.1.8 REG_WRITE_MASK_SREG Command

Description: Write the data from a scratch register, except the masked bits, to the specified register address

Assembly command: REG_WRITE_MASK_SREG [REG=]<Scratch Register> [ADDR=]<Address>

[MASK=]<Mask>

'REG=', 'ADDR=', and 'MASK=' are options. When included, the parameters can be in any order.

Scratch Register can be R0, R1, R2, or R3.

Address and Mask can be in any literal integer format (decimal, hex, and so forth).

Examples:

• REG_WRITE_MASK_SREG R2 0x22 0x00 —Write the content of scratch register 2 to address 0x22

• REG_WRITE_MASK_SREG REG=R0 ADDR=0x054 MASK=0xF0 —Write the lower 4 bits of scratch

register 0 to address 0x54

8.4.2.1.9 SREG_READ_REG Command

Description: Write scratch register (REG0-3) with data from a specified address

Assembly command: SREG_READ_REG [REG=]<Scratch Register> [ADDR=]<Address>

'REG=' and 'ADDR=' are options. When included, the parameters can be in any order.

Scratch Register can be R0, R1, R2, or R3.

Address can be in any literal integer format (decimal, hex, and so forth).

Examples:

• SREG_READ_REG R2 0x15 —Read the content of address 0x15 and write the data to scratch register 2

• SREG_READ_REG ADDR=0x077 REG=R3 —Read the content of address 0x77 and write the data to

scratch register 3

8.4.2.1.10 SREG_WRITE_IMM Command

Description: Write the specified data to the scratch register (REG0-3)

Assembly command: SREG_WRITE_IMM [REG=]<Register> [DATA=]<Data>

Data can be in any literal integer format (decimal, hex, and so forth).

Register can be R0, R1, R2, or R3.

'REG=' and 'DATA=' are options. When included, the parameters can be in any order.

Examples:

• SREG_WRITE_IMM R2 0x15 —Write 0x15 to scratch register 2

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• SREG_WRITE_IMM ADDR=0x077 REG=R3 —Read 0x77 to scratch register 3

8.4.2.1.11 WAIT Command

Description: Wait upon a condition of a given type. Execution is paused until the specified type of the condition is

met or timed out

Assembly

command:

WAIT

[COND=]<Condition>

[TYPE=]<Type>

[TIMEOUT=]<Timeout>

[DEST=]<Destination>

Alternative assembly command: JUMP [DEST=]<Destination>

'COND=', 'TYPE=', 'TIMEOUT=', and 'DEST=' are options. When included, the parameters can be in any order.

Condition are listed in 表8-3. Examples: GPIO1, BUCK1_PG, I2C_1

Type = LOW, HIGH, RISE, or FALL

Timeout = timeout value in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between

0-63. Timeout value is be rounded to the nearest achievable time based on the current step size. Current step

size is based on the default NVM setting or a SET_DELAY value from a previous command in the same

sequence. Assembler reports an error if the step size is too large or too small to meet the delay.

Destination = Label to jump to if when timeout occurs. Destination must be after the WAIT statement in memory.

Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1'

indicates the destination address is external and represents a FSM state ID.

When using the jump command, the PFSM performs an unconditional jump. The command is be compiled as

"WAIT COND=63 TYPE=LOW TIMEOUT=0 DEST=<Destination>". Condition 63 is a hardcoded 1, so the

condition is never satisfied and hence always times out. Therefore this command always jumps to the

destination.

Examples:

• WAIT GPIO4 RISE 1 s <Destination> 0 —Wait to execute the command at the specified SRAM address

when a rise edge is detected at GPIO4, or after 1 second

• WAIT COND=BUCK1_PG TYPE=HIGH TIMEOUT=500 µs DEST=<mcu2act_seq> —Wait to execute the

commands at <mcu2act_seq> address as soon as BUCK1 output is within power-good range, or after 500 µs

表8-3. WAIT Command Conditions

COND_ Condition Name

SEL

COND_ Condition Name

SEL

COND_ Condition Name

SEL

COND_ Condition Name

SEL

0

1

GPIO1

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

N/A

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

I2C_0

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

LP_STANDBY_SEL

GPIO2

N/A

I2C_1

N/A

0

2

GPIO3

N/A

I2C_2

3

GPIO4

N/A

I2C_3

4

GPIO5

PGOOD

I2C_4

5

GPIO6

TWARN_EVENT

I2C_5

6

GPIO7

INTERRUPT_PIN

I2C_6

7

GPIO8

N/A

I2C_7

8

GPIO9

SREG0_0

SREG0_1

SREG0_2

SREG0_3

SREG0_4

SREG0_5

SREG0_6

SREG0_7

9

GPIO10

N/A

10

11

12

13

14

15

BUCK1_PG

BUCK2_PG

BUCK3_PG

BUCK4_PG

N/A

1

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8.4.2.1.12 DELAY_IMM Command

Description: Delay the execution by a specified time

Assembly command: DELAY_IMM <Delay>

Delay = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63.

Delay value is be rounded to the nearest achievable time based on the current step size. Current step size is

based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence.

Assembler reports an error if the step size is too large or too small to meet the delay.

Examples:

• DELAY_IMM 100 µs —Delay execution by 100 µs

• DELAY_IMM 10 ms —Delay execution by 10 ms

• DELAY_IMM 8 —Delay execution by 8 ticks of the current PFSM time step

8.4.2.1.13 DELAY_SREG Command

Description: Delay the execution by a time value stored in the specified scratch register.

Assembly command: DELAY_SREG <Register>

Register can be R0, R1, R2, or R3.

Examples:

• DELAY_SREG R0 —Delay execution by the time value stored in scratch register0

8.4.2.1.14 TRIG_SET Command

Description: Set a trigger destination address for a given input signal or condition. These commands must be

defined at the beginning of PFSM configuration memory.

Assembly

command:

TRIG_SET

[DEST=]<Destination>

[ID=]<Trig_ID>

[SEL=]<Trig_sel>

[TYPE=]<Trig_type> [IMM=]<IMM> [EXT=]<Memory space>

'DEST=', 'ID=', 'SEL='. 'TYPE=', 'IMM=', and 'EXT=' are options. When included, the parameters can be in any

order.

Destination is the label where this trigger starts executing.

Trig_ID is the ID of the hardware trigger module to be configured (value range 0-27). They must be defined in

numeric order based on the priority of the trigger.

Trig_Sel is the 'Trigger Name' from the 表 8-5. This 'Trigger Name' is the trigger signal to be associated with the

specified TRIG_ID.

Trig_type = LOW, HIGH, RISE, or FALL.

IMM can be either '0' or '1'. = '0' if the trigger is not activated until the END command of a given task; '1' if the

trigger is activated immediately and can abort a sequence.

REENTRANT can be either '0' or '1'. '1' permits a trigger to return to the current state, that allows a self-

branching trigger to execute the current sequence again.

Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1'

indicates the destination address is external and represents a FSM state ID.

Examples:

• TRIG_SET seq1 20 GPIO_1 LOW 0 0 —Set trigger 20 to be GPIO_1=Low, not immediate. When triggered,

start executing at ‘seq1’label.

• TRIG_SET DEST=seq2 ID=15 SEL=WD_ERROR TYPE=RISE IMM=0 EXT=0 —Set trigger 15 to be rising

WD_ERROR trigger, not immediate. When triggered, start executing at ‘seq2’label.

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8.4.2.1.15 TRIG_MASK Command

Description: Sets a trigger mask that determines which triggers are active. Setting a ‘0’ enables the trigger,

setting a ‘1’disables (masks) the trigger.

Assembly command: TRIG_MASK <Mask value>

Mask Value = 28-bit mask in any literal integer format (decimal, hex, and so forth).

Examples:

• TRIG_MASK 0x5FF82F0 —Set the trigger mask to 0x5FF82F0

8.4.2.1.16 END Command

表8-4 shows the format of the END commands.

表8-4. END Command Format

Bit[3:0]

CMD

4 bits

Description: Marks the final instruction in a sequential task

Fields:

• CMD: Command opcode (0xC)

Assembly command: END

8.4.2.2 Configuration Memory Organization and Sequence Execution

The configuration memory is loaded from NVM into an SRAM. 图 8-5 shows an example configuration memory

with only two configured sequences.

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pfsm_start:

TRIG_SET DEST=sequence_name1 ID=0 SEL=trigger_name TYPE=high/low/rise/fall IMM=0/1 EXT=0/1

TRIG_SET DEST=sequence_name2 ID=1 SEL=trigger_name TYPE=high/low/rise/fall IMM=0/1 EXT=0/1

TRIG_SET DEST=sequence_name3 ID=2 SEL=trigger_name TYPE=high/low/rise/fall IMM=0/1 EXT=0/1

TRIG_SET DEST=sequence_name4 ID=4 SEL=trigger_name TYPE=high/low/rise/fall IMM=0/1 EXT=0/1

TRIG_SET DEST=sequence_name5 ID=4 SEL=trigger_name TYPE=high/low/rise/fall IMM=0/1 EXT=0/1

……

TRIG_MASK 0xFFFFFF0

END

sequence_name1

These TRIG_SET instructions are used to

define the trigger types which initiates each

power state sequence. There are a total of

28 TRIG_SET available for each PMIC. TYPE

parameter defines the type of trigger as:

REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting

REG_WRITE_VCTRL_IMM REGULATOR=regulator VCTRL=ctrl_setting MASK=mask_setting DELAY=delay_time

DELAY_IMM delay_time

REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting

REG_WRITE_VCTRL_IMM REGULATOR=regulator VCTRL=ctrl_setting MASK=mask_setting DELAY=delay_time

REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting

TRIG_MASK 0xFC00EDF

END

……

sequence_name4

High: active high (level sensitive)

Low: active low (level sensitive)

Rise: active high (edge sensitive)

Fall: active low (edge sensitive)

REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting

DELAY_IMM delay_time

REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting

REG_WRITE_VCTRL_IMM REGULATOR=regulator VCTRL=ctrl_setting MASK=mask_setting DELAY=delay_time

DELAY_IMM delay_time

REG_WRITE_VCTRL_IMM REGULATOR=regulator VCTRL=ctrl_setting MASK=mask_setting DELAY=delay_time

REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting

REG_WRITE_VCTRL_IMM REGULATOR=regulator VCTRL=ctrl_setting MASK=mask_setting DELAY=delay_time

REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting

TRIG_MASK 0xFEF6EDC

END

图8-5. Configuration Memory Script Example

As soon as the PMIC state reaches the mission states, it starts reading from the configuration memory until it

hits the first END command. Setting up the triggers (1-28) must be the first section of the configuration memory,

as well as the first set of trigger configurations. The trigger configurations are read and mapped to an internal

lookup table that contains the starting address associated with each trigger in the configuration memory. If the

trigger destination is an FFSM state then the address contains the fixed state value. After the trigger

configurations are read and mapped into the SRAM, these triggers control the execution flow of the state

transitions. The signal source of each trigger is listed under 表8-5.

When a trigger or multiple triggers are activated, the PFSM execution engine looks up the starting address

associated with the highest priority unmasked trigger, and starts executing commands until it hits an END

command. The last commands before END statement is generally the TRIG_MASK command, which directs the

PFSM to a new set of unmasked trigger configurations, and the trigger with the highest priority in the new set is

serviced next. Trigger priority is determined by the Trigger ID associated with each trigger. The priority of the

trigger decreases as the associated trigger ID increases. As a result, the critical error triggers are usually located

at the lowest trigger IDs.

The TRIG_SET commands specify if a trigger is immediate or non-immediate. Immediate triggers are serviced

immediately, which involves branching from the current sequence of commands to reach a new target

destination. The non-immediate triggers are accumulated and serviced in the order of priority through the

execution of each given sequence until the END command in reached. Therefore, the trigger ID assignment for

each trigger can be arranged to produce the desired PFSM behavior.

The TRIG_MASK command determines which triggers are active at the end of each sequence, and is usually

placed just before the END instruction. The TRIG_MASK takes a 28 bit input to allow any combination of triggers

to be enabled with a single command. Through the definition of the active triggers after each sequence

execution the TRIG_MASK command can be conceptualized as establishing a power state.

The above sequence of waiting for triggers and executing the sequence associated with an activated trigger is

the normal operating condition of the PFSM execution engine when the PMIC is in the MISSION state. The

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FFSM state machine takes over control from the execution engine each time an event occurs that requires a

transition from the MISSION state of the PMIC to a fixed device state.

表8-5. PFSM Trigger Selections

Trigger Name

Trigger Source

An error event causes one of the triggers defined in the FSM_TRIG_SEL_1/2 register to activate, and

the intended action for the activated trigger is to immediate shutdown the device

IMMEDIATE_SHUTDOWN

MCU_POWER_ERROR

ORDERLY_SHUTDOWN

Output failure detection from a regulator which is assigned to the MCU rail group (x_GRP_SEL = '01')

An event which causes MODERATE_ERR_INT = '1'

nPWRON long-press event when NPOWRON_SEL = '01', or ENABLE = '0' when NPOWERON_SEL =

'00'

FORCE_STANDBY

SPMI_WD_BIST_DONE

ESM_MCU_ERROR

WD_ERROR

Completion of SPMI WatchDog BIST

An event that causes ESM_MCU_RST_INT

An event that causes WD_RST_INT

SOC_POWER_ERROR

Output failure detection from a regulator which is assigned to the SOC rail group (x_GRP_SEL = '10')

NSLEEP2 and NSLEEP1 = '11'. More information regarding the NSLEEP1 and NSLEEP2 functions

can be found under 节8.4.2.4.2.1

A

WKUP1

A rising or falling edge detection on a GPIO pin that is configured as WKUP1

A valid On-Request detection when STARTUP_DEST = '11'

SU_ACTIVE

NSLEEP2 and NSLEEP1 = '10'. More information regarding the NSLEEP1 and NSLEEP2 functions

can be found under 节8.4.2.4.2.1

B

WKUP2

A rising or falling edge detection on a GPIO pin that is configured as WKUP2

A valid On-Request detection when STARTUP_DEST = '10'

SU_MCU_ONLY

NSLEEP2 and NSLEEP1 = '01', More information regarding the NSLEEP1 and NSLEEP2 functions

can be found under 节8.4.2.4.2.1

C

D

NSLEEP2 and NSLEEP1 = '00'. More information regarding the NSLEEP1 and NSLEEP2 functions

can be found under 节8.4.2.4.2.1

SU_STANDBY

SU_X

A valid On-Request detection when STARTUP_DEST = '00'

A valid On-Request detection when STARTUP_DEST = '01'

PFSM WAIT command condition timed out. More information regarding the WAIT command can be

found under 节8.4.2.1.11

WAIT_TIMEOUT

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

I2C_0

Input detection at GPIO1 pin

Input detection at GPIO2 pin

Input detection at GPIO3 pin

Input detection at GPIO4 pin

Input detection at GPIO5 pin

Input detection at GPIO6 pin

Input detection at GPIO7 pin

Input detection at GPIO8 pin

Input detection at GPIO9 pin

Input detection at GPIO10 pin

Input detection of TRIGGER_I2C_0 bit

Input detection of TRIGGER_I2C_1 bit

Input detection of TRIGGER_I2C_2 bit

Input detection of TRIGGER_I2C_3 bit

Input detection of TRIGGER_I2C_4 bit

Input detection of TRIGGER_I2C_5 bit

Input detection of TRIGGER_I2C_6 bit

Input detection of TRIGGER_I2C_7 bit

Input detection of SCRATCH_PAD_REG_0 bit 0

I2C_1

I2C_2

I2C_3

I2C_4

I2C_5

I2C_6

I2C_7

SREG0_0

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表8-5. PFSM Trigger Selections (continued)

Trigger Source

Trigger Name

SREG0_1

SREG0_2

SREG0_3

SREG0_4

SREG0_5

SREG0_6

SREG0_7

0

Input detection of SCRATCH_PAD_REG_0 bit 1

Input detection of SCRATCH_PAD_REG_0 bit 2

Input detection of SCRATCH_PAD_REG_0 bit 3

Input detection of SCRATCH_PAD_REG_0 bit 4

Input detection of SCRATCH_PAD_REG_0 bit 5

Input detection of SCRATCH_PAD_REG_0 bit 6

Input detection of SCRATCH_PAD_REG_0 bit 7

Always '0'

1

Always '1'

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8.4.2.3 Mission State Configuration

The Mission States portion of the FSM engine manages the sequencing of power rails and external outputs in

the user defined states. The rest of Device State Machine the 图8-6 is used as an example state machine that is

defined through the configuration memory using the configuration FSM instructions.

To LP_STANDBY

To Safe Recovery

State

Severe or

Moderate PFSM

Errors

From any

Operation States

LP_STAND

=1

BY_SEL

Immediate or Orderly

Shutdown Condition

Detected

Valid On Request and

STANDBY

STARTUP_DEST[1:0] = 0x00

Valid On Request and

OFF request

STARTUP_DEST[1:0] = 0x03

Warm Reset triggered by

ESM or WDOG error

Valid On Request and

STARTUP_DEST[1:0] = 0x02

OFF request

ACTIVE

OFF request

WKUP1 0W1 or

NSLEEP1

NSLEEP2&NSLEEP1

11W10

0W1

NSLEEP2

1:0

WKUP1 0W 1 or

NSLEEP2&NSLEEP1

00W11

MCU ONLY

WKUP2 0W 1 or

NSLEEP2&NSLEEP1

00W10

NSLEEP2

1:0

Warm Reset triggered by

ESM or WDOG error

DEEP SLEEP

/S2R

图8-6. Example of a Mission State-Machine

Each power state (light blue bubbles in 图 8-6) defines the ON or OFF state and the sequencing timing of the

external regulators and GPIO outputs. This example defines 4 power states: STANDBY, ACTIVE, MCU ONLY,

and DEEP_SLEEP/S2R states. The priority order of these states is as follows:

1. ACTIVE

2. MCU ONLY

3. DEEP SLEEP/S2R

4. STANDBY

The transitions between each power state is determined by the trigger signals source pre-selected from 表 8-5.

These triggers are then placed in the order of priority through the trigger ID assignment of each trigger source.

The critical error triggers are placed first, some specified as immediate triggers that can interrupt an on-going

sequence. The non-error triggers, which are used to enable state transitions during normal device operation, are

then placed according to the priority order of the state the device is transitioning to. 表 8-6 list the trigger signal

sources, in the order of priority, used to define the power states and transitions of the example mission state

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machine shown in 图8-6. This table also helps to determine which triggers must be masked by the TRIG_MASK

command upon arriving a pre-defined power state to produce the desired PFSM behavior.

表8-6. List of Trigger Used in Example Mission State Machine

Trigger ID

Trigger Masked In Each User Defined Power State

Trigger Signal

State Transitions

DEEP

SLEEP / S2R

STANDBY

ACTIVE

MCU ONLY

0

1

2

3

IMMEDIATE_SHUTDOWN ⁽¹⁾

MCU_POWER_ERROR ⁽¹⁾

ORDERLY_SHUTDOWN ⁽¹⁾

TRIGGER_FORCE_STANDBY

From any state to SAFE

RECOVERY

From any state to SAFE

RECOVERY

From any state to SAFE

RECOVERY

From any state to

STANDBY or

Masked

LP_STANDBY

4

5

7

8

WD_ERROR

Perform warm reset of all

power rails and return to

ACTIVE

Masked

ESM_MCU_ERROR

WD_ERROR

Perform warm reset of all

power rails and return to

ACTIVE

Perform warm reset of all

power rails and return to

MCU ONLY

Masked

ESM_MCU_ERROR

Perform warm reset of all

power rails and return to

MCU ONLY

9

SOC_POWER_ERROR

ACTIVE to MCU ONLY

Start RUNTIME_BIST

Masked

10

11

TRIGGER _I2C_1 (self-cleared)

TRIGGER_I2C_2 (self-cleared)

Enable I2C CRC

Function

Masked

12

13

14

TRIGGER_SU_ACTIVE

TRIGGER_WKUP1

STANDBY to ACTIVE

Any State to ACTIVE

TRIGGER_A (NSLEEP2&NSLEEP1 MCU ONLY or DEEP

= '11')

Masked

SLEEP/S2R to ACTIVE

15

16

TRIGGER_SU_MCU_ONLY

TRIGGER_WKUP2

STANDBY to MCU ONLY

Masked

STANDBY or DEEP

SLEEP/S2R to MCU

ONLY

17

18

TRIGGER_B (NSLEEP2&NSLEEP1 ACTIVE or DEEP

= '10')

SLEEP/S2R to MCU

ONLY

Masked

TRIGGER_D or TRIGGER_C

(NSLEEP2 = '0' )

ACTIVE or MCU ONLY

to DEEP SLEEP/S2R

Masked

Mask

Masked

19

20

TRIGGER_I2C_0 (self-cleared)

Always '1' ⁽²⁾

Any state to STANDBY

STANDBY to SAFE

RECOVERY

Masked

21

22

23

24

25

26

27

Not Used

Mask

Masked

Not Used

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表8-6. List of Trigger Used in Example Mission State Machine (continued)

Trigger ID

Trigger Masked In Each User Defined Power State

Trigger Signal

State Transitions

DEEP

SLEEP / S2R

STANDBY

ACTIVE

MCU ONLY

28-bit TRIG_MASK Value in Hex format: 0xFFE4FF8 0xFF181C0

0xFF01270

0xFFC9FF0

(1) This is an immediate trigger.

(2) When an error occurs, which requires the device to enter directly to the SAFE RECOVERY state, the mask for this trigger must be

removed while all other non-immediate triggers are masked. The device exits the mission states and the FFSM state machine takes

over control of the device power states once this trigger is executed.

8.4.2.4 Pre-Configured Hardware Transitions

There are some pre-defined trigger sources, such as on-requests and off-requests, that are constructed with the

combination of hardware input signals and register bits settings. This section provides more detail to these pre-

defined trigger sources and shows how they can be utilized in the PFSM configuration to initiate state to state

transitions.

8.4.2.4.1 ON Requests

ON requests are used to switch on the device, which then transitions the device from the STANDBY or the

LP_STANDBY to the state specified by STARTUP_DEST[1:0].

After the device arrives at the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the

NSLEEP1 and NSLEEP2 signals accordingly before clearing the STARTUP_INT interrupt. Once the interrupt is

cleared, the device stays or moves to the next state corresponding to the NSLEEP signals state assignment as

specified in 表8-10.

表8-7 lists the available ON requests.

表8-7. ON Requests

EVENT

MASKABLE

COMMENT

DEBOUNCE

ENABLE (pin)

Yes

Level sensitive

8 µs

VCCA > VCCA_UV and FSD

unmasked

First Supply Detection (FSD)

WKUP1 or WKUP2 Detection

Yes

N/A

Edge sensitive

8 µs

Recover from system errors

which caused immediate or

orderly shutdown of the

device

Recovery from Immediate and

Orderly Shutdown

No

N/A

If one of the events listed in 表 8-7 occurs, then the event powers on the device unless one of the gating

conditions listed in 表8-8 is present.

表8-8. ON Requests Gating Conditions

EVENT

MASKABLE

COMMENT

VCCA ⩾VCCA_OVPDevice stays in SAFE RECOVERY until VCCA

VCCA_OVP (event)

No

< VCCA_OVP

VCCA_UVLO (event)

VINT_OVP (event)

VINT_UVLO (event)

No

VCCA < VCCA_UVLO

LDOVINT > 1.98 V

LDOVINT < 1.62 V

Device stays in SAFE RECOVERY until temperature decreases

below TWARN level

TSD (event)

No

8.4.2.4.2 OFF Requests

An OFF request is used to orderly switch off the device. OFF requests initiate transition from any other mission

state to the STANDBY state or the LP_STANDBY state depending on the setting of the LP_STANDBY_SEL bit.

表8-9 lists the conditions to generate the OFF requests and the corresponding destination state.

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表8-9. OFF Requests

LP_STANDBY_SEL BIT

EVENT

DEBOUNCE

DESTINATION STATE

SETTING

LP_STANDBY_SEL = 0

LP_STANDBY_SEL = 1

LP_STANDBY_SEL = 0

LP_STANDBY_SEL = 1

STANDBY

LP_STANDBY

STANDBY

ENABLE (pin)

8 µs

I2C_TRIGGER_0

NA

LP_STANDBY

Using the I2C_TRIGGER_0 bit as the OFF request enables the device to wake up from the STANDBY or the

LP_STANDBY states through the detection of WKUPn pins. To enable this feature the device must set the

I2C_TRIGGER_0 bit to '1' while the NSLEEPn signals are masked, and the ON request initialized by the

ENABLE pin remains active (if the ENABLE pin is used). Also the interrupt bits ENABLE_INT, FSD_INT and the

GPIOx_INT bits (for the GPIOx pins assigned as WKUP1 or WKUP2) must be cleared before setting the

I2C_TRIGGER_0 bit to '1'.

8.4.2.4.2.1 NSLEEP1 and NSLEEP2 Functions

The SLEEP requests are activated through the assertion of nSLEEP1 or nSLEEP2 pins that are the secondary

functions of the 10 GPIO pins. These pins can be selected through GPIO configuration using the GPIOx_SEL

register bits. If the nSLEEP1 or nSLEEP2 pins are not available, the NSLEEP1B and NSLEEP2B register bits

can be configured in place for their functions. The input of nSLEEP1 pin and the state of the NSLEEP1B register

bit are combined to create the NSLEEP1 signal through an OR function. Similarly for the input of the nSLEEP2

pin and the NSLEEP2B register bit as they are combined to create the NSLEEP2 signal.

A 1 → 0 logic level transition of the NSLEEP signal generates a sleep request, while a 0 → 1 logic level

transition reverses the sleep request in the example PFSM from 图 8-6. When a NSLEEPn signal transitions

from 1 →0, it generates a sleep request to go from a higher power state to a lower power state. When the signal

transitions from 0 →1, it reverses the sleep request and returns the device to the higher power state.

The NSLEEP1 signal is designed to control the SoC supply rails. The NSLEEP2 signal is designed to control the

MCU supply rails. When NSLEEP1 signal changes from 1 → 0, depending on the state of NSLEEP2, the

LP8764-Q1 device exits ACTIVE state and enters either the MCU ONLY or the S2R states. When NSLEEP2

signal changes from 1 →0, the device enters the S2R state regardless the state of NSLEEP1.

When the NSLEEP2 input signal changes from 0 →1, the MCU supply rails are enabled and the device exits

S2R state. Depending on the state of NSLEEP1 signal, the device enters either the MCU ONLY or the ACTIVE

state. In order for the system to function correctly, the MCU rails must be enabled when the NSLEEP1 input

signal changes from 0 →1, which enables the SOC supply rails. NSLEEP1 0 →1 transition is ignored if

NSLEEP2 is 0.

The NSLEEPn_MASK bit can be used to mask the sleep request associated with the corresponding NSLEEPn

signal. When the NSLEEPn_MASK = 1, the corresponding NSLEEPn signal is ignored. 表 8-10 shows how the

combination of the NSLEEPn signals and NSLEEPn_MASK bits creates triggers A/B/C/D to the FSM to control

the power state of the device.

The states of the resources during ACTIVE, SLEEP, and DEEP SLEEP/S2R states are defined in the

BUCKn_CTRL registers. For each resource, a transition to the MCU ONLY or the DEEP SLEEP/S2R states is

controlled by the FSM when the resource is associated to the SLEEP or DEEP SLEEP/S2R states.

表 8-10 shows the corresponding state assignment based on the state of the NSLEEPn and their corresponding

mask signals using the example PFSM from 图8-6.

表8-10. NSLEEPn Transitions and Mission State Assignments

Current State

NSLEEP1

NSLEEP2

NSLEEP1 MASK NSLEEP2 MASK

Trigger to FSM

TRIGGER B

TRIGGER A

Next State

MCU ONLY

ACTIVE

DEEP SLEEP/S2R

0

1

0

0 →1

Don't care

ACTIVE

0 →1

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表8-10. NSLEEPn Transitions and Mission State Assignments (continued)

Current State

NSLEEP1

NSLEEP2

NSLEEP1 MASK NSLEEP2 MASK

Trigger to FSM

TRIGGER A

TRIGGER D

Next State

ACTIVE

DEEP SLEEP/S2R

or MCU ONLY

Don't care

0

1

0 →1

MCU ONLY

1

0

ACTIVE

0 →1

0

DEEP SLEEP

or S2R

1 →0

MCU ONLY

Don't care

1

0

DEEP SLEEP

or S2R

1 →0

TRIGGER D

TRIGGER B

TRIGGER D

ACTIVE

1

0

MCU ONLY

1 →0

DEEP SLEEP

or S2R

1 →0

ACTIVE

Don't care

1

0

1

DEEP SLEEP

or S2R

1 →0

TRIGGER D

TRIGGER B

Don't care

MCU ONLY

1 →0

8.4.2.4.2.2 WKUP1 and WKUP2 Functions

The WKUP1 and WKUP2 functions are activated through the edge detection on all GPIO pins. Any one of these

GPIO pins when configured as an input pin can be configured to wake up the device by setting GPIOn_SEL bit

to select the WKUP1 or WKUP2 functions. In the example PFSM depicted in 图 8-6, when a GPIO pin is

configured as a WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by the

GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) wakes up the device to the ACTIVE state. Likewise if a

GPIO pin is configured as a WKUP2 pin, a detected edge wakes up the device to the MCU ONLY state. If

multiple edge detections of WKUP signals occur simultaneous, the device goes to the state in the following

priority order:

1. ACTIVE

2. MCU ONLY

When a valid edge is detected at a WKUP pin, the nINT pin generates an interrupt to signal the MCU of the

wake-up event, and the GPIOx_INT interrupt bit is set. The wake request remains active until the GPIOx_INT bit

is cleared by the MCU. While the wake request is executing, the device does not react to sleep requests to enter

a lower power state until the corresponding GPIOx_INT interrupt bit is cleared to cancel the wake request. After

the wake request is canceled, the device returns to the state indicated by the NSLEEP1 and NSLEEP2 signals

as shown in 表8-10.

The WKUP1 and WKUP2 functions can be used in all Mission States and also in LP_STANDBY state.

8.4.3 Error Handling Operations

The FSM engine of the LP8764-Q1 device is designed to handle the following types of errors throughout the

operation:

• Power Rail Output Error

• Boot BIST Error

• Runtime BIST Error

• Catastrophic Error

• Watchdog Error

• Error Signal Monitor (ESM) Error

• Warnings

8.4.3.1 Power Rail Output Error

A power rail output error occurs when an error condition is detected from the output rails of the device that are

used to power the attached MCU or SoC. These errors include the following:

• Rails not reaching or maintaining within the power good voltage level threshold.

• A short condition that is detected at a regulator output.

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• The load current that exceeds the forward current limit.

The BUCKn_GRP_SEL, VMONn_GRP_SEL and VCCA_GRP_SEL registers are used to configure the rail group

for all of the Bucks and the voltage monitors that are available for external rails. The selectable rail groups are

MCU rail group, SoC rail group, or other rail group. The LP8764-Q1 device is designed to react differently when

an error is detected from a power resource assigned to the different rail groups.

图8-4 shows how the SOC_RAIL_TRIG[1:0], MCU_RAIL_TRIG[1:0], and OTHER_RAIL_TRIG[1:0] registers are

used as the Immediate Shutdown Trigger Mask, Orderly Shutdown Trigger Mask, MCU Power Error Trigger

Mask, or the SoC Power Error Trigger Mask. The settings of these register bits determine the error handling

sequence that the assigned groups of rails perform in case of an output error. The PFSM engine can be

configured to execute the appropriate error handling sequence for the following error handling sequence options:

immediate shutdown, orderly shutdown, MCU power error, or SOC power error. For example, if an immediate

shutdown sequence is assigned to the MCU rail group through the MCU_RAIL_TRIG[1:0], any failure detected in

this group of rails causes the IMMEDIATE_SHUTDOWN trigger to be executed. This trigger is expected to start

the immediate shutdown sequence and cause the device to enter the SAFE RECOVERY state. The device

immediately resets the attached MCU and SoC by driving the nRSTOUT and nRSTOUT_SoC pins low. All of the

power resources assigned to the MCU and SOC shut down immediately without a sequencing order. The nINT

pin signals that an MCU_PWR_ERR_INT interrupt event has occurred and the EN_DRV pin is forced low. If the

error is recoverable within the recovery time interval, the device increments the recovery count, returns to INIT

state, and reattempts the power up sequence (if the recovery count has not exceeded the counter threshold). If

the recovery count has already exceeded the threshold, the device stays in the SAFE RECOVERY state until

VCCA voltage is below the VCCA_UVLO threshold and the device is power cycled.

The power resources assigned to the SoC rail group are typically assigned to the SOC power error handling

sequence. In this PFSM example depicted in 图8-6, when a power resource in this group is detected, the PFSM

typically causes the device to execute the shutdown of all the resources assigned to the SoC rail group, and the

device enters the MCU ONLY state. The device immediately resets the attached SoC by toggling the

nRSTOUT_SoC pin. The reset output to the MCU and the resources assigned to the MCU rail group remain

unchanged. The EN_DRV pin also remains unchanged, and the nINT pin signals that an SOC_PWR_ERR_INT

interrupt event has occurred. To recover from the MCU_ONLY state after a SOC power error, the MCU software

must set NSLEEP1 signal to '0' while NSLEEP2 signal remains '1'. This action signals LP8764-Q1 that MCU has

acknowledged the SOC power error, and is ready to return to normal operation. MCU can then set the NSLEEP1

signal back to '1' for the device to return to ACTIVE state and reattempt the SoC power up. Refer to 节

8.4.2.4.2.1 for information regarding the setting of the NSLEEP1 and NSLEEP2 signals.

8.4.3.2 Boot BIST Error

Boot BIST error occurs when the device is not able to pass the BOOT BIST during device power up. Every

failure of the BOOT BIST attempt causes the recovery count to increment as the device enters the SAFE

RECOVERY state. If the count value is smaller than the counter threshold, the device attempts to enter the INIT

state again and reattempts the BOOT BIST until the recovery count reaches the maximum threshold. When this

occurs, the device stays in the SAFE RECOVERY state until VCCA voltage is below the VCCA_UVLO threshold

and the device is power cycled.

8.4.3.3 Runtime BIST Error

Runtime BIST error occurs when the device is not able to pass the Runtime BIST while the device is in an

operation state. This error creates an immediate shutdown condition, that causes the device to execute the

immediate shutdown sequence and enter the SAFE RECOVERY state. The device immediately resets the

attached MCU and SoC by driving the nRSTOUT and nRSTOUT_SoC pins low. All of the power resources

assigned to the MCU and SOC are immediately shut down. The EN_DRV pin is forced low, and the nINT pin is

driven low to signal an interrupt event has occurred.

8.4.3.4 Catastrophic Error

Catastrophic errors are errors that affect multiple power resources such as errors detected in supply voltage,

LDOVINT supply for control logic, errors on internal clock signals, and device temperature passing the thermal

shutdown threshold, error detected on the SPMI bus, or an error detected in the PFSM sequence.

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Following errors are grouped as severe errors:

• VCCA ⩾OVP threshold

• Junction temperature ⩾immediate shutdown level

• Error in PFSM Sequence

For these above listed errors, depending on the setting of bits SEVERE_ERR_TRIG[1:0], an immediate or

orderly shutdown condition is created. The PFSM executes the corresponding sequence for the

IMMEDIATE_SHUTDOWN trigger or the ORDERLY_SHUTDOWN trigger and enters the SAFE RECOVERY

state.

Following errors are grouped as moderate errors:

• Junction temperature ⩾orderly shutdown level

• BIST failure

• CRC error in register map

• Recovery counter exceeding the threshold value

• Error on SPMI bus

• Readback error on nRSTOUT pin or nINT pin

For these above listed errors, depending on the setting of bits MODERATE_ERR_TRIG[1:0], an immediate or

orderly shutdown condition is created. The PFSM executes the corresponding sequence for the

IMMEDIATE_SHUTDOWN trigger or the ORDERLY_SHUTDOWN trigger and enters the SAFE RECOVERY

state.

For following errors, the device performs an immediate shutdown and resets all internal logic circuits:

• VCCA < UVLO threshold

• Error on LDOVINT supply

• Errors on internal clock signals

• Unrecoverable CRC error in the SRAM memory of the PFSM

For all of the above listed errors, the device resets the attached MCU and SoC by driving the GPIO pins used as

nRSTOUT and nRSTOUT_SoC pins low. All of the power resources assigned to the MCU and SOC are shut

down. The nINT pin is driven low to signal an interrupt event has occurred, and the GPIO pins used as EN_DRV

pin is forced low.

8.4.3.5 Watchdog (WDOG) Error

Watchdog (WD) describes details about the Watchdog (WDOG) errors detection mechanisms.

8.4.3.6 Error Signal Monitor (ESM) Error

There is one Error Signal Monitor (ESM) available for the LP8764-Q1 device, designed to detect and handle the

error signal received from the attached MCU. The error detection mechanisms for the monitor is described in

detail under 节8.15.

8.4.3.7 Warnings

Warning are non-catastrophic errors. When such an error occurs while the device is in the operating states, the

device detects the error and handles the error through the interrupt handler. These are errors such as thermal

warnings, I2C, or SPI communication errors, or power resource current limit detection while the output voltage

still maintains within the power good threshold. When these errors occur, the nINT pin is driven low to signal an

interrupt event has occurred. The device remains in the operation state and the state of the EN_DRV pin, the

power resources, and the reset outputs remain unchanged.

The power resource current limit detection can, by setting bit EN_ILIM_FSM_CTRL=1, be configured such that it

is handled as a Power Rail Output Error as described in 节8.4.3.1.

8.4.4 Device Start-up Timing

图8-7 shows the timing diagram of the LP8764-Q1 after the first supply detection.

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图8-7. Device Start-up Timing Diagram

t_{INIT_REF_CLK_LDO}is the start-up time for the reference block, LDOVINT and internal oscillator. t_{INIT_NVM_ANALOG}is

the time for the device to load the default values of the NVM configurable registers from the NVM memory, and

the start-up time for the analog circuits in the device. Both t_{INIT_REF_CLK_LDO}and t_{INIT_NVM_ANALOG}are defined in

the electrical characterization table.

t_{BOOT_BIST}is the sum of t_ABISTrunand t_LBISTrun, which are defined in the electrical characterization tables.

The Power Sequence time is the total time for the device to complete the power up sequence. Please refer to 节

8.4.5 for more details.

The reset delay time is a configurable wait time for the nRSTOUT and the nRSTOUT_SoC release after the

power up sequence is completed.

8.4.5 Power Sequences

A power sequence is an automatic preconfigured sequence the LP8764-Q1 device applies to its resources,

which include the states of the BUCKs and the GPIO output signals. For a detailed description of the GPIOs

signals, please refer to General-Purpose I/Os (GPIO Pins).

图 8-8 shows an example of a power up transition followed by a power down transition. The power up sequence

is triggered through a valid on request, and the power down sequence is trigger by a valid off request. The

resources controlled (for this example) are: BUCK3, BUCK2, REGEN1, SYNCCLKOUT, and nRSTOUT. The

time between each resource enable and disable (TinstX) is also part of the preconfigured sequence definition.

When a resource is not assigned to any power sequence, it remains in off mode. The MCU can enable and

configure this resource independently when the power sequence completes.

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Power Up Sequence

Power Down Sequence

Valid On

X

Request

X

Valid Off

Request

X

BUCK3

BUCK2

t_(inst10)

t_(inst1)

t_(inst9)

t_(inst2)

REGEN1

t_(inst8)

t_(inst3)

BUCK1

t_(inst4)

t_(inst5)

t_(inst7)

t_(inst6)

SYNCCLKOUT

nRSTOUT

图8-8. Power Sequence Example

As the power sequences of the LP8764-Q1 device are defined according to the processor requirements, the

total time for the completion of the power sequence varies across various system definitions.

8.4.6 First Supply Detection

The LP8764-Q1 device can be configured to automatically start up from a first supply-detection (FSD) event

detection. This feature is enabled by setting the FSD_MASK register bit to '0', and driving ENABLE pin active if

ENABLE pin function is selected for GPIO. When the device is powered up from the NO SUPPLY state, the FSD

detection is validated after the NVM default for this feature is loaded into the device memory.

When the FSD feature is enabled, the PMIC immediately powers up from the NO SUPPLY state to an operation

state, configured by the STARTUP_DEST[1:0] bits when VCCA > VCCA_UV, while VCCA_UV gating is

performed, and only when VCCA voltage monitoring is enabled (VCCA_VMON_EN = 1). After the device arrives

the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the NSLEEP1 and NSLEEP2

signals accordingly before clearing the FSD_INT interrupt. Once the interrupt is cleared, the device either stays

in the current state or moves to the destination state according to the state of the NSLEEP1/2 signals as

specified in 表8-10.

8.5 Power Resources

The power resources provided by the LP8764-Q1 device include 4 inductor-based buck regulators. These

supply resources provide the required power to the external processor cores, external components, and to

modules embedded in the LP8764-Q1 device. The supply of the bucks, the PVIN_Bx pins, must connect to the

VCCA pin externally.

8.5.1 Buck Regulators

8.5.1.1 BUCK Regulator Overview

The LP8764-Q1 includes four synchronous buck converters, that can be combined in a multi-phase

configuration. All of the buck converters support the following features:

• Automatic mode control based on the loading (PFM or PWM mode) or Forced-PWM mode operation

• External clock synchronization option to minimize crosstalk

• Optional spread spectrum technique to reduce EMI

• Soft start

• AVS support with configurable slew-rate

• Windowed undervoltage and overvoltage monitors with configurable threshold

• Windowed voltage monitor for external supply when the buck converter is disabled

• Output Current Limit

• Short-to-Ground Detection on SW_Bx pins at start-up of the buck regulator

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When the outputs of these buck converters are combined in multi-phase configuration, it also supports the

following features:

• Current balancing between the phases of the converter

• Differential voltage sensing from point of the load

• Phase shifted outputs for EMI reduction

• Optional dynamic phase shedding or adding

There are two modes of operation for the buck converter, depending on the required output current: pulse-width

modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load

currents of approximately 600 mA or higher. Lighter output current loads cause the converter to automatically

switch into PFM mode for reduced current consumption. The device avoids pulse skipping and allows easy

filtering of the switch noise by external filter components when forced-PWM mode is selected (BUCKn_FPWM =

1). The forced-PWM mode is the recommended mode of operation for the buck converter to achieve better ripple

and transient performance. The drawback of this forced-PWM mode is the higher quiescent current at low output

current levels.

When operating in PWM mode the phases of a multi-phase regulator are automatically added or shed based on

the load current level. The forced multi-phase mode can be enabled for lower ripple at the output.

A multi-phase synchronous BUCK converter offers several advantages over a single power stage converter.

Lower ripple on the input and output currents and faster transient response to load steps are the most significant

advantages for application processor power delivery. The heat generated is greatly reduced for each channel

due to the fact that power loss is proportional to the square of current with the even distribution of the load

current in a multi-phase output configuration. The physical size of the output inductor shrinks significantly due to

this heat reduction.

图8-9 shows a block diagram of a single core.

图8-10 shows the interleaving switching action of the multi-phase converters.

PVIN

High-Side

Current Limit

Loop

Comparator

FBP

Feedback Network

FBN

PDN

Gate

Driver

PWM

Generator

œ

Low-Side

Current Limit

DAC

+

Error

Amplifier

CLK

图8-9. BUCK Core Block Diagram

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I_{L_TOT_4PH}

I_L1

I_L2

I_L4

I_L3

0

90

180

270

360

450

540

630

720

PWM₁

PWM₂

PWM₄

PWM₃

Switching Cycle 360º

0

90

180

270

360

450

540

630

720

Phase (Degrees)

图8-10. Example of PWM Timings, Inductor Current Waveforms, and Total Output Current in 4-Phase

Configuration. ¹

8.5.1.2 Multi-Phase Operation and Phase-Adding or Shedding

The 4-phase converters (BUCK1, BUCK2, BUCK3, and BUCK4) switches each channel 90° apart under heavy

load conditions. As a result, the 4-phase converter has an effective ripple frequency four times greater than the

switching frequency of any one phase. In the same way, 3-phase converter has an effective ripple frequency

three times greater and 2-phase converter has an effective ripple frequency two times greater than the switching

frequency of any one phase; the parallel operation, however, decreases the efficiency at light load conditions.

The LP8764-Q1 can change the number of active phases to optimize efficiency for the variations of the load in

order to overcome this operational inefficiency. The process in which the multi-phase buck regulator in case of

increasing load current automatically increases the number of active phases is called phase adding. The process

in which the multi-phase buck regulator in case of decreasing load current automatically decreases the number

of active phases is called phase shedding. The concept is shown in 图8-11.

The converter can be forced to multi-phase operation by the BUCKn_FPWM_MP bit in BUCKn_CTRL1 register.

If the regulator operates in forced multi-phase mode , each phase automatically operates in the forced-PWM

mode. If the multi-phase operation is not forced, the number of phases are added and shed automatically to

follow the required output current.

1

Graph is not in scale and is for illustrative purposes only.

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Best efficiency obtained with

N=1

N=2

N=3

N=4

Load Current

图8-11. Multiphase BUCK Converter Efficiency vs Number of Phases (Converters in PWM Mode) ²

8.5.1.3 Transition Between PWM and PFM Modes

The forced-PWM mode operation with phase-adding or shedding optimizes efficiency at mid-to-full load.

TheLP8764-Q1 converter operates in PWM mode at load current of about 600 mA or higher. The device

automatically switches into PFM mode for reduced current consumption when forced-PWM mode is disabled

(BUCKn_FPWM = 0) at lighter load-current levels. A high efficiency is achieved over a wide output-load-current

range by combining the PFM and the PWM modes.

8.5.1.4 Spread-Spectrum Mode

The LP8764-Q1 device supports spread-spectrum modulation of the switching clock signal used by the BUCK

regulators. Three factory-selectable modulation modes are available: the first mode is modulation from external

input clock at the SYNCCLKIN pin; the second mode is modulating the input clock at the SYNCCLKIN pin using

the DPLL; the third mode is modulating the internal 20-MHz RC-Oscillator clock using the DPLL.

The spread-spectrum modulation mode is pre-configured in NVM. Changing this modulation mode during

operation is not supported.

The modulation frequency range is limited by the DPLL bandwidth. The max frequency spread for the input clock

to the DPLL is ±18% to secure parametric compliance of the BUCK output performance.

The internal modulation is disabled by default and can be enabled and configured after power up. Internal

modulation is activated by setting the SS_EN control bit. The internal modulation must be disabled (SS_EN = 0)

when changing the following parameter:

• SS_DEPTH[1:0] –Spread Spectrum modulation depth

When internal modulation is enabled and configured, it can be disabled by the system MCU during operation.

The device transition to different mission states does not impact internal modulation when it is enabled and

configured.

2

Graph is not in scale and is for illustrative purposes only.

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8.5.1.5 Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support

An AVS or a DVS voltage value can be configured by the attached MCU after the BUCK regulator is powered up

to the default output voltage selected in register BUCKn_VSET1, that loads its default value from NVM. The

purpose of the AVS/DVS voltage is to set the BUCK output voltage to enable optimal efficiency and performance

of the attached SoC.

All of BUCK regulators in the LP8764-Q1 device support AVS and DVS voltage scaling changes. Once the

AVS/DVS voltage value is written into the BUCKn_VSET1 or BUCKn_VSET2 register, and the MCU sets the

BUCKn_VSEL register to select the AVS/DVS voltage, the output of the BUCK regulator remains at the

AVS/DVS voltage level instead of the default voltage from NVM until one of the following events occur:

• Error that causes the device to re-initialize itself through a power cycle after reaching the SAFE RECOVERY

state

• Error that causes the device to execute warm reset

• MCU configures the device to enter the LP STANDBY state if SKIP_LP_STANDBY_EE_READ = 0

图 8-12 shows the arbitration scheme for loading the output level of the BUCK regulator from the AVS register

using the BUCKn_VSET control registers.

I2C/SPI

BUCK ENABLE *)

I2C/SPI

BUCK VOLTAGE SELECT *)

BUCKn_EN

BUCKn_VSEL

I2C/SPI

BUCKn_VSET1

BUCKn_VSET2

DCDC

Regulator

MUX

*) BUCK ENABLE and BUCK VOLTAGE SELECT bits

are located in BUCKx_CTRL register

图8-12. AVS/DVS Configuration Register Arbitration Diagram

The digital control block automatically updates the OV and UV threshold of the BUCK output voltage monitor

during the AVS or DVS voltage change. When the output voltage is increased, the OV threshold is updated at

the same time the BUCKn_VSETx is updated to the AVS voltage level, while the UV threshold is updated after a

delay calculated by 方程式1.

When the output voltage is decreased, the UV threshold is updated at the same time the BUCKn_VSETx is

updated to the AVS voltage level, while the OV threshold is updated after a delay calculated by 方程式1.

t_{PG_OV_UV_DELAY}= (dV / BUCKn_SLEW_RATE) + t_{settle_Bx}

(1)

In order to prevent erroneous voltage monitoring, the digital block also temporarily masks the results of the OV

and UV monitor from the regulator output when the BUCK regulator is enabled and the voltage is rising to the

BUCKn_VSETx level. The duration of the mask starts from the time the BUCK regulator is enabled. The BUCK

OV monitor output is masked for a fixed delay time of t_{PG_OV_GATE}, that is approximately 115 µs – 128 µs. The

UV monitor output is masked for the time duration calculated by 方程式 2. The 370-µs additional delay time in

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the formula includes the start-up delay of the BUCK regulator, the fixed delay after the ramp, and the time for the

BIST operation of the OV and UV monitors.

t_{PG_UV_GATE}= (BUCKn_VSET / BUCKn_SLEW_RATE) + 370 µs

(2)

备注

Because output capacitance, forward and negative current limits and load current of the BUCK

regulator may affect the slew rate of the BUCK regulator output voltage, the delay time of t_{PG_UV_GATE}

may not be sufficient long for the slower slew rate setting when the target BUCK regulator output

voltage is higher. Please refer to the PMIC User's Guide for detail information about the supported

voltage level and slew rate setting combinations of a particular orderable part number.

图 8-13 and 图 8-14 are timing diagrams illustrating the voltage change for AVS and DVS enabled BUCK

regulators and the corresponding OV and UV monitor threshold changes.

Ini al voltage

AVS_VNOM

OV limit

UV limit

ABIST

UV limit

ABIST

Default from NVM

BUCKn VOUT

I2C/SPI write

State control (or I2C/SPI write)

0x00

0

0x5F

0x5A

BUCKn_VSET1

BUCKn_VSET2

BUCKn_EN

Automa c control

by digital

1

0

1

0 us

BUCKn_OV_SET

(internal register, not

Register bits

0x00

0

0x5F

0x5A

accessible by user)

t_{PG_OV_UV_DELAY}

BUCKn_UV_SET

(internal register, not

0x5A

accessible by user)

BUCKn_VSEL

0

1

0

1

BUCKn_VMON_EN

Automa c control

by digital

Automa c control

by digital

0 us

Automa c control

by digital

BUCKn_OV Monitor Output

BUCKn_OV Ga ng

ABIST

50ꢀs

t_{PG_OV_GATE}

50ꢀs

Automa c control

by digital

0 us

BUCKn_UV Monitor Output

BUCKn_UV Ga ng

t_{PG_UV_GATE}

图8-13. AVS Voltage and OV UV Threshold Level Change Timing Diagram

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OPP_OD

(or OPP_TURBO)

OPP_OD

(or OPP_TURBO)

OPP_NOM

OV limit

UV limit

ABIST

UV limit

BUCKn VOUT

I2C/SPI write (DVFS control)

State control (or I2C/SPI write)

0x5F

1

0x73

BUCKn_VSET1

BUCKn_VSET2

BUCKn_EN

Automa c control

by digital

0

1

0 us

BUCKn_OV_SET

(internal register, not

0x5F

0

0x73

Register bits

accessible by user)

t_{PG_OV_UV_DELAY}

BUCKn_UV_SET

(internal register, not

0x73

accessible by user)

BUCKn_VSEL

1

0

1

BUCKn_VMON_EN

Automa c control

by digital

0 us

Automa c control

by digital

BUCKn_OV Monitor Output

BUCKn_OV Ga ng

ABIST

t_{PG_OV_GATE}

50ꢀs

0 us

BUCKn_UV Monitor Output

BUCKn_UV Ga ng

t_{PG_UV_GATE}

图8-14. DVS Voltage and OV UV Threshold Level Change Timing Diagram

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8.5.2 Sync Clock Functionality

The LP8764-Q1 device contains a SYNCCLKIN input to synchronize switching clock of the buck regulator with

the external clock. The block diagram of the clocking and DPLL module is shown in 图 8-15. The external clock

is selected when the external clock is available, and SEL_EXT_CLK = '1'. The nominal frequency of the external

input clock is set by EXT_CLK_FREQ[1:0] bits in the NVM and it can be 1.1 MHz, 2.2 MHz, 4.4 MHz, or 8.8

MHz.

The EXT_CLK_INT interrupt is also generated in cases the external clock is expected, but it is not available.

The LP8764-Q1 device can also generate clock SYNCCLKOUT for external device use. The

SYNCCLKOUT_FREQ_SEL[1:0] selects the frequency of the SYNCCLKOUT. Please note that

SYNCCLKOUT_FREQ_SEL[1:0] must stay static while SYNCCLKOUT is used, as changing the output

frequency selection may cause glitches on the clock output.

20 MHz

RC

Oscillator

Main CLK

Detector

RESET

Main Digital Clock

Buck1

Buck2

20 MHz

RC

Oscillator

÷ 18

Phase and

freq control

DPLL

/N

52.8MHz +/- 20%

SYNCCLKIN

Detector

Divider

SYNCCLKOUT

_FREQ_SEL

SYNCCLKOUT

Divider

“EXT_CLK_

FREQ“

Clock Select

Logic

Spread-spec

Control

SYNCCLKIN

SEL_EXT_CLK

图8-15. Sync Clock and DPLL Module

8.5.3 Internal Low Dropout Regulator (LDOVINT)

The LDOVINT voltage regulator is dedicated to supply the digital and analog functions of the LP8764-Q1 device.

The LDOVINT regulator is controlled by VCCA supply, when VCCA is available the LDOVINT is enabled.

8.6 Residual Voltage Checking

The residual voltage (RV) checking feature ensures the voltage level at the buck regulators or VMONx inputs is

below V_{TH_SC_RV}before it can be ramped up the target output voltage. If BUCKn/VMONn_RV_SEL=1 by default,

residual voltage is also checked before the device enters BOOT_BIST state. If the residual voltage is greater

than V_{TH_SC_RV}, the device waits until voltage goes below V_{TH_SC_RV}before starting BOOT_BIST.

This feature is enabled by the BUCKn_VMON_EN and BUCKn_RV_SEL bits for each buck regulators, and by

the VMONn_EN and VMONn_RV_SEL bits for VMON inputs. When this feature is enabled, the voltage monitor

of the corresponding regulator or monitoring input remains on after the monitoring is disabled, and remain on for

the RV Timeout period. After the RV Timeout period elapses the monitored voltage is compared to the short

circuit (SC) threshold of V_{TH_SC_RV}, and assert the corresponding BUCKn_SC_INT or VMONn_RV_INT interrupt

bits if the residual voltage is still higher than the threshold voltage. The RV timeout period for the BUCK

regulators and VMON inputs is automatically calculated by the digital controller inside the device by 方程式 3

and 方程式 4. If external voltage is monitored with buck feedback pin, buck is disabled all the time (BUCKn_EN

= 0).

t_{BUCK_RV_TIMEOUT}= BUCKn_VSET / BUCKn_SLEW_RATE + 100 µs

t_{VMON_RV_TIMEOUT}= VMONn_PG_VSET / VMONn_SLEW_RATE + 100 µs

(3)

(4)

图8-16 shows the timing diagram of the residual voltage checking operation that results in pass or fail results.

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图8-16. Residual Voltage Check Timing Diagram

备注

Unless mentioned otherwise in the User's Guide for the orderable part number, the residual voltage

monitoring is enabled .once, immediately after a power-up event on the VCCA input supply pin. Before

the LP8764-Q1 executes the start-up sequence of the BUCK regulators, the LP8764-Q1 disables all

residual voltage monitors. TI has made this implementation to prevent false-positive residual-voltage

detection caused by charge accumulation in the output capacitors of the BUCK regulators or at the

output voltage rails monitored through VMON_1 (at GPIO7 pin) or VMON_2 (at GPIO8 pin).

8.7 Output Voltage Monitor and PGOOD Generation

The LP8764-Q1 device monitors the undervoltage (UV) and overvoltage (OV) conditions on the output voltages

of the BUCK regulators, the UV and OV conditions on the VMONn voltage monitoring input pins , and VCCA

(when it is expected to be 5 V or 3.3 V), and has the option to indicate the result with a PGOOD signal. Thermal

warning can also be included in the result of the PGOOD monitor if it is not masked. Either voltage and current

monitoring or only voltage monitoring can be selected for PGOOD indication. This selection is set by the

PGOOD_SEL_BUCKn register bits for each BUCK regulator (select primary phase for multi-phase regulator).

When voltage and current are monitored, an active PGOOD signal active indicates that the regulator output is

inside the Power-Good voltage window and that load current is below the current limit. If only voltage is

monitored, then the current monitoring is ignored for the PGOOD signal.

The PGOOD signal represents the momentary status of the included indications without latching. If the PGOOD

signal goes low due to an indicated warning or error condition, the PGOOD signal goes high immediately when

the previous indicated warning or error condition is no longer present.

The BUCKn_VMON_EN bit enables the overvoltage (OV) , undervoltage (UV) and short-circuit (SC)

comparators. The current limit (ILIM) comparator of each BUCK regulator is activated as soon as the

corresponding BUCK regulator is enabled. In order to add the current limit indication of a BUCK regulator to the

PGOOD signal, the BUCKn_VMON_EN bit of the corresponding BUCK regulator must be set. When a BUCK is

not needed as a regulated output, it can be used as a voltage monitor for an external rail. For BUCK converters,

if the BUCKn_VMON_EN bit remains '1' while the BUCKn_EN bit is '0', it can be used as a voltage monitor for

an external rail that is connected to the FB_Bn pin of the BUCK regulator.

When the voltage monitor for a BUCK regulator is disabled, the output of the corresponding monitor is

automatically masked to prevent it from forcing PGOOD inactive. The masking allows PGOOD to be connected

to other open-drain power good signals in the system.

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The VCCA input voltage monitoring is enabled with VCCA_VMON_EN bit. The monitoring can be enabled by an

NVM default setting, that starts the monitoring of the VCCA voltage after the voltage monitor passes ABIST

during the BOOT BIST state. The reference voltage for the VCCA monitor can be set by the VCCA_PG_SET bit

to either 3.3 V or 5 V. The PGOOD_SEL_VCCA register bit selects whether or not the result of the VCCA

monitor is included in the PGOOD monitor output signal.

An NVM option is available to gate the PGOOD output with the nRSTOUT and the nRSTOUT_SoC signals, the

intended reset signals for the safety MCU and the SoC respectively. When PGOOD_SEL_NRSTOUT = '1', the

PGOOD pin is gated by the nRSTOUT signal. When PGOOD_SEL_NRSTOUT_SOC = '1', the PGOOD pin is

gated by the nRSTOUT_SoC signal. This option allows the PGOOD output to be used as an enable signal for

external peripherals.

The outputs of the voltage monitors from all the output rails are combined, and PGOOD is active only if all the

sources shows active status.

The type of output voltage monitoring for PGOOD signal is selected by PGOOD_WINDOW bit. If the bit is 0, only

undervoltage is monitored; if the bit is 1, then undervoltage and overvoltage are monitored.

The polarity and the output type (push-pull or open-drain) are selected by PGOOD_POL and GPIO9_OD bits.

图8-17 shows the Power-Good generation block diagram, and 图8-18 shows the Power-Good waveforms.

Die

Temperature

Monitor

T_J< T_WARN

TWARN_LEVEL

PGOOD_SEL_TDIE_WARN

BUCKn

Monitor

PGOOD_BUCKn

PGOOD_WINDOW

BUCKn_ILIM

BUCKn_VSET

BUCKn_VMON_EN

PGOOD_SEL_BUCKn

VMON

VMONn

LDOn

PGOOD_VMONn

PGOOD_WINDOW

Monitor

PGOOD

VMONn_PG_SET

VMONn_UV_THR

VMONn_OV_THR

VMONn_EN

PGOOD_SEL_VMONn

PGOOD_POL

PGOOD_VCCA

VCCA

Monitor

PGOOD_WINDOW

VCCA_PG_SET

VCCA_UV_THR

VCCA_OV_THR

VCCA_VMON_EN

PGOOD_SEL_VCCA

nRSTOUT

PGOOD_SEL_NRSTOUT

nRSTOUT_SOC

PGOOD_SEL_NRSTOUT_SOC

图8-17. PGOOD Block Diagram

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Voltage

Powergood window

BUCKx_VSET (1)

Power-good

window

BUCKx_VSET (2)

Time

On Request

VIO

BUCKn_VMON_EN

nRSTOUT

t_{MON_STARTUP_latency}

10 µs

PGOOD

(PGOOD_SEL_NRSTOUT =1)

t_{MON_STARTUP_latency}

PGOOD

(PGOOD_SEL_NRSTOUT = 0)

BUCKx_VSET (1)

BUCKx_VSET (2)

Regulator VSET

图8-18. PGOOD Waveforms

The OV and UV threshold of the voltage monitors of the BUCK regulators and VMON input voltage monitor are

updated automatically by the digital control block when the voltage setting changes. When the output voltage of

the regulator is increased, the OV threshold is updated at the same time the _VSET of the regulator or the

PG_LEVEL of the VMON is changed. The UV threshold is updated after a delay calculated by the delta voltage

change and the slew rate setting. When the output voltage is decreased, the UV threshold is updated at the

same time the _VSET of the regulator or PG_SET of the VMON is changed. The OV threshold is updated after a

delay calculated by the delta voltage change and the slew rate setting. The OV and UV threshold of the BUCK

output voltage monitors and VMON input voltage monitors are calculated based on the target output voltage set

by the corresponding BUCKn_VSET1, BUCKn_VSET2 , or VMONn_PG_SET registers, and the deviation from

the target output voltage set (the voltage window) by the corresponding BUCKn_UV_THR, BUCKn_OV_THR,

VMONn_UV_THR, and the VMONn_OV_THR registers. For the OV and UV threshold of BUCK output monitors

to update with the correct timing, the following operating procedures must be followed when updating the _VSET

values of the regulators to avoid detection of OV/UV fault:

• BUCK regulators must be enabled at the same time as or earlier than as their VMON, such that the voltage

reaches its target value before OV/UV self-test (BIST) is done

• New voltage level must not be set before the start-up has finished and OV/UV self-test (BIST) is completed

• New voltage level must not be set before the previous voltage change (ramp plus settling time) has

completed

It is important to note: when a regulator is enabled, a voltage monitor self-test is performed to ensure proper

operation. The monitoring function is disabled and gated during this time. 图 8-19 shows the timing diagram of

the BUCK regulator UV/OV self-test. 图 8-20 shows the timing diagram of the VMON UV/OV self-test. The

monitoring function is activated after the gating period.

The self-test for VCCA, BUCK and VMON voltage monitors is done every time when the monitoring function is

enabled and VMON_ABIST_EN=1. The self-test checks that OV and UV comparators are changing their output

when the input thresholds are swapped. The self-test assumes that the input voltage is inside OV/UV threshold

limits. If the voltage is outside the limits, the self-test fails and BIST_FAIL_INT interrupt is set. In addition, a failed

self-test for over-voltage comparator sets the over-voltage interrupt.

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OV/UV test 1 & 2:

25µs + 25µs

OV limit

UV limit

Settling time

BUCKx VOUT

Ramp time

Vout/SR

Start-up delay

BUCKx_VMON_EN

BUCKx_EN

buckx_ov_gating

buckx_uv_gating

50µs

t_{PG_OV_GATE}

Total time: t_{PG_UV_GATE}

图8-19. Timing of BUCK Regulator UV/OV Self-Test

The voltage monitors of unused BUCK regulators can be used for external supply rails monitoring. In three-

phase configuration, the Voltage Monitor of BUCK3 (on FB_B3 pin) becomes a free available resource for

monitoring an external supply voltage. In four-phase configuration, the Voltage Monitor of both BUCK3 (on

FB_B3 pin) and BUCK4 (on FB_B4 pin) become free available resources for monitoring two external supply

voltages.. The target output voltage is set by the corresponding BUCKn_VSET1, BUCKn_VSET2 registers, and

the deviation from the target output voltage set (the voltage window) by the corresponding BUCKn_UV_THR,

BUCKn_OV_THR registers. Following aspects need to be taken into account if Voltage Monitors of unused

BUCK regulators are used for monitoring external supply rails:

• For voltage monitors of unused BUCK : the maximum nominal supply voltage of the monitored supply rail is

3.3V

• For voltage monitors of unused BUCK regulators and for voltage monitors of BUCK3 and/or BUCK4

regulators if used in a three-phase or four-phase configuration: the configured values for the BUCKn_VSET

and the BUCKn_SLEW_RATE determine the delay-time for the voltage monitoring to become active after the

corresponding BUCKn_VMON_EN bit is set. See equation (2) in 节8.5.1.5. If BUCK3 and/or BUCK4

regulators are used in a three-phase or four-phase configuration: even though the values for the

BUCK1_VSET and BUCK1_SLEW_RATE bits determine the output voltage and slew-rate of the three-phase

or four-phase output rail, the values for BUCK3_VSET respectively BUCK4_VSET and BUCK3_SLEW_RATE

respectively BUCK4_SLEW_RATE bits determine the power-good level and the voltage monitoring delay

time for the BUCK3 respectively BUCK4 Voltage Monitors.

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OV/UV test 1 & 2:

25µs + 25µs

OV limit

UV limit

Settling time

VMONx input

Ramp time

PG_SET/SR

Start-up delay

VMONx_EN

vmonx_ov_gaꢀng

vmonx_uv_gaꢀng

50µs

t_{PG_OV_GATE}

Total time: t_{PG_UV_GATE}

图8-20. Timing of VMON Input UV/OV Self-Test

The voltage monitoring threshold for the VMONx input pins are shown in 表8-12.

备注

For Voltage Monitors that are used to monitor external supply voltages, in order to not have a failing

self-test or a false-positive UV/OV detection after completion of the self-test, the actual voltage level of

the external supply (VOUT_actual) must satisfy following conditions:

• For VOUT > 1V: VOUT_actual = VOUT_typical +/- (75% * Typical UV/OV Threshold –1%)

• For VOUT ≤1V: VOUT_actual = VOUT_typical +/- (Typical UV/OV Threshold –15mV)

VOUT_typical is the configured power-good voltage level for the used Voltage Monitor in registers

BUCKn_VOUT1/2 and VMONn_PG_LEVEL. This requirement also applies to the voltage on the

VCCA pin in case the VCCA UV/OV Monitor is used.

表8-12. Monitoring Voltage Selection for VMONx External Voltage Pins

Output

Voltage [V]

VMO

Nx_P

G_SE

T

VMO

Nx_P

G_SE

T

VMO

Nx_P

G_SE

T

VMO

Nx_P

G_SE

T

VMO

Nx_P

G_SE

T

VMO

Nx_P

G_SE

T

VMO

VMO VMON

Nx_R x_RA

ANG NGE =

VMO VMON

Nx_R x_RA

ANG NGE =

VMO VMON

Nx_R x_RA

ANG NGE =

VMO VMON

Nx_R x_RA

ANG NGE =

VMONx

_RANG

E = 1

VMON

Nx_R

x_RAN

ANG

Nx_R

ANG

E = 0

GE = 1

E = 0

1

E = 0

1

E = 0

1

E = 0

1

Reserve

d

Reserv

ed

Reser

ved

Reser

ved

0x00

0.3

0x0F

0.6

ed

0x41 0.85

4.25 0x73

1.1

0xAB 1.66

0xAC 1.68

0xAD 1.7

0xAE 1.72

0xAF 1.74

0xB0 1.76

0xD6 2.52

0xD7 2.54

0xD8 2.56

0xD9 2.58

0xDA 2.6

0xDB 2.62

Reserve

d

Reserv

ed

Reser

ved

Reser

ved

0x01 0.32

0x02 0.34

0x03 0.36

0x04 0.38

0x10 0.605

0x42 0.855 4.275 0x74

1.11

ed

Reserve

d

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x11

0.61

0x43 0.86

4.3 0x75 1.12

Reserve

d

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x12 0.615

0x13 0.62

0x14 0.625

0x44 0.865 4.325 0x76 1.13

Reserve

d

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x45 0.87

4.35 0x77 1.14

Reserve

d

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x05

0.4

0x46 0.875 4.375 0x78 1.15

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表8-12. Monitoring Voltage Selection for VMONx External Voltage Pins (continued)

Output

Voltage [V]

Output

Voltage [V]

VMO

Nx_P

G_SE

T

VMO

Nx_P

G_SE

T

VMO

Nx_P

G_SE

T

VMO

Nx_P

G_SE

T

VMO

Nx_P

G_SE

T

VMO

Nx_P

G_SE

T

VMO

VMO VMON

Nx_R x_RA

ANG NGE =

VMO VMON

Nx_R x_RA

ANG NGE =

VMO VMON

Nx_R x_RA

ANG NGE =

VMO VMON

Nx_R x_RA

ANG NGE =

VMONx

_RANG

E = 1

VMON

Nx_R

x_RAN

ANG

Nx_R

ANG

E = 0

GE = 1

E = 0

1

E = 0

1

E = 0

1

E = 0

1

Reserve

d

Reserv

ed

Reser

ved

Reser

ved

0x06 0.42

0x07 0.44

0x08 0.46

0x09 0.48

0x15 0.63

0x16 0.635

0x17 0.64

0x18 0.645

0x19 0.65

0x1A 0.655

0x1B 0.66

0x1C 0.665

0x1D 0.67

0x47 0.88

4.4 0x79 1.16

0xB1 1.78

0xDC 2.64

0xDD 2.66

0xDE 2.68

ed

Reserve

d

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x48 0.885 4.425 0x7A 1.17

0xB2

1.8

Reserve

d

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x49 0.89

4.45 0x7B 1.18

0xB3 1.82

0xB4 1.84

0xB5 1.86

0xB6 1.88

Reserve

d

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x4A 0.895 4.475 0x7C 1.19

0xDF

2.7

Reserve

d

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x0A

0.5

0x4B

0.9

4.5 0x7D

1.2

0xE0 2.72

0xE1 2.74

0xE2 2.76

0xE3 2.78

Reserve

d

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x0B 0.52

0x0C 0.54

0x0D 0.56

0x0E 0.58

0x4C 0.905 4.525 0x7E 1.21

Reserve

d

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x4D 0.91

4.55 0x7F 1.22

0xB7

1.9

Reserve

d

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x4E 0.915 4.575 0x80 1.23

0xB8 1.92

0xB9 1.94

0xBA 1.96

0xBB 1.98

Reserve

d

Reserv

ed

Reser

ved

Reser

ved

3.35 0x4F 0.92

4.6 0x81 1.24

0xE4

2.8

Reserv

ed

Reser

ved

Reser

ved

0x1E 0.675 3.375 0x50 0.925 4.625 0x82 1.25

0xE5 2.82

0xE6 2.84

0xE7 2.86

0xE8 2.88

Reserv

ed

Reser

ved

Reser

ved

0x1F 0.68

3.4

0x51 0.93

4.65 0x83 1.26

Reserv

ed

Reser

ved

Reser

ved

0x20 0.685 3.425 0x52 0.935 4.675 0x84 1.27

0xBC

2

Reserv

ed

Reser

ved

Reser

ved

0x21 0.69

3.45 0x53 0.94

4.7 0x85 1.28

0xBD 2.02

0xBE 2.04

0xBF 2.06

0xC0 2.08

Reserv

ed

Reser

ved

Reser

ved

0x22 0.695 3.475 0x54 0.945 4.725 0x86 1.29

0xE9

2.9

Reserv

ed

Reser

ved

Reser

ved

0x23

0.7

3.5

0x55 0.95

4.75 0x87

1.3

0xEA 2.92

0xEB 2.94

0xEC 2.96

0xED 2.98

Reserv

ed

Reser

ved

Reser

ved

0x24 0.705 3.525 0x56 0.955 4.775 0x88 1.31

Reserv

ed

Reser

ved

Reser

ved

0x25 0.71

3.55 0x57 0.96

4.8 0x89 1.32

0xC1

2.1

Reserv

ed

Reser

ved

Reser

ved

0x26 0.715 3.575 0x58 0.965 4.825 0x8A 1.33

0xC2 2.12

0xC3 2.14

0xC4 2.16

Reserv

ed

Reser

ved

Reser

ved

0x27 0.72

3.6

0x59 0.97

4.85 0x8B 1.34

0xEE

3.0

Reserv

ed

Reser

ved

Reser

ved

0x28 0.725 3.625 0x5A 0.975 4.875 0x8C 1.35

0xEF 3.02

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表8-12. Monitoring Voltage Selection for VMONx External Voltage Pins (continued)

Output

Voltage [V]

VMO

Nx_P

G_SE

T

VMO

Nx_P

G_SE

T

VMO

Nx_P

G_SE

T

VMO

Nx_P

G_SE

T

VMO

Nx_P

G_SE

T

VMO

Nx_P

G_SE

T

VMO

VMO VMON

Nx_R x_RA

ANG NGE =

VMO VMON

Nx_R x_RA

ANG NGE =

VMO VMON

Nx_R x_RA

ANG NGE =

VMO VMON

Nx_R x_RA

ANG NGE =

VMONx

_RANG

E = 1

VMON

Nx_R

x_RAN

ANG

Nx_R

ANG

E = 0

GE = 1

E = 0

1

E = 0

1

E = 0

1

E = 0

1

Reserv

ed

Reser

ved

Reser

ved

0x29 0.73

3.65 0x5B 0.98

4.9 0x8D 1.36

0xC5 2.18

0xF0 3.04

0xF1 3.06

0xF2 3.08

Reserv

ed

Reser

ved

Reser

ved

0x2A 0.735 3.675 0x5C 0.985 4.925 0x8E 1.37

0xC6

2.2

Reserv

ed

Reser

ved

Reser

ved

0x2B 0.74

3.7

0x5D 0.99

4.95 0x8F 1.38

0xC7 2.22

0xC8 2.24

0xC9 2.26

0xCA 2.28

0xCB 2.3

0xCC 2.32

0xCD 2.34

0xCE 2.36

0xCF 2.38

Reserv

ed

Reser

ved

Reser

ved

0x2C 0.745 3.725 0x5E 0.995 4.975 0x90 1.39

0xF3

3.1

Reserv

ed

Reser

ved

Reser

ved

0x2D 0.75

3.75 0x5F

1.0

5.0 0x91

1.4

0xF4 3.12

0xF5 3.14

0xF6 3.16

0xF7 3.18

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x2E 0.755 3.775 0x60 1.005

0x92 1.41

0x93 1.42

0x94 1.43

0x95 1.44

0x96 1.45

0x97 1.46

0x98 1.47

0x99 1.48

0x9A 1.49

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x2F 0.76

3.8

0x61 1.01

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x30 0.765 3.825 0x62 1.015

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x31 0.77

3.85 0x63 1.02

0xF8

3.2

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x32 0.775 3.875 0x64 1.025

0xF9 3.22

0xFA 3.24

0xFB 3.26

0xFC 3.28

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x33 0.78

3.9

0x65 1.03

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x34 0.785 3.925 0x66 1.035

0xD0

2.4

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x35 0.79

3.95 0x67 1.04

0xD1 2.42

0xD2 2.44

0xD3 2.46

0xD4 2.48

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x36 0.795 3.975 0x68 1.045

0xFD

3.3

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x37

0.8

4.0

0x69 1.05

0x9B

1.5

0xFE 3.32

0xFF 3.34

Reserv

ed

Reserv

ed

Reser

ved

Reser

ved

0x38 0.805 4.025 0x6A 1.055

0x9C 1.51

0x9D 1.52

0x9E 1.53

0x9F 1.54

0xA0 1.55

Reserv

ed

Reserv

ed

Reser

ved

0x39 0.81

4.05 0x6B 1.06

0xD5

2.5

Reserv

ed

Reserv

ed

0x3A 0.815 4.075 0x6C 1.065

Reserv

ed

Reserv

ed

0x3B 0.82

4.1

0x6D 1.07

Reserv

ed

Reserv

ed

0x3C 0.825 4.125 0x6E 1.075

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表8-12. Monitoring Voltage Selection for VMONx External Voltage Pins (continued)

Output

Voltage [V]

Output

Voltage [V]

VMO

Nx_P

G_SE

T

VMO

Nx_P

G_SE

T

VMO

Nx_P

G_SE

T

VMO

Nx_P

G_SE

T

VMO

Nx_P

G_SE

T

VMO

Nx_P

G_SE

T

VMO

VMO VMON

Nx_R x_RA

ANG NGE =

VMO VMON

Nx_R x_RA

ANG NGE =

VMO VMON

Nx_R x_RA

ANG NGE =

VMO VMON

Nx_R x_RA

ANG NGE =

VMONx

_RANG

E = 1

VMON

Nx_R

x_RAN

ANG

Nx_R

ANG

E = 0

GE = 1

E = 0

1

E = 0

1

E = 0

1

E = 0

1

Reserv

ed

Reserv

ed

0x3D 0.83

4.15 0x6F 1.08

0xA1 1.56

0xA2 1.57

0xA3 1.58

0xA4 1.59

Reserv

ed

Reserv

ed

0x3E 0.835 4.175 0x70 1.085

Reserv

ed

Reserv

ed

0x3F 0.84

4.2

0x71 1.09

Reserv

ed

Reserv

ed

0x40 0.845 4.225 0x72 1.095

Reserv

ed

0xA5

1.6

Reserv

ed

0xA6 1.61

0xA7 1.62

0xA8 1.63

0xA9 1.64

0xAA 1.65

Reserv

ed

Reserv

ed

Reserv

ed

Reserv

ed

8.8 General-Purpose I/Os (GPIO Pins)

The LP8764-Q1 device integrates ten configurable general-purpose I/Os that are multiplexed with alternative

features as listed in Pin Configuration and Functions.

For GPIOs characteristics, refer to Electrical Characteristics tables for Digital Input Signal Parameters and Digital

Output Signal Parameters.

When configured as primary functions, all GPIOs are controlled through the following set of registers bits under

the individual GPIOn_CONF register.

• GPIOn_DEGLITCH_EN: Enables the 8 µs deglitch time for each GPIO pin (input)

• GPIOn_PU_PD_EN: Enables the internal pull up or pull down resistor connected to each GPIO pin

• GPIOn_PU_SEL: Selects the pull up or the pull down resistor to be connected when GPIOn_PU_PD_EN =

'1'. '1' = pull-up resistor selected, '0' = pull-down resistor selected

• GPIOn_OD: Configures the GPIO pin (output) as: '1' = open drain, '0' = push-pull

• GPIOn_DIR: Configures the input or output direction of each GPIO pin

Each GPIO event can generate an interrupt on a rising edge, falling edge, or both, configured through the

GPIOn_FALL_MASK and the GPIOn_RISE_MASK register bits. A GPIO-interrupt applies when the primary

function (general-purpose I/O) has been selected and also for the following alternative functions:

• ENABLE

• EN_DRV

• nRSTOUT

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• nRSTOUT_SOC

• PGOOD

• nERR_MCU

• TRIG_WDOG

• NSLEEP1, NSLEEP2

• WKUP1, WKUP2

The GPIOn_SEL[2:0] register bits under the GPIOn_CONF registers control the selection between a primary and

an alternative function. When a pre-defined function is selected, some predetermined IO characteristics (such as

pullup, pulldown, push-pull or open drain) for the pin are enforced regardless of the settings of the associated

GPIO configuration register. Please note that if the GPIOn_SEL[2:0] is changed during device operation, a signal

glitch may occur, which may cause digital malfunction, especially if it involves a clock signal such as SCL_I2C2,

SCL_SPMI, SYNCCLKIN, or SYNCCLKOUT. Please refer to Digital Signal Descriptions for more detail on the

predetermined IO characteristics for each pre-defined digital interface function.

All GPIOs can be configured as a wake-up input when it is configured as a WKUP1 or a WKUP2 signal. All

GPIOs can also be configured as a NSLEEP1 or a NSLEEP2 input. For more information regarding the usage of

the NSLEEPx pins and the WKUPx pins, please refer to 节8.4.2.4.2.1 and 节8.4.2.4.2.2.

Any of the GPIO pin can also be configured as part of the power-up sequence to enable external devices such

as external BUCKs when it is configured as a general-purpose output port.

The nINT pin and the GPIO pins assigned as EN_DRV , nRSTOUT and nRSTOUT_SOC have readback

monitoring to detect errors on the signals. The monitoring of the GPIO pin assigned as EN_DRV checks for

mismatch in both low and high levels. For the nINT pin and the GPIO pins assigned as nRSTOUT and

nRSTOUT_SOC, the readback monitoring only checks for mismatches in the low level, therefore it is allowed to

combine these signals with other external pull-down sources. The readback mismatch is continuously monitored

without deglitch circuitry during operation, and the monitoring is gated for t_{gate_readback}period when the signal

state is changed or when a new function is selected for the GPIO pin with the GPIOn_SEL bits.

NINT_READBACK_INT,

EN_DRV_READBACK_INT,

NRSTOUT_READBACK_INT,

and

NRSTOUT_SOC_READBACK_INT are the interrupt bits that are set in an event of a readback mismatch for

these pins, respectively.

备注

All GPIO pin are set to generic input pins with resistive pull-down before NVM memory is loaded

during device power up. Therefore, if any GPIOs has external pull-up resistors connecting to a voltage

domain that is energized before the NVM memory is loaded, the GPIO pin is pulled high before the

configuration for the pin is loaded from the NVM.

备注

For GPIO pins with internal pull down enabled, additional leakage current flows into the GPIO pin if

this pin is pulled-up to a voltage higher than the voltage level of its output power domain. If the internal

pull down must be enabled, please use a resistor divider to divide down the input voltage, or use a

series resistor to connect to the input source and ensure the voltage level at the GPIO pin is below the

voltage level of its output power domain.

8.9 Thermal Monitoring

The LP8764-Q1 device includes several thermal monitoring functions for internal thermal protection of the PMIC.

The LP8764-Q1 device integrates thermal detection modules to monitor the temperature of the die. These

modules are placed on opposite sides of the device and close to the BUCK modules. An over-temperature

condition at either module first generates a warning to the system, and if the temperature continues to rise, then

a switch-off of the PMIC device can occur before damage to the die.

Three thermal protection levels are available. One of these protections is a thermal warning function described in

节 8.9.1, that sends an interrupt to software. Software is expected to close any noncritical running tasks to

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reduce power. The second and third protections are the thermal shutdown (TS) function described in 节 8.9.2,

that begins device shutdown orderly or immediately.

Thermal monitoring is automatically enabled when one of the BUCK outputs is enabled within the mission states.

The thermal monitoring is disabled in the LP_STANDBY state, when only the internal regulator is enabled, to

minimize the device power consumption. Indication of a thermal warning event is written to the TWARN_INT

register.

The current consumption of the thermal monitoring can be decreased in the mission states when the low power

dissipation is important. If LPM_EN bit is set and the temperature is below thermal warning level in all thermal

detection modules, only one thermal detection module is monitored. If the temperature rises in this module,

monitoring in all thermal detection modules is started.

If the die temperature of the LP8764-Q1 device continues to rise while the device is in mission state, an

TSD_ORD_INT or TSD_IMM_INT interrupt is generated, causing a SEVERE or MODERATE error trigger

(respectively) in the state machine. While the sequencing and error handling is NVM memory dependent, TI

recommends a sequenced shutdown for MODERATE errors, and an immediate shutdown, using resistive

discharging, for SEVERE errors to prevent damage to the device. The system cannot restart until the

temperature falls below the thermal warning threshold.

8.9.1 Thermal Warning Function

The thermal monitor provides a warning to the host processor through the interrupt system when the

temperature reaches within a cautionary range. The threshold value must be set to less than the thermal

shutdown threshold.

The integrated thermal warning function provides the MCU an early warning of over-temperature condition. This

monitoring system is connected to the interrupt controller and can send an TWARN_INT interrupt when the

temperature is higher than the preset threshold. The LP8764-Q1 device uses the TWARN_LEVEL register bit to

set the thermal warning threshold temperature at 130°C or 140°C. There is no hysteresis for the thermal warning

level.

When the power-management software triggers an interrupt, immediate action must be taken to reduce the

amount of power drawn from the PMIC device (for example, noncritical applications must be closed).

8.9.2 Thermal Shutdown

The thermal shutdown detector monitors the temperature on the die. If the junction reaches a temperature at

which damage can occur, a switch-off transition is initiated and a thermal shutdown event is written into a status

register. There are two levels of thermal shutdown threshold. When the die temperature reaches the T_{SD_orderly}

level, the LP8764-Q1 device performs an orderly shutdown of all output power rails. If the die temperature raises

rapidly and reaches the T_{SD_imm}level before the orderly shutdown process completes, the LP8764-Q1 device

performs an immediate shutdown with activated pull-down on all output power rails, in order to turn off all of the

output power rails as rapidly as possible. After the thermal shutdown takes place, the system cannot restart until

the die temperature is below the thermal warning threshold.

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8.10 Interrupts

The interrupt registers in the device are organized in hierarchical fashion. The interrupts are grouped into the

following categories:

BUCK ERROR

These interrupts indicate over-voltage (OV), under-voltage (UV), short-circuit (SC),

residual voltage (also indicated as SC interrupt) and over-current (ILIM) error

conditions found on the BUCK regulators .

VMON ERROR

These interrupts indicate OV and UV or residual voltage error conditions found on the

VMON1 and VMON2 inputs and on the VCCA supply.

SEVERE ERROR

These errors indicate severe device error conditions, such as thermal shutdown,

PFSM sequencing and execution error and VCCA over-voltage, that causes the

device to trigger the PFSM to execute immediate shutdown of all digital outputs,

external voltage rails and monitors, and proceed to the Safe Recovery State.

MODERATE ERROR

These interrupts provide warnings to the system to indicate multiple restart attempts

from SAFE RECOVERY state exceeding the allowed recovery count, multiple warm-

reset executions exceeding the allowed recovery count, SPMI communication error,

register CRC error, BIST failure, read-back error on nRSTOUT or nINT pins, or

junction temperature reaching orderly shutdown level. These warning causes the

device to trigger the PFSM to execute orderly shutdown of all digital outputs, external

voltage rails and monitors, and proceed to the SAFE RECOVERY state.³

MISCELLANEOUS

WARNING

These interrupts provide information to the system to indicate detection of WDOG or

ESM errors, die temperature crossing thermal warning threshold, device passing

BIST test, or external sync clock availability.

START-UP SOURCE

GPIO DETECTION

These interrupts provide information to the system on the mechanism that caused the

device to start up, which includes FSD, the activation of the ENABLE pin

These interrupts indicate the High/Rising-Edge or the Low/Falling-Edge detection at

the GPIO1 through GPIO10 pins.

FSM ERROR

INTERRUPT

These interrupts indicate the detection of an error that causes the device mission

state changes.

All interrupts are logically combined on a single output pin, nINT (active low). The host processor can read the

INT_TOP register to find the interrupt registers to find out the source of the interrupt, and write '1' to the

corresponding interrupt register bit to clear the interrupt. This mechanism ensures when a new interrupt occurs

while the nINT pin is still active, all of the corresponding interrupt register bits retain the interrupt source

information until it is cleared by the host.

Some of the interrupts and EN_DRV status are also sent to host during SPI communication. See 节 8.11.3 for

more information on SPI status signals.

Hierarchical Structure of Interrupt Registers shows the hierarchical structure of the interrupt registers according

to the categories described above. The purpose of this register structure is to reduce the number of interrupt

register read cycles the host has to perform in order to identify the source of the interrupt. Summary of Interrupt

Signals summarizes the trigger and the clearing mechanism for all of the interrupt signals. This table also shows

which interrupt sources can be masked by setting the corresponding mask register to '1'. When an interrupt is

masked, the interrupt bit is not updated when the associated event occurs, the nINT line is not affected, and the

event is not recorded. If an interrupt is masked after the event occurred, the interrupt register bit reflects the

event until the bit is cleared. While the event is masked, the interrupt register bit is not over-written when a new

event occurs.

More detail descriptions of each interrupt register can be found in 节8.16.

3

The SEVERE ERROR and the MODERATE ERROR are handled in NVM memory but TI requires that the NVM pre-configurable finite

state machine (PFSM) settings always follow this described error handling to meet device specifications.

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INT_FSM_ERR[7:0]

READBACK

_ERR_INT

SOC_PWR

_ERR_INT

MCU_PWR

_ERR_INT

ORD_

SHUTDOWN_INT

IMM_

SHUTDOWN_INT

WD_INT

ESM_INT

COMM_ERR_INT

INT_COMM_ERR[7:0]

I2C2_ADR

_ERR_INT

I2C2_CRC

_ERR_INT

COMM_ADR

_ERR_INT

COMM_CRC

_ERR_INT

COMM_FRM

_ERR_INT

INT_READBACK_ERR[7:0]

NRSTOUT_SOC

_READBACK_INT

EN_DRV

_READBACK_INT

INT_ESM[7:0]

ESM_MCU

_RST_INT

ESM_MCU

_FAIL_INT

ESM_MCU

_PIN_INT

INT_SEVERE_ERR[7:0]

PFSM_ERR_INT

VCCA_OVP_INT

BIST_FAIL_INT

EXT_CLK_INT

ENABLE_INT

TSD_IMM_INT

TSD_ORD_INT

BIST_PASS_INT

INT_MODERATE_ERR[7:0]

NRSTOUT

_READBACK_INT

NINT

_READBACK_INT

SPMI_ERR_INT

RECOV_CNT_INT

REG_CRC_ERR_INT

INT_MISC[7:0]

INT_STARTUP[7:0]

INT_GPIO[7:0]

TWARN_INT

SOFT_REBOOT_INT

FSD_INT

GPIO1_8_INT

GPIO4_INT

GPIO10_INT

GPIO2_INT

GPIO9_INT

GPIO1_INT

INT_GPIO1_8[7:0]

GPIO8_INT

GPIO7_INT

GPIO6_INT

GPIO5_INT

GPIO3_INT

INT_VMON[7:0]

VMON2_RV_INT

VMON2_UV_INT

VMON2_OV_INT

VMON1_RV_INT

VMON1_UV_INT

VMON1_OV_INT

VCCA_UV_INT

VCCA_OV_INT

INT_BUCK[7:0]

BUCK3_4_INT

BUCK3_UV_INT

BUCK1_UV_INT

BUCK1_2_INT

BUCK3_OV_INT

BUCK1_OV_INT

INT_BUCK3_4[7:0]

BUCK4_ILIM_INT

BUCK4_SC_INT

BUCK2_SC_INT

BUCK4_UV_INT

BUCK2_UV_INT

BUCK4_OV_INT

BUCK2_OV_INT

BUCK3_ILIM_INT

BUCK1_ILIM_INT

BUCK3_SC_INT

BUCK1_SC_INT

INT_BUCK1_2[7:0]

BUCK2_ILIM_INT

图8-21. Hierarchical Structure of Interrupt Registers

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表8-13. Summary of Interrupt Signals

MASK FOR

INTERRUPT

CLEAR

EVENT

TRIGGER FOR FSM

RESULT ⁽¹⁾

RECOVERY

INTERRUPT BIT

LIVE STATUS BIT

INTERRUPT

EN_ILIM_FSM_CTR

L=1:

According to

BUCKn_GRP_SEL

and x_RAIL_TRIG

bits

EN_ILIM_FSM_CTR

L=0:

N/A

EN_ILIM_FSM_CT

RL=1:

Transition according Depends on PFSM

to FSM trigger and configuration, see

interrupt

EN_ILIM_FSM_CT diagram

RL=0:

Write 1 to

BUCKn_ILIM_INT

bit

BUCK regulator

forward current limit

triggered

BUCKn_ILIM_INT =

1

BUCKn_ILIM_MASK

BUCKn_ILIM_STAT Interrupt is not

cleared if current

PFSM transition

limit violation is

active

Interrupt only

Write 1 to

BUCKn_SC_INT bit

Interrupt is not

cleared if the

According to

BUCK output or switch BUCKn_GRP_SEL

Regulator disable

and transition

according to FSM

Depends on PFSM

configuration, see

PFSM transition

BUCKn is enabled

and the BUCKn

output voltage is

below the short-

circuit threshold

after elapse of

expected ramp-up

time interval

BUCKn_SC_INT = 1 N/A

N/A

short circuit detected

and x_RAIL_TRIG

bits

trigger and interrupt diagram

Write 1 to

BUCKn_SC_INT bit

If BUCKn_SC_INT

was set due to a

detected residual

voltage, this bit can

only be read by the

MCU if the residual

voltage condition is

no longer present

and the device has

performed a

BUCKn_RV_SEL =

1

According to

BUCKn_GRP_SEL

and x_RAIL_TRIG

bits

BUCKn_RV_SEL =

0

BUCKn_RV_SEL =

1

Regulator disable

and transition

according to FSM

trigger and interrupt

BUCKn_RV_SEL =

0

Depends on PFSM

BUCK output residual

voltage violation

configuration, see

PFSM transition

diagram

BUCKn_SC_INT = 1 N/A

N/A

succesfull power-up

sequence

Write 1 to

BUCKn_OV_INT bit

Interrupt is not

According to

BUCKn_GRP_SEL

and x_RAIL_TRIG

bits

Depends on PFSM

configuration, see

PFSM transition

diagram

Transition according

to FSM trigger and

interrupt

BUCK regulator

overvoltage

BUCKn_OV_INT = 1 BUCKn_OV_MASK

BUCKn_UV_INT = 1 BUCKn_UV_MASK

VCCA_OV_INT = 1 VCCA_OV_MASK

VCCA_UV_INT = 1 VCCA_UV_MASK

BUCKn_OV_STAT cleared if the

associated fault

condition is still

present

Write 1 to

BUCKn_UV_INT bit

Interrupt is not

According to

BUCKn_GRP_SEL

and x_RAIL_TRIG

bits

Depends on PFSM

configuration, see

PFSM transition

diagram

Transition according

to FSM trigger and

interrupt

BUCK regulator

undervoltage

BUCKn_UV_STAT cleared if the

associated fault

condition is still

present

Write 1 to

VCCA_OV_INT bit

Interrupt is not

cleared if the

associated fault

condition is still

present

According to

VCCA_GRP_SEL

and x_RAIL_TRIG

bits

Depends on PFSM

configuration, see

PFSM transition

diagram

VCCA input

overvoltage

monitoring

Transition according

to FSM trigger and

interrupt

VCCA_OV_STAT

VCCA_UV_STAT

Write 1 to

VCCA_UV_INT bit

Interrupt is not

cleared if the

associated fault

condition is still

present

According to

VCCA_GRP_SEL

and x_RAIL_TRIG

bits

Depends on PFSM

configuration, see

PFSM transition

diagram

VCCA input

undervoltage

monitoring

Transition according

to FSM trigger and

interrupt

Write 1 to

VMONx_OV_INT bit

Interrupt is not

VMONx_OV_STAT cleared if the

associated fault

According to

VMONx_GRP_SEL

and X_RAIL_TRIG

bits

Depends on PFSM

configuration, see

PFSM transition

diagram

VMONx input

overvoltage

monitoring

Transition according

to FSM trigger and

interrupt

VMONx_OV_INT =

VMONx_OV_MASK

1

condition is still

present

Write 1 to

VMONx_UV_INT bit

Interrupt is not

According to

VMONx_GRP_SEL

and X_RAIL_TRIG

bits

Depends on PFSM

configuration, see

PFSM transition

diagram

VMONx input

undervoltage

monitoring

Transition according

to FSM trigger and

interrupt

VMONx_UV_INT =

VMONx_UV_MASK

1

VMONx_UV_STAT cleared if the

associated fault

condition is still

present

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表8-13. Summary of Interrupt Signals (continued)

MASK FOR

INTERRUPT

CLEAR

EVENT

TRIGGER FOR FSM

RESULT ⁽¹⁾

RECOVERY

INTERRUPT BIT

LIVE STATUS BIT

INTERRUPT

VMONx_RV_SEL =

1

According to

VMONn_GRP_SEL

and x_RAIL_TRIG

bits

VMONx_RV_SEL =

0

VMONx_RV_SEL =

1

Transition according Depends on PFSM

to FSM trigger and configuration, see

interrupt

VMONx_RV_SEL = diagram

VMONx residual

voltage violation

VMONx_RV_INT =

1

Write 1 to

VMONx_RV_INT bit

N/A

PFSM transition

0

N/A

Write 1 to

TWARN_INT bit

Interrupt is not

cleared if

Thermal warning

N/A

Interrupt only

Not valid

TWARN_INT = 1

TWARN_MASK

TWARN_STAT

temperature is

above thermal

warning level

Write 1 to

TSD_ORD_INT bit

This interrupt bit can

only be read by the

MCU after the

device has

recovered from a

previously occurred

over-temperature

event.

All regulators

disabled and Output STARTUP_DEST[1:0]

GPIOx set to low in state after

Automatic start-up to

ORDERLY_SHUTDO

WN

(MODERATE_ERR_I

NT)

Thermal shutdown,

orderly sequenced

TSD_ORD_INT = 1 N/A

TSD_ORD_STAT

a sequence and

temperature is below

TWARN level

interrupt⁽¹⁾

Write 1 to

TSD_IMM_INT bit

This interrupt bit can

only be read by the

MCU after the

device has

recovered from a

previously occurred

over-temperature

event.

All regulators

Automatic start-up to

STARTUP_DEST[1:0]

state after

temperature is below

TWARN level

disabled with pull-

down resistors and

Output GPIOx set to

low immediately

and interrupt⁽¹⁾

IMMEDIATE_SHUTD

OWN

(SEVERE_ERR_INT)

Thermal shutdown,

immediate

TSD_IMM_INT = 1

N/A

TSD_IMM_STAT

All regulators

disabled and Output Automatic start-up to

GPIOx set to low

immediately and

interrupt⁽¹⁾

ORDERLY_SHUTDO

WN

(MODERATE_ERR_I

NT)

Write 1 to

BIST_FAIL_INT bit

BIST error

STARTUP_DEST[1:0] BIST_FAIL_INT = 1 BIST_FAIL_MASK

state

N/A

All regulators

disabled and Output Automatic start-up to

GPIOx set to low

immediately and

interrupt⁽¹⁾

ORDERLY_SHUTDO

WN

(MODERATE_ERR_I

NT)

Write 1 to

REG_CRC_ERR_IN

T bit

REG_CRC_ERR_IN

T = 1

Register CRC error

STARTUP_DEST[1:0]

state

REG_CRC_ERR_MASK N/A

All regulators

disabled and Output Automatic start-up to

GPIOx set to low

immediately and

interrupt⁽¹⁾

ORDERLY_SHUTDO

SPMI communication WN

Write 1 to

SPMI_ERR_INT bit

STARTUP_DEST[1:0] SPMI_ERR_INT = 1 SPMI_ERR_MASK

state

N/A

error

(MODERATE_ERR_I

NT)

Write 1 to

COMM_FRM_ERR_

INT bit

COMM_FRM_ERR_ COMM_FRM_ERR_MA

Not valid

SPI frame error

N/A

Interrupt only

N/A

INT = 1

SK

Write 1 to

COMM_CRC_ERR_

INT bit

COMM_CRC_ERR_ COMM_CRC_ERR_MA

INT = 1 SK

I2C1 or SPI CRC error N/A

Not valid

Write 1 to

COMM_ADR_ERR_

INT bit

I2C1 or SPI address

COMM_ADR_ERR_ COMM_ADR_ERR_MA

N/A

error⁽⁴⁾

INT = 1

SK

Write 1 to

I2C2_CRC_ERR_IN

T bit

I2C2_CRC_ERR_IN

T = 1

I2C2 CRC error

N/A

I2C2_CRC_ERR_MASK N/A

I2C2_ADR_ERR_MASK N/A

Write 1 to

I2C2_ADR_ERR_IN

T bit

I2C2_ADR_ERR_IN

T = 1

I2C2 address error⁽⁴⁾

Automatic start-up to

STARTUP_DEST[1:0]

state. If previous

PFSM_ERR_INT is

pending, VCCA power

cycle needed for

recovery.

All regulators

disabled with pull-

down resistors and

Output GPIOx set to

low immediately

and interrupt⁽¹⁾

IMMEDIATE_SHUTD

OWN

(SEVERE_ERR_INT)

PFSM_ERR_INT =

1

Write 1 to

PFSM_ERR_INT bit

PFSM error

N/A

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表8-13. Summary of Interrupt Signals (continued)

MASK FOR

INTERRUPT

CLEAR

EVENT

TRIGGER FOR FSM

RESULT ⁽¹⁾

RECOVERY

INTERRUPT BIT

LIVE STATUS BIT

INTERRUPT

Write 1 to

EN_DRV_READBA

CK_INT bit

EN_DRV pin readback

error (monitoring high N/A

and low states)

EN_DRV_READBA EN_DRV_READBACK_ EN_DRV_READBA Interrupt is not

Interrupt only

Not valid

CK_INT = 1

MASK

CK_STAT

cleared if the

associated fault

condition is still

present

Write 1 to

NINT_READBACK_I

NT bit

All regulators

disabled and Output Automatic start-up to

GPIOx set to low

immediately and

interrupt⁽¹⁾

ORDERLY_SHUTDO

WN

(MODERATE_ERR_I

NT)

NINT pin readback

error (monitoring low

state)

NINT_READBACK_I NINT_READBACK_MA NINT_READBACK Interrupt is not

STARTUP_DEST[1:0]

state

NT = 1

SK

_STAT

cleared if the

associated fault

condition is still

present

Write 1 to

NRSTOUT_READB

ACK_INT bit

All regulators

disabled and Output Automatic start-up to

GPIOx set to low

immediately and

interrupt⁽¹⁾

ORDERLY_SHUTDO

WN

(MODERATE_ERR_I

NT)

NRSTOUT pin

readback error

(monitoring low state)

NRSTOUT_READB NRSTOUT_READBACK NRSTOUT_READB Interrupt is not

STARTUP_DEST[1:0]

state

ACK_INT = 1

_MASK

ACK_STAT

cleared if the

associated fault

condition is still

present

Write 1 to

NRSTOUT_SOC_R

EADBACK_INT bit

NRSTOUT_SOC pin

readback error

(monitoring low state)

NRSTOUT_SOC_R NRSTOUT_SOC_READ NRSTOUT_SOC_R Interrupt is not

N/A

Interrupt only

Not valid

EADBACK_INT = 1 BACK_MASK

EADBACK_STAT

cleared if the

associated fault

condition is still

present

Write 1 to

ESM_MCU_PIN_IN

T bit

Interrupt is not

cleared if the

associated fault

condition is still

present

Fault detected by

MCU ESM (level

mode: low level

detected, PWM mode:

PWM signal timing

violation

ESM_MCU_PIN_IN

T = 1

Interrupt only

ESM_MCU_PIN_MASK N/A

Fault detected by

MCU ESM (level

mode: low level longer

than DELAY1 time,

PWM mode: ESM

error counter >

Write 1 to

ESM_MCU_FAIL_IN

T bit

Interrupt is not

cleared if the

associated fault

condition is still

present

Interrupt and

EN_DRV = 0

(configurable)

ESM_MCU_FAIL_IN

T = 1

ESM_MCU_FAIL_MASK N/A

FAIL_THR longer than

DELAY1 time)

Write 1 to

ESM_MCU_RST_IN

T bit

Fault detected by

MCU ESM (level

mode: low level longer

than

DELAY1+DELAY2

time, PWM mode:

ESM error counter >

FAIL_THR longer than

DELAY1+DELAY2

time)

Interrupt and Warm Automatically returns

Reset (EN_DRV = 0 to the current

and NRSTOUT and operating state after

This bit can only be

read by the MCU

after the LP8764-Q1

has executed a

warm-reset and the

recovery counter

does not exceed the

recovery threshold

ESM_MCU_RST_IN

T = 1

ESM_MCU_RST

ESM_MCU_RST_MASK N/A

NRSTOUT_SOC

the completion of

warm reset

toggle)⁽¹⁾

Write 1 to

External clock is

expected, but it is not

available or the

frequency is not in the

valid range

EXT_CLK_INT bit

Interrupt is not

cleared if the

associated fault

condition is still

present

N/A

Interrupt only

Not valid

EXT_CLK_INT = 1⁽²⁾EXT_CLK_MASK

EXT_CLK_STAT

BIST completed

successfully

BIST_PASS_INT =

BIST_PASS_MASK

1

Write 1 to

BIST_PASS_INT bit

N/A

Clear interrupt and

WD_FAIL_CNT <

WD_FAIL_TH

Watchdog fail counter

above fail threshold

Interrupt and

EN_DRV = 0

Write 1 to

WD_FAIL_INT bit

WD_FAIL_INT = 1

N/A

Write 1 to

WD_RST_INT bit

This bit can only be

read by the MCU

after the LP8764-Q1

has executed a

warm-reset and the

recovery counter

does not exceed the

recovery threshold

Interrupt and Warm

Reset if

Automatically returns

to the current

operating state after

the completion of

warm reset

WD_RST_EN = 1

(EN_DRV = 0 and

NRSTOUT and

NRSTOUT_SOC

toggle)⁽¹⁾

Watchdog fail counter WD_RST (if

above reset threshold WD_RST_EN = 1)

WD_RST_INT = 1

N/A

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表8-13. Summary of Interrupt Signals (continued)

MASK FOR

INTERRUPT

CLEAR

EVENT

TRIGGER FOR FSM

RESULT ⁽¹⁾

RECOVERY

INTERRUPT BIT

LIVE STATUS BIT

INTERRUPT

Write 1 to

WD_LONGWIN_TI

MEOUT_INT bit

Interrupt and Warm Automatically returns

Reset (EN_DRV = 0 to the current

and NRSTOUT and operating state after

This bit can only be

read by the MCU

after the LP8764-Q1

has executed a

warm-reset and the

recovery counter

does not exceed the

recovery threshold

Watchdog long

window timeout

WD_LONGWIN_TI

MEOUT_INT = 1

WD_RST

N/A

NRSTOUT_SOC

the completion of

warm reset

toggle)⁽¹⁾

Transition to

TRIGGER_FORCE_ STANDBY or

Low state in ENABLE STANDBY/ LP_STANDBY

TRIGGER_FORCE_ depending on the

ENABLE pin rise

Not valid

N/A

LP_STANDBY

LP_STANDBY_SEL

bit setting⁽¹⁾

(1)

Write 1 to

ENABLE_INT bit

ENABLE pin rise

TRIGGER_SU_x

ENABLE_INT = 1

ENABLE_MASK

ENABLE_STAT

N/A

All regulators

disabled and Output Automatic start-up to

GPIOx set to low in STARTUP_DEST[1:0]

Write 1 to

ORD_SHUTDOWN_

INT

Fault causing orderly

shutdown

ORDERLY_SHUTDO

WN

ORD_SHUTDOWN_ ORD_SHUTDOWN_MA

INT SK

a sequence and

state

interrupt⁽¹⁾

All regulators

disabled (depending

on NVM

configuration with or Automatic start-up to

Write 1 to

IMM_SHUTDOWN_I

NT

Fault causing

immediate shutdown

IMMEDIATE_SHUTD

OWN

IMM_SHUTDOWN_I IMM_SHUTDOWN_MA

NT SK

without pull-down

resistors) and

STARTUP_DEST[1:0]

state

N/A

Output GPIOx set to

low immediately

and interrupt⁽¹⁾

Depends on PFSM

configuration, see

PFSM transition

diagram

Transition according

to FSM trigger and

interrupt

Write 1 to

MCU_PWR_ERR_I

NT

Power supply error for MCU_POWER_ERR

MCU OR

MCU_PWR_ERR_I MCU_PWR_ERR_MAS

NT

N/A

K

Depends on PFSM

configuration, see

PFSM transition

diagram

Transition according

to FSM trigger and

interrupt

Write 1 to

SOC_PWR_ERR_I

NT

Power supply error for SOC_POWER_ERR

SOC_PWR_ERR_I SOC_PWR_ERR_MAS

SOC

OR

NT

K

Write 1 to

VCCA_OVP _INT bit

This bit can only be

read by the MCU if

VCCA < VCCA_OVP

level. As long as

VCCA ⩾VCCA_OVP

level, device stays in

SAFE RECOVEY

state, and hence

this interrupt cannot

be not cleared.

All regulators

Automatic start-up to

STARTUP_DEST[1:0]

state after VCCA

voltage is below

VCCA_OVP

disabled with pull-

down resistors and

Output GPIOx set to

low immediately

and interrupt⁽¹⁾

IMMEDIATE_SHUTD

OWN

(SEVERE_ERR_INT)

VCCA over-voltage

VCCA_OVP_INT =

1

N/A

VCCA_OVP_STAT

(VCCA_OVP

)

According to

GPIOx_FSM_MASK Transition according

GPIOx_RISE_MASK

GPIOx_FALL_MASK

Write 1 to

GPIOx_INT bit

GPIO interrupt

and

to FSM trigger and Not valid

GPIOx_INT = 1

GPIOx_IN

GPIOx_FSM_MASK_ interrupt

POL bits

Transition to

GPIOx_RISE_MASK

GPIOx_FALL_MASK

Write 1 to

GPIOx_INT bit

WKUP1 signals

WKUP2 signals

WKUP1

WKUP2

ACTIVE state and

Not valid

N/A

GPIOx_IN

interrupt⁽¹⁾

Transition to MCU

ONLY state and

interrupt⁽¹⁾

GPIOx_RISE_MASK

GPIOx_FALL_MASK

Write 1 to

GPIOx_INT bit

According to

NSLEEP1 and

NSLEEP2

State transition

based on NSLEEP1 Not valid

and NSLEEP2

NSLEEP1 signal,

NSLEEP1B bit

NSLEEP1_MASK

NSLEEP2_MASK

N/A

According to

NSLEEP1 and

NSLEEP2

State transition

based on NSLEEP1 Not valid

and NSLEEP2

NSLEEP2 signal,

NSLEEP2B bit

All regulators

disabled with pull-

LDOVINT over- or

undervoltage

Reset condition for

all logic circuits

Valid LDOVINT

voltage

down resistors and

Output GPIOx set to

low immediately⁽¹⁾

N/A

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表8-13. Summary of Interrupt Signals (continued)

MASK FOR

INTERRUPT

CLEAR

EVENT

TRIGGER FOR FSM

RESULT ⁽¹⁾

RECOVERY

INTERRUPT BIT

LIVE STATUS BIT

INTERRUPT

All regulators

disabled with pull-

Main clock outside

valid frequency

Reset condition for

all logic circuits

down resistors and VCCA power cycle

Output GPIOx set to

N/A

low immediately⁽¹⁾

All regulators

Recovery counter limit ORDERLY_SHUTDO disabled and Output

VCCA power cycle

N/A

exceeded⁽³⁾

WN

GPIOx set to low in

a sequence⁽¹⁾

All regulators

disabled with pull-

VCCA supply falling

below VCCA_UVLO

Reset condition for

all logic circuits

down resistors and VCCA voltage rising

Output GPIOx set to

N/A

low immediately⁽¹⁾

Start-up to

STARTUP_DEST[1:

First supply detection,

VCCA supply rising

above VCCA_UVLO

Write 1 to FSD_INT

bit

TRIGGER_SU_x

Not valid

FSD_INT = 1

FSD_MASK

0] state and

interrupt⁽¹⁾

(1) The results shown in this column are selected to meet functional safety assumptions and device specifications. The actual results can

be configured differently in NVM memory. TI recommends reviewing of the system and device functional safety goal and

documentation before deviating from these recommendations.

(2) Interrupt is generated during clock detector operation and in case clock is not available when clock detector is enabled.

(3) This event does not occur if RECOV_CNT_THR = 0, even though RECOV_CNT continues to accumulate and increase, and eventually

saturates when it reaches the maximum count of 15.

(4) I2C1, I2C2, or SPI address error only occur in safety applications if the interface CRC feature is enabled, when both

I2C1_SPI_CRC_EN and I2C2_CRC_EN are set to '1'.

8.11 Control Interfaces

The device has two, exclusive selectable (from factory settings) interfaces. Please refer to the User's Guide of

the orderable part number which option has been selected. The first selection is up to two high-speed I²C

interfaces. The second selection is one SPI interface. The SPI and I2C1 interfaces are used to fully control and

configure the device, and have access to all of the configuration registers and Watchdog registers. During

normal operating mode, when the I²C configuration is selected, and the GPIO2 and GPIO3 pins are configured

as the SCL_I2C2 and SDA_I2C2 pins, the I2C2 interface becomes the dedicated interface for the Q&A

Watchdog communication channel, while I2C1 interface no longer has access to the Watchdog registers. .

8.11.1 CRC Calculation for I²C and SPI Interface Protocols

For safety applications, the LP8764-Q1 supports read and write protocols with embedded CRC data fields. The

LP8764-Q1 uses a standard CRC-8 polynomial to calculate the checksum value: X⁸+ X²+ X + 1. The CRC

algorithm details are as follows:

• Initial value for the remainder is all 1s

• Big-endian bit stream order

• Result inversion is enabled

For I²C Interface, the LP8764-Q1 uses the above mentioned CRC-8 polynomial to calculate the checksum value

on every bit except the ACK and NACK bits it receives from the MCU during a write protocol. The LP8764-Q1

compares this calculated checksum with the R_CRC checksum value that it receives from the MCU. The

LP8764-Q1 also uses the above mentioned CRC-8 polynomial to calculate the T_CRC checksum value during a

read protocol. This T_CRC checksum value is based on every bit that the LP8764-Q1 receives, except the ACK

and NACK bits and except the repeated I2C_ID bits, and the data that the LP8764-Q1 transmits to the MCU

during a read protocol. The MCU must use this same CRC-8 polynomial to calculate the checksum value based

on the bits that the MCU receives from the LP8764-Q1. The MCU must compare this calculated checksum with

the T_CRC checksum value that it receives from the LP8764-Q1.

For the SPI interface, the LP8764-Q1 uses the above mentioned CRC-8 polynomial to calculate the checksum

value on every bit it receives from the MCU during a write protocol. The LP8764-Q1 compares this calculated

checksum with the R_CRC checksum value, that it receives from the MCU. During a read protocol, the device

also uses the above mentioned CRC-8 polynomial to calculate the T_CRC checksum value based on the first 16

bits sent by the MCU, and the next 8 bits the LP8764-Q1 transmits to the MCU. The MCU must use this same

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CRC-8 polynomial to calculate the checksum value based on the bits which the MCU sends to and receives from

the LP8764-Q1, and compare it with the T_CRC checksum value that it receives from the LP8764-Q1.

图8-22 and 图8-23 are examples for the 8-bit R_CRC and the T_CRC calculation from 16-bit databus.

24

24-bit bus ordering value for I2C:

RW ADDR[7:0]

0

I2C_ID[7:1]

ADDR[7:0]

WDATA[7..0]

24

24-bit bus ordering value for SPI:

PAGE[2:0]

0

RESERVED[3:0]

Flip-Flop the Preload Value

(Seed Value)

1

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Flip Flop

R_CRC[7]

R_CRC[6]

R_CRC[5]

R_CRC[4]

R_CRC[3]

R_CRC[2]

R_CRC[1]

R_CRC[0]

图8-22. Calculation of 8-Bit CRC on Received Data (R_CRC)

32

24

32-bit bus ordering value for I2C:

0

I2C_ID[7:1]

RW

ADDR[7:0]

I2C_ID[7:1]

RW

WDATA[7..0]

24-bit bus ordering value for SPI:

ADDR[7:0]

PAGE[2:0]

0

RESERVED[3:0]

Flip-Flop the Preload Value

(Seed Value)

1

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Flip Flop

T_CRC[7]

T_CRC[6]

T_CRC[5]

T_CRC[4]

T_CRC[3]

T_CRC[2]

T_CRC[1]

T_CRC[0]

图8-23. Calculation of 8-Bit CRC on Transmitted Data (T_CRC)

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8.11.2 I²C-Compatible Interface

The default I²C1 7-bit device address of the LP8764-Q1 device is set to a binary value that is described in the

User's Guide of the orderable part number of the LP8764-Q1 PMIC, while the two least-significant bits can be

changed for alternative page selection listed under 节 8.13.1. The default 7-bit device address for the I²C2

interface, for accessing the watchdog configuration registers and for operating the watchdog in Q&A mode, is

described in the User's Guide of the orderable part number of the LP8764-Q1 PMIC.

The I²C-compatible synchronous serial interface provides access to the configurable functions and registers on

the device. This protocol uses a two-wire interface for bidirectional communications between the devices

connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL).

Every device on the bus is assigned a unique address and acts as either a master or a slave depending on

whether it generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor

placed somewhere on the line and remain HIGH even when the bus is idle. The device supports standard mode

(100 kHz), fast mode (400 kHz), and fast mode plus (1 MHz) when VIO is 3.3 V or 1.8 V, and high-speed mode

(3.4 MHz) only when VIO is 1.8 V.

8.11.2.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the

state of the data line can only be changed when clock signal is LOW.

SCL

SDA

data

change

allowed

data

change

allowed

data

change

allowed

data

valid

data

valid

图8-24. Data Validity Diagram

8.11.2.2 Start and Stop Conditions

The device is controlled through an I²C-compatible interface. START and STOP conditions classify the beginning

and end of the I²C session. A START condition is defined as the SDA signal going from HIGH to LOW while the

SCL signal is HIGH. A STOP condition is defined as the SDA signal going from LOW to HIGH while the SCL

signal is HIGH. The I²C master device always generates the START and STOP conditions.

SDA

SCL

S

P

START

STOP

Condition

图8-25. Start and Stop Sequences

The I²C bus is considered busy after a START condition and free after a STOP condition. The I²C master can

generate repeated START conditions during data transmission. A START and a repeated START condition are

equivalent function-wise. 图 8-26 shows the SDA and SCL signal timing for the I²C-compatible bus. For timing

values, see the Specification section.

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t_BUF

SDA

t_HD;STA

t_rCL

t_fDA

t_rDA

t_SP

t_LOW

t_fCL

SCL

t_HD;STA

t_SU;STA

t_SU;STO

t_HIGH

t_HD;DAT

S

t_SU;DAT

S

RS

P

START

REPEATED

START

STOP

START

图8-26. I²C-Compatible Timing

8.11.2.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The device pulls

down the SDA line during the 9th clock pulse, signifying an acknowledge. The device generates an acknowledge

after each byte has been received.

There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must

indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out

of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),

but the SDA line is not pulled down.

After the START condition, the bus master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE and a 1

indicates a READ. The second byte selects the register to which the data is written. The third byte contains data

to write to the selected register. 图8-27 shows an example bit format of device address 110000-Bin = 60Hex.

MSB

LSB

1

Bit 7

1

Bit 6

0

Bit 5

0

Bit 4

0

Bit 3

0

Bit 2

0

Bit 1

R/W

Bit 0

I²C Address (chip address)

图8-27. Example Device Address

For safety applications, the device supports read and write protocols with embedded CRC data fields. In a write

cycle, the I²C master device (i.e. the MCU) must provide the 8-bit CRC value after sending the write data bits

and receiving the ACK from the slave. The CRC value must be calculated from every bit included in the write

protocol except the ACK bits from the slave. See CRC Calculation for I2C and SPI Interface Protocols. In a read

cycle, the I²C slave must provide the 8-bit CRC value after sending the read data bits and the ACK bit, and

expect to receive the NACK from the master at the end of the protocol. The CRC value must be calculated from

every bit included in the read protocol except the ACK and NACK bits. See CRC Calculation for I2C and SPI

Interface Protocols.

备注

If I2C CRC is enabled in the device and an I2C write without R_CRC bits is done, the device does not

process the write request. The device does not set any interrupt bit and does not pull the nINT pin low.

The embedded CRC field can be enabled or disabled from the protocol by setting the I2C1_SPI_CRC_EN (for

I2C1) or I2C2_CRC_EN (for I2C2) register bit to '1' - enabled, '0' - disabled. The default of this bit is configurable

through the NVM.

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In case the calculated CRC-value does not match the received CRC-check-sum, an I²C-CRC-error is detected,

the COMM_CRC_ERR_INT (for I2C1) or I2C2_CRC_ERR_INT (for I2C2) bit is set, unless it is masked by the

COMM_CRC_ERR_MASK or I2C2_CRC_ERR_MASK bit. The MCU must clear this bit by writing a ‘1’ to the

COMM_CRC_ERR_INT (for I2C1) or I2C2_CRC_ERR_INT (for I2C2) bit.

When the CRC field is enabled, in the case when MCU attempts to write to a read-only register or a register-

address that does not exist, the device sets the COMM_ADR_ERR_INT (for I2C1) or I2C2_ADR_ERR_INT (for

I2C2) bit, unless the COMM_ADR_ERR_MASK or I2C2_ADR_ERR_MASK bit is set. The MCU must clear this

bit by writing a ‘1’to the COMM_ADR_ERR_INT (for I2C1) or I2C2_ADR_ERR_INT (for I2C2) bit.

START

ACK

ACK STOP

I2C_ID[7:1]

0

ADDR[7:0]

WDATA[7:0]

STOP

SCL

SDA

0x60

0x36

0x16

图8-28. I²C Write Cycle without CRC

START

ACK

ACK STOP

STOP

R_CRC[7:0]

I2C_ID[7:1]

0

ADDR[7:0]

WDATA[7:0]

SCL

SDA

0x43

0x60

0x36

0x16

The I²C master device (i.e. the MCU) provides R_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, and the WDATA bits (24

bits). See CRC Calculation for I2C and SPI Interface Protocols.

图8-29. I²C Write Cycle with CRC

REPEATED

STOP

START

ACK

NCK

I2C_ID[7:1]

0

ADDR[7:0]

I2C_ID[7:1]

1

RDATA[7:0]

STOP

SCL

SDA

0x60

0x36

0x60

0x16

When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.

图8-30. I²C Read Cycle without CRC

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REPEATED

START

STOP

NCK

START

ACK

I2C_ID[7:1]

0

ADDR[7:0]

I2C_ID[7:1]

1

RDATA[7:0]

T_CRC[7:0]

STOP

SCL

SDA

0x60

0x36

0x60

0x16

0x7D

The I²C slave device (i.e. the LP8764-Q1) provides T_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, I2C_ID, R/W, and

the RDATA bits (32 bits). See CRC Calculation for I2C and SPI Interface Protocols.

图8-31. I²C READ Cycle with CRC

8.11.2.4 Auto-Increment Feature

The auto-increment feature allows writing several consecutive registers within one transmission. Every time an

8-bit word is sent to the device, the internal address index counter is incremented by one and the next register is

written. 表8-14 lists the writing sequence to two consecutive registers. Note that auto increment feature does not

support CRC protocol.

表8-14. Auto-Increment Example

DEVICE

ADDRESS =

0x60

MASTER

ACTION

REGISTER

ADDRESS

START

WRITE

DATA

STOP

PMIC device

ACK

8.11.3 Serial Peripheral Interface (SPI)

The device supports SPI serial-bus interface and it operates as a peripheral device. The MCU in the system acts

as the controller device. A single read and write transmission consists of 24-bit write and read cycles (32-bit if

CRC is enabled) in the following order:

• Bits 1-8: ADDR[7:0], Register address

• Bits 9-11: PAGE[2:0], Page address for register

• Bit 12: Read/Write definition, 0 = WRITE, 1 = READ.

• Bits 13-16: RESERVED[4:0], Reserved, use all zeros.

• For Write: Bits 17-24: WDATA[7:0], write data

• For Write with CRC enabled: Bits 25-32: R_CRC[7:0], CRC error code calculated from bits 1-24 sent by the

controller device (i.e. the MCU). See 节8.11.1.

• For Read: Bits 17-24: RDATA[7:0], read data

• For Read with CRC enabled: Bits 25-32: T_CRC[7:0], CRC error code calculated from bits 1-16 sent by the

controller device (i.e. the MCU), and bits 17-24, sent by the peripheral device (i.e. the LP8764-Q1). See 节

8.11.1.

In parallel with ADDR[7:0], PAGE[2:0], Read/Write definition and RESERVED[3:0] bits the device sends 16-bit

interrupt status using SDO_SPI pin in the following order:

• Bit 1: always 0

• Bits 2-8: status of several interrupts and EN_DRV pin

• Bit 9: always 1

• Bits 10-16: status of several interrupts and EN_DRV pin, with opposite polarity

The status signals are in INT_SPI_STATUS register:

• Bit 8: always 0

• Bit 7: COMM_ADR_ERR_SWINT

• Bit 6: COMM_CRC_ERR_SWINT

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• Bit 5: COMM_FRM_ERR_SWINT

• Bit 4: ESM_MCU_PIN_SWINT

• Bit 3: TWARN_SWINT

• Bit 2: WD_SWINT

• Bit 1: EN_DRV_STAT

Please refer to the bit descriptions of the INT_SPI_STATUS register in 节 8.16.1 for the needed conditions in

order to have an error-indication through these status bits.

EN_DRV_STAT bit is showing the live state of the EN_DRV pin, whereas all other status bits are latched in the

same way as interrupts indicated with nINT pin. The latched status bits in INT_SPI_STATUS register are cleared

by writing 1 to the latched bit. Bits 10-16 are sent for redundancy for bits 2-8 with opposite polarity. Bits 10-16

are always correlating with bits 2-8 and do not change during communication even when the status signal

changes.

The embedded CRC filed can be enabled or disabled from the protocol by setting the I2C1_SPI_CRC_EN

register bit to '1' - enabled, '0' - disabled. The default of this bit is configurable through the NVM.

The SDO_SPI output is in a high-impedance state when the CS_SPI pin is high. When the CS_SPI pin is low,

the SDO_SPI output is always driven low except when the RDATA or SCRC bits are sent. When the RDATA or

SCRC bits are sent, the SDO_SPI output is driven accordingly.

The address, page, data, and CRC are transmitted MSB first. The chip-select signal (CS_SPI) must be low

during the cycle transmission. The CS_SPI signal resets the interface when it is high, and must be taken high

between successive cycles. Data is clocked in on the rising edge of the SCK_SPI clock signal and it is clocked

out on the falling edge of SCK_SPI clock signal.

The SPI Timing diagram shows the timing information for these signals.

CS_SPI

SCLK_SPI

PAGE

[2:0]

Reserved[3:0]

0

WDATA[7:0]

SDI_SPI

ADDR[7:0]

SDO_SPI Hi-Z

Hi-Z

0

SPI_STATUS[6:0]

1 SPI_STATUS[6:0]

图8-32. SPI Write Cycle

CS_SPI

SCLK_SPI

SDI_SPI

PAGE

[2:0]

Reserved[3:0]

0

WDATA[7:0]

R_CRC[7:0]

ADDR[7:0]

SDO_SPI Hi-Z

Hi-Z

0

SPI_STATUS[6:0]

1

SPI_STATUS[6:0]

图8-33. SPI Write Cycle with CRC

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CS_SPI

SCLK_SPI

SDI_SPI

PAGE

[2:0]

Reserved[3:0]

1

ADDR[7:0]

Hi-Z

0

SPI_STATUS[6:0]

1

SPI_STATUS[6:0]

RDATA[7:0]

Hi-Z

SDO_SPI

图8-34. SPI Read Cycle

CS_SPI

SCLK_SPI

SDI_SPI

PAGE

[2:0]

Reserved[3:0]

ADDR[7:0]

1

SDO_SPI

Hi-Z

0

SPI_STATUS[6:0]

1

SPI_STATUS[6:0]

RDATA[7:0]

T_CRC[7:0]

Hi-Z

图8-35. SPI Read Cycle with CRC

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8.12 Multi-PMIC Synchronization

A multi-PMIC synchronization scheme is implemented in the LP8764-Q1 device to synchronize the power state

changes with other PMIC devices. This feature consolidates and simplifies the IO control signals required

between the application processor or the microcontroller and multiple PMICs in the system. The control interface

consists of an SPMI protocol that communicates the next power state information from the primary PMIC to up to

5 secondary PMICs, and receives feedback signal from the secondary PMICs to indicate any error condition or

power state information. 图 8-36 is the block diagram of the power state synchronization scheme. The primary

PMIC in this block diagram is responsible for broadcasting the synchronous system power state data, and

processing the error feedback signals from the secondary PMICs. The primary PMIC is the controller device on

the SPMI bus, and the secondary PMICs are the target devices on the SPMI bus.

Synchronous-System Power-State Data

Error Feedback

Primary PMIC

Secondary PMIC

Sequencing and Power

State Configurations in

Nonvolatile Memory

Sequencing and Power

State Configurations in

Nonvolatile Memory

Sequencing and Power

State Configurations in

Nonvolatile Memory

Power-State

Sequencer

Controller

Power-State

Sequencer

Controller

Power-State

Sequencer Controller

Power supply

configuration

STATE

1

Exit Condition 1

Signal list

Internal condition list

Error Conditions

Timeout on PGOOD

Thermal

Power supply

configuration

Power supply

configuration

Current

Voltage

STATE

1

Exit Condition

Signal list

Internal condition list

1

STATE

1

Exit Condition 1

Signal list

Internal condition list

STATE_1

Error Conditions

Timeout on PGOOD

Thermal

Error Conditions

Timeout on PGOOD

Thermal

...

STATE

2

Exit Condition

Signal list

Internal condition list

1

2

Current

Voltage

Current

Voltage

STATE_1

Effective

...

Effective

power

state

Effective

power

state

OFF

STATE

2

Exit Condition

Signal list

Internal condition list

1

2

STATE

2

Exit Condition

Signal list

Internal condition list

1

2

STATE

2

Exit Condition

Signal list

Internal condition list

STATE_2

OFF

STATE

2

Exit Condition

Signal list

Internal condition list

STATE

2

Exit Condition

Signal list

Internal condition list

STATE_2

power

state

ERROR

(SAFE STATE)

ERROR

(SAFE STATE)

ERROR

(SAFE STATE)

STATE_3

Controller for

Output Power

Supply Rails

STATE_3

Controller for

Output Power

Supply Rails

Controller for

Output Power

Supply Rails

STATE_N

Power

supply

error

Power

supply

error

Power

supply

error

Signal Arbitration

Logic

ENABLE or WAKE

signals from

external hardware

Power-State Control

Signals such as:

ACTIVE, SLEEP, RESET,

ERROR, TRACKING

Scalable Microprocessor and System on Chip

图8-36. Multi-PMIC Power State Synchronization Block Diagram

In this scheme, each primary and secondary PMIC runs on its own system clock, and maintains its own register

map. Each PMIC monitors its own activities and pulls down the open-drain output of nINT or PGOOD pin when

errors are detected. The microprocessor must read the status bits from each PMIC device through the I2C or

SPI interface to find out the source of the error that is reported.

图 8-37 illustrates the pin connections between the primary, the secondary, and the application processor or the

System-on-Chip.

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VIO

Secondary PMIC

I2C_SCL

I2C_SDA

SDATA

SCLK

Interrupt

Handler

Power

nINT

Sequencer

Power Good

Monitor

PGOOD

Secondary PMIC

I2C_SCL

I2C_SDA

SDATA

SCLK

Power

Sequencer

nINT

µProcessor

&

PGOOD

System

on

Primary PMIC

Chip

I2C1_SCL

I2C1_SDA

ENABLE

nINT

nERR_MCU

nSLEEPx

Power

Sequencer

GPIO

nRSTOUTx

WAKEn

PGOOD

SCLK

SDATA

I2C2_SCL

I2C2_SDA

Q&A

WDOG

图8-37. multi-PMIC Pin Connections

The power sequencer of the multiple PMICs are synchronized at the beginning of each power up and power

down sequence; a variation in the sequence timing, however, is still possible due to the ±5% clock accuracy of

the independent system clocks on the primary and secondary PMICs. The worst-case sequence timing variation

from different PMIC rails is up to ±10% of the target delay time. 图 8-38 illustrates the creation of this timing

variation between PMICs.

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Primary PMIC

System clock

(+/-5% accuracy)

...

Primary PMIC

Rail X

Sequence delay between rails in Primary PMIC

Primary PMIC

Rail Y

Secondary PMIC

System clock

(+/-5% accuracy)

...

Sequence delay between rails in secondary PMIC

Secondary PMIC

Rail Z

Sequencing timing variation between PMIC rails

图8-38. Multi-PMIC Rail Sequencing Timing Variation

8.12.1 SPMI Interface System Setup

An SPMI interface in the LP8764-Q1 device is utilized to communicate the power state transition across multiple

PMICs in the system. The SPMI interface contains a controller block and a target block. There is only one PMIC,

which is the primary PMIC, that acts as SPMI controller in any given system. As the SPMI controller it initiates

SPMI interface BIST and executes periodic checking of the SPMI bus health.

The primary PMIC has a controller-ID (CID)= 1. The target block of SPMI interface in the primary PMIC device is

activated as well, in order to receive SPMI communication messages from the secondary PMICs. The primary

PMIC has a target-ID (TID) = 0101.

Each secondary PMIC on the SPMI network only has the target block of its SPMI interface enabled. There

cannot be more than five secondary PMICs in the system. The target-IDs (TIDs) for the five secondary PMICs

are:

• 1st target device: 0011

• 2nd target device: 1100

• 3rd target device: 1001

• 4th target device: 0110

• 5th target device: 1010

All devices in the SPMI network listen to the group target-ID (GTID): 1111. This address is used to communicate

all power state transition information in broadcast mode to all connected devices on the SPMI bus.

8.12.2 Transmission Protocol and CRC

The communication between the devices on the network utilizes Extended Register Write command to GTID

address 1111 with byte length of 2. Sequence format complies with MIPI SPMI 2.0 specification. First data frame

carries the data payload of 5 bits and 3 filler bits.

Communication over the SPMI interface may contain information regarding the power state transition or the

unique TID of one or more target devices. In the case of power state information, the data payload contains 5

bits of Trigger ID information and 3 trigger state bits. In the case of TID information, all 8 bits contain the TID of

the target device.

Second data frame carries 8 bits of CRC information. CRC polynomial used is X⁸+ X²+ X + 1. CRC is

calculated over the SPMI command frame, the address frame, and the first data frame (which contains the

payload and excludes the parity bits in these three frames).

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图8-39 shows the data format of the SPMI Extended Register Write Command.

SCLK

SDATA

SA3

SA2

SA1

SA0

0

BC3

BC2

BC1

BC0

P

Extended register-write command frame

SSC

SCLK

SDATA

P

A7

A6

A5

A4

A3

A2

A1

A0

P

Register address (data frame) for first register

SCLK

SDATA

P

D7

D6

D5

D4

D3

D2

D1

D0

P

First data frame

... Intermediate Data Frames ...

SCLK

SDATA

P

D7

D6

D5

D4

D3

D2

D1

D0

P

0

Last data frame

Bus park ACK or Bus park

NAK

Signal driven by BOM or request-capable peripheral device

(SCLK always driven by BOM only)

Signal not driven; pulldown only.

Response by peripheral devices

For reference only

图8-39. SPMI Extended Register Write Command

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8.12.2.1 Operation with Transmission Errors

If the receiving device detects a parity or CRC error in the incoming sequence it responds with negative ACK/

NACK per SPMI standard.

If the transmitting device sees NACK response, it tries to resend the message as many times as indicated by

SPMI_RETRY_LIMIT register bits. After that it considers the SPMI bus inoperable, sets SPMI_ERR_INT

interrupt and goes to the safe recovery state and executes an orderly shutdown. Bus arbitration requests do not

count as failed attempts if a target device loses bus arbitration. SPMI_RETRY_LIMIT counter is reset after each

successful transmission by the device.

If a target device has determined that SPMI does not work reliably it does not respond to any SPMI commands

anymore until power-on-reset event has occurred. This "no-response" behavior is to prevent continued operation

in a situation where SPMI is unreliable. If a target device does no longer respond to any SPMI command, the

controller device on the SPMI bus detects a missing target device on the network during the periodic testing of

SPMI bus. The target device then internally handles the SPMI error condition per error handling rules set for the

device (in general executing an orderly shutdown). SPMI block signals to the device that SPMI bus error has

occurred after the retry limit has been exceeded.

8.12.2.2 Transmitted Information

The SPMI bus is used to carry two types of information:

• PFSM Trigger ID between the SPMI controller and target devices

• TID from SPMI target devices to SPMI controller device

The SPMI controller device reads the TID of the target devices periodically to check the health of the interface.

Exchanging Trigger IDs for the power state transition is sufficient to keep the PFSMs of all the devices on the

SPMI network in synchronization. Device interrupts explain reason for the power state transitions.

8.12.3 SPMI Target Device Communication to SPMI Controller Device

An SPMI target device communicates to the SPMI controller device and any other SPMI target devices, only if

there is an internal error that is not SPMI related. The target device initiates the error communication using

Arbitration Request with A-bit as defined in the SPMI 2.0 specification. SPMI 2.0 protocol manages the situation

with multiple target devices requesting error communication at the same time, by using the target arbitration

process as described in SPMI 2.0 specification. Once the SPMI target device wins the arbitration using the A-bit

protocol, it performs an Extended Register Write command to Group Target ID (GTID) address 1111 by using the

protocol described in 节8.12.2 for communicating PFSM trigger ID.

8.12.3.1 Incomplete Communication from SPMI Target Device to SPMI Controller Device

In case the SPMI controller device detects an arbitration request on the SPMI interface, but the received

sequence has an error or is incomplete, the SPMI controller device immediately performs the SPMI Built-In Self-

Test (SPMI-BIST). If this SPMI-BIST fails, the SPMI controller device executes the error handling for the SPMI

error. If the SPMI-BIST passes successfully, the SPMI controller device resumes normal operation.

8.12.4 SPMI-BIST Overview

The SPMI-BIST is performed during BIST state and regularly during runtime operation. 图 8-40 below illustrates

how the SPMI-BIST operates during device power-up.

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PMIC internal sequencing

PWRON/ENABLE causes transition

to active mode

ñ

read NVM

initialization

Etc.

Power sequence

FTTI >> SPMI BIST interval

VIN

PWRON/ENABLE

PMIC State

BOOT BIST

STANDBY

ACTIVE/MISSION

SPMI

SPMI BIST patterns

SPMI BIST pattern as part of BOOT

BIST sequence

SPMI messaging to secondary PMIC

to go to ACTIVE state

图8-40. SPMI-BIST Operation

After the input power is detected and verified to be at the correct level, the LP8764-Q1 initializes itself by reading

the NVM and performs all actions that are needed to prepare for operation . After this initialization, the LP8764-

Q1 enters the BOOT BIST state, in which the internal logic performs a series of tests to verify that the LP8764-

Q1 device is OK. As part of this test, the SPMI- BIST is performed. After it is completed successfully, the

LP8764-Q1 device goes to the standby state and waits for further signals from the system to initiate the power-

up sequence of the processor.

A valid on request initiates the processor power-up sequence. The controller device communicates this event

through the SPMI bus to all of the target devices. After that, the power-up sequence is executed and LP8764-Q1

enters the configured mission state.

8.12.4.1 SPMI Bus during Boot BIST and RUNTIME BIST

During Boot BIST and RUNTIME BIST, both the Logic BIST (LBIST) on the SPMI logic and the SPMI-BIST are

performed to check correct operation of the SPMI bus. The LBIST is performed first before the SPMI-BIST

during BOOT BIST and RUNTIME BIST. The SPMI-BIST is implemented by reading TID from each target device

on the SPMI bus into the controller device, and ensuring they are unique and match the expected amount of

target devices. This process of checking the TID of each target device ensures that:

• All SPMI target devices are present in the system as expected

• The SPMI logic blocks are working on the SPMI controller device and all of the SPMI target devices

• The pins and wires on the ICs and PCB are in working order

The SPMI-BIST is initiated by the SPMI controller block in the primary PMIC by writing a request to all SPMI

target device(s) (using GTID) to send their TIDs to the SPMI controller block of the primary PMIC. Upon

receiving this command from the SPMI controller device, the SPMI target devices request SPMI bus arbitration

using the SR-bit protocol. Upon winning the bus arbitration the SPMI target devices transmit their TID into the

SPMI target block of the primary PMIC.

The SPMI controller block of the primary PMIC contains a list of all SPMI target device(s) on the SPMI bus and

their TIDs in the register set. The SPMI controller block of the primary PMIC reads the TID from each SPMI

target device and compares the result with the stored TID for the corresponding SPMI target device. The SPMI

controller device has to ensure that every non-zero TID on its list is returned, in order to support use cases in

which there are two or more identical SPMI target devices, with same TID, in the system. In these cases, it is

mandatory that the expected number of the same TIDs is returned. If no identical PMICs are to be used, then a

return of the same TID multiple times is an error due to incorrect assembly of identical PMICs onto the PCB. An

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all-zero TID stored in the list of the primary PMIC indicates that there are no SPMI target device(s) present on

the SPMI Bus.

8.12.4.2 Periodic Checking of the SPMI

The SPMI controller block in the primary PMIC executes the SPMI-BIST periodically while device is operating.

The time-period after the SPMI-BIST is repeated according factory-configured settings during the device boot

time, and after the device reaches mission states. The factory-configured settings of this SPMI-BIST time period

must be the same for all PMICs on the same SPMI network. The SPMI target devices on the SPMI bus expect a

request for sending its TID from the SPMI controller device within 1.5x the factory-configured period . This factor

1.5x provides enough margin for clock uncertainty between the SPMI controller device and the SPMI target

device.

During mission state operation, the SPMI controller device expects the SPMI target devices to respond to the

TID request within the factory-configured polling time-out period . In other words, from the polling start command

each SPMI target device must respond within this factory-configured time interval.

During boot time or when the device enters Safe Recovery state, to prevent the SPMI controller device from

polling the SPMI target devices too often while one or more of these recovering from a system error such as a

thermal shutdown event, the device sets a longer timeout period that allows the SPMI target devices to respond

to the SPMI controller device before he SPMI controller device reports an error.

If one or more devices on the SPMI bus cause a violating of the polling time-out period either during start-up or

during normal operation, the SPMI controller block in the affected PMIC(s) sets a SPMI error trigger signal to the

PFSM of the affected PMIC(s), causing a complete shutdown of the affected PMIC(s). As a result, the affected

PMIC(s) no longer respond on the SPMI bus, which in turn is detected by the SPMI controller block off the non-

affected PMICs on the SPMI bus. The SPMI controller block in these PMICs sets an SPMI error to the PFSM in

these PMICs, causing a complete shutdown of these PMICs. Therefore, all PMICs are finally shutdown if one or

more devices on the SPMI bus cause a violating of the polling time-out period .

8.12.4.3 SPMI Message Priorities

The SPMI Bus uses the protocol priority levels listed in 表8-15 for each type of communication message.

表8-15. SPMI Message Types and Priorities

SPMI protocol priority level

Name of priority level in SPMI standard

Message types

State transition messages from

target device(s) to controller

device

Highest

A-bit arbitration

State transition messages from

controller device to target

device(s)

priority arbitration

target device TID to controller

device

SR-bit arbitration

Controller device request of TIDs

from target device(s)

Lowest

secondary arbitration

8.13 NVM Configurable Registers

8.13.1 Register Page Partitioning

The registers in the LP8764-Q1 device are organized into five internal pages. Each page represents a different

type of register. The below list shows the pages with their register types:

• Page 0: User Registers

• Page 1: NVM Control, Configuration, and Test Registers

• Page 2: Trim Registers

• Page 3: SRAM for PFSM Registers

• Page 4: Watchdog Registers

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备注

When I²C Interfaces are used, each of the above listed register pages has its own 6-bit I²C device

address. In order to address Page 0 to 3, the two LSBs if the pre-configured I2C1_ID are replaced

with 00 for Page 0, 01 for Page 1, 10 for Page 2 and 11 for Page 3. As an example, if I2C1_ID=0x26

(0100110b) , Page 0 to 3 have following addresses:

• Page 0: 0100100

• Page 1: 0100101

• Page 2: 0100110

• Page 3: 0100111

For Page 4 the I²C device address is according register bits I2C2_ID. Therefore, in case both I²C1

and I²C2 Interfaces are used, each LP8764-Q1 device occupies four I²C device addresses (for Page

0, Page 1, Page 2 and Page 3) on the I²C1 bus and one I²C device address (for Page 4) on the I²C2

bus. And in case only I²C1 Interfaces is used, each LP8764-Q1 device occupies five I²C device

addresses (for Page 0, Page 1, Page 2, Page 3 and Page 4) on the I²C1 bus. In case multiple devices

are used on a common I²C bus, care must be taken to avoid overlapping I²C device addresses.

备注

When SPI Interface is used, the above listed register pages are addresses with the PAGE[2:0] bits:

0x0 addresses Page 0, 0x1 addresses Page 1, 0x2 addresses Page 2, 0x3 addresses Page 3

8.13.2 CRC Protection for Configuration, Control, and Test Registers

The LP8764-Q1 device includes a static CRC-16 engine to protect all the static registers of the device. Static

registers are registers in Page 1, 2, and 3, with values that do not change once loaded from NVM. The CRC-16

engine continuously checks the control registers on the device. The expected CRC-16 value is stored in the

NVM. When the CRC-16 engine detects a mismatch between the calculated and expected CRC-16 values, the

interrupt bit REG_CRC_ERR_INT is set and the device forces an orderly shutdown sequence to return to the

SAFE RECOVERY state. The device NVM control, configuration, and test registers in page 1 are protected

against read or write access when the device is in normal functional mode. .

The CRC-16 engine uses a standard CRC-16 polynomial to calculate the internal known-good checksum-value,

which is X¹⁶+ X¹⁴+ X¹³+ X¹²+ X¹⁰+ X⁸+ X⁶+ X⁴+ X³+ X + 1.

The initial value for the remainder of the polynomial is all 1s and is in big-endian bit-stream order. The inversion

of the calculated result is enabled.

备注

The CRC-16 engine assumes a default value of '0' for all undefined or reserved bits in all control

registers. Therefore, the software MUST NOT write the value of '1' to any of these undefined or

reserved bits. If the value of '1 is written to any undefined or reserved bit of a writable register, the

CRC-16 engine detects a mismatch between the calculated and expected CRC-16 values, and hence

the interrupt bit REG_CRC_ERR_INT is set and the device forces an orderly shutdown sequence to

return to the SAFE RECOVERY state.

8.13.3 CRC Protection for User Registers

A dynamic CRC-8 engine exists to protect registers that have values that can change during operation. These

are registers in Page 1 and 4. When writes occur to these pages, the dynamic CRC-8 is checked, computed,

and updated. Continuously during operation the CRC-8 are evaluated and verified in a round-robin fashion.

The CRC-8 engine utilizes the Polynomial(0xA6) = X⁸+ X⁶+ X³+ X²+ 1, which provides a H4 hamming

distance.

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备注

If a RESERVED bit in a R/W configuration register gets set to 1h through a I2C/SPI write, the LP8764-

Q1 detects a CRC error in the register map. Therefore, it is important that system software involved in

the I2C/SPI write-access to the LP8764-Q1 keeps all RESERVED bits (i.e. all bits with the word

RESERVED in the Register Field Description tables in the Register Map section LP8764x_map

Registers at 0h.

8.13.4 Register Write Protection

For safety application, in order to prevent unintentional writes to the control registers, the LP8764-Q1 device

implements locking and unlocking mechanisms to many of its configuration/control registers described in the

following subsections.

8.13.4.1 ESM and WDOG Configuration Registers

The configuration registers for the watchdog and the ESM are locked when their monitoring functions are in

operation. The locking mechanism and the list of the locked watchdog register is described under 节 8.14.2. The

locking mechanism and the list of the locked ESM registers is described under 节8.15

8.13.4.2 User Registers

User registers in page 0, except the ESM and the WDOG configuration registers described in 节 8.13.4.1, and

the interrupt registers (x_INT) at address 0x5a through 0x6c in page 0, can be write protected by a dedicated

lock. User must write '0x9B' to the REGISTER_LOCK register to unlock the register. Writing any value other than

'0x9B' activates the lock again. To check the register lock status, user must read the

REGISTER_LOCK_STATUS bit. When this bit is '0', it indicates the user registers are unlocked. When this bit is

'1', the user registers are locked. During start-up sequence such as powering up for the first time, waking up from

LP_STANDBY, or recovering from SAFE_RECOVERY, the user registers are unlocked automatically.

As an extra measure of protection to prevent the accidental change of the buck frequency while the buck is in

operation, the BUCKn_FREQ_SEL register bits are locked by the pre-configured NVM settings, unless

mentioned otherwise in the User's Guide of the orderable part number. .

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8.14 Watchdog (WD)

The watchdog monitors the correct operation of the MCU. This watchdog requires specific messages from the

MCU in specific time intervals to detect correct operation of the MCU. The MCU can control the logic-level of the

EN_DRV pin when the watchdog detects correct operation of the MCU. When the watchdog detects an incorrect

operation of the MCU, the LP8764-Q1 device pulls the EN_DRV pin low . This EN_DRV pin can be used in the

application as a control-signal to deactivate the power output stages, for example a motor driver, in case of

incorrect operation of the MCU.

The watchdog has two different modes that are defined as follows:

Trigger mode In trigger mode, the MCU applies a pulse signal with a minimum pulse width of t_{WD_pulse}on the

pre-assigned GPIO input pin to send the required watchdog trigger. To select this mode, the

MCU must clear bit WD_MODE_SELECT. 节8.14.6 provides more details.

Q&A

In Q&A mode, the MCU sends watchdog answers through the I2C1 bus , I2C2 bust or SPI bus.

(question and (Which of these communication busses is to be used depends on the NVM configuration.

answer) mode Please refer to the User's Guide of the orderable part number for further details). To select this

mode, the MCU must set bit WD_MODE_SELECT. 节8.14.8 provides more details.

8.14.1 Watchdog Fail Counter and Status

The watchdog includes a watchdog fail counter WD_FAIL_CNT[3:0] that increments because of bad events or

decrements because of good events. Furthermore, the watchdog includes two configurable thresholds:

1. Fail-threshold (configurable through bits WD_FAIL_TH[2:0])

2. Reset-threshold (configurable through bits WD_RST_TH[2:0])

When the WD_FAIL_CNT[3:0] counter value is less than or equal to the configured Watchdog-Fail threshold

(WD_FAIL_TH[2:0]) and bit WD_FIRST_OK=1, the MCU can set the ENABLE_DRV bit when no other error-

flags are set.

When the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail threshold

(WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]), the device clears the ENABLE_DRV bit, sets the error-flag

WD_FAIL_INT, and pulls the nINT pin low.

When the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail plus Watchdog-Reset

threshold (WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0])) and the watchdog-reset function is

enabled (configuration bit WD_RST_EN=1), the device generates a WD_ERROR trigger in the state machine

(see 表 8-5) and sets the error-flag WD_RST_INT, and pulls the nINT pin low. Unless described otherwise in the

User's Guide of the orderable part number, this WD_ERROR trigger in the state machine causes the LP8764-Q1

to execute a warm-reset, during which the GPIO pins assigned as nRSTOUT and nRSTOUT_SoC are pulled

low, and released after a pre-configured delay time.

The device clears the WD_FAIL_CNT[3:0] each time the watchdog enters the Long Window. The status bits

WD_FAIL_INT and WD_RST_INT are latched until the MCU writes a ‘1’to these bits.

Overview of Watchdog Fail Counter Value Ranges and Corresponding Device Status gives an overview of the

Watchdog Fail Counter value ranges and the corresponding device status.

表8-16. Overview of Watchdog Fail Counter Value Ranges and Corresponding Device Status

Watchdog Fail Counter value

Device Status

WD_FAIL_CNT[3:0]

MCU can set the ENABLE_DRV bit if WD_FIRST_OK=1 and no

other error-flags are set

WD_FAIL_CNT[3:0] ≤WD_FAIL_TH[2:0]

The device clears the ENABLE_DRV bit, sets error-flag

WD_FAIL_INT and pulls the nINT pin low

WD_FAIL_TH[2:0] < WD_FAIL_CNT[3:0] ≤(WD_FAIL_TH[2:0] +

WD_RST_TH[2:0])

If configuration bit WD_RST_EN=1, device generates WD_ERROR

trigger in the state machine and reacts as defined in the PFSM, sets

the error-flag WD_RST_INT, and pulls the nINT pin low. See

Summary of Interrupt Signals for the interrupt handling of WD_RTS.

WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0])

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The WD_FAIL_CNT[3:0] counter responds as follows:

• When the Watchdog is in the Long-Window, the WD_FAIL_CNT[3:0] is cleared to 4’b0000

• A good event decrements the WD_FAIL_CNT[3:0] by one before the start of the next Window-1

• A bad event increments the WD_FAIL_CNT[3:0] by one before the start of the next Window-1

Refer to Watchdog Trigger Mode and Watchdog Q&A Related Definitions respectively for definitions of good

events and bad events.

8.14.2 Watchdog Start-Up and Configuration

When the device releases the nRSTOUT pin, the watchdog starts with the Long Window. This Long Window has

a time interval (t_{LONG_WINDOW}) with a default value set in bits WD_LONGWIN[7:0].

As long as the watchdog is in the Long Window, the MCU can configure the watchdog through the following

register bits:

• WD_EN to enable or disable the watchdog

• WD_LONGWIN[7:0] to increase the duration of the Long-Window time-interval

• WD_MODE_SELECT to select the Watchdog mode (Trigger mode or Q&A Mode)

• WD_PWRHOLD to activate the Watchdog Disable function (more detail in 节8.14.4)

• WD_RETURN_LONGWIN to configure whether to return to Long-Window or continue to the next sequence

after the completion of the current watchdog sequence (more detail in 节8.14.4)

• WD_WIN1[6:0] to configure the duration of the Window-1 time-interval

• WD_WIN2[6:0] to configure the duration of the Window-2 time-interval

• WD_RST_EN to enable or disable the watchdog-reset function

• WD_FAIL_TH[2:0] to configure the Watchdog-Fail threshold

• WD_RST_TH[2:0] to configure the Watchdog-Reset threshold

• WD_QA_FDBK[1:0] to configure the settings for the reference answer-generation

• WD_QA_LFSR[1:0] to configure the settings for the question-generation

• WD_QUESTION_SEED[3:0] to configure the starting-point for the 1st question-generation

The device keeps the above register bit values configured by the MCU as long as the device is powered.

The MCU can configure the time interval of the Long Window (t_{LONG_WINDOW}) with the WD_LONGWIN[7:0] bits.

The WD_LONGWIN[7:0] bits are defined as:

• 0x00: 80 ms

• 0x01 - 0x40: 125 ms to 8 sec, in 125-ms steps

• 0x41 - 0xFF: 12 sec to 772 sec, in 4-sec steps

Use 方程式 5 and 方程式 6 to calculate the minimum and maximum values for the Long Window (t_{LONG_WINDOW}

)

time interval when WD_LONGWIN[7:0] > 0x00:

t_{LONG_WINDOW_MIN}= WD_LONGWIN[7:0] × 0.95

t_{LONG_WINDOW_MAX}= WD_LONGWIN[7:0] × 1.05

(5)

(6)

When the MCU clears bit WD_EN, the watchdog goes out of the Long Window and disables the watchdog.

When the watchdog is disabled in this way, the MCU can set bit WD_EN back to ‘1’ to enable the watchdog

again, and the MCU can control the ENABLE_DRV bit when no other error-flags are set. The MCU must clear bit

WD_PWRHOLD before setting bit WD_EN back to ‘1’to start the watchdog in Long Window.

The watchdog locks the following configuration register bits when it goes out of the Long Window and starts the

first watchdog sequence:

• WD_WIN1[6:0]

• WD_WIN2[6:0]

• WD_LONGWIN[7:0]

• WD_MODE_SELECT

• WD_QA_FDBK[1:0], WD_QA_LFSR[1:0] and WD_QUESTION_SEED[3:0]

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• WD_RST_EN, WD_EN, WD_FAIL_TH[2:0] and WD_RST_TH[2:0]

8.14.3 MCU to Watchdog Synchronization

In order to go out of the Long Window and start the first watchdog sequence, the MCU must do the following

before elapse of the Long Window time interval:

• Clear bits WD_PWRHOLD (more detail in 节8.14.4)

• Apply a pulse signal with a minimum pulse-width t_{WD_pulse}on the pre-assigned GPIO pin in the case the

watchdog is configured for Trigger mode, or

• Write four times to WD_ANSWER[7:0] in the case the watchdog is configured for Q&A mode

When the MCU fails to get the watchdog out of the Long Window before the configured Long Window time

interval (t_{LONG_WINDOW}

)

elapses, the device goes through

a

warm reset, and sets the

WD_LONGWIN_TIMEOUT_INT. This bit latched until the MCU writes a ‘1’to clear it.

8.14.4 Watchdog Disable Function

In case the MCU needs to be reprogrammed while the watchdog monitors the correct operation of the MCU, the

MCU can set bit WD_RETURN_LONGWIN to put the watchdog back in the Long Window. When the MCU set

this bit, the watchdog returns to the Long Window after the current Watchdog Sequence completes. In order to

make the watchdog stay in the Long Window as long as needed the MCU can either re-configure the Long

Window (t_{LONG_WINDOW}) time interval, or set the WD_PWRHOLD bit. Once the MCU starts the first watchdog

sequence (as described in 节 8.14.3), the MCU must clear bit WD_RETURN_LONGWIN before the end of the

first watchdog sequence in order to continue the watchdog sequence operation.

8.14.5 Watchdog Sequence

Once the watchdog is out of the Long Window, each watchdog sequence starts with a Window-1 followed by a

Window-2. The watchdog ends the current sequence and after one 20-MHz system clock cycle starts a next

sequence when one of the events below occurs:

• The configured Window-2 time period elapses

• The watchdog detects a pulse signal with a minimum pulse-width t_{WD_pulse}on the pre-assigned GPIO pin if

the watchdog is used in Trigger mode

• The watchdog detects four times a write access to WD_ANSWER[7:0] in case the watchdog is used in Q&A

mode

The MCU can configure the time periods of the Window-1 (t_WINDOW1) and Window-2 (t_WINDOW2) with the bits

WD_WIN1[6:0] and WD_WIN2[6:0] respectively, before starting the sequence.

Use 方程式7 and 方程式8 to calculate the minimum and maximum values for the t_WINDOW1time interval.

t_{WINDOW1_MIN}= (WD_WIN1[6:0] + 1) × 0.55 × 0.95 ms

t_{WINDOW1_MAX}= (WD_WIN1[6:0] + 1) × 0.55 × 1.05 ms

(7)

(8)

Use 方程式9 and 方程式10 to calculate the minimum and maximum values for the t_WINDOW-2time interval.

t_{WINDOW2_MIN}= (WD_WIN2[6:0] + 1) × 0.55 × 0.95 ms

t_{WINDOW2_MAX}= (WD_WIN2[6:0] + 1) × 0.55 × 1.05 ms

(9)

(10)

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8.14.6 Watchdog Trigger Mode

When the LP8764-Q1 device is configured to use the Watchdog Trigger Mode, the watchdog receives the

watchdog-triggers from the MCU on the pre-assigned GPIO pin. A rising edge on this GPIO pin, followed by a

stable logic-high level on that pin for more than the maximum pulse time, t_{WD_pulse(max)}, is a watchdog-trigger.

The watchdog uses a deglitch filter with a t_{WD_pulse}filter time and the internal 20-MHz system clock to create the

internally-generated trigger pulse from the watchdog-trigger on the pre-assigned GPIO pin.

The watchdog detects a good event when the watchdog-trigger comes in Window-2. The rising edge of the

watchdog-trigger on the pre-assigned GPIO pin must occur for at least the t_{WD_pulse}time before the end of

Window-2 to generate such a good event.

The watchdog detects a bad event when one of the following events occurs:

• The watchdog-trigger comes in Window-1. The rising edge of the watchdog-trigger on the pre-assigned GPIO

pin must occur for at least the t_{WD_pulse}time before the end of Window-1 to generate such a bad event. In

case of this bad event, the device sets bits WD_TRIG_EARLY and WD_BAD_EVENT.

• No watchdog-trigger comes in Window-2. In case of this bad event (also referred to as time-out event), the

device sets bits WD_TIMEOUT and WD_BAD_EVENT.

Please consider that the minimum WD-pulse duration needs to meet the maximum deglitch time t_{WD_pulse (max)}

.

The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of

the watchdog-sequence.

节8.14.7 shows the flow-chart of the watchdog in Trigger mode.

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8.14.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode

NO SUPPLY

Device sets WD_RST_EN=1 per default

Device sets WD_EN=1 per default.

Wake-up

request?

NO

YES

RESTART

from all

states except

NO SUPPLY

Reset-Extension

me-interval

elapsed?

NO

YES

WATCHDOG LONG WINDOW

- MCU reset inac ve

- Device forces ENABLE_DRV= 0

- MCU clears error- ags

WD_RETURN_

LONGWIN=1?

YES

- Device releases nINT pin if no other error- ags are set

- Device unlocks Watchdog-Con gura on registers

- Device sets WD_FAIL_CNT[3:0]=4'b0000 and sets WD_FIRST_OK=0

MCU either clears WD_EN, or:

NO

WINDOW-1

- If FIRST_WD_OK=0, device forces

ENABLE_DRV=0, else device does not change

ENABLE_DRV bit

1) MCU con gures watchdog in Trigger mode

2) MCU con gures Window-1 and Window-2 me-intervals

3) MCU con gures WD_FAIL_TH, WD_RST_TH and WD_RST_EN

4) MCU sends trigger pulse

- Device waits un l WINDOW-1 me elapses

NO

- Device sets

WD_TRG_EARLY

error- ag

- Device sets

WD_BAD_EVENT

error- ag

Device has

Received trigger-

NO

WD_PWRHOLD=0?

YES

WINDOW-1

NO

YES

me-interval

elapsed?

pulse

?

YES

WD_EN=0?

YES

NO

WINDOW-2

- If FIRST_WD_OK=0, device forces

ENABLE_DRV=0, else device does not

change ENABLE_DRV bit

YES

- MCU sends trigger-pulse

NO

NORMAL – NO Watchdog

- MCU reset inac ve

- MCU can set

ENABLE_DRV=1 if no other

error- ags are set

NO

WD_EN=0?

Device sets

WD_TIMEOUT error-

ag

Device has

Received trigger-

WINDOW-2

me-interval

elapsed?

YES

NO

Device clears

WD_BAD_EVENT

error- ag

- Device sets

WD_BAD_EVENT

error- ag

pulse

?

- Interrupt inac ve if no

other error- ag set

YES

- Device decrements WD_FAIL_CNT

- Device sets WD_FIRST_OK=1

- MCU can set ENABLE_DRV=1 if no other error- ags are set

Device has

received trigger

pulse?

Device locks all Watchdog

con gura on register bits, except

WD_RETURN_LONGWIN bit

YES

NO

Device Increments

WD_FAIL_CNT[3:0]

LONG-WINDOW

me-interval

elapsed?

NO

YES

WD_FAIL_CNT[3:0] >

WD_FAIL_TH

[2:0]

NO

Device sets

WD_LONGWIN_TIMEOUT

error- ag

YES

WATCHDOG-RESET

- Device pulls MCU & SoC reset

pins low (trigger to FSM)

- Device forces ENABLE_DRV=0

- Device clears WD_FIRST_OK bit

- Device forces ENABLE_DRV=0

- Device sets WD_FAIL_INT

error- ag

- Interrupt ac ve

Reset-Extension

me-interval

YES

NO

elapsed?

WD_FAIL_CNT[3:0] >

(WD_FAIL_TH[2:0] +

WD_RST_TH[2:0])

&

- Device sets WD_RST_INT

error- ag

- Interrupt ac ve

- Device clears

WD_BAD_EVENT error- ag

YES

NO

WD_RST_EN=1

图8-41. Flow Chart for WatchDog Monitor in Trigger Mode

图 8-42, 图 8-43, 图 8-44, 图 8-45, and 图 8-46 give examples of watchdog is trigger mode with good and bad

events after device start-up. In these figures, the red bended arrows indicate a delay of one 20-MHz system

clock cycle.

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8.14.8 Watchdog Question-Answer Mode

When the LP8764-Q1 device is configured to use the Watchdog Question Answer mode, the watchdog requires

specific messages from the MCU in specific time intervals to detect correct operation of the MCU.

The device provides a question for the MCU in WD_QUESTION[3:0] during operation. The MCU performs a

fixed series of arithmetic operations on this question to calculate the required 32-bit answer. This answer is split

into four answer bytes: Answer-3, Answer-2, Answer-1, and Answer-0. The MCU writes these answer bytes one

byte at a time into WD_ANSWER[7:0] from the SPI or the dedicated I²C2 interface, mapped to GPIO2 and

GPIO3 pins.

A good event occurs when the MCU sends the correct answer-bytes calculated for the current question in the

correct watchdog window and in the correct sequence.

A bad event occurs when one of the events that follows occur:

• The MCU sends the correct answer-bytes, but not in the correct watchdog window.

• The MCU sends incorrect answer-bytes.

• The MCU returns correct answer-bytes, but in the incorrect sequence.

If the MCU stops providing answer-bytes for the duration of the watchdog time-period, the watchdog detects a

time-out event. This time-out event sets the WD_TIMEOUT status bit, increments the WD_FAIL_CNT[3:0]

counter, and starts a new watchdog sequence.

8.14.8.1 Watchdog Q&A Related Definitions

A question and answer are defined as follows:

Question

A question is a 4-bit word (see 节8.14.8.2).

The watchdog provides the question to the MCU when the MCU reads the WD_QUESTION[3:0] bits.

The MCU can request each new question at the start of the watchdog sequence, but this is not

required to calculate the answer. The MCU can also have a software implementation that generates

the question according the circuit shown in 图 8-49. Nevertheless, the answer and therefore the

answer-bytes are always based on the question generated inside the watchdog of the device. So, if

the MCU generates an incorrect question and gives answer-bytes calculated from this incorrect

question, the watchdog detects a bad event

Answer An answer is a 32-bit word that is split into four answer bytes: Answer-3, Answer-2, Answer-1, and

Answer-0.

The watchdog receives an answer-byte when the MCU writes to the WD_ANSWER[7:0] bits. For

each question, the watchdog requires four correct answer-bytes from the MCU in the correct timing

and order (Answer-3, Answer-2, and Answer-1 in Window 1 in the correct sequence, and Answer-0

in Window 2) to detect a good event.

The watchdog sequence in Q&A mode ends after the MCU writes the fourth answer byte (Answer-0), or after a

time-out event when the Window-2 time-interval elapses.

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Window-1

t = t_WINDOW-1

Window-2

t = t_WINDOW-2

Three correct answer-bytes must be provided in Window-1 and

in the correct order:

The fourth answer-byte, Answer-0, must be provided

in Window-2.

ñ

Answer-3

Answer-2

Answer-1

After the MCU writes the fourth Answer-0 to

WD_ANSWER[7:0], the Watchdog generates the

next question within 1 Internal System Clock Cycle,

after which the next Watchdog Sequence

(Q&A [n + 1]) begins

After the Window-1 time elapses, Window 2 begins.

The MCU needs to write the answer-bytes to the WD_ANSWER[7:0] bits.

Question

Answer

MCU reads question⁽¹⁾

MCU provides answer⁽²⁾

Write to

WD_ANSWER[7:0]

-> Answer-1

Read bits WD_

QUESTION[3:0]

Write to

WD_ANSWER[7:0]

-> Answer-0

WD_ANSWER[7:0] WD_ANSWER[7:0]

-> Answer-3

I2C2/SPI

Commands

-> Answer-2

NCS Pin (for

SPI only)

1 Internal System Clock Cycle

to Generate a new question for the next watchdog

sequence Q&A [n + 1]

Q&A [n]

Q&A [n + 1]

Watchdog Sequence

(1) The MCU is not required to read the question. The MCU can give correct answer-bytes Answer-3, Answer-2, Answer-1 as soon as

Window-1 starts. The next watchdog sequence always starts in 1 system clock cycle after the watchdog receives the final Answer-0.

(2) The MCU can put other I²C or SPI commands in-between the write-commands to WD_ANSWER[7:0] (even re-requesting the

question). The insertion of other commands in-betwween the write-commands to WD_ANSWER[7:0] has no influence on the detection

of a good event, as long as the three correct answer-bytes in Window-1 are in the correct sequence, and the fourth correct answer-byte

is provided before the configured Window-2 time-interval elapses.

图8-47. Watchdog Sequence in Q&A Mode

8.14.8.2 Question Generation

The watchdog uses a 4-bit question counter (QST_CNT[3:0] bits in 图 8-48), and a 4-bit Markov chain to

generate a 4-bit question. The MCU can read this question in the WD_QUESTION[3:0] bits. The watchdog

generates a new question when the question counter increments, which only occurs when the watchdog detects

a good event. The watchdog does not generate a new question when it detects a bad event or a time-out event.

The question-counter provides a clock pulse to the Markov chain when it transitions from 4’b1111 to 4’b0000.

The question counter and the Markov chain are set to the default value of 4’b0000 when the watchdog goes

out of the Long Window.

图8-48 shows the logic combination for the WD_QUESTION[3:0] generation.

图 8-49 shows how the logic combination of the question-counter with the WD_ANSW_CNT[1:0] status bits

generates the reference answer-bytes.

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4-Bit LFSR Polynomial Equation⁽¹⁾

WD_QA_LFSR[1:0] = 0x00:

y = x4 + x3 + 1 (Default Value)

y = x4 + x2 + 1

y = x3 + x2 + 1

WD_QA_LFSR[1:0] = 0x01:

WD_QA_LFSR[1:0] = 0x10:

WD_QA_LFSR[1:0] = 0x11:

y = x4 + x3 + x2 +1

x3

x1

x2

x4

Bit 0

Bit 3

Bit 1

Bit 2

4-bit SEED Value Loaded when the device goes to the RESET state

(Configurable Through WD_QUESTION_SEED[3:0])

(Default Value 4'b1010)

x1

1

0

1

0

1

0

1

0

1

x2

0

1

0

1

0

1

0

1

0

x3

1

0

1

0

1

0

1

0

1

x4

0

1

0

1

0

1

0

1

0

x2

x1

x4

x3

00

01

10

11

WD_QUESTION[0]

SEED

1

QST_CNT[1]

QST_CNT[0]

QST_CNT[3]

QST_CNT[2]

00

01

10

11

2

3

4

x4

x3

x2

x1

00

01

10

11

5

WD_QUESTION[1]

6

7

QST_CNT[3]

QST_CNT[2]

QST_CNT[1]

QST_CNT[0]

00

01

10

11

8

9

10

11

12

13

14

15

00

01

10

11

x1

x4

x3

x2

WD_QUESTION[2]

00

01

10

11

QST_CNT[0]

QST_CNT[3]

QST_CNT[2]

QST_CNT[1]

The default question-sequence order with the default

WD_QUESTION_SEED[3:0] and WD_QA_LFSR[1:0] values

x3

x2

x1

x4

00

01

10

11

WD_QUESTION[3]

”Question‘ Counter

CNT [0]

QST_CNT[0]

QST_CNT[1]

QST_CNT[2]

QST_CNT[3]

QST_CNT[2]

QST_CNT[1]

QST_CNT[0]

QST_CNT[3]

00

01

10

11

CNT [1]

—good event“

INCR + 1

trigger

CNT [2]

CNT [3]

Feedback settings are controllable through the bits

WD_QA_FDBK[1:0]

(Default value is 2'b00; the selected signals are in red)

(1) If the current value for bits (x1, x2, x3, x4) is 4'b0000, the next value for these bits (x1, x2, x3, x4) is 4'b0001, and all further question

generation begins from this value.

图8-48. Watchdog Question Generation

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WD_QUESTION[0]

WD_QUESTION[1]

WD_QUESTION[2]

WD_QUESTION[3]

00

01

10

11

Reference-Answer-X[0]

X = 3, 2,1, 0

WD_ANSW_CNT[1]

WD_QUESTION[3]

WD_QUESTION[2]

WD_QUESTION[1]

WD_QUESTION[0]

00

01

10

11

WD_QUESTION[0]

WD_QUESTION[1]

WD_QUESTION[2]

WD_QUESTION[3]

00

01

10

11

Reference-Answer-X[1]

X = 3, 2,1, 0

WD_QUESTION[2]

WD_QUESTION[1]

WD_QUESTION[0]

WD_QUESTION[3]

00

01

10

11

WD_QUESTION[1]

WD_ANSW_CNT[1]

WD_QUESTION[0]

WD_QUESTION[3]

WD_QUESTION[1]

00

01

10

11

Reference-Answer-X[2]

X = 3, 2,1, 0

WD_QUESTION[3]

WD_QUESTION[2]

WD_QUESTION[1]

WD_QUESTION[0]

00

01

10

11

WD_QUESTION[1]

WD_ANSW_CNT[1]

WD_QUESTION[2]

WD_QUESTION[1]

WD_QUESTION[0]

WD_QUESTION[3]

00

01

10

11

Reference-Answer-X[3]

X = 3, 2,1, 0

WD_QUESTION[0]

WD_QUESTION[3]

WD_QUESTION[2]

WD_QUESTION[1]

00

01

10

11

WD_QUESTION[3]

WD_ANSW_CNT[1]

WD_QUESTION[1]

WD_QUESTION[0]

WD_QUESTION[2]

WD_QUESTION[3]

00

01

10

11

Reference-Answer-X[4]

X = 3, 2,1, 0

WD_ANSW_CNT[0]

WD_QUESTION[3]

WD_QUESTION[2]

WD_QUESTION[1]

WD_QUESTION[0]

00

01

10

11

Reference-Answer-X[5]

X = 3, 2,1, 0

WD_ANSW_CNT[0]

WD_QUESTION[0]

WD_QUESTION[3]

WD_QUESTION[2]

WD_QUESTION[1]

00

01

10

11

Reference-Answer-X[6]

X = 3, 2,1, 0

WD_ANSW_CNT[0]

WD_QUESTION[2]

WD_QUESTION[1]

WD_QUESTION[0]

WD_QUESTION[3]

00

01

10

11

Reference-Answer-X[7]

X = 3, 2,1, 0

WD_ANSW_CNT[0]

Feedback settings are controllable through the bits WD_QA_FDBK[1:0]

(Default value is 2'b00; the selected signals are in red)

Calculated Reference-Answer-X byte

图8-49. Watchdog Reference Answer Calculation

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8.14.8.3 Answer Comparison

The 2-bit, watchdog-answer counter, WD_ANSW_CNT[1:0], counts the number of received answer-bytes and

controls the generation of the reference answer-byte as shown in 图 8-49. At the start of each watchdog

sequence, the default value of the WD_ANSW_CNT[1:0] counter is 2’b11 to indicate that the watchdog expects

the MCU to write the correct Answer-3 in WD_ANSWER[7:0].

The device sets the WD_ANSW_ERR status bit as soon as one answer byte is not correct. The device clears

this status bit only if the MCU writes a ‘1’to this bit.

8.14.8.3.1 Sequence of the 2-bit Watchdog Answer Counter

The sequence of the 2-bit, watchdog answer-counter is as follows for each counter value:

• WD_ANSW_CNT[1:0] = 2‘b11:

1. The watchdog calculates the reference Answer-3.

2. A write access occurs. The MCU writes the Answer-3 byte in WD_ANSWER[7:0].

3. The watchdog compares the reference Answer-3 with the Answer-3 byte in WD_ANSWER[7:0].

4. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘10 and sets the WD_ANSW_ERR

status bit to 1 if the Answer-3 byte was incorrect.

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• WD_ANSW_CNT[1:0] = 2b‘10:

1. The watchdog calculates the reference Answer-2.

2. A write access occurs. The MCU writes the Answer-2 byte in WD_ANSWER[7:0].

3. The watchdog compares the reference Answer-2 with the Answer-2 byte in WD_ANSWER[7:0]..

4. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘01 and sets the WD_ANSW_ERR

status bit to 1 if the Answer-2 byte was incorrect.

• WD_ANSW_CNT[1:0] = 2b‘01:

1. The watchdog calculates the reference Answer-1.

2. A write access occurs. The MCU writes the Answer-1 byte in WD_ANSWER[7:0].

3. The watchdog compares the reference Answer-1 with the Answer-1 byte in WD_ANSWER[7:0]..

4. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘00 and sets the WD_ANSW_ERR

status bit to 1 if the Answer-1 byte was incorrect.

• WD_ANSW_CNT[1:0] = 2b‘00:

1. The watchdog calculates the reference Answer-0.

2. A write access occurs. The MCU writes the Answer-0 byte in WD_ANSWER[7:0].

3. The watchdog compares the reference Answer-0 with the Answer-0 byte in WD_ANSWER[7:0].

4. The watchdog sets the WD_ANSW_ERR status bit to 1 if the Answer-0 byte was incorrect.

5. The watchdog starts a new watchdog sequence and sets the WD_ANSW_CNT[1:0] to 2‘b11’.

The MCU needs to clear the bit by writing a '1' to the WD_ANSW_ERR bit.

表8-17. Set of Questions and Corresponding Answer-Bytes Using the Default Setting of WD_QA_CFG

Register

ANSWER-BYTES (EACH BYTE TO BE WRITTEN INTO WD_ANSWER[7:0])

WD QUESTION

ANSWER-3

ANSWER-2

ANSWER-1

ANSWER-0

WD_ANSW_CNT [1:0] =

WD_QUESTION[3:0]

2’b11

2’b10

2’b01

2’b00

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

FF

B0

E9

A6

75

3A

63

2C

D2

9D

C4

8B

58

17

4E

01

0F

40

19

56

85

CA

93

DC

22

6D

34

7B

A8

E7

BE

F1

F0

BF

E6

A9

7A

35

6C

23

DD

92

CB

84

57

18

41

0E

00

4F

16

59

8A

C5

9C

D3

2D

62

3B

74

A7

E8

B1

FE

8.14.8.3.2 Watchdog Sequence Events and Status Updates

The watchdog sequence events are as follows for the different scenarios listed:

• A good event occurs when all answer bytes are correct in value and timing. After such a good event,

following events occur:

1. The WD_FAIL_CNT[2:0] counter decrements by one at the end of the watchdog-sequence.

2. The question-counter increments by one and the watchdog generates a new question.

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• A bad event occurs when all answer-bytes are correct in value but not in correct timing. After such a bad

event, following events occur:

1. The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before

watchdog has received Answer-3, Answer-2 and Answer-1.

2. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answers

in Window-1.

3. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence.

4. The question-counter does not change, and hence the watchdog does not generate a new question.

• A bad event occurs when one or more of the answer-bytes are not correct in value but in correct timing. After

such a bad event, following events occur:

1. The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an

incorrect answer-byte.

2. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence.

3. The question-counter does not change, and hence the watchdog does not generate a new question.

• A bad event occurs when one or more of the answer-bytes are not correct in value and not in correct timing.

After such a bad event, following events occur:

1. The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an

incorrect answer-byte.

2. The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before

watchdog has received Answer-3, Answer-2 and Answer-1.

3. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answer-

bytes in Window-1.

4. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence.

5. The question-counter does not change, and hence the watchdog does not generate a new question.

• A time-out event occurs when the device receives less than 4 answer-bytes before Window-2 time-interval

elapses. After a time-out event occurs, following events occur:

1. WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before

watchdog has received Answer-3, Answer-2 and Answer-1.

2. The WD_TIMEOUT and WD_BAD_EVENT status bits are set at the end of the watchdog-sequence.

3. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence.

4. The question-counter does not change, and hence the watchdog does not generate a new question.

The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of

the watchdog-sequence.

The status bits WD_SEQ_ERR, WD_ANSW_EARLY, and WD_TIMEOUT are latched until the MCU writes a

‘1’ to these bits. If one or more of these status bits are set, the watchdog can still detect a good event in the

next watchdog-sequence. These status bits are read-only. The watchdog clears the WD_BAD_EVENT status bit

at the end of the watchdog-sequence.

图8-50 shows the flow-chart of the watchdog in Q&A mode.

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WD_RETURN_

LONGWIN=1?

YES

NO

NO SUPPLY

ANSWER-3

Device sets WD_RST_EN=1 per default

Device sets WD_EN=1 per default.

Wake-up

- Device sets WD_ANSW_CNT[2:0]=2'b11

- If FIRST_WD_OK=0, device forces

ENABLE_DRV=0, else device does not

change ENABLE_DRV bit

NO

request?

NO

- MCU sends ANSWER-3

- Device sets

WD_SEQ_ERR

error- ag

YES

Device has

received

ANSWER-3 ?

- Device sets

WD_BAD

_EVENT

WINDOW-2

me-interval

elapsed?

WINDOW-1

me-interval

elapsed?

YES

NO

error- ag

RESTART

from all

states except

NO SUPPLY

YES

Reset-Extension

me-interval

elapsed?

NO

YES

- Device sets

WD_ANSW_ERR error- ag

- Device sets

ANSWER-3

correct?

NO

YES

WD_BAD_EVENT error- ag

YES

WATCHDOG LONG WINDOW

- Device releases MCU reset pin

- Device forces ENABLE_DRV= 0

- MCU clears error- ags

- Device releases nINT pin if no other error- ags are set

- Device unlocks Watchdog-Con gura on registers

- Device sets WD_ANSW_CNT[2:0]=2'b11

- Device sets WD_FAIL_CNT[3:0]=4'b0000 and sets WD_FIRST_OK=0

MCU either clears WD_EN, or:

1) MCU con gures watchdog in Q&A mode

2) MCU con gures Window-1 and Window-2 me-intervals

3) MCU con gures WD_FAIL_TH, WD_RST_TH and WD_RST_EN

4) MCU sends 4 answers

ANSWER-2

- Device sets WD_ANSW_CNT[2:0]=2'b10

- If FIRST_WD_OK=0, device forces

ENABLE_DRV=0, else device does not

change ENABLE_DRV bit

NO

- MCU sends ANSWER-2

- Device sets

WD_SEQ_ERR

error- ag

- Device sets

WD_BAD

_EVENT

Device has

received

ANSWER-2?

YES

WINDOW-2

me-interval

elapsed?

WINDOW-1

me-interval

elapsed?

NO

YES

error- ag

YES

- Device sets

ANSWER-2

correct?

WD_ANSW_ERR error- ag

- Device sets

WD_BAD_EVENT error- ag

NO

WD_PWRHOLD=0?

YES

ANSWER-1

- Device sets WD_ANSW_CNT[2:0]=2'b01

- If FIRST_WD_OK=0, device forces

ENABLE_DRV=0, else device does not

change ENABLE_DRV bit

WD_EN=0?

YES

NO

- MCU sends ANSWER-1

- Device sets

WD_SEQ_ERR

error- ag

- Device sets

WD_BAD

_EVENT

YES

Device has

WINDOW-2

me-interval

elapsed?

WINDOW-1

me-interval

elapsed?

NORMAL – NO Watchdog

- MCU reset inac ve

- MCU can set

ENABLE_DRV=1 if no other

error- ags are set

YES

NO

received

NO

WD_EN=0?

ANSWER-1?

error- ag

YES

- Device released nINT pin if

no other error- ag set

YES

- Device sets

WD_ANSW_ERR error- ag

- -Device sets

NO

ANSWER-1

correct?

WD_BAD_EVENT error- ag

YES

Device generates 1^st

QUESTION

Device has

received 4

answers ?

YES

ANSWER-0

- Device locks all Watchdog

con gura on register bits,

except

- Device sets WD_ANSW_CNT[2:0]=2'b00

- If FIRST_WD_OK=0, device forces

ENABLE_DRV=0, else device does not

change ENABLE_DRV bit

WD_RETURN_LONGWIN bit

NO

- MCU sends ANSWER-0

Device sets

WD_TIMEOUT

error- ag

- Device sets

WD_BAD_EVENT

error- ag

LONG-WINDOW

me-interval

elapsed?

Device has

received

ANSWER-0?

NO

WINDOW-2

me-interval

elapsed?

YES

NO

Device

Increments

WD_FAIL_CNT

[3:0]

YES

Device sets

WD_LONGWIN_TIMEOUT

error- ag

Device sets

WD_ANSW_EARLY error- ag

- Device sets

WINDOW-1

me-interval

not elapsed?

YES

WD_FAIL_CNT[3:0] >

WD_FAIL_TH

[2:0]

NO

WD_BAD_EVENT error- ag

WATCHDOG-RESET

- Device pulls MCU & SoC reset

pins low (trigger to FSM)

NO

YES

- Device forces ENABLE_DRV=0

- Device clears WD_FIRST_OK bit

- Device sets

WD_ANSW_ERR error- ag

- Device sets

Device clears

WD_BAD_EVENT

error- ag

NO

ANSWER-0

correct?

- Device forces ENABLE_DRV=0

- Device sets WD_FAIL_INT

error- ag

WD_BAD_EVENT error- ag

YES

- Interrupt ac ve

Reset-Extension

me-interval

YES

NO

elapsed?

- Device sets WD_RST_INT

error- ag

YES

WD_BAD_EVENT

=1?

- Interrupt ac ve

- Device clears

WD_BAD_EVENT error- ag

NO

WD_FAIL_CNT[3:0] >

(WD_FAIL_TH[2:0] +

WD_RST_TH[2:0])

&

- Device decrements WD_FAIL_CNT

- Device generates next QUESTION

- Device sets WD_FIRST_OK=1

YES

NO

- MCU can set ENABLE_DRV=1 if no other error- ags are set

WD_RST_EN=1

图8-50. Flow Chart for WatchDog in Q&A Mode

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8.14.8.3.3 Watchdog Q&A Sequence Scenarios

表8-18. Correct and Incorrect WD Q&A Sequence Run Scenarios

NUMBER OF WD ANSWERS

WD STATUS BITS IN WDT_STATUS REGISTER

ACTION

COMMENTS

RESPONSE

WINDOW 1

RESPONSE

WINDOW 2

ANSW_ERR ANSW_EARLY

SEQ_ERR

TIME_OUT

-New WD cycle starts after the

end of RESPONSE WINDOW 2

-Increment WD failure counter

-New WD cycle starts with the

same WD question

0 answers

0b

1b

0b

1b

0b

No answers

-New WD cycle starts after the

4th WD answer

-Increment WD failure counter

-New WD cycle starts with the

same WD question

4 INCORRECT

answers

1b

WD_ANSW_CNT[1:0] = 3

-New WD cycle starts after the

4th WD answer

-Increment WD failure counter

-New WD cycle starts with the

same WD question

4 CORRECT

answers

0 answers

1 CORRECT answer

Less than 3 CORRECT

ANSWER in RESPONSE

WINDOW 1 and 1 CORRECT

ANSWER in RESPONSE

WINDOW 2

-New WD cycle starts after the

end of RESPONSE WINDOW 2

-Increment WD failure counter

-New WD cycle starts with the

same WD question

1 CORRECT answer 1 CORRECT answer

0b

1b

0b

1b

2 CORRECT answer 1 CORRECT answer

(WD_ANSW_CNT[1:0] < 3)

1 INCORRECT

0 answers

answer

Less than 3 CORRECT

ANSWER in RESPONSE

WINDOW 1 and 1 INCORRECT

ANSWER in RESPONSE

WINDOW 2

-New WD cycle starts after the

end of RESPONSE WINDOW 2

-Increment WD failure counter

-New WD cycle starts with the

same WD question

1 INCORRECT

1 CORRECT answer

answer

2 CORRECT

answers

1 INCORRECT

answer

(WD_ANSW_CNT[1:0] < 3)

4 CORRECT

answers

0 answers

-New WD cycle starts after the

4th WD answer

-Increment WD failure counter

-New WD cycle starts with the

same WD question

Less than 3 CORRECT

ANSWER in WIN1 and more

than 1 CORRECT ANSWER in

RESPONSE WINDOW 2

(WD_ANSW_CNT[1:0] = 3)

3 CORRECT

answers

1 CORRECT answer

0b

1b

0b

1b

0b

2 CORRECT

answers

2 CORRECT

answers

4 INCORRECT

answers

0 answers

Less than 3 CORRECT

-New WD cycle starts after the

4th WD answer

-Increment WD failure counter

-New WD cycle starts with the

same WD question

ANSWER in RESPONSE

WINDOW 1 and more than 1

INCORRECT ANSWER in

RESPONSE WINDOW 2

(WD_ANSW_CNT[1:0] = 3)

3 INCORRECT

answers

1 CORRECT answer

2 CORRECT

answers

2 INCORRECT

answers

-New WD cycle starts after the

end of RESPONSE WINDOW 2

-Increment WD failure counter

-New WD cycle starts with the

same WD question

3 CORRECT

answers

0 answers

0b

1b

0b

1b

Less than 3 INCORRECT

ANSWER in RESPONSE

WINDOW 1 and more than 1

CORRECT ANSWER in

RESPONSE WINDOW 2

(WD_ANSW_CNT[1:0] < 3)

1 INCORRECT

answer

2 CORRECT

answers

-New WD cycle starts after the

end of RESPONSE WINDOW 2

-Increment WD failure counter

-New WD cycle starts with the

same WD question

2 INCORRECT

answers

1 CORRECT answer

3 INCORRECT

answers

0 answers

Less than 3 INCORRECT

ANSWER in RESPONSE

WINDOW 1 and more than 1

INCORRECT ANSWER in

RESPONSE WINDOW 2

(WD_ANSW_CNT[1:0] < 3)

-New WD cycle starts after the

end of RESPONSE WINDOW 2

-Increment WD failure counter

-New WD cycle starts with the

same WD question

1 INCORRECT

answer

2 INCORRECT

answer

1b

0b

1b

2 INCORRECT

answer

1 INCORRECT

answer

4 CORRECT

answers

0 answers

0b

1b

0b

1b

0b

Less than 3 INCORRECT

ANSWER in RESPONSE

WINDOW 1 and more than 1

CORRECT ANSWER in

RESPONSE WINDOW 2

(WD_ANSW_CNT[1:0] = 3)

-New WD cycle starts after the

4th WD answer

-Increment WD failure counter

-New WD cycle starts with the

same WD question

1 INCORRECT

answer

3 CORRECT

answers

2 INCORRECT

answers

2 CORRECT

answers

4 INCORRECT

answers

0 answers

Less than 3 INCORRECT

ANSWER in RESPONSE

WINDOW 1 and more than 1

INCORRECT ANSWER in

RESPONSE WINDOW 2

(WD_ANSW_CNT[1:0] = 3)

-New WD cycle starts after the

4th WD answer

-Increment WD failure counter

-New WD cycle starts with the

same WD question

1 INCORRECT

answer

3 INCORRECT

answers

1b

0b

1b

0b

2 INCORRECT

answers

2 INCORRECT

answers

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表8-18. Correct and Incorrect WD Q&A Sequence Run Scenarios (continued)

NUMBER OF WD ANSWERS

WD STATUS BITS IN WDT_STATUS REGISTER

ACTION

COMMENTS

RESPONSE

WINDOW 1

RESPONSE

WINDOW 2

ANSW_ERR ANSW_EARLY

SEQ_ERR

TIME_OUT

3 CORRECT

answers

0 answers

0b

1b

-New WD cycle starts after the

end of RESPONSE WINDOW 2

-Increment WD failure counter

-New WD cycle starts with the

same WD Question

Less than 4 CORRECT ANSW in

RESPONSE WINDOW 1 and


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LP8764-Q1 [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E