LP87702KRHBT [TI]
LP87702 Dual Buck Converter and 5-V Boost With Diagnostic Functions;型号: | LP87702KRHBT |
厂家: | TEXAS INSTRUMENTS |
描述: | LP87702 Dual Buck Converter and 5-V Boost With Diagnostic Functions |
文件: | 总98页 (文件大小:4553K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LP87702
SNVSBU3 – MARCH 2021
LP87702 Dual Buck Converter and 5-V Boost With Diagnostic Functions
•
Factory Automation:
1 Features
– Industrial Robot – Safety Area Scanner
– Autonomous Guided Vehicle (AGV)
– Level Transmitter – Sensing
Industrial Transport:
•
FMEDA and Functional Safety Manual Available
to Support System-Level Functional Safety
Requirements up to SIL-2 (IEC 61508)
Two High-Efficiency Step-Down DC/DC
converters:
•
•
– Traffic Enforcement
– Intersection Monitoring
– Road-Railway Sensors
– Intelligent Lighting Sensors
Appliances:
– AC Control
– Appliances User Interface and Connectivity
Modules
– Maximum Output Current 3.5 A
– 2-MHz, 3-MHz, or 4-MHz Switching Frequency
– Auto PWM/PFM and Forced-PWM Operations
– Output Voltage = 0.7 V to 3.36 V
5-V 600 mA Boost Converter
Two Inputs for External Voltage Monitoring
Two Programmable Power-Good Signals
Dedicated Reference Voltage for Diagnostics
Window Watchdog with Reset Output
External Clock Input to Synchronize Switching
Spread-Spectrum Modulation
•
•
•
•
•
•
•
•
•
3 Description
The LP87702 contains two step-down DC/DC
converters, and a 5-V boost converter to support
safety critical applications. The device integrates two
voltage monitoring inputs for external power supplies
and a window watchdog.
Programmable Start-up and Shutdown Delays and
Sequencing with Enable Signal
•
•
•
•
•
•
Configurable General Purpose Outputs (GPOs)
I2C-Compatible Interface
The automatic PWM/PFM (AUTO mode) operation
gives high efficiency over a wide output current range
for buck converters.
Interrupt Function with Programmable Masking
Output Short-Circuit and Overload Protection
Overtemperature Warning and Protection
Overvoltage Protection (OVP) and Undervoltage
Lockout (UVLO)
This device contains one-time-programmable (OTP)
memory. Each orderable part number has specific
OTP settings for a given application. Details of the
default OTP configuration for each orderable part
number is found in the technical reference manual.
2 Applications
Device Information(1)
•
Building Automation:
PART NUMBER
LP87702
PACKAGE
BODY SIZE (NOM)
– Automated Doors and Gates
– Motion Detector (PIR/Motion Sensor)
– Video Surveillance:
VQFN (32)
5.00 mm × 5.00 mm
(1) See the orderable addendum at the end of the data sheet for
all available packages.
•
Occupancy Detection (People Tracking,
People Counting)
100
90
VIN
VOUT0
VIN_B0
VIN_B1
VANA
SW_B0
FB_B0
LOAD
SW_BST
VOUT1
SW_B1
FB_B1
LOAD
80
NRST
SDA (EN3)
SCL (EN2)
nINT
70
VOUT2
EN1
VOUT_BST
LOAD
CLKIN (GPO2/WD_DIS)
60
PG0
PG1 (GPO1)
GPO0
VIN=3.3V, VOUT=1.2V
VIN=3.3V, VOUT=1.8V
VIN=3.3V, VOUT=2.3V
VMON1
VMON2
WDI
WD_RESET
50
GNDs
1
10
100
Output Current (mA)
1000 5000
Exce
Copyright © 2017, Texas Instruments Incorporated
Buck Efficiency vs Output Current
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP87702
SNVSBU3 – MARCH 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 I2C Serial Bus Timing Parameters............................ 12
6.7 Typical Characteristics..............................................14
7 Detailed Description......................................................15
7.1 Overview...................................................................15
7.2 Functional Block Diagram.........................................16
7.3 Feature Descriptions.................................................16
7.4 Device Functional Modes..........................................39
7.5 Programming............................................................ 41
7.6 Register Maps...........................................................44
8 Application and Implementation..................................78
8.1 Application Information............................................. 78
8.2 Typical Application.................................................... 78
9 Power Supply Recommendations................................87
10 Layout...........................................................................87
10.1 Layout Guidelines................................................... 87
10.2 Layout Example...................................................... 88
11 Device and Documentation Support..........................89
11.1 Third-Party Products Disclaimer............................. 89
11.2 Receiving Notification of Documentation Updates..89
11.3 Support Resources................................................. 89
11.5 Electrostatic Discharge Caution..............................89
11.6 Glossary..................................................................89
12 Mechanical, Packaging, and Orderable
Information.................................................................... 89
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
March 2021
*
Initial Release
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5 Pin Configuration and Functions
24
23
22
21
20
19
18
17
SW_B0
SW_B0
VIN_B0
VIN_B0
PG0
SW_B1
SW_B1
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VIN_B1
VIN_B1
THERMAL PAD
GPO0
VMON1
VMON2
PG1 (GPO1)
NRST
PGND_BST
SW_BST
1
2
3
4
5
6
7
8
Figure 5-1. RHB Package 32-Pin VQFN With Thermal Pad Top View
Table 5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
AGND
CLKIN
EN1
NUMBER
4
22
19
2
G
Ground
D/I/O External clock input. Alternative function is general purpose digital output 2 (GPO2).
D/I
A
Programmable Enable 1 signal.
FB_B0
FB_B1
GPO0
nINT
Output voltage feedback for Buck0.
Output voltage feedback for Buck1.
General purpose digital output 0.
Open-drain interrupt output. Active LOW.
Reset signal for the device.
3
A
12
1
D/O
D/O
D/I
D/O
NRST
PG0
11
29
Programmable power-good indication signal.
Programmable power-good indication signal. Alternative function is general purpose digital output
1 (GPO1).
PG1
32
D/O
PGND_B0
PGND_B1
PGND_BST
23, 24
17, 18
10
P/G
P/G
P/G
Power ground for Buck0.
Power Ground for Buck1.
Power ground for boost.
Serial interface clock input for I2C access. Connect a pullup resistor. Alternative function is
programmable to the enable 2 signal.
SCL
SDA
20
21
D/I
Serial interface data input and output for I2C access. Connect a pullup resistor. Alternative
function is programmable to the enable 3 signal.
D/I/O
SW_B0
SW_B1
SW_BST
VANA
25, 26
P/O
P/O
P/I
P
Buck0 switch node.
15, 16
Buck1 switch node.
9
5
Boost input.
Supply voltage for analog and digital blocks. Must be connected to same node with VIN_Bx.
Voltage monitoring input 1.
VMON1
30
A/I
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Table 5-1. Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NAME
NUMBER
VMON2
31
A/I
P/I
Voltage monitoring input 2.
Input for Buck0. The separate power pins VIN_Bx are not connected together internally – VIN_Bx
pins must be connected together in the application and be locally bypassed.
VIN_B0
VIN_B1
27, 28
Input for Buck1. The separate power pins VIN_Bx are not connected together internally – VIN_Bx
pins must be connected together in the application and be locally bypassed.
13, 14
P/I
VOUT_BST
WD_RESET
WDI
8
6
P/O
D/O
D/I
G
Boost output.
Reset output from window watchdog
Digital input signal for window watchdog
7
Thermal pad
N/A
A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
UNIT
VIN_B0,
Voltage on input power connections
–0.3
6
VIN_B1, SW_BST,
VANA
V
SW_B0, SW_B1
FB_B0, FB_B1
VOUT_BST
Voltage on buck switch nodes
Voltage on buck voltage sense nodes
Voltage on boost output
–0.3
–0.3
(VIN_Bx + 0.3 V) with
6-V maximum
V
(VANA + 0.3 V) with
6-V maximum
V
V
V
V
–0.3
–0.3
6
SCL (EN2), SDA (EN3), Voltage on voltage monitoring pins
VMON1, VMON2
(VANA + 0.3 V) with
6-V maximum
NRST, EN1, nINT
Voltage on logic pins (input or output pins)
Voltage on logic pins (input or output pins)
–0.3
–0.3
6
PG0, PG1 (GPO1),
GPO0, CLKIN (GPO2),
WDI, WD_RESET
(VANA + 0.3 V) with
6-V maximum
V
TJ-MAX
Tstg
Junction temperature
Storage temperature
−40
–65
150
150
260
°C
°C
°C
Maximum lead temperature (soldering, 10 sec.)
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to network ground.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
All pins
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC
Corner pins (1, 8, 9, 16, 17,
24, 25, 32)
Q100-011
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
INPUT VOLTAGE
VIN_B0, VIN_B1, SW_BST, VANA
VMON1, VMON2
Voltage on input power connections
Voltage on voltage monitoring pins
Voltage on logic pins (input or output pins)
2.8
0
5.5
5.5
5.5
V
V
NRST, EN1, EN2, EN3, nINT
0
PG0, PG1 (GPO1), GPO0, CLKIN
(GPO2), WDI, WD_RESET
Voltage on logic pins (input or output pins)
0
VANA
1.95
V
V
V
Voltage on I2C interface, Standard (100 kHz), Fast
(400 kHz), Fast+ (1 MHz), and High-Speed (3.4
MHz) Modes
0
0
SCL, SDA
Voltage on I2C interface, Standard (100 kHz), Fast
(400 kHz), and Fast+ (1 MHz) Modes
VANA with 3.6-V
maximum
TEMPERATURE
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over operating free-air temperature range (unless otherwise noted)
MIN
−40
−40
MAX
140
UNIT
°C
Junction temperature, TJ
Ambient temperature, TA
125
°C
6.4 Thermal Information
RHB (VQFN)
THERMAL METRIC(1)
UNIT
32 PINS
31.7
17.1
5.6
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
5.6
RθJCbot
1.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Limits apply over the junction temperature range –40°C ≤ TJ ≤ 140°C, specified VVANA, VVIN_Bx, VVOUT_Bx, VVOUT_BST, and
IOUT range, unless otherwise noted. Typical values are at TA = 25°C, VVANA = VVIN_Bx = 3.3 V, VOUT_BST = 5 V and VOUT_Bx
=
1 V, unless otherwise noted. (1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
EXTERNAL COMPONENTS
Input filtering capacitance Effective capacitance, connected from
CIN_BUCK
1.9
15
10
22
µF
for buck converters
VIN_Bx to PGND_Bx
Output filtering
capacitance for buck
converters
COUT_BUC
Effective total capacitance. Maximum
includes POL capacitance
100
µF
µF
µF
K
Point-of-load (POL)
capacitance for buck
converters
COUT_BUC
Optional POL capacitance
Effective capacitance
22
22
K_POL
Output filtering
COUT_BST capacitance for boost
converter
10
40
10
Input and output
ESRC
[1-10] MHz
2
mΩ
µH
capacitor ESR
0.47
Inductor for buck
LBUCK
Inductance of the inductor
converters
–30%
–30%
30%
30%
Inductance of the inductor, 2-MHz switching
Inductance of the inductor, 4-MHz switching
Inductance of the inductor
1
1
Inductor for boost
converters
LBST
µH
DCRL
BUCK CONVERTERS
V(VIN_Bx)
V(VANA)
Inductor DCR
25
mΩ
,
Input voltage range
2.8
0.7
3.3
5.5
V
V
Programmable voltage range
Step size, 0.7 V ≤ VOUT < 0.73 V
Step size, 0.73 V ≤ VOUT < 1.4 V
Step size, 1.4 V ≤ VOUT ≤ 3.36 V
Output current
1
10
5
3.36
VOUT_Bx Output voltage
mV
A
20
IOUT_Bx
Output current
3.5 (3)
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Limits apply over the junction temperature range –40°C ≤ TJ ≤ 140°C, specified VVANA, VVIN_Bx, VVOUT_Bx, VVOUT_BST, and
IOUT range, unless otherwise noted. Typical values are at TA = 25°C, VVANA = VVIN_Bx = 3.3 V, VOUT_BST = 5 V and VOUT_Bx
1 V, unless otherwise noted. (1) (2)
=
PARAMETER
TEST CONDITIONS
V(VIN_Bx) – VOUT, IOUT_Bx ≤ 2 A
V(VIN_Bx) – VOUT, IOUT_Bx > 2 A
MIN
0.8
1
TYP
MAX UNIT
Minimum voltage
difference between
V(VIN_Bx) and VOUT_Bx for
electrical characteristics
V
DC output voltage
accuracy, includes
voltage reference, DC
load and line regulations,
process and temperature
Force PWM mode, VOUT ˂ 1.0 V
Force PWM mode, VOUT ≥ 1.0 V
–20
–2%
–20
20
2%
40
mV
mV
PFM mode, VOUT ˂ 1.0 V, the average output
voltage level is increased by max. 20 mV
PFM mode, VOUT ≥ 1.0 V, the average output
voltage level is increased by max. 20 mV
–2%
2% + 20mV
PWM mode, VOUT = 1.2 V, fSW = 4 MHz,
COUT = 22 + 22 µF (GCM31CR71A226KE02)
5
Ripple voltage
mVp-p
%/V
PFM mode, L = 0.47 µH, COUT = 22 + 22 µF
(GCM31CR71A226KE02)
25
±0.05
0.3%
DCLNR
DCLDR
DC line regulation
IOUT = IOUT(max)
DC load regulation in
PWM mode
VOUT_Bx = 1.0 V, IOUT from 0 to IOUT(max)
IOUT = 0 A to 3 A, TR = TF = 1 µs, PWM
mode, VVIN_Bx = 3.3V, VOUT_Bx = 1.2 V, COUT
= 22 + 22 µF, L = 0.47 µH, fSW = 4 MHz
Transient load step
response
TLDSR
±65
±20
mV
mV
V(VIN_Bx) stepping 3 V ↔ 3.5 V, TR = TF = 10
µs, IOUT = IOUT(max)
TLNSR
Transient line response
Programmable range
1.5
4.5
Forward current limit for
both bucks (peak for
every switching cycle)
Step size
0.5
7.5%
7.5%
2
ILIM FWD
A
Accuracy, V(VIN_Bx) ≥ 3 V, ILIM = 4 A
Accuracy, 2.8 V ≤ V(VIN_Bx) < 3 V, ILIM = 4 A
–5%
–20%
1.6
20%
20%
3
ILIM NEG
RDS(ON)
Negative current limit
A
On-resistance, high-side Each phase, between VIN_Bx and SW_Bx
FET
60
55
110
mΩ
BUCK HS
FET
pins (I = 1.0 A)
RDS(ON)
On-resistance, low-side
FET
Each phase, between SW_Bx and PGND_Bx
pins (I = 1.0 A)
80
mΩ
BUCK LS
FET
2-MHz setting or VOUT_Bx < 0.8 V
3-MHz setting and VOUT_Bx ≥ 0.8 V
4-MHz setting and VOUT_Bx ≥ 1.1 V
1.8
2.7
3.6
2
3
4
2.2
Switching frequency,
PWM mode
OTP programmable
ƒSW
3.3 MHz
4.4
From ENx to VOUT_Bx = 0.35 V (slew-rate
control begins)
Start-up time (soft start)
Overshoot during start-up
120
µs
50
mV
Output voltage slew-
rate(4)
SLEW_RATEx[2:0] = 010, VVOUT_Bx ≥ 0.7 V
SLEW_RATEx[2:0] = 011, VVOUT_Bx ≥ 0.7 V
SLEW_RATEx[2:0] = 100, VVOUT_Bx ≥ 0.7 V
SLEW_RATEx[2:0] = 101, VVOUT_Bx ≥ 0.7 V
SLEW_RATEx[2:0] = 110, VVOUT_Bx ≥ 0.7 V
SLEW_RATEx[2:0] = 111, VVOUT_Bx ≥ 0.7 V
–15%
–15%
–15%
–15%
–15%
–15%
10
7.5
15% mV/µs
15% mV/µs
15% mV/µs
15% mV/µs
15% mV/µs
15% mV/µs
Output voltage slew-
rate(4)
Output voltage slew-
rate(4)
3.8
Output voltage slew-
rate(4)
1.9
Output voltage slew-
rate(4)
0.94
0.47
Output voltage slew-
rate(4)
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Limits apply over the junction temperature range –40°C ≤ TJ ≤ 140°C, specified VVANA, VVIN_Bx, VVOUT_Bx, VVOUT_BST, and
IOUT range, unless otherwise noted. Typical values are at TA = 25°C, VVANA = VVIN_Bx = 3.3 V, VOUT_BST = 5 V and VOUT_Bx
1 V, unless otherwise noted. (1) (2)
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
PFM-to-PWM switch -
current threshold(5)
IPFM-PWM
IPWM-PFM
520
mA
mA
Ω
PWM-to-PFM switch -
current threshold(5)
240
125
Output pull-down
resistance
Converter disabled
75
175
BOOST CONVERTER
Input voltage range for
2.8
4.5
3.3
4
V
V
boost power inputs
VIN_BST
Input voltage range when
bypass switch mode
selected
5.5
BOOST_VSET = 00
4.9
5.0
5.1
5.2
BOOST_VSET = 01
Output voltage, boost
mode
VOUT_BST
V
BOOST_VSET = 10
BOOST_VSET = 11
IOUT_BST Output current
Both boost and bypass mode
BOOST_ILIM = 00, VIN_BST < 3.6 V
BOOST_ILIM = 01, VIN_BST < 3.6 V
BOOST_ILIM = 10, VIN_BST < 3.6 V
BOOST_ILIM = 11, VIN_BST < 3.6 V
0.6
1.3
1.9
2.3
3.4
A
A
ILIM_BST
Output current limit
0.8
1.1
1.5
2.2
1
1.4
1.9
2.8
DC output voltage
accuracy, includes
VOUT_BST voltage reference, DC
Default output voltage
Iout = 250 mA
–3%
3%
83
load and line regulations,
_DC
process and temperature.
Boost mode
VDROP
Voltage drop, bypass
mode,
mV
Ripple voltage, boost
mode
22 µF effective output capacitance
IOUT = 1 mA to IOUT(max)
20
mVp-p
DC load regulation, boost
mode
DCLDR
TLDSR
0.3%
Transient load step
response, boost mode
IOUT = 1 mA to 250 mA, TR = TF = 1 µs, 22
µF effective output capacitance, VIN > 3 V
–220
220
mV
mA
During start-up, both boost and bypass
mode. Short circuit current limit applies until
VOUT_BST = VIN_BST
Short circuit current
limitation
ISHORT
625
RDS(ON)
On-resistance, high-side Pin-to-pin, between SW_BST and
145
90
220
175
mΩ
mΩ
FET
VOUT_BST pins (I = 250 mA)
BST HS FET
RDS(ON)
On-resistance, low-side
FET
Pin-to-pin, between SW_BST and
PGND_BST pins (I = 250 mA)
BST LS FET
2-MHz setting
4-MHz setting
1.8
3.6
2
4
2.2 MHz
4.4 MHz
Switching frequency,
boost mode
ƒSW
From enable to boost VOUT within 3% of
target value. COUT_BST = 22 µF
Start-up time, boost mode
450
135
µs
Ω
Output pull-down
resistance
Converter disabled
EXTERNAL CLOCK AND PLL
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Limits apply over the junction temperature range –40°C ≤ TJ ≤ 140°C, specified VVANA, VVIN_Bx, VVOUT_Bx, VVOUT_BST, and
IOUT range, unless otherwise noted. Typical values are at TA = 25°C, VVANA = VVIN_Bx = 3.3 V, VOUT_BST = 5 V and VOUT_Bx
1 V, unless otherwise noted. (1) (2)
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Nominal frequency
1
24
MHz
µs
External input clock(6)
Nominal frequency step size
1
Required accuracy from nominal frequency
–30%
10%
1.8
Delay for detecting loss of external clock,
nominal internal clock, clock accuracy ±10%
External clock detection
Delay for detecting valid external clock,
nominal internal clock, clock accuracy ±10%
20
Clock change delay
(internal to external)
Delay from valid clock detection to use of
external clock
600
300
µs
PLL output clock jitter
Cycle to cycle
ps, p-p
MONITORING FUNCTIONS
Voltage threshold, VANA_THRESHOLD = 0
Voltage threshold, VANA_THRESHOLD = 1
3.3
5.0
V
VANA Voltage Monitoring Voltage window, VANA_WINDOW = 00
Voltage window, VANA_WINDOW = 01
Voltage window, VANA_WINDOW = 10 or 11
VMONx_THRESHOLD = 000
±3%
±4%
±9%
±4%
±5%
±10%
0.65
0.8
±5%
±6%
±11%
VMONx_THRESHOLD = 001
VMONx_THRESHOLD = 010
1.0
VMON1 and VMON2
Voltage Monitoring
VMONx_THRESHOLD = 100
Thresholds
VMONx_THRESHOLD = 011
1.1
V
1.2
VMONx_THRESHOLD = 101
VMONx_THRESHOLD = 110
VMONx_THRESHOLD = 111
1.3
1.8
1.8
VMONx_WINDOW = 00,
VMONx_THRESHOLD from 000 to 111
±1%
±2%
±3%
±2%
±3%
±4%
±5%
VMONx_WINDOW = 01,
VMONx_THRESHOLD from 000 to 111
±3%
±4%
VMON1 and VMON2
Voltage Monitoring
VMONx_WINDOW = 10,
Windows
VMONx_THRESHOLD from 000 to 111
VMONx_WINDOW = 11,
VMONx_THRESHOLD from 000 to 111
±5%
±6%
±7%
BUCKx_WINDOW = 00
±20
±37
±30
±50
±40
±63
BUCKx_WINDOW = 01
BUCKx_WINDOW = 10
BUCKx_WINDOW = 11
BOOST_WINDOW = 00
BOOST_WINDOW = 01
BOOST_WINDOW = 10
BOOST_WINDOW = 11
VANA, VMONx and BOOST monitoring
BUCKx monitoring
Buck0 and Buck1 Voltage
Monitoring Windows
mV
±57
±70
±83
±77
±90
±103
±3.4%
±5.4%
±7.4%
±9.4%
17
±0.6%
±2.6%
±4.6%
±6.6%
12
±2%
±4%
±6%
±8%
Boost Voltage Monitoring
Deglitch time
μs
°C
6
9
PROTECTION FUNCTIONS
Temperature rising, TDIE_WARN_LEVEL = 0
Temperature rising, TDIE_WARN_LEVEL = 1
Hysteresis
115
130
125
140
20
135
150
Thermal warning
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Limits apply over the junction temperature range –40°C ≤ TJ ≤ 140°C, specified VVANA, VVIN_Bx, VVOUT_Bx, VVOUT_BST, and
IOUT range, unless otherwise noted. Typical values are at TA = 25°C, VVANA = VVIN_Bx = 3.3 V, VOUT_BST = 5 V and VOUT_Bx
1 V, unless otherwise noted. (1) (2)
=
PARAMETER
TEST CONDITIONS
MIN
TYP
150
20
MAX UNIT
Temperature rising
140
160
Thermal shutdown
°C
V
Hysteresis
Voltage rising, VANA_OVP_SEL = 0
Voltage falling, VANA_OVP_SEL = 0
Voltage rising, VANA_OVP_SEL = 1
Voltage falling, VANA_OVP_SEL = 1
Hysteresis
5.6
5.45
4.1
5.8
6.1
5.96
4.6
5.73
4.3
VANAOVP VANA Overvoltage
VANAUVL VANA Undervoltage
3.95
40
4.23
4.46
200
2.75
2.7
mV
V
Voltage rising
2.51
2.5
2.63
2.6
Lockout
O
Voltage falling
BUCKx short circuit
detection
Threshold
0.32
0.35
0.45
V
Bypass short circuit
current limit
270
420
mA
LOAD CURRENT MEASUREMENT FOR BUCK CONVERTERS
Current corresponding to maximum output
code (note: maximum current for LP87702
buck is 3.5A)
Current measurement
range
10.22
A
Resolution
LSB
20
mA
Measurement accuracy
IOUT > 1A
<10%
Auto mode (automatically changing to PWM
mode for the measurement)
50
Measurement time
µs
PWM mode
25
CURRENT CONSUMPTION
Shutdown current
consumption
NRST = 0
1
9
µA
µA
Standby current
consumption, converters NRST = 1
disabled
Active current
consumption, one buck
converter enabled in
Auto mode, internal RC
oscillator
IOUT_Bx = 0 mA, not switching
55
90
µA
µA
Active current
consumption, two buck
converters enabled in
Auto mode, internal RC
oscillator
IOUT_Bx = 0 mA, not switching
Active current
consumption during PWM
operation, one buck
converter enabled
IOUT_Bx = 0 mA
15
27
mA
mA
Active current
consumption during PWM
operation, two buck
converters enabled
IOUT_Bx = 0 mA
Active current
consumption, Boost
converter in PWM
operation
IOUT_BST = 0 mA, fSW = 4 MHz
18
2
mA
mA
PLL and clock detector
current consumption
Additional current consumption when
enabled, 2 MHz external clock
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Limits apply over the junction temperature range –40°C ≤ TJ ≤ 140°C, specified VVANA, VVIN_Bx, VVOUT_Bx, VVOUT_BST, and
IOUT range, unless otherwise noted. Typical values are at TA = 25°C, VVANA = VVIN_Bx = 3.3 V, VOUT_BST = 5 V and VOUT_Bx
1 V, unless otherwise noted. (1) (2)
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DIGITAL INPUT SIGNALS SCL, SDA, NRST, EN1, EN2, EN3, CLKIN,
WDI
VIL
VIH
Input low level
Input high level
0.4
V
1.2
10
Hysteresis of Schmitt
Trigger inputs
VHYS
80
500
500
200
mV
kΩ
kΩ
ENx, CLKIN, WDI pull-
down resistance
ENx_PD = 1, CLKIN_PD = 1, WDI_PD = 1
Always enabled
NRST pull-down
resistance
DIGITAL OUTPUT SIGNALS nINT, SDA
SDA: ISOURCE = 20 mA
nINT: ISOURCE = 2 mA
0.5
0.4
VOL
RP
Output low level
V
External pull-up resistor
for nINT
To VIO Supply
10
kΩ
DIGITAL OUTPUT SIGNALS PGOOD, PG1, GPO0, GPO1, GPO2,
WD_RESET
VOL
VOH
Output low level
ISOURCE = 2 mA
ISINK = 2 mA
0.4
Output high level,
configured to push-pull
VVANA - 0.4
VVANA
V
Supply voltage for
VPU
external pull-up resistor,
configured to open-drain
VVANA
External pull-up resistor,
configured to open-drain
RPU
10
kΩ
ALL DIGITAL INPUTS
All logic inputs except NRST, over pin voltage
range, when PD not enabled
−1
–1
1
µA
µA
ILEAK
Input current
NRST, over pin voltage range. Other logic
inputs when PD enabled.
20
(1) All voltage values are with respect to network ground.
(2) Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis.
(3) The maximum output current can be limited by the forward current limit ILIM FWD. The maximum output current is also limited by
the junction temperature and maximum average current over lifetime. The power dissipation inside the die increases the junction
temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient temperature.
(4) The slew-rate can be limited by the current limit (forward or negative current limit), output capacitance and load current. Applies when
internal oscillator is used.
(5) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependant on the output voltage, input voltage and
the inductor current level.
(6) The external clock frequency must be selected so that buck switching frequency is above 1.7 MHz.
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6.6 I2C Serial Bus Timing Parameters
See (1)
.
MIN
MAX
100
400
1
UNIT
Standard mode
kHz
Fast mode
fSCL
Serial clock frequency
Fast mode +
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
3.4
1.7
MHz
4.7
1.3
0.5
160
320
4
Fast mode
µs
ns
µs
ns
tLOW
SCL low time
Fast mode +
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
Fast mode
0.6
0.26
60
tHIGH
SCL high time
Data setup time
Data hold time
Fast mode +
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
120
250
100
50
Fast mode
tSU;DAT
tHD;DAT
tSU;STA
ns
Fast mode +
High-speed mode
Standard mode
10
0.01
0.01
0.01
10
3.45
0.9
Fast mode
µs
ns
Fast mode +
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
70
10
150
4.7
0.6
0.26
160
4
Fast mode
µs
ns
µs
ns
µs
Setup time for a start or a
repeated start condition
Fast mode +
High-speed mode
Standard mode
Fast mode
0.6
0.26
160
4.7
1.3
0.5
4
Hold time for a start or a
repeated start condition
tHD;STA
Fast mode +
High-speed mode
Standard Mode
Bus free time between a stop
and start condition
tBUF
Fast Mode
Fast mode +
Standard Mode
Fast Mode
0.6
0.26
160
µs
ns
tSU;STO
Setup time for a stop condition
Fast mode +
High-speed mode
Standard mode
1000
300
120
80
Fast mode
20+0.1 Cb
trDA
Rise time of SDA signal
Fast mode +
ns
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
10
20
160
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See (1)
.
MIN
MAX
250
250
120
80
UNIT
Standard mode
Fast mode
20+0.1 Cb
20+0.1 Cb
10
tfDA
Fall time of SDA signal
Fast mode +
ns
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
20
160
1000
300
120
40
Fast mode
20+0.1 Cb
trCL
trCL1
tfCL
Rise time of SCL signal
Fast mode +
ns
ns
ns
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
10
20
80
1000
300
120
80
Fast mode
20+0.1 Cb
Rise time of SCL signal after
a repeated start condition and
after an acknowledge bit
Fast mode +
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
10
20
160
300
300
120
40
Fast mode
20+0.1 Cb
20+0.1 Cb
10
Fall time of a SCL signal
Fast mode +
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
20
80
Capacitive load for each bus
line (SCL and SDA)
Cb
400
50
pF
ns
Pulse width of spike
suppressed (Spikes shorter
than indicated width are
suppressed)
Fast mode, Fast mode +
High-speed mode
tSP
10
(1) Cb refers to the capacitance of one bus line. Cb is expressed in pF units.
tBUF
SDA
tHD;STA
trCL
tfDA
trDA
tSP
tLOW
tfCL
SCL
tHD;STA
tSU;STA
tSU;STO
tHIGH
tHD;DAT
S
tSU;DAT
S
RS
P
START
REPEATED
START
STOP
START
Figure 6-1. I2C Timing
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6.7 Typical Characteristics
Unless otherwise specified: VIN = 3.3 V, TA = 25°C, ƒSW -setting 4 MHz, L0 = L1 = 0.47 µH (TOKO
DFE252012PD-R47M), L2 = 1 µH (TFM252012ALMA1R0), COUT_BUCK = 22 µF, and CPOL_BUCK = 22 µF,
COUT_BOOST = 22 µF. Measurements are done using connections in the Figure 8-1.
4
3.5
3
30
25
20
15
10
5
2.5
2
1.5
1
0.5
0
0
2.8
3.1
3.4
3.7
4 4.3
Input Voltage (V)
4.6
4.9
5.2
5.5
2.8
3.1
3.4
3.7
4
4.3
Input Voltage (V)
Regulators disabled
4.6
4.9
5.2
5.5
D016
D015
V(NRST) = 0 V
V(NRST) = 1.8 V
Figure 6-2. Shutdown Current Consumption vs
Input Voltage
Figure 6-3. Standby Current Consumption vs Input
Voltage
90
85
80
75
70
65
60
55
50
45
40
50
45
40
35
30
25
20
15
10
5
0
2.8
3.1
3.4
3.7
4
4.3
Input Voltage (V)
Load = 0 mA
4.6
4.9
5.2
5.5
2.8
3.1
3.4
3.7
4
4.3
Input Voltage (V)
Load = 0 mA
4.6
4.9
5.2
5.5
D013
D012
VOUT = 1.2 V
VOUT = 1.2 V
Figure 6-4. Active State Current Consumption vs
Input Voltage, One Buck Converter Enabled in PFM
Mode
Figure 6-5. Active State Current Consumption vs
Input Voltage, One Buck Converter Enabled in
PWM Mode
50
45
40
35
30
25
20
15
10
5
0
2.8
3
3.2
3.4
Input Voltage (V)
Load = 0 mA
3.6
3.8
4
D014
VOUT = 5.0 V
Figure 6-6. Active State Current Consumption vs Input Voltage, Boost Converter Enabled in PWM Mode
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7 Detailed Description
7.1 Overview
The LP87702 is a high-efficiency, high-performance power supply IC with two step-down DC/DC converters
(Buck0 and Buck1) and boost converter for automotive and industrial applications. The input voltage range is
from 2.8 V to 5.5 V. The typical application input voltage levels are 3.3 V and 5 V. VANAOVP is set to 4.3 V
(typical) with 3.3 V input and boost enabled. The boost can be used as a load switch and VANAOVP is set to 5.8
V (typical) when input voltage is 5 V. VANAOVP is selected in OTP by VANA_OVP_SEL and is a fixed factory
setting. Table 7-1 lists the output characteristics of the various converters.
Table 7-1. Supply Specification
OUTPUT
SUPPLY
VOUT RANGE (V)
RESOLUTION (mV)
IMAX MAXIMUM OUTPUT CURRENT (mA)
Boost
Buck0
4.9 to 5.2
100
600
10 (0.7 V to 0.73 V)
5 (0.73 V to 1.4 V)
20 (1.4 V to 3.36 V)
0.7 to 3.36
0.7 to 3.36
3500
3500
10 (0.7 V to 0.73 V)
5 (0.73 V to 1.4 V)
20 (1.4 V to 3.36 V)
Buck1
The LP87702 converters support switching clock synchronization to an external clock connected to CLKIN input.
The external clock can be from 1 MHz to 24 MHz with 1-MHz steps. Alternatively, optional spread spectrum
mode can be enabled to reduce EMI.
LP87702 features include diagnostics, monitoring, and protections for the devices internal and system level
operation, which are the following:
•
•
•
Soft start
Input undervoltage lockout
Programmable undervoltage or window (overvoltage and undervoltage) monitoring for the input (from VANA
pin)
•
•
Programmable undervoltage or window (overvoltage and undervoltage) monitoring for the buck and boost
converter outputs
Two inputs (VMONx) with programmable undervoltage or window (overvoltage and undervoltage) thresholds,
for monitoring external rails in the system
•
•
•
•
•
•
•
One dedicated power-good output (PG0) to which selected monitoring signals can be combined
Second programmable power-good output (PG1), multiplexed with general purpose output (GPO1)
Power good flags with maskable interrupt
Programmable window watchdog
Buck and boost converter overload detection
Thermal warning with two selectable thresholds
Thermal shutdown
LP87702 control interface:
•
Up to three enable inputs ( EN1, EN2, and EN3) with programmable power-up or power-down sequence
control
•
•
•
•
•
Optional I2C (multiplexed with EN2 and EN3 inputs)
Interrupt signal (nINT) to host
Reset input (NRST)
One dedicated general purpose output (GPO0)
Watchdog disable WD_DIS, multiplexed with CLKIN/GPO2
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7.2 Functional Block Diagram
VANA
Buck0
ILIM Det
Pwrgood
Det
Overload
and SC
nINT
Interrupts
Enable/
Disable,
Delay
Control
Slew-Rate
Control
EN1
Det
Iload ADC
GPO0
Buck1
ILIM Det
Pwrgood
SDA / EN3
SCL / EN2
I2C
Overload
and SC Det
Iload ADC
OTP
EPROM
Registers
Boost
ILIM Det
Pwrgood Det
Digital
Logic
NRST
Overload and
SC Det
Thermal
Monitor
UVLO
Diagnostics
SW
Reset
Ref &
Bias
PG0
Ref &
Bias
Oscillator
PG1/ GPO1
CLKIN / GPO2/ WD_DIS
Window
Watchdog
WD_RESET
VMON1
VMON2
WDI
7.3 Feature Descriptions
7.3.1 Step-Down DC/DC Converters
7.3.1.1 Overview
The LP87702 includes two high-efficiency step-down DC/DC converters. The buck converters deliver 0.7-V
to 3.36-V regulated voltage rails from 2.8-V to 5.5-V input-supply voltage. The converters are designed for
flexibility; most of the functions are programmable, thus optimizing the converter operation for each application:
•
•
•
•
•
•
•
•
•
•
DVS support with programmable slew rate
Automatic mode control based on the loading (PWM or PFM mode)
Forced PWM mode option
Optional external clock input to minimize crosstalk
Optional spread spectrum technique to reduce EMI
Synchronous rectification
Current mode loop with PI compensator
Soft start
Programmable output voltage monitoring with maskable interrupt and selectable connection PG0 or PG1
Average output current sensing (for PFM entry and load current measurement)
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Some of the key parameters that can be programmed through the registers (with default values set by OTP bits):
•
•
•
•
•
Output voltage
Forced PWM operation
Switch current limit
Output voltage slew rate
Enable and disable delays with ENx pin control
There are two modes of operation for the buck converters, depending on the output current required: pulse width
modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load
currents of approximately 520 mA or higher. Lighter output current loads will cause the converter to automatically
switch into PFM mode for reduced current consumption when forced PWM mode is disabled. The forced PWM
mode can be selected to maintain fixed switching frequency at all load currents. When buck is disabled, buck
output is isolated from the input voltage rail. Output has an optional pulldown resistor.
Figure 7-1 shows a block diagram of a single buck converter.
HS FET
CURRENT
SENSE
VIN
FB
POS
CURRENT
LIMIT
RAMP
GENERATOR
V
OUT
-
GATE
CONTROL
ERROR
AMP
SW
+
LOOP
COMP
VOLTAGE
SETTING
SLEW RATE
CONTROL
NEG
CURRENT
LIMIT
POWER
GOOD
+
-
VDAC
ZERO
CROSS
DETECT
LS FET
CURRENT
SENSE
CONTROL
BLOCK
PROGRAMMABLE
PARAMETERS
IADC
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 7-1. Detailed Block Diagram Showing One Buck Converter
7.3.1.2 Transition Between PWM and PFM Modes
The LP87702 buck converter operates in PWM mode at load current of about 520 mA or higher. The device
automatically switches into PFM mode for reduced current consumption when forced PWM mode is disabled
(AUTO mode operation) at lighter load current levels. A high efficiency is achieved over a wide output-load
current range by combining the PFM and the PWM modes.
7.3.1.3 Buck Converter Load Current Measurement
Buck load current can be monitored through the I2C registers. The monitored buck converter is selected
with the LOAD_CURRENT_BUCK_SELECT bit in the SEL_I_LOAD register. A write to this selection register
starts a current measurement sequence. The converter is forced to PWM mode during the measurement. The
measurement sequence is 50 µs long at maximum. LP87702 can be configured to give out an I_MEAS_INT
interrupt in the INT_TOP_1 register after the load current measurement sequence is finished. Load current
measurement interrupt can be masked with I_MEAS_MASK bit in TOP_MASK_1 register. The measurement
result can be read from I_LOAD_1 and I_LOAD_2 registers. The buck converter load current measurement
result is 9-bit wide, with 8 LSB bits stored in I_LOAD_1 register and 1 MSB bit stored in I_LOAD_2 register. The
single bit resolution is 20 mA, with a maximum load current value of 10.22 A.
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7.3.2 Boost Converter
The LP87702 device integrates a boost converter with programmable output voltage from 4.9 V to 5.2 V in 0.1
V steps, and input voltage range from 2.8 V to 4 V. The boost converter has flexibility to support wide range of
application conditions:
•
•
•
•
•
•
•
Forced PWM operation
Optional external clock input to minimize crosstalk
Optional spread spectrum technique to reduce EMI
Synchronous rectification
Current mode loop with PI compensator
Soft start
Programmable output voltage monitoring with maskable interrupt and selectable connection to PG0 and PG1
or both
The following parameters can be programmed through the registers, with default values set by the OTP bits
(unless otherwise noted):
•
•
•
•
Output voltage level (BOOST_VSET)
Switch current limit (BOOST_ILIM)
Enable and disable delays when ENx pin control is used (BOOST_DELAY register)
Output pulldown resistor enable or disable when boost is disabled (BOOST_RDIS_EN bit, discharge is
enabled by default)
•
Output voltage monitoring enable or disable and monitoring window thresholds
The boost converter operates in forced PWM mode with fixed switching frequency across all load currents.
When boost is disabled, boost output is isolated from the input voltage rail.
Boost converter supports an alternative operating mode as a bypass or load switch, with input voltage range
from 4.5 V to 5.5 V. Operating mode is selected in OTP and is fixed; changing the mode on-the-fly is not
supported.
7.3.3 Spread-Spectrum Mode
Systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband
frequencies (the switching frequency and its harmonics). The usual solution to reduce noise coupling is to add
EMI-filters and shields to the boards. The LP87702 device supports the spread-spectrum switching frequency
modulation mode that is register controlled. This mode minimizes the need for output filters, ferrite beads, or
chokes. The switching frequency varies between 0.85 × fSW and fSW in spread spectrum mode, where fSW is
switching the frequency selected in the OTP. Figure 7-2 shows how the spread spectrum modulation reduces
conducted and radiated emissions by the converter and associated passive components and PCB traces. This
feature is available only when internal RC oscillator is used (EN_PLL is 0 in PLL_CTRL register) and it is
enabled with the EN_SPREAD_SPEC bit in CONFIG register, and it affects both buck converters and the boost
converter.
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Frequency
Where a fixed frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread spectrum
architecture of the LP87702 spreads that energy over a large bandwidth.
Figure 7-2. Spread Spectrum Modulation
7.3.4 Sync Clock Functionality
The LP87702 device contains a CLKIN input to synchronize buck and boost converters' switching clock with
the external clock. Figure 7-3 shows the block diagram of the clocking and PLL module. Table 7-2 shows how
the external clock is selected and interrupt is generated depending on the EN_PLL bit in PLL_CTRL register
and the external clock availability. The interrupt can be masked with SYNC_CLK_MASK bit in TOP_MASK_1
register. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[4:0] bits in PLL_CTRL
register and it can be from 1 MHz to 24 MHz with 1-MHz steps. The external clock must be inside accuracy limits
(–30%/+10%) for valid clock detection.
The SYNC_CLK_INT interrupt in INT_TOP_1 register is also generated in cases the external clock is expected
but it is not available. These cases are Startup (Read OTP-to-standby transition) when EN_PLL = 1 and buck or
boost converter is enabled (standby-to-active transition) when EN_PLL = 1.
24 MHz
RC
Oscillator
Internal
24 MHz
clock
CLKIN
Detector
Divider
“EXT_CLK
_FREQ“
Clock Select
Logic
1 MHz
CLKIN
24 MHz
PLL
“EN_PLL“
1 MHz
Divider
24
Figure 7-3. Clock and PLL Module
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Table 7-2. PLL Operation
DEVICE
OPERATION MODE
PLL AND CLOCK
DETECTOR STATE
INTERRUPT FOR
EXTERNAL CLOCK
EN_PLL
CLOCK
STANDBY
ACTIVE
0
0
Disabled
Disabled
No
No
Internal RC
Internal RC
Automatic change to internal
RC oscillator when External
clock is not available
When external clock
disappears or appears
STANDBY
ACTIVE
1
1
Enabled
Enabled
Automatic change to internal
RC oscillator when External
clock is not available
When external clock
disappears or appears
7.3.5 Power-Up
The power-up sequence for the LP87702 is as follows:
•
•
VANA (and VIN_Bx) reach minimum recommended levels (VVANA > VANAUVLO).
Driving the NRST input high initiates OTP read and enables the system I/O interface. Minimum delay from
the NRST reset input rising edge to I2C write or read access is 1.2 ms.
Device enters STANDBY mode. Watchdog operation starts.
The host can change the default register setting by I2C if needed.
The converters can be enabled or disabled and the GPOx signals can be controlled by ENx pins and by I2C
interface.
•
•
•
7.3.6 Buck and Boost Control
7.3.6.1 Enabling and Disabling Converters
The buck converters can be enabled when the device is in STANDBY or ACTIVE state. There are two ways to
enable and disable the buck converters:
•
Using BUCKx_EN bit in BUCKx_CTRL_1 register (BUCKx_EN_PIN_CTRL bit is 00 in BUCKx_CTRL_1
register)
•
Using ENx control pin (BUCKx_EN bit is 1 in BUCKx_CTRL_1 register and BUCKx_EN_PIN_CTRL bit is not
00 in BUCKx_CTRL_1 register)
Similarly there are two ways to enable and disable the boost converter:
•
•
Using BOOST_EN bit in BOOST_CTRL register (BOOST_EN_PIN_CTRL bit is 0 in BOOST_CTRL register)
Using ENx control pin (BOOST_EN bit is 1 in BOOST_CTRL register and BOOST_EN_PIN_CTRL bit is not
00 in BOOST_CTRL register)
If the ENx control pin is used to enable and disable, then the delay from the control signal rising edge to start-up
is set by BUCKx_STARTUP_DELAY[3:0] bits in BUCKx_DELAY register and BOOST_STARTUP_DELAY[3:0]
bits in BOOST_DELAY register. The delay from falling edge of control signal to shutdown is set by
BUCKx_SHUTDOWN_DELAY[3:0] bits in BUCKx_DELAY register and BOOST_SHUTDOWN_DELAY[3:0] bits
in BOOST_DELAY register. The delays are valid only when ENx pin control is used, not when converters are
enabled by I2C write to BUCKx_EN and BOOST_EN bits.
The control of the converters (with 0-ms delays) is shown in Table 7-3.
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Table 7-3. Converter Control
BUCKx_EN_PIN_C
TRL /
BOOST_EN_PIN_C
TRL
BUCKx_EN /
BOOST_EN
BUCKx OUTPUT VOLTAGE /
BOOST OUTPUT VOLTAGE
EN1 PIN
EN2 PIN
EN3 PIN
Enable or disable
control with BUCKx_EN/
BOOST_EN bit
0
1
Don't Care
00
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Disabled
BUCKx_VSET[7:0] / BOOST_VSET[1:0]
Enable or disable control
with EN1 pin
1
1
1
1
1
1
01
01
10
10
11
11
Low
Don't Care
Don't Care
Low
Don't Care
Don't Care
Don't Care
Don't Care
Low
Disabled
High
BUCKx_VSET[7:0] / BOOST_VSET[1:0]
Disabled
Enable/disable control
with EN2 pin
Don't Care
Don't Care
Don't Care
Don't Care
High
BUCKx_VSET[7:0] / BOOST_VSET[1:0]
Disabled
Enable or disable control
with EN3 pin
Don't Care
Don't Care
High
BUCKx_VSET[7:0] / BOOST_VSET[1:0]
Figure 7-4 shows how the BUCKx converter is enabled by an ENx pin or by I2C write access. The soft-start
circuit limits the in-rush current during start-up. The output voltage increase rate is typically 30 mV/μsec during
soft start. The output voltage becomes slew-rate controlled when the output voltage rises to 0.35-V level. If
there is a short circuit at the output and the output voltage does not increase above a 0.35-V level in 1 ms, the
converter is disabled, and interrupt is set. When the output voltage rises above the undervoltage power-good
threshold level the BUCKx_PG_INT interrupt flag in the INT_BUCK register is set.
Power-good thresholds are defined by BUCKx_WINDOW bits. A PGOOD_WINDOW bit in PGOOD_CTRL
register sets the detection method for the valid buck output voltage, either undervoltage detection
or undervoltage and overvoltage detection. The powergood interrupt flag can be masked using the
BUCKx_PGR_MASK bit in the BUCK_MASK register when reaching the valid output voltage. The power-
good interrupt flag can also be generated when the output voltage becomes invalid. The interrupt mask for
invalid output voltage detection is set by BUCKx_PGF_MASK bit in BUCK_MASK register. When the window
monitoring (under and overvoltage monitoring) is selected, the mask bits apply when voltage is crossing either
threshold. A BUCKx_PG_STAT bit in BUCK_STAT register shows always the validity of the output voltage; '1'
means valid, and '0' means invalid output voltage.
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BUCKx_VSET[7:0]
Voltage decrease because of load
Voltage
BUCKx_WINDOW[1:0]
Ramp
BUCKx_SLEW_RATE[2:0]
0.6V
0.35V
Time
Resistive pull-down
(if enabled)
Soft start
Enable
0
0
0
1
0
0
1
BUCK_STATUS(BUCKx_STAT)
BUCK_STATUS(BUCKx_PG_STAT)
INT_BUCK(BUCKx_PG_INT)
nINT
1
1
0
1
1
0
0 1
0
0
Powergood
interrupts
Host clears
interrupts
BUCK_MASK(BUCKx_PGF_MASK) = 0
BUCK_MASK(BUCKx_PGR_MASK) = 0
Figure 7-4. Buck Converter Enable and Disable
Figure 7-5 shows how the boost converter is enabled by an ENx pin or by I2C write access. The soft-start circuit
limits the in-rush current during start-up. The output voltage increase rate is less than 100 mV/μsec during soft
start. If there is a short circuit at the output and the output voltage does not reach the input voltage level in 1 ms,
the converter is disabled, and the interrupt is set. When the output voltage reaches the power-good threshold
level, the BOOST_PG_INT interrupt flag in INT_BOOST register is set.
Power-good thresholds are defined by BOOST_WINDOW bits. A PGOOD_WINDOW bit in PGOOD_CTRL
register sets the detection method for the valid boost output voltage, either undervoltage detection or
undervoltage and overvoltage detection. The power-good interrupt flag, when reaching valid output voltage, can
be masked using BOOST_PGR_MASK bit in BOOST_MASK register. The power-good interrupt flag can also
be generated when the output voltage becomes invalid. The interrupt mask for invalid output voltage detection
is set by the BOOST_PGF_MASK bit in BOOST_MASK register. A BOOST_PG_STAT bit in the BOOST_STAT
register always shows the validity of the output voltage; '1' means valid and '0' means invalid output voltage.
The ENx input pins have integrated pulldown resistors. The pulldown resistors are enabled by default and host
can disable those with ENx_PD bits in CONFIG register.
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BOOST_VSET[1:0]
Voltage decrease because of load
Voltage
BOOST_WINDOW[1:0]
Resistive pull-down
(if enabled)
Time
Enable
0
0
0
1
0
0
1
BOOST_STATUS(BOOST_STAT)
BOOST_STATUS(BOOST_PG_STAT)
INT_BOOST(BOOST_PG_INT)
nINT
1
0
1
1
1
0
0 1
0
0
Powergood
interrupts
Host clears
interrupts
BOOST_MASK(BOOST_PGF_MASK) = 0
BOOST_MASK(BOOST_PGR_MASK) = 0
Figure 7-5. Boost Converter Enable and Disable
7.3.6.2 Changing Buck Output Voltage
The output voltage of BUCKx converter can be changed by writing to the BUCKx_VOUT register. The
voltage change for buck converter is always slew-rate controlled, and the slew-rate is defined by the
BUCKx_SLEW_RATE[2:0] bits in BUCKx_CTRL_2 register. The forced PWM mode is used automatically during
a voltage change. When the programmed output voltage is achieved, the mode becomes the one defined by
load current, and the BUCKx_FPWM bit.
Figure 7-6 shows the voltage change and power-good interrupts.
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Ramp for Buck
BUCKx_CTRL2(BUCKx_SLEW_RATE[2:0])
Voltage
BUCKx_VSET
Powergood
Powergood
Time
1
1
0
BUCK_STATUS(BUCKx_STAT)
BUCK_STATUS(BUCKx_PG_STAT)
INT_BUCK(BUCKx_PG_INT)
0
1
1
0
1
1
0
0
nINT
Powergood
interrupt
Host clears
interrupt
Powergood
interrupt
Host clears
interrupt
BUCK_MASK(BUCKx_PGF_MASK)=0
BUCK_MASK(BUCKx_PGR_MASK)=0
Figure 7-6. Buck Output Voltage Change
7.3.7 Enable and Disable Sequences
The LP87702 device supports programmable start-up and shutdown sequencing. An enable control signal
is used to initiate the start-up sequence and to turn off the device according to the programmed shutdown
sequence. Up to three enable inputs are available: EN1 is a dedicated enable input; EN2 and EN3 are
multiplexed with I2C interface. The buck converter is selected for sequence control with:
•
•
•
•
BUCKx_CTRL_1(BUCKx_EN) = 1
BUCKx_CTRL_1(BUCKx_EN_PIN_CTRL) = 0x1 or 0x2 or 0x3, for EN1 or EN2 or EN3 control, respectively
BUCKx_VOUT.(BUCKx_VSET[7:0]) = Required voltage when EN pin is high
The delay from rising edge of EN pin to the converter enable is set by
BUCKx_DELAY(BUCKx_STARTUP_DELAY[3:0]) bits and
•
The delay from falling edge of EN pin to the converter disable is set by
BUCKx_DELAY(BUCKx_SHUTDOWN_DELAY[3:0])
In the same way the boost converter is selected for delayed control with:
•
•
•
•
BOOST_CTRL(BOOST_EN) = 1
BOOST_CTRL(BOOST_EN_PIN_CTRL) = 0x1 or 0x2 or 0x3, for EN1. EN2, or EN3 control (respectively)
BOOST_CTRL(BOOST_VSET[2:0]) = Required voltage when EN pin is high
The delay from rising edge of EN pin to the converter enable is set by
BOOST_DELAY(BOOST_STARTUP_DELAY[3:0]) bits and
•
The delay from falling edge of EN pin to the converter disable is set by
BOOST_DELAY(BOOST_SHUTDOWN_DELAY[3:0])
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An example of start-up and shutdown sequences for buck converters are shown in Figure 7-7. The start-up and
shutdown delays for Buck0 converter are 1 ms and 4 ms and for Buck1 converter 3 ms and 1 ms. The delay
settings are used only for enable or disable control with the EN signal.
Typical sequence
ENx
Internal
BUCK0 enable
1 ms
4 ms
Internal
BUCK1 enable
3 ms
1 ms
Sequence with short EN low and high periods
ENx
Startup cntr
0
0
0
1
0
1
2
3
4
5
6
0
2
Shutdown cntr
0
1
0
1
0
1
2
3
4
5
Internal
BUCK0 enable
1 ms
4 ms
Internal
BUCK1 enable
3 ms
1 ms
Figure 7-7. Start-up and Shutdown Sequencing Example
7.3.8 Window Watchdog
Figure 7-8 shows the LP87702 watchdog's operation (for an example, when the ENx pin is used for controlling
power sequence and ENx pin is active).
WDI is the watchdog function input pin, and WD_RESET is the reset output. The WDI pin needs pulsed
within a certain timing window to avoid a watchdog expiration. The minimum pulse width is 100 µs. The
watchdog expiration always causes a reset pulse at WD_RESET output, otherwise the device behavior after
watchdog expiration is programmable. WD_RESET output polarity and mode, push-pull or open drain, are also
programmable.
Watchdog default settings are read from OTP during device start-up. Default settings in WD_CTRL_1 and
WD_CTRL_2 register can be over-written through the I2C (as long as WD_LOCK bit is not set to 1). Writing
WD_LOCK = 1 in WD_CTRL_2 register locks watchdog settings until NRST input is driven low, power cycle or
register reset by SW_RESET.
Table 7-4 shows how the long open, close, and open window periods are independently programmable. The
watchdog enters the WD Reset state when the long open or open window expires before the WDI input is
received. Also, the watchdog enters the WD Reset when the WDI is received during close window. Long open
period can be extended by a I2C write to WD_CTRL_1 or WD_CTRL_2 register; the register access initializes
the long open counter and the long open period restarts (except in Stop mode).
LP87702 behavior after WD expiration is programmable:
•
When WD_RESET_CNTR_SEL = 00, system restart is disabled and converters are maintained ON.
WD_RESET pin is active for 10 ms. Watchdog returns to Long Open mode.
•
When WD_RESET_CNTR_SEL = 01 (restart after first reset pulse), LP87702 performs shutdown sequence
followed by start-up sequence so the converters are disabled and re-enabled according to the OTP
programmed sequences. The device reloads OTP defaults when WD_EN_OTP_READ = 1 during start-up.
Settings valid before shutdown are maintained when the WD_EN_OTP_READ = 0. WD_RESET output pin is
active for a period of (10 ms + maximum shutdown delay). Maximum shutdown delay can be selected as 7.5
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ms (SHUTDOWN_DELAY_SEL = 0) or 15 ms (SHUTDOWN_DELAY_SEL = 1). After the restart watchdog
returns to Long Open mode.
•
The status bit (WD_SYSTEM_RESTART_FLAG) is set to indicate that a system restart has happened. The
status can be cleared by writing 1 to WD_CLR_SYSTEM_RESTART_FLAG. WD_RESET_CNTR_SEL can
be set to 10 or 11 to select restart after 2 or 4 WD expirations, respectively. The current status of the
reset counter is available in WD_RESET_CNTR_STATUS. The reset counter can be cleared by writing
WD_CLR_RESET_CNTR to 1.
Watchdog settings in WD_CTRL_1 and WD_CTRL_2 registers are locked by setting the WD_LOCK bit.
WD_SYSTEM_RESTART_FLAG and WD_RESET_CNTR_STATUS can be cleared even if WD_LOCK = 1.
Description above is for a case where ENx pin is used for controlling power sequence and ENx pin is active.
Watchdog behavior can be slightly different depending on the OTP settings and the ENx pin state, which follows:
•
When the ENx pin is used for controlling the power sequence and the ENx pin is not active, the shutdown
sequence cannot be performed. WD_RESET pulse length is fixed 31 ms.
•
There is no OTP defined power sequence when the ENx pins are not used for power sequence control, and
all converters and GPOs are enabled through the I2C. WD expiration does not cause a converter disable
or enable sequence even when the OTP settings for the watchdog enable restart. In this case WD_RESET
pulse is 11 ms.
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NRST low OR
VANA < VANA_UVLO
(WD_SYSTEM_RESTART_FLAG = 0
OR
WD_SYSTEM_RESTART_FLAG_MODE = 0)
AND
Stop
Shutdown
WD_EN_OTP_READ = 1
NRST high AND
VANA > VANA_UVLO
(WD_SYSTEM_RESTART_FLAG = 0
OR
WD_SYSTEM_RESTART_FLAG_MODE = 0)
AND
WD_EN_OTP_READ = 0
Read OTP
WD_SYS_RESTART_FLAG_MODE = 1
WD_EN_OTP_READ = 1
Shutdown
Sequence
WD_RESET output
active for (7.5ms +10ms)
or (15ms+10ms)
Release ENx
pin gating
WD_EN_OTP_READ = 0
Set
WD_SYSTEM_
RESTART_FLAG = 1
Long Open
WD_RESET output
active for 10ms
Restart Enabled AND
Reset Counter >= Counter Select
I2C Writing to WD Control Register
(from all states except Stop)
WDI Rising
Restart Disabled OR
Reset Counter < Counter Select
LongOpenTime Expired
WD Reset
Increase Reset Counter value,
WDI Rising
Close
OpenTime Expired
CloseTime Expired
WDI Rising
Open
Figure 7-8. Watchdog Operation
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Table 7-4. Watchdog Window Periods
CONTROL BIT
DEFAULT
VALUES
00 – 200 ms
01 – 600 ms
10 – 2000 ms
11 – 5000 ms
WD_LONG_OPEN_TIME
OTP
OTP
00 – 10 ms
01 – 20 ms
10 – 50 ms
11 – 100 ms
WD_CLOSE_TIME
7.3.9 Device Reset Scenarios
There are four reset methods implemented on the LP87702:
•
•
•
•
Software reset with the SW_RESET bit in the RESET register
NRST input signal low
Undervoltage lockout (UVLO) reset from VANA supply
Watchdog expiration (depending on the watchdog settings)
A SW reset occurs when the SW_RESET bit is set to 1. The bit is automatically cleared after writing. Figure
7-14shows how this event disables all the converters immediately, drives GPO signals low, resets all the register
bits to the default values and the OTP bits are loaded. I2C interface is not reset during a software reset. The host
must wait at least 1.2 ms after writing SW reset until making a new I2C read or write to the device.
If VANA supply voltage falls below the UVLO threshold level or the NRST signal is set low, then all the
converters are disabled immediately, the GPOx signals are driven low, and all the register bits are reset to the
default values. When the VANA supply voltage rises above the UVLO threshold level and the NRST signal rises
above the threshold level, the OTP bits are loaded to the registers and a start-up is initiated according to the
register settings. The host must wait at least 1.2 ms before reading or writing to the I2C interface.
Depending on the watchdog settings, the watchdog expiration can reset the device to the OTP default values.
7.3.10 Diagnostics and Protection Features
The LP87702 provides four levels of protection features:
•
•
•
Input and output voltage information. Non-valid voltage sets interrupt or PGx signal:
– Validity of the output voltage of BUCK or BOOST converters
– Validity of VANA, VMON1, and VMON2 input voltages
Warnings causing interrupt:
– Peak current limit detection in BUCK or BOOST converters
– Thermal warning
Protection events which are disabling the converters:
– Short-circuit and overload protection for BUCK and BOOST converters
– Input overvoltage protection (VANAOVP
)
– Watchdog expiration (optional, depends on the watchdog settings)
– Thermal shutdown
•
•
Protection events which are causing the device to shutdown:
– Undervoltage lockout (VANAUVLO
)
Protections not causing interrupt or converter disable:
– Negative current limit detection in the BUCK or BOOST converters
7.3.10.1 Voltage Monitorings
The LP87702 device has programmable voltage monitoring for the BUCKx and BOOST converter output
voltages and for VANA, VMON1, and VMON2 inputs. Monitoring of each signal is independently enabled in
the PGOOD_CTRL register. Voltage monitoring can be under-voltage monitoring only (PGOOD_WINDOW =
0) or overvoltage and undervoltage monitoring (PGOOD_WINDOW = 1). This selection is common for all
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enabled monitorings. Section 7.3.10.3describes how the enabled monitoring signals are combined to generate
power-good (PG0 and PG1) and interrupts. Monitoring comparators have a dedicated reference and bias block,
which is independent of the main reference and bias block.
Nominal level for the output voltage of BUCKx converter is set with BUCKx_VSET in the BUCKx_VOUT
register. Overvoltage and undervoltage detection levels, with respect to nominal level, are selected with
BUCKx_WINDOW as ± 30 mV, ± 50 mV, ± 70 mV or ± 90 mV. Nominal level for the output voltage of the
BOOST converter is set with BOOST_VSET in the BOOST_CTRL register. Available levels are 4.9 V, 5 V,
5.1 V, and 5.2 V. Overvoltage and undervoltage detection levels, with respect to nominal level, are selected
with BOOST_WINDOW as ± 2%, ± 4%, ± 6% or ± 8%. Converter monitoring window selection bits are in the
PGOOD_LEVEL_3 register.
Input voltage of LP87702 is monitored at the VANA pin. Nominal level can be selected as 3.3 V or 5 V with the
VANA_THRESHOLD bit. Overvoltage and undervoltage detection levels are selected with VANA_WINDOW as
(nominal). VANA_THRESHOLD and VANA_WINDOW are set in the PGOOD_LEVEL_2 register.
VMON1 and VMON2 inputs can be used for monitoring external rails in the system. VMONx settings are
defined in the PGOOD_LEVEL_1 and PGOOD_LEVEL_2 registers. Nominal value for the input level of VMONx
is selected with VMONx_THRESHOLD, between 0.65 V to 1.8 V. Higher voltage levels or levels not directly
supported can be monitored using an external resistor divider. In this case VMONx_THRESHOLD must be set
as 0.65 V to have a high-impedance input, and the resistor divider must scale the monitored level down to 0.65 V
at the VMONx pin. Overvoltage and undervoltage detection levels are selected with VMONx_WINDOW as ± 2%,
± 3%, ± 4% or ± 6%.
See Section 6 for more details on the accuracy of the monitoring windows and deglitch filtering.
7.3.10.2 Interrupts
The LP87702 sets the flag bits indicating what protection or warning conditions have occurred, and the nINT pin
is pulled low. The nINT output pin is driven high after all the flag bits and pending interrupts are cleared.
Fault detection is indicated by the RESET_REG_INT interrupt flag bit set in the INT_TOP_2 register after the
start-up event.
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Table 7-5. Summary of Interrupt Signals
EVENT
SAFE STATE
INTERRUPT BIT
INTERRUPT MASK
STATUS BIT
RECOVERY/INTERRUPT
CLEAR
Buck current limit
triggered (20-µs
debounce)
No effect
BUCK_INT = 1
BUCKx_ILIM_INT = 1
BUCKx_ILIM_MASK
BUCKx_ILIM_STAT
Write 1 to the
BUCKx_ILIM_INT bit
Interrupt is not cleared if the
current limit is active.
Boost current limit
triggered
No effect
BOOST_INT = 1
BOOST_ILIM_INT = 1
BOOST_ILIM_MASK
BOOST_ILIM_STAT
N/A
Write 1 to the
BOOST_ILIM_INT bit.
Interrupt is not cleared if the
current limit is active.
Buck short circuit
(VVOUT < 0.35V at
1 ms after enable)
or Overload (VVOUT
decreasing below 0.35
V during operation, 1 ms
debounce)
Converter disable
BUCKx_INT = 1
BUCKx_SC_INT = 1
N/A
Write 1 to the BUCKx_SC_INT
bit.
Boost short circuit
Converter disable
No effect
BOOST_INT = 1
BOOST_SC_INT = 1
N/A
N/A
Write 1 to the BOOST_SC_INT
bit.
Thermal warning
TDIE_WARN_INT) = 1
TDIE_WARN_MASK
TDIE_WARN_STAT
Write 1 to the
TDIE_WARN_INT bit.
Interrupt is not cleared if
the temperature is above the
thermal warning level.
Thermal shutdown
VANA overvoltage
All converters disabled
immediately and GPOx
set to low
TDIE_SD_INT = 1
OVP_INT
N/A
N/A
TDIE_SD_STAT
OVP_STAT
Write 1 to TDIE_SD_INT bit
Interrupt is not cleared if
temperature is above thermal
shutdown level
All converters disabled
immediately and GPOx
set to low
Write 1 to the OVP_INT bit.
Interrupt is not cleared if the
VANA voltage is above the
VANAOVP level.
(VANAOVP
)
Buck power-good,
output voltage becomes
valid.
No effect
No effect
No effect
No effect
No effect
No effect
No effect
No effect
No effect
No effect
BUCK_INT = 1
BUCKx_PG_INT = 1
BUCKx_PGR_MASK
BUCKx_PGF_MASK
BOOST_PGR_MASK
BOOST_PGF_MASK
VMON1_PGR_MASK
VMON1_PGF_MASK
VMON2_PGR_MASK
VMON2_PGF_MASK
VANA_PGR_MASK
VANA_PGF_MASK
BUCKx_PG_STAT
BUCKx_PG_STAT
BOOST_PG_STAT
BOOST_PG_STAT
VMON1_PG_STAT
VMON1_PG_STAT
VMON2_PG_STAT
VMON2_PG_STAT
VANA_PG_STAT
VANA_PG_STAT
Write 1 to the BUCKx_PG_INT
bit.
Buck power-good,
output voltage becomes
invalid
BUCK_INT = 1
BUCKx_PG_INT = 1
Write 1 to the BUCKx_PG_INT
bit.
Boost power-good,
output voltage becomes
valid.
BOOST_INT = 1
BOOST_PG_INT = 1
Write 1 to the BOOST_PG_INT
bit.
Boost power-good,
output voltage becomes
invalid.
BOOST_INT = 1
BOOST_PG_INT = 1
Write 1 to the BOOST_PG_INT
bit.
VMON1 power-good,
input voltage becomes
valid.
DIAG_INT = 1
VMON1_PG_INT = 1
Write 1 to the VMON1_PG_INT
bit.
VMON1 power-good,
input voltage becomes
invalid.
DIAG_INT = 1
VMON1_PG_INT = 1
Write 1 to the VMON1_PG_INT
bit.
VMON2 power-good,
input voltage becomes
valid.
DIAG_INT = 1
VMON2_PG_INT = 1
Write 1 to the VMON2_PG_INT
bit.
VMON2 power-good,
input voltage becomes
invalid.
DIAG_INT = 1
VMON2_PG_INT = 1
Write 1 to the VMON2_PG_INT
bit.
VANA power-good,
input voltage becomes
valid.
DIAG_INT = 1
VANA_PG_INT = 1
Write 1 to the VANA_PG_INT
bit.
VANA power-good,
input voltage becomes
invalid.
DIAG_INT = 1
VANA_PG_INT = 1
Write 1 to the VANA_PG_INT
bit.
External clock appears
or disappears.
No effect to converters
No effect
SYNC_CLK_INT(1)
I_MEAS_INT = 1
N/A
SYNC_CLK_MASK
I_MEAS_MASK
N/A
SYNC_CLK_STAT
Write 1 to the SYNC_CLK_INT
bit.
Load current
measurement ready
N/A
N/A
Write 1 to the I_MEAS_INT bit.
Supply voltage
VANAUVLO triggered
(VANA falling)
Immediate shutdown,
registers reset to default
values
N/A
Supply voltage
VANAUVLO triggered
(VANA rising)
Start-up, registers reset
to default values and
OTP bits loaded
RESET_REG_INT = 1
RESET_REG_MASK
N/A
Write 1 to the
RESET_REG_INT bit.
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Table 7-5. Summary of Interrupt Signals (continued)
EVENT
SAFE STATE
INTERRUPT BIT
INTERRUPT MASK
STATUS BIT
RECOVERY/INTERRUPT
CLEAR
Software requested
reset
Immediate shutdown
followed by powerup,
registers reset to default
values
RESET_REG_INT = 1
RESET_REG_MASK
N/A
Write 1 to the
RESET_REG_INT bit.
(1) Interrupt generated during the Clock Detector operation and in case the Clock is not available when the Clock Detector is enabled.
7.3.10.3 Power-Good Information to Interrupt, PG0, and PG1 Pins
LP87702 supports both interrupt based indication of the power-good levels for various voltage settings and
uses two power-good signals, PG0 and PG1. The selection of monitored signals is independent for the interrupt
(nINT) and PG0 and PG1 signals. Each signal can include the following:
•
•
•
•
•
The output voltage of one or both BUCKx converters
The output voltage of the BOOST converter
Input voltage of VANA
Input voltage of VMON1 and VMON2 or both
Thermal warning
Figure 7-9 shows the block diagram for power-good connections to PG0 and PG1 pins and interrupt.
Monitored signals are enabled in the PGOOD_CTRL register. Converter output voltage monitoring (not current
limit monitoring) can be selected for the indication. Monitoring is enabled by the EN_PGOOD_BUCKx and
EN_PGOOD_BOOST bits. The monitoring is automatically masked to prevent it from forcing PGx inactive or
causing an interrupt when a converter is disabled. Also, monitoring of VANA, VMON1, and VMON2 inputs can
be independently enabled through the PGOOD_CTRL register. The type of voltage monitoring for the PGx
signals and nINT is selected by the PGOOD_WINDOW bit. Only the undervoltage is monitored if the bit is 0
and the undervoltage and overvoltage are monitored if the bit is 1. See Section 7.3.10.1 for voltage monitoring
thresholds.
Monitoring interrupts from all the output rails, input rails, and thermal warning are combined to the nINT pin.
Dedicated mask bits are used to select which interrupts control the state of the nINT pin. See Table 7-5 for
summary of the interrupts, mask bits, and interrupt clearing.
Similarly, enabled monitoring signals from all the output rails, input rails, and thermal warning are combined to
PG0 and PG1 output pins. Register bits (SEL_PGx_x in PG0_CTRL and PG1_CTRL) select which of the signals
control the state of PG0 and PG1, respectively. The polarity and the output type (push-pull or open-drain) of PG0
and PG1 are selected by the PGx_POL and PGx_OD bits in the PG_CTRL register.
PGx is only active or asserted when all monitored input voltages and all output voltages of the monitored and
enabled converters are within the specified tolerance of the set target value.
PGx is inactive or de-asserted if any of the monitored input voltages or output voltages of the monitored and
enabled converters are outside the specified tolerance of the set target value.
When PGx_RISE_DELAY = 1, PGx is set as active or asserted with 11 ms delay from the point of time
where all the enabled power resource output voltages are within the specified tolerance for each requested or
programmed output voltage.
Thermal shutdown and VANA overvoltage protection events force the PGx to the default state (the PGx are
driven low, assuming the PGx polarity set in the OTP is active high).
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Mask
Rising
INT
Mask
Falling
Boost
Powergood
EN_PGOOD_BOOST
Status
Buck0
Powergood
EN_PGOOD_BUCK0
EN_PGOOD_BUCK1
EN_PGOOD_VANA
EN_PGOOD_VMON1
EN_PGOOD_VMON2
nINT
Buck1
Powergood
VANA
VMON1
VMON2
VANA
Powergood
Mask
INT
VMON1
Powergood
Status
VMON2
Powergood
Thermal
Warn
SEL_PG0_TWARN
SEL_PG0_VMON2
SEL_PG0_VMON1
SEL_PG0_VANA
SEL_PG0_BUCK1
SEL_PG0_BUCK0
SEL_PG0_BOOST
PG0
PP/OD
Polarity
PG1/GPO1
PP/OD
PG0 CONTROL
PG1 CONTROL
GPO1_SEL
GPO1
Figure 7-9. Block Diagram of Power-Good Connections
LP87702 power-good detection has two operating modes selected in the OTP: gated (that is, unusual) or
continuous (that is, invalid) mode of operation. These modes are described in Section 7.3.10.3.1 and in Section
7.3.10.3.2.
7.3.10.3.1 PGx Pin Gated (Unusual) Mode
The PGx signal detects unexpected or unusual situations in this mode. Mode is selected by setting the
PGx_MODE bit to 0 in the PG_CTRL register.
For the gated mode of operation, the PGx behaves as follows:
•
•
PGx is set to active or asserted state upon exiting the OTP configuration as an initial default state.
The PGx status is active or asserted during an 800-μs gated time period from the enable activation for each
enabled rail, thereby gating-off the status indication.
•
•
The PGx state typically remains active or asserted for normal conditions during normal power-up sequencing
and requested voltage changes.
The PGx status could change to inactive or de-asserted after an 800-μs gated time period if any output
voltage is outside of regulation range during an abnormal power-up sequencing and requested voltage
changes.
•
Using the gated mode of operation could allow the PGx signal to initiate an immediate power shutdown
sequence if the PGx signal is wired-OR with signal connected to the EN input. This type of circuit
configuration provides a smart PORz function for processor that eliminates the need for additional
components to generate PORz upon start-up and to monitor voltage levels of key voltage domains.
PGx signal is set inactive if the output voltage of a monitored buck or boost converter is invalid or the output
voltage is not valid at 800 µs from the enable of the converter, which should be considered when selecting the
BUCKx_SLEW_RATE setting. Keep the sum of the soft start time and slew rate controlled part of the voltage
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ramp below 800 µs to avoid PGx triggering at start-up. In addition, the PGx is inactive when the invalid input
voltage at VANA, VMON1, or VMON2 pin is detected.
Detected fault sets the corresponding fault bit in PG0_FAULT or in PG1_FAULT register. The detected fault must
be cleared to continue the PGx monitoring. The over-voltage and thermal faults are cleared by writing 1 to the
corresponding interrupt bits in INT_TOP_1 register. Converter, VMONx and VANA faults are cleared by writing 1
to the corresponding register bit in INT_BUCK, INT_BOOST, and INT_DIAG register, respectively. An example
of the PGx pin operation in gated mode is shown in Figure 7-10 and the different use cases for the PGx signal
operation are summarized in Table 7-6.
V(VANA)
VANA_UVLO
Shut
down
Read
OTP
Standby
Active
State
PGx pin
Clear fault
EN
4ms
EN (Buck1)
VOUT (Buck1)
800us Timer
Powergood (Buck1)
EN (Boost)
2ms
800us Timer
VOUT (Boost)
Powergood (Boost)
Figure 7-10. PGx Pin Operation in Gated Mode.
7.3.10.3.2 PGx Pin Operation in Continuous Mode
In this mode the PGx signal shows the validity of the requested voltages continuously. Mode is selected by
setting the PGx_MODE bit to 1 in the PG_CTRL register.
For the continuous mode of operation, the PGx behaves as follows:
•
•
•
•
PGx is set to active or asserted state upon exiting the OTP configuration as an initial default state.
PGx is set to inactive or de-asserted as soon as the converter is enabled.
PGx status begins indicating the output voltage regulation status immediately and continuously.
PGx state changes between inactive or deasserted and active or asserted during power-up sequencing
and requested voltage changes, depending on the output voltages being outside or inside of the regualtion
ranges.
When an invalid output voltage of monitored converter is detected, the corresponding bit in the PG0_FAULT
or PG1_FAULT register is set to 1 and the PGx signal becomes inactive. The PG0_FAULT and PG1_FAULT
register bits are latched and maintain the fault information until host clears the fault bit by writing 1 to the bit.
The PGx signal also indicates the interrupts from VANA, VMON1, and VMON2 inputs and thermal warning and
shutdown. All are cleared by clearing the interrupt bits.
The PGx signal is set inactive when the converter voltage is transitioning from one target voltage to another.
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The source for the fault can be read from PGx_FAULT register when PGx signal becomes inactive. If the invalid
output voltage becomes valid again the PGx signal becomes active. Thus the PGx signal shows all the time if
the monitored output voltages are valid. Figure 7-11 shows an example of the PGx pin operation in continuous
mode.
The PGx signal can also be configured so that it maintains the inactive state even when the monitored outputs
are valid, but there are PG_FAULT_x bits pending clearance. This type of operation is selected by setting the
PGOOD_FAULT_GATES_PGx bit to 1.
V(VANA)
VANA_UVLO
Shut
down
Read
OTP
Standby
Active
State
PGx pin
EN
4ms
EN (Buck1)
VOUT (Buck1)
Powergood (Buck1)
EN (Boost)
2ms
VOUT (Boost)
Powergood (Boost)
Figure 7-11. PGx Pin Operation in Continuous Mode
7.3.10.3.3 Summary of PG0, PG1 Gated, and Continuous Operating Modes
Table 7-6 summarizes the PGx behavior in different application scenarios, for the gated and continuous
operating modes.
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Table 7-6. PGx Operation
PGx SIGNAL(1) (2)
STATUS / USE CASE
CONDITION
GATED MODE
PGx_MODE = 0
CONTINUOUS MODE
PGx_MODE = 1
Device start-up
Until device state is STANDBY
EN_PGOOD_x = 0
Low
Low
OK
Converter not selected for PGx
monitoring
OK
Converter selected for PGx
monitoring and disabled by host
BUCKx_EN / BOOST_EN = 0 OR
(Pin ctrl AND EN = 0)
OK
OK
OK
OK
Converter start-up delay ongoing
EN = 1
NOK
NOK
Converter start-up until valid
output voltage reached
Valid output voltage reached in 800
µs
Converter start-up until valid
output voltage reached
Valid output voltage not reached at
800 µs
NOK
OK
NOK
OK
Output voltage within window
limits after start-up
Must be inside limits longer than
debounce time
If spikes are outside voltage
monitoring threshold(s) longer than
debounce time
Output voltage spikes (over/
undervoltage)
NOK
NOK
NOK
OK (if new voltage reached in 800
µs)
NOK after 800 µs (if new voltage
not reached at 800 µs)
Voltage setting change, output
voltage ramp
Output voltage within window
limits after voltage change
Must be inside limits longer than
debounce time
OK
OK
OK
OK
Converter shutdown delay
ongoing
Buck converter disabled by host,
slew-rate controlled ramp down
ongoing
OK
OK
OK
OK
Converter disabled by host,
pulldown resistor active (if
selected)
Faulty converter disabled by short-
circuit detection
BUCKx_SC_INT / BOOST_SC_INT
= 1
Converter short-circuit interrupt
pending (converter selected for
PGx monitoring)
NOK
NOK
NOK
NOK
Converters disabled by thermal
shutdown detection
Thermal shutdown interrupt
pending
TDIE_SD_INT = 1
Converters disabled by overvoltage
detection
Input (VANA) overvoltage
interrupt pending
NOK
Low
NOK
Low
OVP_INT = 1
Supply voltage below VANAUVLO
(1) NOK (Not OK) means faulty situation. PGx pin is inactive if at least one NOK situation is detected.
(2) PGx pin is generated from PG_FAULT register bits and INT_TOP_1 register bits TDIE_SD_INT, OVP_INT and
INT_TOP_2(RESET_REG_INT) bit.
7.3.10.4 Warning Interrupts for System Level Diagnostics
7.3.10.4.1 Output Power Limit
The buck converters have programmable output peak current limits. The limits are individually programmed for
both converters with BUCKx_ILIM[2:0] bits. If the load current is increased so that the current limit is triggered,
the converter continues to regulate to the limit current level (current peak regulation). The voltage may decrease
if the load current is higher than limit current. If the current regulation continues for 20 µs, the LP87702 device
sets the BUCKx_ILIM_INT bit and pulls the nINT pin low. The host processor can read the BUCKx_ILIM_STAT
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bits to see if the converter is still in peak current regulation mode. During startup or output voltage ramp (output
voltage change has been programmed) no interrupt is generated.
If the load is so high that the output voltage decreases below a 350-mV level, the LP87702 device disables
the converter and sets the BUCKx_SC_INT bit. The interrupt is cleared when the host processor writes 1 to
BUCKx_SC_INT bit. Figure 7-12 shows the Buck overload situation.
Regulator disabled by
digital
New startup if
enable is valid
Voltage
VOUTx
350 mV
Resistive
pull-down
1 ms
Time
Current
ILIMx
Time
20 µs
0
0
1
1
0
INT_BUCK(BUCKx_ILIM_INT)
INT_BUCK(BUCKx_SC_INT)
BUCK_STAT(BUCKx_STAT)
nINT
1
0
0
1
Host clearing the interrupt by writing to flags
Figure 7-12. Buck Overload Situation
The boost converter has programmable output peak current limits. The limits are set with the BOOST_ILIM bits.
If the load current is increased so that the current limit is triggered, the converter continues to regulate to the limit
current level (current peak regulation). The voltage may decrease if the load current is higher than limit current. If
the current regulation continues for 64 µs, the LP87702 device sets the BOOST_ILIM_INT bit and pulls the nINT
pin low. The host processor can read the BOOST_ILIM_STAT bits to see if the converter is still in peak current
regulation mode.
If the load is so high that the output voltage decreases 150 mV (typical) below the input voltage level, then the
converter is disabled after 1 ms. If the output voltage decreases to 2.5 V, boost stops switching. After 1 ms the
deglitch time boost is fully disabled and the interrupt BOOST_SC_INT bit is set. The interrupt is cleared when
the host processor writes 1 to the BOOST_SC_INT bit. Figure 7-13 shows the Boost overload situation.
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Converter disabled
by digital
New startup if
enable is valid
Voltage
VOUTx
VIN
2.5 V
1ms
Resistive
pull-down
Time
Time
Current
ILIMx
64 ms
0
0
1
1
0
INT_BOOST(BOOST_ILIM_INT)
INT_BOOST(BOOST_SC_INT)
BOOST_STAT(BOOST_STAT)
nINT
1
0
0
1
Host clearing the interrupt by writing to flags
Figure 7-13. Boost Overload Situation
The buck converters have a fixed current limit for negative output peak current (ILIM_NEG). When the negative coil
current increases, it is limited below ILIM_NEG, the converter continues to operate and no interrupt is generated.
The boost converter's negative peak current limit operation is similar and the limit value is 1.4 A (typical).
7.3.10.4.2 Thermal Warning
The LP87702 device includes a protection feature against over-temperature by setting an interrupt for the host
processor. The thermal warning's threshold level is selected with the TDIE_WARN_LEVEL bit.
If the LP87702 device temperature increases above the thermal warning level, the device sets the
TDIE_WARN_INT bit and pulls the nINT pin low. The status of the thermal warning can be read from the
TDIE_WARN_STAT bit and the interrupt is cleared by writing 1 to the TDIE_WARN_INT bit. The thermal warning
interrupt can be masked by setting the TDIE_WARN_MASK bit to 1.
7.3.10.5 Protections Causing Converter Disable
If the converter is disabled because of protection or fault (short-circuit protection, thermal shutdown, overvoltage
protection, or undervoltage lockout), the output power FETs are set to high-impedance mode, and the output
pulldown resistor is enabled (if enabled with BUCKx_RDIS_EN and BOOST_RDIS_EN bits). The turnoff time
of the output voltage is defined by the output capacitance, load current, and the resistance of the integrated
pulldown resistor. The pulldown resistors are active as long as the VANA voltage is above the 1.2-V level
(approximately).
7.3.10.5.1 Short-Circuit and Overload Protection
A short-circuit protection feature allows the LP87702 to protect itself and external components against short
circuiting at the output or against overloading during start-up. A short-circuit at the buck converter output is
detected during start-up when the output voltage is below 350 mV (typical) 1 ms after the buck converter is
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enabled. The fault threshold is 150 mV (typical) below the input voltage level for boost. Boost converter is
disabled if the output voltage is below the threshold level 1 ms after the boost converter is enabled.
In a similar way, the overload situation is protected during normal operation. If the feedback-pin voltage of the
buck converter falls below 0.35 V and remains below the threshold level for 1 ms, the buck converter is disabled.
If the output voltage of the boost converter decreases 150 mV below the input voltage level, the converter is
disabled after 1 ms. If the output voltage decreases to 2.5 V, the boost is disabled immediately.
The BUCKx_SC_INT and the BUCK_INT bits are set to 1, the BUCKx_STAT bit is set to 0, and the nINT
signal is pulled low in the buck converter, the short-circuit, and overload situations. The BOOST_SC_INT and
the BOOST_INT bits are set to 1, the BOOST_STAT bit is set to 0, and the nINT signal is pulled low in the
boost converter, short-circuit, and overload situations. The host processor clears the interrupt by writing 1 to
the BUCKx_SC_INT or BOOST_SC_INT bit. The converter makes a new start-up attempt upon clearing the
interrupt, if the converter is in the enabled state.
7.3.10.5.2 Overvoltage Protection
The LP87702 device monitors the input voltage from the VANA pin in the standby and active operation modes.
If the input voltage rises above the VANAOVP voltage level, all the converters are disabled immediately (without
switching ramp or shutdown delays), the pulldown resistors discharge the output voltages (BUCKx_RDIS_EN
= 1 and BOOST_RDIS_EN = 1), the GPOs are set to the logic low level, the nINT signal is pulled low, the
OVP_INT bit is set to 1, and BUCKx_STAT and BOOST_STAT bits are set to 0. The host processor clears the
interrupt by writing 1 to the OVP_INT bit. If the input voltage is above over-voltage detection level, the interrupt
is not cleared. The host can read the status of the overvoltage from the OVP_STAT bit. Converters cannot be
enabled as long as the input voltage is above over-voltage detection level or the overvoltage interrupt is pending.
7.3.10.5.3 Thermal Shutdown
The LP87702 has an overtemperature protection function that operates to protect itself from short-term misuse
and overload conditions. The converters are disabled immediately (without switching ramp or shutdown delays),
the TDIE_SD_INT bit is set to 1, the nINT signal is pulled low, and the device enters STANDBY when the
junction temperature exceeds around 150°C. The nINT is cleared by writing 1 to the TDIE_SD_INT bit. If
the temperature is above thermal shutdown level, the interrupt is not cleared. The host can read the status
of the thermal shutdown from the TDIE_SD_STAT bit. Converters cannot be enabled as long as the junction
temperature is above the thermal shutdown level or the thermal shutdown interrupt is pending.
7.3.10.6 Protections Causing Device Power Down
7.3.10.6.1 Undervoltage Lockout
The buck and boost converters are disabled immediately (without switching ramp or without any shutdown
delays), and the output capacitor is discharged using the pulldown resistor, and the LP87702 device enters
SHUTDOWN when the input voltage falls below VANAUVLO at the VANA pin. The device powers up to STANDBY
state when the V(VANA) voltage is above the VANAUVLO threshold level.
If the reset interrupt is unmasked by default (RESET_REG_MASK = 0 in TOP_MASK_2 register), the
RESET_REG_INT interrupt in the INT_TOP_2 register indicates that the device has been in SHUTDOWN. The
host processor must clear the interrupt by writing 1 to the RESET_REG_INT bit. If the host processor reads the
RESET_REG_INT flag after detecting an nINT low signal, it detects that the input supply voltage has been below
the VANAUVLO level (or the host has requested reset with the RESET(SW_RESET) bit), and the registers are
reset to the default values.
7.3.11 OTP Error Correction
LP87702 supports the OTP bit error detection and 1-bit error correction per five registers. The ECC_STATUS
register bit SED is set if a single bit error was detected and corrected. DED bit is set in case two bit errors have
been detected in any bank of five registers.
7.3.12 Operation of GPO Signals
The LP87702 device supports up to 3 general purpose output (GPO) signals. The GPO1 signal is multiplexed
with the PG1 signal and GPO2 signal is multiplexed with the CLKIN and WD_DIS signals. The selection between
signal use are set with the GPO1_SEL and GPO2_SEL bits in the GPO_CONTROL_2 register.
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The type of output, either push-pull (with V(VANA) level) or open drain, are set with the GPO0_OD and
GPO1_PG1_OD bits in the GPO_CONTROL_1 register and the GPO2_OD bit in the GPO_CONTROL_2
register.
The logic level of the GPOx pins are is set by the GPO0_OUT and GPO1_OUT bits in the GPO_CONTROL_1
register and the GPO2_OUT bit in the GPO_CONTROL_2 register.
The control of the GPOs can be included to start-up and shutdown sequences. The GPO control for a sequence
with ENx pin is selected by the GPOx_EN_PIN_CTRL bits. The delays during start-up and shutdown are set by
bits in the GPOx_DELAY registers.
7.3.13 Digital Signal Filtering
The digital signals have a debounce filtering. The signal or supply is sampled with a clock signal and a counter.
This results as an accuracy of one clock period for the debounce window.
Table 7-7. Digital Signal Filtering
RISING EDGE
FALLING EDGE
LENGTH
EVENT
SIGNAL/SUPPLY
LENGTH
Enable or Disable for BUCKx,
BOOST, or GPOx
ENx
3 µs(1)
3 µs(1)
VANA undervoltage lockout
VANA overvoltage
VANA
VANA
Immediate (VANA voltage rising)
Immediate (VANA voltage falling)
1 µs (VANA voltage rising)
1 µs (VANA voltage falling)
Thermal warning
TDIE_WARN_INT
20 µs
20 µs
20 µs
64 µs
20 µs
20 µs
20 µs
64 µs
Thermal shutdown
TDIE_SD_INT
Current limit, BUCKx
Current limit, BOOST
FB_B0, FB_B1,
VOUT_BST
Overload
1 ms
6 µs
N/V
6 µs
PGx pin and power-good
interrupt (voltage monitoring)
PG0, PG1 / FB_B0, FB_B1
PGx pin and power-good
interrupt (voltage monitoring)
PG0, PG1 / VOUT_BST,
VANA, VMON1, VMON2
15 µs
15 µs
(1) No glitch filtering; only synchronization.
7.4 Device Functional Modes
7.4.1 Modes of Operation
SHUTDOWN: The V(VANA) voltage is below the VANAUVLO threshold level or the NRST signal is low. All switch,
reference, control, and bias circuitry of the LP87702 device are turned off.
READ OTP: The main supply voltage (V(VANA)) is above the VANAUVLO level and the NRST signal is high.
The converters are disabled and the reference and bias circuitry of the LP87702 are enabled.
The OTP bits are loaded to the registers. I2C access is not allowed during OTP read. Section
7.3.8 shows how this also applies to the watchdog.
STANDBY:
The main supply voltage (V(VANA)) is above the VANAUVLO level and the NRST signal is high.
All registers can be read or written by the host processor through the system serial interface.
Watchdog is active and the WDI input is expected to toggle to avoid watchdog expiration. The
converters are disabled and the LP87702's reference, control, and bias circuitry are enabled.
The converters can be enabled if needed.
ACTIVE:
The main supply voltage (V(VANA)) is above the VANAUVLO level and the NRST signal is high. At
least one converter is enabled. All registers can be read or written by the host processor through
the system's serial interface. Watchdog is active and the WDI input is expected to toggle to avoid
watchdog expiration.
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Figure 7-14 shows the operating modes and transitions between the modes. See Section 7.3.8 for the window
watchdog detailed operation.
SHUTDOWN
NRST low OR
< VANAUVLO
V
VANA
NRST high AND
> VANAUVLO
V
VANA
FROM ANY STATE
EXCEPT SHUTDOWN
READ
OTP
REG
RESET
STANDBY
2
I C RESET
CONVERTER
ENABLED
CONVERTER(S)
DISABLED
ACTIVE
Figure 7-14. Device Operation Modes.
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7.5 Programming
7.5.1 I2C-Compatible Interface
The I2C-compatible synchronous serial interface provides access to the programmable functions and registers
on the device. This protocol uses a two-wire interface for bidirectional communications between the ICs
connected to the bus. The two interface lines are the serial data line (SDA) and the serial clock line (SCL).
Every device on the bus is assigned a unique address and acts as either a master or a slave depending on
whether it generates or receives the serial clock SCL. The SCL and SDA lines should each have a pull-up
resistor placed somewhere on the line and remain HIGH even when the bus is idle. The LP87702 supports
standard mode (100 kHz), fast mode (400 kHz), fast mode plus (1 MHz), and high-speed mode (3.4 MHz).
7.5.1.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the
state of the data line can only be changed when clock signal is LOW.
SCL
SDA
data
change
allowed
data
change
allowed
data
change
allowed
data
valid
data
valid
Figure 7-15. Data Validity Diagram
7.5.1.2 Start and Stop Conditions
The LP87702 is controlled through an I2C-compatible interface. START and STOP conditions classify the
beginning and end of the I2C session. A START condition is defined as SDA transitions from HIGH to LOW
while SCL is HIGH. A STOP condition is defined as SDA transition from LOW to HIGH while SCL is HIGH. The
I2C master always generates the START and STOP conditions.
SDA
SCL
S
P
START
STOP
Condition
Condition
Figure 7-16. Start and Stop Sequences
The I2C bus is considered busy after a START condition and free after a STOP condition. The I2C master can
generate repeated START conditions during data transmission. A START and a repeated START condition are
equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock signal (SCL). In
other words, the state of SDA can only be changed when SCL is LOW. Figure 7-17 shows the SDA and SCL
signal timing for the I2C-Compatible Bus.
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tBUF
SDA
tHD;STA
trCL
tfDA
trDA
tSP
tLOW
tfCL
SCL
tHD;STA
tSU;STA
tSU;STO
tHIGH
tHD;DAT
S
START
tSU;DAT
S
RS
P
REPEATED
START
STOP
START
Figure 7-17. I2C-Compatible Timing
7.5.1.3 Transferring Data
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP87702
pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP87702 generates an
acknowledge after each byte has been received.
There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must
indicate to the transmitter an end of data by not acknowledging (negative acknowledge) the last byte clocked out
of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),
but the SDA line is not pulled down.
Note
If the V(VANA) voltage is below the VANAUVLO threshold level during I2C communication, the LP87702
device does not drive the SDA line. The ACK signal and data transfer to the master is disabled at that
time.
The bus master sends a chip address after the START condition. This address is seven bits long followed by an
eighth bit which is a data direction bit (READ or WRITE). A 0 indicates a WRITE and a 1 indicates a READ for
the eighth bit. The second byte selects the register to which the data is written. The third byte contains data to
write to the selected register.
ACK from slave
ACK from slave
ACK from slave
START MSB Chip Address LSB
W
ACK MSB Register Address LSB ACK
MSB Data LSB
ACK STOP
SCL
SDA
START
id = 0x60
W
ACK
address = 0x40
ACK
address 0x40 data
ACK STOP
Figure 7-18. Write Cycle (w = write; SDA = 0), id = Device Address = 60Hex for LP87702
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ACK from slave
ACK from slave REPEATED START
ACK from slave Data from slave NACK from master
START MSB Chip Address LSB
W
MSB Register Address LSB
RS
MSB Chip Address LSB
R
MSB Data LSB
STOP
SCL
SDA
START
ACK
ACK
ACK
NACK
STOP
id = 0x60
W
address = 0x3F
RS
id = 0x60
R
address 0x3F data
A WRITE function must precede the READ function as shown above when the READ function is accomplished.
Figure 7-19. Read Cycle (r = read; SDA = 1), id = Device Address = 60Hex for LP87702
7.5.1.4 I2C-Compatible Chip Address
The device address for the LP87702 is 0x60. After the START condition, the I2C master sends the 7-bit address
followed by an eighth bit, read or write (R/W). R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The
second byte following the device address selects the register address to which the data will be written. The third
byte contains the data for the selected register.
MSB
LSB
1
Bit 7
1
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
R/W
Bit 0
I2C Slave Address (chip address)
A. Here device address is 1100000Bin = 60Hex.
Figure 7-20. Device Address
7.5.1.5 Auto Increment Feature
The auto-increment feature allows writing several consecutive registers within one transmission. The internal
address index counter increments by one and the next register will be written every time an 8-bit word is sent
to the LP87702. Table 7-8 below shows writing sequence to two consecutive registers. Note: the auto increment
feature does not work for read.
Table 7-8. Auto-Increment Example
MASTER START DEVICE
WRITE
REGISTER
ADDRESS
DATA
DATA
STOP
ACTION
ADDRESS =
60H
LP87702
ACK
ACK
ACK
ACK
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7.6 Register Maps
7.6.1 Register Descriptions
The LP87702 is controlled by a set of registers through the system serial interface port. This register map
describes the default values for the bits which are not read from OTP memory. The asterisk (*) marking indicates
the register bits which are updated from the OTP memory during the READ OTP state. OTP values for each
orderable part number are described in a separate technical reference manual TRM.
7.6.1.1 LP8770_map Registers
Table 7-9 lists the memory-mapped registers for the LP8770_map registers. All register offset addresses not
listed in Table 7-9 should be considered as reserved locations and the register contents should not be modified.
Table 7-9. LP8770_MAP Registers
Offset
0h
Acronym
Register Name
Section
DEV_REV
Section 7.6.1.1.1
Section 7.6.1.1.2
Section 7.6.1.1.3
Section 7.6.1.1.4
Section 7.6.1.1.5
Section 7.6.1.1.6
Section 7.6.1.1.7
Section 7.6.1.1.8
Section 7.6.1.1.9
Section 7.6.1.1.10
Section 7.6.1.1.11
Section 7.6.1.1.12
Section 7.6.1.1.13
Section 7.6.1.1.14
Section 7.6.1.1.15
Section 7.6.1.1.16
Section 7.6.1.1.17
Section 7.6.1.1.18
Section 7.6.1.1.19
Section 7.6.1.1.20
Section 7.6.1.1.21
Section 7.6.1.1.22
Section 7.6.1.1.23
Section 7.6.1.1.24
Section 7.6.1.1.25
Section 7.6.1.1.26
Section 7.6.1.1.27
Section 7.6.1.1.28
Section 7.6.1.1.29
Section 7.6.1.1.30
Section 7.6.1.1.31
Section 7.6.1.1.32
Section 7.6.1.1.33
Section 7.6.1.1.34
Section 7.6.1.1.35
1h
OTP_CODE
2h
BUCK0_CTRL_1
BUCK0_CTRL_2
BUCK1_CTRL_1
BUCK1_CTRL_2
BUCK0_VOUT
BUCK1_VOUT
BOOST_CTRL
BUCK0_DELAY
BUCK1_DELAY
BOOST_DELAY
GPO0_DELAY
GPO1_DELAY
GPO2_DELAY
GPO_CONTROL_1
GPO_CONTROL_2
CONFIG
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
PLL_CTRL
PGOOD_CTRL
PGOOD_LEVEL_1
PGOOD_LEVEL_2
PGOOD_LEVEL_3
PG_CTRL
PG0_CTRL
PG0_FAULT
PG1_CTRL
PG1_FAULT
WD_CTRL_1
WD_CTRL_2
WD_STATUS
RESET
INT_TOP_1
INT_TOP_2
INT_BUCK
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Table 7-9. LP8770_MAP Registers (continued)
Offset
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
Acronym
Register Name
Section
INT_BOOST
Section 7.6.1.1.36
Section 7.6.1.1.37
Section 7.6.1.1.38
Section 7.6.1.1.39
Section 7.6.1.1.40
Section 7.6.1.1.41
Section 7.6.1.1.42
Section 7.6.1.1.43
Section 7.6.1.1.44
Section 7.6.1.1.45
Section 7.6.1.1.46
Section 7.6.1.1.47
Section 7.6.1.1.48
Section 7.6.1.1.49
Section 7.6.1.1.50
Section 7.6.1.1.51
Section 7.6.1.1.52
Section 7.6.1.1.53
Section 7.6.1.1.54
INT_DIAG
TOP_STATUS
BUCK_STATUS
BOOST_STATUS
DIAG_STATUS
TOP_MASK_1
TOP_MASK_2
BUCK_MASK
BOOST_MASK
DIAG_MASK
SEL_I_LOAD
I_LOAD_2
I_LOAD_1
FREQ_SEL
BOOST_ILIM_CTRL
ECC_STATUS
WD_DIS_CTRL_CODE
WD_DIS_CONTROL
Complex bit access types are encoded to fit into small table cells. Table 7-10 shows the codes that are used for
access types in this section.
Table 7-10. LP8770_map Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n
When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y
When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.
7.6.1.1.1 DEV_REV Register (Offset = 0h) [reset = 0h]
DEV_REV is shown in Figure 7-19 and described in Table 7-11.
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Return to Table 7-9.
Figure 7-19. DEV_REV Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
DEVICE_ID
R-0h
Table 7-11. DEV_REV Register Field Descriptions
Bit
7-6
5-3
Field
Type
Reset
Description
RESERVED
DEVICE_ID
R
0h
R
0h
Device specific ID code.
(Default from OTP memory)
7.6.1.1.2 OTP_CODE Register (Offset = 1h) [reset = 0h]
OTP_CODE is shown in Figure 7-20 and described in Table 7-12.
Return to Table 7-9.
Figure 7-20. OTP_CODE Register
7
6
5
4
3
2
1
0
OTP_ID
R-0h
OTP_REV
R-0h
Table 7-12. OTP_CODE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
OTP_ID
R
0h
Identification Code of the OTP EPROM.
(Default from OTP memory)
1-0
OTP_REV
R
0h
Version number of the OTP ID.
(Default from OTP memory)
7.6.1.1.3 BUCK0_CTRL_1 Register (Offset = 2h) [reset = 8h]
BUCK0_CTRL_1 is shown in Figure 7-21 and described in Table 7-13.
Return to Table 7-9.
Figure 7-21. BUCK0_CTRL_1 Register
7
6
5
4
3
2
1
0
BUCK0_EN
RESERVED
R/W-0h
BUCK0_FPWM BUCK0_RDIS_
EN
BUCK0_EN_PIN_CTRL
R/W-0h
R/W-0h
R/W-1h
R/W-0h
Table 7-13. BUCK0_CTRL_1 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-6
4
RESERVED
0h
BUCK0_FPWM
0h
Forces the BUCK0 converter to operate in PWM mode:
0 – Automatic transitions between PFM and PWM modes (AUTO
mode).
1 – Forced to PWM operation.
(Default from OTP memory)
3
BUCK0_RDIS_EN
R/W
1h
Enable output discharge resistor when BUCK0 is disabled:
0 – Discharge resistor disabled
1 – Discharge resistor enabled.
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Table 7-13. BUCK0_CTRL_1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2-1
BUCK0_EN_PIN_CTRL
R/W
0h
Enable or disable control for BUCK0:
0x0 – only BUCK0_EN bit controls BUCK0
0x1 – BUCK0_EN bit AND EN1 pin control BUCK0
0x2 – BUCK0_EN bit AND EN2 pin control BUCK0
0x3 – BUCK0_EN bit AND EN3 pin control BUCK0
(Default from OTP memory)
0
BUCK0_EN
R/W
0h
Enable BUCK0 converter:
0 – BUCK0 converter is disabled
1 – BUCK0 converter is enabled.
(Default from OTP memory)
7.6.1.1.4 BUCK0_CTRL_2 Register (Offset = 3h) [reset = 1Ah]
BUCK0_CTRL_2 is shown in Figure 7-22 and described in Table 7-14.
Return to Table 7-9.
Figure 7-22. BUCK0_CTRL_2 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
BUCK0_ILIM
R/W-3h
BUCK0_SLEW_RATE
R/W-2h
Table 7-14. BUCK0_CTRL_2 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-6
5-3
RESERVED
BUCK0_ILIM
0h
3h
Sets the switch peak current limit of BUCK0. Can be programmed at
any time during operation:
0x0 – 1.5 A
0x1 – 2.0 A
0x2 – 2.5 A
0x3 – 3.0 A
0x4 – 3.5 A
0x5 – 4.0 A
0x6 – 4.5 A
0x7 – Reserved
(Default from OTP memory)
2-0
BUCK0_SLEW_RATE
R/W
2h
Sets the output voltage slew rate for BUCK0 converter (rising and
falling edges):
0x0 – Reserved
0x1 – Reserved
0x2 – 10 mV/μs
0x3 – 7.5 mV/μs
0x4 – 3.8 mV/μs
0x5 – 1.9 mV/μs
0x6 – 0.94 mV/μs
0x7 – 0.47 mV/μs
(Default from OTP memory)
7.6.1.1.5 BUCK1_CTRL_1 Register (Offset = 4h) [reset = 8h]
BUCK1_CTRL_1 is shown in Figure 7-23 and described in Table 7-15.
Return to Table 7-9.
Figure 7-23. BUCK1_CTRL_1 Register
7
6
5
4
3
2
1
0
RESERVED
BUCK1_FPWM BUCK1_RDIS_
EN
BUCK1_EN_PIN_CTRL
BUCK1_EN
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Figure 7-23. BUCK1_CTRL_1 Register (continued)
R/W-0h
R/W-0h
R/W-1h
R/W-0h
R/W-0h
Table 7-15. BUCK1_CTRL_1 Register Field Descriptions
Bit
7-5
4
Field
Type
R/W
R/W
Reset
Description
RESERVED
0h
BUCK1_FPWM
0h
Forces the BUCK1 converter to operate in PWM mode:
0 – Automatic transitions between PFM and PWM modes (AUTO
mode).
1 – Forced to PWM operation.
(Default from OTP memory)
3
BUCK1_RDIS_EN
R/W
R/W
1h
0h
Enable output discharge resistor when BUCK1 is disabled:
0 – Discharge resistor disabled
1 – Discharge resistor enabled.
2-1
BUCK1_EN_PIN_CTRL
Enable or disable control for BUCK1:
0x0 – only BUCK1_EN bit controls BUCK1
0x1 – BUCK1_EN bit AND EN1 pin control BUCK1
0x2 – BUCK1_EN bit AND EN2 pin control BUCK1
0x3 – BUCK1_EN bit AND EN3 pin control BUCK1
(Default from OTP memory)
0
BUCK1_EN
R/W
0h
Enable BUCK1 converter:
0 – BUCK1 converter is disabled
1 – BUCK1 converter is enabled.
(Default from OTP memory)
7.6.1.1.6 BUCK1_CTRL_2 Register (Offset = 5h) [reset = 1Ah]
BUCK1_CTRL_2 is shown in Figure 7-24 and described in Table 7-16.
Return to Table 7-9.
Figure 7-24. BUCK1_CTRL_2 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
BUCK1_ILIM
R/W-3h
BUCK1_SLEW_RATE
R/W-2h
Table 7-16. BUCK1_CTRL_2 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-6
5-3
RESERVED
BUCK1_ILIM
0h
3h
Sets the switch peak current limit of BUCK1. Can be programmed at
any time during operation:
0x0 – 1.5 A
0x1 – 2.0 A
0x2 – 2.5 A
0x3 – 3.0 A
0x4 – 3.5 A
0x5 – 4.0 A
0x6 – 4.5 A
0x7 – Reserved
(Default from OTP memory)
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Table 7-16. BUCK1_CTRL_2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2-0
BUCK1_SLEW_RATE
R/W
2h
Sets the output voltage slew rate for BUCK1 converter (rising and
falling edges):
0x0 – Reserved
0x1 – Reserved
0x2 – 10 mV/μs
0x3 – 7.5 mV/μs
0x4 – 3.8 mV/μs
0x5 – 1.9 mV/μs
0x6 – 0.94 mV/μs
0x7 – 0.47 mV/μs
(Default from OTP memory)
7.6.1.1.7 BUCK0_VOUT Register (Offset = 6h) [reset = 0h]
BUCK0_VOUT is shown in Figure 7-25 and described in Table 7-17.
Return to Table 7-9.
Figure 7-25. BUCK0_VOUT Register
7
6
5
4
3
2
1
0
BUCK0_VSET
R/W-0h
Table 7-17. BUCK0_VOUT Register Field Descriptions
Bit
7-0
Field
BUCK0_VSET
Type
Reset
Description
R/W
0h
Output voltage of BUCK0 converter:
0x00 ... 0x13, Reserved, DO NOT USE
0.7 V – 0.73 V, 10 mV steps
0x14 – 0.7 V
...
0x17 – 0.73 V
0.73 V – 1.4 V, 5 mV steps
0x18 – 0.735 V
...
0x9D – 1.4 V
1.4 V – 3.36 V, 20 mV steps
0x9E – 1.42 V
...
0xFF – 3.36 V
(Default from OTP memory)
7.6.1.1.8 BUCK1_VOUT Register (Offset = 7h) [reset = 0h]
BUCK1_VOUT is shown in Figure 7-26 and described in Table 7-18.
Return to Table 7-9.
Figure 7-26. BUCK1_VOUT Register
7
6
5
4
3
2
1
0
BUCK1_VSET
R/W-0h
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Table 7-18. BUCK1_VOUT Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BUCK1_VSET
R/W
0h
Output voltage of BUCK1 converter
0x00 ... 0x13, Reserved, DO NOT USE
0.7 V – 0.73 V, 10 mV steps
0x14 – 0.7 V
...
0x17 – 0.73 V
0.73 V – 1.4 V, 5 mV steps
0x18 – 0.735 V
...
0x9D – 1.4 V
1.4 V – 3.36 V, 20 mV steps
0x9E – 1.42 V
...
0xFF – 3.36 V
(Default from OTP memory)
7.6.1.1.9 BOOST_CTRL Register (Offset = 8h) [reset = 8h]
BOOST_CTRL is shown in Figure 7-27 and described in Table 7-19.
Return to Table 7-9.
Figure 7-27. BOOST_CTRL Register
7
6
5
4
3
2
1
0
BOOST_VSET
R/W-0h
RESERVED
RESERVED
BOOST_RDIS_
EN
BOOST_EN_PIN_CTRL
R/W-0h
BOOST_EN
R/W-0h
R/W-1h
R/W-1h
R/W-0h
Table 7-19. BOOST_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
BOOST_VSET
R/W
0h
Output voltage of Boost:
0x0 – 4.9 V
0x1 – 5.0 V
0x2 – 5.1 V
0x3 – 5.2 V
(Default from OTP memory)
5
4
3
RESERVED
R/W
R/W
R/W
0h
1h
1h
RESERVED
BOOST_RDIS_EN
Enable output discharge resistor when BOOST is disabled:
0 – Discharge resistor disabled
1 – Discharge resistor enabled.
2-1
BOOST_EN_PIN_CTRL
R/W
0h
Enable or disable control for Boost:
0x0 – only BOOST_EN bit controls Boost
0x1 – BOOST_EN bit AND EN1 pin control Boost
0x2 – BOOST_EN bit AND EN2 pin control Boost
0x3 – BOOST_EN bit AND EN3 pin control Boost
(Default from OTP memory)
0
BOOST_EN
R/W
0h
Enable Boost converter:
0 – Boost converter is disabled
1 – Boost converter is enabled.
(Default from OTP memory)
7.6.1.1.10 BUCK0_DELAY Register (Offset = 9h) [reset = 0h]
BUCK0_DELAY is shown in Figure 7-28 and described in Table 7-20.
Return to Table 7-9.
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Figure 7-28. BUCK0_DELAY Register
7
6
5
4
3
2
1
0
BUCK0_SHUTDOWN_DELAY
R/W-0h
BUCK0_STARTUP_DELAY
R/W-0h
Table 7-20. BUCK0_DELAY Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
BUCK0_SHUTDOWN_DE R/W
LAY
0h
Shutdown delay of BUCK0 from falling edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)
3-0
BUCK0_STARTUP_DELA R/W
Y
0h
Startup delay of BUCK0 from rising edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)
7.6.1.1.11 BUCK1_DELAY Register (Offset = Ah) [reset = 0h]
BUCK1_DELAY is shown in Figure 7-29 and described in Table 7-21.
Return to Table 7-9.
Figure 7-29. BUCK1_DELAY Register
7
6
5
4
3
2
1
0
BUCK1_SHUTDOWN_DELAY
R/W-0h
BUCK1_STARTUP_DELAY
R/W-0h
Table 7-21. BUCK1_DELAY Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
BUCK1_SHUTDOWN_DE R/W
LAY
0h
Shutdown delay of BUCK1 from falling edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)
3-0
BUCK1_STARTUP_DELA R/W
Y
0h
Startup delay of BUCK1 from rising edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)
7.6.1.1.12 BOOST_DELAY Register (Offset = Bh) [reset = 0h]
BOOST_DELAY is shown in Figure 7-30 and described in Table 7-22.
Return to Table 7-9.
Figure 7-30. BOOST_DELAY Register
7
6
5
4
3
2
1
0
BOOST_SHUTDOWN_DELAY
R/W-0h
BOOST_STARTUP_DELAY
R/W-0h
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Table 7-22. BOOST_DELAY Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
BOOST_SHUTDOWN_DE R/W
LAY
0h
Shutdown delay of Boost from falling edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)
3-0
BOOST_STARTUP_DELA R/W
Y
0h
Startup delay of Boost from rising edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)
7.6.1.1.13 GPO0_DELAY Register (Offset = Ch) [reset = 0h]
GPO0_DELAY is shown in Figure 7-31 and described in Table 7-23.
Return to Table 7-9.
Figure 7-31. GPO0_DELAY Register
7
6
5
4
3
2
1
0
GPO0_SHUTDOWN_DELAY
R/W-0h
GPO0_STARTUP_DELAY
R/W-0h
Table 7-23. GPO0_DELAY Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
GPO0_SHUTDOWN_DEL R/W
AY
0h
Shutdown delay of GPO0 from falling edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)
3-0
GPO0_STARTUP_DELAY R/W
0h
Startup delay of GPO0 from rising edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)
7.6.1.1.14 GPO1_DELAY Register (Offset = Dh) [reset = 0h]
GPO1_DELAY is shown in Figure 7-32 and described in Table 7-24.
Return to Table 7-9.
Figure 7-32. GPO1_DELAY Register
7
6
5
4
3
2
1
0
GPO1_SHUTDOWN_DELAY
R/W-0h
GPO1_STARTUP_DELAY
R/W-0h
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Table 7-24. GPO1_DELAY Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
GPO1_SHUTDOWN_DEL R/W
AY
0h
Shutdown delay of GPO1 from falling edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15b ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)
3-0
GPO1_STARTUP_DELAY R/W
0h
Startup delay of GPO1 from rising edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)
7.6.1.1.15 GPO2_DELAY Register (Offset = Eh) [reset = 0h]
GPO2_DELAY is shown in Figure 7-33 and described in Table 7-25.
Return to Table 7-9.
Figure 7-33. GPO2_DELAY Register
7
6
5
4
3
2
1
0
GPO2_SHUTDOWN_DELAY
R/W-0h
GPO2_STARTUP_DELAY
R/W-0h
Table 7-25. GPO2_DELAY Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
GPO2_SHUTDOWN_DEL R/W
AY
0h
Shutdown delay of GPO2 from falling edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)
3-0
GPO2_STARTUP_DELAY R/W
0h
Startup delay of GPO2 from rising edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)
7.6.1.1.16 GPO_CONTROL_1 Register (Offset = Fh) [reset = AAh]
GPO_CONTROL_1 is shown in Figure 7-34 and described in Table 7-26.
Return to Table 7-9.
Figure 7-34. GPO_CONTROL_1 Register
7
6
5
4
3
2
1
0
GPO1_PG1_O
D
GPO1_EN_PIN_CTRL
R/W-1h
GPO1_OUT
GPO0_OD
GPO0_EN_PIN_CTRL
R/W-1h
GPO0_OUT
R/W-1h
R/W-0h
R/W-1h
R/W-0h
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Table 7-26. GPO_CONTROL_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
GPO1_PG1_OD
R/W
1h
GPO1/PG1 signal type:
0 – Push-pull output (VANA level)
1 – Open-drain output
(Default from OTP memory)
6-5
GPO1_EN_PIN_CTRL
R/W
1h
Control for GPO1 output:
0x0 – only GPO1_OUT bit controls GPO1
0x1 – GPO1_OUT bit AND EN1 pin control GPO1
0x2 – GPO1_OUT bit AND EN2 pin control GPO1
0x3 – GPO1_OUT bit AND EN3 pin control GPO1
(Default from OTP memory)
4
3
GPO1_OUT
R/W
R/W
R/W
0h
1h
1h
Control for GPO1 signal (when configured to GPO1):
0 – Logic low level
1 – Logic high level
(Default from OTP memory)
GPO0_OD
GPO0 signal type:
0 – Push-pull output (VANA level)
1 – Open-drain output
(Default from OTP memory)
2-1
GPO0_EN_PIN_CTRL
Control for GPO0 output:
0x0 – only GPO0_OUT bit controls GPO0
0x1 – GPO0_OUT bit AND EN1 pin control GPO0
0x2 – GPO0_OUT bit AND EN2 pin control GPO0
0x3 – GPO0_OUT bit AND EN3 pin control GPO0
(Default from OTP memory)
0
GPO0_OUT
R/W
0h
Control for GPO0 signal:
0 – Logic low level
1 – Logic high level
(Default from OTP memory)
7.6.1.1.17 GPO_CONTROL_2 Register (Offset = 10h) [reset = Ah]
GPO_CONTROL_2 is shown in Figure 7-35 and described in Table 7-27.
Return to Table 7-9.
Figure 7-35. GPO_CONTROL_2 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
GPO2_SEL
R/W-0h
GPO1_SEL
R/W-0h
GPO2_OD
R/W-1h
GPO2_EN_PIN_CTRL
R/W-1h
GPO2_OUT
R/W-0h
Table 7-27. GPO_CONTROL_2 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-6
5
RESERVED
GPO2_SEL
0h
0h
CLKIN/GPO2 pin function:
0 – CLKIN
1 – GPO2
(Default from OTP memory)
4
3
GPO1_SEL
GPO2_OD
R/W
R/W
0h
1h
PG1/GPO1 pin function:
0 – PG1
1 – GPO1
(Default from OTP memory)
GPO2 signal type (when configured to GPO2):
0 – Push-pull output (VANA level)
1 – Open-drain output
(Default from OTP memory)
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Table 7-27. GPO_CONTROL_2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2-1
GPO2_EN_PIN_CTRL
R/W
1h
Control for GPO2 output:
0x0 – only GPO2_OUT bit controls GPO2
0x1 – GPO2_OUT bit AND EN1 pin control GPO2
0x2 – GPO2_OUT bit AND EN2 pin control GPO2
0x3 – GPO2_OUT bit AND EN3 pin control GPO2
(Default from OTP memory)
0
GPO2_OUT
R/W
0h
Control for GPO2 signal (when configured to GPO2):
0 – Logic low level
1 – Logic high level
(Default from OTP memory)
7.6.1.1.18 CONFIG Register (Offset = 11h) [reset = 3Ch]
CONFIG is shown in Figure 7-36 and described in Table 7-28.
Return to Table 7-9.
Figure 7-36. CONFIG Register
7
6
5
4
3
2
1
0
STARTUP_DEL SHUTDOWN_D
CLKIN_PD
EN3_PD
EN2_PD
EN1_PD
TDIE_WARN_L EN_SPREAD_
AY_SEL
ELAY_SEL
EVEL
SPEC
R/W-0h
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-0h
Table 7-28. CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
STARTUP_DELAY_SEL
R/W
0h
Startup delays from control signal:
0 – 0 ms – 7.5 ms with 0.5ms steps
1 – 0ms – 15ms with 1ms steps
(Default from OTP memory)
6
5
4
3
2
1
0
SHUTDOWN_DELAY_SE R/W
L
0h
1h
1h
1h
1h
0h
0h
Shutdown delays from from signal:
0 – 0ms – 7.5ms with 0.5ms steps
1 – 0ms – 15ms with 1ms steps
(Default from OTP memory)
CLKIN_PD
R/W
R/W
R/W
R/W
R/W
R/W
Selects the pull down resistor on the CLKIN input pin.
0 – Pull-down resistor is disabled.
1 – Pull-down resistor is enabled.
(Default from OTP memory)
EN3_PD
Selects the pull down resistor on the EN3 pin:
0 – Pull-down resistor is disabled
1 – Pull-down resistor is enabled
(Default from OTP memory)
EN2_PD
Selects the pull down resistor on the EN2 pin:
0 – Pull-down resistor is disabled
1 – Pull-down resistor is enabled
(Default from OTP memory)
EN1_PD
Selects the pull down resistor on the EN1 pin:
0 – Pull-down resistor is disabled
1 – Pull-down resistor is enabled
(Default from OTP memory)
TDIE_WARN_LEVEL
EN_SPREAD_SPEC
Thermal warning threshold level.
0 – 125°C
1 – 140°C.
(Default from OTP memory)
Enable spread spectrum feature for Buck and Boost converters.
0 – Disabled
1 – Enabled
(Default from OTP memory)
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7.6.1.1.19 PLL_CTRL Register (Offset = 12h) [reset = 2h]
PLL_CTRL is shown in Figure 7-37 and described in Table 7-29.
Return to Table 7-9.
Figure 7-37. PLL_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
EN_PLL
R/W-0h
EN_FRAC_DIV
R/W-0h
EXT_CLK_FREQ
R/W-2h
Table 7-29. PLL_CTRL Register Field Descriptions
Bit
7
Field
RESERVED
Type
R/W
R/W
Reset
Description
0h
6
EN_PLL
0h
Selection of external clock and PLL operation:
0 – Forced to internal RC oscillator. PLL disabled.
1 – PLL is enabled in STANDBY and ACTIVE modes. Automatic
external clock use when available, interrupt generated if external
clock appears or disappears.
(Default from OTP memory)
5
EN_FRAC_DIV
R/W
R/W
0h
2h
This bit must be set to '0'.
4-0
EXT_CLK_FREQ
Frequency of the external clock (CLKIN):
0x00 – 1 MHz
0x01 – 2 MHz
0x02 – 3 MHz
...
0x16 – 23 MHz
0x17 – 24 MHz
0x18...0x1F – Reserved
See electrical specification for input clock frequency tolerance.
(Default from OTP memory) Note: To ensure proper operation of
PLL, EXT_CLK_FREQ value must not be changed when PLL is
enabled.
7.6.1.1.20 PGOOD_CTRL Register (Offset = 13h) [reset = 0h]
PGOOD_CTRL is shown in Figure 7-38 and described in Table 7-30.
Return to Table 7-9.
Figure 7-38. PGOOD_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
PGOOD_WIND EN_PGOOD_V EN_PGOOD_V EN_PGOOD_V EN_PGOOD_B EN_PGOOD_B EN_PGOOD_B
OW
ANA
MON2
MON1
OOST
UCK1
UCK0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 7-30. PGOOD_CTRL Register Field Descriptions
Bit
7
Field
RESERVED
Type
R/W
R/W
Reset
Description
0h
6
PGOOD_WINDOW
0h
Voltage monitoring method for PG0 and PG1 signals:
0 - Only undervoltage monitoring.
1 - Overvoltage and undervoltage monitoring.
(Default from OTP memory) Note: Changing this value during
operation may cause interrupt.
5
EN_PGOOD_VANA
R/W
0h
Enable powergood diagnostics for VANA
0 – Disabled
1 – Enabled
(Default from OTP memory) Note: Changing this value during
operation may cause interrupt.
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Table 7-30. PGOOD_CTRL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
EN_PGOOD_VMON2
R/W
0h
Enable powergood diagnostics for VMON2
0 – Disabled
1 – Enabled
(Default from OTP memory) Note: Changing this value during
operation may cause interrupt.
3
2
1
0
EN_PGOOD_VMON1
EN_PGOOD_BOOST
EN_PGOOD_BUCK1
EN_PGOOD_BUCK0
R/W
R/W
R/W
R/W
0h
0h
0h
0h
Enable powergood diagnostics for VMON1
0 – Disabled
1 – Enabled
(Default from OTP memory) Note: Changing this value during
operation may cause interrupt.
Enable powergood diagnostics for Boost
0 – Disabled
1 – Enabled
(Default from OTP memory) Note: Changing this value during
operation may cause interrupt.
Enable powergood diagnostics for Buck1
0 – Disabled
1 – Enabled
(Default from OTP memory) Note: Changing this value during
operation may cause interrupt.
Enable powergood diagnostics for Buck0
0 – Disabled
1 – Enabled
(Default from OTP memory) Note: Changing this value during
operation may cause interrupt.
7.6.1.1.21 PGOOD_LEVEL_1 Register (Offset = 14h) [reset = 0h]
PGOOD_LEVEL_1 is shown in Figure 7-39 and described in Table 7-31.
Return to Table 7-9.
Figure 7-39. PGOOD_LEVEL_1 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
VMON1_WINDOW
R/W-0h
VMON1_THRESHOLD
R/W-0h
Table 7-31. PGOOD_LEVEL_1 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-5
4-3
RESERVED
0h
VMON1_WINDOW
0h
Overvoltage and undervoltage threshold levels for VMON1:
0x0 – ±2%
0x1 – ±3%
0x2 – ±4%
0x3 – ±6%
(Default from OTP memory)
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Table 7-31. PGOOD_LEVEL_1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2-0
VMON1_THRESHOLD
R/W
0h
Threshold voltage for VMON1 input:
0x0 – 0.65V (high impedance input, external resistive divider can be
used)
0x1 – 0.80 V
0x2 – 1.00 V
0x3 – 1.10 V
0x4 – 1.20 V
0x5 – 1.30 V
0x6 – 1.80 V
0x7 – 1.80 V
To monitor any other voltage level, select 0x0 and use an external
resistive divider to scale down to 0.65 V. For other than 0x0 VMONx
input is low impedance (internal resistive divider enabled).
(Default from OTP memory)
7.6.1.1.22 PGOOD_LEVEL_2 Register (Offset = 15h) [reset = 0h]
PGOOD_LEVEL_2 is shown in Figure 7-40 and described in Table 7-32.
Return to Table 7-9.
Figure 7-40. PGOOD_LEVEL_2 Register
7
6
5
4
3
2
1
0
VANA_WINDOW
VANA_THRES
HOLD
VMON2_WINDOW
R/W-0h
VMON2_THRESHOLD
R/W-0h
R/W-0h
R/W-0h
Table 7-32. PGOOD_LEVEL_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
VANA_WINDOW
R/W
0h
Overvoltage and undervoltage threshold levels for VANA:
0x0 – ±4%
0x1 – ±5%
0x2 – ±10%
0x3 – ±10%
(Default from OTP memory)
5
VANA_THRESHOLD
VMON2_WINDOW
R/W
R/W
0h
0h
Threshold voltage for VANA input:
0 – 3.3 V
1 – 5.0 V
(Default from OTP memory)
4-3
Overvoltage and undervoltage threshold levels for VMON2:
0x0 – ±2%
0x1 – ±3%
0x2 – ±4%
0x3 – ±6%
(Default from OTP memory)
2-0
VMON2_THRESHOLD
R/W
0h
Threshold voltage for VMON2 input:
0x0 – 0.65 V (high impedance input, external resistive divider can be
used)
0x1 – 0.80 V
0x2 – 1.00 V
0x3 – 1.10 V
0x4 – 1.20 V
0x5 – 1.30 V
0x6 – 1.80 V
0x7 – 1.80 V
To monitor any other voltage level, select 0x0 and use an external
resistive divider to scale down to 0.65 V. For other than 0x0 VMONx
input is low impedance (internal resistive divider enabled).
(Default from OTP memory)
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7.6.1.1.23 PGOOD_LEVEL_3 Register (Offset = 16h) [reset = 0h]
PGOOD_LEVEL_3 is shown in Figure 7-41 and described in Table 7-33.
Return to Table 7-9.
Figure 7-41. PGOOD_LEVEL_3 Register
7
6
5
4
3
2
1
0
BOOST_WINDOW
R/W-0h
BOOST_THRESHOLD
R/W-0h
BUCK1_WINDOW
R/W-0h
BUCK0_WINDOW
R/W-0h
Table 7-33. PGOOD_LEVEL_3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
BOOST_WINDOW
R/W
0h
Undervoltage or overvoltage threshold levels for Boost:
0x0 – ±2%
0x1 – ±4%
0x2 – ±6%
0x3 – ±8%
(Default from OTP memory)
5-4
3-2
BOOST_THRESHOLD
BUCK1_WINDOW
R/W
R/W
0h
0h
(Default from OTP memory)
Overvoltage and undervoltage threshold levels for Buck1:
0x0 – ±30 mV
0x1 – ±50 mV
0x2 – ±70 mV
0x3 – ±90 mV
(Default from OTP memory)
1-0
BUCK0_WINDOW
R/W
0h
Overvoltage and undervoltage threshold levels for Buck0:
0x0 – ±30 mV
0x1 – ±50 mV
0x2 – ±70 mV
0x3 – ±90 mV
(Default from OTP memory)
7.6.1.1.24 PG_CTRL Register (Offset = 17h) [reset = 2h]
PG_CTRL is shown in Figure 7-42 and described in Table 7-34.
Return to Table 7-9.
Figure 7-42. PG_CTRL Register
7
6
5
4
3
2
1
0
PG1_MODE
PGOOD_FAUL
T_GATES_PG1
RESERVED
PG1_POL
PG0_MODE
PGOOD_FAUL
T_GATES_PG0
PG0_OD
PG0_POL
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-1h
R/W-0h
Table 7-34. PG_CTRL Register Field Descriptions
Bit
Field
PG1_MODE
Type
Reset
Description
7
R/W
0h
Operating mode for PG1 signal:
0 – Detecting unusual situations
1 – Showing when requested outputs are not valid.
(Default from OTP memory)
6
5
PGOOD_FAULT_GATES_ R/W
PG1
0h
0h
Type of operation for PG1 signal:
0 – Indicates live status of monitored voltage outputs.
1 – Indicates status of PG1_FAULT register, inactive if at least one of
PG1_FAULT_x bit
is inactive.
(Default from OTP memory)
RESERVED
R/W
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Table 7-34. PG_CTRL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
PG1_POL
R/W
0h
PG1 signal polarity.
0 – PG1 signal high when monitored outputs are valid
1 – PG1 signal low when monitored outputs are valid
(Default from OTP memory)
3
2
PG0_MODE
R/W
0h
0h
Operating mode for PG0 signal:
0 – Detecting unusual situations
1 – Showing when requested outputs are not valid.
(Default from OTP memory)
PGOOD_FAULT_GATES_ R/W
PG0
Type of operation for PG0 signal:
0 – Indicates live status of monitored voltage outputs.
1 – Indicates status of PG0_FAULT register, inactive if at least one of
PG0_FAULT_x bit
is inactive.
(Default from OTP memory)
1
0
PG0_OD
R/W
R/W
1h
0h
PG0 signal type:
0 – Push-pull output (VANA level)
1 – Open-drain output
(Default from OTP memory)
PG0_POL
PG0 signal polarity.
0 – PG0 signal high when monitored outputs are valid
1 – PG0 signal low when monitored outputs are valid
(Default from OTP memory)
7.6.1.1.25 PG0_CTRL Register (Offset = 18h) [reset = 0h]
PG0_CTRL is shown in Figure 7-43 and described in Table 7-35.
Return to Table 7-9.
Figure 7-43. PG0_CTRL Register
7
6
5
4
3
2
1
0
PG0_RISE_DE SEL_PG0_TWA SEL_PG0_VAN SEL_PG0_VM SEL_PG0_VM SEL_PG0_BOO SEL_PG0_BUC SEL_PG0_BUC
LAY
RN
A
ON2
ON1
ST
K1
K0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 7-35. PG0_CTRL Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
Description
PG0_RISE_DELAY
SEL_PG0_TWARN
0h
0 – PG0 rise is not delayed 1 – PG0 rise is delayed 11 ms
6
0h
PG0 control from thermal warning:
0 - Masked
1 – Affecting PGOOD
(Default from OTP memory)
5
4
3
SEL_PG0_VANA
SEL_PG0_VMON2
SEL_PG0_VMON1
R/W
R/W
R/W
0h
0h
0h
PG0 signal source control from VANA
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
PG0 signal source control from VMON2
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
PG0 signal source control from VMON1
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
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Table 7-35. PG0_CTRL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
SEL_PG0_BOOST
R/W
0h
PG0 signal source control from Boost
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
1
0
SEL_PG0_BUCK1
SEL_PG0_BUCK0
R/W
R/W
0h
0h
PG0 signal source control from Buck1
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
PG0 signal source control from Buck0
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
7.6.1.1.26 PG0_FAULT Register (Offset = 19h) [reset = 0h]
PG0_FAULT is shown in Figure 7-44 and described in Table 7-36.
Return to Table 7-9.
Figure 7-44. PG0_FAULT Register
7
6
5
4
3
2
1
0
RESERVED
PG0_FAULT_T PG0_FAULT_V PG0_FAULT_V PG0_FAULT_V PG0_FAULT_B PG0_FAULT_B PG0_FAULT_B
WARN
ANA
MON2
MON1
OOST
UCK1
UCK0
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
Table 7-36. PG0_FAULT Register Field Descriptions
Bit
7
Field
RESERVED
Type
Reset
Description
R
0h
6
PG0_FAULT_TWARN
PG0_FAULT_VANA
PG0_FAULT_VMON2
PG0_FAULT_VMON1
PG0_FAULT_BOOST
PG0_FAULT_BUCK1
R
0h
Source for PG0 inactive signal:
0 – TWARN has not set PG0 signal inactive.
1 – TWARN is selected for PG0 signal and it has set PG0 signal
inactive. This bit can be cleared by writing '1' to this bit when TWARN
is valid.
5
4
3
2
1
R
R
R
R
R
0h
0h
0h
0h
0h
Source for PG0 inactive signal:
0 – VANA has not set PG0 signal inactive.
1 –VANA is selected for PG0 signal and it has set PG0 signal
inactive. This bit can be cleared by writing '1' to this bit when VANA
input is valid.
Source for PG0 inactive signal:
0 – VMON2 has not set PG0 signal inactive.
1 – VMON2 is selected for PG0 signal and it has set PG0 signal
inactive. This bit can be cleared by writing '1' to this bit when VMON2
input is valid.
Source for PG0 inactive signal:
0 – VMON1 has not set PG0 signal inactive.
1 – VMON1 is selected for PG0 signal and it has set PG0 signal
inactive. This bit can be cleared by writing '1' to this bit when VMON1
input is valid.
Source for PG0 inactive signal:
0 – Boost has not set PG0 signal inactive.
1 – Boost is selected for PG0 signal and it has set PG0 signal
inactive. This bit can be cleared by writing '1' to this bit when Boost
output is valid.
Source for PG0 inactive signal:
0 – Buck1 has not set PG0 signal inactive.
1 – Buck1 is selected for PG0 signal and it has set PG0 signal
inactive. This bit can be cleared by writing '1' to this bit when Buck1
output is valid.
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Table 7-36. PG0_FAULT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
PG0_FAULT_BUCK0
R
0h
Source for PG0 inactive signal:
0 – Buck0 has not set PG0 signal inactive.
1 – Buck0 is selected for PG0 signal and it has set PG0 signal
inactive. This bit can be cleared by writing '1' to this bit when Buck0
output is valid.
7.6.1.1.27 PG1_CTRL Register (Offset = 1Ah) [reset = 0h]
PG1_CTRL is shown in Figure 7-45 and described in Table 7-37.
Return to Table 7-9.
Figure 7-45. PG1_CTRL Register
7
6
5
4
3
2
1
0
PG1_RISE_DE SEL_PG1_TWA SEL_PG1_VAN SEL_PG1_VM SEL_PG1_VM SEL_PG1_BOO SEL_PG1_BUC SEL_PG1_BUC
LAY
RN
A
ON2
ON1
ST
K1
K0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 7-37. PG1_CTRL Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
Description
PG1_RISE_DELAY
SEL_PG1_TWARN
0h
0 – PG1 rise is not delayed 1 – PG1 rise is delayed 11ms
6
0h
PG1 control from thermal warning:
0 – Masked
1 – Affecting PGOOD
(Default from OTP memory)
5
4
3
2
1
0
SEL_PG1_VANA
SEL_PG1_VMON2
SEL_PG1_VMON1
SEL_PG1_BOOST
SEL_PG1_BUCK1
SEL_PG1_BUCK0
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
PG1 signal source control from VANA
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
PG1 signal source control from VMON2
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
PG1 signal source control from VMON1
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
PG1 signal source control from Boost
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
PG1 signal source control from Buck1
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
PG1 signal source control from Buck0
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
7.6.1.1.28 PG1_FAULT Register (Offset = 1Bh) [reset = 0h]
PG1_FAULT is shown in Figure 7-46 and described in Table 7-38.
Return to Table 7-9.
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Figure 7-46. PG1_FAULT Register
7
6
5
4
3
2
1
0
RESERVED
PG1_FAULT_T PG1_FAULT_V PG1_FAULT_V PG1_FAULT_V PG1_FAULT_B PG1_FAULT_B PG1_FAULT_B
WARN
ANA
MON2
MON1
OOST
UCK1
UCK0
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
Table 7-38. PG1_FAULT Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
RESERVED
R
0h
PG1_FAULT_TWARN
R
0h
Source for PG1 inactive signal:
0 – TWARN has not set PG1 signal inactive.
1 – TWARN is selected for PG1 signal and it has set PG1 signal
inactive. This bit can be cleared by writing '1' to this bit when TWARN
is valid.
5
4
3
2
1
0
PG1_FAULT_VANA
PG1_FAULT_VMON2
PG1_FAULT_VMON1
PG1_FAULT_BOOST
PG1_FAULT_BUCK1
PG1_FAULT_BUCK0
R
R
R
R
R
R
0h
0h
0h
0h
0h
0h
Source for PG1 inactive signal:
0 – VANA has not set PG1 signal inactive.
1 – VANA is selected for PG1 signal and it has set PG1 signal
inactive. This bit can be cleared by writing '1' to this bit when VANA
input is valid.
Source for PG1 inactive signal:
0 – VMON2 has not set PG1 signal inactive.
1 – VMON2 is selected for PG1 signal and it has set PG1 signal
inactive. This bit can be cleared by writing '1' to this bit when VMON2
input is valid.
Source for PG1 inactive signal:
0 – VMON1 has not set PG1 signal inactive.
1 – VMON1 is selected for PG1 signal and it has set PG1 signal
inactive. This bit can be cleared by writing '1' to this bit when VMON1
input is valid.
Source for PG1 inactive signal:
0 – Boost has not set PG1 signal inactive.
1 – Boost is selected for PG1 signal and it has set PG1 signal
inactive. This bit can be cleared by writing '1' to this bit when Boost
output is valid.
Source for PG1 inactive signal:
0 – Buck1 has not set PG1 signal inactive.
1 – Buck1 is selected for PG1 signal and it has set PG1 signal
inactive. This bit can be cleared by writing '1' to this bit when Buck1
output is valid.
Source for PG1 inactive signal:
0 – Buck0 has not set PG1 signal inactive.
1 – Buck0 is selected for PG1 signal and it has set PG1 signal
inactive. This bit can be cleared by writing '1' to this bit when Buck0
output is valid.
7.6.1.1.29 WD_CTRL_1 Register (Offset = 1Ch) [reset = 0h]
WD_CTRL_1 is shown in Figure 7-47 and described in Table 7-39.
Return to Table 7-9.
Figure 7-47. WD_CTRL_1 Register
7
6
5
4
3
2
1
0
WD_CLOSE_TIME
R/W-0h
WD_OPEN_TIME
R/W-0h
WD_LONG_OPEN_TIME
R/W-0h
WD_RESET_CNTR_SEL
R/W-0h
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Table 7-39. WD_CTRL_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
WD_CLOSE_TIME
R/W
0h
Watchdog close window time select.
00 – 10 ms
01 – 20 ms
10 – 50 ms
11 – 100 ms
(Default from OTP memory)
5-4
3-2
1-0
WD_OPEN_TIME
R/W
0h
0h
0h
Watchdog open window time select.
00 – 20 ms
01 – 100 ms
10 – 200 ms
11 – 600 ms
(Default from OTP memory)
WD_LONG_OPEN_TIME R/W
WD_RESET_CNTR_SEL R/W
Watchdog long open window time select.
00 – 200 ms
01 – 600 ms
10 – 2000 ms
11 – 5000 ms
(Default from OTP memory)
Watchdog reset counter threshold select. After the selected number
of reset (WDR) pulses system restart sequence is initiated.
00 – system restart disabled
01 – 1
10 – 2
11 – 4
(Default from OTP memory)
7.6.1.1.30 WD_CTRL_2 Register (Offset = 1Dh) [reset = 1h]
WD_CTRL_2 is shown in Figure 7-48 and described in Table 7-40.
Return to Table 7-9.
Figure 7-48. WD_CTRL_2 Register
7
6
5
4
3
2
1
0
WD_LOCK
RESERVED
R/W-0h
WD_SYS_RES WD_EN_OTP_
WDI_PD
WDR_POL
WDR_OD
TART_FLAG_M
ODE
READ
R-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-1h
Table 7-40. WD_CTRL_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
WD_LOCK
R
0h
Lock bit for watchdog controls. Locks all controls to watchdog in
registers WD_CTRL_1, WD_CTRL_2. Lock bit also locks itself.
Once lock bit is written 1 it cannot be written 0. Only reset can
clear it. 0 – Not locked 1 – Locked WD_STATUS register is not
affected by WD_LOCK bit. WD_SYSTEM_RESTART_FLAG and
WD_RESET_CNTR_STATUS can be cleared even if WD_LOCK=1.
6-5
4
RESERVED
R/W
0h
0h
WD_SYS_RESTART_FLA R/W
G_MODE
WD_SYSTEM_RESTART_FLAG mode select. 0 -
WD_SYSTEM_RESTART_FLAG is only a status bit. 1 –
WD_SYSTEM_RESTART_FLAG prevents further system restarts
until it is cleared. (Default from OTP memory)
3
WD_EN_OTP_READ
R/W
0h
Read OTP during system restart sequence 0 – OTP read not
enabled during system restart sequence 1 – OTP read enabled
during system restart sequence (Default from OTP memory)
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Table 7-40. WD_CTRL_2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
WDI_PD
R/W
0h
Selects the pull down resistor on the WDI pin:
0 – Pull-down resistor is disabled
1 – Pull-down resistor is enabled
(Default from OTP memory)
1
0
WDR_POL
WDR_OD
R/W
R/W
0h
1h
Watchdog reset output (WDR) polarity select 0 – Active high 1 –
Active low (Default from OTP memory)
Watchdog reset output (WDR) signal type 0 – Push-pull output
(VANA level) 1 – Open-drain output (Default from OTP memory)
7.6.1.1.31 WD_STATUS Register (Offset = 1Eh) [reset = 0h]
WD_STATUS is shown in Figure 7-49 and described in Table 7-41.
Return to Table 7-9.
Figure 7-49. WD_STATUS Register
7
6
5
4
3
2
1
0
RESERVED
WD_CLR_SYS WD_SYSTEM_ WD_CLR_RES
WD_RESET_CNTR_STATUS
TEM_RESTART RESTART_FLA
ET_CNTR
_FLAG
G
R/W-0h
R-0h
R-0h
R-0h
R-0h
Table 7-41. WD_STATUS Register Field Descriptions
Bit
Field
Type
R/W
R
Reset
Description
7-5
4
RESERVED
0h
WD_CLR_SYSTEM_RES
TART_FLAG
0h
Clear bit for WD_SYSTEM_RESTART_FLAG. Write 1 to generate a
clear pulse. Reg bit value returns to 0 after clearing is finished.
3
WD_SYSTEM_RESTART
_FLAG
R
R
0h
Watchdog requested system restart has occurred. Can be cleared by
writing WD_CLR_SYSTEM_RESTART_FLAG bit 1.
2
WD_CLR_RESET_CNTR
0h
0h
Watchdog reset counter clear. Write 1 to generate a clear pulse.
Current status of watchdog reset counter.
1-0
WD_RESET_CNTR_STAT R
US
7.6.1.1.32 RESET Register (Offset = 1Fh) [reset = 0h]
RESET is shown in Figure 7-50 and described in Table 7-42.
Return to Table 7-9.
Figure 7-50. RESET Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
SW_RESET
R-0h
Table 7-42. RESET Register Field Descriptions
Bit
Field
Type
R/W
R
Reset
Description
7-1
0
RESERVED
SW_RESET
0h
0h
Software commanded reset. When written to 1, the registers will be
reset to default values and OTP memory is read.
The bit is automatically cleared.
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7.6.1.1.33 INT_TOP_1 Register (Offset = 20h) [reset = 0h]
INT_TOP_1 is shown in Figure 7-51 and described in Table 7-43.
Return to Table 7-9.
Figure 7-51. INT_TOP_1 Register
7
6
5
4
3
2
1
0
I_MEAS_INT
DIAG_INT
BOOST_INT
BUCK_INT
R-0h
SYNC_CLK_IN TDIE_SD_INT TDIE_WARN_I
OVP_INT
T
NT
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
Table 7-43. INT_TOP_1 Register Field Descriptions
Bit
Field
I_MEAS_INT
Type
Reset
Description
7
R
0h
Latched status bit indicating that the load current measurement
result is available in I_LOAD_1 and I_LOAD_2 registers.
Write 1 to clear interrupt.
6
5
4
DIAG_INT
R
R
R
0h
0h
0h
Interrupt indicating that INT_DIAG register has a pending interrupt.
The reason for the interrupt is indicated in INT_DIAG register.
This bit is cleared automatically when INT_DIAG register is cleared
to 0x00.
BOOST_INT
BUCK_INT
Interrupt indicating that BOOST have a pending interrupt. The
reason for the interrupt is indicated in INT_BOOST register.
This bit is cleared automatically when INT_BOOST register is
cleared to 0x00.
Interrupt indicating that BUCK0 or BUCK1 have a pending interrupt.
The reason for the interrupt is indicated in INT_BUCK register.
This bit is cleared automatically when INT_BUCK register is cleared
to 0x00.
3
2
SYNC_CLK_INT
TDIE_SD_INT
R
R
0h
0h
Latched status bit indicating that the external clock frequency
became valid or invalid.
Write 1 to clear interrupt.
Latched status bit indicating that the die junction temperature has
exceeded the thermal shutdown level. The converters have been
disabled if they were enabled. The converters cannot be enabled if
this bit is active. The actual status of the thermal warning is indicated
by TDIE_SD_STAT bit in TOP_STATUS register.
Write 1 to clear interrupt. Clearing TSD interrupt automatically re-
enables converters. Clearing this interrupt will also clear thermal
warning status.
1
0
TDIE_WARN_INT
OVP_INT
R
R
0h
0h
Latched status bit indicating that the die junction temperature has
exceeded the thermal warning level. The actual status of the thermal
warning is indicated by TDIE_WARN_STAT bit in TOP_STATUS
register.
Write 1 to clear interrupt.
Latched status bit indicating that the input voltage has exceeded the
over-voltage detection level. The actual status of the over-voltage is
indicated by OVP bit in TOP_STATUS register.
Write 1 to clear interrupt.
7.6.1.1.34 INT_TOP_2 Register (Offset = 21h) [reset = 0h]
INT_TOP_2 is shown in Figure 7-52 and described in Table 7-44.
Return to Table 7-9.
Figure 7-52. INT_TOP_2 Register
7
6
5
4
3
2
1
0
RESERVED
RESET_REG_I
NT
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Figure 7-52. INT_TOP_2 Register (continued)
R/W-0h
R-0h
Table 7-44. INT_TOP_2 Register Field Descriptions
Bit
7-1
0
Field
Type
R/W
R
Reset
Description
RESERVED
RESET_REG_INT
0h
0h
Latched status bit indicating that either VANA supply voltage has
been below undervoltage threshold level or the host has requested a
reset (SW_RESET bit in RESET register). The converters have been
disabled, and registers are reset to default values and the normal
startup procedure is done.
Write 1 to clear interrupt.
7.6.1.1.35 INT_BUCK Register (Offset = 22h) [reset = 0h]
INT_BUCK is shown in Figure 7-53 and described in Table 7-45.
Return to Table 7-9.
Figure 7-53. INT_BUCK Register
7
6
5
4
3
2
1
0
RESERVED
BUCK1_PG_IN BUCK1_SC_IN BUCK1_ILIM_I
RESERVED
R/W-0h
BUCK0_PG_IN BUCK0_SC_IN BUCK0_ILIM_I
T
T
NT
T
T
NT
R/W-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
Table 7-45. INT_BUCK Register Field Descriptions
Bit
7
Field
RESERVED
Type
R/W
R
Reset
Description
0h
6
BUCK1_PG_INT
0h
Latched status bit indicating that BUCK1 powergood event has been
detected.
Write 1 to clear.
5
4
BUCK1_SC_INT
R
R
0h
0h
Latched status bit indicating that the BUCK1 output voltage has
fallen below 0.35 V level during operation or BUCK1 output didn't
reach 0.35 V level in 1 ms from enable.
Write 1 to clear.
BUCK1_ILIM_INT
Latched status bit indicating that BUCK1 output current limit has
been triggered.
Write 1 to clear.
3
2
RESERVED
R/W
R
0h
0h
BUCK0_PG_INT
Latched status bit indicating that BUCK0 powergood event has been
detected.
Write 1 to clear.
1
0
BUCK0_SC_INT
BUCK0_ILIM_INT
R
R
0h
0h
Latched status bit indicating that the BUCK0 output voltage has
fallen below 0.35 V level during operation or BUCK0 output didn't
reach 0.35 V level in 1 ms from enable.
Write 1 to clear.
Latched status bit indicating that BUCK0 output current limit has
been triggered.
Write 1 to clear.
7.6.1.1.36 INT_BOOST Register (Offset = 23h) [reset = 0h]
INT_BOOST is shown in Figure 7-54 and described in Table 7-46.
Return to Table 7-9.
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Figure 7-54. INT_BOOST Register
7
6
5
4
3
2
1
0
RESERVED
BOOST_PG_IN BOOST_SC_IN BOOST_ILIM_I
T
T
NT
R/W-0h
R-0h
R-0h
R-0h
Table 7-46. INT_BOOST Register Field Descriptions
Bit
7-3
2
Field
Type
R/W
R
Reset
Description
RESERVED
0h
BOOST_PG_INT
0h
Latched status bit indicating that Boost powergood event has been
detected.
Write 1 to clear.
1
0
BOOST_SC_INT
BOOST_ILIM_INT
R
R
0h
0h
Latched status bit indicating that the Boost output voltage has fallen
to input voltage level or below 2.5 V level during operation or BOOST
output didn't reach 2.5 V level in 1 ms from enable.
Write 1 to clear.
Latched status bit indicating that Boost output current limit has been
triggered.
Write 1 to clear.
7.6.1.1.37 INT_DIAG Register (Offset = 24h) [reset = 0h]
INT_DIAG is shown in Figure 7-55 and described in Table 7-47.
Return to Table 7-9.
Figure 7-55. INT_DIAG Register
7
6
5
4
3
2
1
0
RESERVED
VMON2_PG_IN RESERVED VMON1_PG_IN RESERVED
VANA_PG_INT
T
T
R/W-0h
R-0h
R/W-0h
R-0h
R/W-0h
R-0h
Table 7-47. INT_DIAG Register Field Descriptions
Bit
Field
Type
R/W
R
Reset
Description
7-5
4
RESERVED
0h
VMON2_PG_INT
0h
Latched status bit indicating that VMON2 powergood event has been
detected.
Write 1 to clear.
3
2
RESERVED
R/W
R
0h
0h
VMON1_PG_INT
Latched status bit indicating that VMON1 powergood event has been
detected.
Write 1 to clear.
1
0
RESERVED
R/W
R
0h
0h
VANA_PG_INT
Latched status bit indicating that VANA powergood event has been
detected.
Write 1 to clear.
7.6.1.1.38 TOP_STATUS Register (Offset = 25h) [reset = 0h]
TOP_STATUS is shown in Figure 7-56 and described in Table 7-48.
Return to Table 7-9.
Figure 7-56. TOP_STATUS Register
7
6
5
4
3
2
1
0
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Figure 7-56. TOP_STATUS Register (continued)
RESERVED
SYNC_CLK_ST TDIE_SD_STAT TDIE_WARN_S
OVP_STAT
R-0h
AT
TAT
R-0h
R-0h
R-0h
R-0h
Table 7-48. TOP_STATUS Register Field Descriptions
Bit
7-4
3
Field
Type
Reset
Description
RESERVED
SYNC_CLK_STAT
R
0h
R
0h
Status bit indicating the status of external clock (CLKIN):
0 – External clock frequency is valid
1 – External clock frequency is not valid.
2
1
0
TDIE_SD_STAT
TDIE_WARN_STAT
OVP_STAT
R
R
R
0h
0h
0h
Status bit indicating the status of thermal shutdown:
0 – Die temperature below thermal shutdown level
1 – Die temperature above thermal shutdown level.
Status bit indicating the status of thermal warning:
0 – Die temperature below thermal warning level
1 – Die temperature above thermal warning level.
Status bit indicating the status of input overvoltage monitoring:
0 – Input voltage below overvoltage threshold level
1 – Input voltage above overvoltage threshold level.
7.6.1.1.39 BUCK_STATUS Register (Offset = 26h) [reset = 0h]
BUCK_STATUS is shown in Figure 7-57 and described in Table 7-49.
Return to Table 7-9.
Figure 7-57. BUCK_STATUS Register
7
6
5
4
3
2
1
0
BUCK1_STAT BUCK1_PG_ST
AT
BUCK1_ILIM_S BUCK0_STAT BUCK0_PG_ST
BUCK0_ILIM_S
TAT
TAT
AT
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
Table 7-49. BUCK_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
4
3
2
0
BUCK1_STAT
R
0h
Status bit indicating the enable or disable status of BUCK1:
0 – BUCK1 converter is disabled
1 – BUCK1 converter is enabled.
BUCK1_PG_STAT
BUCK1_ILIM_STAT
BUCK0_STAT
R
R
R
R
R
0h
0h
0h
0h
0h
Status bit indicating BUCK1 output voltage validity (raw status)
0 – BUCK1 output is not valid
1 – BUCK1 output is valid.
Status bit indicating BUCK1 current limit status (raw status)
0 – BUCK1 output current is below current limit threshold level
1 – BUCK1 output current is at current limit threshold level.
Status bit indicating the enable or disable status of BUCK0:
0 – BUCK0 converter is disabled
1 – BUCK0 converter is enabled.
BUCK0_PG_STAT
BUCK0_ILIM_STAT
Status bit indicating BUCK0 output voltage validity (raw status)
0 – BUCK0 output is not valid
1 – BUCK0 output is valid.
Status bit indicating BUCK0 current limit status (raw status)
0 – BUCK0 output current is below current limit threshold level
1 – BUCK0 output current is at current limit threshold level.
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7.6.1.1.40 BOOST_STATUS Register (Offset = 27h) [reset = 0h]
BOOST_STATUS is shown in Figure 7-58 and described in Table 7-50.
Return to Table 7-9.
Figure 7-58. BOOST_STATUS Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
BOOST_STAT BOOST_PG_S
TAT
BOOST_ILIM_S
TAT
R-0h
R-0h
R-0h
Table 7-50. BOOST_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3
RESERVED
R
0h
BOOST_STAT
R
0h
Status bit indicating the enable/disable status of Boost:
0 – Boost converter is disabled
1 – Boost converter is enabled.
2
0
BOOST_PG_STAT
BOOST_ILIM_STAT
R
R
0h
0h
Status bit indicating Boost output voltage validity (raw status)
0 – Boost output is not valid
1 – Boost output is valid.
Status bit indicating Boost current limit status (raw status)
0 – Boost output current is below current limit threshold level
1 – Boost output current is at current limit threshold level.
7.6.1.1.41 DIAG_STATUS Register (Offset = 28h) [reset = 0h]
DIAG_STATUS is shown in Figure 7-59 and described in Table 7-51.
Return to Table 7-9.
Figure 7-59. DIAG_STATUS Register
7
6
5
4
3
2
1
0
RESERVED
VMON2_PG_S
TAT
RESERVED
VMON1_PG_S
TAT
RESERVED
VANA_PG_STA
T
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
Table 7-51. DIAG_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
4
RESERVED
R
0h
VMON2_PG_STAT
R
0h
Status bit indicating VMON2 input voltage validity (raw status)
0 – VMON2 voltage is not valid
1 – VMON2 voltage is valid.
3
2
RESERVED
R
R
0h
0h
VMON1_PG_STAT
Status bit indicating VMON1 input voltage validity (raw status)
0 – VMON1 voltage is not valid
1 – VMON1 voltage is valid.
1
0
RESERVED
R
R
0h
0h
VANA_PG_STAT
Status bit indicating VANA input voltage validity (raw status)
0 – VANA voltage is not valid
1 – VANA voltage is valid.
7.6.1.1.42 TOP_MASK_1 Register (Offset = 29h) [reset = 0h]
TOP_MASK_1 is shown in Figure 7-60 and described in Table 7-52.
Return to Table 7-9.
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Figure 7-60. TOP_MASK_1 Register
7
6
5
4
3
2
1
0
I_MEAS_MASK
RESERVED
SYNC_CLK_M
ASK
RESERVED TDIE_WARN_M RESERVED
ASK
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 7-52. TOP_MASK_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
I_MEAS_MASK
R/W
0h
Masking for load current measurement ready interrupt I_MEAS_INT
in INT_TOP_1 register.
0 – Interrupt generated
1 – Interrupt not generated.
(Default from OTP memory)
6-4
3
RESERVED
R/W
R/W
0h
0h
SYNC_CLK_MASK
Masking for external clock detection interrupt SYNC_CLK_INT in
INT_TOP_1 register:
0 – Interrupt generated
1 – Interrupt not generated.
(Default from OTP memory)
2
1
RESERVED
R/W
R/W
0h
0h
TDIE_WARN_MASK
Masking for thermal warning interrupt TDIE_WARN_INT in
INT_TOP_1 register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect TDIE_WARN_STAT status bit in
TOP_STATUS register.
(Default from OTP memory)
0
RESERVED
R/W
0h
7.6.1.1.43 TOP_MASK_2 Register (Offset = 2Ah) [reset = 1h]
TOP_MASK_2 is shown in Figure 7-61 and described in Table 7-53.
Return to Table 7-9.
Figure 7-61. TOP_MASK_2 Register
7
6
5
4
3
2
1
0
RESERVED
RESET_REG_
MASK
R/W-0h
R/W-1h
Table 7-53. TOP_MASK_2 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-1
0
RESERVED
0h
RESET_REG_MASK
1h
Masking for register reset interrupt RESET_REG_INT in INT_TOP_2
register:
0 – Interrupt generated
1 – Interrupt not generated.
(Default from OTP memory)
7.6.1.1.44 BUCK_MASK Register (Offset = 2Bh) [reset = 0h]
BUCK_MASK is shown in Figure 7-62 and described in Table 7-54.
Return to Table 7-9.
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Figure 7-62. BUCK_MASK Register
7
6
5
4
3
2
1
0
BUCK1_PGF_ BUCK1_PGR_
RESERVED BUCK1_ILIM_M BUCK0_PGF_ BUCK0_PGR_
RESERVED BUCK0_ILIM_M
ASK
MASK
MASK
ASK
MASK
MASK
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 7-54. BUCK_MASK Register Field Descriptions
Bit
Field
Type
Reset
Description
7
BUCK1_PGF_MASK
R/W
0h
Masking of powergood invalid detection for BUCK1 power good
interrupt BUCK1_PG_INT in INT_BUCK register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect BUCK1_PG_STAT status bit in
BUCK_STATUS register.
(Default from OTP memory)
6
BUCK1_PGR_MASK
R/W
0h
Masking of powergood valid detection for BUCK1 power good
interrupt BUCK1_PG_INT in INT_BUCK register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect BUCK1_PG_STAT status bit in
BUCK_STATUS register.
(Default from OTP memory)
5
4
RESERVED
R/W
R/W
0h
0h
BUCK1_ILIM_MASK
Masking for BUCK1 current monitoring interrupt BUCK1_ILIM_INT in
INT_BUCK register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect BUCK1_ILIM_STAT status bit in
BUCK_STATUS register.
(Default from OTP memory)
3
2
BUCK0_PGF_MASK
BUCK0_PGR_MASK
R/W
R/W
0h
0h
Masking of powergood invalid detection for BUCK0 power good
interrupt BUCK0_PG_INT in INT_BUCK register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect BUCK0_PG_STAT status bit in
BUCK_STATUS register.
(Default from OTP memory)
Masking of powergood valid detection for BUCK0 power good
interrupt BUCK0_PG_INT in INT_BUCK register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect BUCK0_PG_STAT status bit in
BUCK_STATUS register.
(Default from OTP memory)
1
0
RESERVED
R/W
R/W
0h
0h
BUCK0_ILIM_MASK
Masking for BUCK0 current monitoring interrupt BUCK0_ILIM_INT in
INT_BUCK register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect BUCK0_ILIM_STAT status bit in
BUCK_STATUS register.
(Default from OTP memory)
7.6.1.1.45 BOOST_MASK Register (Offset = 2Ch) [reset = 0h]
BOOST_MASK is shown in Figure 7-63 and described in Table 7-55.
Return to Table 7-9.
Figure 7-63. BOOST_MASK Register
7
6
5
4
3
2
1
0
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Figure 7-63. BOOST_MASK Register (continued)
RESERVED
BOOST_PGF_ BOOST_PGR_
RESERVED
R/W-0h
BOOST_ILIM_
MASK
MASK
MASK
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 7-55. BOOST_MASK Register Field Descriptions
Bit
7-4
3
Field
Type
R/W
R/W
Reset
Description
RESERVED
BOOST_PGF_MASK
0h
0h
Masking of powergood invalid detection for Boost power good
interrupt BOOST_PG_INT in INT_BOOST register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect BOOST_PG_STAT status bit in
BOOST_STATUS register.
(Default from OTP memory)
2
BOOST_PGR_MASK
R/W
0h
Masking of powergood valid detection for Boost power good interrupt
BOOST_PG_INT in INT_BOOST register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect BOOST_PG_STAT status bit in
BOOST_STATUS register.
(Default from OTP memory)
1
0
RESERVED
R/W
R/W
0h
0h
BOOST_ILIM_MASK
Masking for Boost current monitoring interrupt BOOST_ILIM_INT in
INT_BOOST register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect BOOST_ILIM_STAT status bit in
BOOST_STATUS register.
(Default from OTP memory)
7.6.1.1.46 DIAG_MASK Register (Offset = 2Dh) [reset = 0h]
DIAG_MASK is shown in Figure 7-64 and described in Table 7-56.
Return to Table 7-9.
Figure 7-64. DIAG_MASK Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
VMON2_PGF_ VMON2_PGR_ VMON1_PGF_ VMON1_PGR_ VANA_PGF_M VANA_PGR_M
MASK
MASK
MASK
MASK
ASK
ASK
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 7-56. DIAG_MASK Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-6
5
RESERVED
0h
VMON2_PGF_MASK
0h
Masking of VMON2 invalid detection for powergood interrupt
VMON2_PG_INT in INT_DIAG register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect VMON2_PG_STAT status bit in
DIAG_STATUS register.
(Default from OTP memory)
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Table 7-56. DIAG_MASK Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
VMON2_PGR_MASK
R/W
0h
Masking of VMON2 valid detection for powergood interrupt
VMON2_PG_INT in INT_DIAG register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect VMON2_PG_STAT status bit in
DIAG_STATUS register.
(Default from OTP memory)
3
2
1
0
VMON1_PGF_MASK
VMON1_PGR_MASK
VANA_PGF_MASK
VANA_PGR_MASK
R/W
R/W
R/W
R/W
0h
0h
0h
0h
Masking of VMON1 invalid detection for powergood interrupt
VMON1_PG_INT in INT_DIAG register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect VMON1_PG_STAT status bit in
DIAG_STATUS register.
(Default from OTP memory)
Masking of VMON1 valid detection for powergood interrupt
VMON1_PG_INT in INT_DIAG register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect VMON1_PG_STAT status bit in
DIAG_STATUS register.
(Default from OTP memory)
Masking of VANA invalid detection for powergood interrupt
VANA_PG_INT in INT_DIAG register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect VANA_PG_STAT status bit in DIAG_STATUS
register.
(Default from OTP memory)
Masking of VANA valid detection for powergood interrupt
VANA_PG_INT in INT_DIAG register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect VANA_PG_STAT status bit in DIAG_STATUS
register.
(Default from OTP memory)
7.6.1.1.47 SEL_I_LOAD Register (Offset = 2Eh) [reset = 0h]
SEL_I_LOAD is shown in Figure 7-65 and described in Table 7-57.
Return to Table 7-9.
Figure 7-65. SEL_I_LOAD Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
LOAD_CURRENT_BUCK_SELE
CT
R/W-0h
Table 7-57. SEL_I_LOAD Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
7-2
1-0
R/W
0h
LOAD_CURRENT_BUCK R/W
_SELECT
0h
Start the current measurement on the selected Buck converter:
0 – BUCK0
1 – BUCK1
2 – BUCK0
3 – BUCK1
The measurement is started when register is written.
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7.6.1.1.48 I_LOAD_2 Register (Offset = 2Fh) [reset = 0h]
I_LOAD_2 is shown in Figure 7-66 and described in Table 7-58.
Return to Table 7-9.
Figure 7-66. I_LOAD_2 Register
7
6
5
4
3
2
1
0
RESERVED
BUCK_LOAD_
CURRENT_8
R-0h
R-0h
Table 7-58. I_LOAD_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
RESERVED
R
0h
BUCK_LOAD_CURRENT
_8
R
0h
This register describes the MSB bit of the average load current on
selected converter with a resolution of 20 mA per LSB and maximum
10 A current.
7.6.1.1.49 I_LOAD_1 Register (Offset = 30h) [reset = 0h]
I_LOAD_1 is shown in Figure 7-67 and described in Table 7-59.
Return to Table 7-9.
Figure 7-67. I_LOAD_1 Register
7
6
5
4
3
2
1
0
BUCK_LOAD_CURRENT_7_0
R-0h
Table 7-59. I_LOAD_1 Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
BUCK_LOAD_CURRENT
_7_0
R
0h
This register describes 8 LSB bits of the average load current on
selected converter with a resolution of 20 mA per LSB and maximum
10 A current.
7.6.1.1.50 FREQ_SEL Register (Offset = 31h) [reset = 0h]
FREQ_SEL is shown in Figure 7-68 and described in Table 7-60.
Return to Table 7-9.
Figure 7-68. FREQ_SEL Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
BOOST_FREQ
_SEL
BUCK_FREQ_SEL
R-0h
R-0h
Table 7-60. FREQ_SEL Register Field Descriptions
Bit
Field
Type
R/W
R
Reset
Description
7-3
2
RESERVED
0h
BOOST_FREQ_SEL
0h
Boost switching frequency:
0 – 2 MHz
1 – 4 MHz
(Default from OTP memory)
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Table 7-60. FREQ_SEL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1-0
BUCK_FREQ_SEL
R
0h
Buck0 and Buck1 switching frequency:
0x0 – 2 MHz
0x1 – 3 MHz
0x2 – 4 MHz
0x3 – 4 MHz
(Default from OTP memory)
7.6.1.1.51 BOOST_ILIM_CTRL Register (Offset = 32h) [reset = 0h]
BOOST_ILIM_CTRL is shown in Figure 7-69 and described in Table 7-61.
Return to Table 7-9.
Figure 7-69. BOOST_ILIM_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
BOOST_ILIM
R/W-0h
Table 7-61. BOOST_ILIM_CTRL Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-2
1-0
RESERVED
BOOST_ILIM
0h
0h
Sets the current limit of Boost.
00 – 1.0 A
01 – 1.4 A
10 – 1.9 A
11 – 2.8 A
(Default from OTP memory)
7.6.1.1.52 ECC_STATUS Register (Offset = 33h) [reset = 0h]
ECC_STATUS is shown in Figure 7-70 and described in Table 7-62.
Return to Table 7-9.
Figure 7-70. ECC_STATUS Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
DED
R-0h
SED
R-0h
Table 7-62. ECC_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
1
RESERVED
DED
R
0h
R
0h
OTP error correction status: 0 – No dual errors detected 1 – Dual
errors detected and not corrected
0
SED
R
0h
OTP error correction status: 0 – No single errors detected 1 – Single
errors detected and corrected
7.6.1.1.53 WD_DIS_CTRL_CODE Register (Offset = 34h) [reset = 0h]
WD_DIS_CTRL_CODE is shown in Figure 7-71 and described in Table 7-63.
Return to Table 7-9.
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Figure 7-71. WD_DIS_CTRL_CODE Register
7
6
5
4
3
2
1
0
WD_DIS_UNLOCK_CODE
R-0h
Table 7-63. WD_DIS_CTRL_CODE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
WD_DIS_UNLOCK_COD
E
R
0h
Unlocking WD_DIS_CTRL bit: Set WD_DIS_CTRL_LOCK=0 by
writing 0x87, 0x65, 0x1B by 3 consecutive I2C write sequences to
WD_DIS_CTRL_CODE register.
Locking WD_DIS_CTRL bit: Set WD_DIS_CTRL_LOCK=1 by writing
anything to WD_DIS_CTRL_CODE register or write WD_LOCK=1.
Reading this address returns always 0x00. WD_DIS_CTRL can be
unlocked only if WD_LOCK=0.
7.6.1.1.54 WD_DIS_CONTROL Register (Offset = 35h) [reset = 0h]
WD_DIS_CONTROL is shown in Figure 7-72 and described in Table 7-64.
Return to Table 7-9.
Figure 7-72. WD_DIS_CONTROL Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
WD_DIS_CTRL WD_DIS_CTRL
_LOCK
R-1h
R/W-0h
Table 7-64. WD_DIS_CONTROL Register Field Descriptions
Bit
Field
Type
R/W
R
Reset
Description
7-2
1
RESERVED
0h
WD_DIS_CTRL_LOCK
1h
Lock status for WD_DIS_CTRL bit.
0 – Not locked, WD_DIS_CTRL bit can be written.
1 – Locked, WD_DIS_CTRL bit is locked and cannot be changed.
Lock can be opened by writing 0x87, 0x65, 0x1B by 3
consecutive I2C write sequences to WD_DIS_CTRL_CODE register
if WD_LOCK=0. Lock can be closed by writing anything to
WD_DIS_CTRL_CODE register or writing WD_LOCK=1.
0
WD_DIS_CTRL
R/W
0h
Watchdog disable pin control.
0 – Watchdog cannot be disabled by WD_DIS pin.
1 – Watchdog can be disabled by WD_DIS pin.
(Default from OTP memory)
This bit can be written 1 only if WD_LOCK=0 and
WD_DIS_CTRL_LOCK=0.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The LP87702 is a power-management unit including a boost converter, two step-down converters, and three
general-purpose digital output signals.
8.2 Typical Application
VIN
VIN_B0
VIN_B1
L0
VOUT0
CIN0
CIN1
SW_B0
FB_B0
LOAD
COUT0
VANA
CANA
L1
VOUT1
L2
SW_B1
FB_B1
LOAD
SW_BST
COUT1
NRST
SDA (EN3)
SCL (EN2)
nINT
VOUT2
EN1
VOUT_BST
LOAD
CLKIN (GPO2)
PG0
PG1 (GPO1)
GPO0
COUT2
VMON1
VMON2
WDI
WD_RESET
GNDs
Copyright © 2017, Texas Instruments Incorporated
Figure 8-1. LP87702 Typical Application
8.2.1 Design Requirements
Table 8-1. Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
3.3 V
Output voltages
1.8 V, 1.24 V, 5 V
4 MHz
Switching frequency
8.2.2 Detailed Design Procedure
The performance of the LP87702 device depends greatly on the care taken in designing the printed circuit board
(PCB). The use of low-inductance and low serial-resistance ceramic capacitors is strongly recommended, while
proper grounding is crucial. Attention should be given to decoupling the power supplies. Decoupling capacitors
must be connected close to the device and between the power and ground pins to support high peak currents
being drawn from the system power rail while turning on the switching MOSFETs. Keep input and output traces
as short as possible, because trace inductance, resistance, and capacitance can easily become the performance
limiting items. The separate buck converter power pins VIN_Bx are not connected together internally. The
VIN_Bx power connections shall be connected together outside the package using a power plane construction.
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8.2.2.1 Application Components
8.2.2.1.1 Inductor Selection
Section 8.2 shows the inductors L0, L1, and L2. The inductor's inductance and DCR affects the buck and boost
converter's control loop. Table 8-2 lists the recommended inductors, or similar ones, that should be used. Pay
attention to the inductor's saturation current and temperature rise current. Check that the saturation current
is higher than the peak current limit and the temperature rise current is higher than the maximum expected
rms output current. Section 6 shows the minimum effective inductance that ensures good performance. The
inductor's DC resistance should be less than 0.05 Ω for good efficiency at high-current condition. The inductor
AC loss (resistance) also affects conversion efficiency. Higher Q factor at switching frequency usually gives
better efficiency at light load to middle load. Shielded inductors are preferred as they radiate less noise.
Table 8-2. Recommended Inductors for Buck Converters
MANUFACTURER
PART NUMBER
VALUE
DIMENSIONS
L × W x× H (mm)
RATED DC CURRENT,
ISAT max / ITEMP max (A)
DCR typ / max
(mΩ)
MURATA
MURATA
DFE20162E-R47M
DFE252012F-R47M
0.47 µH (20%)
0.47 µH (20%)
2 × 1.6 × 1.2
2.5 × 2 × 1.2
5.5 / 4.5(1)
6.7 / 4.9(1)
- / 26
- / 23
(1) Operating temperature range is up to 125°C including self temperature rise.
Table 8-3. Recommended Inductor for Boost Converters
MANUFACTURER
PART NUMBER
VALUE
DIMENSIONS
L × W x× H (mm)
RATED DC CURRENT,
ISAT max / ITEMP max (A)
DCR typ / max
(mΩ)
MURATA
MURATA
DFE201612E-1R0M
DFE252012F-1R0M
1 µH (20%)
1 µH (20%)
2 × 1.6 × 1.2
2.5 × 2 × 1.2
4.0 / 2.9 (1)
4.2 / 3.3 (1)
- / 42
- / 40
8.2.2.1.2 Buck Input Capacitor Selection
Section 8.2 shows the input capacitors CIN0 and CIN1. A ceramic input bypass capacitor of 10 μF is required
for both converters. Place the input capacitor as close as possible to the device's VIN_Bx pin and PGND_Bx
pin. A larger value or higher voltage rating improves the input voltage filtering. Use X7R type of capacitors, not
Y5V or F. The capacitor's DC bias characteristics must also be considered. Minimum effective input capacitance
to ensure good performance is 1.9 μF per buck input at the maximum input voltage including tolerances and
ambient temperature range. In addition, Table 8-4 shows how there must be at least 22 μF of additional
capacitance common for all the power input pins on the system power rail.
The input filter capacitor supplies current to the high-side FET switch in the first half of each cycle and reduces
the voltage ripple imposed on the input power source. A ceramic capacitor's low ESR provides the best noise
filtering of the input voltage spikes due to this rapidly changing current. Select an input filter capacitor with
sufficient ripple current rating. In addition, ferrite can be used in front of the input capacitor to reduce the EMI.
Table 8-4. Recommended Buck Input Capacitors (X7R Dielectric)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS LxWxH VOLTAGE RATING
(mm)
Murata
TDK
GRM21BR71A06KA73
10 µF (10%)
10 µF (10%)
0805
0805
2 × 1.25 × 1.25
2 × 1.25 × 1.25
10 V
10 V
C2012X7R1A106K125AC
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8.2.2.1.3 Buck Output Capacitor Selection
Section 8.2 shows the output capacitor COUT0 and COUT1. A ceramic local output capacitor of 22 μF is
required for both outputs. Use ceramic capacitors, X7R or X7T types; do not use Y5V or F. DC bias voltage
characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out the current flow
from the inductor to the load, whic helps maintain a steady output voltage during transient load changes and
reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low
ESR and ESL to perform these functions. Minimum effective output capacitance for good performance is 15 μF
for each buck, including the DC voltage roll-off, tolerances, aging, and temperature effects.
The output voltage ripple is caused by charging and discharging the output capacitor, and is also due to its RESR
.
Table 8-5 shows how the RESR is frequency dependent (as well as temperature dependent); make sure the value
used for selection process is at the part's switching frequency.
POL capacitors can be used to improve load transient performance and to decrease the ripple voltage. A higher
output capacitance improves the load step behavior, reduces the output voltage ripple, and decreases the PFM
switching frequency. Note: the output capacitor may be the limiting factor in the output voltage ramp, especially
for very large (100-μF range) output capacitors. The output voltage might be slower than the programmed
ramp rate at voltage transitions for large output capacitors, because of the higher energy stored on the output
capacitance. Also, the time required to charge the output capacitor to target value might be longer at start-up.
The output voltage is discharged to 0.6 V level using forced-PWM operation at shutdown. This can increase the
input voltage if the load current is small and the output capacitor is large compared to the input capacitor. The
output capacitor is discharged by the internal discharge resistor when below the 0.6 V level, and more time is
required to settle VOUT down with a large capacitor because of the increased time constant.
Table 8-5. Recommended Buck Output Capacitors (X7R or X7T Dielectric)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS LxWxH VOLTAGE RATING
(mm)
Murata
TDK
GRM21BD71A226ME44
C2012X7S1A226M125AC
22 µF (10%)
22 µF (20%)
0805
0805
2 × 1.25 × 1.25
2 × 1.25 × 1.25
10 V
10 V
8.2.2.1.4 Boost Input Capacitor Selection
A ceramic input capacitor of 10 μF is sufficient for most applications. Place the input capacitor close to the
SW_BST pin of the device. Use X7R types, do not use Y5V or F. See Table 8-6.
Table 8-6. Recommended Boost Input Capacitors (X7R Dielectric)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L×W×H VOLTAGE RATING
(mm)
Murata
GRM21BR71A06KA73
10 µF (10%)
0805
2.0 × 1.25 × 1.25
10 V
8.2.2.1.5 Boost Output Capacitor Selection
Use ceramic capacitors, X7R or X7T types; do not use Y5V or F. Place the output capacitor as close as possible
to the device's VOUT_BST pin and PGND_BST pin. DC bias voltage characteristics of ceramic capacitors must
be considered. DC bias characteristics vary from manufacturer to manufacturer, and DC bias curves should
be requested from them as part of the capacitor selection process. These capacitors must be selected with
sufficient capacitance and sufficiently low ESR and ESL to support load transients. See Table 8-7.
Table 8-7. Recommended Boost Output Capacitors (X7R or X7T Dielectric)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L×W×H (mm)
VOLTAGE RATING
Murata
GRM21BD71A226ME44
22 µF (10%)
0805
2 × 1.25 × 1.25
10 V
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8.2.2.1.6 Supply Filtering Components
The VANA input is used to supply analog and digital circuits in the device. See Table 8-8 recommended
components from for VANA input supply filtering.
Table 8-8. Recommended Supply Filtering Components
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L×W×H
(mm)
VOLTAGE RATING
Murata
Murata
GRT033C71C104KE01
GCM155R71C104KA55D
0.1 nF (10%)
0.1 nF (10%)
0201
0402
0.6 × 0.3 × 0.3
1.0 × 0.5 × 0.5
16 V
16 V
8.2.3 Current Limit vs Maximum Output Current
The current limit must be set high enough to account for the inductor ripple current on top of the maximum
output current for the buck converters and boost. The forward current limit for the buck converters is set by
BUCK0_ILIM, BUCK1_ILIM and for boost it is set by BOOST_ILIM.
For the buck converter the inductor current ripple can be calculated using Equation 1 and Equation 2:
VOUT
D =
V
ì h
IN(max)
(1)
(2)
(VIN(max) - VOUT ) ì D
fSW ì L
DIL =
Example using Equation 1 and Equation 2:
VIN(max) = 5.5 V
VOUT = 1 V
η = 0.75
fSW = 1.8 MHz
L = 0.38 µH
then D = 0.242 and ΔIL = 1.59 A
Peak current is half of the current ripple. If ILIM_FWD_SET_OTP is 3 A, the minimum forward current limit would be
2.85 A when taking the –5% tolerance into account. In this case the difference between set peak current and
maximum load current = 0.795 A + 0.15 A = 0.945 A.
Inductor current =
Forward current
ILIM_FWD_MAX (+20%)
ILIM_FWD_TYP (+7.5%)
LIM_FWD_SET_OTP (1.5...4.5 A, 0.5-A step)
ILIM_FWD_MIN (-5%)
Minimum 1A guard band
to take current ripple,
inductor inductance
variation into account
IL_AVG = IOUT
1 / fSW
IOUT_MAX < ILIM_FWD_SET_OTP œ 1 A
Figure 8-2. Current Limit vs Maximum Output Current
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8.2.4 Application Curves
Unless otherwise specified: VIN = 3.3 V, VOUT_BUCK = 1 V, VOUT_BOOST = 5 V, TA = 25°C, ƒSW-setting 4 MHz, L0 = L1 =
0.47 µH (TOKO DFE252012PD-R47M), L2 = 1 µH (TFM252012ALMA1R0), COUT_BUCK, CPOL_BUCK, and COUT_BOOST = 22
µF. Measurements are done using connections in Figure 8-1.
100
90
80
70
60
50
100
90
80
70
60
50
40
Vin=3.3V, Vout=1.2V
Vin=3.3V, Vout=1.8V
Vin=5.0V, Vout=1.2V
Vin=5.0V, Vout=1.8V
Vout=1.0V, Vin=3.3V
Vout=1.2V, Vin=3.3V
Vout=1.8V, Vin=3.3V
0.001
0.01
0.1
Output Current (A)
1
5
0.01
0.1
Output Current (A)
1
5
D001
D002
.
VIN = 3.3 V
Figure 8-3. Buck Efficiency in AUTO (PFM/PWM)
Mode
Figure 8-4. Buck Efficiency in Forced PWM Mode
100
90
80
70
60
1.02
1.015
1.01
1.005
1
0.995
0.99
Vout=1.0V, Vin=5.0V
Vout=1.2V, Vin=5.0V
Vout=1.8V, Vin=5.0V
50
0.985
0.98
Vin=3.3V, FPWM
Vin=5.0V, FPWM
40
0.01
0.1
Output Current (A)
1
5
0
0.5
1
1.5 2
Output Current (A)
2.5
3
3.5
D003
D004
VIN = 5 V
VOUT = 1 V
Figure 8-5. Buck Efficiency in Forced PWM Mode Figure 8-6. Buck Output Voltage vs Load Current in
Forced PWM Mode
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1.02
1.02
1.015
1.01
1.005
1
1.015
1.01
1.005
1
0.995
0.99
0.985
0.98
0.995
0.99
0.985
0.98
Vin=3.3V, AUTO
Vin=5.0V, AUTO
Vout=1.0V; ILOAD=2.0A
0
0.5
1
1.5 2
Output Current (A)
2.5
3
3.5
2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
Input Voltage (V)
D005
D009
VOUT = 1 V
.
Figure 8-7. Buck Output Voltage vs Load Current in Figure 8-8. Buck Output Voltage vs Input Voltage in
AUTO Mode PWM Mode
1.02
1.015
1.01
1.005
1
0.995
0.99
0.985
0.98
Vin=3.3V; Vout=1.0V
80 100 120 140
-40
-20
0
20
40 60
Temperature (C)
D010
.
IOUT = 0 A
Figure 8-9. Buck Output Voltage vs Temperature
Figure 8-10. Buck Start-up with EN1, Forced-PWM
RLOAD = 1 Ω
RLOAD = 1 Ω
Figure 8-12. Buck Shutdown with EN1, Forced-
PWM
Figure 8-11. Buck Start-up with EN1, Forced-PWM
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VOUT = 1.2 V
IOUT = 500 mA
VOUT = 1.2 V
IOUT = 10 mA
Figure 8-13. Buck Output Voltage Ripple, Forced-
PWM Mode
Figure 8-14. Buck Output Voltage Ripple, PFM
Mode
VOUT = 1.2 V
VOUT = 1.2 V
Figure 8-15. Buck Transient from PFM-to-PWM
Mode
Figure 8-16. Buck Transient from PWM-to-PFM
Mode
IOUT = 0 A → 3 A → 0 A
TR = TF = 1 µs
VOUT = 1 V
IOUT = 0 A → 3 A → 0 A
TR = TF = 1 µs
VOUT = 1.2 V
Figure 8-17. Buck Transient Load Step Response, Figure 8-18. Buck Transient Load Step Response,
Forced-PWM Mode Forced-PWM Mode
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IOUT = 0 A → 3 A → 0 A
TR = TF = 1 µs
VOUT = 1 V
VOUT = 1.2 V
Figure 8-19. Buck Transient Load Step Response,
Auto Mode
Figure 8-20. Buck Transient Load Step Response,
Auto Mode
100
90
80
70
60
50
5.2
5.15
5.1
5.05
5
4.95
4.9
Vout=5.0V, Vin=3.3V
0.4 0.5 0.6
Vout=5.0V, Vin=3.3V
0.1
4.85
40
0.001
0
0.1
0.2 0.3
Output Current (A)
0.01
Output Current (A)
1
D007
D006
.
.
Figure 8-22. Boost Output Voltage vs Load Current
Figure 8-21. Boost Efficiency
5.04
5.03
5.02
5.01
5
4.99
4.98
4.97
Vout=5.0V, ILoad=0.1A
3.6 3.8
2.8
3
3.2
3.4
Input Voltage (V)
4
D008
IOUT = 0.1 A
IOUT = 0 A
Figure 8-23. Boost Output Voltage vs Input Voltage
Figure 8-24. Boost Start-up With EN1, Forced-PWM
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RLOAD = 50 Ω
RLOAD = 50 Ω
Figure 8-26. Boost Shutdown With EN1, Forced-
PWM
Figure 8-25. Boost Start-up With EN1, Forced-PWM
IOUT = 0 A → 0.25 A → 0 A
TR = TF = 1 µs
IOUT = 0.1 A
Figure 8-28. Boost Transient Load Step Response
Figure 8-27. Boost Output Voltage Ripple
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.8 V and 5.5 V. This input
supply must be well regulated and able to withstand maximum input current and maintain stable voltage without
voltage drop even at load transition condition. The resistance of the input supply rail must be low enough that
the input current transient does not cause too high of a drop in the LP87702 supply voltage that can cause false
UVLO fault triggering. If the input supply is located more than a few inches from the LP87702, additional bulk
capacitance may be required in addition to the ceramic bypass capacitors.
10 Layout
10.1 Layout Guidelines
The high frequency and large switching currents of the LP87702 make the choice of layout important. Good
power supply results only occur when care is given to proper design and layout. Layout affects noise pickup
and generation and can cause a good design to perform with less-than-expected results. With a range of output
currents from milliamps to several amps, good power supply layout is much more difficult than most general PCB
design. Use the following steps as a reference to ensure the device is stable and maintains proper voltage and
current regulation across its intended operating voltage and current range.
1. Place CIN as close as possible to the VIN_Bx pin and the PGND_Bx pin. Route the VIN trace wide and thick
to avoid IR drops. The trace between the input capacitor's positive node and one or more of the device
VIN_Bx pins, as well as the trace between the negative node of the input capacitor and one or more of the
power PGND_Bx pins must be kept as short as possible. The input capacitance provides a low-impedance
voltage source for the switching converter. The inductance of the connection is the most important parameter
of a local decoupling capacitor – parasitic inductance on these traces must be kept as tiny as possible for
proper device operation.
2. The output filter, consisting of L and COUT, converts the switching signal at SW_Bx to the noiseless output
voltage. It should be placed as close as possible to the device keeping the switch node small, for best EMI
behavior. Route the traces between the LP87702 devices output capacitors and the load's input capacitors
direct and wide to avoid losses due to the IR drop.
3. Input for analog blocks (VANA and AGND) should be isolated from noisy signals. Connect VANA directly to a
quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling
capacitor as close as possible to the VANA pin.
4. If remote voltage sensing can be used for the load, connect the device feedback pins FB_Bx to the
respective sense pins on the load capacitor. The sense lines are susceptible to noise. They must be kept
away from noisy signals such as PGND_Bx, VIN_Bx, and SW_Bx, as well as high bandwidth signals such as
the I2C. Avoid capacitive and inductive coupling by keeping the sense lines short and direct. Run the lines in
a quiet layer. Isolate them from noisy signals by a voltage or ground plane (if possible).
5. PGND_Bx, VIN_Bx and SW_Bx should be routed on thick layers. They must not surround inner signal layers
which are not able to withstand interference from noisy PGND_Bx, VIN_Bx and SW_Bx.
Due to the small package of this converter and the overall small solution size, the thermal performance of the
PCB layout is important. Many system-dependent issues such as thermal coupling, airflow, added heat sinks,
convection surfaces, and the presence of other heat-generating components affect the power dissipation limits
of a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures.
Wide power traces come with the ability to sink dissipated heat. This can be improved further on multi-layer
PCB designs with vias to different planes. This results in reduced junction-to-ambient (RθJA) and junction-to-
board (RθJB) thermal resistances, which reduces the device junction temperature (TJ). TI strongly recommends
performing a careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design
process, by using a thermal modeling analysis software.
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10.2 Layout Example
VOUT0
VOUT1
COUT0
COUT1
GND
L1
L0
24 23 22
20
19
21
18 17
16
SW_B0
SW_B1
SW_B1
VIN_B1
25
26
15
14
SW_B0
VIN_B0
VIN_B0
CIN0
CIN1
27
VIN
28
GND
VIN
13
GND
GND
VIN_B1
GPO0
NRST
12
PG0
29
30
VMON1
11
10
GND
L2
VMON2
31
PGDN_BST
SW_BST
VIN
9
PG1 (GPO1)
32
GND
1
2
3
4
5
6
7
8
GND
COUT2
AGND
VIN
CANA
Figure 10-1. LP87702 Board Layout Example
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11 Device and Documentation Support
11.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, go to the device product folder on ti.com. In the upper right
corner, click Alert me to register for a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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31-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP87702KRHBR
LP87702KRHBT
ACTIVE
VQFN
VQFN
RHB
32
32
3000 RoHS & Green
250 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 105
-40 to 105
LP8770
2K RHB
ACTIVE
RHB
SN
LP8770
2K RHB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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31-Mar-2021
OTHER QUALIFIED VERSIONS OF LP87702 :
Automotive : LP87702-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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1-Apr-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP87702KRHBR
LP87702KRHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
330.0
180.0
12.4
12.4
5.25
5.25
5.25
5.25
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Apr-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP87702KRHBR
LP87702KRHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
367.0
213.0
367.0
191.0
38.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
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PACKAGE OUTLINE
RHB0032N
VQFN - 0.9 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
5.1
4.9
0.1 MIN
(0.05)
SECTION A-A
A
TYPICAL
C
0.9 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
A
A
2X
SYMM
33
3.5
0.3
32X
0.2
24
0.1
C A B
1
0.05
C
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4222893/B 02/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RHB0032N
VQFN - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL EDGE
EXPOSED METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222893/B 02/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RHB0032N
VQFN - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4222893/B 02/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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