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LP8860-Q1

ZHCSCK8G –MAY 2014–REVISED OCTOBER 2017

LP8860-Q1 具有四个 150mA 通道的低 EMI 汽车 LED 驱动器

1 特性

2 应用

1

•

符合汽车应用应用

具有符合 AEC-Q100 标准的下列特性：

•

为以下应用提供背光：

–

汽车信息娱乐系统

汽车仪表盘

–

器件温度等级 1：–40°C 至 +125°C 环境工作温

度

智能车镜

•

输入电压工作范围：3V 至 48V

抬头显示屏 (HUD)

中央信息显示屏 (CID)

音视频导航 (AVN)

四路高精度电流阱

–

电流匹配度为 0.5%（典型值）

LED 灯串电流高达 150mA/通道

3 说明

采用外部 PWM 亮度控制，调光比大于 13

000:1

LP8860-Q1 是具有升压控制器的汽车用高效 LED 驱动

器。该器件具有可通过 PWM 输入信号、SPI 和/或 I²C

主机控制的 4 路高精度电流阱。

–

通过 SPI 或 I²C 进行 16 位调光控制

支持显示模式（全局调光）和群集模式（独立调

光）

升压转换器具有基于 LED 电流阱余量电压的自适应输

出电压控制。该特性可在所有条件下将电压调节到能够

满足需要的最低水平，从而最大限度降低功耗。凭借宽

范围可调频率，LP8860-Q1 能够避免调幅 (AM) 射频

波段的干扰。

•

针对更高 LED 驱动光效率的混合 PWM 和电流调

光

•

针对 LED PWM 频率的同步

具有介于 100kHz 到 2.2Mhz 之间的可编程开关频

率和用于降低电磁干扰 (EMI) 的扩频选项的升压控

制器

LP8860-Q1 支持内置混合 PWM 和电流调光，从而降

低了 EMI、延长了 LED 使用寿命且提高了总光学效

率。相移 PWM 可减少人耳噪声和输出纹波。

•

升压同步输入

电力线场效应晶体管 (FET) 控制，可实现浪涌电流

保护和待机节能

器件信息⁽¹⁾

•

使用外部温度传感器自动降低 LED 电流

丰富的故障诊断”

器件型号

LP8860-Q1

封装

封装尺寸（标称值）

散热薄型四方扁平

封装 (HLQFP) (32)

7.00mm × 7.00mm

简化原理图

VIN

3...40 V

R

ISENSE

L

D

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

Up to 48V

Q2

C

2x

C

IN

C

OUT

系统效率

Q1

C1P

C1N

SD

95

GD

ISENSE

VSENSE_N

VSENSE_P

90

85

VDD 3.3V

C

R

VDD

SENSE

C

CPUMP

ISENSE_GND

FB

CPUMP

VDD

SQW

VIN = 5 V

VIN = 6 V

VIN = 8 V

VIN = 12 V

VIN = 15 V

80

75

70

65

FILTER

Up to 150 mA/string

BOOST SYNC

V/H SYNC

LP8860-Q1

SYNC

OUT1

VSYNC

BRIGHTNESS

OUT2

OUT3

PWM

SCLK/SCL

MOSI/SDA

MISO

OUT4

FAULT RESET

EN

NSS

0

10

20

30

40

50

60

70

80

90

100

TSENSE

ISET

R

T°

VDDIO/EN

IF

Brightness (%)

C001

FAULT

NTC

SGND PGND LGND PAD

R

ISET

VDDIO

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNVSA21

LP8860-Q1

ZHCSCK8G –MAY 2014–REVISED OCTOBER 2017

www.ti.com.cn

7.17 Typical Characteristics.......................................... 13

Detailed Description ............................................ 14

8.1 Overview ................................................................. 14

8.2 Functional Block Diagram ....................................... 17

8.3 Feature Description................................................. 18

8.4 Device Functional Modes........................................ 48

8.5 Programming........................................................... 49

8.6 Register Maps......................................................... 55

Application and Implementation ........................ 85

9.1 Application Information............................................ 85

9.2 Typical Applications ................................................ 85

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

器件比较表............................................................... 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 6

7.1 Absolute Maximum Ratings ...................................... 6

7.2 ESD Ratings.............................................................. 6

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information.................................................. 7

7.5 Electrical Characteristics .......................................... 7

7.6 Current Sinks Electrical Characteristics.................... 7

7.7 Boost Converter Characteristics ............................... 8

7.8 Logic Interface Characteristics.................................. 9

7.9 V_INUndervoltage Protection (VIN_UVLO) ................ 9

7.10 V_DDUndervoltage Protection (VDD_UVLO) ......... 10

7.11 V_INOvervoltage Protection (VIN_OVP) ............... 10

7.12 V_INOvercurrent Protection (VIN_OCP) ............... 10

8

9

10 Power Supply Recommendations ..................... 99

11 Layout................................................................. 100

11.1 Layout Guidelines ............................................... 100

11.2 Layout Example .................................................. 101

12 器件和文档支持 ................................................... 102

12.1 器件支持.............................................................. 102

12.2 文档支持.............................................................. 102

12.3 接收文档更新通知 ............................................... 102

12.4 社区资源.............................................................. 102

12.5 商标..................................................................... 102

12.6 静电放电警告....................................................... 102

12.7 Glossary.............................................................. 102

13 机械、封装和可订购信息..................................... 103

7.13 Power-Line FET Control Electrical

Characteristics ......................................................... 10

7.14 External Temp Sensor Control Electrical

Characteristics ......................................................... 10

7.15 I²C Serial Bus Timing Parameters (SDA, SCLK) . 12

7.16 SPI Timing Requirements ..................................... 12

4 修订历史记录

Changes from Revision F (July 2017) to Revision G

Page

•

使用更详细的封装图进行了更新 ......................................................................................................................................... 103

Changes from Revision E (November 2016) to Revision F

Page

•

Changed placement of "7" data hold time in Figure 2 ......................................................................................................... 12

Deleted "The LP8860-Q1 doesn’t support incremental addressing." after Table 20 ........................................................... 51

Changed "short" to "open" in DRV_HEADER[2:0] row, EEPROM Register 4 ..................................................................... 70

Changes from Revision D (September 2016) to Revision E

Page

•

Deleted 4-A row from V_OCPin V_INOvercurrent Protection (VIN_OCP) table........................................................................ 10

Changed "+ 150 mA" to "× 150 mA" in eq. 8 ...................................................................................................................... 41

Deleted "01/4A" row from Input voltage overcurrent protection in Table 16 ........................................................................ 43

Deleted duplicate of Figure 42 "State Diagram" .................................................................................................................. 48

Changed "open" to "short" in DRV_LED_FAULT_THR[1:0] row, EEPROM Register 4 ...................................................... 70

Changed "nit" to "not" - correct typo..................................................................................................................................... 71

Deleted "01 = 4 A" from PL_SD_LEVEL[1:0] in EEPROM Register 10............................................................................... 75

更新了 POA 中的可订购选项 .............................................................................................................................................. 103

在 POA 中添加了预生产“R”可订购选项 .............................................................................................................................. 103

2

LP8860-Q1

www.ti.com.cn

ZHCSCK8G –MAY 2014–REVISED OCTOBER 2017

Changes from Revision C (December 2015) to Revision D

Page

•

已更改数据表标题.................................................................................................................................................................. 1

已更改略微修改了“特性”项目中的措辞................................................................................................................................... 1

已删除 “安全和........................................................................................................................................................................ 1

已更改 “公差特性”至“诊断”..................................................................................................................................................... 1

已删除 “SPI 或 I²C 接口”......................................................................................................................................................... 1

已添加附加应用...................................................................................................................................................................... 1

已更改 “高开关”至“宽范围可调”............................................................................................................................................... 1

已删除一些措辞（描述部分）使其更加简洁；已重新编写最后一句话.................................................................................. 1

已添加器件比较表.................................................................................................................................................................. 3

Deleted Table 19 "Default EEPROM Context" - this information now in SNVA757, available in mysecureSW only ......... 50

Changes from Revision B (March 2015) to Revision C

Page

•

已添加特性项目修改：汽车.................................................................................................................................................... 1

已更改 “安全”至“故障检测”...................................................................................................................................................... 1

已更改简化原理图中的“高达 40V”至“高达 48V” .................................................................................................................... 1

Changed SPI Write Cycle and SPI Read Cycle diagrams .................................................................................................. 51

Changes from Revision A (June 2014) to Revision B

Page

•

Changed EXT_TEMP_MINUS[1:0] from "2, 6, 10, 14 μA" to "1, 5, 9, 13 µA"...................................................................... 41

Changed values for EXT_TEMP_MINUS from "2, 6, 10, 14 µA" to '1, 5, 9, 13 µA" ............................................................ 67

已添加文档支持部分 .......................................................................................................................................................... 102

Changes from Original (May 2014) to Revision A

Page

•

Changed first sentence in paragraph beginning "EEPROM bits are intended to be set..." to 2 separate sentences ......... 50

5 器件比较表

LP8860-Q1

LP8862-Q1

LP8861-Q1

TPS61193-Q1

TPS61194-Q1

TPS61196-Q1

VIN 范围

3V 至 48V

4.5V 至 45V

8V 至 30V

LED 通道的数量

LED 电流/通道

I2C/SPI 支持

SEPIC 支持

4

150mA

是

2

160mA

否

4

100mA

否

3

100mA

否

4

100mA

否

6

200mA

无

有

是

有

无

3

LP8860-Q1

ZHCSCK8G –MAY 2014–REVISED OCTOBER 2017

www.ti.com.cn

6 Pin Configuration and Functions

VFP Package

32-Lead PowerPAD™ Quad Flatpack S-PQFP-G32

Top View

C1P

C1N

VDD

1

2

3

4

5

6

7

8

OUT2

LGND

OUT3

OUT4

24

23

22

21

SQW

VSENSE_N

VSENSE_P

ISET

20 IF

19

18

VDDIO/EN

PWM

EP*

TSENSE

17 NSS

*EXPOSED PAD

4

LP8860-Q1

www.ti.com.cn

ZHCSCK8G –MAY 2014–REVISED OCTOBER 2017

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NUMBER

NAME

Positive pin for charge pump flying capacitor.

If feature is disabled, the pin may be left floating.

1

C1P

A

Negative pin for charge pump flying capacitor.

If feature is disabled, the pin may be left floating.

2

3

4

C1N

VDD

SQW

A

P

A

Input voltage pin for internal circuit.

Square wave output. Can be used for generating extra voltage rail.

If unused, the pin may be left floating.

5

6

VSENSE_N

VSENSE_P

A

Pin for input current sense.

Pin for OVP/UVLO protection and input current sense.

Optional resistor for setting LED maximum current.

If feature is disabled, the pin may be left floating.

7

8

ISET

A

External temperature sensor for LED current control.

If feature is disabled, the pin may be left floating.

TSENSE

Low pass filter for PLL.

If feature is disabled, the pin may be left floating.

9

FILTER

SGND

FAULT

A

G

10

11

Signal ground.

Fault signal output.

If unused, the pin may be left floating.

OD

Input for synchronizing boost.

This pin must be connected to GND if not used.

12

SYNC

I

Input for synchronizing PWM generation to display refresh.

This pin must be connected to GND if feature is disabled.

13

14

15

VSYNC

MISO

I

O

Slave data output (SPI). If unused, the pin may be left floating.

Slave data input (SPI) or serial data (I²C).

This pin must be connected to GND if not used.

MOSI/SDA

I/O

Serial clock for SPI or I²C.

This pin must be connected to GND if not used.

Slave select (SPI mode) or fault reset (I²C or standalone mode).

This pin must be connected to GND if not used.

16

17

18

SCLK/SCL

NSS

I

PWM dimming input.

This pin must be connected to GND if feature is disabled.

PWM

19

20

VDDIO/EN

IF

I

Enable input pin and reference voltage for digital pins.

Interface selection: low – I²C or standalone mode; high – SPI.

LED current sink output.

If unused, the pin may be left floating.

21

OUT4

A

LED current sink output.

If unused, the pin may be left floating.

22

23

24

OUT3

LGND

OUT2

A

G

A

LED current ground.

LED current sink output.

If unused, the pin may be left floating.

LED current sink output.

If unused, the pin may be left floating.

25

OUT1

A

26

27

28

29

30

31

FB

ISENSE_GND

ISENSE

PGND

A

G

A

P

Boost feedback input.

Boost controller’s current sense resistor GND.

Boost current sense pin.

Power ground.

GD

Gate driver output for boost FET.

Charge pump output pin.

CPUMP

Power line FET control.

If unused, the pin may be left floating.

32

SD

A

(1) A: Analog pin, G: Ground pin, P: Power pin, I: Input pin, I/O: Input/Output pin, O: Output pin, OD: Open Drain pin

5

LP8860-Q1

ZHCSCK8G –MAY 2014–REVISED OCTOBER 2017

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

MAX

UNIT

Voltage on pins VSENSE_N, VSENSE_P, OUT1 to OUT4, FB, SD

–0.3

52

V

Voltage on pins VDD, FILTER, SYNC, VSYNC, PWM, SCLK/SCL, MOSI/SDA, MISO, NSS,

VDDIO/EN, IF, ISENSE, ISENSE_GND, FAULT, ISET, TSENSE, C1N

–0.3

6

V

Voltage on pins C1P, CPUMP, GD, SQW

Continuous power dissipation⁽³⁾

–0.3

12

Internally Limited

(4)

Ambient temperature, T_A

–40

125

150

See⁽⁵⁾

°C

(4)

Junction temperature, T_J

Maximum lead temperature (soldering)

Storage temperature, T_stg

–65

150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the potential at the GND pins.

(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J= 165°C (typical) and

disengages at T_J= 135°C (typical).

(4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP

=

150°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the

part/package in the application (R_θJA), as given by the following equation: T_A-MAX= T_J-MAX-OP– (R_θJA× P_D-MAX).

(5) For detailed soldering specifications and information, refer to PowerPAD™ Thermally Enhanced Package Application Note .

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

All pins

V_(ESD)

Electrostatic discharge

V

Corner pins

(1,8,9,16,17,24,25,32)

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

V

Voltage on pins VSENSE_N, VSENSE_P

VDD input voltage

3

48

5.5

3

1.65

0

V

VDDIO/EN input voltage

VDD

5.5

V

Voltage on pins FILTER, ISENSE, ISENSE_GND, ISET, TSENSE, C1N

FAULT, PWM, SCLK/SCL, MOSI/SDA, NSS, IF, SYNC, MISO, VSYNC

Voltage on pins C1P, CPUMP, GD, SQW

Voltage on pins OUT1 to OUT4, FB, SD

V

0

VDDIO

11

V

0

V

0

48

V

(1) All voltages are with respect to the potential at the GND pins.

6

LP8860-Q1

www.ti.com.cn

ZHCSCK8G –MAY 2014–REVISED OCTOBER 2017

7.4 Thermal Information

LP8860

THERMAL METRIC⁽¹⁾

HLQFP PowerPAD (VLP)

UNIT

32 PINS

36.0

23.3

15.5

3.2

R_θJA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJCtop

R_θJB

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

15.5

1.6

R_θJCbot

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

7.5 Electrical Characteristics

T_J= −40°C to +125°C (unless otherwise noted).⁽¹⁾⁽²⁾

PARAMETER

POWER SUPPLIES

TEST CONDITIONS

MIN

TYP

1

MAX

UNIT

Shutdown supply current for VDD Device disabled, VDDIO/EN = 0 V

5

6

μA

Backlight enabled (no load), boost

enabled, PLL and CP disabled,

DRV_LED_BIAS_CTRL[1:0] = 10 ,

2.5

I_Q

boost ƒ_SW= 300 kHz

Active supply current for VDD,

VDD = 5 V

mA

Backlight enabled (no load), boost

enabled, CP disabled, ƒ_PLL= 10

MHz, DRV_LED_BIAS_CTRL[1:0] =

11, boost ƒ_SW= 400 kHz

4.5

15

2.2

V_{VDD_POR_R}

V_{VDD_POR_F}

T_TSD

Power-on reset rising threshold

Power-on reset falling threshold

Thermal shutdown threshold

Thermal shutdown hysteresis

V

1.1

150

165

30

180

°C

T_{TSD_THR}

INTERNAL OSCILLATOR

Frequency

ƒ_OSC

10

MHz

Frequency accuracy

–7%

7%

(1) All voltages are with respect to the potential at the GND pins.

(2) Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis.

7.6 Current Sinks Electrical Characteristics

Limits apply over the full ambient temperature range –40°C ≤ T_A≤ +125°C. Unless otherwise specified: V_DD= 3.3 V, V_IN= 12

V, EN/VDDIO = 3.3 V, L = 22 μH, C_IN= 2 × 10 μF ceramic and 33 μF electrolytic, C_OUT= 2 × 10 μF ceramic and 33 μF

electrolytic, C_VDD= 1 μF, C_CPUMP= 10 μF, Q = IPD25N06S4L-30-ND, D = SS5P10-M3/86A.

PARAMETER

TEST CONDITIONS

Outputs OUT1 to OUT4, V_OUT= 48 V

OUT1 to OUT4

MIN

TYP

0.1

MAX UNIT

I_LEAKAGE

I_MAX

Leakage current

1

µA

Maximum source current

Output current accuracy

Output current matching⁽¹⁾

150

mA

I_OUT

I_OUT= 150 mA

−3%

3%

2%

I_MATCH

I_OUT= 150 mA, 100% brightness

0.5%

LED PWM output frequency

for display mode

PWM_FREQ[3:0] = 0000b

PWM_FREQ[3:0] = 1111b

4883

39 063

ƒ_{LED_PWM}

Hz

(1) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current.

Matching is the maximum difference from the average. For the constant current sinks on the part (OUT1 to OUT4), the following are

determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG).

Two matching numbers are calculated: (MAX-AVG)/AVG and (AVG-MIN)/AVG. The largest number of the two (worst case) is

considered the matching figure. The typical specification provided is the most likely norm of the matching figure for all parts. Note that

some manufacturers have different definitions in use.

7

LP8860-Q1

ZHCSCK8G –MAY 2014–REVISED OCTOBER 2017

www.ti.com.cn

Current Sinks Electrical Characteristics (continued)

Limits apply over the full ambient temperature range –40°C ≤ T_A≤ +125°C. Unless otherwise specified: V_DD= 3.3 V, V_IN= 12

V, EN/VDDIO = 3.3 V, L = 22 μH, C_IN= 2 × 10 μF ceramic and 33 μF electrolytic, C_OUT= 2 × 10 μF ceramic and 33 μF

electrolytic, C_VDD= 1 μF, C_CPUMP= 10 μF, Q = IPD25N06S4L-30-ND, D = SS5P10-M3/86A.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

ƒ_PWM

PWM input frequency

BRT_MODE[1:0] = 00, 01 and 10

100

500

Hz

Minimum on and off time for

PWM input

t_{PWM MIN}

400

ns

External 100 Hz PWM

SPI or I²C control

13 000:1

Dimming ratio (input

resolution)

I_DIM

16

10

bit

ƒ_{LED_PWM}= 5 kHz, ƒ_OSC= 5 MHz

ƒ_{LED_PWM}= 10 kHz, ƒ_OSC= 5 MHz

ƒ_{LED_PWM}= 20 kHz, ƒ_OSC= 5 MHz

ƒ_{LED_PWM}= 40 kHz, ƒ_OSC= 5 MHz

ƒ_{LED_PWM}= 5 kHz, ƒ_OSC= 40 MHz

ƒ_{LED_PWM}= 10 kHz, ƒ_OSC= 40 MHz

ƒ_{LED_PWM}= 20 kHz, ƒ_OSC= 40 MHz

ƒ_{LED_PWM}= 40 kHz, ƒ_OSC= 40 MHz

DRV_OUTx_CORR[3:0] = 1111

DRV_OUTx_CORR[3:0] = 0000

I_OUT= 150 mA

9

8

PWM output resolution, PWM

control for BRT_MODE[1:0] =

00, 01, and 10 (without

dithering)

7

PWM_RES

bits

13

12

11

10

–7.4%

6.5%

0.5

3.6

6.9

10.6

Individual output current

adjustment range

ΔI_OUT

V_SAT

Saturation voltage⁽²⁾

0.75

V

DRV_LED_FAULT_THR[1:0] = 00

DRV_LED_FAULT_THR[1:0] = 01

DRV_LED_FAULT_THR[1:0] = 10

DRV_LED_FAULT_THR[1:0] = 11

V_{SHORT_FAULT_THR}LED short detection threshold

(2) Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1 V.

7.7 Boost Converter Characteristics

Limits apply over the full ambient temperature range – 40°C ≤ T_A≤ +125°C. Unless otherwise specified: V_DD= 3.3 V, V_IN= 12

V, EN/VDDIO = 3.3 V, L = 22 μH, C_IN= 2 × 10 μF ceramic and 33-μF electrolytic, C_OUT= 2 × 10 μF ceramic and 33-μF

electrolytic, C_VDD= 1 μF, C_CPUMP= 10 μF, Q = IPD25N06S4L-30-ND, D = SS5P10-M3/86A.

PARAMETER

TEST CONDITIONS

MIN

600

150

100

TYP

MAX

UNIT

V_IN= 6 V, V_BOOST= 48 V (ƒ_SW= 303 kHz)

V_IN= 3 V, V_BOOST= 30 V (ƒ_SW= 1.1 MHz)

V_IN= 3 V, V_BOOST= 30 V (ƒ_SW= 2.2 MHz)

Maximum continuous load

current

I_LOAD

mA

V_OUT/V_IN

Conversion ratio

10

BOOST_FREQ = 000

BOOST_FREQ = 001

BOOST_FREQ = 010

BOOST_FREQ = 011

BOOST_FREQ = 100

BOOST_FREQ = 101

BOOST_FREQ = 110

BOOST_FREQ = 111

100

200

303

400

629

800

1100

2200

Switching frequency (central

frequency if spread spectrum

is enabled)

ƒ_SW

–7%

7%

kHz

ms

t_BOOST

START-UP

(1)

Start-up time

50

(1) Start-up time is measured from the moment the boost is activated until the V_OUTcrosses 90% of its initial voltage value.

8

LP8860-Q1

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ZHCSCK8G –MAY 2014–REVISED OCTOBER 2017

Boost Converter Characteristics (continued)

Limits apply over the full ambient temperature range – 40°C ≤ T_A≤ +125°C. Unless otherwise specified: V_DD= 3.3 V, V_IN= 12

V, EN/VDDIO = 3.3 V, L = 22 μH, C_IN= 2 × 10 μF ceramic and 33-μF electrolytic, C_OUT= 2 × 10 μF ceramic and 33-μF

electrolytic, C_VDD= 1 μF, C_CPUMP= 10 μF, Q = IPD25N06S4L-30-ND, D = SS5P10-M3/86A.

PARAMETER

TEST CONDITIONS

R_SENSE= 25 mΩ

MIN

TYP

MAX

UNIT

BOOST_IMAX_SEL=000

BOOST_IMAX_SEL=001

BOOST_IMAX_SEL=010

BOOST_IMAX_SEL=011

BOOST_IMAX_SEL=100

BOOST_IMAX_SEL=101

BOOST_IMAX_SEL=110

BOOST_IMAX_SEL=111

2

3

4

5

6

7

8

9

I_MAX

SW current limit

A

V_GD

Gate driver output voltage

0

11

V

A

I_{GD_SOURCE_}Gate driver peak current,

PEAK

BOOST_DRIVER_SIZE[1:0] = 11

BOOST_GD_VOLT = 1

V_DD= 5 V, V_CPUMP= 10 V

FET SQ4850EY

1.7

1.5

sourcing

I_{GD_SINK_PEA}Gate driver peak current,

K

sinking

7.8 Logic Interface Characteristics

VDDIO/EN = 1.65 V to V_DD, V_DD= 3.3 V unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

0.4

UNIT

LOGIC INPUT VDDIO/EN

V_IL

V_IH

I_I

Input low level

Input high level

Input current

V

1.2

−1

1

µA

LOGIC INPUT SYNC, VSYNC, PWM, SCLK/SCL, MOSI/SDA, NSS, IF

0.2 ×

VDDIO/EN

V_IL

Input low level

V

V_IH

I_I

Input high level

Input current

0.8 × VDDIO/EN

−1

1

μA

LOGIC OUTPUT FAULT

V_OL

Output low level

I = 3 mA

0.3

0.5

1

V

I_LEAKAGE

Output leakage current

V = 5.5 V

μA

LOGIC OUTPUT MISO

V_OL

V_OH

I_L

Output low level

I_OUT= 3 mA

0.5

1

V

I_OUT= –2 mA

0.9 ×

VDDIO/EN

Output high level

0.7 × VDDIO/EN

Output leakage current

μA

LOGIC OUTPUTS SDA

V_OL

Output low level

Output leakage current

I = 3 mA

0.3

0.5

1

V

I_LEAKAGE

V = 5.5 V

μA

7.9 V_INUndervoltage Protection (VIN_UVLO)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

UVLO[1:0] = 00

UVLO[1:0] = 01

UVLO[1:0] = 10

UVLO[1:0] = 11

Disabled

2.64

4.4

3

5

8

3.36

5.6

V_UVLO

V_INUVLO threshold voltage

V

7.04

8.96

9

LP8860-Q1

ZHCSCK8G –MAY 2014–REVISED OCTOBER 2017

www.ti.com.cn

7.10 V_DDUndervoltage Protection (VDD_UVLO)

PARAMETER

TEST CONDITIONS

MIN

TYP

2.5

3

MAX

UNIT

V

VDD_UVLO_LEVEL = 0

VDD_UVLO_LEVEL = 1

V_{VDD_UVLO}V_DDUVLO threshold voltage

V_HYST

V_DDUVLO hysteresis

50

mV

7.11 V_INOvervoltage Protection (VIN_OVP)

PARAMETER

TEST CONDITIONS

TYP

Disabled

7

MAX

UNIT

OVP[1:0] = 00

OVP[1:0] = 01

OVP[1:0] = 10

OVP[1:0] = 11

6.16

9.68

19.8

7.84

12.32

25.2

V_OVP

V_INOVP threshold voltage

V

11

22.5

7.12 V_INOvercurrent Protection (VIN_OCP)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_INcurrent protection limit with

R_ISENSE= 20 mΩ, V_IN= 12 V

See⁽¹⁾

PL_SD_LEVEL[1:0] = 10

PL_SD_LEVEL[1:0] = 11

6

V_OCP

A

8

(1) Refer to Selecting Current Sensing Resistor for LP8860-Q1 Power Input application note.

7.13 Power-Line FET Control Electrical Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_{L,VSENSE_P}

I_{L,VSENSE_N}

I_L,SD

VSENSE_P pin leakage current

VSENSE_N pin leakage current

SD pin leakage current

V_{SENSE_P}= 48 V

V_{SENSE_N}= 48 V

V_SD= 48 V

0.1

3

µA

PL_SD_SINK_LEVEL = 00

PL_SD_SINK_LEVEL = 01

PL_SD_SINK_LEVEL = 10

PL_SD_SINK_LEVEL = 11

55

110

220

440

Pulldown current for power-line

p-FET, NMOS_PLFET_EN=0

I_{SD PFET}

µA

7.14 External Temp Sensor Control Electrical Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

EXT_TEMP_LEVEL_HIGH[3:0] = 0000

EXT_TEMP_LEVEL_HIGH[3:0] = 0001

EXT_TEMP_LEVEL_HIGH[3:0] = 0010

EXT_TEMP_LEVEL_HIGH[3:0] = 0011

EXT_TEMP_LEVEL_HIGH[3:0] = 0100

EXT_TEMP_LEVEL_HIGH[3:0] = 0101

EXT_TEMP_LEVEL_HIGH[3:0] = 0110

EXT_TEMP_LEVEL_HIGH[3:0] = 0111

EXT_TEMP_LEVEL_HIGH[3:0] = 1000

EXT_TEMP_LEVEL_HIGH[3:0] = 1001

EXT_TEMP_LEVEL_HIGH[3:0] = 1010

EXT_TEMP_LEVEL_HIGH[3:0] = 1011

EXT_TEMP_LEVEL_HIGH[3:0] = 1100

EXT_TEMP_LEVEL_HIGH[3:0] = 1101

EXT_TEMP_LEVEL_HIGH[3:0] = 1110

EXT_TEMP_LEVEL_HIGH[3:0] = 1111

79.67

43.35

29.77

22.67

18.30

15.34

13.21

11.60

10.34

9.32

8.49

7.79

7.20

6.69

6.25

5.87

T_SENSEhigh level

resistance value

R_{TEMP_HIGH}

kΩ

10

LP8860-Q1

www.ti.com.cn

ZHCSCK8G –MAY 2014–REVISED OCTOBER 2017

External Temp Sensor Control Electrical Characteristics (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

EXT_TEMP_LEVEL_LOW[3:0] = 0000

EXT_TEMP_LEVEL_LOW[3:0] = 0001

EXT_TEMP_LEVEL_LOW[3:0] = 0010

EXT_TEMP_LEVEL_LOW[3:0] = 0011

EXT_TEMP_LEVEL_LOW[3:0] = 0100

EXT_TEMP_LEVEL_LOW[3:0] = 0101

EXT_TEMP_LEVEL_LOW[3:0] = 0110

EXT_TEMP_LEVEL_LOW[3:0] = 0111

EXT_TEMP_LEVEL_LOW[3:0] = 1000

EXT_TEMP_LEVEL_LOW[3:0] = 1001

EXT_TEMP_LEVEL_LOW[3:0] = 1010

EXT_TEMP_LEVEL_LOW[3:0] = 1011

EXT_TEMP_LEVEL_LOW[3:0] = 1100

EXT_TEMP_LEVEL_LOW[3:0] = 1101

EXT_TEMP_LEVEL_LOW[3:0] = 1110

EXT_TEMP_LEVEL_LOW[3:0] = 1111

79.67

43.35

29.77

22.67

18.30

15.34

13.21

11.60

10.34

9.32

8.49

7.79

7.20

6.69

6.25

5.87

TSENSE low-level

resistance value

R_{TEMP_LOW}

kΩ

T_SENSEmaximum

resistance (missing

resistor fault value)

R_{TS_FLOAT}

2

MΩ

11

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ZHCSCK8G –MAY 2014–REVISED OCTOBER 2017

www.ti.com.cn

7.15 I²C Serial Bus Timing Parameters (SDA, SCLK)

See Figure 1.

MIN

NOM

MAX

UNIT

kHz

µs

ƒ_SCLK

Clock frequency

400

1

2

3

4

5

6

7

8

9

10

Hold time (repeated) START Condition

Clock low time

0.6

1.3

25000

µs

Clock high time

600

ns

Set-up time for a repeated START condition

Data hold time

600

ns

50

ns

Data setup time

100

ns

Rise Time of SDA and SCL

Fall Time of SDA and SCL

Set-up time for STOP condition

Bus free time between a STOP and a START Condition

20+0.1xC_b

15+0.1xC_b

600

300

ns

1.3

µs

Capacitive load parameter for each bus line

load of 1 pF corresponds to 1 ns.

C_b

10

200

ns

7.16 SPI Timing Requirements

See Figure 2.

MIN

70

35

20

NOM

MAX

UNIT

ns

1

Cycle time

2

Enable lead time

Enable lag time

Clock low time

Clock high time

Data setup time

Data hold time

Disable time

ns

3

ns

4

ns

5

ns

6

ns

7

ns

8

10

29

ns

9

Data valid

ns

10

C_b

NSS inactive time

Bus capacitance

700

5

ns

40

pF

Figure 1. I²C Timing

NSS

t10t

t2t

t1t

7

4

5

3

SCLK

MOSI

6

MSB IN

BIT 14

BIT 9

BIT 8

BIT 7

BIT 1

LSB IN

9

8

High

Impedance

9

MISO

MSBOUT

BIT 1

Data

LSB OUT

Address

R/W

Figure 2. SPI Timing Diagram

12

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ZHCSCK8G –MAY 2014–REVISED OCTOBER 2017

7.17 Typical Characteristics

Unless otherwise specified: L= 22 µH (IHLP-5050FDER220M5A), C_IN= 2 × 10-µF ceramic and 33 µF electrolytic, C_OUT= 2 ×

10-µF ceramic and 33-µF electrolytic, Q = IPD25N06S4L-30-ND, D = SS5P10-M3/86A, V_DD= 5 V, charge pump disabled, T =

25°C

95

90

85

80

75

70

65

90

85

80

75

70

65

60

VIN = 5 V

VIN = 6 V

VIN = 8 V

VIN = 12 V

VIN = 15 V

VIN = 5 V

VIN = 6 V

VIN = 8 V

VIN = 12 V

VIN = 15 V

0

10

20

30

40

50

60

70

80

90

100

0

10

20

30

40

50

60

70

80

90

100

Brightness (%)

C001

C004

ƒ_SW= 303 kHz

4 strings

8 LEDs/string

150 mA/string

ƒ_SW= 2.2 MHz

4 strings

8 LEDs/string

100 mA/string

Figure 3. System Efficiency

Figure 4. System Efficiency

4000

160

140

120

100

80

Vout = 26 V

3500

3000

2500

2000

1500

1000

500

25 mA

30 mA

50 mA

60 mA

80 mA

100 mA

120 mA

150 mA

Vout = 33 V

Vout = 39 V

Vout = 45 V

60

40

20

0

5

6

7

8

9

10

11

12

13

14

15

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Input Voltage (V)

Voltage (V)

C007

C006

ƒ_SW= 303 kHz

Adaptive voltage control off

Figure 5. Boost Maximum Output Current

Figure 6. LED Current vs Headroom Voltage

200

180

160

140

120

100

80

200

VIN = 5 V

VIN = 6 V

VIN = 8 V

VIN = 12 V

VIN = 15 V

VIN = 5 V

VIN = 6 V

VIN = 8 V

VIN = 12 V

VIN = 15 V

180

160

140

120

100

80

60

40

20

0

10

20

30

40

50

60

70

80

90

100

0

10

20

30

40

50

60

70

80

90

100

Brightness (%)

8 LEDs/string

Phase shift 90º

Brightness (%)

8 LEDs/string

Phase shift 90º

C003

C005

ƒ_SW= 303 kHz

4 strings

150 mA/string

ƒ_{LED_PWM}= 4.9 kHz

f_SW= 2.2 MHz

4 strings

100 mA/string

f_{LED_PWM}= 4.9 kHz

Figure 7. Boost Ripple

Figure 8. Boost Ripple

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8 Detailed Description

8.1 Overview

The LP8860-Q1 is a high-voltage LED driver for automotive infotainment, LED clusters, and medium-sized LCD

backlight applications with a boost controller. The device can be used as a stand-alone device, with a simple

four-wire control:

•

VDDIO/EN for enable

PWM input for brightness control

FAULT output to indicate fault condition

NSS input for fault reset

Alternatively, the LP8860-Q1 can be controlled through I²C or SPI serial interface which allows wide range of

user-specific configurable features.

8.1.1 Boost Controller

The boost controller generates a 16-V to 48-V supply for LED strings. To optimize LED drive efficiency the boost

controller includes adaptive output voltage control which gets feedback from monitoring the internal LED current

sinks voltage circuit. This feature minimizes power consumption by adjusting the boost voltage to lowest

sufficient level in all conditions.

Boost switching frequency can be set in a wide range from 100 kHz to 2.2 MHz. This enables system

optimization for both high power applications, where efficiency is critical, and for lower power applications where

small solution size can be achieved with high boost switching frequency.

The LP8860-Q1 has several features for system EMI optimization:

•

Boost switching frequency can be selected either below or above AM band.

Spread spectrum can be enabled to reduce energy around the switching frequency and its harmonics.

Boost switching can be synchronized to an external clock with a dedicated SYNC input.

Gate drive strength for the external FET is controllable with EEPROM.

8.1.2 LED Output Configurations

The LP8860-Q1 has four high-precision current sinks with up to 150 mA per output capability. LED outputs can

be connected parallel to reach higher current levels.

LED outputs are highly configurable; for example, there are features such as brightness slope control, external

clock synchronization, phase shifting, adaptive headroom control, etc.

In general there are 2 main user modes:

•

Display Mode (with full feature set) and/or

Cluster Mode (with limited feature set)

These modes and features are detailed in later sections.

8.1.3 Display Mode

In Display Mode LED outputs are configured to power an LCD backlight. Maximum current per string is set by

R_ISET; alternatively, through a user-programmable EEPROM value.

Brightness is controlled with PWM input or I²C/SPI register writes. An optional sloper feature enables automatic

smooth transition between brightness levels. Sloper time can be programmed to EEPROM registers, and an

advanced slope feature allows smoother response to eye compared to traditional linear slope.

Outputs are controlled with a Phase Shift PWM (PSPWM) Scheme. Due to the phase shift between the outputs

they are not activated simultaneously which brings several benefits:

•

Peak load current from the boost output is decreased, which reduces the voltage ripple seen at the boost

output and allows smaller output capacitors.

•

Smaller ripple reduces the possible audible noise from the ceramic boost output capacitors.

PSPWM scheme multiplies the effective load frequency seen at the boost output by number of active

channels. This further reduces the audible noise by transferring the output ripple frequency above human

14

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ZHCSCK8G –MAY 2014–REVISED OCTOBER 2017

Overview (continued)

hearing.

•

Optical ripple through LCD panel is reduced, helping to reduce the “waterfall” effect which is caused by

asynchronous backlight ripple and LCD refresh.

PWM output frequency is set with EEPROM registers from 4.9 kHz to 39 kHz. Selecting output frequency

depends on the number of strings used, system requirements for the frequency, and desired dimming ratio.

Dimming resolution is a function of PWM output frequency — the higher the frequency, the lower the resolution.

User can choose to increase resolution by:

•

enabling dithering function (optional through EEPROM), or

increasing internal clock frequency.

Increasing internal clock frequency increases device current consumption.

In high-quality display systems an "anti-waterfall" feature may be required. The LP8860-Q1 supports this by

offering output synchronization to the LCD refresh signal through VSYNC input. VSYNC input is synchronized to

outputs through internal PLL; EEPROM and filtering are described in later sections.

8.1.4 Cluster Mode

In Cluster mode LED strings have independent control but fewer features enabled than in Display Mode.

Brightness (PWM and current) are independently controlled for all 4 outputs. When there is an unequal number

of LEDs per channel, the LP8860-Q1 adaptive voltage control is not used in Cluster mode; therefore, boost

output voltage is fixed (or externally controlled or powered).

In Cluster mode PWM frequency can be set through EEPROM, and Phase Shift PWM mode is enabled.

Cluster mode does not support the PWM input pin, hybrid dimming, slope control or dither mode.

8.1.5 Hybrid Dimming

Hybrid dimming combines both PWM and current-dimming benefits offering the best optical efficiency to drive

LEDs. At higher brightness levels only the LED constant current is controlled; at lower brightness levels LED

brightness is controlled by adding PWM on top of low constant current value.

Because LED optical efficacy declines with high forward current, reducing the current yields better system optical

efficiency compared with conventional PWM dimming. An additional benefit of current dimming is reduced EMI

compared to PWM switching. PWM dimming is used with lower brightness values to achieve a higher dimming

ratio. The optimum switch point between PWM and current dimming is programmable and depends on the LED

type.

8.1.6 Charge Pump and Square Waveform (SQW) Output

The gate driver for the external boost FET can be powered directly from the VDD input or from the charge pump

integrated into the LP8860-Q1. When a 5-V rail is available in the system for VDD supply, it is typically a high

enough voltage to drive the external FET, and the internal charge pump can be disabled. In this case, the VDD

and CPUMP pins must be shorted together, and the fly cap can be removed. When the system VDD is not high

enough to drive the gate of the boost FET (typical case is 3.3 V), the charge pump can be used to multiply the

gate drive voltage to 2× VDD.

The SQW output provides a 100-kHz square wave signal (1 mA maximum) with amplitude equal to the charge-

pump output voltage. When the charge pump is disabled, the amplitude of the SQW signal is equal to VDD. See

Charge Pump and High Output Voltage Application sections for usage examples.

8.1.7 Power-Line FET

Some automotive systems require a safety switch to disconnect the driver device from the battery. The LP8860-

Q1 offers a power-line FET control circuit, which limits inrush current from the power line during start-up and

reduces standby power consumption by disconnecting device from the power-line during an off state. This FET

disconnects the boost and LED strings from the input during fault conditions. For example, when the input

voltage is above the overvoltage protection (OVP) level, the power-line FET disconnects the LED strings from the

power-line to protect LED outputs against overheating.

15

LP8860-Q1

ZHCSCK8G –MAY 2014–REVISED OCTOBER 2017

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Overview (continued)

Depending on which fault has shut down the power-line FET, the device can enter automatic fault recovery state

where the power-line FET is turned on in 100-ms time periods to see if the fault condition has been removed. If

the fault was only short-term, and normal operation condition returns, the device turns back on automatically.

8.1.8 Protection Features

Extensive fault-detection and protection features of the LP8860-Q1 include:

•

Open-string and shorted LED detections

LED fault detection prevents system overheating in case of open in some of the LED strings

–

•

Boost overcurrent

Boost overvoltage

VIN input overvoltage protection

–

Threshold sensing from VSENSE_P pin

VIN input undervoltage protection

Threshold sensing from VSENSE_P pin

VIN input overcurrent protection

Threshold sensing across R_ISENSEresistor

•

–

•

VDD input undervoltage lockout

Thermal shutdown in case of die overtemperature (165°C nominal)

Fault protection thresholds are EEPROM programmable and some protection features can be disabled, or

masked, if necessary.

A fault condition is indicated through the FAULT pin. If an I²C/SPI interface is used, the fault reason can be read

from the register, and flags can be cleared with register write.

8.1.9 Advanced Thermal Protection Features

The LP8860-Q1 has a unique features for protecting against overheating:

1. Die temperature based Thermal de-rating function. Average LED current is automatically lowered when die

temperature increases above a predefined (90ºC, 100ºC, or 110ºC) level. Decreasing LED current reduces

thermal loading on the device and prevents overheating.

2. An external NTC sensor-based protection, where a sensor can be placed close to LEDs to protect them from

overheating. The sensor is connected to the TSENSE pin of the device. Two methods are available:

–

Current de-rating, where the LED current is lowered proportionally to the temperature measured with the

external NTC sensor. This method is available only if LED max current is set with R_ISETresistor.

–

Brightness limitation above a predefined temperature

16

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8.2 Functional Block Diagram

R_ISENSE

Q2

VIN

D

C_IN

C_OUT

VSENSE_P VSENSE_N

SD

POWER-LINE FET CONTROL

C_2X

C1N

C1P

VDD

C_VDD

VDD

C_CPUMP

CHARGE PUMP

CPUMP

SQW

FB

Q1

GD

SYNC

BOOST

ISENSE

CONTROLLER

+

R_SENSE

ISENSE_GND

PGND

FILTER

4 x LED

CURRENT

SINK

ANALOG BLOCKS

(CLOCK

GENERATOR, PLL,

VREF, ADC, DACs

etc.)

OUT1

OUT2

OUT3

OUT4

LGND

ISET

R_ISET

TSENSE

NTC

tº

PWM

DIGITAL BLOCKS

(FSM, PWM

VSYNC

DETECTOR,

BRIGTNESS

CONTROL,

FAULT

SLOPER, HYBRID

DIMMING, SAFETY

LOGIC etc.)

VDDIO/EN

SCLK/SCL

MOSI/SDA

MISO

SPI/I²C

INTERFACE

EEPROM

NSS

IF

SGND

EXPOSED PAD

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8.3 Feature Description

8.3.1 Clock Generation

The LP8860-Q1 has an internal 10-MHz oscillator which is used for clocking the PWM input duty cycle

measurement. The 10-MHz clock is divided by two, and the 5-MHz clock is used for clocking the state machine

and internal timings.

The internal 5-MHz clock can be used for generating the LED PWM output frequency directly or it can be

multiplied with an internal PLL to achieve higher resolution. The higher clock frequency for the PWM generation

block allows the higher resolution; however, the tradeoff is higher power consumption of the part. Clock

multiplication is set with <PWM_RESOLUTION[1:0]> EEPROM bits.

8.3.1.1 LED PWM Clock Generation With VSYNC

Unsynchronized LCD line scanning and LED backlight ripple may cause a “waterfall” effect. Synchronizating LED

output PWM frequency with video processor or timing controller VSYNC/HSYNC signal can reduce this effect.

The PLL can be used for generating required PWM generation clock from the VSYNC signal. This ensures that

the LED output PWM remains synchronized to the VSYNC signal, and there is no clock variation between the

LCD display video update and the LED backlight output frequency. If PWM_COUNTER_RESET = 1, the VSYNC

signal rising edge restartsthe PWM generation, ensuring there is no clock drifting. The slow divider is intended for

LED PWM frequency synchronization with an external VSYNC. An external filter connected to the FILTER pin

must be used only if a slow divider is enabled — otherwise the LP8860-Q1 uses internal compensation.

The ƒ_OUTof the PLL must be chosen in the 5-MHz to 40-MHz range. If VSYNC is enabled, the signal must be

active before VDDIO/EN is set high and present whenever VDDIO/EN is high.

VSYNC 50...150 Hz

or 50...150 kHz

SYNC_PRE_DIVIDER[3:0]

V_BOOST

PWM_FREQ[3:0]

PWM_COUNTER_RESET

PWM_RESOLUTION[1:0]

LED_STRING_CONF[2:0]

EN_SYNC

Predivider

PLL

0

1

PWM Generator

Phase

Detector

1

VCO

Filter

5 MHz

10 MHz Internal

Oscillator

Divider

f/2

0

f_OUT

EN_PLL

SEL_DIVIDER

State Machine,

PWM Input, Internal

Timings, Slope etc.

1

0

PWM Input

Divider

1/N_fast

Divider

R_SEL[1:0]

PWM_RESOLUTION[1:0]

0

1

Divider

1/N_slow

PWM_SYNC

SLOW_PLL_DIV[12:0]

Figure 9. PLL Clock Generation

8.3.1.2 LED PWM Frequency and Resolution

LED output PWM frequency is selected with <PWM_FREQ[3:0]> EEPROM register when using a 5-MHz internal

oscillator for generating PWM output. <LED_STRING_CONF[2:0]> bits define phase shift between LED outputs

as described later. <PWM_RESOLUTION[1:0]> EEPROM bits select the PLL output frequency and hence the

LED PWM resolution. PWM frequencies with <EN_SYNC> = 0 are listed in Table 1.

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Feature Description (continued)

NOTE

If the VSYNC signal is used for generating PWM output frequency, it affects all clock

frequencies, as well as the LED PWM output frequency. The EEPROM Bit Explanations

section explains how all the dividers affect the output clocks.

V_BOOST

PWM_FREQ[3:0]

LED_STRING_CONF[2:0]

5 MHz

PWM Generator

EN_PLL=0

PWM_RESOLUTION[1:0]=00

PWM_COUNTER_RESET=0

Figure 10. PWM Clocking With Internal Oscillator

V_BOOST

PWM_FREQ[3:0]

PWM_RESOLUTION[1:0]

LED_STRING_CONF[2:0]

PLL

5 MHz

Phase

Detector

VCO

Filter

PWM Generator

Divider

1/N_fast

Fout=10, 20, 40 MHz

EN_PLL=1

EN_SYNC=0

SEL_DIVIDER =1

PWM_COUNTER_RESET=0

PWM_RESOLUTION[1:0]

Figure 11. PWM Clocking With PLL, Internal Oscillator as Reference

Table 1. Output PWM Frequency and Resolution With Internal Oscillator

00

01

10

11

OSC = 5 MHz

OSC = 10 MHz

OSC = 20 MHz

OSC = 40 MHz

PWM_FREQ[3:0]

PWM_RESOLUTION[1:0]

PWM FREQUENCY (Hz)

RESOLUTION (bit)

1111

1110

1101

1100

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

39063

34180

30518

29297

28076

26855

25635

24412

23192

21973

20752

19531

17090

13428

7

8

9

10

11

9

10

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Feature Description (continued)

Table 1. Output PWM Frequency and Resolution With Internal Oscillator (continued)

00

01

10

11

OSC = 5 MHz

OSC = 10 MHz

OSC = 20 MHz

OSC = 40 MHz

PWM_FREQ[3:0]

PWM_RESOLUTION[1:0]

PWM FREQUENCY (Hz)

RESOLUTION (bit)

0001

0000

9766

4883

9

10

11

12

13

10

VSYNC 50...150 Hz

or 50...150 kHz

V_BOOST

PWM_FREQ[3:0]

PWM_COUNTER_RESET

PWM_RESOLUTION[1:0]

LED_STRING_CONF[2:0]

SYNC_PRE_DIVIDER[3:0]

PLL

Phase

Detector

VCO

Filter

Predivider

PWM generator

EN_PLL=1

SEL_DIVIDER=0

EN_SYNC=1

PWM_SYNC=1

Divider

1/N_slow

SLOW_PLL_DIV[12:0]

Figure 12. PWM Synchronization With External VSYNC Input

PWM clock frequencies with different <SEL_DIVIDER>, <EN_PLL>, and <EN_SYNC> combinations are listed in

Table 2.

Table 2. PLL Clock and LED PWM Frequency

PWM_SYNC

SEL_DIVIDER

EN_PLL

EN_SYNC

PLL CLOCK

5 MHz

PWM FREQUENCY

See Table 1

0

X

1

0

1

0

1

5, 10, 20, 40 MHz

See Table 1

SYNC × R_SEL[1:0] ×

SLOW_PLL_DIV[12:0]/

SYNC_PRE_DIV[3:0]

PLL clock / GEN_DIV

1

0

1

SYNC × GEN_DIV ×

SLOW_PLL_DIV[12:0]/

SYNC_PRE_DIV[3:0]

PLL clock / GEN_DIV

GEN_DIV coefficients and resolution (bit) are listed on Table 3.

Table 3. GEN_DIV Coefficients and Resolution

PWM_RESOLUTION[1:0]

00

01

10

11

PWM_

FREQ[3:0]

STEP GEN_DIV RES

(bits)

STEP

GEN_DIV

RES STEP

(bits)

GEN_DIV

RES STEP

(bits)

GEN_DIV

RES

(bits)

0000

0001

0010

0011

0100

0101

0110

64

1024.00

512.00

372.36

292.57

256.00

240.94

227.56

10

9

32

64

2048.00

1024.00

744.73

585.14

512.00

481.88

455.11

11

10

9

16

32

44

56

64

68

72

4096.00

2048.00

1489.45

1170.29

1024.00

963.76

12

11

10

9

8

8192.00

4096.00

2978.91

2340.57

2048.00

1927.53

1820.44

13

12

11

10

128

176

224

256

272

288

16

22

28

32

34

36

8

88

8

112

128

136

144

9

8

9

7

8

7

8

910.22

9

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Table 3. GEN_DIV Coefficients and Resolution (continued)

PWM_RESOLUTION[1:0]

00

01

10

11

PWM_

FREQ[3:0]

STEP GEN_DIV RES

(bits)

STEP

GEN_DIV

RES STEP

(bits)

GEN_DIV

RES STEP

(bits)

GEN_DIV

RES

(bits)

0111

1000

1001

1010

1011

1100

1101

1110

1111

304

320

336

352

368

384

400

448

512

215.58

204.80

195.05

186.18

178.09

170.67

163.84

146.29

128.00

7

152

160

168

176

184

192

200

224

256

431.16

409.60

390.10

372.36

356.17

341.33

327.68

292.57

256.00

8

76

80

862.32

819.20

780.19

744.73

712.35

682.67

655.36

585.14

512.00

9

38

40

42

44

46

48

50

56

64

1724.63

1638.40

1560.38

1489.45

1424.70

1365.33

1310.72

1170.29

1024.00

10

84

88

92

96

100

112

128

Dithering allows increased resolution and smaller average steps size. Dithering can be programmed with

EEPROM bits <DITHER[2:0]> 0 to 4 bits. Figure 13 shows 1-bit dithering. For 3-bit dithering, every 8^thpulse is

made 1 LSB longer to increase the average value by 1/8^th. Dither is available in steady state condition when

<EN_STEADY_DITHER> is high, otherwise during slope only.

PWM value 510 (10-bit)

+1LSB

PWM value 510 ½ (10-bit)

PWM value 511 (10-bit)

Figure 13. Example of the Dithering, 1-Bit Dither, 10-Bit Resolution

8.3.2 Brightness Control (Display Mode)

The LP8860-Q1 LED outputs can be configured to display or cluster mode. The following sections describe

display mode options. Cluster mode is a special mode with individually controlled LED outputs. See Cluster

Mode section for details.

The LP8860-Q1 controls the brightness of the display with conventional PWM or with Hybrid PWM and Current

dimming. Brightness control is received either from PWM input pin or from I²C/SPI register bits. The brightness

source is selected with <BRT_MODE[1:0]> bits as follows:

Table 4. Brightness Control Selection

BRT_MODE[1:0]

BRIGHTNESS CONTROL

00

01

10

11

PWM input duty cycle

PWM input duty cycle x Brightness register

Brightness register

PWM direct control (PWM in = PWM out)

8.3.2.1 PWM Input Duty Cycle Based Control

In this mode the LED brightness is controlled by the input PWM duty cycle. The PWM detector block measures

the duty cycle in the PWM pin and uses this 16-bit value to control the duty cycle of the LED output PWM. Input

PWM period is measured from rising edge to the next rising edge.

The ratio of input PWM frequency and 10-MHz sampling clock defines resolution reachable with external PWM.

PWM input block timeout is 24 ms after the last rising edge; it must be taken into account for 0% and 100%

brightness setting. For setting 100% brightness, a high-level PWM input signal must last at least 24 ms. The

minimum on and off time for the PWM input signal is 400 ns.

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8.3.2.2 Brightness Register Control

With brightness register control the LED output PWM is controlled with 16-bit resolution <DISP_CL1_BRT[15:0]>

register bits.

8.3.2.3 PWM Input Duty × Brightness Register

In this mode the PWM input duty cycle value is multiplied with the 16-bit <DISP_CL1_BRT[15:0]> register value

to achieve the LED output PWM.

8.3.2.4 PWM-Input Direct Control

With PWM-input direct control the output PWM directly follows the input PWM frequency and duty cycle. Due to

the internal logic structure the input is clocked with the 5-MHz clock or the PLL clock (if it is enabled). The output

PWM delay can be 5 to 6 clock cycles from input PWM.

In the direct control mode several of the advanced features are not available: Phase Shift PWM (PSPWM),

brightness slope, dither, Hybrid PWM and Current dimming, and LED current limitation with external NTC.

Dimming ratio can be calculated as the ratio between the brightness PWM input signal and sampling clock (5-

MHz or PLL clock) frequencies. In direct mode PWM duty cycle must be less than 100%. Boost adaptive mode

turns off at 100% duty cycle.

8.3.2.5 Brightness Slope

Sloper makes the smooth transition from one brightness value to another. Slope time can be programmed with

EEPROM bits <PWM_SLOPE[2:0]> from 0 to 511 ms. Slope time is used for sloping up and down. Advanced

slope makes brightness changes smooth for eye.

Table 5. Slope Time

PWM_SLOPE[2:0]

SLOPE TIME

disabled

1 ms

000

001

010

011

100

101

110

111

2 ms

52 ms

105 ms

210 ms

315 ms

511 ms

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Brightness (PWM)

Sloper Input

Time

Steady state with or

without dithering

Brightness (PWM)

PWM Output

Normal slope

If dither is enabled it will

be used during transition

to enable smooth effect

Advanced slope

Time

Slope Time

Figure 14. Sloper Operation

8.3.2.6 LED Dimming Methods

In additional to conventional PWM dimming control the LP8860-Q1 supports Hybrid PWM and Current dimming.

Hybrid dimming combines the PWM and current dimming methods. PWM dimming operates with a lower range

of light, and linear current dimming is used with higher brightness values. If the <EN_PWM_I EEPROM> bit is set

to 1, the system enables hybrid dimming. Principles of PWM dimming and Hybrid PWM and Current dimming are

illustrated by Figure 15. Only 25% switch points and slope gain = 1 are shown for simplicity.

Max current can be set with EEPROM bits or

with R

resistor

ISET

PWM DIMMING

CURRENT DIMMING

100%

75%

50%

25%

I_SLOPE[2:0]=000

Slope gain = 1

GAIN_CTRL[2:0]=011

Switch point = 25%

100%

25%

50%

BRIGHTNESS

Figure 15. Principles of PWM Dimming and Hybrid PWM and Current Dimming

LED forward voltage increases and efficiency declines when forward current is increased. Use of constant

current with PWM dimming at lower brightness and current dimming at greater brightness (instead of PWM

dimming at full brightness range), yields better optical efficiency and resolution especially at lower brightness

values. The optimum switch point between PWM and current dimming modes and current slope depend on the

LED type.

PWM control ranges from 12.5% to 50% and the current slope can be selected using <GAIN_CTRL[2:0]> and

<I_SLOPE[2:0]> EEPROM bits, respectively (see Table 6 and Table 7).

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100%

25%

BRIGHTNESS

HYBRID DIMMING

~20%

PWM DIMMING

BRIGHTNESS

Figure 16. Optical Efficiency Improvement With PWM and Current Dimming

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Table 6. Gain Control Selections

SWITCH POINT FROM PWM

TO CURRENT DIMMING

GAIN_CTRL[2:0]

000

001

010

011

100

101

110

111

50.0%

40.6%

31.3%

25.0%

21.9%

18.8%

15.6%

12.5%

Table 7. Current Slope Control Selections

I_SLOPE[2:0]

SLOPE GAIN

1.000

000

001

010

011

100

101

110

111

1.023

1.047

1.070

1.094

1.117

1.141

1.164

The current setting for DISP_CL1_CURRENT[11:0] in Hybrid PWM and Current dimming mode can be defined

by the following formula (assuming individual LED sink current correction DRV_OUTx_CORR[3:0] is 0%):

(100%- GAIN_CTRL[2 : 0])

I_{DISP_CL1_CURRENT[11:0]}= I_MAX-DRV _LED_CURRENT_SCALE[2 : 0]ìI_SLOPE[2 : 0]ì

100%

(1)

Example of calculation for Hybrid PWM and Current dimming mode, 100-mA maximum output current:

Target maximum current 100 mA

Maximum scale 100 mA

(DRV_LED_CURRENT_SCALE[2:0]=101)

I_{DISP_CL1_CURRENT}= 100 – 100 × 1 × ((100 – 25) / 100) = 25 mA

Slope = 1.000 (I_SLOPE[2:0]=000)

Switch point = 25% (GAIN_CTRL[2:0]=011)

Example of calculation for Hybrid PWM and Current dimming mode, 23-mA maximum output current:

Target maximum current 23 mA

Maximum scale 25 mA

(DRV_LED_CURRENT_SCALE[2:0]=000)

I_{DISP_CL1_CURRENT}= 23 – 25 × 1.094 × ((100 – 25) / 100) = 2.49 mA

Slope = 1.094 (I_SLOPE[2:0]=100)

Switch point = 25% (GAIN_CTRL[2:0]=011)

NOTE

1. Formula is only approximation for the actual value.

2. DISP_CL1_CURRENT[11:0] value must be chosen to avoid current saturation before 100%

brightness is achieved.

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8.3.2.7 PWM Calculation Data Flow for Display Mode

Figure 17 shows the PWM calculation data flow for display mode. In PWM direct control mode most of the blocks

are bypassed, and this flow chart does not apply.

10

MHz

Clock

External

Temp Sensor

HYSTERESIS

[1:0]

PWM_SLOPE[3:0]

EN_BRT_ADV_SLOPE

I_SLOPE[2:0]

BRT_MODE[1:0]

00

DITHER[2:0]

Current 12-bit

PWM Input

Signal

16-bit

PWM

PWM &

Current

Control

16-bit

01

Advanced

Slope

PWM

Comparator

Temperature

Regulator

...

Detector

Sloper

Dither

PWM

16-bit

10

11

PWM

freq

DISPLAY

MODE LED

CURRENT

SINKS

16-bit

11-bit

EN_PWM_I

GAIN_CTRL[2:0]

PWM

Counter

Brightness

Register

Internal

Temp Sensor

PWM_RESOLUTION

[1:0]

PWM_FREQ[3:0]

PLL Clock 5...40 MHz

Figure 17. PWM Data Flow Calculation

Table 8. PWM Calculation Blocks

BLOCK NAME

DESCRIPTION

PWM detector block measures the duty cycle of the input PWM signal. Resolution depends on the

input signal frequency. Hysteresis selection sets the minimum allowable change to the input.

Smaller changes are ignored.

PWM detector

Brightness register

Brightness mode control

16-bit register for brightness setting <DISP_CL1_BRT[15:0]>

Brightness control block gets 16-bit value from the PWM detector, and also 16-bit value from the

brightness register <DISP_CL1_BRT[15:0]>. <BRT_MODE[1:0]> selects whether to use PWM input

duty cycle value, the brightness register value or multiplication.

Temperature regulator reduces LED PWM duty cycle depending on internal and external

temperature sensor.

See LED Current Dimming With Internal Temperature Sensor and LED Current Limitation With

External NTC Sensor for details

Temperature regulator

External temperature sensor

Internal temperature sensor

External NTC temperature sensor

Internal die temperature sensor

Sloper makes the smooth transition from one brightness value to another. Slope time can be

adjusted from 0 ms to 511 ms with <PWM_SLOPE[2:0]> EEPROM bits.

Sloper

Advanced sloper

Advanced slope makes brightness changes smoother for eye; see Brightness Slope for details

Hybrid PWM and Current dimming improves the optical efficiency of the LEDs by using PWM

control with lower brightness values and current control with greater values. <EN_PWM_I>

EEPROM bit enables Hybrid PWM and Current control. PWM dimming range can be set 12.5 to

50% of the brightness range with <GAIN_CTRL[2:0]> EEPROM bits. Current slope can be adjusted

by using the <I_SLOPE[2:0]> EEPROM bits. See LED Dimming Methods for details

PWM and Current Control

Dither

With dithering the output resolution can be further increased. This way the brightness change steps

are not visible to eye. The amount of dithering is 0 to 4 bits, and is selected with <DITHER[2:0]>

EEPROM bits.

PWM comparator compares the PWM counter output to the value received from the dither block.

Output of the PWM comparator directly controls the LED current sinks. If Phase Shift PWM

(PSPWM) mode is used, the PWM counter values for each LED output are modified by summing an

offset value to create different phases.

PWM comparator

PWM counter

Overflowing 16-bit PWM counter creates new PWM cycle. Step for incrementation is defined by

<PWM_FREQ[3:0]> and <PWM_RESOLUTION[1:0]> bits, see Table 3.

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8.3.3 LED Output Modes and Phase Shift PWM (PSPWM) Scheme

The PSPWM scheme allows delaying the time when each LED output is active. When the LED outputs are not

activated simultaneously, the peak load current from the boost output is greatly decreased. This reduces the

ripple seen on the boost output and allows smaller output capacitors. Reduced ripple also reduces the output

ceramic capacitor audible ringing. The PSPWM scheme also increases the load frequency seen on boost output

up to 4 times, therefore transferring possible audible noise to a frequency above human hearing range. In

addition, “optical ripple” through the LCD panel is reduced helping in waterfall noise reduction.

Figure 18 shows the available LED output modes. The number of LED outputs used can be one to four; outputs

can be tied together to increase current for one string or all four strings can be independently controlled in the

cluster mode.

In <LED_STRING_CONF[2:0]> = 000 the phase difference between channels is 90 degrees. This mode is

intended for application in Figure 53. When <LED_STRING_CONF[2:0] > = 001 the phase difference between 3

channels in display mode is 120 degrees. This mode is intended for application shown in Figure 63. When

<LED_STRING_CONF[2:0]> = 010 the phase difference between 2 channels in display mode is 180 degrees,

channels 3 and 4 in cluster mode, intended for application illustrated by Figure 60. LED strings not used in

Display mode can be used for Cluster mode, or not used. When <LED_STRING_CONF[2:0]> = 111 all strings

are in cluster mode.

Phase shift

90 degrees

Cycle time

1/(f_PWM

Phase shift

120 degrees

Cycle time

1/(f_PWM

)

V_BOOST

External

power

supply

OUT1

DISPLAY

OUT1

DISPLAY

OUT2

DISPLAY

OUT2

DISPLAY

Output 4 in

cluster mode

or not

1

2

3

4

connected

OUT3

DISPLAY

1

2

3

OUT3

DISPLAY

4

OUT4

CLUSTER

OUT4

DISPLAY

4-channel Phase Shift PWM (Mode 0)

3-channel Phase Shift PWM (Mode 1)

Cycle time

Phase shift 120 degrees

1/(f_PWM

)

Phase shift

180 degrees

Cycle time

1/(f_PWM

External

power

supply

OUT1

DISPLAY

)

V_BOOST

External

power

supply

OUT1

DISPLAY

V_BOOST

OUT2

CLUSTER

Outputs 2,3

and 4 in

cluster mode

or not

OUT2

Outputs 3 and

4 in cluster

mode or not

connected

1

2

3

4

DISPLAY

OUT3

CLUSTER

1

2

3

4

connected

OUT3

CLUSTER

OUT4

CLUSTER

OUT4

CLUSTER

Phase shift 120 degrees

2-channel Phase Shift PWM (Mode 2)

Phase shift

Cycle time

Phase Shift PWM (Mode 3)

V_BOOST

180 degrees

1/(f_PWM

)

V_BOOST

Cycle time

1/(f_PWM

)

OUT1

OUT2

DISPLAY

OUT3

1

2

3

OUT4

DISPLAY

4

1

2

3

OUT3

4

OUT4

DISPLAY

Mode 4

Mode 5

Phase shift

90 degrees

Cycle time

1/(f_PWM

)

Phase shift

120 degrees

Cycle time

V_BOOST

1/(f_PWM

)

OUT1

CLUSTER

V_BOOST

External

power

OUT1

OUT2

DISPLAY

supply

OUT2

CLUSTER

Outputs 3 and

4 in cluster

mode or not

connected

OUT3

CLUSTER

OUT3

CLUSTER

1

2

3

4

1

2

3

4

OUT4

CLUSTER

OUT4

CLUSTER

Phase shift

120 degrees

Mode 6

Mode 7

Figure 18. Phase Shift Modes

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Table 9. Description of the LED Output Modes

MODE

LED_STRING_CONF[2:0]

DESCRIPTION

0

000

4 separate LED strings with 90° phase shift

3 separate LED strings with 120° phase shift (String 4 in cluster mode or

not used)

1

001

2 separate LED strings with 180° phase shift (Strings 3 and 4 in cluster

mode or not used)

2

3

4

5

6

7

010

011

100

101

110

111

1 LED string. (Strings 2,3 and 4 in cluster mode or not used)

2 LED strings (1+2, 3+4) with 180° phase shift. Strings with same phase

can be connected together.

1 LED string (1+2+3+4). All strings with same phase (can be tied together).

1 LED string (1+2). 1st and 2nd strings tied with same phase, strings 3 and

4 are in cluster mode or not used

All strings are used in cluster mode with 90° phase shift

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8.3.4 LED Current Setting

EXT_TEMP_GAIN[3:0]

EXT_TEMP_MINUS[1:0]

EXT_TEMP_I_DIMMING_EN

TEMPERATURE

TSENSE

DRV_OUT1_CORR[3:0]

CURRENT

DIMMING

DRV_EN_EXT_LED_CUR_CTRL

LED CURRENT

SINK 1

OUT1

EXTERNAL

ISET

CURRENT

SETTING

1

0

DAC

V_REF

DRV_OUT2_CORR[3:0]

CL2_CURRENT[7:0]

CL3_CURRENT[7:0]

DAC

OUT2

OUT3

LED CURRENT

SINK 2

DRV_OUT3_CORR[3:0]

LED CURRENT

SINK 3

DRV_OUT4_CORR[3:0]

CL4_CURRENT[7:0]

DISP_CL1_CURRENT[11:0]

OUT4

DAC

LED CURRENT

SIUNK 4

DRV_LED_BIAS_CTRL[1:0]

DRV_EN_SPLIT_FET

DRV_LED_CURRENT_SCALE[2:0]

Figure 19. LED Current Setting

The output LED current can be set by a register. Maximum output LED current can be set by an external resistor

when that option is enabled. For strings in cluster mode current for every LED output can be set independently.

The maximum current for the LED outputs in display mode are controlled with <DISP_CL1_CURRENT [11:0]>

bits. Current for the outputs in the cluster mode are controlled separately by the register bits

<DISP_CL1_CURRENT[11:0]>, <CL2_CURRENT[7:0]>, <CL3_CURRENT[7:0]>, and <CL4_CURRENT[7:0]>

respectively. In the display mode resolution for current control is 12 bits. In the cluster mode resolution is 8 bits

for all outputs except OUT1. For OUT1 maximum current resolution is always 12 bits.

Additionally, current for every output current can be scaled with <DRV_LED_CURRENT_SCALE[2:0]> bits (see

Table 11) and can be corrected by <DRV_OUTx_CORR[3:0]> EEPROM bits. The adjustment range is shown in

Table 12 Maximum current settings are effective for display and cluster modes.

Table 11. LED Current Scaling

DRV_LED_CURRENT_SCALE[2:0]

MAXIMUM CURRENT

25 mA

000

001

010

011

100

101

110

30 mA

50 mA

60 mA

80 mA

100 mA

120 mA

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Table 11. LED Current Scaling (continued)

DRV_LED_CURRENT_SCALE[2:0]

111

MAXIMUM CURRENT

150 mA

When maximum current is controlled by anexternal resistor R_ISET(<DRV_EN_EXT_LED_CUR_CTRL>=1),

current for outputs in display mode or for OUT1 in cluster mode can be calculated as follows:

3000ìV

^BGì

DISP_CL1_CURRENT[11: 0] DRV _LED_CURRENT_SCALE[2: 0] (DRV_OUTx_CORR[3 : 0] +100)

I_LED

=

ì

R

4095

150

100

ISET

(2)

Where V_BG= 1.2 V.

space

For example, if <DISP_CL1_CURRENT[11:0]> is 0xFFF, <DRV_LED_CURRENT_SCALE[0:2]> is 111, and a

24-kΩ R_ISETresistor is used, then the LED maximum current is 150 mA.

When current control with external resistor is disabled (<DRV_EN_EXT_LED_CUR_CTRL>=0) LED current for

outputs in display mode or for OUT1 in cluster mode can be calculated as follow:

DISP_CL1_CURRENT[11: 0]

(DRV _OUTx _CORR[3 : 0] +100)

I_LED

=

ìDRV _LED_CURRENT_SCALE[2: 0]ì

4095

100

(3)

When maximum current control with external resistor is enabled, LED current for OUT2…OUT4 outputs in cluster

mode is defined as:

3000ì V_BG

R_ISET

CLx _CURRENT[7 : 0] DRV _LED_CURRENT _SCALE[2 : 0] (DRV _OUTx _CORR[3 : 0] +100)

I_LED

=

ì

255

150

100

(4)

Otherwise, when current control with external resistor is disabled:

CLx_CURRENT[7 : 0]

(DRV _OUTx_CORR[3 : 0] +100)

I_LED

=

ìDRV _LED_CURRENT_SCALE[2: 0]ì

255

100

(5)

Correction value is defined by <DRV_OUTx_CORR[3:0]> shown in Table 12:

Table 12. Individual Current Correction

DRV_OUTx_CORR[3:0]

CORRECTION

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

6.50%

5.60%

4.70%

3.70%

2.80%

1.90%

0.90%

0.00%

–0.9%

–1.90%

–2.80%

–3.70%

–4.70%

–5.60%

–6.50%

–7.40%

NOTE

Formulas are only approximation for the actual current.

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The <DISP_CL1_CURRENT[11:0]> register is initialized during start-up by the <LED_CURRENT_CTRL[11:0]>

EEPROM bits. <DRV_LED_CURRENT_SCALE[2:0]> are initialized by the <DRV_LED_CURRENT_SCALE[2:0]>

EEPROM bits. Cluster mode current registers for outputs OUT2 and OUT3 are initialized by 0 during power on

reset.

Current register value must be not written to 0 if brightness is not zero – it may cause LED faults and adaptive

voltage control instability.

8.3.5 Cluster Mode

Cluster is a simplified mode which allows independent current and PWM control for every string in cluster mode.

In this mode brightness control is limited to conventional PWM through the SPI/I²C brightness registers. The

PWM input pin, Hybrid PWM and Current dimming mode, slope control, or dither are not available. Brightness for

different LED strings depends on <DISP_CL1_BRT[15:0]>, <CL2_BRT[12:0]>, <CL3_BRT[12:0]> and

<CL4_BRT[12:0]> registers. If OUT1 is in cluster mode, only 13 MSB are used. If all LED outputs are in the

cluster mode, LED output PWM resolution is always 13 bits, and frequency depends on

<PWM_RESOLUTION[1:0]> bits (see Table 13). If one or more of the LED outputs is in display mode, frequency,

and resolution for strings in the cluster mode is the same as for strings in the display mode (see Table 1).

CL#_CURRENT[7:0]

Cluster

Current

Register

CL#_BRT[12:0]

Cluster

...

PWM

Comparator

Brightness

Register

CLUSTER

MODE LED

CURRENT

SINKS

PWM_RESOLUTION[1:0]

PWM_FREQ[3:0]

PWM

Counter

PLL Clock 5...40 MHz

Figure 20. Cluster Mode Block Diagram

Table 13. Output PWM Frequency for Mode 7 (All Strings in Cluster Mode)

PWM_RESOLUTION[1:0]

OSC frequency (MHz)

ƒ_{LED PWM}(Hz)

00

5

01

10

20

11

40

610

1221

2442

4883

When the LP8860-Q1 is set in cluster mode, fault protection functionality is limited. Headroom for LED strings

must be between the high-voltage comparator level <DRV_LED_FAULT_THR[1:0]> and low-voltage comparator

level <DRV_HEADR[2:0]> (which depend upon saturation voltage); otherwise a fault is generated.

Adaptive boost control does not follow strings in cluster mode. Display mode strings and cluster mode strings

must not be connected to the same boost. When LED strings in display and cluster modes are connected to the

same boost, LED open or short faults may be generated if the LED forward-voltage mismatch is too high.

If all LED outputs are in cluster mode, boost output voltage is fixed and must be set by EEPROM

<BOOST_INITIAL_VOLTAGE[5:0]> bits to a value high enough to ensure correct LED string operation in all

conditions.

<EN_CL_LED_FAULT>=0 disables cluster LED fault detection, even if all LED strings are in the cluster mode.

The current de-rating (based on the internal temperature sensor) and LED current limitation (based on external

temperature sensor) are not functional in this mode, and analog current dimming based on the external sensor

functionality is limited (LED shutdown for high temperature is not operational).

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8.3.6 Boost Controller

The LP8860-Q1 boost controller generates a 16-V to 48-V supply voltage for the LEDs. Output voltage can be

increased by an external resistive voltage divider connected to the FB pin, but voltage lower than 16 V is not

supported.

The output voltage can be controlled either with EEPROM register bits <BOOST_INITIAL_VOLTAGE[5:0]>, or

automatic adaptive boost control can be used. During start-up the output voltage is ramped to default start-up

voltage <BOOST_INITIAL_VOLTAGE[5:0]> where it then adapts to the required voltage based on LED output

headroom voltage (if adaptive mode has been enabled in EEPROM). Initial voltage for adaptive voltage control

mode must be higher than LED string voltage — otherwise the system may generate a boost overvoltage fault

during VDDIO/EN pin toggling if the output boost capacitor is not discharged below the initial voltage before the

next boost start-up. A different option is to set <MASK_BOOST_OVP_STATUS> bit high to prevent a boost

overvoltage fault.

The converter is a magnetic switching PWM mode DC-DC converter with a current limit. The topology of the

magnetic boost converter is called Current Programmed Mode (CPM) control, where the inductor current is

measured and controlled with the feedback. Switching frequency is selectable from 100 kHz and 2.2 MHz with

EEPROM bits <BOOST_FREQ_SEL[2:0]>. In most cases lower frequency has the highest system efficiency.

In adaptive mode the boost output voltage is adjusted automatically based on LED current sink headroom

voltage. Boost output voltage control step size is, in this case, 125 mV to ensure as small as possible current

sink headroom and high efficiency. The adaptive mode is enabled with the <EN_ADAP EEPROM> bit. If boost is

started with adaptive mode enabled, then the initial boost output voltage value is defined with the

<BOOST_INITIAL_VOLTAGE[5:0]> EEPROM register bits in order to eliminate long output voltage iteration time

when boost is started after VDDIO/EN toggling or power-on reset.

Boost can be clocked by an external SYNC signal (100 kHz to 2.2 MHz); minimum pulse length for the signal is

200 ns. If an external SYNC disappears, boost uses internal frequency defined by <BOOST_FREQ_SEL[2:0]>

EEPROM bits. The boost frequency with external SYNC and EEPROM bits-defined frequency need to be close

to each other; maximum frequency mismatch is ±25%. The boost controller has optional spread-spectrum

switching operation (±3% from central frequency, 1.875-kHz modulation frequency) which reduces spectrum

spikes around the switching frequency and its harmonic frequencies.

Further EMI reduction can be achieved by limiting the rise and fall times of the FET with an additional external

resistor on the GD pin.

The boost gate driver is powered directly from VDD voltage or from the charge pump which multiplies V_DD

voltage by 2. If the charge pump is disabled, the VDD and CPUMP pins must be tied together.

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BOOST_INIT_VOLTAGE[5:0]

BOOST_SEL_LLC[1:0]

OCP

BOOST_SEL_I[1:0]

BOOST_SEL_P[1:0]

FB

LIGHT

LOAD

OVP

R

BOOST_GD_VOLT

BLANK TIME

R

S

R

RC Filter

GD

-

G_M

R

+

GATE DRIVER

BOOST_DRIVER_SIZE[1:0]

BOOST_SEL_JITTER_FILTER[1:0]

BOOST_EN_SPREAD_SPECTRUM

BOOST_FREQ_SEL[2:0]

CURRENT SENSE

BOOST OSCILLATOR

CURRENT RAMP

GENERATOR

OFF/BLANK TIME

PULSE GENERATOR

ISENSE

G_M

ꢀ

MUX

ISENCE_GND

SYNC

BOOST_EXT_CLK_SEL

BOOST_IMAX_SEL[2:0]

BOOST_SEL_IRAMP[1:0]

BOOST_EN_IRAMP_SU_DELAY

BOOST_BLANKTIME_SEL[1:0]

BOOST_OFFTIME_SEL[1:0]

Figure 21. Boost Converter Topology

8.3.7 Charge Pump

The boost switch FET gate driver is powered typically from VDD voltage. When the VDD voltage is not high

enough to drive the boost FET gate, the charge pump can be used to increase gate-driver voltage.

The charge pump effectively doubles the VDD voltage for gate driver. Maximum DC output current is 50 mA.

Boost driver voltage selection bit BOOST_GD_VOLT must be set to 1 before enabling the charge pump. If VDD

voltage is 5 V, the charge pump is not typically needed. In this case, a flying capacitor is not necessary, and the

charge pump output CPUMP pin must be connected to the VDD input pin.

GATE DRIVER

CP_2X_EN

CP_2X_CLK[1:0]

SQW_PULSE_GEN_EN

CPUMP

CP_2X_FAULT

CHARGE PUMP

SQW

VDD

C1P

C1N

Figure 22. Charge Pump

Table 14. Charge Pump Clock Frequency

CP_2X_CLK

FREQUENCY (kHz)

00

01

10

11

104

208

417

833

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Square-waveform (SQW) output provides a 100-kHz square wave signal (1 mA max) with amplitude equal to the

charge pump output voltage. When the charge pump is disabled, amplitude of this voltage is equal to VDD. This

signal can be used to generate low-current voltage rails; for example, a gate-reference voltage for output

protective FET (Figure 61) or for using nMOSFET as power-line FET (Figure 25). Figure 23 and Figure 24 show

examples of possible connections.

C1P

C1N

GD

SD

VSENSE_N

VSENSE_P

ISENSE

SQW

V_RAIL

~10V

5V

VDD

CPUMP

LP8860

Figure 23. V_RAILMultiplied by 2

C1P

C1N

GD

SD

VSENSE_N

VSENSE_P

ISENSE

3.3V

V_RAIL

~13.2V

VDD

SQW

CPUMP

LP8860

~6.6V

Figure 24. V_RAILMultiplied by 4

R_ISENSE

Q2

Up to 40V

L1

D1

C

2x

C

IN

Q1

C1N

C1P

GD

SD

VSENSE_N

VSENSE_P

ISENSE

R_SENSE

ISENSE_GND

FB

VDD

CPUMP

LP8860

SQW

Figure 25. Using nFET for Power-Line Control

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8.3.8 Powerline Control FET

The power-line FET limits peak current from the power line during start-up and allows the boost and LED strings

to be disconnected during a fault condition, when device is in fault recovery state.

The power-line control block has VSENSE_P and VSENSE_N pins for sensing input current and a shutdown SD

pin for driving the gate of the power-line FET. The power-line FET is opened when the LP8860-Q1 is enabled by

VDDIO/EN signal and V_INis greater than V_GSin steady state (when pFET is used as a power-line FET). A power-

line pFET must be chosen with minimal V_GSin steady state. Gate current is defined by the

<PL_SD_SINK_LEVEL[1:0]> EEPROM bits.

R_ISENSE

VIN

C_IN

tV_GS

t

I_G

SD

PL_SD_SINK_LEVEL[1:0]

NMOS_PLFET_EN

VSENSE_N

VSENSE_P

Figure 26. Power-line FET Control

During a shutdown state the LP8860-Q1 closes the power-line FET and prevents possible boost and LED

leakage. Sense pins are used to detect overcurrent. Power-line FET is closed when an OCP fault occurs. A VIN

OCP is indicated with PL_FET_FAULT bit. The power-line FET closes with all faults, followed by entering to a

recovery state.

When it is not possible to choose a pFET with the necessary characteristics, a schematic with nFET can be used

(see Charge Pump section, Figure 25); the <NMOS_PLFET_EN EEPROM> bit must be set accordingly. In this

case the SD pin provides current to shut down the power-line nFET during fault condition.

8.3.9 Protection and Fault Detection Modes

The LP8860-Q1 has fault detection for LED outputs, low and high input voltage, power line overcurrent, boost

overcurrent, boost overvoltage, and charge pump overload. In addition, the device has thermal shutdown and

LED overtemperature protection with an external NTC thermistor.

Faults have dedicated fault flags in registers <FAULT> and <LED_FAULT>. Mask bits can be used to disable

certain faults (see Table 17 for details). In addition the open-drain output pin FAULT can be used to indicate

occurred fault. Writing CLEAR_FAULTS or setting the NSS pin (I²C interface mode only) high resets the fault.

Setting the VDDIO/EN pin low, then high again, resets the faults as well.

8.3.9.1 LED Fault Comparators and Adaptive Boost Control

Every LED current sink has 3 comparators for adaptive boost control and fault detection. Each comparator

outputs is filtered. Filter control bits <BL_COMP_FILTER_SEL [3:0]> select how many PWM generator clock

cycles (5 MHz if PLL disabled or PLL clock) high/mid comparator is filtered before it is used to detect shorted

LEDs and boost voltage down-scaling. Usually

1 µs is sufficient; for 5-MHz frequency it means

<BL_COMP_FILTER_SEL [3:0]> = 0000b, 10 MHz = 0001b, 20 MHz = 0010b, and 40 MHz = 0011b.

Adaptive boost-control function adjusts the boost output voltage to the minimum sufficient voltage for proper LED

current sink operation. The output with the highest V_FLED string is detected and the boost output voltage

adjusted accordingly. Current sink headroom can be adjusted with EEPROM bits <DRV_HEADR[2:0]>. Boost

adaptive control voltage step size is 125 mV. Boost adaptive control operates similarly with and without PSPWM.

Additionally, when faster boost response is needed in larger brightness steps, the "jump" command can be used.

Jump allows increase of the boost voltage with greater steps. Jump is enabled with the <EN_JUMP> EEPROM

bit. The threshold for the magnitude of brightness increase that requires use of jump can be set with the

<JUMP_STEP_SIZE[1:0]> EEPROM bits. <BRIGHTNESS_JUMP_THRES[1:0]> EEPROM bits define when the

jump command is activated.

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V_BOOST

Driver

headroom

V_BOOST

Figure 27. Boost Voltage Adaptation

OUT#

DRV_LED_FAULT_THR[1:0]

HIGH_COMP

DRV_LED_COMP_HYST[1:0]

MID_COMP

DRV_HEADR[2:0]

LOW_COMP

DAC

Figure 28. Output Voltage Comparators

Figure 29 shows different cases which cause boost voltage increase, decrease, or generate faults.

Boost

decreases

voltage

Short LED fault (at least

one output should be

between LOW_COMP

and MID_COMP)

Boost

increases

voltage

Open LED fault

when

V_BOOST=MAX

No actions

Boost up level

reached for 1

output only

Boost down

level

reached

All outputs are

above boost up

level

Open LED

fault

Short LED

fault

HIGH_COMP

MID_COMP

LOW_COMP

Figure 29. Protection and Boost Adaptation Algorithms

NOTE

In the Cluster mode, if voltage of one or more outputs is below LOW_COMP, it causes

open LED fault detection.

8.3.9.2 LED Current Dimming With Internal Temperature Sensor

The LP8860-Q1 can prevent thermal shutdown (TSD) by reducing the average LED strings current based on die

temperature.

When die temperature reaches <INT_TEMP_LIM[1:0]> EEPROM bits-defined threshold, the device automatically

lowers the brightness (2.25% / ºC typical). Depending on brightness control mode either PWM duty cycle or

current is used for average current reduction.

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100%

50%

TSD

160

150

90

100

110

120

130

140

TEMPERATURE (°C)

Figure 30. Thermal De-Rating Function

Example With 100% and 50% Brightness

Table 15. Thermal De-rating Function Temperature

Thresholds

INT_TEMP_LIM[1:0]

TEMPERATURE

disabled

90ºC

00

01

10

11

100ºC

110ºC

Table 16. Temperature ADC Output for Different Temperatures

DECIMAL OUTPUT VALUE OF TEMP[10:0] REGISTER

TEMPERATURE (°C)

VDD 3.6 (V)

885

VDD 5 (V)

891

–40

–35

–30

–25

–20

–15

-10

-5

901

907

916

923

932

939

948

954

964

970

980

986

994

1002

1018

1034

1050

1066

1082

1098

1115

1131

1147

1163

1180

1196

1212

1229

0

1010

1026

1041

1057

1073

1089

1105

1121

1137

1154

1170

1186

1202

1219

5

10

15

20

25

30

35

40

45

50

55

60

65

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Table 16. Temperature ADC Output for Different Temperatures (continued)

DECIMAL OUTPUT VALUE OF TEMP[10:0] REGISTER

TEMPERATURE (°C)

VDD 3.6 (V)

1235

VDD 5 (V)

1245

70

75

1252

1262

80

1268

1278

85

1285

1293

90

1301

1310

95

1318

1328

100

105

110

1332

1343

1349

1359

1365

1375

8.3.9.3 LED Current Limitation With External NTC Sensor

The <EXT_TEMP_COMP_EN> EEPROM bit enables the LED current limitation mode. The principle of current

limitation is shown in Figure 31.

When LED temperature reaches <EXT_TEMP_LEVEL_LOW[3:0]> level, the device automatically tries to reduce

LED average current step-by-step by 3.125% from maximum brightness value. Step time is defined by

<EXT_TEMP_PERIOD[4:0]> EEPROM bits. If temperature continues to increase and reaches

<EXT_TEMP_LEVEL_HIGH[3:0]> level, the device shuts down the LEDs and generates a fault condition. The

LEDs are turned on automatically when the temperature is below the <EXT_TEMP_LEVEL_LOW[3:0]> level.

Otherwise, if after one or more steps the temperature drops down below <EXT_TEMP_LEVEL_LOW[3:0]>,

brightness increases with the same step time until it reaches the original level. The LP8860-Q1 uses PWM duty

reduction to reduce LED current. The device detects external NTC resistor availability, and the

<TEMP_RES_MISSING> flag is set, if the NTC sensor is missing (resistance is 2 MΩ or more).

PWM

HIGH LEVEL

Temperature

LOW LEVEL

TIME

Figure 31. LED Current Limitation With NTC

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TEMPERATURE

EXT_TEMP_LEVEL_LOW[3:0]

EXT_TEMP_FLAG_L

FAULT PIN

READ STATUS REGISTER

(EXT_TEMP_FLAG_L and

EXT_TEMP_FLAG_H bits)

WRITE CLEAR FAULTS

Figure 32. Timing Diagram for LED Current Limitation With NTC

8.3.9.4 LED Current Dimming With External NTC Sensor

When an external resistor for maximum current control is used, current dimming for LED current can be used

also. In this case LED current can be de-rated when ambient temperature is high. This option must be enabled

by <EXT_TEMP_I_DIMMING_EN> and <EXT_TEMP_COMP_EN> EEPROM bits.

Knee point and slope are defined by <EXT_TEMP_MINUS[1:0]> and <EXT_TEMP_GAIN[3:0]> EEPROM bits

respectively. LED shutdown temperature is defined by <EXT_TEMP_LEVEL_HIGH[3:0]> bits. Serial and parallel

resistors R1 and R2 affect the slope and knee point and can be used for the thermal curve adjustment and NTC

linearization.

100%

Knee Point

High Temperature Comparator Level

EXT_TEMP_LEVEL_HIGH[3:0]

I₁

I₂

AMBIENT TEMPERATURE T₁

T₂

Figure 33. Current Dimming for High Ambient Temperature

R₁

R₂

R_T

NTC

Figure 34. NTC Linearization

Figure 35 and Figure 36 show the block diagrams for current dimming.

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I

Tsense BLOCK

I_SET

CURRENT

MULTIPLIER

CURRENT

TSENSE

SUBTRACTOR

T°

ISET

EXTERNAL

CURRENT

SETTING

LIMIT

OUT

LED

CURRENT

SINKS

EXT_TEMP_GAIN[3:0]

TSENSE

OFFSET CURRENT

Tsense

BLOCK

EXT_TEMP_MINUS[1:0]

I

I_LED

I_TEMP

I_SET- I_TEMP

T°

Figure 35. Temperature-Dependent NTC Current

(Subtracted from ISET Current)

Figure 36. NTC Current Processing —

Scaling, Shift, and Limitation

Current dimming by external NTC sensor for 150-mA scale can be defined by formulas:

V_BG

I_SET

=

ì1000

50ìR_ISET

(6)

»

…

ÿ

Ÿ

≈

∆

’

÷

V_BG

R2ìR_NTC

R2 + R_NTC

ì1000 + 3.57mA

R1+

∆

÷

«

◊

I_TEMP

=

- EXT_TEMP_MINUS[1:0]

EXT_TEMP_GAIN[3:0]

Ÿ

⁄

(7)

I_TEMPcannot be negative; if I_TEMP< 0, then I_TEMPmust be 0.

I_LED= (I_SET– I_TEMP) × 150 mA

I_LEDcannot go below a 5-mA level; if calculated I_LED< 5 mA, then I_LED= 5 mA.

where

•

I_SET: Maximum current setting with external resistor R_ISET, µA

I_TEMP: Temperature compensation, µA

R_ISET: External resistor, kΩ

R1, R2: Resistors for adjustment, kΩ

I_LED: Output current per channel, mA

EXT_TEMP_MINUS[1:0]: 1, 5, 9, 13 µA

EXT_TEMP_GAIN[[3:0]: 50/n, n = 16 to 1

V_BG: 1.2 V

(8)

8.3.9.5 Protection Feature and Fault Summary

Table 17 summarizes protection features and related faults.

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Fault detection is digitally filtered — filtering time for different faults is shown in Table 18.

Table 18. Fault Filters

FAULT/PROTECTON

Boost Overcurrent Protection

Boost Overvoltage Protection

Input Overvoltage Protection

Input Undervoltage Protection

Input Overcurrent Protection

VDD Undervoltage Protection

Thermal Shutdown

FAULT NAME

BOOST_OCP

BOOST_OVP

VIN_OVP

TIME

110 ms

100 µs

5 µs

ENABLED

From boost start

In normal mode

From soft start

Always

VIN_UVLO

PL_FET_FAULT

VDD_UVLO

TSD

100 µs

10 µs

From soft start

From boost start

In normal mode

Charge Pump fault

CP_2X_FAULT

EXT_TEMP_FLAG_H

EXT_TEMP_FLAG_L

TEMP_RES_FAULT

Thermal LED Current Limit with

external NTC sensor.

10 µs

NTC missing

100 µs

OVP Threshold

VIN

FB

OVP Threshold

V

SD

t_softstart

tt_RECOVERY= 100 mst

VIN_OVP

FLAG

FAULT PIN

WRITE

CLEAR_FAULTS

Figure 37. Input OVP Triggering and Recovery

UVLO

Threshold

VIN

FB

UVLO

Threshold

V

SD

tt_RECOVERY= 100 mst

t_softstart

VIN_UVLO

FLAG

tt_RECOVERY= 100 mst

FAULT PIN

WRITE

CLEAR_FAULTS

Figure 38. Input UVLO Triggering and Recovery

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PL_SD_LEVEL[1:0]

I

IN

FB

V

SD

tt_RECOVERY= 100 mst

t_softstart

tt_RECOVERY= 100 mst

PL_FET_FAULT

FLAG

FAULT PIN

WRITE

CLEAR_FAULTS

Figure 39. Input OVP Triggering and Recovery

OVERLOAD CONDITION

OVERLOAD REMOVED

t_FILTER= 110 ms

VDDIO/EN

t_FILTER= 110 ms

t_RECOVERY= 100 ms

t_FILTER= 110 ms

t_RECOVERY= 100 ms

t_FILTER= 110 ms

t_RECOVERY= 100 ms

V

œ 5 V

BOOST SET

FB

V

SD

tt_shutdown

t

tt_softstart

t

BOOST_OCP

FLAG

FAULT PIN

WRITE

CLEAR_FAULTS

Figure 40. Boost OCP Triggering and Recovery

V

+1.6 V

BOOST SET

FB

BOOST SET

GD

BOOST_OVP

FLAG

FAULT PIN

WRITE

CLEAR_FAULTS

Figure 41. Boost OVP Triggering and Recovery

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8.4 Device Functional Modes

8.4.1 Standby Mode

The device is in standby mode when the EN/VDDIO pin is low. Current consumption from the VDD pin in this

mode is typically 1 µA.

8.4.2 Active Mode

The EN/VDDIO pin enables the logic and analog blocks. The device goes through the start-up sequence where

EEPROM context is loaded to the registers, the power-line FET is enabled during soft start, and boost starts

during boost start-time. In this mode I²C and SPI communication are available after soft start, and register

settings can be changed.

8.4.3 Fault Recovery State

Fault recovery state is special state which can be caused by faults. In this state power line FET is switched off,

boost and LED current sinks are disabled. I²C or SPI interfaces are available in this state — for example, fault

flags can be read.

POR=1

STANDBY

EEPROM:

SOFT_START_SEL[1:0]

00=5 ms

VDDIO/EN=1

01=10 ms

10=20 ms

11=50 ms

EEPROM READ

~300 ꢀs

FAULTS

100 ms

SOFT START

5...50 ms

FAULT RECOVERY

BOOST START

50 ms

FAULTS or

BOOST_OCP

VDDIO/EN=0

NORMAL

FAULTS or

FAULTS:

BOOST_OCP

- PL_FET_FAULT

- VIN_UVLO

- VIN_OVP

VDDIO/EN=0

- TSD

- CP_2X_FAULT

SHUTDOWN

VDD_UVLO=1

Figure 42. State Diagram

8.4.4 Start-Up and Shutdown Sequences

Depending on EEPROM settings the LP8860-Q1 can be started up or shut down differently. Typical start-

up/shutdown sequence is shown in Figure 43.

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Device Functional Modes (continued)

t>0

t>500 ꢀs

VIN

VDD

VDDIO/EN

PL pFET Drain

Headroom Adaptation

V_OUT= V_INLevel œ Diode Drop

VBOOST

PWM OUT

I_Q

Active Mode

tSOFTt

tSTARTt

tBOOSTt

tSTARTt

Figure 43. Timing Diagram for the Typical Start-Up and Shutdown

8.5 Programming

8.5.1 EEPROM

EEPROM memory stores various parameters for chip control. The 200-bit EEPROM memory is organized as 25

× 8 bits. The EEPROM structure consists of a register front-end and the non-volatile memory (NVM). Register

data can be read and written through the I²C/SPI serial interface. EEPROM must be burned with the new data;

otherwise, data disappears after power-on reset or VDDIO/EN cycling. PWM outputs and PLL must be disabled

when writing to EEPROM registers or burning EEPROM (<DISP_CL1_BRT[15:0]> = 0, <CL2_BRT[12:0]> = 0,

<CL3_BRT[12:0]> = 0, <CL2_BRT[12:0]> = 0, <EN_PLL> = 0). To read and program EEPROM NVM separate

commands need to be sent. Erase and program voltages are generated internally; no other voltages other than

the normal VDD voltage is required. A complete EEPROM memory map is shown in the Table 23.

The user must make sure that VDD power is on, and the VDDIO/EN pin is kept high, during the whole

programming/burn sequence to avoid memory corruption.

EE_PROG = 1

EEPROM

REGISTERS

Address 60h...78h

EEPROM

NVM

25 x 8 bits

Startup or

EE_READ=1

User

Device Control

REGISTERS

ADDRESS 00h...1Ah

Device Control

Figure 44. EEPROM and Register Configuration

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Programming (continued)

EEPROM has protection against accidental writes. EEPROM access can be unlocked by writing a pass code to

the EEPROM_UNLOCK register. It unlocks the EEPROM Control register EEPROM_CNTRL and all EEPROM

registers. Lock is enabled again by writing any other code to the EEPROM_UNLOCK register (for example, 0x00

enables the lock any time).

Table 19. EEPROM Pass Code Protection

PASS CODE TO EEPROM_UNLOCK REGISTER

0x08, 0xBA, 0xEF

EEPROM is used as fixed product-configuration storage, to be set or programmed during production before

normal operation. EEPROM can be reprogrammed for evaluation purposes up to 1000 cycles. Data-retention

lifetime for factory-programmed content is 10 years, minimum. For more details regarding EEPROM options, see

TI Application Note Selecting the Correct LP8860-Q1 EEPROM Version (SNVA757).

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8.5.2 Serial Interface

The LP8860-Q1 supports 2 different interface modes:

•

SPI interface (4-wire serial)

I²C-compatible (2-wire serial)

The user can define the interface mode by IF pin as shown in Table 20. The LP8860-Q1 detects interface mode

selection during start-up. When the device is in normal mode, the IF signal does not affect the interface selection.

Table 20. Interface Modes

IF PIN

GND

INTERFACE

I²C

VDDIO

SPI

8.5.2.1 SPI Interface

The LP8860-Q1 is compatible with SPI serial-bus specification, and it operates as a slave. The transmission

consists of 16-bit write and read cycles. One cycle consists of 7 address bits, 1 read/write (R/W) bit, and 8 data

bits. The R/W bit high state defines a write cycle and low defines a read cycle. MISO output is normally in a high-

impedance state. When the slave select NSS for LP8680 is active (that is, low), MISO output is pulled low for

both read and write operations, except for the period when Data is sent out during a read cycle. The Address

and Data are transmitted MSB first. The Slave Select signal NSS must be low during the Cycle transmission.

NSS resets the interface when high, and it has to be taken high between successive cycles. Data is clocked in

on the rising edge of the SCLK clock signal, while data is clocked out on the falling edge of SCLK.

NSS

SCLK

1

R/W

MOSI

MISO

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

Hi-Z

Figure 45. SPI Write Cycle

NSS

SCLK

MOSI

MISO

R/W

0

A6

A5

A4

A3

A2

A1

A0

tDon't Caret

D4 D3

Hi-Z

D7

D6

D5

D2

D1

D0

Figure 46. SPI Read Cycle

8.5.2.2 I²C Serial Bus Interface

8.5.2.2.1 Interface Bus Overview

The I²C-compatible synchronous serial interface provides access to the programmable functions and registers on

the device. This protocol is using a two-wire interface for bi-directional communications between the devices

connected to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL).

These lines must be connected to a positive supply through a pullup resistor and remain HIGH even when the

bus is idle.

Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on

whether it generates or receives the SCL. The LP8860-Q1 is always a slave device.

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8.5.2.2.2 Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the SCL.

Consequently, throughout the clock high period, the data must remain stable. Any changes on the SDA line

during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New data must

be sent during the low SCL state. This protocol permits a single data line to transfer both command/control

information and data using the synchronous serial clock.

SDA

SCL

Data Line

Stable:

Data Valid

Change

of Data

Allowed

Figure 47. Bit Transfer

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a

Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is

transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following

sections provide further details of this process.

Data Output

by

Transmitter Stays Off the

Bus During the

Transmitter

Acknowledgment Clock

Data Output

by

Receiver

Acknowledgment

Signal From Receiver

SCL

3 - 6

1

2

7

8

9

S

Start

Condition

Figure 48. Start and Stop

The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start

Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop

Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a

Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition.

SDA

SCL

S

P

Start

Stop

Condition

Figure 49. Stop and Start Conditions

In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction.

This allows another device to be accessed, or a register read cycle.

8.5.2.2.3 Acknowledge Cycle

The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte

transferred, and the acknowledge signal sent by the receiving device.

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The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter

releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver

must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the

high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to

receive the next byte.

8.5.2.2.4 Acknowledge After Every Byte Rule

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge

signal after every byte received.

There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must

indicate to the transmitter an end of data by not-acknowledging (negative acknowledge”) the last byte clocked out

of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),

but the SDA line is not pulled down.

8.5.2.2.5 Addressing Transfer Formats

Each device on the bus has a unique slave address. The LP8860-Q1 operates as a slave device with 7-bit

address combined with data direction bit. Default slave address is 2Dh as 7-bit or 5Ah for write and 5Bh for read

in 8-bit format.

Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device

sends an acknowledge signal on the SDA line, once it recognizes its address. The slave address is the first

seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the slave

address — the eighth bit. When the slave address is sent, each device in the system compares this slave

address with its own. If there is a match, the device considers itself addressed and sends an acknowledge

signal. Depending upon the state of the R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.

MSB

LSB

ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 R/W

Bit7

x

bit6

bit5

x

bit4

x

bit3

x

bit2

x

bit1

x

bit0

x

2

I C SLAVE address (chip address)

Figure 50. Address and Read/Write Bit

8.5.2.2.6 Control Register Write Cycle

1. Master device generates start condition.

2. Master device sends slave address (7 bits) and the data direction bit (r/w = “0”).

3. Slave device sends acknowledge signal if the slave address is correct.

4. Master sends control register address (8 bits).

5. Slave sends acknowledge signal.

6. Master sends data byte to be written to the address register.

7. Slave sends acknowledgement.

8. Write cycle ends when the master creates stop condition.

8.5.2.2.7 Control Register Read Cycle

1. Master device generates start condition.

2. Master device sends slave address (7 bits) and the data direction bit (r/w = “0”).

3. Slave device sends acknowledge signal if the slave address is correct.

4. Master sends control register address (8 bits).

5. Slave sends acknowledge signal if slave address is correct.

6. Master generates repeated start condition

7. Master sends the slave address (7 bits) and the data direction bit (r/w = “1”)

8. Slave sends acknowledgment if the slave address is correct.

9. Read cycle ends when master does not generate acknowledge signal after data byte and generates stop

condition.

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Table 21. Data Read and Write Cycles

MODE

Data Read

ACTION⁽¹⁾

<Slave Address><r/w = ‘0’>[Ack]

<Register Addr.>[Ack]

<Slave Address><r/w = ‘1’>[Ack]

[Register Data]<Ack or Nack>

register address possible

Data Write

<Slave Address><r/w=’0’>[Ack]

<Register Addr.>[Ack]

<Register Data>[Ack]

register address possible

(1) <> Data from master; [] Data from slave

Slave Address

(7 bits)

Control Register Add.

Register Data

(8 bits)

S

'0'

A

P

(8 bits)

Data transfered,

byte + Ack

R/W

From Slave to Master

From Master to Slave

A - ACKNOWLEDGE (SDA Low)

S - START CONDITION

P - STOP CONDITION

Register Write Format

Figure 51. Register Write Format

Slave Address

(7 bits)

Slave Address

(7 bits)

Data- Data

(8 bits)

Control Register Add.

(8 bits)

A/

P

S

'0'

A

Sr

'1'

A

NA

Data transfered, byte +

Ack/NAck

R/W

Direction of the transfer will

change at this point

From Slave to Master

From Master to Slave

A

- ACKNOWLEDGE (SDA Low)

NA - ACKNOWLEDGE (SDA High)

- START CONDITION

Sr - REPEATED START CONDITION

- STOP CONDITION

S

P

Register Read Format

Figure 52. Register Read Format

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Table 23. EEPROM Register Map⁽¹⁾

ADDR

0x60

REGISTER

D7

D6

D5

DRV_LED_BIAS_CTRL[1:0]

LED_CURRENT_CTRL[7:0]

EN_ADVANCED_

D4

D3

D2

D1

D0

EEPROM REG 0

EEPROM REG 1

EXT_TEMP_MINUS[1:0]

LED_CURRENT_CTRL[11:8]

0x61

EN_STEADY_

DITHER

0x62

0x63

EEPROM REG 2

EEPROM REG 3

RESERVED

PWM_INPUT_HYSTERESIS[1:0]

PWM_SLOPE[2:0]

SLOPE

EN_DISPAY_LED_

FAULT

DRV_LED_CURRENT_SCALE[2:0]

LED_STRING_CONF[2:0]

EN-PWM_I

EN_CL_LED_

FAULT

0x64

0x65

0x66

EEPROM REG 4

EEPROM REG 5

EEPROM REG 6

DRV_LED_COMP_HYST[1:0]

I_SLOPE[2:0]

DRV_LED_FAULT_THR[1:0]

PWM_RESOLUTION[1:0]

DRV_HEADR[2:0]

DITHER[2:0]

DRV_EN_EXT_

LED_CUR_CTR

DRV_EN_SPLI

T_FET

RESERVED

GAIN_CTRL[2:0]

BRT_MODE[1:0]

0x67

0x68

0x69

EEPROM REG 7

EEPROM REG 8

EEPROM REG 9

DRV_OUT2_CORR[3:0]

DRV_OUT4_CORR[3:0]

EXT_TEMP_GAIN[3:0]

NMOS_PLFET_

DRV_OUT1_CORR[3:0]

DRV_OUT3_CORR[3:0]

BL_COMP_FILTER_SEL[3:0]

EEPROM REG

10

EXT_TEMP_I_

DIMMING_EN

0x6A

0x6B

SOFT_START_SEL[1:0]

PL_SD_LEVEL[1:0]

PL_SD_SINK_LEVEL[1:0]

EN

EEPROM REG

11

SLOW_PLL_DIV[12:5]

PWM_

COUNTER_

RESET

EEPROM REG

12

0x6C

EN_SYNC

PWM_SYNC

SLOW_PLL_DIV[4:0]

EEPROM REG

13

0x6D

0x6E

0x6F

R_SELL[1:0]

SEL_DIVIDER

EN_PLL

SYNC_PRE_DIVIDER[3:0]

PWM_FREQ[3:0]

EEPROM REG

14

RESERVED

SYNC_TYPE

EEPROM REG

15

MASK_BOOST_

OVP_FSM

MASK_BOOST_

OCP_FSM

MASK_OVP_

FSM

MASK_VIN_

UVLO

UVLO_LEVEL[1:0]

OVP_LEVEL[1:0]

BOOST_EN_

IRAMP _SU_

DELAY

EEPROM REG

16

BOOST_EXT_

CLK_SEL

BOOST_GD_

VOLT

0x70

0x71

RESERVED

BOOST_IMAX_SEL[2:0]

BOOST_EN_

SPREAD_

SPECTRUM

EEPROM REG

17

BOOST_SEL_IND[1:0]

BOOST_SEL_IRAMP[1:0]

BOOST_FREQ_SEL[2:0]

EEPROM REG

18

0x72

0x73

0x74

0x75

0x76

0x77

0x78

BOOST_DRIVER_SIZE[1:0]

RESERVED

EN_ADAP

EN_JUMP

BRIGHTNESS_JUMP_THRES[1:0]

BOOST_INITIAL_VOLTAGE[5:0]

BOOST_SEL_I[1:0]

JUMP_STEP_SIZE[1:0]

EEPROM REG

19

EEPROM REG

20

BOOST_SEL_JITTER_FILTER[1:0

]

BOOST_SEL_LLC[1:0]

BOOST_OFFTIME_SEL[1:0]

BOOST_SEL_P[1:0]

BOOST_VO_SLOPE_CTRL[2:0]

SQW_PULSE_

EEPROM REG

21

BOOST_BLANKTIME_SEL[1:0]

RESERVED

CP_2X_CLK[1:0]

EXT_TEMP_LEVEL_LOW[3:0]

EEPROM REG

22

VDD_UVLO_LEVE

CP_2X_EN

L

GEN_EN

EEPROM REG

23

EXT_TEMP_LEVEL_HIGH[3:0]

INT_TEMP_LIM[1:0]

EEPROM REG

24

EXT_TEMP_

COMP_EN

EXT_TEMP_PERIOD[4:0]

(1) Unused bits data must not be changed.

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8.6.1 Register Bit Explanations

8.6.1.1 Display/Cluster1 Brightness Control MSB

Address 0x00

Reset value 0000 0000b

DISP_CL1_BRT MSB

7

6

5

4

3

2

1

0

DISP_CL1_BRT[15:8]

Name

DISP_CL1_BRT[15:8]

Bit

Access Description

7:0

R/W

Backlight brightness control MSB

8.6.1.2 Display/Cluster1 Brightness Control LSB

Address 0x01

Reset value 0000 0000b

DISP_CL1_BRT LSB

7

6

5

4

3

2

1

0

DISP_CL1_BRT[7:0]

Name

DISP_CL1_BRT LSB

Bit

Access Description

7:0

R/W

Backlight brightness control LSB

The DISP_CL1_BRT MSB register must be written first. New value is valid after writing DISP_CL1_BRT LSB. If

output 1 is used in display mode, the Brightness/Cluster Output 1 Brightness Control register is used for all

outputs in display mode (16-bits register). Otherwise it is the Brightness Control register for cluster output 1. For

cluster bit control is 13 bit, most significant bit are used.

8.6.1.3 Display/Cluster1 Output Current MSB

Address 0x02

Reset value loaded during start-up from EEPROM REG0

DISP_CL1_CURRENT MSB

7

6

5

4

3

2

1

0

RESERVED

DISP_CL1_CURRENT[11:8]

Name

DISP_CL1_CURRENT[11:8]

Bit

Access

Description

Display/Cluster current control MSB

3:0

R/W

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8.6.1.4 Display/Cluster1 Output Current LSB

Address 0x03

Reset value loaded during start-up from EEPROM REG1

DISP_CL1_CURRENT LSB

7

6

5

4

3

2

1

0

DISP_CL1_CURRENT[7:0]

Name

DISP_CL1_CURRENT[7:0]

Bit

Access Description

R/W Display/Cluster current control LSB

7:0

The DISP_CL1_CURRENT MSB register must be written first. New value is valid after writing

DISP_CL1_CURRENT LSB. If one of few outputs is used in display mode, the DISP_CL1_CURRENT register is

used for all outputs in display mode (12-bit), otherwise it is Cluster1 Output Current register.

Maximum current is defined by DRV_LED_CURRENT_SCALE[2:0] bits.

8.6.1.5 Cluster2 Brightness Control MSB

Address 0x04

Reset value 0000 0000b

CL2_BRT MSB

7

6

5

4

3

2

1

0

RESERVED

CL2_BRT[12:8]

Name

CL2_BRT[12:8]

Bit

Access Description

R/W Cluster output 2 brightness control MSB

4:0

8.6.1.6 Cluster2 Brightness Control LSB

Address 0x05

Reset value 0000 0000b

CL2_BRT LSB

7

6

5

4

3

2

1

0

CL2_BRT[7:0]

Name

CL2_BRT[7:0]

Bit

Access Description

R/W Cluster output 2 brightness control LSB

7:0

The CL2_BRT MSB register must be written first. New value is valid after writing CL2_BRT LSB.

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8.6.1.7 Cluster2 Output Current

Address 0x06

Reset value 0000 0000b

CL2_CURRENT

7

6

5

4

3

2

1

0

CL2_CURRENT[7:0]

Name

CL2_CURRENT[7:0]

Bit

Access Description

R/W Cluster output 2 current control

7:0

Maximum current is defined by DRV_LED_CURRENT_SCALE[2:0] bits.

8.6.1.8 Cluster3 Brightness Control MSB

Address 0x07

Reset value 0000 0000b

CL3_BRT MSB

7

6

5

4

3

2

1

0

RESERVED

CL3_BRT[12:8]

Name

CL3_BRT[12:8]

Bit

Access Description

R/W Cluster output 3 brightness control MSB

4:0

8.6.1.9 Cluster3 Brightness Control LSB

Address 0x08

Reset value 0000 0000b

CL3_BRT LSB

7

6

5

4

3

2

1

0

CL3_BRT[7:0]

Name

CL3_BRT[7:0]

Bit

Access Description

R/W Cluster output 3 brightness control LSB

7:0

The CL3_BRT MSB register must be written first. New value is valid after writing CL3_BRT LSB.

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8.6.1.10 Cluster3 Output Current

Address 0x09

Reset value 0000 0000b

CL3_CURRENT

7

6

5

4

3

2

1

0

CL3_CURRENT[7:0]

Name

CL3_CURRENT[7:0]

Bit

Access Description

R/W Cluster output 3 current control

7:0

Maximum current is defined by DRV_LED_CURRENT_SCALE[2:0] bits.

8.6.1.11 Cluster4 Brightness Control MSB

Address 0x0A

Reset value 0000 0000b

CL4_BRT MSB

7

6

5

4

3

2

1

0

RESERVED

CL4_BRT[12:8]

Name

CL4_BRT[12:8]

Bit

Access Description

R/W Cluster output 4 brightness control MSB

4:0

8.6.1.12 Cluster4 Brightness Control LSB

Address 0x0B

Reset value 0000 0000b

CL4_BRT LSB

7

6

5

4

3

2

1

0

CL4_BRT[7:0]

Name

CL4_BRT[7:0]

Bit

Access Description

R/W Cluster output 4 brightness control LSB

7:0

The CL4_BRT MSB register must be written first. New value is valid after writing CL4_BRT LSB.

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8.6.1.13 Cluster4 Output Current

Address 0x0C

Reset value 0000 0000b

CL4_CURRENT

7

6

5

4

3

2

1

0

CL4_CURRENT[7:0]

Name

CL4_CURRENT[7:0]

Bit

Access Description

R/W Cluster output 4 current control

7:0

Maximum current is defined by DRV_LED_CURRENT_SCALE[2:0] bits.

8.6.1.14 Configuration

Address 0x0D

Reset value loaded during start-up from EEPROM

CONFIGURATION

7

6

5

4

3

2

1

0

RESERVED

DRV_LED_CURRENT_SCALE[2:0]

EN_ADVANCED

_SLOPE

PWM_SLOPE[2:0]

Name

Bit

Access

Description

DRV_LED_CURRENT_SCALE[2:0]

6:4

R/W

Scales the maximum LED current when EN_EXT_LED_CUR_CTRL = 0

Effective for display and cluster mode.

000 = 25 mA

001 = 30 mA

010 = 50 mA

011 = 60 mA

100 = 80 mA

101 = 100 mA

110 = 120 mA

111 = 150 mA

EN_ADVANCED_SLOPE

PWM_SLOPE[2:0]

3

R/W

Enable for advanced slope (smooth brightness change)

0 = Linear slope used only

1 = Advanced slope used

2:0

Linear brightness sloping time (typical)

000 = 0 ms

001 = 1 ms

010 = 2 ms

011 = 52 ms

100 = 105 ms

101 = 210 ms

110 = 315 ms

111 = 511 ms

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8.6.1.15 Status

Address 0x0E

Reset value 0000 0000b

STATUS

7

6

5

4

3

2

1

0

RESERVED

BRT_SLOPE_DONE

TEMP_RES_MISSING

EXT_TEMP_FLAG_L

EXT_TEMP_FLAG_H

Name

Bit

Access Description

BRT_SLOPE_DONE

TEMP_RES_MISSING

EXT_TEMP_FLAG_L

EXT_TEMP_FLAG_H

3

R

Status bit for the brightness sloping

0 = Sloping ongoing

1 = Sloping done

2

1

0

NTC sensor missing flag

0 = sensor OK

1 = NTC sensor missing

External temperature sensor low limit exceeded flag

0 = limit not detected

1 = low temperature limit detected

External temperature sensor high limit exceeded flaf

0 = limit not detected

1 = high temperature limit detected

8.6.1.16 Fault

Address 0x0F

Reset value 0000 0000b

STATUS

7

6

5

4

3

2

1

0

RESERVED

VIN_OVP

VIN_UVLO

TSD

BOOST_OCP

BOOST_OVP

PL_FET_FAULT CP_2X_FAULT

Name

Bit

Access Description

VIN_OVP

6

R

VIN overvoltage protection flag

0 = No fault

1 = Fault detected

VIN_UVLO

TSD

5

4

3

2

1

0

VIN undervoltage lockout flag

0 = No fault

1 = Fault detected

Thermal shutdown

0 = No flag

1 = Fault detected

BOOST_OCP

BOOST_OVP

PL_FET_FAULT

CP_2X_FAULT

Boost overcurrent protection flag

0 = No flag

1 = Fault detected

Boost output overvoltage protection flag

0 = No flag

1 = Fault detected

VIN overcurrent protection flag

0 = No fault

1 = Fault detected

Charge pump output voltage too low

0 = No fault

1 = Fault detected

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8.6.1.17 LED Fault

Address 0x10

Reset value 0000 0000b

LED FAULT

7

6

5

4

3

2

1

0

RESERVED

OPEN_LED

SHORT_LED

LED_FAULT[4:1]

Name

Bit

Access Description

OPEN_LED

5

R

Open LED fault.

0 = No fault

1 = Fault detected

SHORT_LED

4

Short LED fault.

0 = No fault

1 = Fault detected

LED_FAULT[4:1]

3:0

Defines which string has either open or short fault.

0001 = LED OUT1

0010 = LED OUT2

0100 = LED OUT3

1000 = LED OUT4

8.6.1.18 Fault Clear

Address 0x11

Reset value 0000 0000b

FAULT CLEAR

7

6

5

4

3

2

1

0

RESERVED

CLEAR_FAULTS

Name

CLEAR_FAULTS

Bit

Access Description

W Write only bit, writing CLEAR_FAULTS high clears faults.

0

8.6.1.19 Identification

Address 0x12

ID

7

6

5

4

3

2

1

0

FULL_LAYER_REVISION[3:0]

METAL REVISIONS[3:0]

Name

Bit

7:4

3:0

Access Description

FULL_LAYER_REVISION

METAL REVISIONS

R

Manufacturer ID code – full layer revision

Manufacturer ID code – metal mask revision

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8.6.1.20 Temp MSB

Address 0x13

TEMP MSB

7

6

5

4

3

2

1

0

RESERVED

TEMP[10:8]

Name

TEMP[10:8]

Bit

Access Description

2:0

R

Device internal temperature sensor reading, first 3 MSB. MSB must be read before LSB,

because reading of MSB register latches the data.

8.6.1.21 Temp LSB

Address 0x14

TEMP LSB

7

6

5

4

3

2

1

0

TEMP[7:0]

Name

TEMP[7:0]

Bit

Access Description

7:0

R

Device internal temperature sensor reading, last 8 LSB. MSB must be read before LSB,

because reading of MSB register latches the data.

8.6.1.22 Display LED Current MSB

Address 0x15

DISP LED CURRENT MSB

7

6

5

4

3

2

1

0

RESERVED

LED_CURRENT[11:8]

Name

LED_CURRENT[11:8]

Bit

Access Description

3:0

R

Display LED current value reading, first 3 MSB. DISP LED CURRENT MSB must be

read before DISP LED CURRENT LSB, DISP LED PWM MSB, and DISP LED PWM

LSB because reading of the MSB register latches the data for current and PWM.

8.6.1.23 Display LED Current LSB

Address 0x16

DISP LED CURRENT LSB

7

6

5

4

3

2

1

0

LED_CURRENT[7:0]

Name

LED_CURRENT[7:0]

Bit

Access Description

Display LED current value reading, last 8 LSB.

Note: DISP LED CURRENT MSB latches the data for current and PWM.

7:0

R

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8.6.1.24 Display LED PWM MSB

Address 0x17

Reset value 0000 0000b

DISP LED PWM MSB

7

6

5

4

3

2

1

0

PWM[15:8]

Name

PWM[7:0]

Bit

Access Description

R Display LED current value reading, first 8 MSB.

Note: DISP LED CURRENT MSB latches the data for current and PWM.

7:0

8.6.1.25 Display LED PWM LSB

Address 0x18

Reset value 0000 0000b

DISP LED PWM LSB

7

6

5

4

3

2

1

0

PWM[7:0]

Name

PWM[7:0]

Bit

Access Description

R Display LED PWM reading, last 8 LSB.

Note: DISP LED CURRENT MSB latches the data for current and PWM.

7:0

8.6.1.26 EEPROM Control

Address 0x19

Reset value 1000 0000b

EEPROM CTRL

7

6

5

4

3

2

1

0

EE_READY

RESERVED

EE_PROG

EE_READ

Name

Bit

Access Description

EE_READY

7

R

EEPROM ready

0 = EEPROM programming or read in progress

1 = EEPROM ready, not busy

EE_PROG

1

0

R/W

EEPROM programming

0 = Normal operation

1 = Start the EEPROM programming sequence. Programs data currently in the

EEPROM registers to non-volatile memory (NVM).

EE_READ

R/W

EEPROM read

0 = Normal operation

1 = Reads the data from NVM to the EEPROM registers. Can be used to restore

default values if EEPROM registers are changed during testing.

Programming sequence (program data permanently from registers to NVM):

1. Turn on the chip by setting VDDIO/EN pin high.

2. Unlock EEPROM by writing the unlock codes to register 0x1A.

–

Write 0x08 to address 0x1A

Write 0xBA to address 0x1A

Write 0xEF to address 0x1A

3. Write data to EEPROM registers (address 0x60…0x78).

4. Write EE_PROG to high in address 0x19. (0x02 to address 0x19).

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5. Wait 200 ms.

6. Write EE_PROG to low in address 0x19. (0x00 to address 0x19).

Read sequence (load data from NVM to registers):

1. Turn on the chip by writing setting VDDIO/EN pin high.

2. Unlock EEPROM by writing the unlock codes to register 0x1A.

–

Write 0x08 to address 0x1A

Write 0xBA to address 0x1A

Write 0xEF to address 0x1A

3. Write EE_READ to high in address 0x19. (0x01 to address 0x19).

4. Wait 1 ms.

5. Write EE_READ to low in address 0x19. (0x00 to address 0x19).

NOTE

EEPROM bits are intended to be set/programmed before normal operation only once

during silicon production, but can be reprogrammed for evaluation purposes up to 1000

cycles.

8.6.1.27 EEPROM Unlock Code

Address 0x1A

Reset value 0000 0000b

EEPROM UNLOCK

7

6

5

4

3

2

1

0

EEPROM UNLOCK_CODE[7:0]

Name

EEPROM_UNLOCK_CODE[7:0]

Bit

Access

Description

7:0

W

Unlock EEPROM control register (0x19) and EEPROM registers.

Writing 0x08, 0xBA, 0xEF sequence unlocks EEPROM registers.

Lock is enabled again by writing any other code to the register.

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8.6.2 EEPROM Bit Explanations

8.6.2.1 EEPROM Register 0

Address 0x60

EEPROM REGISTER 0

7

6

5

4

3

2

1

0

EXT_TEMP_MINUS[1:0]

DRV_LED_BIAS_CTRL[1:0]

LED_CURRENT_CTRL[11:8]

Name

Bit

Access Description

EXT_TEMP_MINUS[1:0]

7:6

R/W

External temperature sensor current dimming knee point, see LED Current Dimming

With Internal Temperature Sensor for details.

00 = 1 μA

01 = 5 μA

10 = 9 μA

11 = 13 μA

DRV_LED_BIAS_CTRL[1:0]

LED_CURRENT_CTRL[11:8]

5:4

3:0

R/W

Controls the LED current sink bias current. Effects LED current sink rise time and

current consumption. 150-mA LED current is suggested.

00 = slowest LED current sink setting and low Iq (typical 800-ns rise time / 200 μA

per sink)

01 = slow (typical 400-ns rise time / 400 μA per sink)

10 = fast (typical 200-ns rise time / 800 μA per sink)

11 = fastest LED current sink and higher current consumption (typical100-ns rise

time / 1.6 mA per sink)

R/W

MSB bits for 12-bit LED current control. Step size is 150 mA / 4095 = 36.63 µA

(typical) when max current is set to 150 mA. Max current can be scaled with R_ISET

resistor or with DRV_LED_CURRENT_SCALE EEPROM bits.

000h = 0 mA

001h = 0.037 mA

002h = 0.073 mA

003h = 0.110 mA

…

FFEh = 149.963 mA

FFFh = 150.000 mA

8.6.2.2 EEPROM Register 1

Address 0x61

EEPROM REGISTER 1

7

6

5

4

3

2

1

0

LED_CURRENT_CTRL[7:0]

Name

LED_CURRENT_CTRL[7:0]

Bit

7:0

Access Description

R/W

LSB bits for 12-bit LED current control. Step size is 150 mA / 4095 = 36.63 µA when

max current is set to 150 mA. Max current can be scaled with R_ISETresistor or with

DRV_LED_CURRENT_SCALE EEPROM bits.

000h = 0 mA

001h = 0.037 mA

002h = 0.073 mA

003h = 0.110 mA

…

FFEh = 149.963 mA

FFFh = 150.000 mA

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8.6.2.3 EEPROM Register 2

Address 0x62

EEPROM REGISTER 2

7

6

5

4

3

2

1

0

RESERVED

EN_STEADY_DITHER

PWM_INPUT_HYSTERESIS[1:0]

EN_ADVANCED_SLOPE

PWM_SLOPE[2:0]

Name

Bit

Access Description

EN_STEADY_DITHER

6

R/W

Enable dithering in steady state condition

0 = Disabled, dithering used in sloping (brightness changes) only

1 = Enabled, dithering used in sloping as well as steady-state condition. Dithering

defined with DITHER[2:0] bits.

PWM_INPUT_HYSTERESIS[1:0]

5:4

PWM input hysteresis function. Defines how small changes in the PWM input are

ignored. Hysteresis used to remove constant switching between two values.

00 = ±1-step hysteresis with 16-bit resolution

01 = ±8-step hysteresis with 16-bit resolution

10 = ±16-step hysteresis with 16-bit resolution

11 = ±256-step hysteresis with 16-bit resolution

EN_ADVANCED_SLOPE

PWM_SLOPE[2:0]

3

R/W

Advanced smooth slope for brightness changes

0 = Advanced slope is disabled

1 = Use advanced slope for brightness change to make brightness changes

smooth for eye

2:0

Linear brightness sloping time (typical)

000 = Slope function disabled, immediate brightness change

001 = 1 ms

010 = 2 ms

011 = 52 ms

100 = 105 ms

101 = 210 ms

110 = 315 ms

111 = 511 ms

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8.6.2.4 EEPROM Register 3

Address 0x63

EEPROM REGISTER 3

7

6

5

4

3

2

1

0

EN_DISPLAY_LED_FAULT

DRV_LED_CURRENT_SCALE[2:0]

LED_STRING_CONF[2:0]

EN_PWM_I

Name

Bit

Access Description

EN_DISPLAY_LED_FAULT

7

R/W

0 = LED open/short faults disabled

1 = LED open/short faults enabled

DRV_LED_CURRENT_SCALE[2:0]

6:4

R/W

Scales the maximum LED current when EN_EXT_LED_CUR_CTRL = 0

Effective for both modes – display and cluster.

000 = 25 mA

001 = 30 mA

010 = 50 mA

011 = 60 mA

100 = 80 mA

101 = 100 mA

110 = 120 mA

111 = 150 mA

LED_STRING_CONF[2:0]

3:1

R/W

LED current sink configuration

000 = 4 separate LED strings with 90° phase shift

001 = 3 separate LED strings with 120° phase shift (String 4 in cluster mode or

not used)

010 = 2 separate LED strings with 180° phase shift (Strings 3 and 4 in cluster

mode or not used)

011 = 1 LED string. (Strings 2,3 and 4 in cluster mode or not used)

100 = 2 LED strings (1+2, 3+4) with 180° phase shift. Tied strings with same

phase.

101 = 1 LED string (1+2+3+4). Tied strings with same phase

110 = 1 LED string (1+2). 1st and 2nd strings tied with same phase, strings 3

and 4 are in cluster mode or not used

111 = All strings are used in cluster mode

EN_PWM_I

0

R/W

Enable Hybrid PWM and Current dimming mode

0 = Disabled, dimming only with PWM

1 = Enabled

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8.6.2.5 EEPROM Register 4

Address 0x64

EEPROM REGISTER 4

7

6

5

4

3

2

1

0

EN_CL_LED_FAULT

DRV_LED_COMP_HYST[1:0]

DRV_LED_FAULT_THR[1:0]

DRV_HEADER[2:0]

Name

Bit

Access

Description

EN_CL_LED_FAULT

7

R/W

Enable open/short LED fault for cluster strings

0 = LED fault in cluster mode disabled

1 = LED fault in cluster mode enabled

DRV_LED_COMP_HYST[1:0]

6:5

R/W

LED comparator hysteresis – difference between mid and low

comparator, used for boost adaptive voltage control (boost high

level)

00 = 1000 mV

01 = 750 mV

10 = 500 mV

11 = 250 mV

DRV_LED_FAULT_THR[1:0]

DRV_HEADER[2:0]

4:3

2:0

R/W

LED Fault thresholds, used for short LED detection.

00 = 3.6 V

01 = 3.6 V

10 = 6.9 V

11 = 10.6 V

LED current sink headroom control, used for boost adaptive voltage

control (boost low level) and open LED detection.

V_SATis the saturation voltage of the sink, typically 500 mV with 150-

mA current.

111 = V_SAT+ 50 mV

110 = V_SAT+ 175 mV

101 = V_SAT+ 300 mV

100 = V_SAT+ 450 mV

011 = V_SAT+ 575 mV

010 = V_SAT+ 700 mV

001 = V_SAT+ 875 mV

000 = V_SAT+ 1000 mV

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8.6.2.6 EEPROM Register 5

Address 0x65

EEPROM REGISTER 5

7

6

5

4

3

2

1

0

I_SLOPE[2:0]

PWM_RESOLUTION[1:0]

DITHER[2:0]

Name

Bit

Access

Description

I_SLOPE[2:0]

7:5

R/W

Slope gain adjusts the current slope for Hybrid PWM and Current

dimming mode

000 = 1.000

001 = 1.023

010 = 1.047

011 = 1.070

100 = 1.094

101 = 1.117

110 = 1.141

111 = 1.164

PWM_RESOLUTION[1:0]

4:3

2:0

R/W

For PWM clocking with internal oscillator (VSYNC is not used) these

bits control the PLL multiplier and hence the PWM output resolution

00 = 5-MHz clock used for generating PWM

01 = 10-MHz clock used for generating PWM

10 = 20-MHz clock used for generating PWM

11 = 40-MHz clock used for generating PWM

DITHER[2:0]

Dither function controls

000 = Dither function disabled

001 = 1-bit dither

010 = 2-bit dither

011 = 3-bit dither

1XX = 4-bit dither

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8.6.2.7 EEPROM Register 6

Address 0x66

EEPROM Register 6

7

6

5

4

3

2

1

0

RESERVED

GAIN_CTRL[2:0]

EN_EXT_LED_CUR_CTRL

DRV_EN_SPLIT_FET

BRT_MODE[1:0]

Name

Bit

Access

Description

GAIN_CTRL[2:0]

6:4

R/W

Switch point from PWM to current control for Hybrid PWM and

Current dimming mode

000 = 50.0%

001 = 40.6%

010 = 31.3%

011 = 25.0%

100 = 21.9%

101 = 18.8%

110 = 15.6%

111 = 12.5%

EN_EXT_LED_CUR_CTRL

DRV_EN_SPLIT_FET

3

2

R/W

Enable LED current set resistor

0 = Resistor is disabled and current is scaled with SCALE[2:0]

EEPROM register bits

1 = Enable LED current set resistor. LED current is scaled by the

R_ISETresistor

LED current sink FET control

0 = big size FET is driving LED current

1 = enable use of smaller FET for driving low LED output currents.

Smaller FET is selected automatically when current setting is below

1/16 of the scale. Automatic scaling improves accuracy for output

currents below 1/16 of the full current scale.

BRT_MODE[1:0]

1:0

R/W

Brightness control mode

00 = PWM input pin duty cycle control

01 = PWM input duty x Brightness register

10 = Brightness register

11 = Direct PWM control from PWM input pin

8.6.2.8 EEPROM Register 7

Address 0x67

EEPROM Register 7

7

6

5

4

3

2

1

0

DRV_OUT2_CORR[3:0]

DRV_OUT1_CORR[3:0]

Name

DRV_OUT2_CORR[3:0]

Bit

Access

Description

7:4

R/W

Current correction for OUT2 LED current sink

0000 = 6.5%

0001 = 5.6%

0010 = 4.7%

0011 = 3.7%

0100 = 2.8%

0101 = 1.9%

0110 = 0.9%

0111 = 0.0%

1000 = –0.9%

1001 = –1.9%

1010 = –2.8%

1011 = –3.7%

1100 = –4.7%

1101 = –5.6%

1110 = –6.5%

1111 = –7.4%

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Name

Bit

Access

Description

DRV_OUT1_CORR[3:0]

3:0

R/W

Current correction for OUT1 LED current sink

0000 = 6.5%

0001 = 5.6%

0010 = 4.7%

0011 = 3.7%

0100 = 2.8%

0101 = 1.9%

0110 = 0.9%

0111 = 0.0%

1000 = –0.9%

1001 = –1.9%

1010 = –2.8%

1011 = –3.7%

1100 = –4.7%

1101 = –5.6%

1110 = –6.5%

1111 = –7.4%

8.6.2.9 EEPROM Register 8

Address 0x68

EEPROM Register 8

7

6

5

4

3

2

1

0

DRV_OUT4_CORR[3:0]

DRV_OUT3_CORR[3:0]

Name

DRV_OUT4_CORR[3:0]

Bit

Access

Description

7:4

R/W

Current correction for OUT4 LED current sink

0000 = 6.5%

0001 = 5.6%

0010 = 4.7%

0011 = 3.7%

0100 = 2.8%

0101 = 1.9%

0110 = 0.9%

0111 = 0.0%

1000 = –0.9%

1001 = –1.9%

1010 = –2.8%

1011 = –3.7%

1100 = –4.7%

1101 = –5.6%

1110 = –6.5%

1111 = –7.4%

DRV_OUT3_CORR[3:0]

3:0

R/W

Current correction for OUT3 LED current sink

0000 = 6.5%

0001 = 5.6%

0010 = 4.7%

0011 = 3.7%

0100 = 2.8%

0101 = 1.9%

0110 = 0.9%

0111 = 0.0%

1000 = –0.9%

1001 = –1.9%

1010 = –2.8%

1011 = –3.7%

1100 = –4.7%

1101 = –5.6%

1110 = –6.5%

1111 = –7.4%

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8.6.2.10 EEPROM Register 9

Address 0x69

EEPROM Register 8

7

6

5

4

3

2

1

0

EXT_TEMP_GAIN[3:0]

BL_COMP_FILTER_SEL[3:0]

Name

Bit

Access

Description

EXT_TEMP_GAIN[3:0]

7:4

R/W

External temperature sensor current dimming gain control, see LED

Current Dimming With Internal Temperature Sensor for details.

BL_COMP_FILTER_SEL[3:0]

3:0

R/W

Filter selects how many PWM generator clock cycles high/mid

comparator is filtered before it is used to detect shorted LEDs and

boost voltage down scaling.

0000 = 5

0001 = 10

0010 = 20

0011 = 40

0100 = 60

0101 = 80

0110 = 100

0111 = 140

1000 = 180

1001 = 220

1010 = 260

1011 = 300

1100 = 340

1101 = 380

1110 = 420

1111 = 460

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8.6.2.11 EEPROM Register 10

Address 0x6A

EEPROM Register 9

7

6

5

4

3

2

1

0

EXT_TEMP_I_DIMMING_

EN

NMOS_PLFET_EN

SOFT_START_SEL[1:0]

PL_SD_LEVEL[1:0]

PL_SD_SINK_LEVEL[1:0]

Name

Bit

Access

Description

EXT_TEMP_I_DIMMING_EN

7

R/W

External temperature sensor current dimming enabled

0 = disabled

1 = enabled

NMOS_PLFET_EN

6

Powerline FET selection:

0 = pFET

1 = nFET

SOFT_START_SEL[1:0]

5:4

Soft-start time selection

00 = 5 ms

01 = 10 ms

10 = 20 ms

11 = 50 ms

PL_SD_LEVEL[1:0]

3:2

1:0

R/W

Power-line FET current limit selection VIN OCP (assumed R_ISENSE= 20 mΩ).

10 = 6 A

11 = 8 A

PL_SD_SINK_LEVEL[1:0]

Power-line FET gate current

NMOS_PLFET_EN = 0

NMOS_PLFET_EN = 1

(current for normal mode) (current for fault recovery mode,

otherwise 0mA)

00

01

10

11

55 µA

110 µA

220 µA

440 µA

0.3 mA

0.5 mA

1.0 mA

2.2 mA

8.6.2.12 EEPROM Register 11

Address 0x6B

EEPROM Register 11

7

6

5

4

3

2

1

0

SLOW_PLL_DIV[12:5]

Name

SLOW_PLL_DIV[12:5]

Bit

Access

Description

Divider for VSYNC operation. 8 MSB bits

7:0

R/W

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8.6.2.13 EEPROM Register 12

Address 0x6C

EEPROM Register 12

7

6

5

4

3

2

1

0

EN_SYNC

PWM_SYNC

PWM_COUNTER_RESET

SLOW_PLL_DIV[4:0]

Name

Bit

Access

Description

EN_SYNC

7

R/W

VSYNC input enable

0 = VSYNC input disabled

1 = VSYNC input enabled

PWM_SYNC

6

R/W

Enable PWM generation synchronization to VSYNC signal

0 = Disabled

1 = Enabled. PWM output used for phase detector input after

dividing with SLOW_PLL_DIV divider

PWM_COUNTER_RESET

SLOW_PLL_DIV[4:0]

5

R/W

Enable PWM generator resetting on VSYNC signal rising edge

0 = Disabled

1 = Enabled

4:0

Divider for VSYNC operation. 5 LSB bits

8.6.2.14 EEPROM Register 13

Address 0x6D

EEPROM Register 13

7

6

5

4

3

2

1

0

R_SEL[1:0]

SEL_DIVIDER

EN_PLL

SYNC_PRE_DIVIDER[3:0]

Name

Bit

Access

Description

R_SEL[1:0]

7:6

R/W

Coefficient for the slow PLL divider

00 = 16

01 = 32

10 = 64

11 = 128

SEL_DIVIDER

EN_PLL

5

4

R/W

PLL divider selection

0 = Slow PLL divider with external compensation (when using

VSYNC)

1 = Fast PLL divider with internal compensation (when using 5-MHz

internal clock)

PLL enable

0 = PLL disabled and internal 5-MHz oscillator used for PWM

generation

1 = PLL is used for generating the PWM generation clock from the

internal oscillator or VSYNC signal

SYNC_PRE_DIVIDER[3:0]

3:0

VSYNC signal pre-divider from 1 to 16. Used when VSYNC

frequency is higher than PWM output frequency.

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8.6.2.15 EEPROM Register 14

Address 0x6E

EEPROM Register 14

7

6

5

4

3

2

1

0

RESERVED

SYNC_TYPE

PWM_FREQ[3:0]

Name

SYNC_TYPE

Bit

Access

Description

4

R/W

Type of the VSYNC input. Affects the PLL functionality.

0 = HSYNC (50 to 150 kHz)

1 = VSYNC (50 to 150 Hz)

PWM_FREQ[3:0]

3:0

R/W

PWM output frequency setting when internal oscillator is used. See

Brightness Control (Display Mode)

8.6.2.16 EEPROM Register 15

Address 0x6F

EEPROM Register 13

7

6

5

4

3

2

1

0

MASK_BOOST_OVP_ MASK_BOOST_OCP

STATUS _FSM

MASK_OVP_FSM

MASK_VIN_UVLO

UVLO_LEVEL[1:0]

OVP_LEVEL[1:0]

Name

Bit

Access

Description

MASK_BOOST_OVP_STATUS

7

R/W

Boost overvoltage protection enable

0 = Enabled

1 = Fault bit and FAULT pin disabled.

MASK_BOOST_OCP_FSM

6

5

R/W

Boost overcurrent protection fault recovery state enable

0 = Enabled

1 = Entering fault recovery state disabled. Fault bit and FAULT pin

operate normally.

MASK_OVP_FSM

MASK_VIN_UVLO

UVLO_LEVEL[1:0]

VIN overvoltage fault recovery state enable

0 = Enabled

1 = Entering fault recovery state disabled. Fault bit and FAULT pin

operate normally.

4

VIN undervoltage lockout fault recovery state enable

0 = Enabled

1 = Entering fault recovery state disabled. Fault bit and FAULT pin

operate normally.

3:2

VIN Undervoltage protection thresholds (UVLO)

00 = disabled

01 = 3 V

10 = 5 V

11 = 8 V

OVP_LEVEL[1:0]

1:0

R/W

VIN Overvoltage protection thresholds (OVP)

00 = disabled

01 = 7 V

10 = 11 V

11 = 22.5 V

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8.6.2.17 EEPROM Register 16

Address 0x70

EEPROM Register 16

7

6

5

4

3

2

1

0

RESERVED

BOOST_EN_IRAMP_DELAY BOOST_EXT_CLK_SEL

BOOST_IMAX_SEL[2:0]

BOOST_GD_VOLT

Name

Bit

Access

Description

BOOST_EN_IRAMP_DELAY

BOOST_EXT_CLK_SEL

5

R/W

Boost current ramp delay enable (for adjusting conversion

ratio/stability, 35% of period)

1 = Delay enabled

0 = Delay disabled

4

R/W

Boost clock selection

0 = Internal clock

1 = External clock (SYNC pin)

If external clock selected and sync disappears for 1.5…2 periods,

boost automatically switches to using internal oscillator with

frequency defined by BOOST_FREQ_SEL[2:0]

BOOST_IMAX_SEL[2:0]

3:1

Maximum current limit for boost SW mode. Values below based on

25-mΩ sense resistor value.

000 = 2 A

001 = 3 A

010 = 4 A

011 = 5 A

100 = 6 A

101 = 7 A

110 = 8 A

111 = 9 A

BOOST_GD_VOLT

0

R/W

Boost gate driver voltage selection

1 = Charge pump output (V_{GATE DRIVER}> 6 V)

0 = VDD

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8.6.2.18 EEPROM Register 17

Address 0x71

EEPROM Register 17

7

6

5

4

3

2

1

0

BOOST_EN_SPREAD_

SPECTRUM

BOOST_SEL_IND[1:0]

BOOST_SEL_IRAMP[1:0]

BOOST_FREQ_SEL[2:0]

Name

Bit

Access

Description

BOOST_EN_SPREAD_

SPECTRUM

7

R/W

Boost spread spectrum (±3% from central frequency, 1.875 kHz modulation

frequency) enable

0 = Spread spectrum disabled

1 = Spread spectrum enabled

BOOST_SEL_IND[1:0]

6:5

4:3

R/W

See BOOST_SEL_IRAMP for selecting BOOST_SEL_IND setting

Boost artificial current ramp peak value, A/s.

BOOST_SEL_IRAMP[1:0]

Select value higher than I_{RAMP_GAIN}

:

I_{RAMP_GAIN}=1.2 x 0.5 x (VOUT_max- VIN_min)/(0.7 x L x 60000), where VIN, VOUT are

boost input and output voltage, L - inductance, H. 25-mΩ R_SENSEis suggested.

BOOST_SEL_IND[1:0]

BOOST_SEL_IRAMP

[1:0]

00

01

10

11

00

130

88

65

43

28

18

34

23

15

10

29

20

13

8.5

01

10

56

11

37

BOOST_FREQ_SEL[2:0]

2:0

R/W

BOOST_EXT_CLK_SEL=0

Boost output frequency selection (internal oscillator)

000= 100 kHz

001 = 200 kHz

010 = 303 kHz

011 = 400 kHz

100 = 629 kHz

101 = 800 kHz

110 = 1100 kHz

111 = 2200 kHz

BOOST_EXT_CLK_SEL=1

Boost output frequency selection (for external sync mode if external sync

disappears)

000= 100 kHz

001 = 200 kHz

010 = 303 kHz

011 = 400 kHz

100 = 625 kHz

101 = 833 kHz

110 = 1111 kHz

111 = 2500 kHz

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8.6.2.19 EEPROM Register 18

Address 0x72

EEPROM Register 16

7

6

5

4

3

2

1

0

BOOST_DRIVER_SIZE[1:0]

EN_ADAP

EN_JUMP

BRIGHTNESS_JUMP_THRES[1:0]

JUMP_STEP_SIZE[1:0]

Name

Bit

7:6

Access

Description

BOOST_DRIVER_SIZE[1:0]

R/W

Boost gate driver scaling. Affects gate driver peak current and SW

node voltage rise/fall times

00 = 0.4/0.45 A (typical) peak sink/source current

01 = 0.75/0.87 A (typical) peak sink/source current

10 = 1.2/1.3 A (typical) peak sink/source current

11 = 1.5/1.7 A (typical) peak sink/source current

EN_ADAP

5

R/W

Enable boost converter adaptive mode

0 = adaptive mode disabled, boost converter output voltage is set with

BOOST_INITIAL_VOLTAGE EEPROM register bits.

1 = adaptive mode enabled. Boost converter start-up voltage is set

with BOOST_INITIAL_VOLTAGE EEPROM register bits. Further boost

voltage is adapted to the highest LED string V_F.

If all LED outputs are in cluster mode, adaptive mode is disabled

automatically.

EN_JUMP

4

R/W

Enable large boost voltage jump command for the fast brightness

increase.

0 = Normal steps used for boost voltage control

1 = Jump command allowed in boost voltage control

BRIGHTNESS_JUMP_THRES[1:0]

3:2

Defines the magnitude of the input brightness change after which jump

command is given.

00 = Jump command after 10% brightness change

01 = Jump command after 30% brightness change

10 = Jump command after 50% brightness change

11 = Jump command after 70% brightness change

JUMP_STEP_SIZE[1:0]

1:0

R/W

Boost control step size that jump command increases backlight boost

output voltage

00: 8 steps (1.0 V typ)

01: 16 steps (2.0 V typ)

10: 32 steps (4.0 V typ)

11: 64 steps (8.0 V typ)

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8.6.2.20 EEPROM Register 19

Address 0x73

EEPROM Register 19

7

6

5

4

3

2

1

0

RESERVED

BOOST_INITIAL_VOLTAGE[5:0]

Name

Bit

Access

Description

BOOST_INITIAL_VOLTAGE[5:0]

5:0

R/W

Boost voltage control from 16 V to 47.5 V with 0.5 V step (without

FB resistive divider). When resistive divider is used on the FB pin,

the voltages are scaled accordingly. If adaptive boost control is

enabled, this sets the initial start voltage for the boost converter. If

adaptive mode is disabled, this sets the output voltage of the boost

converter.

000000 = 16.0 V (typical)

000001 = 16.5 V (typical)

000010 = 17.0 V (typical)

000011 = 17.5 V (typical)

000100 = 18.0 V (typical)

...

111100 = 46.0 V (typical)

111101 = 46.5 V (typical)

111110 = 47.0 V (typical)

111111 = 47.5 V (typical)

8.6.2.21 EEPROM Register 20

Address 0x74

EEPROM Register 20

7

6

5

4

3

2

1

0

BOOST_SEL_LLC[1:0]

BOOST_SEL_JITTER_FILTER[1:0]

BOOST_SEL_I[1:0]

BOOST_SEL_P[1:0]

Name

Bit

Access

Description

BOOST_SEL_LLC[1:0]

7:6

R/W

Light load comparator control. Selects boost PFM entry threshold

(compensator current)

00 = 5 μA (boost switches from PFM to PWM early at light loads)

01 = 10 μA

10 = 15 μA

11 = 20 μA (boost operates in PFM mode to higher loads)

BOOST_SEL_JITTER_FILTER[1:0]

BOOST_SEL_I[1:0]

5:4

3:2

1:0

R/W

Boost jitter filter selection

00 = bypass

01 = 300 kHz

10 = 60 kHz

11 = 30 kHz

Boost PI compensator control: integral part

00 = 1

01 = 2

10 = 3

11 = 4

BOOST_SEL_P[1:0]

Boost PI compensator control: proportional part

00 = 1

01 = 2

10 = 3

11 = 4

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8.6.2.22 EEPROM Register 21

Address 0x75

EEPROM Register 21

7

6

5

4

3

2

1

0

BOOST_OFFTIME_SEL[1:0]

BOOST_BLANKTIME_SEL[1:0]

RESERVED

BOOST_VO_SLOPE_CTRL[2:0]

Name

Bit

Access

Description

BOOST_OFFTIME_SEL[1:0]

7:6

R/W

Boost time off selection

00 = 131 ns

01 = 68 ns

10 = 38 ns

11 = 24 ns

BOOST_BLANKTIME_SEL[1:0]

BOOST_VO_SLOPE_CTRL[2:0]

5:4

2:0

R/W

Boost blank time selection

00 = 162 ns

01 = 88 ns

10 = 63 ns

11 = 40 ns

Sets the speed for boost output voltage scaling up or down

000 = 1 (every PWM cycle)

001 = 2 (every other PWM cycle)

010 = 3 (every third PWM cycle)

011 = 4 (every 4th PWM cycle)

100 = 5 (every 5th PWM cycle)

101 = 6 (every 6th PWM cycle)

110 = 8 (every 8th PWM cycle)

111 = 16 (every 16th PWM cycle)

8.6.2.23 EEPROM Register 22

Address 0x76

EEPROM Register 20

7

6

5

4

3

2

1

0

VDD_UVLO_

LEVEL

RESERVED

CP_2X_CLK[1:0]

CP_2X_EN

SQW_PULSE_

GEN_EN

Name

Bit

Access

Description

VDD_UVLO_LEVEL

7

R/W

VDD UVLO protection level

0 = 2.5 V

1 = 3.0 V

Voltage hysteresis typically 50 mV.

2.5V level can be used if PLL frequency up to 20 MHz. With higher

PLL frequency logic is not specified to work down to 2.5 V VDD

CP_2X_CLK[1:0]

3:2

R/W

Charge pump clock frequency

00 = 104 kHz

01 = 208 kHz

10 = 417 kHz

11 = 833 kHz

CP_2X_EN

1

0

R/W

Charge pump enable. CP is enabled at soft start if CP_2X_EN

EEPROM bit asserted.

0 = disabled

1 = enabled

SQW_PULSE_GEN_EN

External charge pump clock enable (50% duty cycle 100 kHz).

Clock connected to SQW pin. SQW clock enabled at soft start.

0 = disabled

1 = enabled

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8.6.2.24 EEPROM Register 23

Address 0x77

EEPROM Register 23

7

6

5

4

3

2

1

0

EXT_TEMP_LEVEL_HIGH[3:0]

EXT_TEMP_LEVEL_LOW[3:0]

Name

Bit

Access

Description

EXT_TEMP_LEVEL_HIGH[3:0]

7:4

R/W

High external temperature sensor limit, kΩ

0000 = 79.67

0001 = 43.35

0010 = 29.77

0011 = 22.67

0100 = 18.30

0101 = 15.34

0110 = 13.21

0111 = 11.60

1000 = 10.34

1001 = 9.32

1010 = 8.49

1011 = 7.79

1100 = 7.20

1101 = 6.69

1110 = 6.25

1111 = 5.87

EXT_TEMP_LEVEL_LOW[3:0]

3:0

R/W

Low external temperature sensor limit, kΩ

0000 = 79.67

0001 = 43.35

0010 = 29.77

0011 = 22.67

0100 = 18.30

0101 = 15.34

0110 = 13.21

0111 = 11.60

1000 = 10.34

1001 = 9.32

1010 = 8.49

1011 = 7.79

1100 = 7.20

1101 = 6.69

1110 = 6.25

1111 = 5.87

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8.6.2.25 EEPROM Register 24

Address 0x78

EEPROM Register 24

7

6

5

4

3

2

1

0

INT_TEMP_LIM[1:0]

EXT_TEMP_PERIOD[4:0]

EXT_TEMP_COMP_EN

Name

Bit

Access

Description

INT_TEMP_LIM[1:0]

7:6

R/W

Internal temperature sensor brightness thermal de-rating starting

level.

Thermal de-rating function temperature threshold:

00 = thermal de-rating function disabled

01 = 90°C

10 = 100°C

11 = 110°C

EXT_TEMP_PERIOD[4:0]

5:1

R/W

Step time for temperature limitation with external sensor

00000 = 2 s

00001 = 4 s

00010 = 6 s

00011 = 8 s

00100 = 10 s

00101 = 12 s

00110 = 14 s

00111 = 16 s

01000 = 18 s

01001 = 20 s

01010 = 22 s

01011 = 24 s

01100 = 26 s

01101 = 28 s

01110 = 30 s

01111 = 32 s

…

11110 = 62 s

11111 = 64 s

EXT_TEMP_COMP_EN

0

R/W

External temperature sensor (NTC) enable

0 = disabled

1 = enabled

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LP8860-Q1 is designed for automotive applications, and an input voltage V_INis intended to be connected to

the car battery. The device is internally powered from the VDD pin, and voltage must be in 3-V to 5.5-V range.

The device has flexible configurability; outputs configuration are defined by EEPROM settings. If the VDD voltage

is not high enough to drive an external nMOSFET gate, an internal charge pump must be used to power the gate

driver. The charge pump is configured by EEPROM.

The LP8860-Q1 can be used as a stand-alone device, using only the VDDIO/EN pin and the PWM signal.

Alternatively, the device can be a part of system, connected to a microprocessor by an SPI or I²C interface.

NOTE

Maximum operating voltage for V_INis 48 V; the boost converter can achieve output voltage

up to 48 V (typical) without external feedback divider in adaptive voltage control mode.

However, V_INmust be below output voltage, and the conversion ratio (max 10) must be

taken into account. If necessary, boost can provide higher output voltage with an external

resistive feedback voltage divider. For high output-voltage applications, outputs must be

protected by external components to prevent overvoltage.

9.2 Typical Applications

9.2.1 Typical Application for Display Backlight

Figure 53 shows the typical application for the LP8860-Q1 with factory-programmed settings. It supports 4 LED

strings in display mode with a 90° phase shift. Brightness control register is used for LED dimming by using

conventional PWM dimming method. VDD voltage is 5 V, charge pump is disabled, and boost switching

frequency is 303 kHz.

VIN

3...40 V

R

ISENSE

L

D

Up to 40 V

Q2

C

IN

C

OUT

Q1

C1P

C1N

SD

GD

VSENSE_N

VSENSE_P

ISENSE

VDD 5 V

C_VDD

R

VDD

SENSE

ISENSE_GND

FB

CPUMP

C_CPUMP

SQW

FILTER

LP8860-Q1

SYNC

OUT1

VSYNC

OUT2

OUT3

PWM

SCL

SDA

SCLK/SCL

MOSI/SDA

MISO

OUT4

FAULT RESET

EN

NSS

MCU/GPU

TSENSE

ISET

VDDIO/EN

IF

FAULT

SGND PGND LGND PAD

VDDIO

Figure 53. VDD = 5 V, I²C, 4 LED Outputs in Display Mode

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Typical Applications (continued)

9.2.1.1 Design Requirements

Table 24. EEPROM Setting Example

ADDRESS (HEX)

DATA (HEX)

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

ED

DF

DC

F0

DF

E5

F2

77

71

3F

B7

17

EF

B0

87

CE

72

E5

DF

35

06

DC

FF

3E

DESIGN PARAMETER

VIN voltage range

VALUE

3 V to 40 V

5 V

VDD voltage

Charge pump

Disabled

I²C

Brightness Control

Output configuration

LED string current

External current set resistor

Boost frequency

Inductor

Mode 1, OUT1 to OUT4 are in display mode (phase shift 90º)

130 mA

Disabled

303 kHz

22 μH to 33 μH, at least 9-A saturation current

Input/Output capacitors

R_ISENSE

10 μF ceramic and 33 μF electrolytic

20 mΩ

R_SENSE

25 mΩ

Current dimming with external NTC

Disabled

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9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Inductor Selection

There are two main considerations when choosing an inductor; the inductor must not saturate, and the inductor

current ripple must be small enough to achieve the desired output voltage ripple. Different saturation current

rating specifications are followed by different manufacturers so attention must be given to details. Saturation

current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of

application should be requested from the manufacturer. Shielded inductors radiate less noise and are preferable.

The saturation current must be greater than the sum of the maximum load current and the worst case average-

to-peak inductor current. The equation below shows the worst case conditions.

I_OUTMAX

I_SAT

>

+ I_RIPPLE

For Boost

D‘

V_IN

x

(V_OUT- V_IN)

(2 x L x f)

Where I_RIPPLE

=

V_OUT

(V_OUTœ V_IN)

and D‘ = (1 - D)

Where D =

(V_OUT

)

•

I_RIPPLE: peak inductor current

I_OUTMAX: maximum load current

V_IN: minimum input voltage in application

L: min inductor value including worst case tolerances

f: minimum switching frequency

V_OUT: output voltage

D: Duty Cycle for CCM Operation

V_OUT: Output Voltage

(9)

As a result the inductor must be selected according to the I_SAT. A more conservative and recommended

approach is to choose an inductor that has a saturation current rating greater than the maximum switch current

limit defined by <BOOST_IMAX_SEL[2:1]> EEPROM bits. A 22-µH to 33-µH inductor with a saturation current

rating of at least 9 A is recommended for most applications. The inductor resistance must be less than 300 mΩ

for good efficiency. See detailed information in Texas Instruments Application Note Understanding Boost Power

Stages in Switch Mode Power Supplies (SLVA061). “Power Stage Designer™ Tools” can be used for the boost

calculation: http://www.ti.com/tool/powerstage-designer.

9.2.1.2.2 Output Capacitor Selection

A ceramic capacitor with a 100-V voltage rating is recommended for the output capacitor. The DC-bias effect can

reduce the effective capacitance by up to 80%, a consideration for capacitance value selection. Effectively the

capacitance must be 33 µF for 600-mA loads. A different option is to use an aluminum electrolytic capacitor with

low ESR and ceramic capacitor in parallel. Typically a 33-µF (ESR < 500 mΩ) with 10-µF (effective) ceramic

capacitor in parallel is sufficient. If ESR is lower, capacitance for ceramic capacitor can be decreased.

For higher switching frequency (2.2 MHz) and boost output current below 400 mA, two 10-µF ceramic capacitors

in parallel are sufficient.

9.2.1.2.3 Input Capacitor Selection

A ceramic capacitor with 50-V voltage rating is recommended for the input capacitor. The DC-bias effect can

reduce the effective capacitance by up to 80%, a consideration for capacitance value selection. Effectively the

capacitance must be 33 µF for 600-mA loads. A different option is to use an aluminum electrolytic capacitor with

low ESR and ceramic capacitor in parallel. Typically a 33-µF (ESR < 500 mΩ) with 10-µF (effective) ceramic

capacitor in parallel is sufficient. If ESR is lower, capacitance for ceramic capacitor can be decreased.

For higher switching frequency (2.2 MHz) and boost output current below 400 mA two 10-µF ceramic capacitors

in parallel are sufficient.

9.2.1.2.4 Charge Pump Output Capacitor

A ceramic capacitor with at least 16-V voltage rating is recommended for the output capacitor of the charge

pump. The DC-bias effect can reduce the effective capacitance by up to 80%, which needs to be considered in

capacitance value selection. Typically a 10-µF capacitor is sufficient.

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9.2.1.2.5 Charge Pump Flying Capacitor

A ceramic capacitor with at least 10-V voltage rating is recommended for the flying capacitor of the charge pump.

Typically 1-µF capacitor is sufficient.

9.2.1.2.6 Diode

A Schottky diode must be used for the boost output diode. Peak repetitive current must be greater than inductor

peak current (up to 9 A) to ensure reliable operation. Average current rating must be greater than the maximum

output current. Schottky diodes with a low forward drop and fast switching speeds are ideal for increasing

efficiency. Choose a reverse breakdown voltage of the Schottky diode significantly larger than the output voltage.

Do not use ordinary rectifier diodes because slow switching speeds and long recovery times cause the efficiency

and the load regulation to suffer.

9.2.1.2.7 Boost Converter Transistor

An nFET transistor with high enough voltage rating (V_DSat least 5 V higher than maximum output voltage) must

be used. Current rating for the FET must be the same as the inductor peak current. Gate-drive voltage for the

FET is VDD or about 2 x VDD, if the charge pump is enabled (EEPROM selection).

9.2.1.2.8 Boost Sense Resistor

A high-power 25-mΩ resistor must be used for sensing the boost SW current. Power rating can be calculated

from the inductor current and sense resistor resistance value.

9.2.1.2.9 Power Line Transistor

A pFET transistor with necessary voltage rating (V_DSat least 5 V higher than max input voltage) must be used.

Current rating for the FET must be the same as input peak current or greater. Transfer characteristic is very

important for pFET. V_GSfor open transistor must be less then V_IN. A 20-kΩ resistor between the pFET gate and

source is sufficient.

If a pFET with high enough V_DSand low V_GSis not available, it is possible to use an nFET with extra external

components with the EEPROM bit NMOS_PLFET_EN set high. See Charge Pump section (Figure 25) for using

the nFET as a power-line FET.

9.2.1.2.10 Input Current Sense Resistor

A high-power 20-mΩ resistor must be used for sensing the boost input current. Power rating can be calculated

from the input current and sense resistor resistance value.

9.2.1.2.11 Filter Component Values

Table 25 shows recommended filter component values for the VSYNC PLL filter (phase margin 60°). An external

filter must be used only when external VSYNC is used; otherwise, the LP8860-Q1 uses internal compensation.

C1

FILTER

C2

R1

Figure 54. Filter Components

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Table 25. Filter Components Selection

V/H SYNC

PLL FREQUENCY (MHz)

C1

C2

R1

50 Hz

(BW3dB = 1 Hz)

5

100 nF

54 nF

27 nF

13.6 nF

10 nF

5 nF

1.4 μF

0.7 μF

0.35 μF

0.175 μF

129 nF

65 nF

85 kΩ

10

20

40

5

170 kΩ

338 kΩ

677 kΩ

14 kΩ

20 kHz

(BW3dB = 330 Hz)

10

20

40

5

28 kΩ

2.5 nF

1.2 nF

22 nF

12 nF

6.2 nF

3.1 nF

32 nF

56 kΩ

16 nF

112 kΩ

5.6 kΩ

11.2 kΩ

22.3 kΩ

44,7 kΩ

50 kHz

(BW3dB = 330 Hz)

322 nF

161 nF

80 nF

10

20

40

40 nF

9.2.1.2.11.1 Critical Components for Design

Schematic on Figure 55 shows the critical part of circuitry: boost components, the LP8860-Q1 internal charge

pump for gate driver powering and powering/grounding of LP8860-Q1 boost components. Layout example for

this is shown in Figure 67.

R1

L1

D1

+VBATT

Q1

C5

C3

C4

C8

1

2

R2

C9

Q2

C1P

C1N

32

R3

SD

30

28

5

6

GD

ISENSE

VSENSE_N

VSENSE_P

VDD 3.3V

C1

3

R4

R5

VDD

C6

27

26

31

ISENSE_GND

FB

CPUMP

C2

C7

4

SQW

9

FILTER

12

13

LP8860-Q1

25

SYNC

to LEDs

OUT1

VSYNC

24

22

OUT2

OUT3

18

16

15

14

to LEDs

PWM

SCLK/SCL

MOSI/SDA

MISO

21

OUT4

17

19

20

NSS

8

7

TSENSE

ISET

VDDIO/EN

IF

11

FAULT

SGND PGND LGND PAD

10 29 23

Figure 55. Critical Components for Design

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Table 26. Bill of Materials for Design Example

REFERENCE DESIGNATOR

DESCRIPTION

NOTE

Input current sensing resistor

Power-line FET gate pullup resistor

Gate resistor for boost FET

Current sensing filter resistor

Boost current sensing resistor

VDD bypass capacitor

R1

R2

R3

R4

R5

C1

C2

C3

C4

C5

C6

C7

C8

C9

L1

20 mΩ 3 W

20 kΩ 0.1 W

10 Ω 0.1 W

25 mΩ 3 W

1 μF 10 V ceramic capacitor

10 μF 16 V ceramic capacitor

33 μF 50 V electrolytic capacitor

10 μF 50 V ceramic capacitor

1 μF 10 V ceramic capacitor

1000 pF 10 V ceramic capacitor

39 pF 50 V ceramic capacitor

33 μF 50 V electrolytic capacitor

10 μF 100 V ceramic capacitor

22 μH saturation current 9 A

60 V 15 A Schottky diode

Charge pump output capacitor

Boost input capacitor

Flying capacitor

Current sensing filter capacitor

High frequency bypass capacitor

Boost output capacitor

Boost inductor

D1

Q1

Q2

Boost Schottky diode

60 V 10 A pMOSFET

Power-line FET

60 V 15 A nMOSFET

Boost nMOSFET

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9.2.1.3 Application Performance Plots

VDDIO/EN 5V/div

V_DPOWER-LINE pFET 10V/div

V_BOOST10 V/DIV

LED OUT 10 V/DIV

20ms/div

40µs/div

ƒ_SW= 303 kHz

C_IN= C_OUT= 33 µF(el) + 10 µF(cer)

130 mA/string

f_{LED_PWM}= 4.9 kHz

Phase shift 90º

4 strings

Figure 57. Typical Start-up

Figure 56. Voltage of LED Outputs Showing Phase-Shift

PWM Operation

BOOST CURRENT

100mA/DIV

BOOST CURRENT

100mA/DIV

BOOST VOLTAGE

1V/DIV

BOOST VOLTAGE

1V/DIV

OUT1 5V/DIV

40ms/DIV

EN_PWM_I = 1

PWM_SLOPE = 101

I_SLOPE =000

130 mA/string

PWM_SLOPE =

110

130 mA/string

Phase Shift = 90°

10 LED/string

GAIN_CTRL =

111

4 strings

EN_ADVANCED_SLOPE = 0

Phase Shift = 90°

EN_ADVANCED_SLOPE = 0

Figure 59. Slope With Hybrid Dimming and Phase Shift

Figure 58. Slope with Phase-Shift Mode

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9.2.2 Low VDD Voltage and Combined Output Mode Application

Figure 60 shows the application for LED strings in Display mode (OUT1 and OUT2) and Cluster mode (OUT3

and OUT4). External powering must be used for Cluster-mode LED strings. VDD voltage is 3.3 V, and the charge

pump for gate driver powering is enabled.

VIN

3...40 V

R

ISENSE

L

D

Up to 40 V

Q2

C

2x

C

IN

C

OUT

Q1

C1P

C1N

SD

GD

ISENSE

VSENSE_N

VSENSE_P

VDD 3.3 V

R

VDD

SENSE

ISENSE_GND

FB

C_VDD

C_CPUMP

SQW

FILTER

OUT1

LP8860-Q1

SYNC

OUT2

VSYNC

PWM

SCLK

MOSI

MISO

NSS

SCLK/SCL

MOSI/SDA

MISO

OUT3

OUT4

MCU/GPU

NSS

TSENSE

ISET

EN

External

Powering

VDDIO/EN

IF

VDDIO

FAULT

SGND

PGND LGND PAD

VDDIO

Figure 60. VDD = 3.3V, SPI, 2 Outputs in Display Mode,

2 in Cluster Mode Schematic

9.2.2.1 Design Requirements

Table 27. EEPROM Setting Example

ADDRESS (HEX)

DATA (HEX)

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

ED

DF

DC

F4

DF

E5

F2

77

71

3F

B7

17

EF

B0

87

CF

72

E5

DF

35

06

DE

FF

3E

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DESIGN PARAMETER

VALUE

VIN voltage range

VDD voltage

3 V to 40 V

3.3 V

Charge pump

Enabled

SPI

Brightness Control

Output configuration

LED string current

External current set resistor

Boost frequency

Mode 2, OUT1 and OUT2 - display mode (phase shift 180º), OUT3 and OUT4 - cluster mode

OUT1 and OUT2 - 130 mA; OUT3 - 30 mA; OUT4 - 33 mA

Disabled

303 kHz

Inductor

22 μH to 33 μH, at least 5-A saturation current

10 μF ceramic and 33 μF electrolytic

Disabled

Input/Output capacitors

Current dimming with external NTC

9.2.2.2 Detailed Design Procedure

See Detailed Design Procedure.

9.2.2.3 Application Performance Plots

See Application Performance Plots.

9.2.3 High Output Voltage Application

The LP8860-Q1 has ability to control up to 16 or 17 LEDs per string with additional external components for

output overvoltage protection. nFET transistors can protect outputs, and SQW output can be used to produce

extra rail voltage for the transistor gates, if necessary voltage is not available in the system.

VIN

8...48 V

R

ISENSE

Up to 60 V

L1

Q2

C

IN

D1

Q1

C

OUT

C1P

C1N

R1

DIV

GD

SD

VSENSE_N

VSENSE_P

ISENSE

R

R2

DIV

SENSE

VDD 5 V

C_VDD

ISENSE_GND

VDD

FB

CPUMP

C_CPUMP

SQW

VDD 5 V

FILTER

OUT1

OUT2

OUT3

LP8860-Q1

SYNC

50 kHz

VSYNC

PWM

SCL

SDA

SCLK/SCL

MOSI/SDA

MISO

MCU/GPU

OUT4

NSS

Protection

FETs

VDDIO/EN

IF

10 V

TSENSE

ISET

FAULT

SGND PGND LGND PAD

VDDIO

Figure 61. VDD = 5 V, I²C, High-Voltage Output with Output Protection FETs Circuits

9.2.3.1 Design Requirements

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Table 28. EEPROM Setting Example

ADDRESS (HEX)

DATA (HEX)

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

ED

DF

DC

F4

DF

E5

F2

77

71

3F

B7

17

EF

B0

87

CF

72

E5

DF

35

06

DE

FF

3E

DESIGN PARAMETER

VIN voltage range

VALUE

3 V to 48 V

5 V

VDD voltage

Charge pump

Brightness Control

Disabled

I²C

Mode 0, all outputs are in display mode, phase shift 90º, synchronized with VSYNC 50kHz,

10 LEDs per string, ƒ_{LED_PWM}= 10 kHz

Output configuration

LED string current

OUT1 to OUT4 - 120 mA

Disabled

External current set resistor

Boost frequency

303 kHz

Inductor

22 μH to 33 μH, at least 9-A saturation current

10 μF ceramic and 33 μF electrolytic

Disabled

Input/Output capacitors

Current dimming with external NTC

VSYNC

Enabled, 50 kHz

Feedback voltage divider

R1_DIV= 30 kΩ, R2_DIV= 150 kΩ

9.2.3.2 Detailed Design Procedure

See Detailed Design Procedure.

9.2.3.3 Application Performance Plots

See Application Performance Plots.

9.2.4 High Output Current Application

The LP8860-Q1 outputs can be tied together to drive LED with higher current. To drive a 300 mA/string, connect

2 outputs together. All 4 outputs connected together can drive up to a 600-mA LED string.

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VIN

3...40V

R

ISENSE

L

D

Up to 40V

Q2

C

2x

C

IN

C

OUT

Q1

C1P

C1N

SD

GD

ISENSE

VSENSE_N

VSENSE_P

VDD 3.3V

R

VDD

SENSE

ISENSE_GND

FB

CPUMP

SQW

FILTER

Up to 300mA/string

BOOST SYNC 300 kHz

LP8860-Q1

SYNC

OUT1

VSYNC

OUT2

OUT3

PWM

SCLK

MOSI

SCLK/SCL

MOSI/SDA

MISO

OUT4

MISO

NSS

MCU/GPU

NSS

EN

TSENSE

ISET

VDDIO/EN

IF

VDDIO

FAULT

SGND PGND LGND PAD

VDDIO

Figure 62. Two Channels at 300 mA/String, VDD = 3.3 V, SPI

9.2.4.1 Design Requirements

Table 29. EEPROM Setting Example

ADDRESS (HEX)

DATA (HEX)

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

EF

FF

DC

F8

DF

E5

F2

77

71

3F

B7

17

EF

B1

87

DF

72

E5

DF

35

06

DE

FF

3E

95

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DESIGN PARAMETER

VIN voltage range

VALUE

3 V to 40 V

3.3 V

VDD voltage

Charge pump

Enabled

SPI

Brightness Control

Output configuration

LED string current

Mode 4, OUT1 to OUT4 in display mode, phase shift between tied groups 180º

OUT1 and OUT2 - 300 mA; OUT3 and OUT4 - 300 mA

Disabled

External current set resistor

Boost frequency

300 kHz externally synchronized

Inductor

22 μH to 33 μH, at least 9-A saturation current

10-μF ceramic and 33-μF electrolytic

Disabled

Input/Output capacitors

Current dimming with external NTC

9.2.4.2 Detailed Design Procedure

See Detailed Design Procedure.

9.2.4.3 Application Performance Plots

See Application Performance Plots.

9.2.5 Three-Channel Configuration Without Serial Interface

Outputs which are not used can be left floating. In this example 3 outputs are in use. PSPWM mode for 3 outputs

is set to mode 1 <LED_STRING_CONF[2:0]> = 001b, and the serial interface is not used. The device is enabled

with the EN/VDDIO pin, and brightness control is set with the PWM input. EEPROM settings must be pre-

programmed for brightness dimming with external PWM.

LED current dimming with external NTC sensor is used in this application to protect LEDs against over-heating.

VIN

3...40 V

R

ISENSE

L

D

Up to 40 V

Q2

C

IN

C

OUT

Q1

C1P

C1N

SD

GD

VSENSE_N

VSENSE_P

ISENSE

VDD 5 V

R

VDD

SENSE

ISENSE_GND

FB

CPUMP

SQW

FILTER

Up to 150 mA/string

LP8860-Q1

SYNC

OUT1

VSYNC

BRIGHTNESS

OUT2

OUT3

PWM

SCLK/SCL

MOSI/SDA

MISO

OUT4

FAULT RESET

EN

R

T1

NSS

TSENSE

ISET

R

T°

VDDIO/EN

IF

FAULT

R

T2

NTC

SGND PGND LGND PAD

R

ISET

VDDIO

Figure 63. Three-Channel Configuration without Serial Interface

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9.2.5.1 Design Requirements

Table 30. EEPROM Setting Example

ADDRESS (HEX)

DATA (HEX)

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

6F

FF

DC

F2

DF

E5

F8

77

E1

BF

B7

17

EF

B1

87

CE

72

E5

DF

35

06

DC

CF

3F

DESIGN PARAMETER

VIN voltage range

VDD voltage

VALUE

3 V to 40 V

5 V

Charge pump

Disabled

PWM

Brightness Control

Output configuration

LED string current

External current set resistor

Boost frequency

Mode 1, OUT1 to OUT3 - display mode; OUT4 - not used

OUT1 to OUT3 - 150 mA

Enabled, R_ISET= 24 kΩ

303 kHz

Inductor

22 μH to 33 μH, at least 6-A saturation current

10-μF ceramic and 33 μF electrolytic

Input/Output capacitors

Enabled,R_T°= NCP15XH103F03RC (Murata), see Figure 64, R_T1= 6.6 kΩ, R_T2not

assembled

Current dimming with external NTC

97

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9.2.5.2 Detailed Design Procedure

LED current dimming with external NTC sensor is used in this application — see section LED Current Dimming

With External NTC Sensor for details. Figure 65 shows LED current de-rating versus temperature measured by

NTC sensor with characteristic shown in Figure 64.

4.0

100

90

80

70

60

50

40

30

20

10

0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

EXT_TEMP_MINUS[1:0]=01b

EXT_TEMP_GAIN[3:0]=1110b

EXT_TEMP_LEVEL_HIGH[3:0]=1100b

40

50

60

70

80

90

100

110

120

40

50

60

70

80

90

100

110

120

Temperature (ºC)

C008

Temperature (ºC)

C009

Figure 65. LED Current De-rating vs Temperature

Figure 64. NTC Sensor Resistance vs Temperature

9.2.5.3 Application Performance Plots

See Application Performance Plots.

9.2.6 Solution With Minimum External Components

The LP8880-Q1 needs only a few external components for basic functionality if material cost and PCB area for a

LP8860-Q1-based solution need to be minimized. In this example the power-line FET is removed, as is input

current sensing. External synchronization functions are disabled.

VIN

3...40 V

Up to 40 V

L1

D

C

IN

Q

C1P

C1N

GD

SD

VSENSE_N

VSENSE_P

ISENSE

R

SENSE

VDD 5 V

ISENSE_GND

FB

VDD

CPUMP

SQW

FILTER

OUT1

OUT2

OUT3

OUT4

LP8860-Q1

SYNC

VSYNC

BRIGHTNESS

PWM

SCLK/SCL

MOSI/SDA

MISO

FAULT RESET

ENABLE

TSENSE

ISET

NSS

VDDIO/EN

IF

FAULT

SGND PGND LGND PAD

VDDIO

Figure 66. Solution With Minimum External Components

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ZHCSCK8G –MAY 2014–REVISED OCTOBER 2017

9.2.6.1 Design Requirements

Table 31. EEPROM Setting Example

ADDRESS (HEX)

DATA (HEX)

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

EF

FF

DC

D0

DF

E5

F0

77

71

3F

B7

17

EF

B0

87

CE

07

E5

DF

75

86

DC

FF

3E

DESIGN PARAMETER

VIN voltage range

VALUE

3 V to 40 V

5 V

VDD voltage

Charge pump

Disabled

PWM

Brightness Control

Output configuration

LED string current

Mode0, OUT1 to OUT4 in display mode, phase shift 90º

OUT1 to OUT4 - 100 mA

External current set resistor

Boost frequency

Disabled

2.2 MHz

Inductor

4.7 µH to 22 µH, at least 6-A saturation current

Input/Output capacitors

Current dimming with external NTC

2 × 10-μF ceramic

Disabled

10 Power Supply Recommendations

The LP8860-Q1 is designed to operate from a car battery. V_INinput must be protected from reversal voltage and

voltage dump over 48 Volts. The impedance of the input supply rail must be low enough that the input current

transient does not cause drop below VIN UVLO level. If the input supply is connected by using long wires,

additional bulk capacitance may be required in addition to normal input capacitor .

The voltage range for VDD is 3 V to 5.5 V. A ceramic capacitor must be placed as close as possible to the VDD

pin. The boost gate driver is powered from the VDD pin; this must be taken into account. For high boost

frequency and high internal PLL frequency (can be up to 40 MHz), power consumption from VDD pin can be

around 20 mA to 40 mA.

99

LP8860-Q1

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11 Layout

11.1 Layout Guidelines

Figure 67 shows a layout recommendation for the LP8860-Q1. Figure 67 is used to show the principles of good

layout. This layout can be adapted to the actual application layout if and where possible. It is important that all

boost components are close to each other and to the device; the high-current traces must be wide enough. VDD

must be as noise-free as possible. Place a VDD bypass capacitor near the pin and ground it to a noise-free

ground. A charge-pump capacitor and boost input and output capacitors must be connected to PGND. Here are

some main points to help the PCB layout work:

•

Current loops need to be minimized:

–

For low frequency the minimal current loop can be achieved by placing the boost components as close to

each other as possible. Input and output capacitor grounds need to be close to each other to minimize

current loop size.

–

Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact

under the current traces. High frequency return currents try to find route with minimum impedance, which

is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when

return current flows just under the positive current route in the ground plane, if the ground plane is intact

under the route.

–

For high frequency the copper area capacitance must be taken into account. For example, the copper

area for the drain of boost nMOSFET is a tradeoff between capacitance and components cooling capacity.

•

GND plane must be intact under the high current boost traces to provide shortest possible return path and

smallest possible current loops for high frequencies.

Current loops when the boost switch is conducting and not conducting must be in the same direction in

optimal case.

Inductors must be placed so that the current flows in the same direction as in the current loops. Rotating the

inductor 180° changes current direction.

Use separate power and noise-free grounds. The power ground is used for boost converter return current and

noise-free ground for more sensitive signals, like VDD bypass capacitor grounding as well as grounding the

GND pins of the LP8860-Q1 itself.

•

Boost output feedback voltage to LEDs need to be taken out after the output capacitors, not straight from the

diode cathode.

A small (for example, 39-pF) bypass capacitor must be placed close to the FB pin to suppress high frequency

noise

VDD line must be separated from the high current supply path to the boost converter to prevent high

frequency ripple affecting the chip behavior. A separate 1-µF bypass capacitor is used for the VDD pin, and it

is grounded to noise-free ground.

•

Capacitor connected to charge pump output CPUMP must have 10-µF capacitance, grounded by shortest

way to boost switch current sensing resistor. This capacitor must be as close as possible to CPUMP pin. This

capacitor provides a greater peak current for gate driver and must be used even if the charge pump is

disabled. If the charge pump is disabled, the VDD and CPUMP pins must be tied together.

•

Input and output capacitors need strong grounding (wide traces, many vias to PGND plane).

If two or more output capacitors are used, symmetrical layout must be used to get all capacitors working

ideally.

•

Input/output ceramic capacitors have DC-bias effect. If the output capacitance is too low, it can cause boost

to become unstable on some loads. DC bias characteristics need to be obtained from the component

manufacturer; it is not taken into account on component tolerance. TI recommends X5R/X7R capacitors.

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ZHCSCK8G –MAY 2014–REVISED OCTOBER 2017

11.2 Layout Example

BATTERY

+VBATT -VBATT

R1

R2

Input capacitors

Q1

L1

C3

C4

C8

C9

D1

Output capacitors

Feedback line

Connection

between PGND

and GND

R5

Q2

Ground wire for

current sensor

R4

C6

R3

C2

C7

1

2

3

4

5

6

7

8

24

OUT2

C1P

C5

C1

C1N

LGND 23

VDD

OUT3

OUT4

IF

22

21

20

19

18

17

SQW

VDD

VSENSE_N

VSENSE_P

ISET

VDDIO/EN

PWM

TSENSE

NSS

VIA to GND plane

Figure 67. LP8860-Q1 Layout

101

LP8860-Q1

ZHCSCK8G –MAY 2014–REVISED OCTOBER 2017

www.ti.com.cn

12 器件和文档支持

12.1 器件支持

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

12.2 文档支持

12.2.1 相关文档

如需相关文档，请参阅：

•

《PowerPAD™ 耐热增强型封装应用手册》

《了解开关模式电源中的升压功率级》

Power Stage Designer™ 工具

12.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。请单击右上角的提醒我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.5 商标

E2E is a trademark of Texas Instruments.

PowerPAD is a trademark of Texas Instruments Incorporated.

All other trademarks are the property of their respective owners.

12.6 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

102

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13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修

订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

103

LP8860-Q1

ZHCSCK8G –MAY 2014–REVISED OCTOBER 2017

www.ti.com.cn

PACKAGE OUTLINE

VFP0032A

PowerPAD ^TMLQFP - 1.6 mm max height

SCALE 1.700

PPLLAASSTTICICQQUUAADDFFLLAATTPPAACCKK

7.2

6.8

B

NOTE 4

25

32

PIN 1 ID

1

24

7.2

6.8

9.2

TYP

8.8

NOTE 3

8

17

16

9

A

0.45

0.30

32X

28X 0.8

4X 5.6

0.22

C A B

C

1.6 MAX

SEATING PLANE

SEE DETAIL A

(0.127)

TYP

9

16

8

17

0.25

GAGE PLANE

(1.4)

2.86

2.32

33

0.15

0.05

0.1 C

0 -7

0.75

0.45

A

15

8X (0.6)

NOTE 4

DETAIL A

TYPICAL

8X (0.23)

NOTE 4

1

24

32

25

4223940/A 10/2017

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs.

4. Strap features may not be present.

5. Reference JEDEC registration MS-026.

www.ti.com

104

LP8860-Q1

www.ti.com.cn

ZHCSCK8G –MAY 2014–REVISED OCTOBER 2017

EXAMPLE BOARD LAYOUT

VFP0032A

PowerPAD^TMLQFP - 1.6 mm max height

PLASTIC QUAD FLATPACK

( 5)

NOTE 8

(

2.86)

SYMM

32

25

SOLDER MASK

DEFINED PAD

32X (1.5)

1

24

32X (0.55)

SYMM

33

(8.4)

(1 TYP)

28X (0.8)

17

8

(R0.05) TYP

(

0.2) TYP

VIA

METAL COVERED

BY SOLDER MASK

SEE DETAILS

9

16

(1 TYP)

(8.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

METAL UNDER

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4223940/A 10/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,

Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled,

plugged or tented.

10. Size of metal pad may vary due to creepage requirement.

www.ti.com

105

LP8860-Q1

ZHCSCK8G –MAY 2014–REVISED OCTOBER 2017

www.ti.com.cn

EXAMPLE STENCIL DESIGN

VFP0032A

PowerPAD ^TMLQFP - 1.6 mm max height

PLASTIC QUAD FLATPACK

(

2.86)

BASED ON

0.125 THICK STENCIL

32

SEE TABLE FOR

SYMM

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

25

32X (1.5)

1

24

32X (0.55)

SYMM

33

(8.4)

28X (0.8)

17

8

(R0.05) TYP

METAL COVERED

BY SOLDER MASK

9

16

(8.4)

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:8X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

3.20 X 3.20

2.86 X 2.86 (SHOWN)

2.61 X 2.61

0.125

0.15

0.175

2.42 X 2.42

4223940/A 10/2017

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

www.ti.com

106

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

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所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

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TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

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型号：	LP8860LQVFPRQ1
厂家：	TEXAS INSTRUMENTS
描述：	汽车类低 EMI 高性能 4 通道 LED 驱动器 \| VFP \| 32 \| -40 to 125 驱动接口集成电路驱动器
文件：	总109页 (文件大小：1604K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LP8860LQVFPRQ1 [TI]

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