LP8861-Q1 [TI]
适用于汽车照明的低 EMI、高性能 4 通道 LED 驱动器;
| 型号： | LP8861-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于汽车照明的低 EMI、高性能 4 通道 LED 驱动器 驱动 驱动器 |
| 文件： | 总44页 (文件大小：1209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LP8861-Q1
ZHCSE41C –AUGUST 2015–REVISED MAY 2017
LP8861-Q1 具有四个 100mA 通道的低 EMI 汽车 LED 驱动器
1 特性
3 说明
1
•
符合汽车应用要求 要求
具有符合 AECQ100 标准的下列结果：
LP8861-Q1 是一款带有集成升压/SEPIC 转换器的低
EMI 且易于使用的汽车类高效 LED 驱动器。该器件具
有四路高精度电流阱，可通过脉宽调制 (PWM) 输入信
号提供调光比率较高的亮度控制。
•
–
器件温度 1 级：-40°C 至 +125°C 的环境运行温
度范围
•
•
输入工作电压范围：4.5V 至 40V
升压/SEPIC 转换器可基于 LED 电流阱余量电压提供
自适应输出电压控制。该特性可在所有条件下将电压调
节到能够满足需要的最低水平，从而最大限度降低功
耗。升压/SEPIC 转换器支持针对开关频率进行扩频以
及通过专用引脚实现外部同步。 凭借宽范围可调频
率，LP8861-Q1 能够避免调幅 (AM) 射频波段的干
扰。
四路高精度电流阱
–
–
–
电流匹配度为 1%（典型值）
LED 灯串电流高达 100mA/通道
100Hz 下的调光比为 10 000:1
•
用于 LED 灯串电源的集成升压/SEPIC 转换器
–
–
–
–
输出电压高达 45V
开关频率：300kHz 至 2.2MHz
开关同步输入
LP8861-Q1 可选择驱动外部 p-FET，以在发生故障时
断开输入电源与系统间的连接，从而减少浪涌电流并降
低待机功耗。该器件可基于外部负温度系数 (NTC) 传
感器测得的温度降低 LED 电流，以防 LED 过热并延
长其使用寿命。
扩展频谱可降低电磁干扰 (EMI)
•
•
电力线场 FET 控制可实现浪涌电流保护和待机节能
丰富的故障检测和容错功能 特性
–
–
故障输出
输入电压过压保护 (OVP)、欠压锁定 (UVLO)
和过流保护 (OCP)
LP8861-Q1 的输入电压范围为 4.5V 至 40V，支持汽
车启动/停止以及负载突降的情况。LP8861-Q1 集成了
丰富的故障检测和保护 功能。
–
–
–
开路和短路 LED 故障检测
使用外部温度传感器自动降低 LED 电流
热关断
器件信息(1)
器件型号
LP8861-Q1
封装
封装尺寸（标称值）
•
最大限度减少外部组件数
TSSOP (20)
6.50mm x 4.50mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
•
为以下应用提供背光：
简化原理图
–
–
–
–
–
–
汽车信息娱乐系统
汽车仪表盘
VIN
4.5...40 V
RISENSE
L1
D1
Q1
Up to 45 V
智能车镜
C
OUT
CIN BOOST
RGS
抬头显示屏 (HUD)
中央信息显示屏 (CID)
音视频导航 (AVN)
R2
R1
SW
SD
VSENSE_N
VIN
FB
C
FB
CLDO
VLDO
RFSET
C
Up to 100 mA/string
IN
LDO
OUT1
LP8861-Q1
OUT2
OUT3
OUT4
系统效率
VLDO
R4
FSET
SYNC
100
95
90
85
80
75
70
65
60
R3
BRIGHTNESS
EN
PWM
TSET
R7
TSENSE
VDDIO/EN
FAULT
RTº
ISET
R6
R5
PGND
GND PAD
NTC
VIN=5V
VIN=8V
VIN=12V
VIN=16V
RISET
0
20
40
60
80
100
Brightness (%)
C010
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSA50
LP8861-Q1
ZHCSE41C –AUGUST 2015–REVISED MAY 2017
www.ti.com.cn
目录
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 23
Application and Implementation ........................ 25
9.1 Application Information............................................ 25
9.2 Typical Applications ................................................ 25
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
器件比较表............................................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 7
7.5 Electrical Characteristics .......................................... 7
7.6 Internal LDO Electrical Characteristics ..................... 7
7.7 Protection Electrical Characteristics ......................... 7
7.8 Power Line FET Control Electrical Characteristics ... 8
7.9 Current Sinks Electrical Characteristics.................... 8
7.10 PWM Brightness Control Electrical Characteristics 8
7.11 Boost/SEPIC Converter Characteristics ................. 8
7.12 Logic Interface Characteristics................................ 9
7.13 Typical Characteristics.......................................... 10
Detailed Description ............................................ 12
9
10 Power Supply Recommendations ..................... 34
11 Layout................................................................... 34
11.1 Layout Guidelines ................................................. 34
11.2 Layout Example .................................................... 35
12 器件和文档支持 ..................................................... 36
12.1 器件支持................................................................ 36
12.2 文档支持................................................................ 36
12.3 接收文档更新通知 ................................................. 36
12.4 社区资源................................................................ 36
12.5 商标....................................................................... 36
12.6 静电放电警告......................................................... 36
12.7 术语表 ................................................................... 36
13 机械、封装和可订购信息....................................... 36
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (April 2017) to Revision C
Page
•
Expanded descriptions for pins 3, 8, 9, 10, and 16 in Pin Functions .................................................................................... 5
Changes from Revision A (November 2015) to Revision B
Page
•
•
•
•
•
•
•
已更改 “200Hz 下的调光比为 10 000:1”改为“100Hz 下的调光比为 10 000:1”........................................................................ 1
已更改 的一些措辞2................................................................................................................................................................ 1
已添加 新的列表项至应用 ....................................................................................................................................................... 1
已更改 “控制器”至“转换器”，“高开关...”至“宽范围可调...” ....................................................................................................... 1
已添加 器件比较表 表 ............................................................................................................................................................. 3
Changed "In synchronization" to "If synchronization"............................................................................................................. 5
Changes to PWM Brightness Control Electrical Characteristics: delete "IOUT = 100 mA. No external load from LDO"
from Minimum ON/OFF time test conditions; move "0.5" from MAX to TYP in same row; add footnote 1............................ 8
•
•
•
•
•
•
•
Added footnote 1 to Boost/SEPIC Converter Characteristics for Toff, tsync_on_min, and tsync_off_min ............................ 8
Deleted "Initial DC-DC voltage is about 88% of VMAX BOOST." from Integrated Boost/SEPIC Converter............................... 14
Changed Equation 1............................................................................................................................................................. 14
Added definitions for Equation 1........................................................................................................................................... 14
Added paragraph after Figure 9 .......................................................................................................................................... 14
Added new paragraph before Internal LDO ......................................................................................................................... 16
Deleted "Dimming ratio is calculated as ratio between the input PWM period and minimum on/off time (0.5 μs)."
from Brightness Control........................................................................................................................................................ 16
•
Changed "less then" to "less than"....................................................................................................................................... 27
2
版权 © 2015–2017, Texas Instruments Incorporated
LP8861-Q1
www.ti.com.cn
ZHCSE41C –AUGUST 2015–REVISED MAY 2017
Changes from Original (August 2015) to Revision A
Page
•
•
•
•
Changed maximum Tstg from 160°C to 150°C ...................................................................................................................... 6
Added last 2 sentences to end of Internal LDO. .................................................................................................................. 16
Changed Equation 3 ............................................................................................................................................................ 16
Changed Figure 29 to update VIN and VSENSE_N pin connections; removed RISENSE row from sub-section
8.2.2.1 Design Requirements ............................................................................................................................................... 28
5 器件比较表
LP8860-Q1
LP8862-Q1
LP8861-Q1
TPS61193-Q1
TPS61194-Q1
TPS61196-Q1
VIN 范围
3V 至 48V
4.5V 至 45V
4.5V 至 45V
4.5V 至 45V
4.5V 至 45V
8V 至 30V
# LED 通道
LED 电流/通道
I2C/SPI 支持
SEPIC 支持
4
150mA
是
2
160mA
否
4
100mA
否
3
100mA
否
4
100mA
否
6
200mA
无
无
有
是
是
是
否
Copyright © 2015–2017, Texas Instruments Incorporated
3
LP8861-Q1
ZHCSE41C –AUGUST 2015–REVISED MAY 2017
www.ti.com.cn
6 Pin Configuration and Functions
PWP Package
20-Pin TSSOP with Exposed Thermal Pad
Top View
VIN
LDO
1
2
3
4
5
6
7
8
9
20 VSENSE_N
19 SD
FSET
18 SW
VDDIO/EN
FAULT
SYNC
17 PGND
16 FB
15 OUT1
14 OUT2
13 OUT3
12 OUT4
11 GND
PWM
TSENSE
TSET
EP*
ISET 10
*EXPOSED PAD
4
Copyright © 2015–2017, Texas Instruments Incorporated
LP8861-Q1
www.ti.com.cn
ZHCSE41C –AUGUST 2015–REVISED MAY 2017
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NUMBER
NAME
1
VIN
P
A
Input power pin as well as the positive input for an optional current-sense resistor.
Output of internal LDO; connect a 1-μF decoupling capacitor between this pin and noise-free
ground.
2
LDO
Boost/SEPIC switching frequency setting resistor; for normal operation, resistor value from 24 kΩ
to 219 kΩ must be connected between this pin and ground.
3
4
5
FSET
VDDIO/EN
FAULT
A
I
Enable input for the device as well as supply input (VDDIO) for digital pins
Fault signal output.
If unused, the pin may be left floating.
OD
Input for synchronizing boost/SEPIC.
6
SYNC
I
If synchronization is not used, connect this pin to GND to disable spread spectrum or to
VDDIO/EN to enable spread spectrum.
7
8
PWM
I
PWM dimming input.
Input for NTC bridge. Refer to LED Current Dimming With External Temperature Sensor for
proper connection. If unused, the pin must be left floating.
TSENSE
A
Input for NTC bridge. Refer to LED Current Dimming With External Temperature Sensor for
proper connection. This pin must be connected to GND if not used.
9
TSET
A
LED current setting resistor; for normal operation, resistor value from 24 kΩ to 129 kΩ must be
connected between this pin and ground.
10
11
12
ISET
GND
A
G
A
Ground.
Current sink output.
This pin must be connected to GND if not used.
OUT4
Current sink output.
This pin must be connected to GND if not used.
13
14
15
16
OUT3
OUT2
OUT1
FB
A
A
A
A
Current sink output.
This pin must be connected to GND if not used.
Current sink output.
This pin must be connected to GND if not used.
Boost/SEPIC feedback input; for normal operation this pin must be connected to the middle of a
resistor divider between VOUT and ground using feedback resistor values from 5 kΩ to 150 kΩ.
17
18
PGND
SW
G
A
Boost/SEPIC power ground.
Boost/SEPIC switch pin.
Power-line FET control.
If unused, the pin may be left floating.
19
20
SD
A
A
Input current sense pin. Connect to VIN pin when optional input current sense resistor is not
used.
VSENSE_N
(1) A: Analog pin, G: Ground pin, P: Power pin, I: Input pin, I/O: Input/Output pin, O: Output pin, OD: Open Drain pin
Copyright © 2015–2017, Texas Instruments Incorporated
5
LP8861-Q1
ZHCSE41C –AUGUST 2015–REVISED MAY 2017
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
VIN, VSENSE_N, SD, SW, FB
50
45
Voltage on pins
OUT1…OUT4
V
LDO, SYNC, FSET, ISET, TSENSE, TSET, PWM, VDDIO/EN, FAULT
5.5
Continuous power dissipation(3)
Internally Limited
(4)
Ambient temperature range, TA
Junction temperature range, TJ
–40
–40
125
ºC
ºC
ºC
°C
(4)
150
See(5)
150
Maximum lead temperature (soldering)
Storage temperature, Tstg
–65
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the potential at the GND pins.
(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 165°C (typical) and
disengages at TJ = 145°C (typical).
(4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP
=
150°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
(5) For detailed soldering specifications and information, refer to the PowerPAD™ Thermally Enhanced Package Application Note
(SLMA002).
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Electrostatic
discharge
V(ESD)
Other pins
V
Corner pins (1,10,11,20)
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VIN
4.5
0
45
45
VSENSE_N, SD, SW
Voltage on pins
OUT1…OUT4
0
40
V
FB, FSET, LDO, ISET, TSENSE, TSET, VDDIO/EN, FAULT
SYNC, PWM
0
5.25
0
VDDIO/EN
(1) All voltages are with respect to the potential at the GND pins.
6
Copyright © 2015–2017, Texas Instruments Incorporated
LP8861-Q1
www.ti.com.cn
ZHCSE41C –AUGUST 2015–REVISED MAY 2017
7.4 Thermal Information
LP8861-Q1
THERMAL METRIC(1)
PWP (TSSOP)
20 PINS
44.2
UNIT
RθJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
26.5
Junction-to-board thermal resistance
22.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.9
ψJB
22.2
RθJCbot
2.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
7.5 Electrical Characteristics
TJ = −40°C to +125°C (unless otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Device disabled, VVDDIO/EN = 0 V,
VIN = 12 V
Standby supply current
4.5
20
μA
IQ
VIN = 12 V, VBOOST= 26 V, output
current 80 mA/channel, ƒSW= 300
kHz
Active supply current
5
12
mA
V
LDO pin voltage. Output of the
internal LDO or an external supply
input (VDD).
VPOR_R
Power-on reset rising threshold
Power-on reset falling threshold
2.7
LDO pin voltage. Output of the
internal LDO or an external supply
input (VDD).
VPOR_F
1.5
V
TTSD
Thermal shutdown threshold
Thermal shutdown hysteresis
150
165
20
175
°C
°C
TTSD_THR
(1) All voltages are with respect to the potential at the GND pins.
(2) Min and Max limits are specified by design, test, or statistical analysis.
7.6 Internal LDO Electrical Characteristics
TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER
Output voltage
TEST CONDITIONS
MIN
4.15
120
TYP
4.3
220
50
MAX
4.45
430
UNIT
V
VLDO
VIN = 12 V
VDR
Dropout voltage
External current load 5 mA
mV
mA
mA
ISHORT
IEXT_MAX
Short circuit current
Maximum current for external load
5
7.7 Protection Electrical Characteristics
TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
41
TYP
42
MAX
44
UNIT
V
VOVP
VIN OVP threshold voltage
VIN OCP current
IOCP
RSENSE = 50 mΩ
2.7
3.2
4.0
100
6
3.7
A
VUVLO
VIN UVLO
V
VUVLO_HYST
VIN UVLO hysteresis
LED short detection threshold
mV
V
5.6
7
Copyright © 2015–2017, Texas Instruments Incorporated
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LP8861-Q1
ZHCSE41C –AUGUST 2015–REVISED MAY 2017
www.ti.com.cn
7.8 Power Line FET Control Electrical Characteristics
TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER
VSENSE_N pin leakage current
SD leakage current
TEST CONDITIONS
VVSENSE_N = 45 V
VSD = 45 V
MIN
TYP
0.1
MAX
UNIT
µA
3
3
0.1
µA
SD pulldown current
185
230
283
µA
7.9 Current Sinks Electrical Characteristics
TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µA
ILEAKAGE
IMAX
Leakage current
Outputs OUT1 to OUT4, VOUTx = 45 V
OUT1 to OUT4
0.1
5
Maximum current
100
mA
IOUT
Output current accuracy
Output current matching(1)
Saturation voltage(2)
IOUT = 100 mA
−5%
5%
3.5%
0.7
IMATCH
VSAT
IOUT = 100 mA, PWM duty = 100%
IOUT = 100 mA, VLDO = 4.3 V
1%
0.4
V
(1) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current.
Matching is the maximum difference from the average. For the constant current sinks on the part (OUT1 to OUT4), the following are
determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG).
Matching number is calculated: (MAX-MIN)/AVG. The typical specification provided is the most likely norm of the matching figure for all
parts. LED current sinks were characterized with 1-V headroom voltage. Note that some manufacturers have different definitions in use.
(2) Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1 V.
7.10 PWM Brightness Control Electrical Characteristics
TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Hz
Recommended PWM input
frequency
ƒPWM
100
20 000
tON/OFF
Minimum ON/OFF time(1)
0.5
µs
(1) This specification is not ensured by ATE.
7.11 Boost/SEPIC Converter Characteristics
TJ = −40°C to +125°C (unless otherwise noted).
Unless otherwise specified: VIN = 12 V, VVDDIO/EN = 3.3 V, L = 22 μH, CIN = 2 × 10-μF ceramic and 33-μF electrolytic,
COUT = 2 × 10-μF ceramic and 33-μF electrolytic, D = NRVB460MFS, ƒSW = 300 kHz.
PARAMETER
Input voltage
Output voltage
TEST CONDITIONS
MIN
4.5
10
TYP
MAX
40
UNIT
V
VIN
VOUT
45
V
Minimum switching frequency
(central frequency if spread
spectrum is enabled)
ƒSW_MIN
300
kHz
kHz
Defined by RFSET resistor
Maximum switching frequency
(central frequency if spread
spectrum is enabled)
ƒSW_MAX
2200
VOUT/VIN
TOFF
Conversion ratio
Minimum switch OFF time(1)
10
55
ƒ
SW ≥ 1.15 MHz
ns
A
ISW_MAX
RDSon
SW current limit
1.8
2
2.2
FET RDSon
Pin-to-pin
240
400
2200
mΩ
kHz
ƒSYNC
External SYNC frequency
300
External SYNC minimum ON
time(1)
tSYNC_ON_MIN
tSYNC_OFF_MIN
150
150
ns
ns
External SYNC minimum OFF
time(1)
(1) This specification is not ensured by ATE.
8
Copyright © 2015–2017, Texas Instruments Incorporated
LP8861-Q1
www.ti.com.cn
ZHCSE41C –AUGUST 2015–REVISED MAY 2017
7.12 Logic Interface Characteristics
TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC INPUT VDDIO/EN
VIL
VIH
II
Input low level
Input high level
Input current
0.4
V
V
1.65
−1
5
30
0.2 × VVDDIO/EN
1
µA
LOGIC INPUTS SYNC, PWM
VIL
VIH
II
Input low level
Input high level
Input current
V
0.8 × VVDDIO/EN
−1
μA
LOGIC OUTPUT FAULT
VOL
Output low level
Pullup current 3 mA
V = 5.5 V
0.3
0.5
1
V
ILEAKAGE
Output leakage current
μA
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ZHCSE41C –AUGUST 2015–REVISED MAY 2017
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7.13 Typical Characteristics
Unless otherwise specified: D = NRVB460MFS, T = 25°C.
1000
900
800
700
600
500
1000
900
800
700
600
500
400
300
200
Vboost = 22 V
Vboost = 30 V
Vboost = 37 V
Vboost = 22 V
Vboost = 30V
Vboost = 37 V
400
300
200
5
10
15
20
25
30
5
10
15
20
25
30
Input Voltage (V)
Input Voltage (V)
C001
C002
ƒSW = 300 kHz
L = 33 μH
DC Load (PWM = 100%)
ƒSW = 800 kHz
L = 15 μH
DC Load (PWM = 100%)
CIN and COUT = 33 µF + 2 × 10 µF (ceramic)
CIN and COUT = 2 × 10 µF (ceramic)
Figure 1. Maximum Boost Output Current
Figure 2. Maximum Boost Output Current
1000
900
800
700
600
500
400
300
200
1000
900
800
700
600
500
400
300
200
Vboost = 22 V
Vboost = 30 V
Vboost = 37 V
Vboost = 22 V
Vboost = 30 V
Vboost = 37 V
5
10
15
20
25
30
5
10
15
20
25
30
Input Voltage (V)
Input Voltage (V)
C003
C004
ƒSW = 1.5 MHz
L = 8.2 μH
DC Load (PWM = 100%)
ƒSW = 2.2 MHz
L = 4.7 μH
DC Load (PWM = 100%)
CIN and COUT = 2 × 10 µF (ceramic)
CIN and COUT = 2 × 10 µF (ceramic)
Figure 3. Maximum Boost Output Current
Figure 4. Maximum Boost Output Current
100
80
60
40
20
0
2200
1800
1400
1000
600
200
20
40
60
80
100
120
140
160
20
60
100
140
180
220
RISET (kꢀ)
C005
RFSET (kꢀ)
C009
Figure 5. LED Current vs RISET
Figure 6. Boost Switching Frequency ƒSW vs RFSET
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Typical Characteristics (continued)
Unless otherwise specified: D = NRVB460MFS, T = 25°C.
120
100
80
60
40
20
0
6
5
4
3
2
1
0
40
50
60
70
80
90
100
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Output current (mA)
Voltage (V)
C013
C014
RISET = 24 kΩ
Figure 7. LED Current Sink Matching
Figure 8. LED Current Sink Saturation Voltage
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8 Detailed Description
8.1 Overview
The LP8861-Q1 is a highly integrated LED driver for automotive infotainment, lighting systems, and medium-
sized LCD backlight applications. It includes a boost/SEPIC converter with an integrated FET, an internal LDO,
and four LED current sinks. A VDDIO/EN pin provides the supply voltage for digital IOs (PWM and SYNC inputs)
and at the same time enables the device.
The switching frequency on the boost/SEPIC regulator is set by a resistor connected to the FSET pin. The
maximum voltage is set by a resistive divider connected to the FB pin. For the best efficiency the voltage is
adapted automatically to the minimum necessary level needed to drive the LED strings. This is done by
monitoring LED output voltage in real time. For EMI reduction and control two optional features are available:
•
•
Spread spectrum, which reduces EMI noise spikes at the switching frequency and its harmonic frequencies.
Boost/SEPIC can be synchronized to an external clock frequency connected to the SYNC pin.
The four constant current sinks for driving the LEDs provide current up to 100 mA per sink and can be tied
together to get a higher current. Value for the current value is set with a resistor connected to the ISET pin.
Current sinks that are not used must be connected to the ground. Grounded current sinks are disabled and
excluded from the adaptive voltage and open/short LED fault detection loop.
Brightness is controlled with the PWM input. Frequency range for the input PWM is from 100 Hz to 20 kHz. LED
output PWM follows the input PWM so the output frequency is equal to the input frequency.
The LP8861-Q1 has extensive fault detection features:
•
•
•
•
Open-string and shorted LED detections
LED fault detection prevents system overheating in case of open or short in some of the LED strings
VIN input-overvoltage protection
Threshold sensing from VIN pin
VIN input undervoltage protection
Threshold sensing from VIN pin
VIN input overcurrent protection
Threshold sensing across RISENSE resistor
–
–
–
–
•
•
Thermal shutdown in case of die overtemperature
LED thermal protection with a external NTC (optional feature)
Fault condition is indicated with the FAULT output pin. Additionally, the LP8861-Q1 supports control for an
optional power-line FET allowing further protection in boost/SEPIC overcurrent state by disconnecting the device
from power-line in fault condition. With the power-line FET control it is possible to protect device, boost
components, and LEDs in case of shorted VBOOST and too-high VIN voltage. Power-line FET control also features
soft-start which reduces the peak current from the power line during start-up.
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8.2 Functional Block Diagram
L
RISENSE
D
Q
VIN
RGS
CIN
COUT
CIN BOOST
VIN
VSENSE_N
SD
POWER-LINE FET CONTROL
LDO
LDO
CLDO
SW
SYNC
FSET
PGND
FB
BOOST
CONTROLLER
RFSET
RISET
4 x LED
CURRENT
SINK
ISET
OUT1
OUT2
OUT3
OUT4
GND
TSET
CURRENT
SETTING
TSENSE
PWM
VDDIO/
EN
DIGITAL BLOCKS
(FSM, ADAPTIVE VOLTAGE
CONTROL, SAFETY LOGIC
etc.)
FAULT
ANALOG BLOCKS
(CLOCK GENERATOR, VREF,
TSD etc.)
VDDIO
EXPOSED PAD
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8.3 Feature Description
8.3.1 Integrated Boost/SEPIC Converter
The LP8861-Q1 boost/SEPIC DC-DC converter generates supply voltage for the LEDs. The maximum output
voltage VMAX BOOST is defined by an external resistive divider (R1, R2).
Maximum voltage must be chosen based on the maximum voltage required for LED strings. Recommended VMAX
is about 30% higher than maximum LED string voltage. DC-DC output voltage is adjusted automatically
BOOST
based on LED current sink headroom voltage. Maximum, minimum, and initial boost voltages can be calculated
with Equation 1:
V
≈
’
BG
VBOOST
=
+K ì 0.0387 ì R1+ VBG
∆
«
÷
R2
◊
where
•
•
•
•
•
•
VBG = 1.2 V
R2 recommended value is 130 kΩ
Resistor values are in kΩ
K = 1 for maximum adaptive boost voltage (typical)
K = 0 for minimum adaptive boost voltage (typical)
K = 0.88 for initial boost voltage (typical)
(1)
45
40
35
30
25
20
15
10
200
300
400
500
600
700
800
900
1000
R1 (kꢀ)
C008
Figure 9. Maximum Converter Output Voltage vs R1 Resistance
Alternatively, a T-divider can be used if resistance less than 100 kΩ is required for the external resistive divider.
Refer to LP8861-Q1EVM Evaluation Module for details.
The converter is a current mode DC-DC converter, where the inductor current is measured and controlled with
the feedback. Switching frequency is adjustable between 300 kHz and 2.2 MHz with RFSET resistor as shown in
Equation 2:
ƒSW = 67600/ (RFSET + 6.4)
where
•
•
ƒSW is switching frequency, kHz
RFSET is frequency setting resistor, kΩ
(2)
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Feature Description (continued)
In most cases lower frequency has higher system efficiency. Boost parameters are chosen automatically during
start-up according to the selected switching frequency (see Table 2). In boost mode a 15-pF capacitor CFB must
be placed across resistor R1 when operating in 300 kHz ... 500 kHz range (see Figure 24). When operating in
the 1.8-MHz...2.2-MHz range, CFB = 4.7 pF (see Figure 29).
D
VIN
VBOOST
CIN
COUT
R1
SW
OCP
ADAPTIVE
VOLTAGE
CONTROL
R2
LIGHT
LOAD
CURRENT
SENSE
OVP
RC
R
S
R
R
filter
FB
-
GM
PGND
R
+
SYNC
FSET
GM
ꢀ
FSET
CTRL
BLANK
TIME
BOOST
OSCILLATOR
OFF/BLANK
TIME
CURRENT
RAMP
PULSE
GENERATOR
GENERATOR
RFSET
Figure 10. Boost Block Diagram
Boost clock can be driven by an external SYNC signal between 300 kHz…2.2 MHz. If the external
synchronization input disappears, boost continues operation at the frequency defined by RFSET resistor. When
external frequency disappears and SYNC pin level is low, boost continues operation without spread spectrum
immediately. If SYNC remains high, boost continues switching with spread spectrum enabled after 256 µs.
External SYNC frequency must be 1.2…1.5 times higher than the frequency defined by the RFSET resistor.
Minimum frequency setting with RFSET is 250 kHz to support minimum switching frequency with external clock
frequency 300 kHz.
The optional spread-spectrum feature (±3% from central frequency, 1-kHz modulation frequency) reduces EMI
noise spikes at the switching frequency and its harmonic frequencies. When external synchronization is used,
spread spectrum is not available.
Table 1. Boost Synchronization Mode
SYNC PIN STATUS
MODE
Low
High
Spread spectrum disabled
Spread spectrum enabled
300...2200 kHz frequency
Spread spectrum disabled, external synchronization mode
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Table 2. Boost Parameters(1)
TYPICAL BOOST
TYPICAL
INDUCTANCE
(µH)
FREQUENCY
INPUT
AND OUTPUT
CAPACITORS (µF)
MIN SWITCH
BLANK
TIME (ns)
CURRENT
RAMP (A/s)
CURRENT RAMP
DELAY (ns)
RANGE
(kHz)
OFF TIME (ns)(2)
2 × 10 (cer.) + 33
(electr.)
1
300...480
33
150
95
24
550
2
3
4
480...1150
1150...1650
1650...2200
15
10
10 (cer.) +33 (electr.)
3 × 10 (cer.)
60
40
40
95
95
70
43
79
300
0
4.7
3 × 10 (cer.)
145
0
(1) Parameters are for reference only.
(2) Due to current sensing comparator delay the actual minimum off time is 6 ns (typical) longer than in the table.
Boost SW pin DC current is limited to 2 A (typical). To support warm start transient condition the current limit is
automatically increased to 2.5 A for a short period of 1.5 seconds when a 2-A limit is reached.
NOTE
Application condition where the 2-A limit is exceeded continuously is not allowed. In this
case the current limit would be 2 A for 1.5 seconds followed by 2.5-A limit for 1.5 seconds,
and this 3-second period repeats.
To keep switching voltage within safe levels there is a 48-V limit comparator in the event that FB loop is broken.
8.3.2 Internal LDO
The internal LDO regulator converts the input voltage at VIN to a 4.3-V output voltage. The LDO regulator
supplies internal and external circuitry. The maximum external load is 5 mA. Connect LDO output with a
minimum of 1-µF ceramic capacitor to ground as close to the LDO pin as possible. If an external voltage higher
than 4.5 V is connected to LDO pin, the internal LDO is disabled, and the internal circuitry is powered from the
external power supply. VIN and VSENSE_N pins must be connected to the same external voltage as LDO pin.
See Figure 29 for application schematic example.
8.3.3 LED Current Sinks
8.3.3.1 Current Sink Configuration
The LP8861-Q1 detects LED current sinks configuration during start-up. Any sink connected to the ground is
disabled and excluded from the adaptive boost control and fault detection.
8.3.3.2 Current Setting
Maximum current for the LED current sinks is controlled with external RISET resistor. RISET value for target
maximum current can be calculated using Equation 3:
RISET = 2342 / (IOUT œ 2.5)
where
•
•
RISET is current setting resistor, kΩ
IOUT is output current per output, mA
(3)
8.3.3.3 Brightness Control
The LP8861-Q1 controls the brightness of the display with conventional PWM. Output PWM directly follows the
input PWM. Input PWM frequency can be in the range of 100 Hz to 20 kHz.
8.3.4 Power-Line FET Control
The LP8861-Q1 has a control pin (SD) for driving the gate of an external power-line FET. Power-line FET is an
optional feature; an example schematic is shown in Figure 24. Power-line FET limits inrush current by turning on
gradually when the device is enabled (VDDIO/EN = high, VIN > VGS). Inrush current is controlled by increasing
sink current for the FET gradually to 230 μA.
16
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In shutdown the LP8861-Q1 turns off the power-line FET and prevents the possible boost and LEDs leakage.
The power switch also turns off in case of any fault which causes the device to enter FAULT RECOVERY state.
8.3.5 LED Current Dimming With External Temperature Sensor
The LP8861-Q1 has an optional feature to decrease automatically LED current when LED overheating is
detected with an external NTC sensor. An example of the behavior is shown in Figure 11. When the NTC
temperature reaches T1, the LP8861-Q1 starts to decrease the LED current. When the LED current has reduced
to 17.5% of the nominal value, current turns off until temperature returns to the operation range. When TSET pin
is grounded this feature is disabled. Temperature T1 and de-rate slope are defined by external resistors as
explained below.
100%
17.5%
T1
T2
AMBIENT TEMPERATURE
Figure 11. Temperature-Based LED Current Dimming Functionality
VBG
ISET_SCALED
1:2000
ISET
+
LED OUT
RISET
VDD
R2
-
ILED
ITSENSE
LED DRIVER
R1
RT
TSET
TSENSE
R5
ITSENSE
R3
R4
NTC
Figure 12. Temperature-Based LED Current Dimming Implementation
When the TSET pin is grounded LED current is set by RISET resistor:
RISET = 2342 / (IOUT œ 2.5)
(4)
When external NTC is connected, the TSENSE pin current decreases LED output current. The following steps
describe how to calculate LED output current.
Parallel resistance of the NTC sensor RT and resistor R4 is calculated by formula:
RT ìR4
RT + R4
RII =
(5)
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TSET voltage can be calculated with Equation 6:
R3
VTSET = VDD
ì
R2 + R3
(6)
TSENSE pin current is calculated by Equation 7:
RII
VTSET - VDD
RII + R5 -
ì
RII + R1
2
ITSENSE
=
RII
RII + R1
(7)
(8)
ISET pin current defined by RISET is:
VBG
ISET _ SCALED
=
RISET
For Equation 9, ITSENSE current must be limited between 0 and ISET_SCALED. If ITSENSE > ISET_SCALED then set
ITSENSE = ISET_SCALED. If ITSENSE < 0 then set ITSENSE = 0.
LED driver output current is:
ILED = (ISET_SCALED – ITSENSE ) x 2 000
(9)
When current is lower than 17.5% of the nominal value, the current is set to 0 (so called cut-off point).
An Excel® calculator is available for calculating the component values for a specific NTC and target thermal
profile (contact your local TI representative). Figure 13 shows an example thermal profile implementation.
120
100
80
60
40
20
0
0.06
0.05
0.04
0.03
0.02
0.01
0.00
LED current
TSENSE current
70
60
80
90
100
110
120
Temperature (ºC)
C006
NTC – 10 kΩ at 25ºC
RISET = 24 kΩ
R1 = 10 kΩ
R2 = 10 kΩ
R3 = 2 kΩ
R4 = 100 kΩ
R5 = 7.5 kΩ
VDD = 4.3 V
Figure 13. Calculation Example
8.3.6 Protection and Fault Detection
The LP8861-Q1 has fault detection for LED open and short, VIN input overvoltage (VIN_OVP), VIN undervoltage
lockout (VIN_UVLO), power line overcurrent (VIN_OCP), and thermal shutdown (TSD).
18
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8.3.6.1 Adaptive Boost Control and Functionality of LED Fault Comparators
Adaptive boost control function adjusts the boost output voltage to the minimum sufficient voltage for proper LED
current sink operation. The output with highest VF LED string is detected and boost output voltage adjusted
accordingly. Boost adaptive control voltage step size is defined by maximum boost voltage settings, VSTEP
=
(VMAX BOOST - VMIN BOOST) / 256. Periodic down pressure is applied to the target boost voltage to achieve better
system efficiency.
Every LED current sink has 3 comparators for an adaptive boost control and fault detection. Comparator outputs
are filtered, filtering time is 1 µs.
OUT#
SHORT STRING
DETECTION LEVEL
HIGH_COMP
VOLTAGE THRESHOLD
MID_COMP
LOWEST VOLTAGE
LOW_COMP
CURRENT/PWM
CONTROL
Figure 14. Comparators for Adaptive Voltage Control and LED Fault Detection
Figure 15 illustrates different cases which cause boost voltage increase, decrease, or generate faults. In normal
operation, voltage at all the OUT# pins is between LOW_COMP and MID_COMP levels and boost voltage stays
constant. LOW_COMP level is the minimum for proper LED current sink operation, 1.1 × VSAT + 0.2 V (typical).
MID_COMP level is 1.1 × VSAT + 1.2 V (typical) — that is, typical headroom window is 1 V.
When voltage at all the OUT# pins increases above MID_COMP level, boost voltage adapts downwards.
When voltage at any of the OUT# pins falls below LOW_COMP threshold, boost voltage adapts upwards. In the
condition where boost voltage reaches the maximum and there are one or more outputs still below LOW_COMP
level, an open LED fault is detected.
HIGH_COMP level, 6 V typical, is the threshold for shorted LED detection. When the voltage of one or more of
the OUT# pins increases above HIGH_COMP level and at least one of the other outputs is within the normal
headroom window, shorted LED fault is detected.
Shorted LED fault (at
Boost
decreases
voltage
Boost
increases
voltage
least one output should
be between LOW_COMP
and MID_COMP)
Open LED fault when
VBOOST = VSET BOOST MAX
No actions
No actions
Shorted
LED fault
Minimum
headroom
level reached
All outputs are
above headroom
window
Open LED
fault
HIGH_COMP
MID_COMP
HEADROOM
WINDOW
LOW_COMP
Figure 15. Boost Adaptation and LED Protection Algorithms
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8.3.6.2 Overview of the Fault/Protection Schemes
The LP8861-Q1 fault detection behavior is described in Table 3. Detected faults (excluding LED faults) cause the
device to enter FAULT_RECOVERY state. In FAULT_RECOVERY the boost and LED outputs of LP8861-Q1 are
disabled, power-line FET is turned off, and the FAULT pin is pulled low. Device recovers automatically and
enters normal operating mode (ACTIVE) after a recovery time of 100 ms if the fault condition has disappeared.
When recovery is successful, the FAULT pin is released.
In case a LED fault is detected, device continues normal operation and only the faulty string is disabled. Fault is
indicated via FAULT pin which can be released by toggling VDDIO/EN pin low for a short period of 2…20 µs.
LEDs are turned off for this period but device stays in ACTIVE mode. If VDDIO/EN is low longer, device goes to
STANDBY and restarts when EN goes high again.
Table 3. Fault/Protection Schemes
FAULT_
RECOVERY
STATE
FAULT/
PROTECTION
CONNECTED TO
FAULT PIN
FAULT NAME
THRESHOLD
ACTION
1. Overvoltage is monitored from the beginning of soft start. Fault is
detected if the duration of overvoltage condition is 100 µs minimum.
2. Overvoltage is monitored from the beginning of normal operation
(ACTIVE mode). Fault is detected if overvoltage condition duration is
560 ms minimum (tfilter). After the first fault detection filter time is
reduced to 50 ms for following recovery cycles. When device
recovers and has been in ACTIVE mode for 160 ms, filter is
increased back to 560 ms.
1. VIN > 42 V
2. VBOOST > VSET_BOOST + (6...10)
V
VSET_BOOST is voltage value
defined by logic during
adaptation
VIN overvoltage
protection
VIN_OVP
Yes
Yes
Detects undervoltage condition at VIN pin. Sensed from the
beginning of soft start. Fault is detected if undervoltage condition
duration is 100 µs minimum.
VIN undervoltage
lockout
Falling 3.9 V
Rising 4 V
VIN_UVLO
VIN_OCP
Yes
Yes
Yes
Yes
Detects overcurrent by measuring voltage of the SENSE resistor
connected between VIN and VSENSE_N pins. Sensed from the
beginning of soft start. Fault is detected if undervoltage condition
duration is 10 µs minimum.
VIN overcurrent
protection
3 A (50-mΩ current sensor
resistor)
Detected if one or more outputs are below threshold level, and boost
adaptive control has reached maximum voltage. Open string(s) is
removed from voltage control loop and PWM is disabled.
Open LED fault
OPEN_LED
LOW_COMP threshold
Yes
No
Fault pin is cleaned by toggling VDDIO/EN pin. If VDDIO/EN is low
for a short period of 2…20 µs, LEDs are turned off for this period but
device stays ACTIVE. If VDDIO/EN is low longer, device goes to
STANDBY and restarts when EN goes high again.
Detected if one or more outputs voltages are above shorted string
detection level and at least one LED output voltage is within
headroom window. Shorted string(s) are removed from the boost
voltage control loop and outputs PWM(s) are disabled.
Fault pin is cleaned by toggling VDDIO/EN pin. If VDDIO/EN is low
for a short period of 2…20 µs, LEDs are turned off for this period but
device stays ACTIVE. If VDDIO/EN is low longer, device goes to
STANDBY and restarts when EN goes high again.
Shorted LED fault
SHORT_LED
Shorted string detection level 6 V
Yes
Yes
No
165ºC
Thermal Shutdown Hysteresis
20ºC
Thermal
protection
Thermal shutdown is monitored from the beginning of soft start. Die
temperature must decrease by 20ºC for device to recover.
TSD
Yes
20
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Time is not enough to
discharge COUT
VIN OVERVOLTAGE
VIN OK
VIN
VBOOST
VSET_BOOST +6...10 V
Powerline
FET state
ON
OFF
ON
OFF
ON
OFF
ON
IOUT
FAULT
tFILTER = 560 ms
tRECOVERY
100 ms
=
tSOFTSTART
tBOOST START
+
tFILTER
50 ms
=
tRECOVERY
100 ms
=
tSOFTSTART
tBOOST START 40 - 50 ms
+
tFILTER
=
tRECOVERY
100 ms
=
tSOFTSTART + tFILTER =
tBOOST START 50 ms
Figure 16. VIN Overvoltage Protection (Boost OVP)
VIN OVP threshold
VIN
BOOST OVP threshold
FB
Powerline
FET state
ON
OFF
ON
ttSOFTSTART +t
ttBOOST STARTUP
FAULT
ttRECOVERY = 100 mst
ttRECOVERY = 100 mst
t
Figure 17. VIN Overvoltage Protection (VIN OVP)
UVLO rising threshold
UVLO falling threshold
VIN
FB
Powerline
FET state
ON
OFF
ON
ttSOFTSTART +t
ttBOOST STARTUP
FAULT
ttRECOVERY = 100 mst
ttRECOVERY = 100 mst
t
Figure 18. VIN Undervoltage Lockout
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3 A @ 50 mꢀ
IIN
FB
Powerline
FET state
ON
OFF
ON
OFF
ttSOFTSTART +t
ttBOOST STARTUP
ttRECOVERY = 100 mst
ttRECOVERY = 100 mst
t
FAULT
Figure 19. Input Voltage Overcurrent Protection
VBOOST SET MAX LEVEL
VBOOST
VOUT
OTHER LEDs
VOUT
OPEN LED
LOW_COMP level
t = 2...20 µs
VDDIO/EN
FAULT
Figure 20. LED Open Fault
MID_COMP level
LOW_COMP level
VOUT OTHER
VOUT
SHORTED LED
HIGH_COMP level
t = 2...20 µs
VDDIO/EN
FAULT
Figure 21. LED Short Fault
22
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8.4 Device Functional Modes
8.4.1 Device States
The LP8861-Q1 enters STANDBY mode when the internal LDO output rises above the power-on reset level,
VLDO > VPOR_R. In STANDBY mode device is able to detect the VDDIO/EN signal. When VDDIO/EN is pulled
high, device powers up. During soft start the external power line FET is opened gradually to limit inrush current.
Soft start is followed by boost start, during which time boost voltage is ramped to the initial value. After boost
start LED outputs are sensed to detect grounded current sinks. Grounded current sinks are disabled and
excluded from the boost voltage control loop.
If a fault condition is detected, the LP8861-Q1 enters FAULT_RECOVERY state. In this state power line FET is
switched off and both the boost and LED current sinks are disabled. Fault that cause the device to enter
FAULT_RECOVERY are listed in Figure 22. When LED open or short is detected, faulty string is disabled but
LP8861-Q1 stays in ACTIVE mode.
POR = 1
STANDBY
VDDIO / EN = 1
100 ms
VIN_OCP
VIN_OVP
VIN_UVLO
SOFT START
65 ms
50 ms
TSD
FAULT RECOVERY
BOOST START
FAULTS
VDDIO / EN = 0
FAULTS:
NO
FAULT
RECOVERY?
FAULTS
- VIN_OCP
- VIN_OVP
- VIN_UVLO
- TSD
LED OUTPUT
CONFIGURATION
DETECTION
YES
ACTIVE
BOOST, LED CURRENT SINKS
AND POWER LINE FET ARE
DISABLED IN FAULT RECOVERY
STATE
VDDIO / EN = 0
SHUTDOWN
Figure 22. State Diagram
Copyright © 2015–2017, Texas Instruments Incorporated
23
LP8861-Q1
ZHCSE41C –AUGUST 2015–REVISED MAY 2017
www.ti.com.cn
Device Functional Modes (continued)
t > 500 ꢀs
T = 50 ꢀs
VIN
LDO
VDDIO/EN
SYNC
PL pFET drain
Headroom adaptation
VOUT = VIN level œ diode drop
VBOOST
PWM OUT
IQ
Active mode
SOFT
tSTARTt
tBOOSTt
START
Figure 23. Timing Diagram for the Typical Start-Up and Shutdown
24
Copyright © 2015–2017, Texas Instruments Incorporated
LP8861-Q1
www.ti.com.cn
ZHCSE41C –AUGUST 2015–REVISED MAY 2017
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LP8861-Q1 is designed for automotive applications, and an input voltage VIN is intended to be connected to
the car battery. Device circuitry is powered from the internal LDO which, alternatively, can be used as external
VDD voltage — in that case, external voltage must be in the 4.5-V to 5.5-V range.
The LP8861-Q1 uses a simple four-wire control:
•
•
•
•
VDDIO/EN for enable
PWM input for brightness control
SYNC pin for boost synchronisation (optional)
FAULT output to indicate fault condition (optional)
9.2 Typical Applications
9.2.1 Typical Application for 4 LED Strings
Figure 24 shows the typical application for LP8861-Q1 which supports 4 LED strings with maximum current 100
mA and boost switching frequency of 300 kHz.
VIN
4.5...28 V
RISENSE
Q1
L1
D1
Up to 37 V
CIN BOOST
COUT
RGS
R2
R1
SW
SD
VSENSE_N
VIN
FB
CFB
CIN
Up to 100 mA/string
LDO
CLDO
OUT1
LP8861-Q1
OUT2
OUT3
RFSET
FSET
SYNC
PWM
OUT4
BRIGHTNESS
TSET
TSENSE
ISET
EN
VDDIO/EN
FAULT
FAULT
RISET
R3
VDDIO
PGND GND
PAD
Figure 24. Typical Application for Four Strings 100 mA/String Configuration
Copyright © 2015–2017, Texas Instruments Incorporated
25
LP8861-Q1
ZHCSE41C –AUGUST 2015–REVISED MAY 2017
www.ti.com.cn
Typical Applications (continued)
9.2.1.1 Design Requirements
DESIGN PARAMETER
VALUE
VIN voltage range
4.5…28 V
LED string
4 x 8 LEDs (30 V)
LED string current
100 mA
Max boost voltage
37 V
Boost switching frequency
300 kHz
External boost sync
not used
Boost spread spectrum
enabled
L1
CIN
33 μH
10 µF 50 V
CIN BOOST
COUT
CLDO
CFB
2 × 10-µF, 50-V ceramic + 33-µF, 50-V electrolytic
2 × 10-µF, 50-V ceramic + 33-µF, 50-V electrolytic
1 µF 10 V
15 pF
RISET
RFSET
RISENSE
R1
24 kΩ
210 kΩ
50 mΩ
750 kΩ
130 kΩ
10 kΩ
R2
R3
RGS
20 kΩ
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Inductor Selection
There are two main considerations when choosing an inductor; the inductor must not saturate, and the inductor
current ripple must be small enough to achieve the desired output voltage ripple. Different saturation current
rating specifications are followed by different manufacturers so attention must be given to details. Saturation
current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of
application should be requested from the manufacturer. Shielded inductors radiate less noise and are preferred.
The saturation current must be greater than the sum of the maximum load current and the worst-case average to
peak inductor current. Equation 10 shows the worst-case conditions:
IOUTMAX
ISAT
>
+ IRIPPLE
For Boost
D‘
VIN
x
(VOUT - VIN)
(2 x L x f)
Where IRIPPLE
=
VOUT
(VOUT œ VIN)
and D‘ = (1 - D)
Where D =
(VOUT
)
•
•
•
•
•
•
•
•
IRIPPLE - peak inductor current
IOUTMAX - maximum load current
VIN - minimum input voltage in application
L - min inductor value including worst case tolerances
ƒ - minimum switching frequency
VOUT - output voltage
D - Duty Cycle for CCM Operation
VOUT - Output Voltage
(10)
26
Copyright © 2015–2017, Texas Instruments Incorporated
LP8861-Q1
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ZHCSE41C –AUGUST 2015–REVISED MAY 2017
As a result the inductor should be selected according to the ISAT. A more conservative and recommended
approach is to choose an inductor that has a saturation current rating greater than the maximum current limit. A
saturation current rating at least 3 A is recommended for most applications. See Table 2 for inductance
recommendation for the different switch frequency ranges. The inductor’s resistance should be less than 300 mΩ
for good efficiency.
See detailed information in Understanding Boost Power Stages in Switch Mode Power Supplies (SLVA061).
Power Stage Designer™ Tools can be used for the boost calculation: http://www.ti.com/tool/powerstage-
designer.
9.2.1.2.2 Output Capacitor Selection
A ceramic and electrolytic capacitors should have sufficient voltage rating. The DC-bias effect in ceramic
capacitors can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance
value selection. Capacitance recommendation for different switching frequency range is shown in Table 2. To
minimize audible of noise ceramic capacitors their geometric size is usually minimized.
9.2.1.2.3 Input Capacitor Selection
A ceramic and electrolytic capacitors should have sufficient voltage rating. The DC-bias effect in ceramic
capacitors can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance
value selection. Capacitance recommendation for different switching frequency range is shown in Table 2. To
minimize audible of noise ceramic capacitors their geometric size is usually minimized.
9.2.1.2.4 LDO Output Capacitor
A ceramic capacitor with at least 10-V voltage rating is recommended for the output capacitor of the LDO. The
DC-bias effect in ceramic capacitors can reduce the effective capacitance by up to 80%, which needs to be
considered in capacitance value selection. Typically a 1-µF capacitor is sufficient.
9.2.1.2.5 Diode
A Schottky diode should be used for the boost output diode. Ordinary rectifier diodes should not be used,
because slow switching speeds and long recovery times degrade the efficiency and the load regulation. Diode
rating for peak repetitive current should be greater than inductor peak current (up to 3 A) to ensure reliable
operation. Average current rating should be greater than the maximum output current. Schottky diodes with a low
forward drop and fast switching speeds are ideal for increasing efficiency. Choose a reverse breakdown voltage
of the Schottky diode significantly larger than the output voltage.
9.2.1.2.6 Power Line Transistor
A pFET transistor with necessary voltage rating (VDS at least 5 V higher than max input voltage) should be used.
Current rating for the FET should be the same as input peak current or greater. Transfer characteristic is very
important for pFET. VGS for open transistor must be less than VIN. A 20-kΩ resistor between pFET gate and
source is sufficient.
9.2.1.2.7 Input Current Sense Resistor
A high-power 50-mΩ resistor should be used for sensing the boost input current. Power rating can be calculated
from the input current and sense resistor resistance value. Increasing RISENSE decreases VIN OCP current
proportionally.
Copyright © 2015–2017, Texas Instruments Incorporated
27
LP8861-Q1
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www.ti.com.cn
9.2.1.3 Application Curves
SD 2V/div
VBOOST 10V/div
IBOOST 200mA/div
VDDIO/EN 5 V/div
20ms/div
OUT1/OUT2/BOOST 10V/div
FAULT 2V/div
40ms/div
ƒSW = 300 kHz
VIN = 10 V
Brightness PWM 50% 100 Hz
Figure 26. Open LED Fault
Figure 25. Typical Start-up
100
95
90
85
80
75
70
65
100
95
90
85
80
75
70
65
VIN=5V
VIN=8V
VIN=12V
VIN=16V
VIN=5V
VIN=8V
VIN=12V
VIN=16V
0
20
40
60
80
100
0
20
40
60
80
100
Brightness (%)
Brightness (%)
C011
C012
Load 4 strings, 8 LED per string
I = 100 mA/string for VIN = 12 V and 16 V
I = 60 mA/sting for VIN = 8 V
ƒSW= 300 kHz
Load 4 strings, 8 LED per string
I = 100 mA/string for VIN = 12 V and VIN = 16 V
I = 60 mA/sting for VIN = 8 V
ƒSW = 300 kHz
I = 50 mA/string for VIN = 5 V
I = 50 mA/string for VIN = 5 V
Figure 27. Boost Efficiency
Figure 28. System Efficiency
9.2.2 High Output Current Application
The LP8861-Q1 current sinks can be tied together to drive LED with higher current. To drive 200 mA per string 2
outputs can be connected together. All 4 outputs connected together can drive an up to 400-mA LED string.
Device circuitry is powered from external VDD voltage.
28
Copyright © 2015–2017, Texas Instruments Incorporated
LP8861-Q1
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ZHCSE41C –AUGUST 2015–REVISED MAY 2017
VIN
4.5...28 V
Q1
L1
D1
Up to 37 V
CIN
CIN BOOST
COUT
R2
R1
SW
SD
VSENSE_N
VIN
FB
CFB
VDD 5 V
Up to 200 mA/string
LDO
CLDO
OUT1
LP8861-Q1
OUT2
OUT3
RFSET
FSET
SYNC
PWM
OUT4
BRIGHTNESS
TSET
TSENSE
ISET
EN
VDDIO/EN
FAULT
FAULT
RISET
R3
PGND GND
PAD
VDDIO
Figure 29. Two Strings 200 mA/String Configuration
9.2.2.1 Design Requirements
DESIGN PARAMETER
VALUE
4.5…28 V
2 × 8 LEDs (30 V)
200 mA
VIN voltage range
LED string
LED string current
Max boost voltage
37 V
Boost switching frequency
2.2 MHz
External boost sync
not used
Boost spread spectrum
disabled
L1
CIN
4.7 μH
10 µF 50 V
2 × 10-µF, 50-V ceramic
3 × 10-µF, 50-V ceramic
1 µF 10 V
4.7 pF
CIN BOOST
COUT
CLDO
CFB
RISET
RFSET
R1
24 kΩ
24 kΩ
750 kΩ
R2
130 kΩ
R3
10 kΩ
RGS
20 kΩ
9.2.2.2 Detailed Design Procedure
See Detailed Design Procedure.
9.2.2.3 Application Curves
See Application Curves.
Copyright © 2015–2017, Texas Instruments Incorporated
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LP8861-Q1
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www.ti.com.cn
9.2.3 SEPIC Mode Application
When LED string voltage can be above or below VIN voltage, SEPIC configuration can be used. The SW pin
voltage is equal to the sum of the input voltage and output voltage in SEPIC mode — this fact limits the
maximum input voltage in this mode. LED current sinks not used should be connected to ground. External
frequency can be used to synchronize boost/SEPIC switching frequency, and external frequency can be
modulated to spread switching frequency spectrum.
RISENSE
Q1
D1
VIN
L1
CIN SEPIC
C1
COUT
RGS
R2
R1
SW
SD
VSENSE_N
VIN
FB
CIN
Up to 100 mA/string
LDO
CLDO
OUT1
LP8861-Q1
RFSET
OUT2
OUT3
FSET
BOOST SYNC
BRIGHTNESS
SYNC
PWM
OUT4
TSET
EN
VDDIO/EN
FAULT
TSENSE
ISET
FAULT
R3
VDDIO
PGND GND
PAD
RISET
Figure 30. SEPIC Mode, 4 Strings 100 mA/String Configuration
30
Copyright © 2015–2017, Texas Instruments Incorporated
LP8861-Q1
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ZHCSE41C –AUGUST 2015–REVISED MAY 2017
9.2.3.1 Design Requirements
DESIGN PARAMETER
VALUE
VIN voltage range
4.5…30 V
LED string
4 × 4 LEDs (14.5 V)
LED string current
100 mA
Max boost voltage
17.5 V
Boost switching frequency
300 kHz
External boost sync
used
Boost spread spectrum
not available with external sync
L1
CIN
33 μH
10 µF 50 V
CIN SEPIC
C1
2 × 10-µF, 50-V ceramic + 33-µF 50-V electrolytic
10-µF 50-V ceramic
COUT
CLDO
RISET
RFSET
RISENSE
R1
2 × 10-µF, 50-V ceramic + 33-µF 50-V electrolytic
1 µF 10 V
24 kΩ
210 kΩ
50 mΩ
390 kΩ
130 kΩ
10 kΩ
R2
R3
RGS
20 kΩ
9.2.3.2 Detailed Design Procedure
See Detailed Design Procedure for external component recommendations. The Power Stage Designer™ Tools
can be use for defining SEPIC component current and voltage ratings according to application:
http://www.ti.com/tool/powerstage-designer
9.2.3.2.1 Diode
A Schottky diode with a low forward drop and fast switching speed should be used for the SEPIC output diode.
Do not use ordinary rectifier diodes, because slow switching speeds and long recovery times degrade the
efficiency and load regulation. The diode must be able to handle peak repetitive current greater than the
integrated FET peak current (SW pin limit), thus 3 A or higher must be used to ensure reliable operation.
Average current rating should be greater than the maximum output current. Choose a diode with reverse
breakdown larger than the sum of input voltage and output voltage.
9.2.3.2.2 Inductor
Coupled or uncoupled inductors can be used in SEPIC mode. Coupled inductor typically provides better
efficiency. Power Stage Designer™ Tools can be used for the SEPIC inductance calculation:
http://www.ti.com/tool/powerstage-designer.
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LP8861-Q1
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www.ti.com.cn
9.2.3.3 Application Curves
100
95
90
85
80
75
70
65
100
95
90
85
80
75
70
65
VIN=8V
VIN=12V
VIN=14V
VIN=18V
VIN=8V
VIN=12V
VIN=14V
VIN=18V
0
20
40
60
80
100
0
20
40
60
80
100
Brightness (%)
Brightness (%)
C016
C015
Load 4 strings, 4 LED per string
I = 100 mA/string
ƒSW = 300 kHz
Load 4 strings, 4 LED per string
I = 100 mA/string
ƒSW = 300 kHz
Figure 32. System Efficiency
Figure 31. SEPIC Efficiency
9.2.4 Application with Temperature Based LED Current De-rating
The LP8881-Q1 is able to protect connected LED strings from overheating. LED current versus temperature
behavior can be adjusted with external resistor as described in LED Current Dimming With External Temperature
Sensor.
VIN
4.5...30 V
RISENSE
Q1
L1
D1
Up to 43 V
CIN BOOST
COUT
RGS
R2
R1
SW
SD
VSENSE_N
VIN
FB
CFB
VLDO
CIN
Up to 50 mA/string
LDO
CLDO
OUT1
LP8861-Q1
OUT2
OUT3
RFSET
FSET
SYNC
PWM
VLDO
R4
OUT4
BRIGHTNESS
R3
RTº
TSET
TSENSE
ISET
R7
EN
VDDIO/EN
FAULT
FAULT
R6
R5
R8
VDDIO
NTC
PGND GND
PAD
RISET
Figure 33. Temperature Based LED Current De-rating
32
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LP8861-Q1
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ZHCSE41C –AUGUST 2015–REVISED MAY 2017
9.2.4.1 Design Requirements
DESIGN PARAMETER
VALUE
VIN voltage range
4.5…30 V
LED string
4 × 9 LEDs (33 V)
LED string current
50 mA
Max boost voltage
43 V
Boost switching frequency
400 kHz
External boost sync
not used
Boost spread spectrum
enabled
L1
CIN
33 μH
10-µF 50-V ceramic
CIN BOOST
COUT
CLDO
CFB
2 × 10-µF, 50-V ceramic + 33-µF, 50-V electrolytic
2 × 10-µF, 50-V ceramic + 33-µF, 50-V electrolytic
1 µF 10 V
15 pF
RISET
RFSET
RISENSE
R1
48 kΩ
160 kΩ
50 mΩ
866 kΩ
130 kΩ
12 kΩ
R2
R3
R4
10 kΩ
R5
1.8 kΩ
R6
82 kΩ
R7
16 kΩ
R8
10 kΩ
RT
10 kΩ @ 25°C
20 kΩ
RGS
9.2.4.2 Detailed Design Procedure
See Detailed Design Procedure.
9.2.4.3 Application Curve
60
50
40
30
20
10
0
60
65
70
75
80
85
90
95
100
105
110
Temperature (ºC)
C007
Figure 34. LED Current vs Temperature
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LP8861-Q1
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www.ti.com.cn
10 Power Supply Recommendations
The LP8861-Q1 device is designed to operate from a car battery. The device should be protected from reverse
voltage polarity and voltage dump over 50 V. The resistance of the input supply rail must be low enough so that
the input current transient does not cause too high drop at the LP8861-Q1 VIN pin. If the input supply is
connected by using long wires additional bulk capacitance may be required in addition to the ceramic bypass
capacitors in the VIN line.
11 Layout
11.1 Layout Guidelines
Figure 35 is a layout recommendation for the LP8861-Q1 used to demonstrate the principles of good layout. This
layout can be adapted to the actual application layout if or where possible. It is important that all boost
components are close to the chip, and the high current traces must be wide enough. By placing boost
components on one side of the chip it is easy to keep the ground plane intact below the high current paths. This
way other chip pins can be routed more easily without splitting the ground plane. Bypass LDO capacitor must as
close as possible to the device.
Here are some main points to help the PCB layout work:
•
Current loops need to be minimized:
–
For low frequency the minimal current loop can be achieved by placing the boost components as close as
possible to the SW and PGND pins. Input and output capacitor grounds need to be close to each other to
minimize current loop size
–
Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact
under the current traces. High-frequency return currents try to find route with minimum impedance, which
is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when
return current flows just under the positive current route in the ground plane, if the ground plane is intact
under the route
•
•
•
•
GND plane needs to be intact under the high current boost traces to provide shortest possible return path and
smallest possible current loops for high frequencies.
Current loops when the boost switch is conducting and not conducting need to be on the same direction in
optimal case.
Inductors must be placed so that the current flows in the same direction as in the current loops. Rotating
inductor 180° changes current direction.
Use separate power and noise-free grounds. Power ground is used for boost converter return current and
noise-free ground for more sensitive signals, like LDO bypass capacitor grounding as well as grounding the
GND pin of the device itself.
•
Boost output feedback voltage to LEDs need to be taken out after the output capacitors, not straight from the
diode cathode.
•
•
•
•
Place LDO 1-µF bypass capacitor as close as possible to the LDO pin.
Input and output capacitors need strong grounding (wide traces, many vias to GND plane).
If two output capacitors are used they need symmetrical layout to get both capacitors working ideally.
Output ceramic capacitors have DC-bias effect. If the output capacitance is too low, it can cause boost to
become unstable on some loads; this increases EMI. DC bias characteristics need to be obtained from the
component manufacturer; DC bias is not taken into account on component tolerance. X5R/X7R capacitors are
recommended.
34
Copyright © 2015–2017, Texas Instruments Incorporated
LP8861-Q1
www.ti.com.cn
ZHCSE41C –AUGUST 2015–REVISED MAY 2017
11.2 Layout Example
RISENSE
VIN
RGS
1
2
VIN
VSENSE_N
SD
20
19
18
17
16
15
14
13
12
11
LDO
LDO
FSET
RFSET
3
SW
VDDIO/EN
4
PGND
FB
FAULT
SYNC
5
6
OUT1
OUT2
OUT3
OUT4
GND
VBOOST
PWM
7
TSENSE
8
TSET
RISET
9
10
ISET
Figure 35. LP8861-Q1 Layout
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35
LP8861-Q1
ZHCSE41C –AUGUST 2015–REVISED MAY 2017
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.2 文档支持
12.2.1 相关文档
更多信息，请参见以下文档：
•
•
•
•
《使用 LP8861-Q1EVM 评估模块》
《PowerPAD™ 耐热增强型封装应用手册》
德州仪器 (TI) 应用手册《了解开关模式电源中的升压功率级》
《Power Stage Designer™ 工具》，http://www.ti.com.cn/tool/cn/powerstage-designer
12.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.5 商标
E2E is a trademark of Texas Instruments.
Excel is a registered trademark of Microsoft Corporation.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
36
版权 © 2015–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
20-May-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP8861QPWPRQ1
ACTIVE
HTSSOP
PWP
20
2000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LP8861Q
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP8861QPWPRQ1
HTSSOP PWP
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 20
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
LP8861QPWPRQ1
2000
Pack Materials-Page 2
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