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LP8867-Q1 [TI]

具有电力线 FET 保护的高集成度 4 通道 120mA 汽车类 LED 驱动器;
LP8867-Q1
型号： LP8867-Q1
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

具有电力线 FET 保护的高集成度 4 通道 120mA 汽车类 LED 驱动器

驱动 驱动器
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LP8867-Q1, LP8869-Q1  
SNVSB83B –JUNE 2019–REVISED JANUARY 2020  
LP8867-Q1, LP8869-Q1 Low EMI Automotive LED Driver with 4-, 3- Channels  
1 Features  
2 Applications  
1
•
AEC-Q100 Qualified for automotive applications:  
•
Backlight for:  
–
Device temperature grade 1:  
–40°C to +125°C, TA  
–
–
–
–
Automotive infotainment  
Automotive instrument clusters  
Smart mirrors  
•
•
Functional safety capable  
–
Documentation available to aid functional  
safety system design  
Heads-up displays (HUD)  
3-, 4-Channel 120-mA current sinks  
3 Description  
The LP8867-Q1, LP8869-Q1 is an automotive highly-  
integrated, low-EMI, easy-to-use LED driver with DC-  
DC converter. The DC-DC converter supports both  
boost and SEPIC mode operation. The device has  
four or three high-precision current sinks that can be  
combined for higher current capability.  
–
–
–
–
High dimming ratio of 10 000:1 at 100 Hz  
Current matching 1% (typical)  
LED String current up to 120 mA per channel  
Outputs can be combined externally for higher  
current per string  
•
Integrated boost and SEPIC converter for LED  
string power  
The DC-DC converter has adaptive output voltage  
control based on the LED forward voltages. This  
feature minimizes the power consumption by  
adjusting the voltage to the lowest sufficient level in  
all conditions. For EMI reduction DC-DC supports  
spread spectrum for switching frequency and an  
external synchronization with dedicated pin. A wide-  
range adjustable frequency allows the LP886x-Q1 to  
avoid disturbance for sensitive frequency band.  
–
–
–
–
–
–
Input voltage operating range 4.5 V to 40 V  
Output voltage up to 45 V  
Integrated 3.3-A Switch FET  
Switching frequency 300 kHz to 2.2 MHz  
Switching synchronization input  
Spread spectrum for lower EMI  
The input voltage range for the LP886x-Q1 is from  
4.5 V to 40 V to support automotive start-stop and  
load dump condition. The LP886x-Q1 integrates  
extensive fault detection features.  
•
Fault detection and protection  
–
–
–
–
–
Fault output  
Input voltage OVP, UVLO and OCP  
Boost block SW OVP and output OVP  
LED open and short fault detection  
Device Information(1)  
PART NUMBER  
LP8867-Q1  
PACKAGE  
BODY SIZE (NOM)  
Power-Line FET control for battery bus  
protection  
HTSSOP (20)  
6.50 mm × 4.40 mm  
LP8869-Q1  
–
–
Automatic LED current reduction with external  
temperature sensor  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
Thermal shutdown  
Simplified Schematic  
LED Backlight Efficiency  
VIN  
4.5...40 V  
RISENSE  
Q1  
D1  
L1  
Up to 45 V  
100  
96  
92  
88  
84  
80  
CIN BOOST  
COUT  
RGS  
R2  
R1  
SW  
SD  
VSENSE_N  
VIN  
FB  
CFB  
VLDO  
CIN  
Up to 120 mA/string  
LDO  
CLDO  
OUT1  
LP8867-Q1  
OUT2  
OUT3  
RFSET  
76  
FSET  
SYNC  
PWM  
VLDO  
R4  
VIN = 16V  
VIN = 12V  
VIN = 8V  
VIN = 6V  
OUT4  
72  
BRIGHTNESS  
R3  
RTº  
TSET  
TSENSE  
ISET  
R7  
EN  
68  
80  
VDDIO/EN  
FAULT  
160  
240 320  
Output Current (mA)  
400  
480  
FAULT  
R6  
D000  
R5  
R8  
VDDIO  
NTC  
PGND GND  
PAD  
RISET  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
LP8867-Q1, LP8869-Q1  
SNVSB83B –JUNE 2019–REVISED JANUARY 2020  
www.ti.com  
Table of Contents  
8.1 Overview ................................................................. 11  
8.2 Functional Block Diagram ....................................... 12  
8.3 Feature Description................................................. 13  
8.4 Device Functional Modes........................................ 25  
Application and Implementation ........................ 27  
9.1 Application Information............................................ 27  
9.2 Typical Applications ................................................ 27  
1
2
3
4
5
6
7
Features.................................................................. 1  
Applications ........................................................... 1  
Description ............................................................. 1  
Revision History..................................................... 2  
Device Comparison Table..................................... 3  
Pin Configuration and Functions......................... 3  
Specifications......................................................... 5  
7.1 Absolute Maximum Ratings ...................................... 5  
7.2 ESD Ratings.............................................................. 5  
7.3 Recommended Operating Conditions....................... 5  
7.4 Thermal Information.................................................. 6  
7.5 Electrical Characteristics........................................... 6  
7.6 Internal LDO Electrical Characteristics ..................... 6  
7.7 Protection Electrical Characteristics ......................... 6  
7.8 Current Sinks Electrical Characteristics.................... 7  
7.9 PWM Brightness Control Electrical Characteristics .. 7  
7.10 Boost and SEPIC Converter Characteristics .......... 7  
7.11 Logic Interface Characteristics................................ 7  
7.12 Typical Characteristics............................................ 9  
Detailed Description ............................................ 11  
9
10 Power Supply Recommendations ..................... 32  
11 Layout................................................................... 32  
11.1 Layout Guidelines ................................................. 32  
11.2 Layout Example .................................................... 33  
12 Device and Documentation Support ................. 34  
12.1 Device Support...................................................... 34  
12.2 Documentation Support ........................................ 34  
12.3 Receiving Notification of Documentation Updates 34  
12.4 Community Resources.......................................... 34  
12.5 Trademarks........................................................... 34  
12.6 Electrostatic Discharge Caution............................ 34  
12.7 Glossary................................................................ 34  
13 Mechanical, Packaging, and Orderable  
8
Information ........................................................... 34  
4 Revision History  
Changes from Revision A (July 2019) to Revision B  
Page  
•
Added the functional safety link to the Features section........................................................................................................ 1  
Changes from Original (June 2019) to Revision A  
Page  
•
Changed from Advance Information to Production Data ....................................................................................................... 1  
2
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Product Folder Links: LP8867-Q1 LP8869-Q1  
 
LP8867-Q1, LP8869-Q1  
www.ti.com  
SNVSB83B –JUNE 2019–REVISED JANUARY 2020  
5 Device Comparison Table  
LP8869-Q1  
3
LP8869C-Q1  
LP8867-Q1  
4
LP8867C-Q1  
Number of LED channels  
LED current / channel  
3
4
120 mA  
Yes  
120 mA  
No  
120 mA  
Yes  
120 mA  
No  
Power Line FET Control and  
Automatic Current De-rating Support  
6 Pin Configuration and Functions  
LP8867-Q1 PWP Package  
20-Pin HTSSOP With Exposed Thermal Pad  
Top View  
1
2
20  
19  
18  
17  
16  
VIN  
LDO  
VSENSE_N  
SD  
3
FSET  
SW  
4
VDDIO/EN  
FAULT  
PGND  
FB  
5
6
15 OUT1  
14 OUT2  
13 OUT3  
12 OUT4  
SYNC  
PWM  
7
8
TSENSE  
TSET  
9
EP*  
10  
11  
ISET  
GND  
*EXPOSED PAD  
LP8869-Q1 PWP Package  
20-Pin HTSSOP With Exposed Thermal Pad  
Top View  
1
2
20  
19  
18  
17  
16  
VIN  
LDO  
VSENSE_N  
SD  
3
FSET  
SW  
4
VDDIO/EN  
FAULT  
PGND  
FB  
5
6
15 OUT1  
14 OUT2  
13 OUT3  
12 GND  
SYNC  
PWM  
7
8
TSENSE  
TSET  
9
EP*  
10  
11  
ISET  
GND  
*EXPOSED PAD  
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LP8867-Q1, LP8869-Q1  
SNVSB83B –JUNE 2019–REVISED JANUARY 2020  
www.ti.com  
Pin Functions  
PIN  
TYPE(1)  
DESCRIPTION  
NO.  
1
NAME  
VIN  
A
A
Input power pin; input voltage OVP detection pin; input current sense positive input pin.  
2
LDO  
Output of internal LDO; connect a 1-μF decoupling capacitor between this pin and noise-free ground.  
Put the capacitor as close to the chip as possible.  
DC-DC (boost or SEPIC) switching frequency setting resistor; for normal operation, resistor value  
from 24 kΩ to 219 kΩ must be connected between this pin and ground.  
3
FSET  
A
4
5
VDDIO/EN  
FAULT  
I
Enable input for the device as well as supply input (VDDIO) for digital pins.  
Fault signal output. If unused, the pin may be left floating.  
OD  
Input for synchronizing DC-DC converter. If synchronization is not used, connect this pin to ground to  
disable spread spectrum or to VDDIO/EN to enable spread spectrum.  
6
7
8
SYNC  
PWM  
I
I
PWM dimming input.  
Input for NTC resistor divider. Refer to LED Current Dimming With External Temperature Sensor for  
proper connection. If unused, the pin must be left floating.  
TSENSE  
A
Input for NTC resistor divider. Refer to LED Current Dimming With External Temperature Sensor for  
proper connection. If unused, the pin must be connected to GND.  
9
TSET  
A
LED current setting resistor; for normal operation, resistor value from 20 kΩ to 129 kΩ must be  
connected between this pin and ground.  
10  
11  
ISET  
GND  
A
G
Ground.  
Current sink output for LP8867-Q1  
This pin must be connected to ground if not used.  
12  
OUT4/GND  
A
GND pin for LP8869-Q1  
Current sink output.  
This pin must be connected to ground if not used.  
13  
14  
15  
OUT3  
OUT2  
OUT1  
A
A
A
Current sink output.  
This pin must be connected to ground if not used.  
Current sink output.  
This pin must be connected to ground if not used.  
DC-DC (boost or SEPIC) feedback input; for normal operation this pin must be connected to the  
16  
FB  
A
middle of a resistor divider between VOUT and ground using feedback resistor values greater than  
5kΩ.  
17  
18  
19  
20  
PGND  
SW  
G
A
A
A
DC-DC (boost or SEPIC) power ground.  
DC-DC (boost or SEPIC) switch pin.  
SD  
Power-line FET control. Open Drain (current sink type) Output. If unused, the pin may be left floating.  
Input current sense negative input. Connect to VIN pin when input current sense resistor is not used.  
VSENSE_N  
(1) A: Analog pin, G: Ground pin, P: Power pin, I: Input pin, I/O: Input/Output pin, O: Output pin, OD: Open Drain pin  
4
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Product Folder Links: LP8867-Q1 LP8869-Q1  
LP8867-Q1, LP8869-Q1  
www.ti.com  
SNVSB83B –JUNE 2019–REVISED JANUARY 2020  
7 Specifications  
7.1 Absolute Maximum Ratings  
over operating free-air temperature range (unless otherwise noted)(1)(2)  
MIN  
MAX  
50  
UNIT  
VIN, VSENSE_N, SD, SW, FB  
–0.3  
Voltage on pins  
OUT1, OUT2, OUT3, OUT4  
–0.3  
45  
V
LDO, SYNC, FSET, ISET, TSENSE, TSET, PWM, VDDIO/EN, FAULT  
–0.3  
5.5  
Continuous power dissipation(3)  
Internally Limited  
(4)  
Ambient temperature, TA  
–40  
–40  
–65  
125  
150  
150  
°C  
°C  
°C  
(4)  
Junction temperature, TJ  
Storage temperature, Tstg  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended  
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltages are with respect to the potential at the GND pins.  
(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 165°C (typical) and  
disengages at TJ = 145°C (typical).  
(4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may  
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP  
=
150°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the  
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).  
7.2 ESD Ratings  
VALUE  
±2000  
±750  
UNIT  
(1)  
Human-body model (HBM), per AEC Q100-002, all pins  
V(ESD)  
Electrostatic discharge  
Corner pins (1, 10, 11 and 20)  
All pins  
V
Charged-device model (CDM), per AEC  
Q100-011  
±500  
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.  
7.3 Recommended Operating Conditions  
Over operating free-air temperature range (unless otherwise noted)(1)  
MIN  
4.5  
0
NOM  
MAX  
45  
UNIT  
VIN  
12  
SW, VSENSE_N, SD  
45  
Voltage on  
pins  
OUT1, OUT2, OUT3, OUT4  
FB, FSET, LDO, ISET, TSENSE, TSET, VDDIO/EN, FAULT  
SYNC, PWM  
0
40  
V
0
5.25  
0
VDDIO/EN  
(1) All voltages are with respect to the potential at the GND pins.  
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LP8867-Q1, LP8869-Q1  
SNVSB83B –JUNE 2019–REVISED JANUARY 2020  
www.ti.com  
7.4 Thermal Information  
LP886x-Q1  
THERMAL METRIC(1)  
PWP (HTSSOP)  
UNIT  
20 PINS  
44.2  
26.5  
22.4  
0.9  
RθJA  
Junction-to-ambient thermal resistance(2)  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
RθJCtop  
RθJB  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
ψJB  
22.2  
2.5  
RθJCbot  
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.  
(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power  
dissipation exists, special care must be paid to thermal dissipation issues in board design.  
7.5 Electrical Characteristics  
Limits apply over the full operation temperature range −40°C ≤ TA ≤ +125°C , unless otherwise speicified, VIN = 12V.  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Standby supply current  
Device disabled, VVDDIO/EN = 0 V, VIN = 12 V  
4.5  
20  
μA  
IQ  
VIN = 12 V, VOUT = 26 V, output current 80  
mA/channel, converter ƒSW = 300 kHz  
Active supply current  
5
12  
mA  
7.6 Internal LDO Electrical Characteristics  
Limits apply over the full operation temperature range −40°C ≤ TA ≤ +125°C , unless otherwise speicified, VIN = 12V.  
PARAMETER  
TEST CONDITIONS  
MIN  
4.15  
120  
TYP  
MAX  
4.55  
430  
UNIT  
V
VLDO  
VDR  
Output voltage  
VIN = 12 V  
4.3  
Dropout voltage  
300  
50  
mV  
mA  
mA  
ISHORT  
IEXT  
Short circuit current  
Current for external load  
5
7.7 Protection Electrical Characteristics  
Limits apply over the full operation temperature range −40°C ≤ TA ≤ +125°C , unless otherwise speicified, VIN = 12V.  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
VOVP  
VIN OVP threshold voltage  
41  
42  
44  
V
VIN OCP threshold voltage, VIN -  
VSENSEN  
VOCP  
135  
3.7  
160  
3.85  
150  
186  
4
mV  
V
VUVLO  
VIN UVLO Falling threshold  
VIN UVLO Rising threshold - VIN UVLO  
Fallling threshold  
VUVLO_HYST  
mV  
ISENSE_N  
ISD_LEAK  
ISD  
VSENSE_N pin leakage  
SD pin leakage  
VSENSE_N = 45V, EN = L  
0.1  
0.1  
3
3
µA  
µA  
µA  
V
VSD = 45V, EN = L  
SD pull down current  
185  
150  
230  
2.3  
283  
VFB_OVP  
TTSD  
FB threshold for BST_OVP fault  
Thermal shutdown Rising threshold  
165  
175  
℃
Thermal shutdown Rising threshold -  
Thermal shutdown Falling threshold  
TTSD_HYS  
20  
℃
6
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Product Folder Links: LP8867-Q1 LP8869-Q1  
LP8867-Q1, LP8869-Q1  
www.ti.com  
SNVSB83B –JUNE 2019–REVISED JANUARY 2020  
7.8 Current Sinks Electrical Characteristics  
Limits apply over the full operation temperature range −40°C ≤ TA ≤ +125°C , unless otherwise speicified, VIN = 12V.  
PARAMETER  
TEST CONDITIONS  
Outputs OUT1 to OUT4 , VOUTx = 45 V, EN = L  
OUT1, OUT2, OUT3, OUT4, RISET = 20 kΩ  
IOUT = 100 mA  
MIN  
TYP  
MAX  
UNIT  
µA  
ILEAKAGE  
IMAX  
Leakage current  
0.1  
5
Maximum current  
120  
mA  
IOUT  
Output current accuracy  
Output current matching(1)  
Low comparator threshold  
Mid comparator threshold  
High comparator threshold  
−5%  
5%  
5%  
IMATCH  
IOUT = 100 mA, PWM duty =100%  
1%  
0.9  
1.9  
6
VLOW_COMP  
VMID_COMP  
VHIGH_COMP  
V
V
V
5.6  
7
(1) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current.  
Matching is the maximum difference from the average. For the constant current sinks on the part (OUTx), the following are determined:  
the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG). Matching  
number is calculated: (MAX-MIN)/AVG. The typical specification provided is the most likely norm of the matching figure for all parts. LED  
current sinks were characterized with 1-V headroom voltage. Note that some manufacturers have different definitions in use.  
7.9 PWM Brightness Control Electrical Characteristics  
Limits apply over the full operation temperature range −40°C ≤ TA ≤ +125°C , unless otherwise speicified, VIN = 12V.  
PARAMETER  
PWM input frequency  
Minimum on/off time(1)  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Hz  
ƒPWM  
100  
20 000  
tON/OFF  
0.5  
µs  
(1) This specification is not ensured by ATE.  
7.10 Boost and SEPIC Converter Characteristics  
Limits apply over the full operation temperature range −40°C ≤ TA ≤ +125°C , unless otherwise speicified, VIN = 12V.  
PARAMETER  
TEST CONDITIONS  
MIN  
4.5  
6
TYP  
MAX  
UNIT  
VIN  
Input voltage  
40  
V
VOUT  
Output voltage  
45  
ƒSW_MIN  
ƒSW_MAX  
tOFF  
Minimum switching frequency  
Maximum switching frequency  
Minimum switch OFF time(1)  
SW current limit first triggerred  
SW current limit first triggerred period  
SW current limit  
Defined by RFSET resistor  
Defined by RFSET resistor  
SW ≥ 1.15 MHz  
300  
kHz  
kHz  
ns  
2 200  
ƒ
55  
ISW_MAX  
tSW_MAX  
ISW_LIM  
RDSON  
fSYNC  
3.3  
3
3.7  
1.6  
4.1  
A
s
3.35  
240  
3.7  
400  
A
FET RDSON  
mΩ  
kHz  
ns  
External SYNC frequency  
External SYNC on time(1)  
External SYNC off time(1)  
300  
150  
150  
2 200  
tSYNC_ON  
tSYNC_OFF  
ns  
(1) This specification is not ensured by ATE.  
7.11 Logic Interface Characteristics  
Limits apply over the full operation temperature range −40°C ≤ TA ≤ +125°C , unless otherwise speicified, VIN = 12V.  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
LOGIC INPUT VDDIO/EN  
VIL  
VIH  
Input low level  
Input high level  
Input DC current  
0.4  
V
1.65  
−1  
5
30  
µA  
IEN  
Input transient current during VDDIO/EN  
powering up  
1.2  
mA  
LOGIC INPUT SYNC, PWM  
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LP8867-Q1, LP8869-Q1  
SNVSB83B –JUNE 2019–REVISED JANUARY 2020  
www.ti.com  
Logic Interface Characteristics (continued)  
Limits apply over the full operation temperature range −40°C ≤ TA ≤ +125°C , unless otherwise speicified, VIN = 12V.  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
V
0.2 ×  
VDDIO/E  
N
VIL  
Input low level  
0.8 ×  
VDDIO/E  
N
VIH  
II  
Input high level  
Input current  
−1  
1
μA  
LOGIC OUTPUT FAULT  
VOL  
Output low level  
Pullup current 3 mA  
0.3  
0.5  
1
V
ILEAKAGE  
Output leakage current  
V = 5.5 V  
μA  
8
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LP8867-Q1, LP8869-Q1  
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SNVSB83B –JUNE 2019–REVISED JANUARY 2020  
7.12 Typical Characteristics  
Unless otherwise specified: D = NRVB460MFS, TA = 25°C  
480  
400  
320  
240  
480  
400  
320  
240  
160  
80  
160  
VBoost = 18V  
VBoost = 26V  
VBoost = 37V  
VBoost = 18V  
VBoost = 26V  
VBoost = 37V  
80  
4.5  
5.5  
6.5  
Input Voltage (V)  
7.5  
8.5  
9
4.5  
5.5  
6.5 7.5  
Input Voltage (V)  
8.5  
9.5 10  
D005  
D006  
ƒSW = 400 kHz  
L = 33 μH  
DC Load (PWM = 100%)  
ƒSW = 1.1 MHz  
L = 15 μH  
DC Load (PWM = 100%)  
CIN and COUT = 33 µF (electrolytic) + 2 × 10 µF (ceramic)  
CIN and COUT = 33 µF (electrolytic) + 10 µF (ceramic)  
Figure 1. Maximum Boost Current  
Figure 2. Maximum Boost Current  
480  
5.5  
5
4.5  
4
400  
320  
240  
3.5  
3
2.5  
2
1.5  
1
160  
VBoost = 18V  
VBoost = 26V  
VBoost = 37V  
0.5  
0
30  
40  
50  
60  
70  
80  
Output Current (mA)  
90  
100 110 120  
80  
4.5  
5.5  
6.5 7.5  
Input Voltage (V)  
8.5 9.5  
D008  
D007  
ƒSW = 2.2 MHz  
L = 10 μH  
DC Load (PWM = 100%)  
Figure 4. LED Current Sink Matching  
CIN and COUT = 3× 10 µF (ceramic)  
Figure 3. Maximum Boost Current  
100  
100  
96  
92  
88  
84  
80  
76  
72  
68  
96  
92  
88  
84  
80  
76  
72  
68  
VIN = 16V  
VIN = 12V  
VIN = 8V  
VIN = 6V  
VIN = 16V  
VIN = 12V  
VIN = 8V  
VIN = 6V  
80  
160  
240 320  
Output Current (mA)  
400  
480  
80  
160  
240 320  
Output Current (mA)  
400  
480  
D001  
D002  
ƒSW = 400 kHz  
L = 22 μH  
DC Load (PWM = 100%)  
VBOOST = 18 V  
ƒSW = 400 kHz  
L = 22 μH  
DC Load (PWM = 100%)  
VBOOST = 30 V  
CIN and COUT = 33 µF (electrolytic)  
+ 2 × 10 µF (ceramic)  
CIN and COUT = 33 µF (electrolytic)  
+ 2 × 10 µF (ceramic)  
Figure 5. Boost Efficiency  
Figure 6. Boost Efficiency  
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Typical Characteristics (continued)  
Unless otherwise specified: D = NRVB460MFS, TA = 25°C  
100  
100  
96  
92  
88  
84  
80  
76  
72  
68  
96  
92  
88  
84  
80  
76  
VIN = 16V  
VIN = 12V  
VIN = 16V  
VIN = 12V  
VIN = 8V  
VIN = 6V  
72  
VIN = 8V  
VIN = 6V  
68  
80  
160  
240 320  
Output Current (mA)  
400  
480  
80  
160  
240 320  
Output Current (mA)  
400  
480  
D003  
D004  
ƒSW = 2.2 MHz  
L = 4.7 μH  
DC Load (PWM = 100%)  
VBOOST = 18 V  
ƒSW = 2.2 MHz  
L = 4.7 μH  
DC Load (PWM = 100%)  
VBOOST = 30 V  
CIN and COUT = 3 × 10 µF (ceramic)  
CIN and COUT = 3 × 10 µF (ceramic)  
Figure 7. Boost Efficiency  
Figure 8. Boost Efficiency  
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8 Detailed Description  
8.1 Overview  
The LP8867-Q1, LP8869-Q1 is a highly integrated LED driver for automotive infotainment , cluster and HUD  
medium-size LCD backlight applications. It includes a DC-DC with an integrated FET, supporting both boost and  
SEPIC modes, an internal LDO enabling direct connection to battery without need for a pre-regulated supply and  
3 or 4 LED current sinks. The VDDIO/EN pin provides the supply voltage for digital IOs (PWM and SYNC inputs)  
and at the same time enables the device.  
The switching frequency on the DC-DC converter is set by a resistor connected to the FSET pin. The maximum  
voltage of the DC-DC is set by a resistive divider connected to the FB pin. For the best efficiency, the output  
voltage is adapted automatically to the minimum necessary level needed to drive the LED strings. This is done  
by monitoring LEDs' cathode voltage in real time. For EMI reduction, two optional features are available:  
•
•
Spread spectrum, which reduces EMI noise around the switching frequency and its harmonic frequencies  
DC-DC can be synchronized to an external frequency connected to SYNC pin  
The 3 or 4 constant current outputs OUT1, OUT2, OUT3, and OUT4 provide LED current up to 120 mA. Value  
for the current per OUT pin is set with a resistor connected to ISET pin. Current sinks that are not used must be  
connected to ground. Grounded current sink is disabled and excluded from boost adaptive voltage detection  
loop.  
Brightness is controlled with the PWM input. Frequency range for the input PWM is from 100 Hz to 20 kHz. LED  
output PWM behavior follows the input PWM so the output frequency is equal to the input frequency.  
LP886x-Q1 has extensive fault detection features:  
•
•
•
•
•
•
•
LED open and short detection  
VIN input overvoltage protection  
VIN input undervoltage protection  
VIN input overcurrent protection  
VBoost output overvoltage protection  
SW overvoltage protection  
Thermal shutdown in case of chip overheated  
Fault condition is indicated through the FAULT output pin.  
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8.2 Functional Block Diagram  
L
RISENSE  
D
Q
VIN  
RGS  
COUT  
CIN  
CIN BOOST  
VIN  
VSENSE_N  
SD  
POWER-LINE FET CONTROL  
LDO  
LDO  
CLDO  
SW  
SYNC  
FSET  
PGND  
FB  
BOOST  
CONTROLLER  
RFSET  
RISET  
4 x LED  
CURRENT  
SINK  
ISET  
OUT1  
OUT2  
OUT3  
OUT4  
GND  
TSET  
CURRENT  
SETTING  
TSENSE  
PWM  
VDDIO/EN  
FAULT  
DIGITAL BLOCKS  
(FSM, ADAPTIVE VOLTAGE  
CONTROL, SAFETY LOGIC  
etc.)  
ANALOG BLOCKS  
(CLOCK GENERATOR, VREF,  
TSD etc.)  
VDDIO  
EXPOSED PAD  
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8.3 Feature Description  
8.3.1 Integrated DC-DC Converter  
The LP886x-Q1 DC-DC converter generates supply voltage for the LEDs and can operate in boost mode or in  
SEPIC mode. The output voltage, switching frequency are all configured by external resistors.  
For detailed boost application, refer to Typical Application for 4 LED Strings  
For detailed SEPIC application, refer to SEPIC Mode Application  
8.3.1.1 DC-DC Converter Parameter Configuration  
The LP886x-Q1 converter is a current-peak mode DC-DC converter, where the switch FET's current and the  
output voltage feedback are measured and controlled. The block diagram is shown in Figure 9.  
D
VIN  
VOUT  
CIN  
COUT  
R1  
SW  
OCP  
ADAPTIVE  
VOLTAGE  
CONTROL  
R2  
LIGHT  
LOAD  
CURRENT  
SENSE  
OVP  
RC  
R
S
R
R
filter  
FB  
-
GM  
PGND  
R
+
SYNC  
FSET  
GM  
ꢀ
FSET  
BLANK  
TIME  
CTRL  
BOOST  
OFF/BLANK  
TIME  
CURRENT  
RAMP  
OSCILLATOR  
PULSE  
GENERATOR  
RFSET  
GENERATOR  
Figure 9. DC-DC converter in Boost Application  
8.3.1.1.1 Switching Frequency  
Switching frequency is adjustable between 300 kHz and 2.2 MHz with RFSET resistor as Equation 1:  
ƒSW = 67600 / (RFSET + 6.4)  
where  
•
•
ƒSW is switching frequency, kHz  
RFSET is frequency setting resistor, kΩ  
(1)  
For example, if RFSET is set to 163 kΩ, fSW will be 400 kHz.  
In most cases, lower switching frequency has higher system efficiency and lower internal temperature increase.  
8.3.1.1.2 Spread Spectrum and External SYNC  
LP886x-Q1 has an optional spread spectrum feature (±3% from central frequency, 1-kHz modulation frequency)  
which reduces EMI noise at the switching frequency and its harmonic frequencies. If SYNC pin level is low,  
spread spectrum function is disabled. If SYNC pin level is high, spread spectrum function is enabled.  
LP886x-Q1 DC-DC converter can be driven by an external SYNC signal between 300 kHz and 2.2 MHz. When  
external synchronization is used, spread spectrum is not available. If the external synchronization input  
disappears, DC-DC continues operation at the frequency defined by RFSET resistor and spread spectrum function  
will be enabled/disabled depending on the final SYNC pin level.  
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Feature Description (continued)  
External SYNC frequency must be 1.2 to 1.5 times higher than the frequency defined by RFSET resistor. In  
external SYNC configuration, minimum frequency setting with RFSET could go as low as 250 kHz to support 300-  
kHz switching with external clock.  
Table 1. DC-DC Synchronization Mode  
SYNC PIN INPUT  
MODE  
Low  
High  
Spread spectrum disabled  
Spread spectrum enabled  
300 to 2200 kHz frequency  
Spread spectrum disabled, external synchronization mode  
8.3.1.1.3 Recommended Component Value and Internal Parameters  
The LP886x-Q1 DC-DC converter has an internal compensation network to ensure the stability. There's no  
external component needed for compensation. It's strongly recommended that the inductance value and the  
boost input and output capacitors value follow the requirement of Table 2. Also, the DC-DC internal parameters  
are chosen automatically according to the selected switching frequency (see Table 2) to ensure stability.  
Table 2. Boost Converter Parameters(1)  
TYPICAL  
INDUCTANCE (µH)  
TYPICAL BOOST INPUT  
AND OUTPUT CAPACITORS (µF)  
MINIMUM SWITCH  
OFF TIME (ns)(2)  
BLANK  
TIME (ns)  
RANGE  
FREQUENCY (kHz)  
1
2
3
4
300 to 480  
480 to 1150  
1150 to 1650  
1650 to 2200  
22 or 33  
15  
2 ×10 (cer.) + 33 (electr.)  
10 (cer.) + 33 (electr.)  
3 × 10 (cer.)  
150  
60  
95  
95  
95  
70  
10  
40  
4.7 or 10  
3 × 10 (cer.)  
40  
(1) Parameters are for reference only  
(2) Due to current sensing comparator delay the actual minimum off time is 6 ns (typical) longer than in the table.  
8.3.1.1.4 DC-DC Converter Switching Current Limit  
The LP886x-Q1 DC-DC converter has an internal SW FET inside chip's SW pin. The internal FET current is  
limited to 3.35 A (typical). The DC-DC converter will sense the internal FET current, and turn off the internal FET  
cycle-by-cycle when the internal FET current reaches the limit.  
To support start transient condition, the current limit could be automatically increased to 3.7 A for a short period  
of 1.6 seconds when a 3.35-A limit is reached.  
NOTE  
Application condition where the 3.35-A limit is exceeded continuously is not allowed. In  
this case the current limit would be 3.35 A for 1.6 seconds followed by 3.7-A limit for 1.6  
seconds, and this 3.2-second period repeats.  
8.3.1.1.5 DC-DC Converter Light Load Mode  
LP886x-Q1 DC-DC converter will enter into light load mode in below condition:  
•
•
•
VIN voltage is very close to VOUT  
Loading current is very low  
PWM pulse width is very short  
When DC-DC converter enters into light load mode, DC-DC converter stops switching occasionally to make sure  
boost output voltage won't rise up too much. It could also be called as PFM mode, since the DC-DC converter  
switching frequency will change in this mode.  
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8.3.1.2 Adaptive Voltage Control  
The LP886x-Q1 DC/DC converter generates the supply voltage for the LEDs. During normal operation, boost  
output voltage is adjusted automatically based on the LED cathode (OUTx pin) voltages. This is called adaptive  
boost control. Only the active LED outputs are monitored to control the adaptive boost voltage. Any LED strings  
with open or short faults are removed from the adaptive voltage control loop. The OUTx pin voltages are  
periodically monitored by the control loop. The boost voltage is raised if any of the OUTx voltage falls below the  
VLOW_COMP threshold. The boost voltage is also lowered if all OUTx voltages are higher than VLOW_COMP  
threshold. The boost voltage keeps unchanged when one of OUTx voltage touches the VLOW_COMP threshold. In  
normal operation, the lowest voltage among the OUTx pins is around VLOW_COMP, and boost voltage stays  
constant. VLOW_COMP level is the minimum voltage which could guarantee proper LED current sink operation. See  
Figure 10 for how the boost voltage automatically scales based on the OUT1-4 pin voltage.  
Boost  
decreases voltage  
Boost  
Increases voltage  
No actions  
OUT 1-4  
VOLTAGE  
The lowest channel  
voltage touches  
VLOW_COMP threshold  
No output is close to  
VLOW_COMP threshold  
One output is lower than  
VLOW_COMP threshold  
VLOW_COMP  
Normal  
Conditions  
Dynamic  
Conditions  
Figure 10. Adaptive Boost Voltage Control Loop Function  
8.3.1.2.1 Using Two-Divider  
VBOOST_MAX voltage should be chosen based on the maximum voltage required for LED strings. Recommended  
maximum voltage is about 3 to 5-V higher than maximum LED string voltage. DC-DC output voltage is adjusted  
automatically based on LED cathode voltage. The maximum, minimum and initial boost voltages can be  
calculated with Equation 2:  
V
≈
’
BG  
VBOOST  
=
+K ì 0.0387 ì R1+ VBG  
∆
«
÷
R2  
◊
where  
•
•
•
•
•
•
VBG = 1.2 V  
R2 recommended value is 10 kΩ to 200 kΩ  
R1/R2 recommended value is 5 to 10  
K = 1 for maximum adaptive boost voltage (typical)  
K = 0 for minimum adaptive boost voltage (typical)  
K = 0.88 for initial boost voltage (typical)  
(2)  
For example, if R1 is set to 750 kΩ and R2 is set to 130 kΩ, VBOOST will be in the range of 8.1 V to 37.1 V.  
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VOUT  
COUT  
R1  
+
VBG  
GM  
œ
FB  
R2  
+
BSTOVP  
VOVP  
œ
Current DAC  
(38.7uA Full-Scale)  
Figure 11. FB External Two-Divider Resistors  
8.3.1.2.2 Using T-Divider  
Alternatively, a T-divider can be used if resistance less than 100 kΩ is required for the external resistive divider.  
Then the maximum, minimum and initial boost voltages can be calculated with  
R1ìR3  
R2  
R1  
R2  
≈
’
◊
≈
’
◊
VBOOST  
=
+R1+R3 Kì0.0387 +  
+1 ìVBG  
∆
«
÷
∆
«
÷
where  
•
•
•
•
•
•
VBG = 1.2 V  
R2 recommended value is 10 kΩ to 200 kΩ  
R1/R2 recommended value is 5 to 10  
K = 1 for maximum adaptive boost voltage (typical)  
K = 0 for minimum adaptive boost voltage (typical)  
K = 0.88 for initial boost voltage (typical)  
(3)  
For example, if R1 is set to 100 kΩ, R2 is set to 10 kΩ and R3 is set to 60 kΩ, VBOOST will be in the range of 13.2  
V to 42.6 V.  
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VOUT  
COUT  
R1  
R2  
+
GM  
VBG  
R3  
œ
FB  
+
BSTOVP  
VOVP  
œ
Current DAC  
(38.7uA Full-Scale)  
Figure 12. FB External T-divider Resistors  
8.3.1.2.3 Feedback Capacitor  
When operating with no electrolytic capacitor in boost output, which is a typical case when boost frequency is in  
the 1.15-MHz to 2.2-MHz range, a feedback capacitor needs to be put in parallel with R1 to ensure the loop  
stability. The value of the capacitor is recommended to be:  
1
CFB  
=
2pfzR1  
where  
•
fz = 20 kHz  
(4)  
For example, if R1 is set to 750 kΩ, CFB needs to be around 11 pF.  
VOUT  
COUT  
R1  
R2  
Optional  
R3  
CFB  
+
GM  
VBG  
œ
FB  
+
BSTOVP  
VOVP  
œ
Current DAC  
(38.7uA Full-Scale)  
Figure 13. FB External Resistors With Capacitor When Operating With No Electrolytic Capacitor In Boost  
Output  
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8.3.2 Internal LDO  
The internal LDO regulator converts the input voltage at VIN to a 4.3-V output voltage for internal use. Connect a  
minimum of 1-µF ceramic capacitor from LDO pin to ground, as close to the LDO pin as possible.  
8.3.3 LED Current Sinks  
8.3.3.1 LED Output Configuration  
LP886x-Q1 detects LED output configuration during start-up. Any current sink output connected to ground is  
disabled and excluded from the adaptive voltage control of the DC-DC converter and fault detections.  
If more current is needed, LP886x-Q1's output could also be connected together to support the high current LED.  
8.3.3.2 LED Current Setting  
The output current of the LED outputs is controlled with external RISET resistor. RISET value for the target LED  
current per channel can be calculated using Equation 5:  
VBG  
ILED = 2000ì  
RISET  
where  
•
•
•
VBG = 1.2 V  
RISET is current setting resistor, kΩ  
ILED is output current per OUTx pin, mA  
(5)  
For example, if RISET is set to 20 kΩ, ILED will be 120 mA per channel.  
8.3.3.3 Brightness Control  
LP886x-Q1 controls the brightness of the display with conventional PWM. Output PWM directly follows the input  
PWM. Input PWM frequency can be in the range of 100 Hz to 20 kHz.  
8.3.4 Power-Line FET Control  
The LP886x-Q1 has a power-line FET control feature. It has a control pin (SD) for driving the gate of an external  
power-line P-Channel MOSFET. This feature grants LP886x-Q1 the ability to immediately cut-off the power part  
of backlight system when failure occurs, protecting other parallel power systems from being impacted. In  
addition, the feature could smooth the inrush current during powering-up by turning on the power-line FET  
gradually. In SOFT START state, the SD pin slowly increases the sink current until it reaches 230 μA. An  
example schematic is shown in Figure 14.  
The value of RGS should follow the rules below  
•
•
ISD_MAX × RGS should be less than the power-line FET's maximum acceptable Source-Gate voltage  
ISD_MIN × RGS should be greater than the minimum power-line FET's Source-Gate voltage which could ensure  
a low On-State Resistance.  
A 20-kΩ RGS is chosen in typical application which generates a 4.6 V difference on power-line FET's Source-  
Gate voltage.  
RISENSE  
Q1  
L1  
VIN  
CIN BOOST  
RGS  
SW  
SD  
VSENSE_N  
VIN  
CIN  
Figure 14. Power-Line FET Control Schematics  
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The LP886x-Q1 turns off the power-line FET and prevents the possible boost and LEDs leakage when the device  
is disabled or in FAULT RECOVERY state.  
Power-line FET control is an optional feature. Leave SD pin NC and don't use power-line FET when this feature  
is not needed.  
8.3.5 LED Current Dimming With External Temperature Sensor  
The LP886x-Q1 has an optional feature to decrease automatically LED current when LED overheating is  
detected with an external NTC sensor. An example of the behavior is shown in Figure 15. When the NTC  
temperature reaches T1, the LP886x-Q1 starts to decrease the LED current. When the LED current has reduced  
to 17.5% of the nominal value, current turns off until temperature returns to the operation range.  
100%  
17.5%  
T1  
NTC TEMPERATURE  
T2  
Figure 15. Temperature-Based LED Current Dimming Functionality  
VBG  
ISET_SCALED  
1:2000  
ISET  
+
LED OUT  
RISET  
VDD  
-
ILED  
ITSENSE  
LED DRIVER  
R3  
RT  
R4  
TSET  
TSENSE  
R7  
ITSENSE  
R5  
R6  
NTC  
Figure 16. Temperature-Based LED Current Dimming Implementation  
When TSET pin is grounded and TSENSE is floated, this feature is disabled. LED current is set by RISET resistor:  
VBG  
ILED = 2000ì  
RISET  
where  
•
•
•
VBG = 1.2 V  
RISET is current setting resistor, kΩ  
ILED is output current per OUTx pin, mA  
(6)  
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When external NTC is connected, the TSENSE pin current decreases LED output current. Temperature T1 and  
de-rate slope are defined by external resistors as explained below.  
Parallel resistance of the NTC sensor RT and resistor R4 is calculated by formula:  
RT ìR6  
RII =  
RT + R6  
(7)  
TSET voltage can be calculated with Equation 8:  
R5  
VTSET = VDD  
ì
R4
+
R5  
(8)  
TSENSE pin current is calculated by Equation 9:  
RII  
VTSET - VDD  
RII + R7 -  
ì
RII + R3  
ITSENSE  
=
2
RII  
RII + R3  
where  
•
VDD is the bias voltage of the resistor group. It's recommended to connect with chip's internal LDO output (pin  
2) (9)  
ISET pin current defined by RISET is:  
VBG  
ISET _ SCALED  
=
RISET  
(10)  
For Equation 11, ITSENSE current must be limited between 0 and ISET_SCALED. If ITSENSE > ISET_SCALED then set  
ITSENSE = ISET_SCALED. If ITSENSE < 0 then set ITSENSE = 0.  
LED driver output current is:  
ILED = (ISET_SCALED – ITSENSE ) x 2 000  
(11)  
When current is lower than 17.5% of the nominal value, the current is set to 0 (the cut-off point).  
An Excel® calculator is available for calculating the component values for a specific NTC and target thermal  
profile (contact TI E2E™ support forums ). Figure 17 shows an example thermal profile implementation.  
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120  
100  
80  
60  
40  
20  
0
0.06  
0.05  
0.04  
0.03  
0.02  
0.01  
0.00  
LED current  
TSENSE current  
70  
60  
80  
90  
100  
110  
120  
Temperature (ºC)  
C006  
NTC – 10 kΩ at 25ºC  
RISET = 24 kΩ  
R1 = 10 kΩ  
R2 = 10 kΩ  
R3 = 2 kΩ  
R4 = 100 kΩ  
R5 = 7.5 kΩ  
VDD = 4.3 V  
Figure 17. Calculation Example  
8.3.6 Fault Detections and Protection  
The LP886x-Q1 has fault detection for LED open and short, VIN input overvoltage protection (VIN_OVP) , VIN  
undervoltage protection (VIN_UVLO), VIN overcurrent protection (VIN_OCP) , Boost output overvoltage  
protection (BST_OVP), SW overvoltage protection (SW_OVP) and thermal shutdown (TSD).  
8.3.6.1 Supply Fault and Protection  
8.3.6.1.1 VIN Undervoltage Fault (VIN_UVLO)  
The LP886x-Q1 device supports VIN undervoltage protection. The VIN undervoltage falling threshold is 3.85-V  
typical and rising threshold is 4-V typical. If during operation of the LP886x-Q1 device, the VIN pin voltage falls  
below the VIN undervoltage falling threshold, the boost, LED outputs, and power-line FET will be turned off, and  
the device will enter FAULT RECOVERY mode. The FAULT pin will be pulled low. The LP886x-Q1 will exit  
FAULT RECOVERY mode after 100 ms and try the start-up sequence again. VIN_UVLO fault detection is  
available in SOFT START, BOOST START, and NORMAL state.  
8.3.6.1.2 VIN Overvoltage Fault (VIN_OVP)  
The LP886x-Q1 device supports VIN overvoltage protection. The VIN overvoltage threshold is 43-V typical. If  
during LP886x-Q1 operation, VIN pin voltage rises above the VIN overvoltage threshold, the boost, LED outputs  
and the power-line FET will be turned off, and the device will enter FAULT RECOVERY mode. The FAULT pin  
will be pulled low. The LP886x-Q1 will exit FAULT RECOVERY mode after 100 ms and try the start-up sequence  
again. VIN_OVP fault detection is available in SOFT START, BOOST START and NORMAL state.  
8.3.6.1.3 VIN Overcurrent Fault (VIN_OCP)  
The LP886x-Q1 device supports VIN overcurrent protection. If during LP886x-Q1 operation, voltage drop  
between VIN pin and VSENSE_N pin rises above 160-mV typical, the boost, LED outputs and the power-line  
FET will be turned off, and the device will enter FAULT RECOVERY mode. The FAULT pin will be pulled low.  
The LP886x-Q1 will exit FAULT RECOVERY mode after 100 ms and try the start-up sequence again. VIN_OCP  
fault detection is available in SOFT START, BOOST START, and NORMAL state.  
A 30-mΩ resistor is recommended to put between VIN pin and VSENSE_N pin, which will set the VIN  
overcurrent threshold to 5.3 A.  
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8.3.6.2 Boost Fault and Protection  
8.3.6.2.1 Boost Overvoltage Fault (BST_OVP)  
The LP886x-Q1 device supports boost overvoltage protection. If during LP886x-Q1 operation, the FB pin voltage  
exceeds the VFB_OVP threshold, which is 2.3-V typical, the boost, LED outputs and the power-line FET will be  
turned off, and the device will enter FAULT RECOVERY mode. The FAULT pin will be pulled low. The LP886x-  
Q1 will exit FAULT RECOVERY mode after 100 ms and try the start-up sequence again. BST_OVP fault  
detection is available in NORMAL state.  
Calculating back from FB pin voltage threshold to boost output OVP voltage threshold, the value is not a static  
threshold, but a dynamic threshold changing with the current target boost adaptive voltage:  
R1  
≈
’
◊
VBOOST_OVP = VBOOST  
+
+1 ì(VFB_OVP - VBG )  
∆
«
÷
R2  
where  
•
VBOOST is the current target boost adaptive voltage, which in most time is the current largest LED string forward  
voltage among multiple strings + 0.9 V in steady state  
•
•
•
VFB_OVP = 2.3 V  
VBG = 1.2 V  
R1 and R2 is the resistor value of FB external network in Using Two-Divider and Using T-Divider  
(12)  
For example, if R1 is set to 750 kΩ and R2 is set to 130 kΩ, VBOOST will report OVP when the boost voltage is 7.4  
V above target boost voltage.  
This equation holds true in both two-divider FB external network and T-divider FB external network.  
8.3.6.2.2 SW Overvoltage Fault (SW_OVP)  
Besides boost overvoltage protection, the LP886x-Q1 supports SW pin overvoltage protection to further protect  
the boost system from overvoltage scenario. If during LP886x-Q1 operation, the SW pin voltage exceeds the  
VSW_OVP threshold, which is 49-V typical, the boost, LED outputs and the power-line FET are turned off, and the  
device will enter FAULT RECOVERY mode. The FAULT pin will be pulled low. The LP886x-Q1 will exit FAULT  
RECOVERY mode after 100 ms and try the start-up sequence again. SW_OVP fault detection is available in  
SOFT START, BOOST START and NORMAL state.  
8.3.6.3 LED Fault and Protection (LED_OPEN and LED_SHORT)  
Every LED current sink has 3 comparators for LED fault detections.  
OUT#  
VHIGH_COMP  
HIGH_COMP  
VMID_COMP  
MID_COMP  
VLOW_COMP  
LOW_COMP  
CURRENT/PWM  
CONTROL  
Figure 18. Comparators for LED Fault Detection  
Figure 19 shows cases which generates LED faults. Any LED faults will pull the Fault pin low.  
During normal operation, boost voltage is raised if any of the used LED outputs falls below the VLOW_COMP  
threshold. Open LED fault is detected if boost output voltage has reached the maximum and at least one LED  
output is still below the threshold. The open string is then disconnected from the boost adaptive control loop and  
its output is disabled.  
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Shorted LED fault is detected if one or more LED outputs are above the VHIGH_COMP threshold (typical 6 V) and at  
least one LED output is inside the normal operation window (between VLOW_COMP and VMID_COMP, typical 0.9 V  
and 1.9 V). The shorted string is disconnected from the boost adaptive control loop and its output is disabled.  
LED Open fault detection and LED Short fault detection are available only in NORMAL state.  
Short LED fault  
(at least one channel between  
LOW_COMP and MID COMP)  
Open LED fault  
when  
VBOOST = MAX  
No actions  
OUT1~4 PIN  
VOLTAGE  
Open LED Fault  
Short LED Fault  
VHIGH_COMP  
VMID_COMP  
VLOW_COMP  
Normal Condition  
Fault Condition  
Figure 19. Protection and DC-DC Voltage Adaptation Algorithms  
If LED fault is detected, the device continues normal operation and only the faulty string is disabled. The fault is  
indicated via the FAULT pin which can be released by toggling VDDIO/EN pin low for a short period of 2 µs to 20  
µs. LEDs are turned off for this period but the device stays in NORMAL state. If VDDIO/EN is low longer, the  
device goes to STANDBY and restarts when EN goes high again.  
This means if the system doesn't want to simply disable the device because of LED faults. It could clear the LED  
faults by toggling VDDIO/EN pin low for a short period of 2 µs to 20 µs.  
8.3.6.4 Thermal Fault and Protection (TSD)  
If the die temperature of LP886x-Q1 reaches the thermal shutdown threshold TTSD, which is 165°C typical, the  
boost, power-line FET and LED outputs are turned off to protect the device from damage. The FAULT pin will be  
pulled low. The LP886x-Q1 will exit FAULT RECOVERY mode after 100 ms and try the start-up sequence again.  
Only if the die temperature drops lower than TTSD - TTSD_HYS, which is 145°C typical, the device could start-up  
normally. TSD fault detection is available in SOFT START, BOOST START and NORMAL state.  
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8.3.6.5 Overview of the Fault and Protection Schemes  
A summary of the LP886x-Q1 fault detection behavior is shown in Table 3. Detected faults (excluding LED open or short) cause device to enter FAULT  
RECOVERY state. In FAULT_RECOVERY the DC-DC and LED current sinks of the device are disabled, and the FAULT pin is pulled low. The device will  
exit FAULT RECOVERY mode after 100 ms and try the start-up sequence again. When recovery is successful and device enters into NORMAL state, the  
FAULT pin is released high.  
Table 3. Fault Detections  
Enter FAULT_  
RECOVERY  
STATE  
FAULT/  
PROTECTION  
FAULT  
PIN  
FAULT NAME  
CONDITION  
ACTIVE STATE  
ACTION  
VIN overvoltage  
protection  
SOFT START, BOOST  
START, NORMAL  
Device enters into FAULT RECOVERY state, and restarts after  
100 ms  
VIN_OVP  
VIN > 43 V  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Effective when VIN <  
3.85 V  
Released when VIN >4  
V
VIN undervoltage  
protection  
SOFT START, BOOST  
START, NORMAL  
Device enters into FAULT RECOVERY state, and restarts after  
100 ms  
VIN_UVLO  
VIN_OCP  
VIN overcurrent  
protection  
VIN-VSENSE_N >  
160mV  
SOFT START, BOOST  
START, NORMAL  
Device enters into FAULT RECOVERY state, and restarts after  
100 ms  
Open string is removed from the DC-DC voltage control loop  
and output is disabled.  
Fault pin low could be released by toggling VDDIO/EN pin, If  
VDDIO/EN is low for a period of 2 µs to 20 µs, LEDs are turned  
off for this period but device stays in NORMAL.  
Adaptive Voltage is  
max. and  
any OUTx voltage <  
0.9 V  
Open LED fault  
LED _OPEN  
LED_SHORT  
Yes  
Yes  
No  
No  
NORMAL  
Short string is removed from the DC-DC voltage control loop  
and output is disabled.  
Fault pin low could be released by toggling VDDIO/EN pin, If  
VDDIO/EN is low for a period of 2 µs to 20 µs, LEDs are turned  
off for this period but device stays NORMAL.  
One of OUTx voltage  
is [0.9 V, 1.9 V] and  
any OUTx voltage > 6  
V
Shorted LED fault  
NORMAL  
NORMAL  
Fault is detected if boost overvoltage condition duration is more  
than 560 ms  
Device enters into FAULT RECOVERY state, and restarts after  
100 ms  
Boost overvoltage  
protection  
BST_OVP  
SW_OVP  
TSD  
VFB > 2.3 V  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
SW overvoltage  
protection  
SOFT START, BOOST  
START, NORMAL  
Device enters into FAULT RECOVERY state, and restarts after  
100 ms  
VSW > 49 V  
Effective when Tj >  
165 ºC  
Released when Tj <  
145 ºC  
SOFT START, BOOST  
START, NORMAL  
Device enters into FAULT RECOVERY state, and restarts until  
TSD fault is released  
Thermal protection  
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8.4 Device Functional Modes  
8.4.1 STANDBY State  
The LP886x-Q1 enters STANDBY state when the VIN voltage powers on and voltage is higher than VINUVLO  
rising threshold, which is 4-V typical. In STANDBY state, the device is able to detect VDDIO/EN signal. When  
VDDIO/EN is pulled high, the internal LDO wakes up and the device enters into SOFT START state. The device  
will re-enter the STANDBY state when VDDIO/EN is pulled low for more than 50 µs.  
8.4.2 SOFT START State  
In SOFT START state, Power-line FET is enabled, and boost input and output capacitors are charged to VIN  
level. VIN_OCP, VIN_OVP, VIN_UVLO, SW_OVP and TSD fault are active. After 65 ms, the device enters into  
BOOST START state.  
8.4.3 BOOST START State  
In BOOST START state, DC-DC controller is turned on and boost voltage is ramped to initial boost voltage level  
with reduced current limit. VIN_OCP, VIN_OVP, VIN_UVLO, SW_OVP and TSD fault are active in this state.  
After 50 ms, LED outputs do a one-time detection on grounded outputs. Grounded outputs are disabled and  
excluded from the adaptive voltage control loop. Then the device enters into NORMAL state.  
8.4.4 NORMAL State  
In NORMAL state, LED drivers are enabled when PWM signal is high. All faults are active in this state. Fault pin  
will be released high in the start of NORMAL state if recovering from FAULT RECOVERY state and no fault is  
available.  
8.4.5 FAULT RECOVERY State  
Non-LED faults can trigger fault recovery state. LED drivers, boost converter and power-line FET are all disabled.  
After 100 ms, the device attempts to restart from SOFT START state if VDDIO/EN is still high.  
8.4.6 State Diagram and Timing Diagram for Start-up and Shutdown  
VIN > VUVLO  
STANDBY  
VDDIO / EN = 1  
VDDIO / EN = 0  
SOFT START  
65 ms  
50 ms  
FAULT  
FAULT  
BOOST START  
100 ms  
FAULT RECOVERY  
LED OUTPUT  
CONFIGURATION  
DETECTION  
(1st time power-up only)  
FAULT  
NORMAL  
VDDIO / EN = 0  
Figure 20. State Diagram  
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Device Functional Modes (continued)  
T=50ꢀs  
t>500ꢀs  
VIN  
LDO  
VDDIO/EN  
SYNC  
Headroom adaptation  
VOUT=VIN level œ diode drop  
VOUT  
PWM OUT  
IQ  
Active mode  
SOFT  
START  
BOOST  
START  
Figure 21. Timing Diagram for the Typical Start-Up and Shutdown  
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9 Application and Implementation  
NOTE  
Information in the following applications sections is not part of the TI component  
specification, and TI does not warrant its accuracy or completeness. TI’s customers are  
responsible for determining suitability of components for their purposes. Customers should  
validate and test their design implementation to confirm system functionality.  
9.1 Application Information  
The LP886x-Q1 is designed for automotive applications. The input voltage (VIN) is intended to be connected to  
the automotive battery, which supports voltage range from 4.5 V to 40 V. Device internal circuitry is powered  
from the integrated LDO.  
The LP886x-Q1 uses a simple four-wire control:  
•
•
•
•
VDDIO/EN for enable  
PWM input for brightness control  
SYNC pin for boost synchronisation (optional)  
FAULT output to indicate fault condition (optional)  
9.2 Typical Applications  
9.2.1 Typical Application for 4 LED Strings  
Figure 22 shows the typical application for LP886x-Q1 which supports 4 LED strings, 100 mA per string with a  
boost switching frequency of 400 kHz.  
VIN  
5...28 V  
L1  
CIN BOOST  
D1  
RISENSE  
Q1  
Up to 34V  
COUT  
R2  
R1  
SW  
SD  
RGS  
VSENSE_N  
VIN  
FB  
CIN  
CLDO  
OUT1  
LDO  
LP8867-Q1  
OUT2  
OUT3  
RFSET  
VLDO  
FSET  
SYNC  
PWM  
OUT4  
R4  
R3  
BRIGHTNESS  
TSET  
VDDIO/EN  
FAULT  
TSENSE  
VDDIO/EN  
FAULT  
R7  
RTf  
NTC  
ISET  
R6  
R5  
R8  
VDDIO/EN  
PGND GND PAD  
RISET  
Figure 22. Four Strings 100 mA per String Configuration  
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Typical Applications (continued)  
9.2.2 Design Requirements  
Table 4. Design Requirements Table  
DESIGN PARAMETER  
VALUE  
VIN voltage range  
5 V – 28 V  
LED string  
4P8S LEDs (30 V max)  
LED string current  
100 mA  
Maximum boost voltage  
34 V  
Boost switching frequency  
400 kHz  
External boost sync  
not used  
Boost spread spectrum  
enabled  
L1  
CIN  
33 μH  
100 µF, 50 V  
CIN BOOST  
COUT  
CLDO  
RISET  
RFSET  
R1  
2 × (10 µF, 50-V ceramic) + 33 µF, 50-V electrolytic  
2 × (10 µF, 50-V ceramic) + 33 µF, 50-V electrolytic  
1 µF, 10 V  
24 kΩ  
160 kΩ  
685 kΩ  
130 kΩ  
10 kΩ  
R2  
R8  
9.2.3 Detailed Design Procedure  
9.2.3.1 Inductor Selection  
There are two main considerations when choosing an inductor; the inductor must not saturate, and the inductor  
current ripple must be small enough to achieve the desired output voltage ripple. Different saturation current  
rating specifications are followed by different manufacturers so attention must be given to details. Saturation  
current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of  
application should be requested from the manufacturer. Shielded inductors radiate less noise and are preferred.  
The saturation current must be greater than the sum of the maximum load current, and the worst case average-  
to-peak inductor current. Equation 13 shows the worst case conditions  
IOUTMAX  
ISAT  
>
+ IRIPPLE  
For Boost  
D‘  
VIN  
x
VOUT  
(VOUT - VIN)  
(2 x L x f)  
Where IRIPPLE  
=
(VOUT œ VIN)  
and D‘ = (1 - D)  
Where D =  
(VOUT  
)
•
•
•
•
•
•
•
IRIPPLE - peak inductor current  
IOUTMAX - maximum load current  
VIN - minimum input voltage in application  
L - min inductor value including worst case tolerances  
f - minimum switching frequency  
VOUT - output voltage  
D - Duty Cycle for CCM Operation  
(13)  
As a result, the inductor should be selected according to the ISAT. A more conservative and recommended  
approach is to choose an inductor that has a saturation current rating greater than the maximum current limit. A  
saturation current rating of at least 4.1 A is recommended for most applications. See Table 2 for recommended  
inductance value for the different switching frequency ranges. The inductor’s resistance should be less than  
300 mΩ for good efficiency.  
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See detailed information in Understanding Boost Power Stages in Switch Mode Power Supplies.  
Power Stage Desinger Tool can be used for the boost calculation.  
9.2.3.2 Output Capacitor Selection  
A ceramic capacitor with 2 × VMAX BOOST or more voltage rating is recommended for the output capacitor. The  
DC-bias effect can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance  
value selection. If the selected ceramic capacitors' voltage rating is less than 2 × VMAX BOOST, an alternative way  
is to increase the number of ceramic capacitors. Capacitance recommendations for different switching  
frequencies are shown in Table 2. To minimize audible noise of ceramic capacitors their physical size should  
typically be minimized.  
9.2.3.3 Input Capacitor Selection  
A ceramic capacitor with 2 × VIN MAX or more voltage rating is recommended for the input capacitor. The DC-bias  
effect can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance value  
selection. If the selected ceramic capacitors' voltage rating is less than 2 × VMAX BOOST, an alternative way is to  
increase the number of ceramic capacitors. Capacitance recommendations for different boost switching  
frequencies are shown in Table 2.  
9.2.3.4 LDO Output Capacitor  
A ceramic capacitor with at least 10-V voltage rating is recommended for the output capacitor of the LDO. The  
DC-bias effect can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance  
value selection. Typically a 1-µF capacitor is sufficient.  
9.2.3.5 Diode  
A Schottky diode should be used for the boost output diode. Do not use ordinary rectifier diodes, because slow  
switching speeds and long recovery times degrade the efficiency and the load regulation. Diode rating for peak  
repetitive current should be greater than inductor peak current (up to 4.1 A) to ensure reliable operation in boost  
mode. Average current rating should be greater than the maximum output current. Schottky diodes with a low  
forward drop and fast switching speeds are ideal for increasing efficiency. Choose a reverse breakdown voltage  
of the Schottky diode significantly larger than the output voltage. The junction capacitance of Schottky diodes are  
also very important. Big junction capacitance leads to huge reverse current and big noise when boost is  
switching. A <500-pF junction capacitance at VR= 0.1 V Schottky diode is recommended.  
9.2.4 Application Curves  
100  
96  
92  
88  
84  
80  
76  
VIN = 16V  
VIN = 12V  
72  
VIN = 8V  
VIN = 6V  
68  
80  
160  
240  
320  
400  
ƒsw=400 kHz, 22 μH  
Figure 23. LED Backlight Efficiency  
480  
Output Current (mA)  
D011  
Load 4 strings, VBoost = 30 V  
Figure 24. Typical Start-Up  
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9.2.5 SEPIC Mode Application  
When LED string voltage can be above or below VIN voltage, SEPIC configuration can be used. In this example,  
two separate coils or coupled coil could both be used for SEPIC. Separate coils can enable lower height external  
components to be used, compared to a coupled coil solution. On the other hand, coupled coil typically maximizes  
the efficiency. Also, in this example, an external clock is used to synchronize SEPIC switching frequency.  
External clock input can be modulated to spread switching frequency spectrum.  
VIN  
4.5...30 V  
D1  
Up to 20V  
COUT  
CIN BOOST  
L1  
C1  
R2  
R1  
C2  
SW  
SD  
VSENSE_N  
VIN  
FB  
CIN  
CLDO  
OUT1  
LDO  
LP8867-Q1  
OUT2  
OUT3  
RFSET  
FSET  
SYNC  
PWM  
OUT4  
BRIGHTNESS  
TSET  
VDDIO/EN  
FAULT  
TSENSE  
VDDIO/EN  
FAULT  
ISET  
R3  
VDDIO/EN  
PGND GND  
PAD  
RISET  
Figure 25. SEPIC Mode, 4 Strings 100-mA per String Configuration  
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9.2.5.1 Design Requirements  
Table 5. Design Requirements Table  
DESIGN PARAMETER  
VALUE  
VIN voltage range  
4.5 V – 30 V  
LED string  
4P4S LEDs (15 V max)  
LED string current  
100 mA  
Maxmum output voltage  
20 V  
SEPIC switching frequency  
2.2 MHz  
External sync for SEPIC  
used  
Spread spectrum  
Internal spread spectrum disabled (external sync used)  
L1, L2  
CIN  
4.7 μH  
10 µF 50 V  
CIN SEPIC  
C1  
2 × 10 µF, 50-V ceramic + 33 µF, 50-V electrolytic  
10-µF 50-V ceramic  
C2  
30 pF  
COUT  
CLDO  
RISET  
RFSET  
R1  
2 × 10 µF, 50-V ceramic + 33 µF, 50-V electrolytic  
1 µF, 10 V  
24 kΩ  
24 kΩ  
265 kΩ  
37 kΩ  
R2  
R3  
10 kΩ  
9.2.5.2 Detailed Design Procedure  
In SEPIC mode the maximum voltage at the SW pin is equal to the sum of the input voltage and the output  
voltage. Because of this, the maximum sum of input and output voltage must be limited below 49 V. See the  
Detailed Design Procedure section for general external component guidelines. Main differences of SEPIC  
compared to boost are described below.  
Power Stage Designer™ Tool can be used for modeling SEPIC behavior. For detailed explanation on SEPIC see  
Texas Instruments Analog Applications Journal Designing DC/DC Converters Based on SEPIC Topology.  
9.2.5.2.1 Inductor  
In SEPIC mode, currents flowing through the coupled inductors or the two separate inductors L1 and L2 are the  
input current and output current, respectively. Values can be calculated using Power Stage Designer™ Tool or  
using equations in Designing DC/DC Converters Based on SEPIC Topology.  
9.2.5.2.2 Diode  
In SEPIC mode diode peak current is equal to the sum of input and output currents. Diode rating for peak  
repetitive current should be greater than SW pin current limit (up to 4.1 A for transients) to ensure reliable  
operation in boost mode. Average current rating should be greater than the maximum output current. Diode  
voltage rating must be higher than sum of input and output voltages.  
9.2.5.2.3 Capacitor C1  
TI recommends a ceramic capacitor with low ESR. Capacitor voltage rating must be higher than maximum input  
voltage.  
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9.2.5.3 Application Curves  
90  
88  
86  
84  
82  
80  
78  
76  
74  
72  
70  
84  
82  
80  
78  
76  
74  
72  
70  
68  
66  
64  
VIN = 16V  
VIN = 12V  
VIN = 8V  
VIN = 6V  
VIN = 16V  
VIN = 12V  
VIN = 8V  
VIN = 6V  
80  
160  
240 320  
Output Current (mA)  
400  
480  
80  
160  
240 320  
Output Current (mA)  
400  
480  
D012  
D013  
4 strings, 4 LEDs per string  
fsw = 2.2 MHz  
4 strings, 4LEDs per string  
fsw = 2.2 MHz  
IHCL-4040DZ-5A 4.7 μH  
IHCL-4040DZ-5A 4.7 μH  
Figure 26. SEPIC Efficiency  
Figure 27. LED Backlight Efficiency  
10 Power Supply Recommendations  
The device is designed to operate from an automotive battery. Device should be protected from reversal voltage  
and voltage dump over 50 V. The resistance of the input supply rail must be low enough so that the input current  
transient does not cause a high drop at LP886x-Q1 VIN pin. If the input supply is connected by using long wires,  
additional bulk capacitance may be required in addition to the ceramic bypass capacitors in the VIN line.  
11 Layout  
11.1 Layout Guidelines  
Figure 28 is a layout recommendation for LP886x-Q1 used to demonstrate the principles of a good layout. This  
layout can be adapted to the actual application layout if or where possible. It is important that all boost  
components are close to the chip, and the high current traces must be wide enough. By placing boost  
components on one side of the chip it is easy to keep the ground plane intact below the high current paths. This  
way other chip pins can be routed more easily without splitting the ground plane. Bypass LDO capacitor must be  
placed as close as possible to the device.  
Here are some main points to help the PCB layout work:  
•
Current loops need to be minimized:  
–
For low frequency the minimal current loop can be achieved by placing the boost components as close as  
possible to the SW and PGND pins. Input and output capacitor grounds must be close to each other to  
minimize current loop size.  
–
Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact  
under the current traces. High-frequency return currents find a route with minimum impedance, which is  
the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when  
return current flows just under the positive current route in the ground plane, if the ground plane is intact  
under the route. To minimize the current loop for high frequencies:  
–
–
Inductor's pin in SW node needs to be as near as possible to chip's SW pin  
Put a small capacitor as near as possible to the diode's pin in boost output node and arrange vias to  
PGND plane close to the capacitor's GND pin.  
•
Use separate power and noise-free grounds. PGND is used for boost converter return current and noise-free  
ground is used for more sensitive signals, such as LDO bypass capacitor grounding as well as grounding the  
GND pin of the device.  
•
Boost output feedback voltage to LEDs must be taken out after the output capacitors, not straight from the  
diode cathode.  
•
Place LDO 1-µF bypass capacitor as close as possible to the LDO pin.  
32  
Submit Documentation Feedback  
Copyright © 2019–2020, Texas Instruments Incorporated  
Product Folder Links: LP8867-Q1 LP8869-Q1  
LP8867-Q1, LP8869-Q1  
www.ti.com  
SNVSB83B –JUNE 2019–REVISED JANUARY 2020  
Layout Guidelines (continued)  
•
Input and output capacitors require strong grounding (wide traces, many vias to GND plane).  
11.2 Layout Example  
RISENSE  
VIN  
RGS  
GND  
PGND  
1
2
VIN  
VSENSE_N  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
LDO  
FSET  
SD  
SW  
RFSET  
3
GND  
VDDIO/EN  
VBOOST  
4
PGND  
FB  
PGND  
FAULT  
SYNC  
5
6
OUT1  
OUT2  
OUT3  
OUT4  
GND  
PWM  
7
TSENSE  
8
PGND  
TSET  
RISET  
9
10  
ISET  
GND  
LED STRINGS  
Vias to PGND Plane  
The only Connection points  
between GND & PGND  
Figure 28. LP886x-Q1 Boost Layout  
Copyright © 2019–2020, Texas Instruments Incorporated  
Submit Documentation Feedback  
33  
Product Folder Links: LP8867-Q1 LP8869-Q1  
LP8867-Q1, LP8869-Q1  
SNVSB83B –JUNE 2019–REVISED JANUARY 2020  
www.ti.com  
12 Device and Documentation Support  
12.1 Device Support  
12.1.1 Development Support  
Power Stage Designer™ Tool can be used for both boost and SEPIC: Power Stage Designer™ Tool  
12.2 Documentation Support  
12.2.1 Related Documentation  
For related documentation see the following:  
•
•
•
•
PowerPAD™ Thermally Enhanced Package  
Understanding Boost Power Stages in Switch Mode Power Supplies  
Designing DC-DC Converters Based on SEPIC Topology  
TI E2E™ support forums  
12.3 Receiving Notification of Documentation Updates  
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper  
right corner, click on Alert me to register and receive a weekly digest of any product information that has  
changed. For change details, review the revision history included in any revised document.  
12.4 Community Resources  
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight  
from the experts. Search existing answers or ask your own question to get the quick design help you need.  
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do  
not necessarily reflect TI's views; see TI's Terms of Use.  
12.5 Trademarks  
Power Stage Designer, E2E are trademarks of Texas Instruments.  
Excel is a registered trademark of Microsoft Corporation.  
All other trademarks are the property of their respective owners.  
12.6 Electrostatic Discharge Caution  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
12.7 Glossary  
SLYZ022 — TI Glossary.  
This glossary lists and explains terms, acronyms, and definitions.  
13 Mechanical, Packaging, and Orderable Information  
The following pages include mechanical, packaging, and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
34  
Submit Documentation Feedback  
Copyright © 2019–2020, Texas Instruments Incorporated  
Product Folder Links: LP8867-Q1 LP8869-Q1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
LP8867QPWPRQ1  
LP8869QPWPRQ1  
ACTIVE  
ACTIVE  
HTSSOP  
HTSSOP  
PWP  
PWP  
20  
20  
2000 RoHS & Green  
2000 RoHS & Green  
NIPDAU  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
-40 to 125  
-40 to 125  
8867Q  
8869Q  
NIPDAU  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
8-Jun-2023  
TAPE AND REEL INFORMATION  
REEL DIMENSIONS  
TAPE DIMENSIONS  
K0  
P1  
W
B0  
Reel  
Diameter  
Cavity  
A0  
A0 Dimension designed to accommodate the component width  
B0 Dimension designed to accommodate the component length  
K0 Dimension designed to accommodate the component thickness  
Overall width of the carrier tape  
W
P1 Pitch between successive cavity centers  
Reel Width (W1)  
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE  
Sprocket Holes  
Q1 Q2  
Q3 Q4  
Q1 Q2  
Q3 Q4  
User Direction of Feed  
Pocket Quadrants  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
LP8867QPWPRQ1  
LP8869QPWPRQ1  
HTSSOP PWP  
HTSSOP PWP  
20  
20  
2000  
2000  
330.0  
330.0  
16.4  
16.4  
6.95  
6.95  
7.0  
7.0  
1.4  
1.4  
8.0  
8.0  
16.0  
16.0  
Q1  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
8-Jun-2023  
TAPE AND REEL BOX DIMENSIONS  
Width (mm)  
H
W
L
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
LP8867QPWPRQ1  
LP8869QPWPRQ1  
HTSSOP  
HTSSOP  
PWP  
PWP  
20  
20  
2000  
2000  
356.0  
356.0  
356.0  
356.0  
35.0  
35.0  
Pack Materials-Page 2  
IMPORTANT NOTICE AND DISCLAIMER  
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE  
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, regulatory or other requirements.  
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an  
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license  
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you  
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these  
resources.  
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with  
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for  
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2023, Texas Instruments Incorporated  

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