LPV511MGX/NOPB [TI]

单路、12V、27kHz 运算放大器 | DCK | 5 | -40 to 85;


型号：	LPV511MGX/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	单路、12V、27kHz 运算放大器 \| DCK \| 5 \| -40 to 85 放大器光电二极管运算放大器
文件：	总27页 (文件大小：1215K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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LPV511

SNOSAG7D –AUGUST 2005–REVISED AUGUST 2016

LPV511 Micropower, Rail-to-Rail Input and Output Operational Amplifier

1 Features

3 Description

The LPV511 is a micropower operational amplifier

that operates from a voltage supply range as wide as

2.7 V to 12 V with ensured specifications at 3 V, 5 V,

and 12 V. The ultra-low power LPV511 exhibits an

excellent speed to power ratio, drawing only 880 nA

of supply current with a bandwidth of 27 kHz. These

specifications make the LPV511 an ideal choice for

battery-powered systems that require long life

through low supply current, such as instrumentation,

sensor conditioning and battery current monitoring.

•

Wide Supply Voltage Range: 2.7 V to 12 V

Slew Rate: 7.7 V/ms

•

Supply Current: 880 nA

Output Short-Circuit Current: 1.35 mA

Rail-to-Rail Input

Rail-to-Rail Output: 100 mV from Rails

Bandwidth (C_L= 50 pF, R_L= 1 MΩ): 27 kHz

Unity Gain Stable

The LPV511 has an input range that includes both

supply rails for ground and high-side battery sensing

applications. The LPV511 output swings within 100

mV of either rail to maximize the signal's dynamic

range in low supply applications. In addition, the

output is capable of sourcing 650 µA of current when

2 Applications

•

Battery Powered Systems

Security Systems

Micropower Thermostats

Solar Powered Systems

Portable Instrumentation

Micropower Filters

The LPV511 is fabricated on TI's advanced VIP50C

process.

The LPV511 is available in the space-saving SC70

package, which makes it ideal for portable electronics

with area-constrained PC boards.

Remote Sensor Amplifiers

Device Information⁽¹⁾

PART NUMBER

LPV511

PACKAGE

BODY SIZE (NOM)

SC70 (5)

2.00 mm × 1.25 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Typical Supply Current

High-Side Battery Current Sensor

V⁺

1.6

1.4

125°/

R₁

2 kΩ

85º/

1.2

R_SENSE

R₂

0.2 Ω

2N3906

25°/

2 kΩ

0.8

0.6

0.4

-40°/

V_OUT

Load

R₃

10 kΩ

I_CHARGE

0.2

SENSE ì R₃

V_OUT

ì I_CHARGE= 1W ì I_CHARGE

SUPPLY VOLTAGE (V)

R₁

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LPV511

SNOSAG7D –AUGUST 2005–REVISED AUGUST 2016

www.ti.com

Table of Contents

7.4 Device Functional Modes........................................ 14

Application and Implementation ........................ 16

8.1 Application Information............................................ 16

8.2 Typical Applications ................................................ 16

8.3 Dos and Don'ts ....................................................... 17

Power Supply Recommendations...................... 18

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics: 3 V ................................... 5

6.6 Electrical Characteristics: 5 V ................................... 6

6.7 Electrical Characteristics: 12 V ................................ 7

6.8 Typical Characteristics.............................................. 9

Detailed Description ............................................ 14

7.1 Overview ................................................................. 14

7.2 Functional Block Diagram ....................................... 14

7.3 Feature Description................................................. 14

10 Layout................................................................... 18

10.1 Layout Guidelines ................................................. 18

10.2 Layout Example .................................................... 18

11 Device and Documentation Support ................. 19

11.1 Device Support .................................................... 19

11.2 Documentation Support ....................................... 19

11.3 Community Resource............................................ 19

11.4 Trademarks........................................................... 19

11.5 Electrostatic Discharge Caution............................ 19

11.6 Glossary................................................................ 19

12 Mechanical, Packaging, and Orderable

Information ........................................................... 19

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (March 2013) to Revision D

Page

•

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section ................................................................................................. 1

•

Added Thermal Information table .......................................................................................................................................... 4

Changes from Revision B (March 2013) to Revision C

Page

•

Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1

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SNOSAG7D –AUGUST 2005–REVISED AUGUST 2016

5 Pin Configuration and Functions

DCK Package

5-Pin SC70

Top View

V_OUT

V^-

V⁺

V_IN

Pin Functions

I/O

DESCRIPTION

NO.

NAME

V_OUT

V^–

Output

Negative supply voltage

Noninverting input

Inverting input

V_IN

–

V_IN

V⁺

Positive supply voltage

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SNOSAG7D –AUGUST 2005–REVISED AUGUST 2016

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

V⁺+ 0.3

–65

MAX

2.1

UNIT

V_INDifferential

Supply voltage (V⁺- V⁻)

Voltage at input and output pins

Short-circuit duration

13.2

V⁻− 0.3

See⁽³⁾

(4)

Junction temperature, T_J

150

°C

Storage temperature, T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3) Output short-circuit duration is infinite for V⁺< 6 V at room temperature and below. For V⁺> 6 V, allowable short-circuit duration is 1.5

ms.

(4) The maximum power dissipation is a function of T_J(MAX), R_θJA, and T_A. The maximum allowable power dissipation at any ambient

temperature is P_D= (T_J(MAX)– T_A) / R_θJA. All numbers apply for packages soldered directly onto a PC board.

6.2 ESD Ratings

VALUE

±2000

±200

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾⁽²⁾

Machine model (MM)⁽³⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) Human Body Model: 1.5 kΩ in series with 100 pF.

(3) Machine Model: 0 Ω in series with 200 pF.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

–40

2.7

MAX

UNIT

Temperature⁽¹⁾

Supply voltage (V⁺– V⁻)

°C

(1) The maximum power dissipation is a function of T_J(MAX), R_θJA, and T_A. The maximum allowable power dissipation at any ambient

temperature is P_D= (T_J(MAX)– T_A) / R_θJA. All numbers apply for packages soldered directly onto a PC board.

6.4 Thermal Information

LPV511

THERMAL METRIC⁽¹⁾

DCK (SC70)

UNIT

5 PINS

278

105.8

56.4

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

R_θJC(bot)

n/a

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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SNOSAG7D –AUGUST 2005–REVISED AUGUST 2016

6.5 Electrical Characteristics: 3 V

Unless otherwise specified, all limits are specified for T_J= 25°C, V⁺= 3 V, V⁻= 0 V, V_CM= V_O= V⁺/2, and R_L= 100 kΩ to

V⁺/2.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN⁽²⁾

TYP⁽³⁾

MAX⁽²⁾

±3

UNIT

T_J= 25°C

±0.2

V_OS

Input offset voltage

T_J= –40°C to 85°C

T_J= 25°C

±3.8

±0.3

–320

110

TC V_OS

Input offset voltage drift⁽⁴⁾

µV/°C

T_J= –40°C to 85°C

±15

T_J= 25°C

–1000

–1600

V_CM= 0.5 V

V_CM= 2.5 V

T_J= –40°C to 85°C

T_J= 25°C

I_B

Input bias current⁽⁵⁾

Input offset current

800

T_J= –40°C to 85°C

1900

I_OS

±10

100

T_J= 25°C

V_CMStepped from 0 V to

1.5 V

T_J= –40°C to 85°C

T_J= 25°C

115

V_CMStepped from 2.4 V

to 3 V

CMRR

Common mode rejection ratio

T_J= –40°C to 85°C

T_J= 25°C

V_CMStepped from 0.5 V

to 2.5 V

T_J= –40°C to 85°C

T_J= 25°C

V⁺= 2.7 V to 5 V,

V_CM= 0.5 V

114

115

117

T_J= –40°C to 85°C

T_J= 25°C

V⁺= 3 V to 5 V,

V_CM= 0.5 V

PSRR

Power supply rejection ratio

T_J= –40°C to 85°C

T_J= 25°C

V⁺= 5 V to 12 V,

V_CM= 0.5 V

T_J= –40°C to 85°C

T_J= 25°C

−0.1

3.1

CMVR

A_VOL

Input common-mode voltage CMRR ≥ 50 dB

T_J= –40°C to 85°C

T_J= 25°C

105

2.9

Sinking, V_O= 2.5 V

Large signal voltage gain

T_J= –40°C to 85°C

T_J= 25°C

Sourcing, V_O= 0.5 V

T_J= –40°C to 85°C

T_J= 25°C

2.85

2.8

Output swing high

Output swing low

V_ID= 100 mV

T_J= –40°C to 85°C

T_J= 25°C

V_O

100

150

200

V_ID= −100 mV

T_J= –40°C to 85°C

Sourcing

V_ID= 100 mV

−500

−225

I_SC

Output short circuit current⁽⁶⁾

µA

Sinking

V_ID= −100 mV

225

1350

0.88

T_J= 25°C

1.2

1.5

I_S

Supply current

Slew rate⁽⁷⁾

µA

T_J= –40°C to 85°C

T_J= 25°C

5.25

3.10

7.7

A_V= 1, V_Oramps from

0.5 V to 2.5 V

V/ms

T_J= –40°C to 85°C

(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very

limited self-heating of the device.

(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the

Statistical Quality Control (SQC) method.

(3) Typical values represent the most likely parametric norm at the time of characterization.

(4) Offset voltage drift is specified by design and/or characterization and is not tested in production. Offset voltage drift is determined by

dividing the change in VOS at temperature extremes into the total temperature change.

(5) Positive current corresponds to current flowing into the device.

(6) The Short-Circuit Test is a momentary test. See Note 3 in Absolute Maximum Ratings.

(7) Slew rate is the average of the rising and falling slew rates.

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Electrical Characteristics: 3 V (continued)

Unless otherwise specified, all limits are specified for T_J= 25°C, V⁺= 3 V, V⁻= 0 V, V_CM= V_O= V⁺/2, and R_L= 100 kΩ to

V⁺/2.⁽¹⁾

PARAMETER

TEST CONDITIONS

R_L= 1 MΩ, C_L= 50 pF

MIN⁽²⁾

TYP⁽³⁾

MAX⁽²⁾

UNIT

kHz

GBW

Gain bandwidth product

Phase margin

R_L= 1 MΩ, C_L= 50 pF

f = 100 Hz

e_n

i_n

Input-referred voltage noise

320

0.02

0.01

nV/√Hz

f = 10 Hz

Input-referred current noise

pA/√Hz

f = 1 kHz

6.6 Electrical Characteristics: 5 V

Unless otherwise specified, all limits are specified for T_J= 25°C, V⁺= 5 V, V⁻= 0 V, V_CM= V_O= V⁺/2, and R_L= 100 kΩ to

V⁺/2.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN⁽²⁾

TYP⁽³⁾

MAX⁽²⁾

±3

UNIT

T_J= 25°C

±0.2

V_OS

Input offset voltage

T_J= –40°C to 85°C

T_J= 25°C

±3.8

±0.3

–320

110

TC V_OS

Input offset voltage drift⁽⁴⁾

µV/°C

T_J= –40°C to 85°C

±15

T_J= 25°C

–1000

–1600

V_CM= 0.5 V

V_CM= 4.5 V

T_J= –40°C to 85°C

T_J= 25°C

I_B

Input bias current⁽⁵⁾

Input offset current

800

T_J= –40°C to 85°C

1900

I_OS

±10

115

T_J= 25°C

—0.1

V_CMStepped from

0 V to 2.5 V

T_J= –40°C to 85°C

T_J= 25°C

107

V_CMStepped from

4.4 to 5 V

CMRR

Common mode rejection ratio

T_J= –40°C to 85°C

T_J= 25°C

V_CMStepped from

0.5 to 4.5 V

T_J= –40°C to 85°C

T_J= 25°C

V⁺= 2.7 V to 5 V,

V_CM= 0.5 V

114

115

117

T_J= –40°C to 85°C

T_J= 25°C

V⁺= 3 V to 5 V,

V_CM= 0.5 V

PSRR

Power supply rejection ratio

T_J= –40°C to 85°C

T_J= 25°C

V⁺= 5 V to 12 V,

V_CM= 0.5 V

T_J= –40°C to 85°C

T_J= 25°C

5.1

CMVR

A_VOL

Input common-mode voltage CMRR ≥ 50 dB

T_J= –40°C to 85°C

T_J= 25°C

110

Sinking, V_O= 4.5 V

Large signal voltage gain

T_J= –40°C to 85°C

T_J= 25°C

Sourcing, V_O= 0.5 V

T_J= –40°C to 85°C

(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very

limited self-heating of the device.

(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the

Statistical Quality Control (SQC) method.

(3) Typical values represent the most likely parametric norm at the time of characterization.

(4) Offset voltage drift is specified by design and/or characterization and is not tested in production. Offset voltage drift is determined by

dividing the change in VOS at temperature extremes into the total temperature change.

(5) Positive current corresponds to current flowing into the device.

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SNOSAG7D –AUGUST 2005–REVISED AUGUST 2016

Electrical Characteristics: 5 V (continued)

Unless otherwise specified, all limits are specified for T_J= 25°C, V⁺= 5 V, V⁻= 0 V, V_CM= V_O= V⁺/2, and R_L= 100 kΩ to

V⁺/2.⁽¹⁾

PARAMETER

TEST CONDITIONS

T_J= 25°C

MIN⁽²⁾

4.8

TYP⁽³⁾

MAX⁽²⁾

UNIT

4.89

Output swing high

V_ID= 100 mV

T_J= –40°C to 85°C

T_J= 25°C

4.75

V_O

110

200

250

Output swing low

V_ID= −100 mV

µA

T_J= –40°C to 85°C

Sourcing to V⁻

V_ID= 100 mV

Sinking to V⁺

–550

–225

I_SC

Output short circuit current⁽⁶⁾

225

1350

0.97

V_ID= −100 mV

T_J= 25°C

1.2

1.5

I_S

Supply current

Slew rate⁽⁷⁾

µA

T_J= –40°C to 85°C

T_J= 25°C

5.25

3.1

7.5

A_V= 1, V_Oramps from

0.5 V to 4.5 V

V/ms

T_J= –40°C to 85°C

GBW

Gain bandwidth product

Phase margin

R_L= 1 MΩ, C_L= 50 pF

f = 100 Hz

kHz

e_n

i_n

Input-referred voltage noise

320

0.02

0.01

nV/√Hz

f = 10 Hz

Input-referred current noise

pA/√Hz

f = 1 kHz

(6) The Short-Circuit Test is a momentary test. See Note 3 in Absolute Maximum Ratings.

(7) Slew rate is the average of the rising and falling slew rates.

6.7 Electrical Characteristics: 12 V

Unless otherwise specified, all limits are specified for T_J= 25°C, V⁺= 12 V, V⁻= 0 V, V_CM= V_O= V⁺/2, and R_L= 100 kΩ to

V⁺/2.⁽¹⁾

(3)

(2)

PARAMETER

TEST CONDITIONS

MIN⁽²⁾

TYP

MAX

UNIT

T_J= 25°C

±0.2

±0.3

−320

110

±3

V_OS

Input offset voltage

T_J= –40°C to 85°C

T_J= 25°C

±3.8

TC V_OSInput offset voltage drift⁽⁴⁾

µV/°C

T_J= –40°C to 85°C

±15

T_J= 25°C

−1000

−1600

V_CM= 0.5 V

T_J= –40°C to 85°C

T_J= 25°C

I_B

Input bias current⁽⁵⁾

Input offset current

800

V_CM= 11.5 V

T_J= –40°C to 85°C

1900

I_OS

±10

115

T_J= 25°C

V_CMStepped from

0 V to 6 V

T_J= –40°C to 85°C

T_J= 25°C

110

V_CMStepped from

11.4 V to 12 V

CMRR Common mode rejection ratio

T_J= –40°C to 85°C

T_J= 25°C

V_CMStepped from

0.5 V to 11.5 V

T_J= –40°C to 85°C

(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very

limited self-heating of the device.

(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the

Statistical Quality Control (SQC) method.

(3) Typical values represent the most likely parametric norm at the time of characterization.

(4) Offset voltage drift is specified by design and/or characterization and is not tested in production. Offset voltage drift is determined by

dividing the change in VOS at temperature extremes into the total temperature change.

(5) Positive current corresponds to current flowing into the device.

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Electrical Characteristics: 12 V (continued)

Unless otherwise specified, all limits are specified for T_J= 25°C, V⁺= 12 V, V⁻= 0 V, V_CM= V_O= V⁺/2, and R_L= 100 kΩ to

V⁺/2.⁽¹⁾

(3)

(2)

PARAMETER

TEST CONDITIONS

MIN⁽²⁾

TYP

MAX

UNIT

V⁺= 2.7 V to 5 V,

T_J= 25°C

114

115

117

V_CM= 0.5 V

T_J= –40°C to 85°C

T_J= 25°C

V⁺= 3 V to 5 V,

V_CM= 0.5 V

PSRR

Power supply rejection ratio

T_J= –40°C to 85°C

T_J= 25°C

V⁺= 5 V to 12 V,

V_CM= 0.5 V

T_J= –40°C to 85°C

T_J= 25°C

−0.1

12.1

CMVR Input common-mode voltage

CMRR ≥ 50 dB

T_J= –40°C to 85°C

T_J= 25°C

110

Sinking, V_O= 0.5 V

Sourcing, V_O= 11.5 V

V_ID= 100 mV

T_J= –40°C to 85°C

T_J= 25°C

A_VOL

Large signal voltage gain

T_J= –40°C to 85°C

T_J= 25°C

11.8

11.72

11.85

150

Output swing high

Output swing low

T_J= –40°C to 85°C

T_J= 25°C

V_O

200

280

V_ID= −100 mV

T_J= –40°C to 85°C

Sourcing

V_ID= 100 mV

−650

−200

I_SC

Output short circuit current⁽⁶⁾

µA

Sinking

V_ID= −100 mV

200

1300

1.2

T_J= 25°C

1.75

2.5

I_S

Supply current

Slew rate⁽⁷⁾

µA

T_J= –40°C to 85°C

5.25

3.1

A_V= 1, V_Oramped from 1 V to 11 V

V/ms

GBW

Gain bandwidth product

Phase margin

R_L= 1 MΩ, C_L= 50 pF

f = 100 Hz

kHz

e_n

i_n

Input-referred voltage noise

320

0.02

0.01

nV/√Hz

f = 10 Hz

Input-referred current noise

pA/√Hz

f = 1 kHz

(6) The Short-Circuit Test is a momentary test. See Note 3 in Absolute Maximum Ratings.

(7) Slew rate is the average of the rising and falling slew rates.

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SNOSAG7D –AUGUST 2005–REVISED AUGUST 2016

6.8 Typical Characteristics

At T_J= 25°C, unless otherwise specified.

1.6

125°/

= 3V

1.4

0.8

0.6

85º/

1.2

-40°C

0.4

0.2

25°/

0.8

0.6

0.4

25°C

-40°/

-0.2

-0.4

0.2

85ºC

SUPPLY VOLTAGE (V)

(V)

Figure 1. Supply Current vs Supply Voltage

Figure 2. Input Offset Voltage vs Input Common Mode

= 12V

= 5V

0.8

0.6

0.4

0.8

0.6

-40°C

0.4

0.2

25°C

85°C

-0.2

-0.4

-0.6

85°C

-0.2

-0.4

(V)

Figure 3. Input Offset Voltage vs Input Common Mode

Figure 4. Input Offset Voltage vs Input Common Mode

= 5V

V = 5V

1.8

1.6

1.4

1.2

4.5

85°C

125°C

25°C

3.5

-40°C

85°C

25°C

2.5

-40°C

0.8

0.6

0.4

0.2

1.5

125°C

-40°C

0.5

0.1

OUTPUT VOLTAGE REFERENCED TO V (V)

Figure 5. Sourcing Current vs Output Voltage

Figure 6. Sinking Current vs Output Voltage

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Typical Characteristics (continued)

At T_J= 25°C, unless otherwise specified.

4.5

= 12V

85°C

1.8

1.6

1.4

1.2

125°C

25°C

3.5

85°C

25°C

-40°C

2.5

-40°C

0.8

0.6

0.4

0.2

125°C

1.5

-40°C

0.5

0.1

100

0.1

100

OUTPUT VOLTAGE REFERENCED TO V (V)

Figure 7. Sourcing Current vs Output Voltage

Figure 8. Sinking Current vs Output Voltage

700

500

125°C

400

= 3V

125°C

500

300

-40°C

300

200

25°C

85°C

100

25°C

-40°C

-100

-300

-500

-100

-200

-300

85°C

125°C

2.5

125°C

= 5V

0.5

1.5

(V)

Figure 9. Input Bias Current vs Common Mode Voltage

Figure 10. Input Bias Current vs Common Mode Voltage

100

500

= 12V

125°C

400

-40°C

300

200

100

25°C

85°C

-100

-200

125°C

100

10k

(V)

FREQUENCY (Hz)

Figure 11. Input Bias Current vs Common Mode Voltage

Figure 12. PSRR vs Frequency

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Typical Characteristics (continued)

At T_J= 25°C, unless otherwise specified.

203

180

160

140

120

100

= 2.7V

= 5V

160

140

120

100

180

158

135

180

158

135

= 20 pF

= 1 MW

= 20 pF

= 1 MW

113

tI!{9

D!Lb

tI!{9

D!Lb

25°C

-40°C

125°C

-20

100

-23

-20

100

-23

10k

100k

10k

100k

FREQUENCY (Hz)

Figure 13. Frequency Response vs Temperature

Figure 14. Frequency Response vs Temperature

203

180

158

135

180

160

140

120

100

203

180

158

135

180

160

140

120

100

= ±6V

= 2.7V

= 20 pF

= 1 MW

= 20 pF

113

PHASE

GAIN

tI!{9

D!Lb

= 10 MW

25°C

-40°C

125°C

= 1 MW

-20

100

-23

-20

100

-23

10k

100k

10k

100k

FREQUENCY (Hz)

Figure 15. Frequency Response vs Temperature

Figure 16. Frequency Response vs R_L

203

180

158

135

180

160

140

120

100

203

180

158

135

113

180

160

140

120

100

= 5V

= ±6V

= 20 pF

113

tI!{9

D!Lb

PHASE

GAIN

= 10 MW

R = 10 MW

= 1 MW

-20

100

-23

-20

100

-23

10k

100k

10k

100k

FREQUENCY (Hz)

Figure 17. Frequency Response vs R_L

Figure 18. Frequency Response vs R_L

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Typical Characteristics (continued)

At T_J= 25°C, unless otherwise specified.

180

203

180

158

135

113

180

160

140

120

100

203

180

158

135

113

= 2.7V

= 5V

160

140

120

100

= 1 MW

= 100 pF

PHASE

= 50 pF

= 20 pF

= 200 pF

= 20 pF

GAIN

-20

100

-23

-20

100

-23

10k

100k

10k

100k

FREQUENCY (Hz)

Figure 19. Frequency Response vs C_L

Figure 20. Frequency Response vs C_L

900

180

170

150

130

110

= ±6V

= 5V

160

140

120

100

800

700

600

= 1 MW

tI!{9

= 100 pF

500

400

300

200

100

= 50 pF

= 200 pF

= 20 pF 30

D!Lb

-10

-20

100

-30

0.1

100

10k

100k

FREQUENCY (Hz)

Figure 22. Voltage Noise vs Frequency

Figure 21. Frequency Response vs C_L

= 5V

INPUT

= 5V

OUTPUT

200 ms/DIV

Figure 23. Noninverting Small-Signal Pulse Response

Figure 24. Noninverting Large-Signal Pulse Response

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Typical Characteristics (continued)

At T_J= 25°C, unless otherwise specified.

INPUT

OUTPUT

= 5V

200 ms/DIV

Figure 25. Inverting Small-Signal Pulse Response

Figure 26. Inverting Large-Signal Pulse Response

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7 Detailed Description

7.1 Overview

The LPV511 is a micropower operational amplifier that operates from a voltage supply range as wide as 2.7 V to

12 V with ensured specifications at 3 V, 5 V, and 12 V. The LPV511 exhibits an excellent speed-to-power ratio,

drawing only 880 nA of supply current with a bandwidth of 27 kHz.

7.2 Functional Block Diagram

V_CC

CLASS AB

OUTPUT

CONTROL

INN

INP

GND

7.3 Feature Description

The LPV511 has a rail-to-rail input which provides more flexibility for the system designer. As can be seen from

Functional Block Diagram, rail-to-rail input is achieved by using in parallel, one PNP differential pair and one

NPN differential pair. When the common mode input voltage (V_CM) is near V⁺, the NPN pair is on and the PNP

pair is off. When V_CMis near V⁻, the NPN pair is off and the PNP pair is on. When V_CMis between V⁺and V⁻,

internal logic decides how much current each differential pair will get. This special logic ensures stable and low

distortion amplifier operation within the entire common mode voltage range.

7.4 Device Functional Modes

7.4.1 Input Stage

Because both input stages have their own offset voltage (V_OS) characteristic, the offset voltage of the LPV511

becomes a function of V_CM. V_OShas a crossover point at 1 V below V⁺. See the V_OSvs V_CMcurve in Typical

Characteristics. Caution must be taken in situations where the input signal amplitude is comparable to the V_OS

value and/or the design requires high accuracy. In these situations, it is necessary for the input signal to avoid

the crossover point.

The input bias current, I_Bwill change in value and polarity as the input crosses the transition region. In addition,

parameters such as PSRR and CMRR which involve the input offset voltage will also be affected by changes in

V_CMacross the differential pair transition region.

Differential input voltage is the difference in voltage between the noninverting (+) input and the inverting input (−)

of the op amp. Due to the three series diodes across the two inputs, the absolute maximum differential input

voltage is ±2.1 V. This may not be a problem to most conventional op amp designs; however, designers must

avoid using the LPV511 as a comparator.

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Device Functional Modes (continued)

7.4.2 Output Stage

The LPV511 output voltage swing 100 mV from rails at 3-V supply, which provides the maximum possible

dynamic range at the output. This is particularly important when operating on low supply voltages.

The LPV511 maximum output voltage swing defines the maximum swing possible under a particular output load.

The LPV511 output swings 110 mV from the rail at 5-V supply with an output load of 100 kΩ.

7.4.3 Driving Capacitive Load

The LPV511 is internally compensated for stable unity gain operation, with a 27-kHz typical gain bandwidth.

However, the unity gain follower is the most sensitive configuration to capacitive load. Direct capacitive loading

reduces the phase margin of the op amp. When the output is required to drive a large capacitive load, greater

than 100 pF, a small series resistor at the output of the amplifier improves the phase margin (see Figure 27).

In Figure 27, the isolation resistor R_ISOand the load capacitor C_Lform a pole to increase stability by adding more

phase margin to the overall system. The desired performance depends on the value of R_ISO. The bigger the R_ISO

resistor value, the more stable V_OUTwill be. But the DC accuracy is degraded when the R_ISOgets bigger. If there

were a load resistor in Figure 27, the output voltage would be divided by R_ISOand the load resistor.

R_ISO

V_OUT

V_IN

Figure 27. Resistive Isolation of Capacitive Load

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LPV511 is fabricated with Texas Instrument's state-of-the-art VIP50C process.

8.2 Typical Applications

8.2.1 Battery Current Sensing

The rail-to-rail common mode input range and the very low quiescent current make the LPV511 ideal to use in

high-side and low-side battery current sensing applications. The high-side current sensing circuit in Figure 28 is

commonly used in a battery charger to monitor the charging current to prevent over charging. A sense resistor

R_SENSEis connected to the battery directly.

V⁺

R₁

2 kΩ

R_SENSE

R₂

0.2 Ω

2N3906

2 kΩ

V_OUT

Load

R₃

10 kΩ

I_CHARGE

SENSE ì R₃

V_OUT

ì I_CHARGE= 1W ì I_CHARGE

R₁

Figure 28. High Side Current Sensing

8.2.1.1 Design Requirements

The high-side current-sensing circuit (Figure 28) is commonly used in a battery charger to monitor charging

current to prevent overcharging. A sense resistor RSENSE is connected to the battery directly. This system

requires an op amp with rail-to-rail input. The LPV511 ideal for this application because its common-mode input

range extends up to the positive supply.

8.2.1.2 Detailed Design Procedure

As seen in Figure 28, the I_CHARGEcurrent flowing through sense resistor R_SENSEdevelops a voltage drop equal to

V_SENSE. The voltage at the negative sense point will now be less than the positive sense point by an amount

proportional to the V_SENSEvoltage.

The low-bias currents of the LPV511 cause little voltage drop through R₂, so the negative input of the LPV551

amplifier is at essentially the same potential as the negative sense input.

The LPV511 will detect this voltage error between its inputs and servo the transistor base to conduct more

current through Q1, increasing the voltage drop across R₁until the LPV511 inverting input matches the

noninverting input. At this point, the voltage drop across R₁now matches V_SENSE

I_G, a current proportional to I_CHARGE, will flow according to the following relation to:

I_G= V_RSENSE/ R₁= ( R_SENSE× I_CHARGE) / R₁

(1)

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Typical Applications (continued)

I_Galso flows through the gain resistor R₃developing a voltage drop equal to:

V₃= I_G× R₃= ( V_RSENSE/ R₁) × R₃= ( ( R_SENSE× I_CHARGE) / R₂) × R₃

V_OUT= (R_SENSE× I_CHARGE) × G

(2)

(3)

where

•

G = R₃/ R₁

8.2.1.3 Application Curve

Figure 29 shows the results of the example current sense circuit.

C001

(A)

CHARGE

The error after 4 V where transistor Q1 runs out of headroom and saturates, limiting the upper output swing.

Figure 29. Current Sense Amplifier Results

8.2.2 Summing Amplifier

The LPV511 operational amplifier is a perfect fit in a summing amplifier circuit because of the rail-to-rail input and

output and the sub-micro Amp quiescent current. In this configuration, the amplifier outputs the sum of the three

input voltages.

Equation 4 shows the ratio of the sum and the output voltage is defined using feedback and input resistors.

≈

∆

_∆V_REF- V₁V_REF- V₂V_REF- V₃

REF

V_OUT= R_F

∆

≈

R₁

R₂

R₃

(4)

R₁

R₂

R₃

V₁

R_F

V₂

V₃

V_OUT

V_REF

Figure 30. Summing Amplifier Circuit

8.3 Dos and Don'ts

Do properly bypass the power supplies.

Do add series resistence to the output when driving capacitive loads, particularly cables, Muxes and ADC inputs.

Do add series current limiting resistors and external Schottky clamp diodes if input voltage is expected to exceed

the supplies. Limit the current to 1 mA or less (1 kΩ per volt).

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9 Power Supply Recommendations

The LPV80x is specified for operation from 1.6 V to 5.5 V (±0.8 V to ±2.75 V) over a –40°C to 125°C temperature

range. Parameters that can exhibit significant variance with regard to operating voltage or temperature are

presented in the Electrical Characteristics: 3 V.

CAUTION

Supply voltages larger than 13.2 V can permanently damage the device.

For proper operation, the power supplies bust be properly decoupled. For decoupling the supply lines it is

suggested that 100 nF capacitors be placed as close as possible to the operational amplifier power supply pins.

For single supply, place a capacitor between V⁺and V^–supply leads. For dual supplies, place one capacitor

between V⁺and ground, and one capacitor between V^–and ground.

Low bandwidth nanopower devices do not have good high frequency (> 1 kHz) AC PSRR rejection against high-

frequency switching supplies and other 1 kHz and above noise sources, so extra supply filtering is recommended

if kilohertz or above noise is expected on the power supply lines.

10 Layout

10.1 Layout Guidelines

•

The V⁺pin should be bypassed to ground with a low-ESR capacitor.

The optimum placement is closest to the V⁺and ground pins.

Take care to minimize the loop area formed by the bypass capacitor connection between V⁺and ground.

The ground pin should be connected to the PCB ground plane at the pin of the device.

The feedback components should be placed as close to the device as possible minimizing strays.

10.2 Layout Example

Figure 31. SOT-23 Layout Example

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

LPV511 PSPICE Model, http://www.ti.com/lit/zip/snom023

TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti

DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm

TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm

TI Filterpro Software, http://www.ti.com/tool/filterpro

11.2 Documentation Support

11.2.1 Related Documentation

•

Handbook of Operational Amplifier Applications (SBOA092)

Compensate Transimpedance Amplifiers Intuitively (SBOA055)

Circuit Board Layout Techniques (SLOA089)

AN-1803 Design Considerations for a Transimpedance Amplifier (SNOA515)

11.3 Community Resource

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LPV511MG/NOPB

LPV511MGX/NOPB

ACTIVE

SC70

DCK

1000 RoHS & Green

3000 RoHS & Green

Level-1-260C-UNLIM

-40 to 85

A91

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

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10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Oct-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LPV511MG/NOPB

LPV511MGX/NOPB

SC70

DCK

1000

3000

178.0

8.4

2.25

2.45

1.2

4.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Oct-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LPV511MG/NOPB

LPV511MGX/NOPB

SC70

DCK

1000

3000

208.0

191.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

DCK0005A

SOT - 1.1 max height

SMALL OUTLINE TRANSISTOR

2.4

1.8

0.1 C

1.4

1.1

1.1 MAX

PIN 1

INDEX AREA

NOTE 4

(0.15)

(0.1)

2X 0.65

1.3

2.15

1.85

1.3

0.33

0.23

0.1

0.0

(0.9)

TYP

0.1

C A B

0.15

0.22

0.08

GAGE PLANE

TYP

0.46

0.26

TYP

SEATING PLANE

4214834/C 03/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-203.

4. Support pin may differ or may not be present.

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EXAMPLE BOARD LAYOUT

DCK0005A

SOT - 1.1 max height

SMALL OUTLINE TRANSISTOR

PKG

5X (0.95)

5X (0.4)

SYMM

(1.3)

2X (0.65)

(R0.05) TYP

(2.2)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214834/C 03/2023

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

DCK0005A

SOT - 1.1 max height

SMALL OUTLINE TRANSISTOR

PKG

5X (0.95)

5X (0.4)

SYMM

(1.3)

2X(0.65)

(R0.05) TYP

(2.2)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL

SCALE:18X

4214834/C 03/2023

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LPV511MGX/NOPB [TI]

相关型号：

LPV521

LPV521

LPV521MG

LPV521MG/NOPB

LPV521MGE

LPV521MGE/NOPB

LPV521MGX

LPV521MGX/NOPB

LPV531

LPV531

LPV531MK

LPV531MK/NOPB