LPV521MG/NOPB [TI]
Single, 5.5-V, 6.2-kHz, ultra low quiescent current (350-nA), 1.6-V min supply, RRIO op amp | DCK | 5 | -40 to 125;
| 型号： | LPV521MG/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Single, 5.5-V, 6.2-kHz, ultra low quiescent current (350-nA), 1.6-V min supply, RRIO op amp | DCK | 5 | -40 to 125 |
| 文件： | 总35页 (文件大小：2045K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LPV521
SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
LPV521 NanoPower, 1.8-V, RRIO, CMOS Input, Operational Amplifier
1 Features
3 Description
The LPV521 is a single nanopower 552-nW amplifier
designed for ultra long life battery applications. The
operating voltage range of 1.6 V to 5.5 V coupled
with typically 351 nA of supply current make it well
suited for RFID readers and remote sensor
nanopower applications. The device has input
1
•
For VS = 5 V, Typical Unless Otherwise Noted
–
–
–
–
–
–
–
–
–
–
–
–
Supply Current at VCM = 0.3 V 400 nA (Max)
Operating Voltage Range 1.6 V to 5.5 V
Low TCVOS 3.5 µV/°C (Max)
VOS 1 mV (Max)
common mode voltage 0.1
V over the rails,
Input Bias Current 40 fA
guaranteed TCVOS and voltage swing to the rail
output performance. The LPV521 has a carefully
designed CMOS input stage that outperforms
competitors with typically 40 fA IBIAS currents. This
low input current significantly reduces IBIAS and IOS
errors introduced in megohm resistance, high
impedance photodiode, and charge sense situations.
The LPV521 is a member of the PowerWise™ family
and has an exceptional power-to-performance ratio.
PSRR 109 dB
CMRR 102 dB
Open-Loop Gain 132 dB
Gain Bandwidth Product 6.2 kHz
Slew Rate 2.4 V/ms
Input Voltage Noise at f = 100 Hz 255 nV/√Hz
Temperature Range −40°C to 125°C
The wide input common mode voltage range,
guaranteed 1 mV VOS and 3.5 µV/°C TCVOS enables
accurate and stable measurement for both high-side
and low-side current sensing.
2 Applications
•
•
•
•
•
•
•
•
Wireless Remote Sensors
Powerline Monitoring
EMI protection was designed into the device to
reduce sensitivity to unwanted RF signals from cell
phones or other RFID readers.
Power Meters
Battery Powered Industrial Sensors
Micropower Oxygen sensor and Gas Sensor
Active RFID Readers
The LPV521 is offered in the 5-pin SC70 package.
Device Information(1)
Zigbee Based Sensors for HVAC Control
Sensor Network Powered by Energy Scavenging
PART NUMBER
LPV521
PACKAGE
BODY SIZE (NOM)
SC70 (5)
2.00 mm x 1.25 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Nanopower Supply Current
125°C
800
700
600
500
400
300
200
85°C
25°C
-40°C
100
0
V
= V ± 0.3V
S
CM
1
2
3
4
5
6
SUPPLY VOLTAGE (V)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LPV521
SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
www.ti.com
Table of Contents
7.1 Overview ................................................................. 19
7.2 Functional Block Diagram ....................................... 19
7.3 Feature Description................................................. 19
7.4 Device Functional Modes........................................ 19
Applications and Implementation ...................... 20
8.1 Application Information............................................ 20
8.2 Typical Applications ................................................ 21
Power Supply Recommendations...................... 25
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings.............................................................. 3
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 1.8-V DC Electrical Characteristics........................... 4
6.6 1.8-V AC Electrical Characteristics........................... 5
6.7 3.3-V DC Electrical Characteristics........................... 6
6.8 3.3-V AC Electrical Characteristics........................... 7
6.9 5-V DC Electrical Characteristics.............................. 7
6.10 5-V AC Electrical Characteristics............................ 8
6.11 Typical Characteristics............................................ 9
Detailed Description ............................................ 19
8
9
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 26
11 Device and Documentation Support ................. 27
11.1 Device Support .................................................... 27
11.2 Documentation Support ........................................ 27
11.3 Trademarks........................................................... 27
11.4 Electrostatic Discharge Caution............................ 27
11.5 Glossary................................................................ 27
12 Mechanical, Packaging, and Orderable
7
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (Feburary 2013) to Revision D
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
2
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SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
5 Pin Configuration and Functions
SC70-5 Top View
1
2
3
5
4
+
OUT
V
-
V
+
-
IN+
IN-
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
1
NAME
OUT
V-
O
P
I
Output
2
Negative Power Supply
Noninverting Input
Inverting Input
3
IN+
IN-
4
I
5
V+
P
Positive Power Supply
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
−0.3
V– – 0.3 V
MAX
6
V+ + 0.3 V
UNIT
V
Any pin relative to V-
IN+, IN-, OUT Pins
V+, V-, OUT Pins
V
40
mA
mV
°C
Differential Input Voltage (VIN+ - VIN-
Junction Temperature(2)
)
–300
–40
300
150
Mounting Temperature
Infrared or Convection (30 sec.)
260
°C
Wave Soldering Lead Temp. (4 sec.)
260
°C
Storage temperature, Tstg
−65
150
°C
(1) Absolute Maximum Ratings indicate limits beyond which damage may occur. Recommended Operating Conditions indicate conditions
for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test
conditions, see the Electrical Characteristics.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature
is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
V(ESD)
Electrostatic discharge
V
Machine Model
±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2009–2014, Texas Instruments Incorporated
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6.3 Recommended Operating Conditions(1)
MIN
−40
1.6
MAX
125
5.5
UNIT
°C
Temperature Range(2)
Supply Voltage (VS = V+ - V−)
V
(1) Absolute Maximum Ratings indicate limits beyond which damage may occur. Recommended Operating Conditions indicate conditions
for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test
conditions, see Electrical Characteristics.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature
is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
6.4 Thermal Information
DCK
THERMAL METRIC(1)
UNIT
5 PINS
(2)
RθJA
Junction-to-ambient thermal resistance
456
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature
is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
6.5 1.8-V DC Electrical Characteristics
Unless otherwise specified, all limits for TA = 25°C, V+ = 1.8 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ.(1)
PARAMETER
Input Offset Voltage
TEST CONDITIONS
VCM = 0.3 V
MIN
–1
TYP
MAX
1
UNIT
VOS
0.1
Temperature extremes
VCM = 1.5 V
–1.23
–1
1.23
1
mV
0.1
±0.4
0.01
Temperature extremes
–1.23
1.23
TCVOS
Input Offset Voltage Drift(2)
Input Bias Current
μV/°C
Temperature extremes
Temperature extremes
–3
–1
3
1
IBIAS
pA
fA
–50
50
IOS
Input Offset Current
10
92
CMRR
Common Mode Rejection Ratio
0 V ≤ VCM ≤ 1.8 V
66
60
75
74
75
53
Temperature extremes
0 V ≤ VCM ≤ 0.7 V
101
120
dB
Temperature extremes
1.2 V ≤ VCM ≤ 1.8 V
Temperature extremes
PSRR
Power Supply Rejection Ratio
1.6 V ≤ V+ ≤ 5.5 V
VCM = 0.3 V
dB
V
85
76
109
125
Temperature extremes
CMRR ≥ 67 dB
CMRR ≥ 60 dB
0
0
1.8
1.8
CMVR
AVOL
Common Mode Voltage Range
Large Signal Voltage Gain
Temperature extremes
VO = 0.5 V to 1.3 V
dB
74
73
RL = 100 kΩ to V+/2
Temperature extremes
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
(2) The offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature
change.
4
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SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
1.8-V DC Electrical Characteristics (continued)
Unless otherwise specified, all limits for TA = 25°C, V+ = 1.8 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ.(1)
PARAMETER
Output Swing High
TEST CONDITIONS
RL = 100 kΩ to V+/2
MIN
TYP
MAX
UNIT
VO
2
50
VIN(diff) = 100 mV
Temperature extremes
RL = 100 kΩ to V+/2
VIN(diff) = −100 mV
50
50
50
mV from
either rail
Output Swing Low
2
3
3
Temperature extremes
Sourcing, VO to V–
VIN(diff) = 100 mV
IO
1
0.5
1
Temperature extremes
Sinking, VO to V+
VIN(diff) = −100 mV
Output Current(3)
Supply Current
mA
nA
Temperature extremes
VCM = 0.3 V
0.5
IS
345
472
400
580
600
850
Temperature extremes
VCM = 1.5 V
Temperature extremes
(3) The short circuit test is a momentary open-loop test.
6.6 1.8-V AC Electrical Characteristics
Unless otherwise specified, all limits for TA = 25°C, V+ = 1.8 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ.(1)
PARAMETER
Gain-Bandwidth Product
Slew Rate
TEST CONDITIONS
MIN
TYP
6.1
2.9
2.3
72
MAX
UNIT
GBW
SR
CL = 20 pF, RL = 100 kΩ
kHz
AV = +1,
VIN = 0V to 1.8V
Falling Edge
Rising Edge
V/ms
θ m
Gm
en
Phase Margin
Gain Margin
CL = 20 pF, RL = 100 kΩ
CL = 20 pF, RL = 100 kΩ
deg
dB
19
Input-Referred Voltage Noise Density f = 100 Hz
265
24
nV/√Hz
μVPP
fA/√Hz
Input-Referred Voltage Noise
Input-Referred Current Noise
0.1 Hz to 10 Hz
f = 100 Hz
In
100
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
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6.7 3.3-V DC Electrical Characteristics
Unless otherwise specified, all limits for TA = 25°C, V+ = 3.3 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ.(1)
PARAMETER
Input Offset Voltage
TEST CONDITIONS
VCM = 0.3 V
MIN
–1
TYP
MAX
1
UNIT
VOS
0.1
Temperature extremes
VCM = 3 V
–1.23
–1
1.23
1
mV
0.1
±0.4
0.01
Temperature extremes
–1.23
1.23
TCVOS
Input Offset Voltage Drift(2)
Input Bias Current
μV/°C
Temperature extremes
Temperature extremes
–3
–1
3
1
IBIAS
pA
fA
–50
50
IOS
Input Offset Current
20
97
CMRR
Common Mode Rejection Ratio
0 V ≤ VCM ≤ 3.3 V
72
70
78
75
77
76
Temperature extremes
0 V ≤ VCM ≤ 2.2 V
106
121
109
dB
Temperature extremes
2.7 V ≤ VCM ≤ 3.3 V
Temperature extremes
1.6 V ≤ V+ ≤ 5.5 V
VCM = 0.3 V
PSRR
CMVR
Power Supply Rejection Ratio
Common Mode Voltage Range
85
76
dB
V
Temperature extremes
CMRR ≥ 72 dB
CMRR ≥ 70 dB
−0.1
0
3.4
3.3
Temperature extremes
VO = 0.5 V to 2.8 V
120
3
82
RL = 100 kΩ to V+/2
AVOL
VO
Large Signal Voltage Gain
Output Swing High
dB
Temperature extremes
RL = 100 kΩ to V+/2
76
50
VIN(diff) = 100 mV
mV
from either
rail
Temperature extremes
RL = 100 kΩ to V+/2
VIN(diff) = −100 mV
50
50
50
Output Swing Low
Output Current(3)
2
Temperature extremes
Sourcing, VO to V–
VIN(diff) = 100 mV
IO
11
12
5
4
5
4
Temperature extremes
Sinking, VO to V+
VIN(diff) = −100 mV
mA
nA
Temperature extremes
VCM = 0.3 V
IS
Supply Current
346
471
400
600
600
860
Temperature extremes
VCM = 3 V
Temperature extremes
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
(2) The offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature
change.
(3) The short circuit test is a momentary open-loop test.
6
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SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
6.8 3.3-V AC Electrical Characteristics
Unless otherwise is specified, all limits for TA = 25°C, V+ = 3.3 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ.(1)
PARAMETER
Gain-Bandwidth Product
Slew Rate
TEST CONDITIONS
MIN
TYP
6.2
2.9
2.5
73
MAX
UNIT
GBW
SR
CL = 20 pF, RL = 100 kΩ
kHz
AV = +1,
VIN = 0V to 3.3V
Falling Edge
Rising Edge
V/ms
θ m
Gm
en
Phase Margin
Gain Margin
CL = 20 pF, RL = 10 kΩ
CL = 20 pF, RL = 10 kΩ
deg
dB
19
Input-Referred Voltage Noise Density f = 100 Hz
259
22
nV/√Hz
μVPP
fA/√Hz
Input-Referred Voltage Noise
Input-Referred Current Noise
0.1 Hz to 10 Hz
f = 100 Hz
In
100
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
6.9 5-V DC Electrical Characteristics
Unless otherwise specified, all limits for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ.(1)
PARAMETER
Input Offset Voltage
TEST CONDITIONS
VCM = 0.3 V
MIN
–1.23
–1.23
–3.5
TYP
MAX
±1
UNIT
mV
VOS
0.1
Temperature extremes
VCM = 4.7 V
1.23
±1
0.1
±0.4
0.04
Temperature extremes
1.23
TCVOS
Input Offset Voltage Drift(2)
Input Bias Current
μV/°C
Temperature extremes
Temperature extremes
3.5
±1
50
IBIAS
pA
fA
–50
IOS
Input Offset Current
60
CMRR
Common Mode Rejection Ratio
0 V ≤ VCM ≤ 5.0 V
75
74
84
80
77
76
85
102
Temperature extremes
0 V ≤ VCM ≤ 3.9 V
108
115
109
dB
dB
Temperature extremes
Temperature extremes
1.6 V ≤ V+ ≤ 5.5 V
VCM = 0.3 V
PSRR
CMVR
AVOL
Power Supply Rejection Ratio
Common Mode Voltage Range
Large Signal Voltage Gain
Temperature extremes
76
CMRR ≥ 75 dB
CMRR ≥ 74 dB
−0.1
5.1
5
V
Temperature extremes
0
VO = 0.5 V to 4.5 V
84
132
dB
RL = 100 kΩ to V+/2
Temperature extremes
76
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
(2) The offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature
change.
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5-V DC Electrical Characteristics (continued)
Unless otherwise specified, all limits for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ.(1)
PARAMETER
Output Swing High
TEST CONDITIONS
RL = 100 kΩ to V+/2
MIN
TYP
MAX
UNIT
VO
3
50
VIN(diff) = 100 mV
Temperature extremes
RL = 100 kΩ to V+/2
VIN (diff) = −100 mV
50
50
mV from
either rail
Output Swing Low
Output Current
3
23
22
Temperature extremes
Sourcing, VO to V−
VIN(diff) = 100 mV
50
IO
15
Temperature extremes
Sinking, VO to V+
VIN(diff) = −100 mV
8
mA
nA
15
Temperature extremes
VCM = 0.3 V
8
IS
Supply Current
351
475
400
620
600
870
Temperature extremes
VCM = 4.7 V
Temperature extremes
6.10 5-V AC Electrical Characteristics(1)
Unless otherwise specified, all limits for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(2)
(3)
(2)
GBW
SR
Gain-Bandwidth Product
Slew Rate
CL = 20 pF, RL = 100 kΩ
6.2
2.7
kHz
AV = +1,
Falling Edge
1.1
1.2
VIN = 0 V to 5 V
Temperature
extremes
V/ms
Rising Edge
1.1
1.2
2.4
Temperature
extremes
θ m
Gm
en
Phase Margin
Gain Margin
CL = 20 pF, RL = 100 kΩ
CL = 20 pF, RL = 100 kΩ
73
20
deg
dB
Input-Referred Voltage Noise Density f = 100 Hz
255
22
nV/√Hz
μVPP
fA/√Hz
Input-Referred Voltage Noise
Input-Referred Current Noise
EMI Rejection Ratio, IN+ and IN−(4)
0.1 Hz to 10 Hz
In
f = 100 Hz
100
121
EMIRR
VRF_PEAK = 100 mVP (−20 dBP),
f = 400 MHz
VRF_PEAK = 100 mVP (−20 dBP),
f = 900 MHz
121
124
142
dB
VRF_PEAK = 100 mVP (−20 dBP),
f = 1800 MHz
VRF_PEAK = 100 mVP (−20 dBP),
f = 2400 MHz
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
(2) All limits are guaranteed by testing, statistical analysis or design.
(3) Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and
will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production
material.
(4) The EMI Rejection Ratio is defined as EMIRR = 20log (VRF_PEAK/ΔVOS).
8
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6.11 Typical Characteristics
At TJ = 25°C, unless otherwise specified.
125°C
800
800
700
600
500
400
300
200
100
0
700
600
500
400
300
200
100
0
125°C
85°C
85°C
25°C
25°C
-40°C
V
CM
= 0.3V
5
V
CM
= V ± 0.3V
S
-40°C
1
2
3
4
6
1
2
3
4
5
6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 1. Supply Current vs. Supply Voltage
Figure 2. Supply Current vs. Supply Voltage
30
25
20
15
10
5
25
20
15
10
5
V
T
= 1.8V
= 25oC
S
A
V
CM
= V /2
S
0
0
-3.0
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
(mV)
-2.0
-1.0
TCV
0.0
1.0
2.0
3.0
V
OS
(PV/C)
OS
Figure 3. Offset Voltage Distribution
Figure 4. TcvOS Distribution
30
25
20
15
10
5
20
18
16
14
12
10
8
V
= 3.3V
S
-40oC d T d 125oC
V
T
= 3.3V
= 25oC
S
A
A
V
= V /2
S
CM
V
CM
= V /2
S
6
4
2
0
0
-3.0
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
(mV)
-2.0
-1.0
TCV
0.0
1.0
2.0
3.0
V
OS
(PV/C)
OS
Figure 5. Offset Voltage Distribution
Figure 6. TcvOS Distribution
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Typical Characteristics (continued)
At TJ = 25°C, unless otherwise specified.
30
25
20
15
10
5
25
V
= 5V
= 25oC
S
T
A
20
15
10
5
V
= V /2
S
CM
0
0
-3.0 -2.0 -1.0 0.0
1.0
2.0
3.0
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
(mV)
TCV
OS
(PV/C)
V
OS
Figure 7. Offset Voltage Distribution
Figure 8. TcvOS Distribution
V
= 3.3V
S
V
S
= 1.8V
-40°C
300
200
100
0
150
-40°C
100
50
25°C
25°C
0
-100
-200
-300
-50
-100
-150
85°C
85°C
125°C
125°C
0.0
0.3
0.6
0.9
(V)
1.2
1.5
1.8
-0.1 0.4 0.9 1.4 1.9 2.4 2.9 3.4
(V)
V
V
CM
CM
Figure 9. Input Offset Voltage vs. Input Common Mode
Figure 10. Input Offset Voltage vs. Input Common Mode
V
= 5V
V
= 0.3V
CM
-40°C
25°C
S
150
100
50
150
100
50
-40°C
25°C
0
0
-50
-100
-150
-50
-100
-150
85°C
85°C
125°C
2
125°C
-50.0 0.5 1.0 5 2.0 2.5 3.0 5 4.0 5 5.0 5.5
(V)
1
3
4
5
6
V
(V)
V
S
CM
Figure 11. Input Offset Voltage vs. Input Common Mode
Figure 12. Input Offset Voltage vs. Supply Voltage
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Typical Characteristics (continued)
At TJ = 25°C, unless otherwise specified.
-40°C
V
CM
= V - 0.3V
S
V = 1.8V
S
150
100
50
150
100
50
-40°C
25°C
25°C
0
0
85°C
-50
-100
-150
-50
-100
-150
85°C
125°C
V
125°C
0.0
0.5
1.0
(V)
1.5
2.0
1
2
3
4
5
6
V
S
(V)
OUT
Figure 13. Input Offset Voltage vs. Supply Voltage
Figure 14. Input Offset Voltage vs. Output Voltage
V
= 5V
S
V
S
= 3.3V
-40°C
25°C
-40°C
25°C
150
100
50
150
100
50
0
0
-50
-100
-150
-50
-100
-150
85°C
85°C
125°C
125°C
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
(V)
0.0
1.0
2.0
3.0
4.0
5.0
V
(V)
V
OUT
OUT
Figure 15. Input Offset Voltage vs. Output Voltage
Figure 16. Input Offset Voltage vs. Output Voltage
V
= 1.8V
V = 3.3V
S
S
-40°C
25°C
-40°C
25°C
150
100
50
150
100
50
0
0
-50
-100
-150
-50
-100
-150
85°C
85°C
125°C
125°C
1.0
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.5
2.0
I
SOURCE
(mA)
I
(mA)
SOURCE
Figure 17. Input Offset Voltage vs. Sourcing Current
Figure 18. Input Offset Voltage vs. Sourcing Current
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Typical Characteristics (continued)
At TJ = 25°C, unless otherwise specified.
V
S
= 5V
V = 1.8V
S
-40°C
25°C
-40°C
25°C
150
100
50
150
100
50
0
0
-50
-100
-150
-50
-100
-150
85°C
85°C
125°C
125°C
1.0
0.0
0.5
1.5
2.0
0.0
0.5
1.0
1.5
2.0
I
(mA)
I
SOURCE
(mA)
SOURCE
Figure 19. Input Offset Voltage vs. Sourcing Current
Figure 20. Input Offset Voltage vs. Sinking Current
V = 5V
S
V
= 3.3V
S
-40°C
25°C
150
100
50
150
100
50
-40°C
25°C
0
0
-50
-100
-150
-50
-100
-150
85°C
85°C
125°C
1.0
125°C
0.0
0.5
1.5
2.0
0.0
0.5
1.0
1.5
2.0
I
(mA)
I
(mA)
SOURCE
SOURCE
Figure 21. Input Offset Voltage vs. Sinking Current
Figure 22. Input Offset Voltage vs. Sinking Current
5
5
V
= 1.8V
V
= 1.8V
25°C
-40°C
S
S
4
3
2
1
-40°C
4
3
2
1
25°C
85°C
85°C
125°C
125°C
0
0.0
0
0.0
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
OUTPUT VOLTAGE REFERENCED TO V- (V)
OUTPUT VOLTAGE REFERENCED TO V+ (V)
Figure 23. Sourcing Current vs. Output Voltage
Figure 24. Sinking Current vs. Output Voltage
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Typical Characteristics (continued)
At TJ = 25°C, unless otherwise specified.
16
16
12
8
-40°C
V
= 3.3V
V
= 3.3V
25°C
-40°C
S
S
12
8
25°C
85°C
85°C
125°C
4
4
125°C
0
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
OUTPUT VOLTAGE REFERENCED TO V+ (V)
Figure 25. Sourcing Current vs. Output Voltage
30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
OUTPUT VOLTAGE REFERENCED TO V- (V)
Figure 26. Sinking Current vs. Output Voltage
30
-40°C
V
= 5V
V = 5V
S
S
-40°C
25
20
15
10
5
25
20
15
10
5
25°C
25°C
85°C
85°C
125°C
125°C
0
0
0
0
1
2
3
4
5
1
2
3
4
5
OUTPUT VOLTAGE REFERENCED TO V+ (V)
OUTPUT VOLTAGE REFERENCED TO V- (V)
Figure 27. Sourcing Current vs. Output Voltage
Figure 28. Sinking Current vs. Output Voltage
40
40
V
= V /2
S
V
= V /2
CM S
CM
-40°C
30
20
10
0
30
20
10
0
-40°C
25°C
25°C
85°C
85°C
125°C
125°C
1
2
3
4
5
6
1
2
3
4
5
6
V
(V)
V
(V)
S
S
Figure 29. Sourcing Current vs. Supply Voltage
Figure 30. Sinking Current vs. Supply Voltage
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Typical Characteristics (continued)
At TJ = 25°C, unless otherwise specified.
5
4
3
2
R
= 100 k:
R = 100 k:
L
L
5
4
3
2
1
0
125°C
125°C
85°C
85°C
25°C
-40°C
25°C
-40°C
1
2
3
4
5
6
1
2
3
4
5
6
V
S
(V)
V
S
(V)
Figure 31. Output Swing High vs. Supply Voltage
Figure 32. Output Swing Low vs. Supply Voltage
15
15
V
S
= 1.8V
V
= 1.8V
S
10
5
10
5
125°C
25°C
0
0
85°C
-5
-5
-40°C
-10
-15
-10
-15
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
V
(V)
V
(V)
CM
CM
Figure 33. Input Bias Current vs. Common Mode Voltage
Figure 34. Input Bias Current vs. Common Mode Voltage
50
15
V
S
= 3.3V
V
S
= 3.3V
40
30
10
5
125°C
25°C
20
10
0
0
85°C
-10
-20
-30
-40
-5
-40°C
-10
-15
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
V
(V)
V
(V)
CM
CM
Figure 35. Input Bias Current vs. Common Mode Voltage
Figure 36. Input Bias Current vs. Common Mode Voltage
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Typical Characteristics (continued)
At TJ = 25°C, unless otherwise specified.
400
30
25
20
15
10
5
V
S
= 5V
V
S
= 5V
300
200
100
0
25°C
125°C
0
-5
-100
-200
-300
85°C
1
-40°C
1
-10
-15
-20
0
2
3
4
5
0
2
3
4
5
V
CM
(V)
V
(V)
CM
Figure 37. Input Bias Current vs. Common Mode Voltage
Figure 38. Input Bias Current vs. Common Mode Voltage
100
V = 5V
S
V
S
= 1.8V, 3.3V, 5V
100
80
60
40
20
0
90
80
70
60
50
40
V
= 1.8V
S
100
10
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 40. CMRR vs. Frequency
Figure 39. PSRR vs. Frequency
V
= 1.8V
= 20 pF
= 1 M:
V
= 3.3V
= 20 pF
= 1 M:
S
S
60
40
20
0
60
40
20
0
C
R
C
R
L
L
L
L
130
110
90
130
110
90
PHASE
PHASE
GAIN
85°C
85°C
70
70
25°C
25°C
50
50
GAIN
30
30
125°C
125°C
10
10
-40°C
-40°C
-10
-30
-10
-30
-20
-20
100
1k
10k
100k
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 41. Frequency Response vs. Temperature
Figure 42. Frequency Response vs. Temperature
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Typical Characteristics (continued)
At TJ = 25°C, unless otherwise specified.
V
= 5V
S
60
40
60
40
20
0
C
R
= 20 pF
= 1 M:
L
L
130
110
90
130
PHASE
110
90
85°C
70
70
25°C
50
50
20 GAIN
30
30
125°C
10
10
0
-40°C
-10
-30
-10
-30
-20
-20
100
1k
10k
100k
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 43. Frequency Response vs. Temperature
Figure 44. Frequency Response vs. RL
60
40
20
0
60
40
20
0
130
110
90
130
110
90
GAIN
70
70
50
50
30
30
10
10
-10
-30
-10
-30
-20
-20
100
1k
FREQUENCY (Hz)
Figure 45. Frequency Response vs. RL
10k
100k
100
1k
10k
100k
FREQUENCY (Hz)
Figure 46. Frequency Response vs. RL
60
40
20
0
60
40
20
0
130
110
90
130
110
90
70
70
50
50
30
30
10
10
-10
-30
-10
-30
-20
-20
100
1k
10k
100k
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 47. Frequency Response vs. CL
Figure 48. Frequency Response vs. CL
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Typical Characteristics (continued)
At TJ = 25°C, unless otherwise specified.
60
40
20
0
3.3
3.0
2.7
2.4
2.1
1.8
130
110
90
FALLING EDGE
70
50
30
10
RISING EDGE
-10
-30
A
V
= +1
V
-20
= V
OUT
4.7
S
100
1k
10k
100k
1.5
2.3
3.1
3.9
5.5
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
Figure 49. Frequency Response vs. CL
Figure 50. Slew Rate vs. Supply Voltage
1000
V
V
= 1.8V
S
= V /2
CM
S
V
S
= 5V
100
1
10
100
1k
10k
FREQUENCY (Hz)
1s/DIV
Figure 51. Voltage Noise vs. Frequency
Figure 52. 0.1 to 10 Hz Time Domain Voltage Noise
V
V
= 5V
S
= V /2
CM
S
V
V
= 3.3V
S
= V /2
CM
S
1s/DIV
1s/DIV
Figure 53. 0.1 to 10 Hz Time Domain Voltage Noise
Figure 54. 0.1 to 10 Hz Time Domain Voltage Noise
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Typical Characteristics (continued)
At TJ = 25°C, unless otherwise specified.
INPUT
INPUT
OUTPUT
OUTPUT
V
= 5V
V
= 1.8V
S
S
R
= 100 k:
R
= 100 k:
L
L
200 Ps/DIV
200 Ps/DIV
Figure 55. Small Signal Pulse Response
Figure 56. Small Signal Pulse Response
INPUT
INPUT
OUTPUT
OUTPUT
V
= 5V
V
= 1.8V
S
S
R
= 100 k:
R
= 100 k:
L
L
200 Ps/DIV
Figure 58. Large Signal Pulse Response
200 Ps/DIV
Figure 57. Large Signal Pulse Response
4
INPUT
OUTPUT
3
2
1
170
150
130
110
90
0
70
-1
50
30
-2
10
+
V
V
= 5V
S
V = +2.5V
-3
-4
-
= -20 dBVp
PEAK
V = -2.5V
2 ms/DIV
0.1
1
10
100
1000
10000
FREQUENCY (MHz)
Figure 59. Overload Recovery Waveform
Figure 60. EMIRR vs. Frequency
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7 Detailed Description
7.1 Overview
The LPV521 is fabricated with Texas Instruments' state-of-the-art VIP50 process. This proprietary process
dramatically improves the performance of Texas Instruments' low-power and low-voltage operational amplifiers.
The following sections showcase the advantages of the VIP50 process and highlight circuits which enable ultra-
low power consumption.
7.2 Functional Block Diagram
Figure 61. Block Diagram
7.3 Feature Description
The amplifier's differential inputs consist of a noninverting input (+IN) and an inverting input (–IN). The amplifier
amplifies only the difference in voltage between the two inputs, which is called the differential input voltage. The
output voltage of the op-amp Vout is given by Equation 1:
VOUT = AOL (IN+ - IN-)
(1)
where AOL is the open-loop gain of the amplifier, typically around 100 dB (100,000x, or 10uV per Volt).
7.4 Device Functional Modes
7.4.1 Input Stage
The LPV521 has a rail-to-rail input which provides more flexibility for the system designer. Rail-to-rail input is
achieved by using in parallel, one PMOS differential pair and one NMOS differential pair. When the common
mode input voltage (VCM) is near V+, the NMOS pair is on and the PMOS pair is off. When VCM is near V−, the
NMOS pair is off and the PMOS pair is on. When VCM is between V+ and V−, internal logic decides how much
current each differential pair will get. This special logic ensures stable and low distortion amplifier operation
within the entire common mode voltage range.
Because both input stages have their own offset voltage (VOS) characteristic, the offset voltage of the LPV521
becomes a function of VCM. VOS has a crossover point at 1.0 V below V+. Refer to the ’VOS vs. VCM’ curve in the
Typical Performance Characteristics section. Caution should be taken in situations where the input signal
amplitude is comparable to the VOS value and/or the design requires high accuracy. In these situations, it is
necessary for the input signal to avoid the crossover point. In addition, parameters such as PSRR and CMRR
which involve the input offset voltage will also be affected by changes in VCM across the differential pair transition
region.
7.4.2 Output Stage
The LPV521 output voltage swings 3 mV from rails at 3.3-V supply, which provides the maximum possible
dynamic range at the output. This is particularly important when operating on low supply voltages.
The LPV521 Maximum Output Voltage Swing defines the maximum swing possible under a particular output
load. The LPV521 output swings 50 mV from the rail at 5-V supply with an output load of 100 kΩ.
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8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LPV521is specified for operation from 1.6 V to 5.5 V (±0.8 V to ±2.25 V). Many of the specifications apply
from –40°C to 125°C. The LMV521 features rail to rail input and rail-to-rail output swings while consuming only
nanowatts of power. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section.
8.1.1 Driving Capacitive Load
The LPV521 is internally compensated for stable unity gain operation, with a 6.2-kHz, typical gain bandwidth.
However, the unity gain follower is the most sensitive configuration to capacitive load. The combination of a
capacitive load placed at the output of an amplifier along with the amplifier’s output impedance creates a phase
lag, which reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the response
will be under damped which causes peaking in the transfer and, when there is too much peaking, the op amp
might start oscillating.
R
ISO
-
V
OUT
V
IN
+
C
L
Figure 62. Resistive Isolation of Capacitive Load
In order to drive heavy capacitive loads, an isolation resistor, RISO, should be used, as shown in Figure 62. By
using this isolation resistor, the capacitive load is isolated from the amplifier’s output. The larger the value of
RISO, the more stable the amplifier will be. If the value of RISO is sufficiently large, the feedback loop will be
stable, independent of the value of CL. However, larger values of RISO result in reduced output swing and
reduced output current drive.
Recommended minimum values for RISO are given in the following table, for 5-V supply. Figure 63 shows the
typical response obtained with the CL = 50 pF and RISO = 154 kΩ. The other values of RISO in the table were
chosen to achieve similar dampening at their respective capacitive loads. Notice that for the LPV521 with larger
CL a smaller RISO can be used for stability. However, for a given CL a larger RISO will provide a more damped
response. For capacitive loads of 20 pF and below no isolation resistor is needed.
CL
0 – 20 pF
50 pF
100 pF
500 pF
1 nF
RISO
not needed
154 kΩ
118 kΩ
52.3 kΩ
33.2 kΩ
17.4 kΩ
13.3 kΩ
5 nF
10 nF
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V
IN
V
OUT
V
= 5V
S
200 Ps/DIV
Figure 63. Step Response
8.1.2 EMI Suppression
The near-ubiquity of cellular, Bluetooth, and Wi-Fi signals and the rapid rise of sensing systems incorporating
wireless radios make electromagnetic interference (EMI) an evermore important design consideration for
precision signal paths. Though RF signals lie outside the op amp band, RF carrier switching can modulate the
DC offset of the op amp. Also some common RF modulation schemes can induce down-converted components.
The added DC offset and the induced signals are amplified with the signal of interest and thus corrupt the
measurement. The LPV521 uses on chip filters to reject these unwanted RF signals at the inputs and power
supply pins; thereby preserving the integrity of the precision signal path.
Twisted pair cabling and the active front-end’s common-mode rejection provide immunity against low-frequency
noise (i.e. 60-Hz or 50-Hz mains) but are ineffective against RF interference. Even a few centimeters of PCB
trace and wiring for sensors located close to the amplifier can pick up significant 1 GHz RF. The integrated EMI
filters of the LPV521 reduce or eliminate external shielding and filtering requirements, thereby increasing system
robustness. A larger EMIRR means more rejection of the RF interference. For more information on EMIRR,
please refer to AN-1698.
8.2 Typical Applications
8.2.1 60-Hz Twin T-Notch Filter
V
= 3V oꢀ2V @ end of life
BATT
CR2032 Coin Cell
225 mAh = 5 circuits @ 9.5 yrs.
10 M:
10 M:
V
BATT
-
Remote Sensor
To ADC
V
OUT
10 M:
10 M:
+
V
IN
Signal
+
60 Hz
Signal × 2
(No 60 Hz)
270 pF
270 pF
60 Hz Twin T Notch Filter
= 2 V/V
10 M:
10 M:
A
V
270 pF
270 pF
Figure 64. 60-Hz Notch Filter
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Typical Applications (continued)
8.2.1.1 Design Requirements
Small signals from transducers in remote and distributed sensing applications commonly suffer strong 60-Hz
interference from AC power lines. The circuit of Figure 64 notches out the 60 Hz and provides a gain AV = 2 for
the sensor signal represented by a 1-kHz sine wave. Similar stages may be cascaded to remove 2nd and 3rd
harmonics of 60 Hz. Thanks to the nA power consumption of the LPV521, even 5 such circuits can run for 9.5
years from a small CR2032 lithium cell. These batteries have a nominal voltage of 3 V and an end of life voltage
of 2 V. With an operating voltage from 1.6 V to 5.5 V the LPV521 can function over this voltage range.
8.2.1.2 Detailed Design Procedure
The notch frequency is set by F0 = 1 / 2πRC. To achieve a 60-Hz notch use R = 10 MΩ and C = 270 pF. If
eliminating 50-Hz noise, which is common in European systems, use R = 11.8 MΩ and C = 270 pF.
The Twin T Notch Filter works by having two separate paths from VIN to the amplifier’s input. A low frequency
path through the resistors R - R and another separate high frequency path through the capacitors C - C.
However, at frequencies around the notch frequency, the two paths have opposing phase angles and the two
signals will tend to cancel at the amplifier’s input.
To ensure that the target center frequency is achieved and to maximize the notch depth (Q factor) the filter
needs to be as balanced as possible. To obtain circuit balance, while overcoming limitations of available
standard resistor and capacitor values, use passives in parallel to achieve the 2C and R/2 circuit requirements
for the filter components that connect to ground.
To make sure passive component values stay as expected clean board with alcohol, rinse with deionized water,
and air dry. Make sure board remains in a relatively low humidity environment to minimize moisture which may
increase the conductivity of board components. Also large resistors come with considerable parasitic stray
capacitance which effects can be reduced by cutting out the ground plane below components of concern.
Large resistors are used in the feedback network to minimize battery drain. When designing with large resistors,
resistor thermal noise, op amp current noise, as well as op amp voltage noise, must be considered in the noise
analysis of the circuit. The noise analysis for the circuit in Figure 64 can be done over a bandwidth of 5 kHz,
which takes the conservative approach of overestimating the bandwidth (LPV521 typical GBW/AV is lower). The
total noise at the output is approximately 800 µVpp, which is excellent considering the total consumption of the
circuit is only 540 nA. The dominant noise terms are op amp voltage noise (550 µVpp), current noise through the
feedback network (430 µVpp), and current noise through the notch filter network (280 µVpp). Thus the total
circuit's noise is below ½ LSB of a 10 bit system with a 2-V reference, which is 1 mV.
8.2.1.3 Application Curve
Figure 65. 60-Hz Notch Filter Waveform
22
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Typical Applications (continued)
8.2.2 Portable Gas Detection Sensor
100 M:
+
V
1 M:
-
V
OUT
+
-
V
R
L
OXYGEN SENSOR
Figure 66. Precision Oxygen Sensor
8.2.2.1 Design Requirements
Gas sensors are used in many different industrial and medical applications. They generate a current which is
proportional to the percentage of a particular gas sensed in an air sample. This current goes through a load
resistor and the resulting voltage drop is measured. The LPV521 makes an excellent choice for this application
as it only draws 345 nA of current and operates on supply voltages down to 1.6V. Depending on the sensed gas
and sensitivity of the sensor, the output current can be in the order of tens of microamperes to a few
milliamperes. Gas sensor datasheets often specify a recommended load resistor value or they suggest a range
of load resistors to choose from.
Oxygen sensors are used when air quality or oxygen delivered to a patient needs to be monitored. Fresh air
contains 20.9% oxygen. Air samples containing less than 18% oxygen are considered dangerous. This
application detects oxygen in air. Oxygen sensors are also used in industrial applications where the environment
must lack oxygen. An example is when food is vacuum packed. There are two main categories of oxygen
sensors, those which sense oxygen when it is abundantly present (i.e. in air or near an oxygen tank) and those
which detect traces of oxygen in ppm.
8.2.2.2 Detailed Design Procedure
Figure 66 shows a typical circuit used to amplify the output of an oxygen detector. The oxygen sensor outputs a
known current through the load resistor. This value changes with the amount of oxygen present in the air sample.
Oxygen sensors usually recommend a particular load resistor value or specify a range of acceptable values for
the load resistor. The use of the nanopower LPV521 means minimal power usage by the op amp and it
enhances the battery life. With the components shown in Figure 66 the circuit can consume less than 0.5 µA of
current ensuring that even batteries used in compact portable electronics, with low mAh charge ratings, could
last beyond the life of the oxygen sensor. The precision specifications of the LPV521, such as its very low offset
voltage, low TCVOS , low input bias current, high CMRR, and high PSRR are other factors which make the
LPV521 a great choice for this application.
Copyright © 2009–2014, Texas Instruments Incorporated
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www.ti.com
Typical Applications (continued)
8.2.2.3 Application Curve
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
10
20
30
40
50
VSENSOR (mV)
C001
Figure 67. Calculated Oxygen Sensor Circuit Output (Single 5V Supply)
8.2.3 High-Side Battery Current Sensing
I
CHARGE
R
+
SENSE
V
10:
LOAD
R
R
2
1
24.9 k:
24.9 k:
+
V
Q1
2N2907
R
X R
3
SENSE
V
OUT
=
X I
CHARGE
R
1
V
OUT
R
3
10 M:
Figure 68. High-Side Current Sensing
8.2.3.1 Design Requirements
The rail-to-rail common mode input range and the very low quiescent current make the LPV521 ideal to use in
high-side and low-side battery current sensing applications. The high-side current sensing circuit in Figure 68 is
commonly used in a battery charger to monitor the charging current in order to prevent over charging. A sense
resistor RSENSE is connected in series with the battery.
8.2.3.2 Detailed Design Procedure
The theoretical output voltage of the circuit is VOUT = [ ®SENSE × R3) / R1 ] × ICHARGE. In reality, however, due to
the finite Current Gain, β, of the transistor the current that travels through R3 will not be ICHARGE, but instead, will
be α × ICHARGE or β/( β+1) × ICHARGE. A Darlington pair can be used to increase the β and performance of the
measuring circuit.
Using the components shown in Figure 68 will result in VOUT ≈ 4000 Ω × ICHARGE. This is ideal to amplify a 1 mA
ICHARGE to near full scale of an ADC with VREF at 4.1 V. A resistor, R2 is used at the noninverting input of the
amplifier, with the same value as R1 to minimize offset voltage.
24
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LPV521
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SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
Typical Applications (continued)
Selecting values per Figure 68 will limit the current traveling through the R1 – Q1 – R3 leg of the circuit to under 1
µA which is on the same order as the LPV521 supply current. Increasing resistors R1 , R2 , and R3 will decrease
the measuring circuit supply current and extend battery life.
Decreasing RSENSE will minimize error due to resistor tolerance, however, this will also decrease VSENSE
=
ICHARGE × RSENSE, and in turn the amplifier offset voltage will have a more significant contribution to the total error
of the circuit. With the components shown in Figure 68 the measurement circuit supply current can be kept below
1.5 µA and measure 100 µA to 1 mA.
8.2.3.3 Application Curve
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
0.25
0.5
0.75
1
1.25
1.5
ICHARGE (mA)
C001
Figure 69. Calculated High-Side Current Sense Circuit Output
9 Power Supply Recommendations
The LPV521 is specified for operation from 1.6 V to 5.5 V (±0.8 V to ±2.75 V) over a –40°C to 125°C
temperature range. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 6 V can permanently damage the device.
Low bandwidth nanopower devices do not have good high frequency (>1KHz) AC PSRR rejection against high-
frequency switching supplies and other kHz and above noise sources, so extra supply filtering is recommended if
kHz range noise is expected on the power supply lines.
Copyright © 2009–2014, Texas Instruments Incorporated
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
•
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close
to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply
applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information refer to
Circuit Board Layout Techniques, SLOA089.
•
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular
as opposed to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. As shown in Layout Example, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
Figure 70. Noninverting Layout Example
26
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LPV521
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SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
LPV521 PSPICE Model, SNOM024
TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti
TI Filterpro Software, http://www.ti.com/tool/filterpro
DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm
TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm
Evaluation board for 5-pin, north-facing amplifiers in the SC70 package, SNOA487.
Manual for LMH730268 Evaluation board 551012922-001
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
•
•
•
•
•
•
•
Feedback Plots Define Op Amp AC Performance, SBOA015 (AB-028)
Circuit Board Layout Techniques, SLOA089
Op Amps for Everyone, SLOD006
AN-1698 A Specification for EMI Hardened Operational Amplifiers, SNOA497
EMI Rejection Ratio of Operational Amplifiers, SBOA128
Capacitive Load Drive Solution using an Isolation Resistor, TIPD128
Handbook of Operational Amplifier Applications, SBOA092
11.3 Trademarks
PowerWise is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2009–2014, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LPV521MG/NOPB
LPV521MGE/NOPB
LPV521MGX/NOPB
ACTIVE
ACTIVE
ACTIVE
SC70
SC70
SC70
DCK
DCK
DCK
5
5
5
1000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
AHA
AHA
AHA
SN
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LPV521MG/NOPB
LPV521MGE/NOPB
LPV521MGX/NOPB
SC70
SC70
SC70
DCK
DCK
DCK
5
5
5
1000
250
178.0
178.0
178.0
8.4
8.4
8.4
2.25
2.25
2.25
2.45
2.45
2.45
1.2
1.2
1.2
4.0
4.0
4.0
8.0
8.0
8.0
Q3
Q3
Q3
3000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LPV521MG/NOPB
LPV521MGE/NOPB
LPV521MGX/NOPB
SC70
SC70
SC70
DCK
DCK
DCK
5
5
5
1000
250
208.0
208.0
208.0
191.0
191.0
191.0
35.0
35.0
35.0
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
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