LPV542 [TI]
双路、5.5V、8kHz、超低静态电流 (480nA)、1.6V 最小电源电压、RRIO 运算放大器;
| 型号： | LPV542 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路、5.5V、8kHz、超低静态电流 (480nA)、1.6V 最小电源电压、RRIO 运算放大器 放大器 运算放大器 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LPV542
ZHCSDK3 –MARCH 2015
LPV542 双路毫微功耗 1.8V、490nA、RRIO CMOS 运算放大器
1 特性
3 说明
1
•
宽电源电压范围：1.6V 至 5.5V
低电源电流：490nA（典型值/通道）
低偏移电压：3mV（最大值/室温）
低 TcVos：1µV/°C（典型值）
增益带宽：8kHz（典型值）
轨到轨输入和输出
LPV542 是一款超低功耗双路运算放大器，带宽
8kHz，静态电流 490nA，是电池供电应用的理想选
择，如医疗和健身可穿戴设备、楼宇自动化和遥感节
点。
•
•
•
•
•
•
•
•
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每个放大器的 CMOS 输入级偏置电流仅为皮安级，可
以减少光电二极管和充电感测应用等兆欧级反馈电阻拓
扑中引入的常见误差。 此外，输入共模范围扩展到电
源轨，输出摆幅扩展到电源轨的 ±3mV 范围内，从而
保持了最宽的动态范围。 同样，LPV542 设有 EMI 保
护，可降低来自手机、WiFi、无线电发射器和标签阅读
器的无用射频信号对系统造成的影响。
单位增益稳定
低输入偏置电流：1pA（最大值/室温）
强化的电磁干扰 (EMI) 保护
温度范围：-40℃ 至 125℃
3mm x 3mm x 0.45mm 薄型 X1SON 封装
2 应用
LPV542 可在 1.6V 的低电源电压下运行，确保在电池
低电量的情况下保持出色性能。 该器件采用 8 焊盘
3mm x 3mm x 0.45mm 薄型无铅 X1SON 封装和标准
8 引脚 VSSOP 封装。
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可穿戴产品
个人健康监视器
电池组
手机和平板电脑
器件信息(1)
太阳能或能量采集系统
PIR、烟雾、燃气和火灾检测系统
电池供电物联网 (IoT) 设备
远程传感器
器件型号
LPV542
封装
X1SON (8)
VSSOP (8)
封装尺寸（标称值）
3.00mm x 3.00mm
3.00mm × 3.00mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
微功耗参考缓冲器
空白
空白
毫微功耗氧气传感器放大器
电源电流与 电源电压间的关系
1000
100 Mꢀ
VCM = 0.3V
900
800
700
600
500
400
300
200
100
0
V+
1 Mꢀ
VOUT
+
125°C
85°C
25°C
0°C
R
L
-40°C
1.5
2
2.5
3
3.5
4
4.5
5
5.5
OXYGEN SENSOR
Supply Voltage (V)
C001
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SNOSCX9
LPV542
ZHCSDK3 –MARCH 2015
www.ti.com.cn
目录
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 14
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application: 60 Hz Twin "T" Notch Filter..... 16
8.3 Do's and Don'ts ...................................................... 17
Power Supply Recommendations...................... 18
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Ratings............................ 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics 1.8 V ................................. 5
6.6 Electrical Characteristics 3.3 V ................................. 6
6.7 Electrical Characteristics 5 V .................................... 7
6.8 Typical Characteristics.............................................. 8
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
8
9
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 器件和文档支持 ..................................................... 19
11.1 器件支持 ............................................................... 19
11.2 文档支持 ............................................................... 19
11.3 商标....................................................................... 19
11.4 静电放电警告......................................................... 19
11.5 术语表 ................................................................... 19
12 机械封装和可订购信息 .......................................... 19
7
4 修订历史记录
日期
修订版本
注释
2015 年 3 月
*
最初发布。
2
Copyright © 2015, Texas Instruments Incorporated
LPV542
www.ti.com.cn
ZHCSDK3 –MARCH 2015
5 Pin Configuration and Functions
8-Pad X1SON
DNX Package
Top View
8-Pin VSSOP
DGK Package
Top View
OUT A
-IN A
+IN A
V-
1
2
3
4
8
7
6
5
V+
Exposed
Thermal
Die Pad
on
OUT A
-IN A
+IN A
V-
1
2
3
4
8
7
6
5
V+
A
OUT B
-IN B
+IN B
OUT B
-IN B
+IN B
B
Underside(1)
(1) Connect thermal die pad to V-.
Pin Functions
PIN
I/O
DESCRIPTION
NAME
OUT A
-IN A
+IN A
V-
DGK
DNX
1
2
3
4
5
6
7
8
--
1
2
O
I
Channel A Output
Channel A Inverting Input
Channel A Non-Inverting Input
Negative (lowest) power supply
Channel B Non-Inverting Input
Channel B Inverting Input
Channel B Output
3
I
4
P
I
+IN B
-IN B
OUT B
V+
5
6
I
7
O
P
P
8
Positive (highest) power supply
Die Pad
DAP
Die Attach Pad. Connect to V- (DNX package only)
Copyright © 2015, Texas Instruments Incorporated
3
LPV542
ZHCSDK3 –MARCH 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN
-0.3
MAX
UNIT
V
Supply voltage, V+ to V–
6
(V+) + 0.3
10
Voltage(2)
Current(2)
(V-) - 0.3
V
Signal input pins
-10
mA
Output short current
Continuous(4)
Junction temperature
Storage temperature, Tstg
-40
-65
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should be
current-limited to 10 mA or less.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(4) Short-circuit to V-.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Ratings
MIN
1.6
NOM
MAX
5.5
UNIT
V
Supply Voltage ( V+– V−
Specified Temperature
)
-40
125
°C
6.4 Thermal Information
DGK (VSSOP)
8 PINS
DNX (X1SON)
THERMAL METRIC(1)
UNIT
8 PINS
46.3
33.3
21
RθJA
Junction-to-ambient thermal resistance
RθJC(top) Junction-to-case (top) thermal resistance
RθJB
ψJT
Junction-to-board thermal resistance
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.2
ψJB
21.2
7
RθJC(bot) Junction-to-case (bottom) thermal resistance
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
LPV542
www.ti.com.cn
ZHCSDK3 –MARCH 2015
6.5 Electrical Characteristics 1.8 V
TA = 25°C, V+ = 1.8V, V− = 0V, VCM = VO = V+/2, and RL > 1 MΩ , unless otherwise noted.
PARAMETER
OFFSET VOLTAGE
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
Input offset voltage (VOS
)
VCM = 0.3 V
VCM = 1.5 V
±1
±1
±2
±3
±4
mV
Over temperature
Drift (dVOS/dT)
VCM = 0.3 V and 1.5 V
1
µV/°C
dB
Power-Supply Rejection Ratio
(PSRR)
VS = 1.6 V to 5.5 V, VCM = 0.3 V
83
109
INPUT VOLTAGE RANGE
Common-mode voltage range (VCM
)
CMRR ≥ 60 dB
0
63
87
63
1.8
V
Common-Mode Rejection Ratio
(CMRR)
0 V < VCM < 1.8 V
0 V < VCM < 0.7 V
1.3 V < VCM < 1.8 V
92
92
98
dB
INPUT BIAS CURRENT
Input bias current (IB)
TA = 25°C
±0.1
±0.1
±1
±100
±1
TA = –40°C to 125°C
pA
Input offset current (IOS
)
INPUT IMPEDANCE
Differential
Common mode
NOISE
1013 || 2.5
1013 || 2.5
Ω || pF
Input voltage noise density, f = 1 kHz (en)
Current noise density, f = 1 kHz (in)
OPEN-LOOP GAIN
250
80
nV/√Hz
fA√Hz
Open-loop voltage gain (AOL
)
RL = 100 kΩ to V+/2, 0.5 V < VO < 1.3 V
91
101
dB
OUTPUT
Voltage output swing from positive rail
Voltage output swing from negative rail
Output current sourcing
RL = 100 kΩ to V+/2
RL = 100 kΩ to V+/2
Sourcing, VO to V–, VIN(diff) = 100 mV
Sinking, VO to V+, VIN(diff) = –100 mV
3
2
3
5
20
20
mV
mA
1
1
Output current sinking
FREQUENCY RESPONSE
Gain-bandwidth product (GBWP)
Slew rate (SR)
CL = 20 pF
7
3.4
3.7
kHz
G = +1, Rising edge, 1Vp-p, CL = 20 pF
G = +1, Falling edge, 1Vp-p, CL = 20 pF
V/ms
POWER SUPPLY
Specified voltage range (VS)
Quiescent current per channel (IQ)
Over temperature
1.6
5.5
800
V
VCM = 0.3 V, IO = 0
VCM = 1.5 V, IO = 0
490
680
1100
1100
1500
nA
Quiescent current per channel (IQ)
Over temperature
(1) Refer to Typical Characteristics.
Copyright © 2015, Texas Instruments Incorporated
5
LPV542
ZHCSDK3 –MARCH 2015
www.ti.com.cn
6.6 Electrical Characteristics 3.3 V
TA = 25°C, V+ = 3.3V, V− = 0V, VCM = VO = V+/2, and RL > 1 MΩ , unless otherwise noted.
PARAMETER
OFFSET VOLTAGE
TEST CONDITIONS
MIN
TYP(1)
MAX UNIT
Input offset voltage (VOS
)
VCM = 0.3
VCM = 3 V
±1
±1
±2
±3
±4
mV
Over temperature
Drift (dVOS/dT)
VCM = 0.3 V and 3 V
1
µV/°C
dB
Power-Supply Rejection Ratio
(PSRR)
VS = 1.6 V to 5.5 V, VCM = 0.3 V
83
109
INPUT VOLTAGE RANGE
Common-mode voltage range (VCM
)
CMRR ≥ 60 dB
0
64
88
64
3.3
V
Common-Mode Rejection Ratio
(CMRR)
0 V < VCM < 3.3 V
0 V < VCM < 2.2V
2.7 V < VCM < 3.3 V
98
98
dB
105
INPUT BIAS CURRENT
Input bias current (IB)
TA = 25°C
±0.1
±0.1
±1
±100
±1
TA = –40°C to 125°C
pA
Input offset current (IOS
)
INPUT IMPEDANCE
Differential
Common mode
NOISE
1013 || 2.5
1013 || 2.5
Ω || pF
Input voltage noise density, f = 1 kHz (en)
Current noise density, f = 1 kHz (in)
OPEN-LOOP GAIN
250
60
nV/√Hz
fA√Hz
Open-loop voltage gain (AOL
)
RL = 100 kΩ to V+/2, 0.5 V < VO < 2.8 V
91
101
dB
OUTPUT
Voltage output swing from positive Rail
Voltage output swing from negative Rail
Output current sourcing
RL = 100 kΩ to V+/2
RL = 100 kΩ to V+/2
Sourcing, VO to V–, VIN(diff) = 100 mV
Sinking, VO to V+, VIN(diff) = –100 mV
3
2
20
20
mV
mA
5
5
14
19
Output current sinking
FREQUENCY RESPONSE
Gain-bandwidth product (GBWP)
Slew rate (SR)
CL = 20 pF
8
3.6
3.7
kHz
G = +1, Rising edge, 1Vp-p, CL = 20 pF
G = +1, Falling edge, 1Vp-p, CL = 20 pF
V/ms
POWER SUPPLY
Specified voltage range (VS)
Quiescent current per channel (IQ)
Over temperature
1.6
5.5
800
V
VCM = 0.3 V, IO = 0
VCM = 3 V, IO = 0
480
650
1200
1100
1500
nA
Quiescent current per channel (IQ)
Over temperature
(1) Refer to Typical Characteristics.
6
Copyright © 2015, Texas Instruments Incorporated
LPV542
www.ti.com.cn
ZHCSDK3 –MARCH 2015
6.7 Electrical Characteristics 5 V
TA = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ , unless otherwise noted.
PARAMETER
OFFSET VOLTAGE
TEST CONDITIONS
MIN
TYP(1)
MAX UNIT
Input offset voltage (VOS
)
VCM = 0.3 V
VCM = 4.7V
±1
±1
±2
±3
±4
mV
Over temperature
Drift (dVOS/dT)
VCM = 0.3 V and 4.7V
1
µV/°C
dB
Power-Supply Rejection Ratio
(PSRR)
VS = 1.6 V to 5.5 V, VCM = 0.3 V
83
109
INPUT VOLTAGE RANGE
Common-Mode voltage range (VCM
)
CMRR ≥ 60 dB
0
73
88
73
5
V
Common-Mode Rejection Ratio
(CMRR)
0 V < VCM < 5 V
0 V < VCM < 3.9V
4.4 V < VCM < 5 V
101
101
109
dB
INPUT BIAS CURRENT
Input bias current (IB)
TA = 25°C
±0.1
±0.1
±1
±100
±1
TA = –40°C to 125°C
pA
Input offset current (IOS
)
INPUT IMPEDANCE
Differential
Common mode
NOISE
1013 || 2.5
1013 || 2.5
Ω || pF
Input voltage noise density, f = 1 kHz (en)
Current noise density, f = 1 kHz (in)
OPEN-LOOP GAIN
250
65
nV/√Hz
fA√Hz
Open-loop voltage gain (AOL
)
RL = 100 kΩ to V+/2, 0.5 V < VO < 4.5 V
91
101
dB
OUTPUT
Voltage output swing from positive rail
Voltage output swing from negative rail
Output current sourcing
RL = 100 kΩ to V+/2
RL = 100 kΩ to V+/2
Sourcing, VO to V–, VIN(diff) = 100 mV
Sinking, VO to V+, VIN(diff) = –100 mV
3
2
20
20
mV
mA
10
10
30
36
Output current sinking
FREQUENCY RESPONSE
Gain-bandwidth product (GBWP)
Slew rate (SR)
CL = 20 pF
8
3.6
3.7
kHz
G = +1, Rising edge, 1Vp-p, CL = 20 pF
G = +1, Falling edge, 1Vp-p, CL = 20 pF
V/ms
POWER SUPPLY
Specified voltage range (VS)
Quiescent current per channel (IQ)
Over temperature
1.6
5.5
850
V
VCM = 0.3 V, IO = 0
VCM = 4.7 V, IO = 0
480
680
1300
1100
1600
nA
Quiescent current per channel (IQ)
Over temperature
(1) Refer to Typical Characteristics.
Copyright © 2015, Texas Instruments Incorporated
7
LPV542
ZHCSDK3 –MARCH 2015
www.ti.com.cn
6.8 Typical Characteristics
TA = 25 °C, VS = 5 V, VOUT = VCM = VS/2, RLOAD = 1 MΩ connected to VS/2, and CL = 20 pF, unless otherwise noted.
1000
900
800
700
600
500
400
300
200
100
0
1000
900
800
700
600
500
400
300
200
100
0
VCM = 0.3V
VCM = VS - 0.3V
125°C
85°C
25°C
0°C
125°C
85°C
25°C
0°C
-40°C
-40°C
1.5
2
2.5
3
3.5
4
4.5
5
5.5
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
Supply Voltage (V)
C001
C001
No Output Load
VCM = 0.3 V
No Output Load
VCM = (V+) – 0.3 V
Figure 1. Supply Voltage vs Supply Current per Channel,
Low Vcm
Figure 2. Supply Voltage vs Supply Current per Channel,
High Vcm
1000
900
800
700
600
500
400
1000
900
800
700
600
500
400
125°C
85°C
25°C
0°C
125°C
85°C
25°C
0°C
300
200
100
0
300
200
100
0
-40°C
-40°C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
Common Mode Voltage (V)
Common Mode Voltage (V)
C001
C001
No Output Load
No Output Load
Figure 3. Supply Current vs
Common Mode at 1.8 V
Figure 4. Supply Current vs
Common Mode at 2.7 V
1000
900
800
700
600
500
400
300
200
100
0
1000
900
800
700
600
500
400
300
200
100
0
125°C
85°C
25°C
0°C
125°C
85°C
25°C
0°C
-40°C
-40°C
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Common Mode Voltage (V)
Common Mode Voltage (V)
C001
C001
No Output Load
No Output Load
Figure 5. Supply Current vs
Common Mode at 3.3 V
Figure 6. Supply Current vs
Common Mode at 5 V
8
Copyright © 2015, Texas Instruments Incorporated
LPV542
www.ti.com.cn
ZHCSDK3 –MARCH 2015
Typical Characteristics (continued)
TA = 25 °C, VS = 5 V, VOUT = VCM = VS/2, RLOAD = 1 MΩ connected to VS/2, and CL = 20 pF, unless otherwise noted.
100
100
10
10
1
1
0.1
0.1
-40°C
25°C
-40°C
25°C
0.01
0.001
0.01
0.001
125°C
125°C
1
10
100
1000
10000
1
10
100
1000
10000
Output Referred to V- (mV)
Output Referred to V+ (mV)
SNK
SRC
VS = 1.8 V
VS = 1.8 V
Figure 7. Output Sinking Current vs
Output Swing at 1.8 V
Figure 8. Output Sourcing Current vs
Output Swing at 1.8 V
100
10
100
10
1
1
0.1
0.1
-40°C
25°C
-40°C
25°C
0.01
0.001
0.01
0.001
125°C
125°C
1
10
100
1000
10000
1
10
100
1000
10000
Output Referred to V- (mV)
SNK
Output Referred to V+ (mV)
SRC
VS = 2.7 V
VS = 2.7 V
Figure 9. Output Sinking Current vs
Output Swing at 2.7 V
Figure 10. Output Sourcing Current vs
Output Swing at 2.7 V
100
10
100
10
1
1
0.1
0.1
-40°C
25°C
-40°C
0.01
0.001
0.01
0.001
25°C
125°C
10000
125°C
1
10
100
1000
1
10
100
1000
10000
Output Referred to V- (mV)
Output Referred to V+ (mV)
SNK
SRC
VS = 3.3 V
VS = 3.3 V
Figure 11. Output Sinking Current vs
Output Swing at 3.3 V
Figure 12. Output Sourcing Current vs
Output Swing at 3.3 V
Copyright © 2015, Texas Instruments Incorporated
9
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ZHCSDK3 –MARCH 2015
www.ti.com.cn
Typical Characteristics (continued)
TA = 25 °C, VS = 5 V, VOUT = VCM = VS/2, RLOAD = 1 MΩ connected to VS/2, and CL = 20 pF, unless otherwise noted.
100
100
10
10
1
1
0.1
0.1
-40°C
25°C
-40°C
25°C
0.01
0.001
0.01
0.001
125°C
125°C
1
10
100
1000
10000
1
10
100
1000
10000
Output Referred to V- (mV)
Output Referred to V+ (mV)
SNK
SRC
VS = 5 V
VS = 5 V
Figure 13. Output Sinking Current vs
Output Swing at 5 V
Figure 14. Output Sourcing Current vs
Output Swing at 5 V
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
-40°C
25°C
-40°C
25°C
125°C
125°C
0
0
1.5
2
2.5
3
3.5
4
4.5
5
1.5
2
2.5
3
3.5
4
4.5
5
Supply Voltage (V)
Supply Voltage (V)
SHR
SHR
Output set high (sourcing), shorted to V–
Ouput set low (sinking), shorted to V+
Figure 15. Output Short Circut Current to V- vs
Supply Voltage
Figure 16. Output Short Circut Current to V+ vs
Supply Voltage
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
-0.3
0.3
0.9
1.5
2.1
2.7
3.3
-0.3
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
Common Mode Voltage (V)
Common Mode Voltage (V)
C004
C001
VS = 3.3 V
TA = 25°C
VS = 1.8 V
TA = 25°C
Figure 18. Input Bias Current vs
Common Mode Voltage at 3.3V
Figure 17. Input Bias Current vs
Common Mode Voltage at 1.8 V
10
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ZHCSDK3 –MARCH 2015
Typical Characteristics (continued)
TA = 25 °C, VS = 5 V, VOUT = VCM = VS/2, RLOAD = 1 MΩ connected to VS/2, and CL = 20 pF, unless otherwise noted.
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-0.3 0.3 0.9 1.5 2.1 2.7 3.3 3.9 4.5 5.1
-0.3
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
Common Mode Voltage (V)
Common Mode Voltage (V)
C007
C002
VS = 5 V
TA = 25°C
VS = 1.8 V
TA = 85°C
Figure 19. Input Bias Current vs
Common Mode Voltage at 5V
Figure 20. Input Bias Current vs
Common Mode Voltage at 1.8V
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0.5
0.0
0.0
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
-0.3
0.3
0.9
1.5
2.1
2.7
3.3
-0.3 0.3 0.9 1.5 2.1 2.7 3.3 3.9 4.5 5.1
Common Mode Voltage (V)
Common Mode Voltage (V)
C005
C008
VS = 3.3 V
TA = 85°C
VS = 5 V
TA = 85°C
Figure 21. Input Bias Current vs
Common Mode Voltage at 3.3 V
Figure 22. Input Bias Current vs
Common Mode Voltage at 5 V
50
40
50
40
30
30
20
20
10
10
0
0
-10
-20
-30
-40
-50
-10
-20
-30
-40
-50
-0.3
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
-0.3
0.3
0.9
1.5
2.1
2.7
3.3
Common Mode Voltage (V)
Common Mode Voltage (V)
C003
C006
VS = 1.8 V
TA = 125°C
VS = 3.3 V
TA = 125°C
Figure 23. Input Bias Current vs
Common Mode Voltage at 1.8 V
Figure 24. Input Bias Current vs
Common Mode Voltage at 3.3 V
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Typical Characteristics (continued)
TA = 25 °C, VS = 5 V, VOUT = VCM = VS/2, RLOAD = 1 MΩ connected to VS/2, and CL = 20 pF, unless otherwise noted.
50
10k
VS = 5V
RL=100k
40
30
20
10
0
1k
-10
-20
-30
-40
-50
100
-0.3 0.3 0.9 1.5 2.1 2.7 3.3 3.9 4.5 5.1
Common Mode Voltage (V)
100m
1
10
100
1k
10k
100k
Frequency (Hz)
C009
C001
VS = 5 V
TA = 125°C
CL = 20 pF
VS = 5 V
RL = 100 kΩ
CL = 20 pF
Figure 25. Input Bias Current vs
Common Mode Voltage at 5 V
Figure 26. Input Referred Voltage Noise
IN
IN
OUT
OUT
Time (100us/div)
Time (200us/div)
C001
C002
VS = ±0.9 V
G = +1
RL = 10 MΩ
CL = 20 pF
VS = ±0.9 V
G = +1
RL = 10 MΩ
CL = 20 pF
VIN = ±100 mV
VIN = ±500mV
Figure 27. Pulse Response, 200mVpp at 1.8 V
Figure 28. Pulse Response, 1Vpp at 1.8V
IN
IN
OUT
OUT
Time (100us/div)
Time (200us/div)
C003
C002
VS = ±2.5 V
G = +1
RL = 10 MΩ
CL = 20 pF
VS = ±2.5 V
G = +1
RL = 10 MΩ
CL = 20 pF
VIN = ±100 mV
VIN = ±1V
Figure 29. Pulse Response, 200mVpp at 5V
Figure 30. Pulse Response, 2Vpp at 5V
12
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Typical Characteristics (continued)
TA = 25 °C, VS = 5 V, VOUT = VCM = VS/2, RLOAD = 1 MΩ connected to VS/2, and CL = 20 pF, unless otherwise noted.
40
30
20
10
0
180
135
90
40
30
20
10
0
180
135
90
-40°C
25°C
125°C
-40°C
25°C
125°C
Gain
Gain
Phase
Phase
45
45
0
0
±10
±45
±10
±45
100
1000
10000
100000
100
100
100
1000
10000
100000
Frequency (Hz)
Frequency (Hz)
C011
C008
VS = 1.8 V
RL = 100 kΩ
CL = 20 pF
VS = 5 V
RL = 100 kΩ
CL = 20 pF
Figure 31. Gain and Phase vs
Temperature at 1.8 V
Figure 32. Gain and Phase vs
Temperature at 5 V
40
30
20
10
0
180
40
30
20
10
0
180
-40°C
-40°C
Gain
Gain
25°C
25°C
125°C
125°C
135
90
135
90
Phase
Phase
45
45
0
0
±10
±45
100000
±10
±45
100000
100
1000
10000
1000
10000
Frequency (Hz)
Frequency (Hz)
C012
C009
VS = 1.8 V
RL = 1 MΩ
CL = 20 pF
VS = 5 V
RL = 1 MΩ
CL = 20 pF
Figure 33. Gain and Phase vs
Temperature at 1.8 V
Figure 34. Gain and Phase vs
Temperature at 5 V
40
30
20
10
0
180
40
30
20
10
0
180
-40°C
-40°C
Gain
Gain
25°C
25°C
125°C
125°C
135
90
135
90
Phase
Phase
45
45
0
0
±10
±45
100000
±10
±45
100000
1000
10000
100
1000
10000
Frequency (Hz)
Frequency (Hz)
C010
C013
VS = 5 V
RL = 10 MΩ
CL = 20 pF
VS = 1.8 V
RL = 10 MΩ
CL = 20 pF
Figure 36. Gain and Phase vs
Temperature at 5 V
Figure 35. Gain and Phase vs
Temperature at 1.8 V
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LPV542
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7 Detailed Description
7.1 Overview
The LPV542 dual op amplifier is unity-gain stable and can operate on a single supply, making it highly versatile
and easy to use.
The LPV542 is fully specified and tested from 1.6 V to 5.5 V. Parameters that vary significantly with operating
voltages or temperature are shown in the Typical Characteristics curves.
7.2 Functional Block Diagram
7.3 Feature Description
The amplifier's differential inputs consist of a non-inverting input (+IN) and an inverting input (–IN). The amplifer
amplifies only the difference in voltage between the two inputs, which is called the differential input voltage. The
output voltage of the op-amp VOUT is given by Equation 1:
VOUT = AOL (IN+ – IN–)
where
•
AOL is the open-loop gain of the amplifier, typically around 100 dB (100,000x, or 100,000 Volts per microvolt).
(1)
7.4 Device Functional Modes
7.4.1 Rail-To-Rail Input
The input common-mode voltage range of the LPV542 extends to the supply rails. This is achieved with a
complementary input stage — an N-channel input differential pair in parallel with a P-channel differential pair.
The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 800 mV to 200 mV above
the positive supply, while the P-channel pair is on for inputs from 300 mV below the negative supply to
approximately (V+) – 800 mV. There is a small transition region, typically (V+) – 1.2 V to (V+) – 0.8 V, in which
both pairs are on. This 400 mV transition region can vary 200 mV with process variation. Within the 400 mV
transition region PSRR, CMRR, offset voltage, offset drift, and THD may be degraded compared to operation
outside this region.
7.4.2 Supply Current Changes over Common Mode
Because of the ultra-low supply current, changes in common mode voltages will cause a noticeable change in
the supply current as the input stages transition through the transition region, as shown in Figure 37 below.
1000
900
800
700
600
500
400
125°C
85°C
25°C
0°C
300
200
100
0
-40°C
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Common Mode Voltage (V)
C001
Figure 37. Supply Current Change over Common Mode at 5 V
14
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Device Functional Modes (continued)
For the lowest supply current operation, keep the input common mode range between V- and 1 V below V+.
7.4.3 Design Optimization With Rail-To-Rail Input
In most applications, operation is within the range of only one differential pair. However, some applications can
subject the amplifier to a common-mode signal in the transition region. Under this condition, the inherent
mismatch between the two differential pairs may lead to degradation of the CMRR and THD. The unity-gain
buffer configuration is the most problematic as it will traverse through the transition region if a sufficiently wide
input swing is required.
7.4.4 Design Optimization for Nanopower Operation
When designing for ultralow power, choose system components carefully. To minimize current consumption,
select large-value resistors. Any resistors will react with stray capacitance in the circuit and the input capacitance
of the operational amplifier. These parasitic RC combinations can affect the stability of the overall system. A
feedback capacitor may be required to assure stability and limit overshoot or gain peaking.
When possible, use AC coupling and AC feedback to reduce static current draw through the feedback elements.
Use film or ceramic capacitors since large electolytics may have static leakage currents in the tens to hundreds
of nanoamps.
7.4.5 Common-Mode Rejection
The CMRR for the LPV542 is specified in two ways so the best match for a given application may be used. First,
the CMRR of the device in the common-mode range below the transition region (VCM < (V+) – 0.9 V) is given.
This specification is the best indicator of the capability of the device when the application requires use of one of
the differential input pairs. Second, the CMRR at VS = 5 V over the entire common-mode range is specified.
7.4.6 Output Stage
The LPV542 output voltage swings 3 mV from rails at 3.3 V supply, which provides the maximum possible
dynamic range at the output. This is particularly important when operating on low supply voltages.
The LPV542 Maximum Output Voltage Swing defines the maximum swing possible under a particular output
load.
7.4.7 Driving Capacitive Load
The LPV542 is internally compensated for stable unity gain operation, with a 8 kHz typical gain bandwidth.
However, the unity gain follower is the most sensitive configuration to capacitive load. The combination of a
capacitive load placed directly on the output of an amplifier along with the amplifier’s output impedance creates a
phase lag, which reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the
response will be under damped which causes peaking in the transfer and, when there is too much peaking, the
op amp might start oscillating.
In order to drive heavy (>50pF) capacitive loads, an isolation resistor, RISO, should be used, as shown in
Figure 38. By using this isolation resistor, the capacitive load is isolated from the amplifier’s output. The larger
the value of RISO, the more stable the amplifier will be. If the value of RISO is sufficiently large, the feedback loop
will be stable, independent of the value of CL. However, larger values of RISO result in reduced output swing and
reduced output current drive.
R
ISO
-
V
OUT
V
IN
+
C
L
Figure 38. Resistive Isolation Of Capacitive Load
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LPV542
ZHCSDK3 –MARCH 2015
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LPV542 is a ultra-low power operational amplifier that provides 8 kHz bandwidth with only 490nA quiescent
current, and near precision offset and drift specifications at a low cost. These rail-to-rail input and output
amplifiers are specifically designed for battery-powered applications. The input common-mode voltage range
extends to the power-supply rails and the output swings to within millivolts of the rails, maintaining a wide
dynamic range.
8.2 Typical Application: 60 Hz Twin "T" Notch Filter
V
= 3V oꢀ2V @ end of life
BATT
CR2032 Coin Cell
225 mAh = 5 circuits @ 9.5 yrs.
10 M:
10 M:
V
BATT
-
Remote Sensor
To ADC
V
OUT
10 M:
10 M:
+
V
IN
Signal
+
60 Hz
Signal × 2
(No 60 Hz)
270 pF
270 pF
60 Hz Twin T Notch Filter
= 2 V/V
10 M:
10 M:
A
V
270 pF
270 pF
Figure 39. 60 Hz Notch Filter
8.2.1 Design Requirements
Small signals from transducers in remote and distributed sensing applications commonly suffer strong 60 Hz
interference from AC power lines. The circuit of Figure 39 notches out the 60 Hz and provides a gain AV = 2 for
the sensor signal represented by a 1 kHz sine wave. Similar stages may be cascaded to remove 2nd and 3rd
harmonics of 60 Hz. Thanks to the nA power consumption of the LPV542, even 5 such circuits can run for 9.5
years from a small CR2032 lithium cell. These batteries have a nominal voltage of 3 V and an end of life voltage
of 2 V. With an operating voltage from 1.6 V to 5.5 V the LPV542 can function over this voltage range.
8.2.2 Detailed Design Procedure
The notch frequency is set by:
F0 = 1 / 2πRC.
(2)
To achieve a 60 Hz notch use R = 10 MΩ and C = 270 pF. If eliminating 50 Hz noise, which is common in
European systems, use R = 11.8 MΩ and C = 270 pF.
The Twin T Notch Filter works by having two separate paths from VIN to the amplifier’s input. A low frequency
path through the series input resistors and another separate high frequency path through the series input
capacitors. However, at frequencies around the notch frequency, the two paths have opposing phase angles and
the two signals will tend to cancel at the amplifier’s input.
16
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LPV542
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ZHCSDK3 –MARCH 2015
Typical Application: 60 Hz Twin "T" Notch Filter (continued)
To ensure that the target center frequency is achieved and to maximize the notch depth (Q factor) the filter
needs to be as balanced as possible. To obtain circuit balance, while overcoming limitations of available
standard resistor and capacitor values, use passives in parallel to achieve the 2C and R/2 circuit requirements
for the filter components that connect to ground.
To make sure passive component values stay as expected clean board with alcohol, rinse with deionized water,
and air dry. Make sure board remains in a relatively low humidity environment to minimize moisture which may
increase the conductivity of board components. Also large resistors come with considerable parasitic stray
capacitance which effects can be reduced by cutting out the ground plane below components of concern.
Large resistors are used in the feedback network to minimize battery drain. When designing with large resistors,
resistor thermal noise, op amp current noise, as well as op amp voltage noise, must be considered in the noise
analysis of the circuit. The noise analysis for the circuit in Figure 39 can be done over a bandwidth of 2 kHz,
which takes the conservative approach of overestimating the bandwidth (LPV542 typical GBW/AV is lower). The
total noise at the output is approximately 800 µVpp, which is excellent considering the total consumption of the
circuit is only 900 nA. The dominant noise terms are op amp voltage noise , current noise through the feedback
network (430 µVpp), and current noise through the notch filter network (280 µVpp). Thus the total circuit's noise
is below 1/2 LSB of a 10-bit system with a 2 V reference, which is 1 mV.
8.2.3 Application Curve
Figure 40. 60 Hz Notch Filter Waveform
8.3 Do's and Don'ts
Do properly bypass the power supplies.
Do add series resistance to the output when driving capacitive loads, particularly cables, Muxes and ADC inputs.
Do add series current limiting resistors and external schottky clamp diodes if input voltage is expected to exceed
the supplies. Limit the current to 1 mA or less (1 KΩ per volt).
Copyright © 2015, Texas Instruments Incorporated
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ZHCSDK3 –MARCH 2015
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9 Power Supply Recommendations
The LPV542 is specified for operation from 1.6 V to 5.5 V (±0.8 V to ±2.75 V) over a –40°C to 125°C
temperature range. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 6 V can permanently damage the device.
For proper operation, the power supplies bust be properly decoupled. For decoupling the supply lines it is
suggested that 10 nF capacitors be placed as close as possible to the operational amplifier power supply pins.
For single supply, place a capacitor between V+ and V– supply leads. For dual supplies, place one capacitor
between V+ and ground, and one capacitor between V– and ground.
Low bandwidth nanopower devices do not have good high frequency (> 1 kHz) AC PSRR rejection against high-
frequency switching supplies and other 1 kHz and above noise sources, so extra supply filtering is recommended
if kilohertz or above noise is expected on the power supply lines.
10 Layout
10.1 Layout Guidelines
The V+ pin should be bypassed to ground with a low ESR capacitor.
The optimum placement is closest to the V+ and ground pins.
Care should be taken to minimize the loop area formed by the bypass capacitor connection between V+ and
ground.
The ground pin should be connected to the PCB ground plane at the pin of the device.
The feedback components should be placed as close to the device as possible to minimize strays.
There is an internal electrical connection between the exposed Die Attach Pad (DAP) and the V- pin. For best
performance the DAP should be connected to the exact same potential as the V- pin. Do not use the DAP as the
primary V- supply. Floating the DAP pad is not recommended. The DAP and V- pin should be joined directly as
shown in the Layout Example.
10.2 Layout Example
Figure 41. X1SON Layout Example (top view)
18
版权 © 2015, Texas Instruments Incorporated
LPV542
www.ti.com.cn
ZHCSDK3 –MARCH 2015
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
TINA-TI 基于 SPICE 的模拟仿真程序，http://www.ti.com.cn/tool/cn/tina-ti
DIP 适配器评估模块，http://www.ti.com.cn/tool/cn/dip-adapter-evm
TI 通用运行放大器评估模块，http://www.ti.com.cn/tool/cn/opampevm
TI FilterPro 滤波器设计软件，http://www.ti.com.cn/tool/cn/filterpro
11.2 文档支持
11.2.1 相关文档
相关文档如下：
•
•
•
•
•
•
•
•
AN-1798《设计电化学传感器》，SNOA514
AN-1803《互阻抗放大器设计注意事项》，SNOA515
AN-1852《设计 pH 电极》，SNOA529
《直观补偿互阻抗放大器》，SBOA055
《高速运算放大器互阻抗注意事项》，SBOA112
《FET 互阻抗放大器噪声分析》，SBOA060
《电路板布局布线技巧》，SLOA089
《运算放大器应用手册》，SBOA092
11.3 商标
All trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
12 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015, Texas Instruments Incorporated
19
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LPV542DGKR
LPV542DGKT
ACTIVE
VSSOP
VSSOP
DGK
8
8
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
LP
V542
Samples
Samples
ACTIVE
DGK
NIPDAUAG | SN
LP
V542
LPV542DNXR
LPV542DNXT
ACTIVE
ACTIVE
X1SON
X1SON
DNX
DNX
8
8
NIPDAUAG
NIPDAUAG
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
LPV542
Samples
Samples
LPV542
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jul-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
DNX0008A
X1SON - 0.5 mm max height
SCALE 4.300
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.5 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
(0.127)
TYP
1.65±0.1
4
1
5
2X
1.5
2.38±0.1
8
6X 0.5
0.3
8X
0.2
0.45
0.35
PIN 1 ID
(OPTIONAL)
0.1
0.05
C A
C
B
8X
4221623/A 08/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DNX0008A
X1SON - 0.5 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
SYMM
8X (0.6)
1
8
8X (0.25)
SYMM
(2.38)
(0.94)
5
6X (0.5)
4
(0.575)
(
0.2) VIA
TYP
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221623/A 08/2014
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DNX0008A
X1SON - 0.5 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.51)
SYMM
METAL
TYP
8X (0.6)
1
8
2X
(1.06)
8X (0.25)
SYMM
(0.63)
6X (0.5)
5
4
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
82% PRINTED SOLDER COVERAGE BY AREA
SCALE:30X
4221623/A 08/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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