LPV7215MF/NOPB [TI]
毫微功耗 CMOS 单路比较器 | DBV | 5 | -40 to 125;
| 型号： | LPV7215MF/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 毫微功耗 CMOS 单路比较器 | DBV | 5 | -40 to 125 比较器 |
| 文件： | 总36页 (文件大小：1768K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LPV7215
SNOSAI6J –SEPTEMBER 2005–REVISED AUGUST 2016
LPV7215 Micropower, CMOS Input, RRIO, 1.8-V, Push-Pull Output Comparator
1 Features
3 Description
•
(For V+ = 1.8 V, Typical Unless Otherwise Noted)
Ultra-Low Power Consumption: 580 nA
Wide Supply Voltage Range: 1.8 V to 5.5 V
Propagation Delay: 4.5 µs
The LPV7215 device is an ultra-low-power
comparator with a typical power supply current of
580 nA. It has the best-in-class power supply current
versus propagation delay performance available
among TI's low-power comparators. The propagation
delay is as low as 4.5 µs with 100-mV overdrive at
1.8-V supply.
1
•
•
•
•
•
•
•
Push-Pull Output Current Drive at 5 V 19 mA
Temperature Range: −40°C to 125°C
Rail-to-Rail Input
Designed to operate over a wide range of supply
voltages, from 1.8 V to 5.5 V, with ensured operation
at 1.8 V, 2.7 V, and 5 V, the LPV7215 is ideal for use
in a variety of battery-powered applications. With rail-
to-rail common-mode voltage range, the LPV7215 is
well suited for single-supply operation.
Tiny 5-Pin SOT-23 and SC70 Packages
2 Applications
•
•
•
•
•
RC Timers
Featuring a push-pull output stage, the LPV7215
allows for operation with absolute minimum power
consumption when driving any capacitive or resistive
load.
Window Detectors
IR Receivers
Multivibrators
Alarm and Monitoring Circuits
Available in a choice of space-saving packages, the
LPV7215 is ideal for use in handheld electronics and
mobile phone applications. The LPV7215 is
manufactured with TI's advanced VIP50 process.
Device Information(1)
PART NUMBER
PACKAGE
SOT-23 (5)
SC70 (5)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
2.00 mm × 1.25 mm
LPV7215
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Supply Current vs Supply Voltage
Propagation Delay vs Overdrive
900
18
V
CM
= 0.8V
+
V
T
= 1.8V
= 25°C
800
700
A
85°C
13
600
500
400
300
200
100
0
25°C
-40°C
t
PD L-H
8
3
t
PD H-L
0
1
2
3
4
5
6
1
10
100
1000
SUPPLY VOLTAGE (V)
OVERDRIVE (mV)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LPV7215
SNOSAI6J –SEPTEMBER 2005–REVISED AUGUST 2016
www.ti.com
Table of Contents
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 16
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Applications ................................................ 20
Power Supply Recommendations...................... 24
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ..................................... 3
6.2 ESD Ratings.............................................................. 3
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics: 1.8 V ............................... 4
6.6 Electrical Characteristics: 2.7 V ............................... 6
6.7 Electrical Characteristics: 5 V ................................... 7
6.8 Typical Characteristics.............................................. 9
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
8
9
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 24
11 Device and Documentation Support ................. 25
11.1 Device Support .................................................... 25
11.2 Receiving Notification of Documentation Updates 25
11.3 Community Resources.......................................... 25
11.4 Trademarks........................................................... 25
11.5 Electrostatic Discharge Caution............................ 25
11.6 Glossary................................................................ 25
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (April 2013) to Revision J
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Updated values in the Thermal Information table to align with JEDEC standards. ............................................................... 4
Changes from Revision H (April 2013) to Revision I
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 22
2
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SNOSAI6J –SEPTEMBER 2005–REVISED AUGUST 2016
5 Pin Configuration and Functions
DBV and DCK Package
5-Pin SOT-23 and SC70
Top View
Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
VOUT
V–
O
P
I
Output
2
Negative Supply
Noninverting Input
Inverting Input
3
VIN+
VIN–
V+
4
I
5
P
Positive Supply
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
2.5
UNIT
V
VIN differential
−2.5
Supply voltage (V+ - V−)
6
V
Voltage at input and output pins
V− − 0.3
V+ + 0.3
V
(2)
Junction temperature, TJ
150
°C
°C
Storage temperature, Tstg
−65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA . All numbers apply for packages soldered directly onto a PCB.
6.2 ESD Ratings
VALUE
±2000
±200
UNIT
Human-body model (HBM)(1)
Machine model (MM)(2)
V(ESD)
Electrostatic discharge
V
(1) Human-body model, applicable std. MIL-STD-883, Method 3015.7.
(2) Machine model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-
C101-C (ESD FICDM std. of JEDEC).
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
–40
1.8
MAX
125
5.5
UNIT
°C
Temperature(1)
Supply voltage (V+ – V−)
V
(1) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA . All numbers apply for packages soldered directly onto a PCB.
6.4 Thermal Information
LPV7215
THERMAL METRIC(1)
DBV (SOT-23)
DCK (SC70)
5 PINS
456
UNIT
5 PINS
234
RθJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
153
110.8
59.8
51.7
38
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
3.6
ψJB
51.2
n/a
59
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA . All numbers apply for packages soldered directly onto a PCB.
6.5 Electrical Characteristics: 1.8 V
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 1.8V, V− = 0 V, and VCM = V+/2, VO= V−.(1)
(2)
(3)
(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25°C
580
750
1050
980
1300
±6
VCM = 0.3 V
Temperature
extremes
IS
Supply current
nA
TA = 25°C
790
VCM = 1.5 V
VCM = 0 V
Temperature
extremes
TA = 25°C
±0.3
±0.4
Temperature
extremes
±8
VOS
Input offset voltage
mV
TA = 25°C
±5
VCM = 1.8 V
Temperature
extremes
±7
(4)
TCVOS
IB
Input offset average drift
See
±1
−40
10
µV/C
fA
(5)
Input bias current
VCM = 1.6 V
IOS
Input offset current
fA
(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using
statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
(4) Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
(5) Positive current corresponds to current flowing into the device.
4
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Electrical Characteristics: 1.8 V (continued)
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 1.8V, V− = 0 V, and VCM = V+/2, VO= V−.(1)
(2)
(3)
(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25°C
66
88
VCM Stepped from
0 V to 0.7 V
Temperature
extremes
62
68
62
44
43
66
63
TA = 25°C
87
77
82
VCM Stepped from
1.2 V to 1.8 V
CMRR
Common-mode rejection ratio
dB
Temperature
extremes
TA = 25°C
VCM Stepped from
0 V to 1.8 V
Temperature
extremes
TA = 25°C
V+ = 1.8 V to 5.5
V, VCM = 0 V
PSRR
Power supply rejection ratio
dB
Temperature
extremes
Temperature
Extremes
CMVR
AV
Input common-mode voltage range
Voltage gain
CMRR ≥ 40 dB
–0.1
1.9
V
120
dB
TA = 25°C
1.63
1.58
1.46
1.37
1.69
IO = 500 µA
IO = 1 mA
Temperature
extremes
Output swing high
Output swing low
Output current
V
TA = 25°C
1.6
88
Temperature
extremes
VO
TA = 25°C
180
230
310
400
IO = −500 µA
IO = −1 mA
Temperature
extremes
mV
mA
TA = 25°C
180
2.26
3.1
Temperature
extremes
TA = 25°C
1.75
1.3
Source
VO = V+/2
Temperature
extremes
IOUT
TA = 25°C
2.35
1.45
Sink
VO = V+/2
Temperature
extremes
Overdrive = 10 mV
13
Propagation delay
(high to low)
TA = 25°C
4.5
6.5
9
µs
µs
Overdrive = 100
mV
Temperature
extremes
Overdrive = 10 mV
12.5
6.6
Propagation delay
(low to high)
TA = 25°C
9
Overdrive = 100
mV
Temperature
extremes
12
Overdrive = 10 mV
CL = 30 pF, RL = 1 MΩ
80
75
70
65
trise
Rise time
Fall time
ns
ns
Overdrive = 100 mV
CL = 30 pF, RL = 1 MΩ
Overdrive = 10 mV
CL = 30 pF, RL = 1 MΩ
tfall
Overdrive = 100 mV
CL = 30 pF, RL = 1 MΩ
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6.6 Electrical Characteristics: 2.7 V
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 2.7 V, V− = 0 V, and VCM = V+/2, VO= V−.(1)
(2)
(3)
(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25°C
605
780
1100
1010
1350
±6
VCM = 0.3 V
Temperature
extremes
IS
Supply current
nA
TA = 25°C
815
VCM = 2.4 V
VCM = 0 V
Temperature
extremes
TA = 25°C
±0.3
±0.3
Temperature
extremes
±8
VOS
Input offset voltage
mV
TA = 25°C
±5
VCM = 2.7 V
Temperature
extremes
±7
(4)
TCVOS
IB
Input offset average drift
See
±1
−40
20
µV/C
fA
(5)
Input bias current
VCM = 1.8 V
IOS
Input offset current
fA
TA = 25°C
72
66
71
63
47
46
66
63
90
VCM Stepped
from 0 V to 1.6 V
Temperature
extremes
TA = 25°C
94
80
82
VCM Stepped
from 2.1V to 2.7V
CMRR
Common-mode rejection ratio
dB
Temperature
extremes
TA = 25°C
VCM Stepped
from 0 V to 2.7 V
Temperature
extremes
TA = 25°C
V+ = 1.8 V to 5.5
V, VCM = 0 V
PSRR
Power supply rejection ratio
dB
Temperature
extremes
Temperature
extremes
CMVR
AV
Input common-mode voltage range
Voltage gain
CMRR ≥ 40 dB
−0.1
2.8
V
120
dB
TA = 25°C
2.57
2.53
2.47
2.4
2.62
IO = 500 µA
IO = 1 mA
Temperature
extremes
Output swing high
Output swing low
V
TA = 25°C
2.53
60
Temperature
extremes
VO
TA = 25°C
130
190
250
330
IO = −500 µA
IO = −1 mA
Temperature
extremes
mV
TA = 25°C
120
Temperature
extremes
(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using
statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
(4) Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
(5) Positive current corresponds to current flowing into the device.
6
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Electrical Characteristics: 2.7 V (continued)
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 2.7 V, V− = 0 V, and VCM = V+/2, VO= V−.(1)
(2)
(3)
(2)
PARAMETER
TEST CONDITIONS
TA = 25°C
MIN
TYP
MAX
UNIT
4.5
3.4
5.6
3.2
5.7
Source
VO = V+/2
Temperature
extremes
IOUT
Output current
mA
TA = 25°C
7.5
Sink
VO = V+/2
Temperature
extremes
Overdrive = 10 mV
14.5
5.8
Propagation delay
(high to low)
TA = 25°C
8.5
Overdrive = 100
mV
Temperature
extremes
10.5
µs
Overdrive = 10 mV
15
Propagation delay
(low to high)
TA = 25°C
7.5
10
Overdrive = 100
mV
Temperature
extremes
12.5
Overdrive = 10 mV
CL = 30 pF, RL = 1 MΩ
90
85
85
75
trise
Rise time
Fall time
ns
ns
Overdrive = 100 mV
CL = 30 pF, RL = 1 MΩ
Overdrive = 10 mV
CL = 30 pF, RL = 1 MΩ
tfall
Overdrive = 100 mV
CL = 30 pF, RL = 1 MΩ
6.7 Electrical Characteristics: 5 V
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 5 V, V− = 0 V, and VCM = V+/2, VO= V−.
(1)
(2)
(3)
(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25°C
612
790
VCM = 0.3 V
Temperature
extremes
1150
1030
1400
±6
IS
Supply current
nA
TA = 25°C
825
VCM = 4.7 V
VCM = 0 V
VCM = 5 V
Temperature
extremes
TA = 25°C
±0.3
Temperature
extremes
±8
VOS
Input offset voltage
mV
TA = 25°C
±5
Temperature
extremes
±7
(4)
TCVOS
IB
Input offset average drift
See
±1
−400
20
µV/C
fA
(5)
Input bias current
VCM = 4.5 V
IOS
Input offset current
fA
(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using
statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
(4) Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
(5) Positive current corresponds to current flowing into the device.
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Electrical Characteristics: 5 V (continued)
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 5 V, V− = 0 V, and VCM = V+/2, VO= V−. (1)
(2)
(3)
(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25°C
72
98
VCM Stepped from
0 V to 3.9 V
Temperature
extremes
66
73
67
53
49
66
63
TA = 25°C
92
82
82
VCM Stepped from
4.4 V to 5 V
CMRR
Common-mode rejection ratio
dB
Temperature
extremes
TA = 25°C
VCM Stepped from
0 V to 5 V
Temperature
extremes
TA = 25°C
V+ = 1.8 V to 5.5
V, VCM = 0 V
PSRR
Power supply rejection ratio
dB
Temperature
extremes
Temperature
extremes
CMVR
AV
Input common-mode voltage range
Voltage gain
CMRR ≥ 40 dB
−0.1
5.1
V
120
dB
TA = 25°C
4.9
4.86
4.82
4.77
4.94
IO = 500 µA
IO = 1 mA
Temperature
extremes
Output swing high
Output swing low
Output current
V
TA = 25°C
4.89
43
Temperature
extremes
VO
TA = 25°C
90
130
170
230
IO = −500 µA
IO = −1 mA
Temperature
extremes
mV
TA = 25°C
88
Temperature
extremes
TA = 25°C
13
7.5
17
Source
VO = V+/2
Temperature
extremes
IOUT
mA
µs
TA = 25°C
14.5
8.5
19
Sink
VO = V+/2
Temperature
extremes
Overdrive = 10 mV
18
Propagation delay
(high to low)
TA = 25°C
7.7
13.5
16
Overdrive = 100
mV
Temperature
extremes
Overdrive = 10 mV
30
12
µs
Propagation delay
(low to high)
TA = 25°C
15
20
Overdrive = 100
mV
Temperature
extremes
Overdrive = 10 mV
CL = 30 pF, RL = 1 MΩ
100
100
115
95
trise
Rise time
Fall time
ns
ns
Overdrive = 100 mV
CL = 30 pF, RL = 1 MΩ
Overdrive = 10 mV
CL = 30 pF, RL = 1 MΩ
tfall
Overdrive = 100 mV
CL = 30 pF, RL = 1 MΩ
8
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6.8 Typical Characteristics
At TJ = 25°C unless otherwise specified.
900
800
900
V
CM
= 0.8V
+
V
= 1.8V
850
800
750
700
85°C
700
85°C
25°C
600
25°C
500
-40°C
400
650
600
550
500
450
-40°C
300
200
100
0
0
1
2
3
4
5
6
0
0.5
1
1.5
2
SUPPLY VOLTAGE (V)
COMMON MODE INPUT (V)
Figure 1. Supply Current vs Supply Voltage
Figure 2. Supply Current vs Common-Mode Input
900
+
900
+
V
= 2.7V
V = 5V
850
800
750
800
700
600
500
85°C
700
650
600
550
500
450
85°C
25°C
25°C
-40°C
3
-40°C
1
0
0.5
1.5
2
2.5
3
1
2
4
5
6
0
COMMON MODE INPUT VOLTAGE (V)
COMMON MODE INPUT (V)
Figure 4. Supply Current vs Common-Mode Input
Figure 3. Supply Current vs Common-Mode Input
30
30
25
25
-40°C
-40°C
20
20
25°C
25°C
15
15
85°C
85°C
10
5
10
5
0
0
1
2
3
4
5
6
1
2
3
4
5
6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 5. Short-Circuit Sinking Current vs Supply Voltage
Figure 6. Short-Circuit Sourcing Current vs Supply Voltage
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Typical Characteristics (continued)
At TJ = 25°C unless otherwise specified.
0.6
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 1.8V
CC
0.5
0.4
0.3
0.2
0.1
0
85°C
V
= 2.7V
CC
25°C
V
= 5V
CC
-40°C
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SINK CURRENT (mA)
SINK CURRENT (mA)
Figure 7. Output Voltage Low vs Sink Current
Figure 8. Output Voltage Low vs Sink Current
0.6
0.6
85°C
V
= 1.8V
CC
V
= 2.7V
CC
0.5
0.4
0.3
0.2
0.1
0
0.5
25°C
0.4
-40°C
V
= 5V
CC
0.3
0.2
0.1
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
Figure 9. Output Voltage High vs Source Current
Figure 10. Output Voltage High vs Source Current
25
13
V
V
= 20 mV
OD
CM
V
V
= 20 mV
OD
CM
+
+
= V /2
= V /2
12
85°C
85°C
25°C
20
15
10
11
10
9
25°C
-40°C
-40°C
8
7
6
5
1
2
3
4
5
6
1
2
3
4
5
6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 12. Propagation Delay vs Supply Voltage
Figure 11. Propagation Delay vs Supply Voltage
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Typical Characteristics (continued)
At TJ = 25°C unless otherwise specified.
15
14
13
12
11
10
9
18
+
+
V
V
= 1.8V
= 0.5V
V
T
= 1.8V
= 25°C
CM
A
13
85°C
25°C
-40°C
t
PD L-H
8
3
8
7
6
t
PD H-L
5
1
10
100
1000
0
100
200
300
400
500
OVERDRIVE (mV)
OVERDRIVE (mV)
Figure 14. Propagation Delay vs Overdrive
Figure 13. Propagation Delay vs Overdrive
14
18
+
+
V
V
= 1.8V
= 1.3V
V
V
= 2.7V
= 0.5V
CM
13
12
11
10
9
CM
16
14
12
10
85°C
25°C
85°C
25°C
8
7
-40°C
25°C
-40°C
6
8
6
5
4
0
100
200
300
400
500
0
100
200
300
400
500
OVERDRIVE (mV)
OVERDRIVE (mV)
Figure 15. Propagation Delay vs Overdrive
Figure 16. Propagation Delay vs Overdrive
30
34
V+ = 5V
+
V
V
= 5.0V
= 4.5V
28
26
24
22
20
18
16
14
12
10
V
CM
= 2.5V
CM
29
24
19
14
85°C
t
PD L-H
25°C
-40°C
85°C
9
4
t
PD H-L
10
100
1000
10000
0
100
200
300
400
500
OVERDRIVE (mV)
OVERDRIVE (mV)
Figure 17. Propagation Delay vs Overdrive
Figure 18. Propagation Delay vs Overdrive
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Typical Characteristics (continued)
At TJ = 25°C unless otherwise specified.
12
10
34
+
V
V
= 5V
= 0.5V
32
CM
30
28
26
24
22
20
18
16
14
12
10
t
PDL-H
+
V
= 5V
85°C
25°C
-40°C
8
6
4
t
PDH-L
t
PDL-H
-40°C
+
t
PDH-L
V
= 1.8V
1
10
100
1000
10000
0
100
200
300
400
500
OVERDRIVE (mV)
RESISTIVE LOAD (kW)
Figure 19. Propagation Delay vs Overdrive
Figure 20. Propagation Delay vs Resistive Load
80
20
+
V
= 2.7V
+
V
= 1.8V
40
0
-20
0
-40
-80
-40
-60
0.3
0.6
0.9
(V)
1.2
1.5
1.8
0
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
(V)
V
CM
V
CM
Figure 21. IBIAS vs VCM
Figure 22. IBIAS vs VCM
12
11.5
11
800
400
+
V
V
= 20 mV
OD
+
V
= 5V
= 1.8V
85°C
10.5
0
-400
10
9.5
9
25°C
-40°C
8.5
8
-800
7.5
-1200
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
0
1
2
3
4
5
COMMON MODE VOLTAGE (V)
V
CM
(V)
Figure 24. Propagation Delay vs Common-Mode Input
Figure 23. IBIAS vs VCM
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Typical Characteristics (continued)
At TJ = 25°C unless otherwise specified.
15
13
12
11
V
= 20 mV
V
V
= 20 mV
OD
+
OD
+
14.5
14
V
= 2.7V
85°C
= 5V
13.5
13
85°C
25°C
12.5
12
25°C
-40°C
11.5
11
10
9
-40°C
10.5
10
0
1
2
3
4
5
0
0.5
1
1.5
2
2.5
3
COMMON MODE INPUT VOLTAGE (V)
COMMON MODE VOLTAGE (V)
Figure 26. Propagation Delay vs Common-Mode Input
Figure 25. Propagation Delay vs Common-Mode Input
1400
+
24
85°C
V
= 5V
1200
23
22
85°C
25°C
1000
800
600
400
25°C
21
20
19
-40°C
-40°C
18
17
200
0
V
V
= 20 mV
OD
+
= 5V
0
1
2
3
4
5
0
2
4
1
3
5
COMMON MODE VOLTAGE (V)
COMMON MODE VOLTAGE (V)
Figure 27. Propagation Delay vs Common-Mode Input
Figure 28. Offset Voltage vs Common-Mode Input
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7 Detailed Description
7.1 Overview
The LPV7215 is a single-channel comparator with a push-pull output stage. This comparator is optimized for low-
power consumption and single-supply operation with greater than rail-to-rail input operation. The push-pull output
of the LPV7215 supports rail-to-rail output swing and interfaces with TTL/CMOS logic.
7.2 Functional Block Diagram
V
CC
+
-
INVERTERS
OUTPUT
I
I
NP
NN
+
-
GND
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7.3 Feature Description
Low supply current and fast propagation delay distinguish the LPV7215 from other low-power comparators.
7.3.1 Input Stage
The LPV7215 has rail-to-rail input common-mode voltage range. It can operate at any differential input voltage
within this limit as long as the differential voltage is greater than zero. A differential input of zero volts may result
in oscillation.
The differential input stage of the comparator is a pair of PMOS and NMOS transistors, therefore, no current
flows into the device. The input bias current measured is the leakage current in the MOS transistors and input
protection diodes. This low bias current allows the comparator to interface with a variety of circuitry and devices
with minimal concern about matching the input resistances.
The input to the comparator is protected from excessive voltage by internal ESD diodes connected to both supply
rails. This protects the circuit from both ESD events, as well as signals that significantly exceed the supply
voltages. When this occurs the ESD protection diodes becomes forward-biased and draws current into these
structures, resulting in no input current to the terminals of the comparator. Until this occurs, there is essentially
no input current to the diodes. As a result, placing a large resistor in series with an input that may be exposed to
large voltages, limits the input current but have no other noticeable effect.
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Feature Description (continued)
7.3.2 Output Stage
The LPV7215 has a MOS push-pull rail-to-rail output stage. The push-pull transistor configuration of the output
keeps the total system power consumption to a minimum. The only current consumed by the LPV7215 is the less
than 1-µA supply current and the current going directly into the load. No power is wasted through the pullup
resistor when the output is low. The output stage is specifically designed with dead time between the time when
one transistor is turned off and the other is turned on (break-before-make) to minimize shoot through currents.
The internal logic controls the break-before-make timing of the output transistors. The break-before-make delay
varies with temperature and power condition.
7.3.3 Output Current
Even though the LPV7215 uses less than 1-µA supply current, the outputs are able to drive very large currents.
The LPV7215 can source up to 17 mA and can sink up to 19 mA, when operated at 5-V supply. This large
current handling capability allows driving heavy loads directly.
7.3.4 Response Time
Depending upon the amount of overdrive, the propagation delay is typically 6 to 30 µs. The curves showing
propagation delay vs overdrive in the Typical Characteristics section shows the delay time when the input is
preset with 100 mV across the inputs and then is driven the other way by 10 mV to 500 mV.
The output signal can show a step during switching depending on the load. A fast RC time constant due to both
small capacitive and resistive loads shows a significant step in the output signal. A slow RC time constant due to
either a large resistive or capacitive load has a clipped corner on the output signal. The step is observed more
prominently during a falling transition from high to low.
The plot in Figure 29 shows the output for single 5-V supply with a 100-kΩ resistor. The step is at 1.3 V.
5
4
3
2
1
0
TIME (2 ms/DIV)
Figure 29. Output Signal Without Capacitive Load
The plot in Figure 30 shows the output signal when a 20-pF capacitor is added as a load. The step is at about
2.5 V.
5
4
3
2
1
0
TIME (2 ms/DIV)
Figure 30. Output Signal With 20-pF Load
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7.4 Device Functional Modes
7.4.1 Capacitive and Resistive Loads
The propagation delay is not affected by capacitive loads at the output of the LPV7215. However, resistive loads
slightly affect the propagation delay on the falling edge by a reduction of almost 2 µs depending on the load
resistance value.
7.4.2 Noise
Most comparators have rather low gain. This allows the output to spend time between high and low when the
input signal changes slowly. The result is that the output may oscillate between high and low when the
differential input is near zero. The exceptionally high gain of this comparator, 120 dB, eliminates this problem.
Less than 1 µV of change on the input drives the output from one rail to the other rail. If the input signal is noisy,
the output cannot ignore the noise unless some hysteresis is provided by positive feedback (see Hysteresis).
7.4.3 Hysteresis
To improve propagation delay when low overdrive is needed, hysteresis can be added.
7.4.4 Inverting Comparator With Hysteresis
The inverting comparator with hysteresis requires a three resistor network that is referenced to the supply voltage
V+ of the comparator as shown in Figure 31. When VIN at the inverting input is less than VA, the voltage at the
noninverting node of the comparator (VIN < VA), the output voltage is high (for simplicity assume VO switches as
high as V+). The three network resistors can be represented as R1//R3 in series with R2.
The lower input trip voltage VA1 is defined as Equation 1.
VA1 = VCCR2 / ((R1//R3) + R2)
(1)
When VIN is greater than VA, the output voltage is low or very close to ground. In this case the three network
resistors can be presented as R2//R3 in series with R1.
The upper trip voltage VA2 is defined as Equation 2.
VA2 = VCC (R2//R3) / ((R1+ (R2//R3)
(2)
The total hysteresis provided by the network is defined as ΔVA = VA1 – VA2, as shown in Equation 3.
+VCCR1R2
DVA =
R1R2 + R1R3 + R2R3
(3)
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Device Functional Modes (continued)
Figure 31. Inverting Comparator With Hysteresis
7.4.5 Noninverting Comparator With Hysteresis
A noninverting comparator with hysteresis requires a two resistor network, and a voltage reference (VREF) at the
inverting input. When VIN is low, the output is also low. For the output to switch from low to high, VIN must rise up
to VIN1 where VIN1 is calculated by Equation 4.
VREF(R1 + R2)
=
R2
V
IN1
(4)
As soon as VO switches to VCC, VA steps to a value greater than VREF, which is given by Equation 5.
(VCC - V ) R1
IN1
VA = V +
IN
R1 + R2
(5)
To make the comparator switch back to its low state, VIN must equal VREF before VA again equals VREF. VIN2 can
be calculated by Equation 6.
VREF(R1 + R2) - VCC R1
=
R2
V
IN2
(6)
(7)
The hysteresis of this circuit is the difference between VIN1 and VIN2, as shown in Equation 7.
ΔVIN = VCCR1/R2
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Device Functional Modes (continued)
V
CC
V
REF
-
V
A
V
O
V
IN
+
R
R
1
L
R
2
Figure 32. Noninverting Comparator With Hysteresis
Figure 33. Noninverting Comparator With Hysteresis
7.4.6 Zero Crossing Detector
In a zero crossing detector circuit, the inverting input is connected to ground and the noninverting input is
connected to a 100-mVPP AC signal. As the signal at the noninverting input crosses 0 V, the comparator’s output
changes state.
Figure 34. Zero Crossing Detector
To improve switching times and to center the input threshold to ground a small amount of positive feedback is
added to the circuit. The voltage divider, R4 and R5, establishes a reference voltage, V1, at the positive input. By
making the series resistance, R1 plus R2 equal to R5, the switching condition, V1 = V2, is satisfied when VIN = 0.
The positive feedback resistor, R6, is made very large with respect to R5 (R6 = 2000 R5). The resultant hysteresis
established by this network is very small (ΔV1 < 10 mV) but it is sufficient to insure rapid output voltage
transitions. Diode D1 is used to insure that the inverting input terminal of the comparator never goes below
approximately −100 mV. As the input terminal goes negative, D1 will forward bias, clamping the node between R1
and R2 to approximately −700 mV. This sets up a voltage divider with R2 and R3 preventing V2 from going below
ground. The maximum negative input overdrive is limited by the current handling ability of D1.
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Device Functional Modes (continued)
V
CC
R
3
R
4
R
2
R
1
V
-
IN
V
2
V
O
V
1
+
D
1
R
6
R
5
Figure 35. Zero Crossing Detector With Positive Feedback
7.4.7 Threshold Detector
Instead of tying the inverting input to 0 V, the inverting input can be tied to a reference voltage. As the input on
the noninverting input passes the VREF threshold, the comparator’s output changes state. It is important to use a
stable reference voltage to ensure a consistent switching point.
Figure 36. Threshold Detector
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LPV7215 is an ultra-low-power comparator with a typical power supply current of 580 nA. It has the best-in-
class power supply current versus propagation delay performance available among TI's low-power comparators.
The propagation delay is as low as 4.5 µs with 100-mV overdrive at 1.8-V supply.
8.2 Typical Applications
8.2.1 Square Wave Generator
R4
C1
-
VC
VO
+
R1
R3
VA
V+
V+
R2
0
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Figure 37. Square Wave Generator Schematic
8.2.1.1 Design Requirements
A typical application for a comparator is as a square wave oscillator. The circuit in Figure 38 generates a square
wave whose period is set by the RC time constant of the capacitor C1 and resistor R4. The maximum frequency
is limited by the large signal propagation delay of the comparator and by the capacitive loading at the output,
which limits the output slew rate.
8.2.1.2 Detailed Design Procedure
Figure 38. Square Wave Oscillator
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Typical Applications (continued)
Consider the output of Figure 38 to be high to analyze the circuit. That implies that the inverted input (VC) is
lower than the noninverting input (VA). This causes the C1 to be charged through R4, and the voltage VC
increases until it is equal to the noninverting input. The value of VA at this point is in Equation 8.
V
CC ´R2
VA1 =
R2 + R1 P R3
(8)
If R1 = R2 = R3 then VA1 = 2 VCC/3
At this point the comparator switches pulling down the output to the negative rail. The value of VA at this point, as
shown in Equation 9:
VCC(R2 P R3)
=
R1 + (R2 P R3)
VA2
(9)
If R1 = R2 = R3 then VA2 = VCC/3
The capacitor C1 now discharges through R4, and the voltage VC decreases until it is equal to VA2, at which point
the comparator switches again, bringing it back to the initial stage. The time period is equal to twice the time it
takes to discharge C1 from 2 VCC/3 to VCC/3, which is given by R4C1 × ln2. Hence the formula for the frequency is
given by Equation 10:
F = 1/(2 × R4 × C1 × ln2)
(10)
8.2.1.3 Application Curves
Figure 39 shows the simulated results of an oscillator using the following values:
1. R1 = R2 = R3 = R4 = 100 kΩ
2. C1 = 100 pF, CL = 20 pF
3. V+ = 5 V, V– = GND
4. CSTRAY (not shown) from Va to GND = 10 pF
6
VOUT
5
V
a
4
3
2
1
V
c
0
-1
0
10
20
30
40
50
TIME (µs)
Figure 39. Square Wave Oscillator Output Waveform
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Typical Applications (continued)
8.2.2 Window Detector
A window detector monitors the input signal to determine if it falls between two voltage levels.
The comparator outputs A and B are high only when VREF1 < VIN < VREF2 or within the window. These are defined
as:
VREF1 = R3 / (R1+ R2 + R3) × V+
(11)
(12)
VREF2 = (R2+ R3) / (R1 + R2 + R3) × V+
Others names for window detectors are: threshold detector, level detectors, and amplitude trigger or detector.
V+
R1
VREF2
+
-
OUTPUT A
OUTPUT B
A
B
VIN
R2
+
VREF1
-
R3
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Figure 40. Window Detector
OUTPUT B
V
IN
+
V
V
REF2
REF1
V
OUTPUT A
BOTH OUTPUTS
ARE HIGH
Figure 41. Window Detector Output Signal
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Typical Applications (continued)
8.2.3 Crystal Oscillator
A simple crystal oscillator using the LPV7215 is shown in Figure 42. Resistors R1 and R2 set the bias point at the
comparator’s noninverting input. Resistors, R3 and R4 and capacitor C1 set the inverting input node at an
appropriate DC average level based on the output. The crystal’s path provides resonant positive feedback and
stable oscillation occurs. The output duty cycle for this circuit is roughly 50%, but it is affected by resistor
tolerances and to a lesser extent by the comparator offset.
Copyright © 2016, Texas Instruments Incorporated
Figure 42. Crystal Oscillator
8.2.4 IR Receiver
The LPV7215 can also be used as an infrared receiver. The infrared photo diode creates a current relative to the
amount of infrared light present. The current creates a voltage across RD. When this voltage level crosses the
voltage applied by the voltage divider to the inverting input, the output transitions.
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Figure 43. IR Receiver
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9 Power Supply Recommendations
Comparators are very sensitive to input noise. To minimize supply noise, power supplies must be capacitively
decoupled by a 0.01-µF ceramic capacitor in parallel with a 10-µF electrolytic capacitor.
10 Layout
10.1 Layout Guidelines
Proper grounding and the use of a ground plane help ensure the specified performance of the LPV7215.
Minimizing trace lengths, reducing unwanted parasitic capacitance and using surface-mount components also
helps.
10.2 Layout Example
Figure 44. LPV7215 Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti
DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm
TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm
11.1.2 Documentation Support
11.1.2.1 Related Documentation
For related documentation, see the following
AN-74 - A Quad of Independently Functioning Comparators (SNOA654).
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LPV7215MF/NOPB
LPV7215MFX/NOPB
LPV7215MG/NOPB
LPV7215MGX/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
5
5
5
5
1000 RoHS & Green
3000 RoHS & Green
1000 RoHS & Green
3000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
C30A
C30A
C37
SN
SN
SN
SC70
C37
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LPV7215MF/NOPB
LPV7215MFX/NOPB
LPV7215MG/NOPB
LPV7215MGX/NOPB
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
5
5
5
5
1000
3000
1000
3000
178.0
178.0
178.0
178.0
8.4
8.4
8.4
8.4
3.2
3.2
3.2
3.2
1.4
1.4
1.2
1.2
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
2.25
2.25
2.45
2.45
SC70
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LPV7215MF/NOPB
LPV7215MFX/NOPB
LPV7215MG/NOPB
LPV7215MGX/NOPB
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
5
5
5
5
1000
3000
1000
3000
208.0
208.0
208.0
208.0
191.0
191.0
191.0
191.0
35.0
35.0
35.0
35.0
SC70
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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