LQM2HPN1R0MJ0_技术文档

bq24152

www.ti.com ...................................................................................................................................................................................................... SLUS847–JUNE 2008

Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and

USB-OTG Support

1

FEATURES

2

•

Charge Faster than Linear Chargers

–

Output Voltage for VBUS: 5.05 V

•

High-Accuracy Voltage and Current Regulation

•

1.976 x 1.924mm 20-Pin WCSP Package

–

Input Current Regulation Accuracy: ±5%

(100 mA and 500 mA)

APPLICATIONS

•

Mobile and Smart Phones

MP3 Players

Handheld Devices

Charge Voltage Regulation Accuracy:

±0.5% (25°C), ±1% (0°C-125°C)

Charge Current Regulation Accuracy: ±5%

•

High-Efficiency Mini-USB/AC Battery Charger

for Single-Cell Li-Ion and Li-Polymer Battery

Packs

DESCRIPTION

The bq24152 is a compact, flexible, high-efficiency,

USB-friendly switch-mode charge management

device for single-cell Li-ion and Li-polymer batteries

used in a wide range of portable applications. The

charge parameters can be programmed through an

I²C interface. The bq24152 integrates a synchronous

PWM controller, power MOSFETs, input current

•

20-V Absolute Maximum Input Voltage Rating

6-V Maximum Operating Input Voltage

Built-In Input Current Sensing and Limiting

Integrated Power FETs for Up To 1.25-A

Charge Rate

sensing,

high-accuracy

current

and

voltage

•

Programmable Charge Parameters through

I²C™ Interface (up to 3.4 Mbps):

regulation, and charge termination, into a small

WCSP package.

–

Input Current

The bq24152 charges the battery in three phases:

conditioning, constant current and constant voltage.

The input current is automatically limited to the value

set by the host. Charge is terminated based on

user-selectable minimum current level. A safety timer

with reset control provides a safety backup for I²C

interface. During normal operation, bq24152

automatically restarts the charge cycle if the battery

voltage falls below an internal threshold and

automatically enters sleep mode or high impedance

mode when the input supply is removed. The charge

status is reported to the host using the I²C interface.

Fast-Charge/Termination Current

Charge Voltage (3.5 V to 4.44 V)

Safety Timer

Termination Enable

•

Synchronous Fixed-Frequency PWM

Controller Operating at 3 MHz with 0% to

99.5% Duty Cycle

Automatic High Impedance Mode for Low

Power Consumption

•

Safety Timer with Reset Control

Typical Application Circuit

Reverse Leakage Protection Prevents Battery

Drainage

L

1.0 mH

O

R

SNS

V

BUS

C

VBUS

SW

C

O

IN

C

U1

•

Thermal Regulation and Protection

Input/Output Overvoltage Protection

Status Output for Charging and Faults

USB Friendly Boot-Up Sequence

Automatic Charging

BOOT

10nF

10

mF

1 mF

bq24152

PACK+

+

PMID

BOOT

PGND

C

IN

0.1 mF

VAUX

4.7 mF

CSIN

10 kW

2

I

C BUS

PACK-

10 kW

CSOUT

SCL

SDA

STAT

SDA

STAT

OTG

AUXPWR

VREF

C

AUXPWR

OTG

C

1

mF

VREF

10 kW

1

mF

HOST

Power up System without Battery

Boost Mode Operation for USB OTG:

–

Input Voltage Range (from Battery): 2.5 V to

4.5 V

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

I2C is a trademark of Philips Electronics.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

bq24152

SLUS847–JUNE 2008 ...................................................................................................................................................................................................... www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION CONTINUED

During the charging process, the bq24152 monitors its junction temperature (T_J) and reduces the charge current

once T_Jincreases to approximately 125°C. To support USB OTG device, bq24152 provides VBUS

(approximately 5.05V) by boosting the battery voltage. The bq24152 is available in 20-pin WCSP package.

WCSP PACKAGE

(Top View)

A1

A2

A3

A4

VBUS

BOOT

SCL

B1

B2

B3

B4

PMID

SDA

C1

SW

C2

SW

C3

SW

C4

STAT

D1

D2

D3

D4

PGND

OTG

E1

E2

AUX

PWR

E3

E4

CSOUT

CSIN

VREF

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

CSOUT

VBUS

PMID

SW

NO.

Battery voltage and current sense input. Bypass it with a ceramic capacitor (minimum 0.1 µF) to

PGND if there are long inductive leads to battery.

E4

I

A1, A2

B1, B2, B3

C1, C2, C3

A3

I

Charger input voltage. Bypass it with a 1-µF ceramic capacitor from VBUS to PGND.

Connection point between reverse blocking MOSFET and high-side switching MOSFET. Bypass it

with a minimum of 3.3-µF capacitor from PMID to PGND.

O

Internal switch to output inductor connection.

Boot-strapped capacitor for the high-side MOSFET gate driver. Connect a 10-nF ceramic capacitor

(voltage rating above 10 V) from BOOT pin to SW pin.

BOOT

PGND

CSIN

D1, D2, D3

E1

Power ground

Charge current-sense input. Battery current is sensed via the voltage drop across an external sense

resistor. A 0.1-µF ceramic capacitor to PGND is required.

I

I²C interface clock. Open drain output, connect a 10-kΩ pullup resistor

I²C interface data. Open drain output, connect a 10-kΩ pullup resistor

SCL

SDA

A4

B4

I

I/O

Charge status pin. Pull low when charge in progress. Open drain for other conditions. During faults, a

128µS pulse is sent out. STAT pin can be disabled by the EN_STAT bit in control register. STAT can

be used to drive a LED or communicate with a host processor.

STAT

C4

O

Internal bias regulator voltage. Connect a 1-µF ceramic capacitor from this output to PGND. External

load on VREF is not allowed.

VREF

E3

E2

O

I

Auxiliary power supply, connected to the battery pack to provide power in high-impedance mode.

Bypass it with a 1-µF ceramic capacitor from this pin to PGND.

AUXPWR

Boost mode enable control or input current limiting selection pin. When OTG is in active status,

bq24152 is forced to operate in boost mode. It has higher priority over I²C control and can be disabled

through control register. The logic voltage level at OTG active status can also be controlled. At POR,

the OTG pin is default to be used as the input current limiting selection pin. When OTG = High, Iin –

limit = 500 mA and when OTG = Low, Iin – limit = 100 mA, see the Control Register for details.

OTG

D4

I

2

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bq24152

www.ti.com ...................................................................................................................................................................................................... SLUS847–JUNE 2008

ORDERING INFORMATION⁽¹⁾

Part NO.

bq24152YFFR

bq24152YFFT

MARKING

bq24152

MEDIUM

QUANTITY

3000

Tape and Reel

250

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

DISSIPATION RATINGS⁽¹⁾

T

_A≤ 25°C

DERATING FACTOR

T_A> 25°C

PACKAGE

R_θJA

R_θJC

POWER RATING

(1)

WSCP-20

185°C/W⁽²⁾

1.57°C/W

0.54 W

0.0054 W/°C

(1) Maximum power dissipation is a function of T_J(max), Rθ_JAand T_A. The maximum allowable power dissipation at any allowable ambient

temperature is P_D= [T_J(max)-T_A] / Rθ_JA

.

(2) For PCB board with only top trace layer. For PCB board with four layers (top trace layer, buried ground layer, buried signal layer and

bottom layer), Rθ_JAdrops to 75.96°C/W

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

Supply voltage range (with

respect to PGND)

V_SS

V_I

VBUS

–0.3 to 20

V

Input voltage range (with

respect to and PGND)

SCL, SDA, OTG, CSIN, CSOUT, AUXPWR

–0.3 to 7

V

PMID, STAT

VREF

–0.3 to 20

6.5

V

Output voltage range (with

respect to and PGND)

V_O

SW, BOOT

–0.7 to 20

±7

V

Voltage difference between CSIN and CSOUT inputs (V_(CSIN)-V_(CSOUT)

)

V

Output sink

STAT

SW

10

mA

A

I_O

Output current (average)

1.25

T_A

T_J

Operating free-air temperature range

Junction temperature

–40 to 85

–40 to 150

–65 to 150

800

°C

V

T_stg

Storage temperature

Human body model at VBUS, PMID, STAT⁽²⁾⁽³⁾

ESD

Rating

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage

values are with respect to the network ground terminal unless otherwise noted.

(2) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.

(3) Other pins pass 2 kV for human body model.

All voltages are with respect to PGND if not specified. Currents are positive into, negative out of the specified terminal.

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RECOMMENDED OPERATING CONDITIONS

MIN

4

NOM

MAX

6⁽¹⁾

UNIT

V

V_BUS

T_J

Supply voltage, VBUS

Operating junction temperature range

0

+125

°C

(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW pins. A tight

layout minimizes switching noise.

ELECTRICAL CHARACTERISTICS

Circuit of Figure 1, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (charger mode operation), T_J= 0°C to 125°C, T_J= 25°C for

typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

INPUT CURRENTS

VBUS > VBUS(min), PWM switching

10

mA

5

VBUS > VBUS(min), PWM NOT switching

0°C < T_J< 85°C, VBUS = 5 V, HZ_MODE = 1,

V_(AUXPWR)> V_(LOWV), SCL, SDA, OTG = 0 V or

1.8 V

20

µA

I_(VBUS)

VBUS supply current control

0°C < T_J< 85°C, VBUS = 5 V, HZ_MODE = 1,

V_(AUXPWR)< V_(LOWV), 32 S mode, SCL, SDA, OTG

= 0 V or 1.8 V

35

5

µA

Leakage current from battery to

VBUS pin

0°C < T_J< 85°C, V_(AUXPWR)= 4.2 V, High

impedance mode

I_lkg

Battery discharge current in High 0°C < T_J< 85°C, V_(AUXPWR)= 4.2 V, High

Impedance mode, (CSIN,

impedance mode

20

CSOUT, AUXPWR, SW pins)

SCL, SDA, OTG = 0 V or 1.8 V

VOLTAGE REGULATION

V_(OREG)Output charge voltage

Operating in voltage regulation, programmable

T_A= 25°C

3.5

4.44

V

–0.5%

0.5%

Voltage regulation accuracy

CURRENT REGULATION (FAST CHARGE)

±1%

V

_(LOWV)≤ V_(AUXPWR)< V_(OREG), VBUS > V_(SLP)

,

550

I_O(CHARGE)

Output charge current

1250

mA

R_(SNS)= 68 mΩ Programmable

20 mV ≤ V_(IREG)≤ 40 mV

40 mV < V_(IREG)

Regulation accuracy for charge

current across R_(SNS)

V_(IREG)= I_O(CHARGE)× R_(SNS)

–5%

–3%

5%

3%

WEAK BATTERY DETECTION

V_(LOWV)Weak battery voltage threshold

Programmable

3.4

3.7

5%

V

Weak battery voltage accuracy

Hysteresis for V_(LOWV)

–5%

Battery voltage falling

100

30

mV

ms

Deglitch time for weak battery

threshold

Rising voltage, 2 mV overdrive, t_RISE= 100 ns

OTG PIN LOGIC LEVEL

V_IL

V_IH

Input low threshold level

Input high threshold level

0.4

V

1.3

50

CHARGE TERMINATION DETECTION

Termination charge current

V_(AUXPWR)> V_(OREG)– V_(RCH)

VBUS > V_(SLP), R_(SNS)= 68 mΩ Programmable

,

mA

ms

I_(TERM)

400

Deglitch time for charge

termination

Both rising and falling, 2 mV overdrive, t_RISE, t_FALL

= 100 ns

30

Voltage regulation accuracy for

termination current across R_(SNS)

V_{(IREG_TERM)}= I_O(TERM)× R_(SNS)

3 mV ≤ V_{(IREG_TERM)}< 20 mV

20 mV ≤ V_{(IREG_TERM)}≤ 40 mV

–25%

–5%

25%

5%

INPUT POWER SOURCE DETECTION

Input voltage lower limit

Input power source detection

3.6

3.8

30

4

V

Deglitch time for VBUS rising

above V_IN(min)

ms

V_IN(min)

Rising voltage, 2 mV overdrive, t_RISE= 100 ns

Hysteresis for V_IN(min)

Input voltage rising

100

200

mV

S

t_INT

Detection Interval

Input power source detection

2

4

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ELECTRICAL CHARACTERISTICS (continued)

Circuit of Figure 1, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (charger mode operation), T_J= 0°C to 125°C, T_J= 25°C for

typical values (unless otherwise noted)

PARAMETER

INPUT CURRENT LIMITING

TEST CONDITIONS

MIN

TYP

MAX UNIT

I_IN= 100 mA

I_IN= 500 mA

88

93

98

mA

I_IN

VREF BIAS REGULATOR

V_refInternal bias regulator voltage

Input current limiting threshold

USB charge mode

450

475

500

VBUS >V_IN(min) or V_(AUXPWR)> V_(BAT)min,

I(VREF) = 1 mA, C(VREF) = 1 µF

V

2

6.5

V_refoutput short current limit

30

mA

V

Voltage from BOOT pin to SW

During charge or boost operation

6.5

BATTERY RECHARGE THRESHOLD

V_(RCH)

Recharge threshold voltage

Below V_(OREG)

100

120

130

150

mV

ms

V_(AUXPWR)decreasing below threshold,

t_FALL= 100ns, 10 mV overdrive

Deglitch time

STAT OUTPUTS

Low-level output saturation

voltage, STAT

I_O= 10 mA, sink current

0.4

1

V

V_OL(STAT)

High-level leakage current for

STAT

Voltage on STAT pin is 5 V

µA

I²C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS

V_OL

V_IL

Output low threshold level

Input low threshold level

Input high threshold level

Input bias current

I_O= 10 mA, sink current

0.4

V

V_IH

1.2

V

I_(BIAS)

f_(SCL)

V_(pull-up)= 1.8 V, SDA and SCL

1

µA

MHz

SCL clock frequency

3.4

BATTERY DETECTION

Battery detection current before

Begins after termination detected,

V_(AUXPWR)≤ V_(OREG)

–0.45

262

mA

ms

(1)

charge done (sink current)

I_(DETECT)

Battery detection time

SLEEP COMPARATOR

Sleep-mode entry threshold,

V_BUS- V_AUXPWR

V_(SLP)

2.3 V ≤ V_(AUXPWR)≤ V_(OREG), V_BUSfalling

2.3 V ≤ V_(AUXPWR)≤ V_(OREG)

+0.0

40

+0.04

100

30

+0.1

160

V

Sleep-mode exit hysteresis

mV

ms

V_{(SLP_EXIT)}

Deglitch time for VBUS rising

above V_(SLP)+ V_{(SLP_EXIT)}

Rising voltage, 2-mV overdrive, t_RISE= 100ns

UNDERVOLTAGE LOCKOUT

UVLO

IC active threshold voltage

VBUS rising

3.05

120

3.3

3.55

V

UVLO_(HYS)

PWM

IC active hysteresis

VBUS falling from above UVLO

150

mV

Internal top reverse blocking

MOSFET on-resistance

I_IN(LIMIT)= 500 mA, Measured from VBUS to

PMID

180

120

250

200

Internal top N-channel Switching

MOSFET on-resistance

Measured from PMID to SW

Measured from SW to PGND

mΩ

Internal bottom N-channel

MOSFET on-resistance

150

3

f_(OSC)

Oscillator frequency

Frequency accuracy

Maximum duty cycle

Minimum duty cycle

Synchronous mode to

MHz

–10%

0

10%

D_(MAX)

D_(MIN)

99.5%

100

non-synchronous mode transition Low side MOSFET cycle by cycle current sensing

mA

current threshold⁽²⁾

(1) Negative charge current means the charge current flows from the battery to charger (discharging battery).

(2) Bottom N-channel MOSFET always turns on for ≈60 ns and then turns off if current is too low.

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ELECTRICAL CHARACTERISTICS (continued)

Circuit of Figure 1, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (charger mode operation), T_J= 0°C to 125°C, T_J= 25°C for

typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

BOOST MODE OPERATION FOR VBUS (OPA_MODE = 1, HZ_MODE = 0)

Boost output voltage (to pin

VBUS)

V_{(BUS_B)}

2.5 V < V_(AUXPWR)< 4.5 V, Open loop

5.05

±3%

V

Boost output voltage accuracy

Including line and load regulation

Maximum output current for

boost

I_(BO)

V_{(BUS_B)}= 5.05 V, 2.5 V < V_(AUXPWR)< 4.5 V

200

mA

A

Cycle by cycle current limit for

boost

I_(BLIMIT)

V_{(BUS_B)}= 5.05 V, 2.5 V < V_(AUXPWR)< 4.5 V

1

Overvoltage protection threshold Threshold over VBUS to turn off converter during

5.8

6

125

4.9

6.2

V

mV

V

for boost (VBUS pin)

boost

VBUS_(OVP)

VBUS_(OVP)hysteresis

VBUS falling from above VBUS_(OVP)

Maximum battery voltage for

boost (CSOUT pin)

V_(CSOUT)rising edge during boost

4.75

5.05

V_(BAT)MAX

V_(BAT)MIN

V_(BAT)MAX hysteresis

V_(CSOUT)falling from above VBATMAX

During boosting

200

2.5

2.9

mV

V

Minimum battery voltage for

boost (AUXPWR pin)

Before boost starts

3.05

V

Boost output resistance at

high-impedance mode (From

VBUS to PGND)

HZ_MODE = 1

165

kΩ

PROTECTION

Input VBUS OVP threshold

voltage

Threshold over VBUS to turn off converter during

charge

6.3

6.5

140

117

11

6.7

V

V_(OVP-IN)

V_{(OVP_IN)}hysteresis

VBUS falling from above V_{(OVP_IN)}

mV

V_(CSOUT)threshold over V_(OREG)to turn off charger

during charge

Battery OVP threshold voltage

V_(OVP)hysteresis

110

121

%V_(ORE

V_(OVP)

G)

Lower limit for V_(CSOUT)falling from above V_(OVP)

Charge mode operation

Cycle-by-cycle current limit for

charge

I_(LIMIT)

1.5

1.9

2.3

3

A

Short-circuit voltage threshold

V_(SHORT)hysteresis

V_(AUXPWR)falling

2

100

10

2.1

V

V_(SHORT)

V_(AUXPWR)rising from below V_(SHORT)

mV

mA

I_(SHORT)

Short-circuit current

V_(AUXPWR)≤ V_(SHORT)

5

15

T_(SHTDWN)

Thermal trip

165

10

Thermal hysteresis

°C

s

T_(CF)

Thermal regulation threshold⁽³⁾

Charge current begins to reduce

32 Second mode

120

Time constant for the 32 second

timer

T_(32S)

12

32

(3) Verified by design

6

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TYPICAL APPLICATION CIRCUITS

VBUS = 5 V, I_{(IN_LIMIT)}= 500 mA, I_(CHARGE)= 750 mA, VBAT = 3.5 V to 4.44 V (adjustable), Safety Timer = 32

minutes or 32 seconds.

L

1.0 mH

R

SNS

O

V

BAT

V

BUS

VBUS

SW

C

O

IN

68 mW

C

U1

BOOT

10 mF

1 mF

bq24152

10 nF

PACK +

BOOT

PGND

PMID

4.7 mF

C

IN

2

C

CSIN

+

VAUX

10 kW

0.1 mF

CSIN

CSOUT

AUXPWR

VREF

I C BUS

10 kW

PACK -

10 kW

SCL

SDA

STAT

SDA

C

AUXPWR

STAT

OTG

1 mF

C

VREF

10 kW

1 mF

HOST

Figure 1. I²C Controlled 1-Cell Charger Application Circuit

VBUS = 5 V, I_{(IN_LIMIT)}= 500 mA, V_OUT= 3.5 V to 4.44 V (adjustable), Safety Timer = 32 minutes or 32 seconds.

LO 1.0 mH

R

SNS

V

OUT

V

BUS

Host-

Controlled

Switch

VBUS

PMID

SW

C

O

IN

68 mW

0.1 mF

C

U1

bq24152

BOOT

10 mF

1 mF

10nF

BOOT

PGND

C

IN

4.7 mF

C

CSIN

V

SYS

VAUX

10 kW

CSIN

PACK +

2

I C BUS

10 kW

+

10 kW

CSOUT

SCL

SDA

STAT

SDA

AUXPWR

VREF

C

AUXPWR

STAT

C

PACK-

CSOUT

0.1 mF

OTG

C

1 mF

VREF

10 kW

1 mF

HOST

Figure 2. I²C Controlled 1-Cell Pre-Regulator Application

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TYPICAL CHARACTERISTICS

Using circuit shown in Figure 1, T_A= 25°C, unless otherwise specified.

ADAPTER INSERTION

BATTERY INSERTION/REMOVAL

VBAT

2 V/div

VBUS

2 V/div

Vbus =5 V, Iin_limit = 500 mA,

32S Mode

VSW

5 V/div

Vbus = 0–5 V, Vbat = 3.5 V Charge mode

I_BAT

0.5 A/div

1S/div

500 mS/div

Figure 3.

Figure 4.

PWM CHARGING WAVEFORMS

POOR SOURCE DETECTION

VBUS

2 V/div

VSW

2 V/div

VSW

5 V/div

IL

0.5 A/div

Vbus = 5 V @ 10 mA, Iin_limit = 100 mA,

Vbat = 3.2 V, Ichg = 550 mA

I_BUS

Vbus = 5 V, Vbat = 2.6 V, Voreg = 4.2 V, Ichg = 1250 mA

0.1 A/div

2 mS/div

100 nS/div

Figure 5.

Figure 6.

BATTERY DETECTION AT POWER UP

CYCLE BY CYCLE CURRENT LIMIT IN CHARGE MODE

V_BUS

5 V/div

VSW

2 V/div

V_IN= 0-5 V,

No Battery,

V_BAT

C_OUT= 100 mF,

1 V/div

R_LOAD= 5 kW

I_L

0.5 A/div

OTG

5 V/div

Vbus = 5 V, Vbat = 3.6 V Charge mode

operation

I_BAT

50 mA/div

20 mS/div

2 mS/div

Figure 7.

Figure 8.

8

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TYPICAL CHARACTERISTICS (continued)

INPUT CURRENT CONTROL

CHARGER EFFICIENCY

92

90

88

86

Vbus = 5 V, Iin_limit = 100/500 mA,

(OTG Control, 32 Minute Mode),

2

Iin_limit = 100 mA (I C Control, 32 Second Mode)

V_BUS= 5 V

Vbat = 4 V

Vbat = 3.6 V

OTG

5 V/div

32 Second

Mode

32 Minute

Mode

I_BUS

84

0.2 A/div

Vbat = 3 V

82

80

0.5 S/div

0

100 200 300 400 500 600 700 800 900 10001100 12001300

Charge Current - mA

Figure 9.

Figure 10.

BOOST WAVEFORM (PWM MODE)

BOOST WAVEFORM (PFM MODE)

VBUS 100 mV/div, 5.06 V Offset

VBUS 10 mV/div, 5.08 V Offset

VBAT 10 mV/div, 3.52 V Offset

VBAT 100 mV/div, 3.5 V Offset

VSW

2 V/div

VBAT = 3.5 V, VBUS = 5.06 V, IBUS = 42 mA

IL

0.2 A/div

VBAT = 3.5 V, VBUS = 5.07 V, IBUS = 215 mA

5 mS/div

100 nS/div

Figure 11.

Figure 12.

VBUS OVERLOAD WAVEFORMS (BOOST MODE)

LOAD STEP UP RESPONSE (BOOST MODE)

VBUS

100 mV/div,

5.06 V Offset

VBAT = 3.5 V, VBUS = 5.05 V, IBUS = 42 mA

VBUS

2 V/div

VBAT = 3.85 V, VBUS = 5.07 V, IBUS = 0-215 mA

VPMID

200 mV/div,

5.02 V Offset

VBAT

0.2 V/div,

3.8 V Offset

VSW

5 V/div

VSW

5 V/div

I_BUS

0.2 A/div

I_BAT

0.1 A/div

5 mS/div

100 mS/div

Figure 13.

Figure 14.

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TYPICAL CHARACTERISTICS (continued)

LOAD STEP DOWN RESPONSE (BOOST MODE)

CYCLE BY CYCLE CURRENT LIMITING IN BOOST MODE

VBUS

100 mV/div,

5.06 V Offset

Vbat = 3.6 V, Vbus = 4.11 V, Boost mode

overload operation

VBAT = 3.85 V, VBUS = 5.07 V, IBUS = 215 mA-0

VSW

V_BAT

2 V/div

0.2 A/div,

3.8 V Offset

VSW

5 V/div

IL

0.5 A/div

I_BAT

0.1 A/div

100 mS/div

200 nS/div

Figure 15.

Figure 16.

BOOST TO CHARGE MODE TRANSITION (OTG CONTROL)

BOOST EFFICIENCY

95

VBUS

0.5 V/div,

4.5 V Offset

VBAT = 4 V

VBAT = 3.6 V

90

OTG

2 V/div

Vbus = 4.5 V, (Charge Mode)/5.1 V (Boost Mode),

Iin_limit = 500 mA, Vbat = 3.4 V, 32S Mode.

85

VSW

5 V/div

VBAT = 2.5 V

80

IL

0.5 A/div

75

70

0.5 mS/div

0

50

100

150

200

Load Current at VBUS - mA

Figure 17.

Figure 18.

LINE REGULATION FOR BOOST

LOAD REGULATION FOR BOOST

5.1

IBUS = 100 mA

5.09

IBUS = 200 mA

5.08

5.07

5.06

5.05

5.04

VBAT = 3.6 V

5.06

5.05

VBAT = 4 V

5.04

IBUS = 50 mA

5.03

5.02

5.01

5

VBAT = 2.5 V

5.01

5

4.99

0

50

100

150

200

2.5

2.7

2.9

3.1

3.3

3.5

3.7

3.9

4.1

Load Current at VBUS - mA

VBAT - V

Figure 19.

Figure 20.

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FUNCTIONAL BLOCK DIAGRAM (Charge Mode)

PMID

bq24152

PMID

V_PMID

PMID

NMOS

VBUS

SW

V_BUS

Q2

CBC

Current

Limiting

Q3

Q1

I_LIMIT

NMOS

VOUT

PWM

Controller

VREF1

OSC

Charge

Pump

-

+

-

+

CSOUT

CSIN

-

I_{IN_}

V_OREG

LIMIT

-

+

-

T_CF

T_J

+

VCSIN

I_OCHARGE

-

PWM_CHG

VREF

V_BUS

V_UVLO

V_BUS

+

VBUS UVLO

VREF

BOOT

-

REFERNCES

& BIAS

+

Poor Input

VBUS OVP

V

IN(

MIN)

V_PMID

V_BUS

+

-

V_OVP

_IN

VBAT

CHARGE CONTRO,L

TIMER and DISPLAY

LOGIC

VREF

I_SHORT

T_J

+

Thermal

Shutdown

-

T_SHTDWN

AUXPWR

STAT

V_OUT

V_OVP

+

Battery OVP

Sleep

*

LINEAR _CHG

-

V_BAT

V_BUS

V_OREG-V_RCH

V_OUT

+

*

-

+

Recharge

*

-

OTG

Termination

V_OUT

V_CSIN

I_TERM

-

+

-

PGND

*

2

(I C Control)

Decoder

DAC

SCL

SDA

PGND

V_BAT

+

PWM Charge

Mode

*

-

V_SHORT

*

Signal Deglitched

Figure 21. Function Block Diagram of bq24152 in Charge Mode

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FUNCTIONAL BLOCK DIAGRAM (Boost Mode)

PMID

bq24152

PMID

V_PMID

PMID

NMOS

VBUS

SW

V_BUS

Q2

CBC

Current

Limiting

Q1

I_BLIMIT

PWM

Controller

VREF1

OSC

Charge

Pump

Q3

CSOUT

CSIN

NMOS

-

+

PFM Mode

75mA

+

V_{BUS_FB}

VREF

-

VREF

BOOT

-

I_BO

V_{BUS_FB}

REFERNCES

& BIAS

PWM_BOOST

V_BUS

+

VBUS OVP

VREF1

-

V_BUSOVP

V_PMID

T_J

+

Thermal

Shutdown

-

T_SHTDWN

VBAT

AUXPWR

STAT

CHARGE CONTROL,

TIMER and DISPLAY

LOGIC

Battery OVP

V_OUT

+

*

-

V_BATMAX

V_BAT

+

Low Battery

*

OTG

-

V_BATMIN

PGND

2

(I C Control)

Decoder

DAC

SCL

SDA

PGND

*

Signal Deglitched

Figure 22. Function Block Diagram of bq24152 in Boost Mode

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OPERATIONAL FLOW CHART

Power Up

V_BUS>V_UVLO

V_AUXPWR<V_LOWV

and bq24152?

High Impedance Modeor Host

Controlled Operation Mode

No

POR

2

Yes

Load I C Registers

with Default Value

Reset and Start

32-Minute Timer

Disable Charge

/CE=LOW

/CE=HIGH

Any Charge State

Charge Configure

Mode

Disable Charge

Wait Mode

Delay T

Indicate Power

not Good

INT

Yes

No

Enable I_SHORT

32-Minute

Timer Expired?

V_AUXPWR<V_SHORT

?

Yes

V_BUS<V_IN(MIN)

?

No

Indicate Short

Circuit condition

No

Regulate

Input Current, Charge

Current or Voltage

Yes

Indicate Charge-In-

Progress

Yes

V_BUS<V_IN(MIN)

?

Yes

Turn Off Charge

Indicate Fault

Yes

/CE=HIGH

No

Turn Off Charge

Enable I_DETECTfor

t_DETECT

32-Minute

Timer Expired?

No

Battery Removed

No

V_AUXPWR< V_OREG

V_RCH

-

Wait Mode

Delay T

Yes

Reset Charge

Parameters

?

INT

Yes

No

V_AUXPWR<V_SHORT

?

Charge Complete

Indicate DONE

32-Minute Timer

Active?

No

Yes

Termination Enabled

I_TERMdetected

Charge Complete

V_AUXPWR< V_OREG

V_RCH

-

and V_AUXPWR>V_OREG-V_RCH

?

High Impedance

Mode

Yes

Figure 23. Operational Flow Chart of bq24152 in Charge Mode

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bq24152

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DETAILED FUNCTIONAL DESCRIPTION

For a current limited power source, such as a USB host or hub, the high efficiency converter is critical in fully

using the input power capacity and charging the battery. Due to the high efficiency in a wide range of the input

voltage and battery voltage, the switching mode charger is a good choice for high speed charging with less

power loss and better thermal management.

The bq24152 is a highly integrated synchronous switch-mode charger with reverse boost function for USB OTG

support, featuring integrated MOSFETs and small external components, targeted at extremely space-limited

portable applications powered by 1-cell Li-Ion or Li-polymer battery pack.

The bq24152 usually has three operation modes: charge mode, boost mode, and high impedance mode. In

charge mode, the bq24152 supports a precision Li-ion or Li-polymer charging system for single-cell applications.

In boost mode, bq24152 boosts the battery voltage to VBUS for powering attached OTG devices. In high

impedance mode, the bq24152 stops charging or boosting and operates in a mode with low current from VBUS

or battery, to effectively reduce the power consumption when the portable device in standby mode. Through the

proper control, bq24152 can achieve the smooth transition among different operation modes.

CHARGE MODE OPERATION

Charge Profile

In charge mode, bq24152 has four control loops to regulate input current, charge current, charge voltage and

device junction temperature, as shown in Figure 21. During the charging process, all four loops are enabled and

the one that is dominant will take over the control. The bq24152 supports a precision Li-ion or Li-polymer

charging system for single-cell applications. Figure 24(a) indicates a typical charge profile without input current

regulation loop and it is similar to the traditional CC/CV charge curve, while Figure 24(b) shows a typical charge

profile when input current limiting loop is dominant during the constant current mode, and in this case the charge

current is higher than the input current so the charge process is faster than the linear chargers. For bq24152, the

input current limits, the charge current, termination current, and charge voltage are all programmable using I²C

interface.

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Precharge

Phase

Current Regulation

Phase

Voltage Regulation

Phase

Regulation

Voltage

Regulation

Current

Charge Voltage

V_SHORT

Charge Current

Termination

I SHORT

Precharge

(Linear Charge)

Fast Charge

(PWM Charge)

(a)

Precharge

Phase

Current Regulation

Phase

Voltage Regulation

Phase

Regulation

voltage

Charge Voltage

V_SHORT

Charge Current

Termination

I_SHORT

Fast Charge

Precharge

(Linear Charge)

(PWM Charge)

(b)

Figure 24. Typical Charging Profile of bq24152 for (a) without Input Current Limit, and (b) with Input

Current Limit

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PWM Controller in Charge Mode

The bq24152 provides an integrated, fixed 3-MHz frequency voltage-mode controller with Feed-Forward function

to regulate charge current or voltage. This type of controller is used to help improve line transient response,

thereby, simplifying the compensation network used for both continuous and discontinuous current conduction

operation. The voltage and current loops are internally compensated using a Type-III compensation scheme that

provides enough phase margin for stable operation, allowing the use of small ceramic capacitors with low ESR.

There is a 0.5-V offset on the bottom of the PWM ramp to allow the device to operate between 0% to 99.5% duty

cycles.

The bq24152 has two back to back common-drain N-channel MOSFETs at the high side and one N-channel

MOSFET at low side. An input N-MOSFET (Q1) prevents battery discharge when VBUS is lower than

VAUXPWR. The second high-side N-MOSFET (Q2) behaves as the switching control switch (see Figure 21). A

charge pump circuit is used to provide gate drive for Q1, while a boot strap circuit with external boot-strap

capacitor is used to boost up the gate drive voltage for Q2.

Cycle-by-cycle current limit is sensed through the internal sense MOSFETs for Q2 and Q3. The threshold for Q2

is set to a nominal 1.9-A peak current. The low-side MOSFET (Q3) also has a current limit that decides if the

PWM Controller will operate in synchronous or non-synchronous mode. This threshold is set to 100mA and it

turns off the low-side N-channel MOSFET (Q3) before the current reverses, preventing the battery from

discharging. Synchronous operation is used when the current of the low-side MOSFET is greater than 100mA to

minimize power losses.

Battery Charging Process

At the beginning of precharge, while battery voltage is below the V_(SHORT)threshold, the bq24152 applies a

short-circuit current, I_(SHORT), to the battery.

When the battery voltage is above V_(SHORT)and below V_(OREG), the charge current ramps up to fast charge

current, I_O(CHARGE), or a charge current that corresponds to the input current of I_{(IN_LIMIT)}. The slew rate for fast

charge current is controlled to minimize the current and voltage over-shoot during transient. Both the input

current limit (default at 100 mA), IIN_LIMIT, and fast charge current, I_O(CHARGE), can be set by the host. Once the

battery voltage is close to the regulation voltage, V_(OREG), the charge current is tapered down as shown in

Figure 24. The voltage regulation feedback occurs by monitoring the battery-pack voltage between the CSOUT

and PGND pins. bq24152 is a fixed single-cell voltage version, with adjustable regulation voltage (3.5 V to 4.44

V) programmed through I²C interface.

The bq24152 monitors the charging current during the voltage regulation phase. Once the termination threshold,

ITERM, is detected and the battery voltage is above the recharge threshold, the bq24152 terminates charge. The

termination current level is programmable. To disable the charge current termination, the host can set the charge

termination bit (I_Term) of charge control register to 0, see the I²C section for details.

A new charge cycle is initiated when one of the following conditions is detected:

•

The battery voltage falls below the V_(OREG)– V_(RCH)threshold.

VBUS Power-on reset (POR), if battery voltage is below the V_(LOWV)threshold.

CE bit toggle or RESET bit is set (host controlled)

Safety Timer in Charge Mode

At the beginning of charging process, the bq24152 starts a 32-minute timer (T32min) that can be stopped by any

write-action performed by host through I²C interface. Once the 32-minute timer is stopped, a 32-second timer

(T32sec) is automatically started. The 32-second timer can be reset by host using I²C interface. Writing "1" to

reset bit of TMR_RST in control register resets the 32-second timer and TMR_RST is automatically set to "0"

after the 32-second timer is reset. If the 32-second timer expires, the charge is terminated and charge

parameters are reset to default values. Then the 32-minute timer starts and the charge resumes.

During normal charging process, the bq24152 is normally in 32-second mode with host control, and 32-minute

mode without host control using I²C interface. The process repeats until the battery is fully charged. If the

32-minute timer expires, bq24152 turns off the charger and enunciates FAULT on the STATx bits of status

register. This function prevents battery over charge if the host fails to reset the safety timer. The safety timer flow

chart is shown in Figure 25. Fault condition is cleared by POR and fault status bits can only be updated after the

status bits are read out by the host.

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Charge Start

Start T32min

Timer

Reset Charge

Parameters

Yes

T32sec Expired?

Start T32sec

Stop T32min

No

Yes

Charge

Any I²C Write-

Action?

T32min

Expired?

T32min Active?

Yes

No

Host Should Reset

T32sec Timer

Yes

Timer Fault

Figure 25. Timer Flow Chart for bq24152 in Charge Mode

USB Friendly Boot-Up Sequence

At power on reset (POR) of VBUS, if the battery voltage is above the weak battery threshold, V_LOWV, bq24152

will operate in a mode dictated by the I²C control registers. On the other hand, if the battery voltage is below

V_LOWVand the host control through I²C interface is lost (32 minute mode), bq24152 will reset all I²C registers with

default values and enable the charger with an input current limit dictated by the OTG pin voltage level until the

host programs the I²C registers. During this period, the input current limit is 100 mA when the voltage level of

OTG pin is Low; while the input current limit is 500 mA when the voltage level of OTG pin is high. This feature

could quickly revive the deeply discharged cell. The charge process continues even the battery is charged to the

regulation voltage (default at 3.54 V) since termination is disabled by default. In another case, if the battery

voltage is below V_LOWVbut the host control using I²C interface is available (32 second mode), bq24152 will

operate in a mode dictated by control registers.

Input Current Limiting

To maximize the charge rate of bq24152 without overloading the USB port, the input current for bq24152 can be

limited to 100mA or 500mA which is programmed in the control register or OTG pin. Once the input current

reaches the input current limiting threshold, the charge current is reduced to keep the input current from

exceeding the programmed threshold. For bq14150, the default input current limit is controlled by the OTG pin at

VBUS power on reset when V_(AUXPWR)is lower than V_(LOWV). The input current sensing resistor and control loop

are integrated into bq24152. The input current limit can also be disabled using I²C control, see the definition of

control register (01H) for details.

Thermal Regulation and Protection

To prevent overheating the chip during the charging process, the bq24152 monitors the junction temperature, T_J,

of the die and begins to taper down the charge current once T_Jreaches the thermal regulation threshold, T_CF

The charge current is reduced to zero when the junction temperature increases approximately 10°C above T_CF

.

At any state, if T_Jexceeds T_SHTDWN, bq24152 suspends charging. At thermal shutdown mode, PWM is turned off

and all timers are frozen. Charging resumes when T_Jfalls below T_SHTDWNby approximately 10°C.

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Input Voltage Protection in Charge Mode

Sleep Mode

The bq24152 enters the low-power sleep mode if the voltage on VBUS pin falls below sleep-mode entry

threshold, V_AUXPWR+ V_SLP, and VBUS is still higher than the poor source detection threshold, V_IN(min). This

feature prevents draining the battery during the absence of VBUS. During sleep mode, both the reverse blocking

switch Q1 and PWM are turned off.

Input Source Detection

During the charging process, bq24152 continuously monitors the input voltage, VBUS. If VBUS falls to the low

input voltage threshold, V_IN(min), poor input power source is detected. Under this condition, bq24152 terminates

the charge process, waits for a delay time of T_INTand repeats the charging process, as indicated in Figure 23.

This unique function provides intelligence to bq24152 and so prevents USB power bus collapsing and oscillation

when connecting to a suspended USB port, or a USB-OTG device with low current capability.

Input Overvoltage Protection

The bq24152 provides a built-in input over-voltage protection to protect the device and other components against

damages if the input voltage (Voltage from VBUS to PGND) goes too high. When an input overvoltage condition

is detected, bq24152 turns off the PWM converter, sets fault status bits, and sends out fault pulse in STAT pin.

Once VBUS drops below the input overvoltage exit threshold, the fault is cleared and charge process resumes.

Battery Protection in Charge Mode

Output Overvoltage Protection

The bq24152 provides a built-in overvoltage protection to protect the device and other components against

damage if the battery voltage goes too high, as when the battery is suddenly removed. When an overvoltage

condition is detected, bq24152 turns off the PWM converter, sets fault status bits and sends out fault pulse in

STAT pin. Once V_(CSOUT)drops to the battery overvoltage exit threshold, the fault is cleared and charge process

back to normal.

Battery Detection During Normal Charging

For applications with removable battery packs, the bq24152 provides a battery absent detection scheme to

reliably detect insertion or removal of battery packs.

During normal charging process with host control, once the voltage at the AUXPWR pin is above the battery

recharge threshold, V_(OREG)– V_(RCH), and the termination charge current is detected, bq24152 turns off the

charge and enables a discharge current, I_(DETECT), for a period of t_DETECT, then checks the battery voltage. If the

battery voltage is still above recharge threshold, the battery is present and the charge done is detected.

However, if the battery voltage is below battery recharge threshold, the battery is absent. Under this condition,

the charge parameters (such as input current limit) are reset to the default values and charge resumes after a

delay of T_INT, as shown in Figure 23. This function ensures that the charge parameters are reset whenever the

battery is replaced.

Power Up Without Battery

When no battery is present, at VBUS power up, bq24152 will charge the output capacitor in short circuit mode

(when V_AUXPWR<V_SHORT) or PWM mode (when V_AUXPWR>V_SHORT). Once the output voltage at CSOUT pin is

charged to the default regulation voltage (3.54V), the voltage is kept constant until the 32-minute timer expires or

the host takes over the control through I²C interface. This unique feature makes bq24152 capable of starting the

system without battery.

Battery Short Protection

During the normal charging process, if the battery voltage is lower than the short-circuit threshold, V_(SHORT), the

charger operates in short circuit mode with a lower charge rate of I_(SHORT), as shown in Figure 22.

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Charge Status Output, STAT Pin

The STAT pin is used to indicate operation conditions for bq24152. STAT is pulled low during charging and

EN_STAT bit in control register (00H) is set to "1". Under other conditions, the STAT pin acts as a high

impedance (open-drain) output. Under fault conditions, a 128-µs pulse is sent out to notify the host. The status of

STAT pin at different operation conditions is summarized in Table 1. The STAT pin can be used to drive an LED

or communicate to the host processor.

Table 1. STAT Pin Summary

Charge State

STAT

Charge in progress and EN_STAT = 1

Other normal conditions

Low

Open-drain

Charge mode faults: Timer fault, sleep mode, VBUS 128-µs pulse, then open-drain

or battery overvoltage, poor input source, VBUS

UVLO, no battery, thermal shutdown

Boost mode faults: Timer fault, over load, VBUS or 128-µs pulse, then open-drain

battery overvoltage, low battery voltage, thermal

shutdown

Control Bits in Charge Mode

CE Bit (Charge Mode)

The bit of CE in control register is used to disable or enable the charge process. A low logic level (0) on this bit

enables the charge and a high logic level (1) disables the charge.

RESET Bit

The bit of RESET in control register is used to reset all the charge parameters. Writing '1" to RESET bit resets all

the charge parameters to default values and RESET bit is automatically cleared to zero once the charge

parameters are reset. It is designed for charge parameter reset before charge starts, and it is not recommended

to set the RESET bit when charging or boosting in progress.

OPA_Mode Bit

OPA_MODE is the operation mode control bit. When OPA_MODE = 0, the bq24152 charges the related

operation modes if HZ_MODE is set to "0", refer to Table 2 for detail.

Table 2. Operation Mode Summary

OPA_MODE

0

HZ_MODE

0

OPERATION MODE

Charge (no fault)

Charge configure (fault, V_bus> V_UVLO

)

High impedance (V_bus< V_UVLO

)

1

0

1

Boost (no faults)

Any fault go to charge configure mode

High impedance

X

Boost Mode Operation

In 32 second mode, when the OTG pin is in active status or the bit of operation mode (OPA_MODE) at control

register is set to 1, the bq24152 operates in boost mode and delivers the power to VBUS from the battery. At

normal boost mode, bq24152 converts the battery voltage (2.5 V to 4.5 V) to VBUS-B (about 5.05V) and delivers

a current as much as I_(BO)(approximately 200 mA) to support other USB OTG devices connected to the USB

connector.

PWM Controller in Boost Mode

Similar to charge mode operation, in boost mode, the bq24152 provides an integrated, fixed 3 MHz frequency

voltage-mode controller to regulate output voltage at PMID pin (VPMID), as shown in Figure 22. The voltage

control loop is internally compensated using a Type-III compensation scheme that provides enough phase

margin for stable operation with a wide load range and battery voltage range

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In boost mode, the input N-MOSFET (Q1) prevents battery discharge when VBUS pin is overloaded.

Cycle-by-cycle current limit is sensed through the internal sense MOSFET for Q3. The threshold for Q3 is set to

a nominal 1-A peak current. The upper-side MOSFET (Q2) also has a current limit that decides if the PWM

Controller will operate in synchronous or non-synchronous mode. This threshold is set to 75 mA and it turns off

the high-side N-channel MOSFET (Q2) before the current reverses, preventing the battery from charging.

Synchronous operation is used when the current of the high-side MOSFET is greater than 75 mA to minimize

power losses.

Boost Start Up

To prevent the inductor saturation and limit the inrush current, a soft-start control is applied during the boost start

up.

PFM Mode at Light Load

In boost mode, the bq24152 operates in pulse skipping mode (PFM mode) to reduce the power loss and improve

the converter efficiency at light load condition. During boosting, the PWM converter is turned off once the

inductor current is less than 75 mA; and the PWM is turned back on only when the voltage at PMID pin drops to

about 99.5% of the rated output voltage. A unique pre-set circuit is used to make the smooth transition between

PWM and PFM mode.

Safety Timer in Boost Mode

At the beginning of boost operation, the bq24152 starts a 32-second timer that can be reset by host through I²C

interface. Writing "1" to reset bit of TMR_RST in the control register resets the 32-second timer and TMR_RST is

automatically set to "0" after the 32-second timer is reset. To keep in boost mode, the host must reset the

32-second timer repeatedly. Once the 32-second timer expires, the bq24152 turns off the boost converter,

enunciate the fault pulse in STAT pin and set fault status bits in status register. Fault condition is cleared by POR

or host control.

Protection in Boost Mode

Output Overvoltage Protection

The bq24152 provides a built-in overvoltage protection to protect the device and other components against

damage if the VBUS voltage goes too high. When an overvoltage condition is detected, the bq24152 turns off the

PWM converter, reset OPA_MODE bit to 0, sets fault status bits, and sends out fault pulse in STAT pin. Once

VBUS drops to the normal level, the boost starts after host sets OPA_MODE to "1", or the OTG pin remains in

active status.

Output Overload Protection

The bq24152 provides a built-in overload protection to prevent the device and battery from damage when VBUS

is over loaded. Once over load condition is detected, Q1 operates in linear mode to limit the output current while

VPMID keeps in voltage regulation. If the overload condition lasts for more than 30ms, the overload fault is

detected. When an overload condition is detected, the bq24152 turns off the PWM converter, reset OPA_MODE

bit to 0, sets fault status bits, and sends out fault pulse in STAT pin. The boost will not start until the host clears

the fault register.

Battery Voltage Protection

During boosting, when battery voltage is above the battery overvoltage threshold, V_(BATMX), or below the minimum

battery voltage threshold, V_(BAT)min, the bq24152 turns off the PWM converter, reset OPA_MODE bit to 0, sets

fault status bits, and sends out fault pulse in STAT pin. Once battery voltage goes back to the normal level, the

boost starts after host sets OPA_MODE to "1", or the OTG pin remains in active status.

STAT Pin Boost Mode

During normal boosting process, the STAT pin behaves as a high impedance (open-drain) output. Under fault

conditions, a 128-µs pulse is sent out to notify the host.

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High Impedance Mode

When control bit of HZ-MODE is set to "1" and the OTG pin is not in active status, the bq24152 operates in high

impedance mode, with the impedance in VBUS pin higher than 165 kΩ. In high impedance mode, a crude

32-second timer is enabled when the battery voltage is below V_(LOWV)to monitor the host control is available or

not. If the crude 32 second timer expires, the bq24152 operates in 32 minute mode and the crude 32 second

timer is disabled. In 32 minute mode, when VBUS is below UVLO, the bq24152 operates in high impedance

mode regardless of the setting of the HZ_MODE bit.

Output Inductor and Capacitance Selection Guidelines

The bq24152 provides internal loop compensation. With this scheme, the best stability occurs when the LC

resonant frequency, ƒ_o, is approximately 40 kHz (20 kHz to 80 kHz). Equation 1 is used to calculate the value of

the output inductor, L_OUT, and output capacitor, C_OUT

.

1

f

=

o

2p ´

L

´ C

OUT

(1)

To reduce the output voltage ripple, a ceramic capacitor with the capacitance between 4.7 µF and 47 µF is

recommended for C_OUT, see the application section for components selection.

Pre-Regulator Application

Figure 2 shows a typical pre-regulator application that the bq24152 operates as a DC/DC converter, with the

termination disabled. The robust internal compensation design ensures the stable operation when the

host-controlled switch is turned off. With the input overvoltage protection, output current regulation and high

efficiency power conversion, the bq24152 is an ideal choice for pre-regulator used in pulse charging applications.

State Machine Table and State Diagram

Based on the previously-described operation modes, the definitions of all operation states are shown in Table 3

and Table 4, whereas the relationship among different states is shown in Figure 26.

Table 3. State Machine Table 1 of bq24152

MODE

POWER DOWN

CHARGE CONFIGURE

SHORT CIRCUIT

PWM CHARGE

OPA_MODE = 0

HZ_MODE = 0

OTG Inactive

VBUS > UVLO

VBUS < VBUS(MIN)

or

OPA_MODE = 0

HZ_MODE = 0

OTGIinactive

VBUS < VBUS(MIN)

VBUS < V_{(SLP_ENT)}

+V_{(SLP_EXIT)}

OPA_MODE = 0

HZ_MODE = 0

OTG Inactive

VBUS < VBUS(MIN)

VBUS < V_{(SLP_ENT)}

+V_{(SLP_EXIT)}

VBUS < UVLO

V_(AUXPWR)< V_(SHORT)

IN Condition

VBUS < V_{(SLP_ENT)}

or

V_(AUXPWR)< V_(SHORT)

CE = Low

V_(AUXPWR)< V_(SHORT)

CE = Low

CE = HIGH

No Faults

OPA_MODE = 1

or HZ_MODE = 1

VBUS < VBUS(MIN)

VBUS < V_{(SLP_ENT)}

or

OPA_MODE = 1

or HZ_MODE = 1

VBUS < VBUS(MIN)

VBUS < V_{(SLP_ENT)}

or

OPA_MODE = 1

or HZ_MODE = 1

or

VBUS > VBUS(MIN)

VBUS > V_{(SLP_ENT)}

+ V_{(SLP_EXIT)}

VBUS > UVLO

V_(AUXPWR)> V_(SHORT)

OUT Condition

V_(AUXPWR)< V_(SHORT)

CE = HIGH

V_(AUXPWR)< V_(SHORT)

CE = HIGH

or VBUS > UVLO

OTG Active

or Faults

or OTG Active

or Faults

or OTG Active

I²C

Buck

I_(SHORT)

Boost

Q1

Off

On

Off

On

Off

On

Off

On

Off

On

Off

On/Off

Note

POR when out

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Table 4. State Machine Table 2 of bq24152

MODE

HIGH IMPEDANCE

BOOST CONFIGURE

BOOST

OPA_MODE = 1

or OTG inactive

VBUS < UVLO, V_(AUXPWR)> V_(SHORT)

or Boost Configure,

OPA_MODE = 1

or HZ_MODE = 1

or OTG active

V_(AUXPWR)> V_(LOWV)

Ready To Start Up

or Faults During Boost

OPA_MODE = 1

HZ_MODE = 0

or OTG active

IN Condition

V_(AUXPWR)> V_(BAT)MIN

Start Up Finished

or No Faults

V_(AUXPWR)+ V_(LOWV)

or Boost, V_(AUXPWR)+V_(BAT)MIN

HZ_MODE = 0, OPA_MODE = 0

VBUS > UVLO

or HZ_MODE = 0, OPA_MODE = 1

V_(AUXPWR)> V_(LOWV)

OPA_MODE = 0

OTG Inactive

or HZ_MODE = 1

OPA_MODE = 0

OTG Inactive

or HZ_MODE = 1

or V_(AUXPWR)> V_(BAT)MIN

or Faults

OUT Condition

or V_(AUXPWR)> V_(LOWV)

Boost Start Up Finished

or V_(AUXPWR)+V_(SHORT)

or OTG Active

On

Off

On

Off

On

Off

On

Off

On/Off⁽¹⁾

(1) Q1 is OFF when VBUS is shorted to ground.

V_BUS<V_UVLO

V_AUXPWR<V_SHORT

V_BUS>V_UVLO

V_AUXPWR<V_LOWV

ANY STATE

POWER DOWN

V_AUXPWR>V_POR

HZ_MODE=1

or V_BUS<V_UVLO, V_AUXPWR>V_SHORT

V_BUS>

POR

V_BUS>V_UVLO

HZ_MODE=0, OPA_MODE=0

HIGH

IMPEDANCE

CHARGE

CONFIGURE

HZ_MODE=1

OPA_MODE=1

HZ_MODE=0

HZ_MODE=1

Or

V_AUXPWR<V_LOWV

V_AUXPWR>V_SHORT

or V_BUS<V_BUS(MIN)

or FAULTS

OPA_MODE=1

HZ_MODE=0

V_AUXPWR>V_LOWV

OPA_MODE=0

V_AUXPWR<V_SHORT

V_BUS>V_BUS(MIN)

BOOST

CONFIGURE

HZ_MODE=1

or

V_AUXPWR<V_BATMIN

V_BUS>V_{SLP_ENT}+V_{SLP_EXIT}

NO FAULTS

V_AUXPWR<V_SHORT

or V_BUS<V_BUS(MIN)

or FAULTS

SHORT

OPA_MODE=1

HZ_MODE=0

CIRCUIT

START UP

No FAULTS

V_AUXPWR>V_SHORT, V_BUS>V_BUS(MIN)

V_BUS>V_{SLP_ENT}+V_{SLP_EXIT}

NO FAULTS

PWM CHARGE

BOOST

OPA_MODE=0

or FAULTS

Figure 26. State Diagram for bq24152

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SERIAL INTERFACE DESCRIPTION

I²C™ is a 2-wire serial interface developed by Philips Semiconductor (see I²C-Bus Specification, Version 2.1,

January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the

bus is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices connect to the I²C bus

through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal

processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The

master also generates specific conditions that indicate the START and STOP of data transfer. A slave device

receives and/or transmits data on the bus under control of the master device.

The bq24152 device works as a slave and supports the following data transfer modes, as defined in the

I²C-Bus™ Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps

in write mode). The interface adds flexibility to the battery charge solution, enabling most functions to be

programmed to new values depending on the instantaneous application requirements. Register contents remain

intact as long as supply voltage remains above 2.2 V (typical).

The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the

F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to

as the HS-mode. The bq24152 device only supports 7-bit addressing. The device 7-bit address is defined as

‘1101011’ (6BH).

F/S Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low

transition occurs on the SDA line while SCL is high, as shown in Figure 27. All I²C-compatible devices should

recognize a start condition.

DATA

CLK

S

P

START Condition

STOP Condition

Figure 27. START and STOP Condition

The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W

on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires

the SDA line to be stable during the entire high period of the clock pulse (see Figure 28). All devices recognize

the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a

matching address generates an acknowledge (see Figure 28) by pulling the SDA line low during the entire high

period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a

slave has been established.

DATA

CLK

Data Line

Stable;

Data Valid

Change

of Data

Allowed

Figure 28. Bit Transfer on the Serial Interface

The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the

slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an

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acknowledge signal can either be generated by the master or by the slave, depending on which one is the

receiver. the 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as

necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line

from low to high while the SCL line is high (see Figure 30). This releases the bus and stops the communication

link with the addressed slave. All I²C compatible devices must recognize the stop condition. Upon the receipt of a

stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching

address. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the

slave I²C logic from remaining in a bad state. Attempting to read data from register addresses not listed in this

section will result in FFh being read out.

Data Output

by Transmitter

Not Acknowledge

Data Output

by Receiver

Acknowledge

SCL From

Master

9

8

1

2

Clock Pulse for

Acknowledgement

START

Condition

Figure 29. Acknowledge on the I²C Bus™

Recognize START or

REPRATED START

Condition

Recognize STOP or

REPRATED START

Condition

Generate ACKNOWLEDGE

Signal

P

SDA

Acknowledgement

Signal From Slave

MSB

Sr

Address

R/W

SCL

S

or

Sr

or

P

ACK

Sr

Clock Line Held Low While

Interrupts are Serviced

Figure 30. Bus Protocol

H/S Mode Protocol

When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.

The master generates a start condition followed by a valid serial byte containing HS master code '00001XXX'.

This transmission is made in F/S mode at no more than 400 Kbps. No device is allowed to acknowledge the HS

master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation

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The master then generates a repeated start condition (a repeated start condition has the same timing as the start

condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission

speeds up to 3.4 Mbps are allowed. A stop condition ends the HS mode and switches all the internal settings of

the slave devices to support the F/S mode. Instead of using a stop condition, repeated start conditions should be

used to secure the bus in HS mode. If a transaction is terminated prematurely, the master needs sending a

STOP condition to prevent the slave I²C logic from remaining in a bad state.

Attempting to read data from register addresses not listed in this section results in FFh being read out.

bq24152 I²C Update Sequence

The bq24152 requires a start condition, a valid I²C address, a register address byte, and a data byte for a single

update. After the receipt of each byte, bq24152 device acknowledges by pulling the SDA line low during the high

period of a single clock pulse. A valid I²C address selects the bq24152. The bq24152 performs an update on the

falling edge of the acknowledge signal that follows the LSB byte.

For the first update, bq24152 requires a start condition, a valid I²C address, a register address byte, a data byte.

For all consecutive updates, bq24152 needs a register address byte, and a data byte. Once a stop condition is

received, the bq24152 releases the I²C bus, and awaits a new start conditions.

S

SLAVE ADDRESS

R/W

A

REGISTER ADDRESS

Data Transferred

A

DATA

P

A/A

‘0’ (Write)

(n Bytes + Acknowledge)

From master to bq24152

From bq24152 to master

A

= Acknowledge (SDA LOW)

= Not acknowledge (SDA

HIGH)

S

= START condition

Sr = Repeated START condition

= STOP condition

P

(a) F/S-Mode

F/S-Mode

HS-Mode

S

HS-MASTER CODE

Sr

SLAVE ADDRESS

R/W

A

REGISTER ADDRESS

A

DATA

P

A

A/A

Data Transferred

HS-Mode

‘0’ (write)

(n Bytes + Acknowledge)

Continues

Sr

Slave A.

(b) HS-Mode

Figure 31. Data Transfer Format in F/S Mode and H/S Mode

Slave Address Byte

MSB

LSB

1

X

1

0

1

0

1

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The slave address byte is the first byte received following the START condition from the master device. The

address bits are factory preset to ‘1101011’.

Register Address Byte

MSB

LSB

D0

0

D2

D1

Following the successful acknowledgment of the slave address, the bus master will send a byte to the bq24152,

which contains the address of the register to be accessed. The bq24152 contains five 8-bit registers accessible

via a bidirectional I²C-bus interface. Among them, four internal registers have read and write access; and one

has only read access.

I²C INTERFACE TIMING CHARACTERISTICS

SYMBOL

PARAMETER

TEST CONDITIONS

Standard mode

MIN

TYP

MAX

100

UNIT

kHz

Fast mode

400

kHz

High-speed mode (write operation)

CB - 100 pF max

3.4

2

High-speed mode (read operation)

CB - 100 pF max

f_SCL

SCL clock frequency

MHz

High-speed mode (write operation)

CB - 400 pF max

1.7

2

High-speed mode (read operation)

CB - 400 pF max

Standard mode

4.7

1.3

4

Bus free time between a STOP and

START condition

t_BUF

µs

ns

Fast mode

Standard mode

Hold time (repeated) START

condition

t_HD; t_STA

Fast mode

600

160

4.7

1.3

160

320

4

High-speed mode

Standard mode

µs

Fast mode

t_LOW

LOW period of the SCL clock

HIGH period of the SCL clock

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

Standard mode

ns

µs

Fast mode

600

60

t_HIGH

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

Standard mode

ns

120

4.7

600

160

250

100

10

µs

Setup time for a repeated START

condition

t_SU; t_STA

Fast mode

ns

High-speed mode

Standard mode

t_SU; t_DAT

Data setup time

Data hold time

Fast mode

ns

High-speed mode

Standard mode

3.45

0.9

70

µs

Fast mode

t_HD; t_DAT

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

ns

150

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SYMBOL

PARAMETER

TEST CONDITIONS

Standard mode

MIN

20+0.1C_B

10

TYP

MAX

1000

300

40

UNIT

Fast mode

t_RCL

Rise time of SCL signal

ns

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

Standard mode

20

80

20+0.1C_B

10

1000

300

80

Rise time of SCL signal after a

repeated START condition and after

an acknowledge bit

Fast mode

t_RCL1

ns

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

Standard mode

20

160

300

40

20+0.1C_B

10

Fast mode

t_FCL

Fall time of SCL signal

Rise time of SDA signal

Fall time of SDA signal

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

Standard mode

20

80

20+0.1C_B

10

1000

300

80

Fast mode

t_RDA

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

Standard mode

20

160

300

80

20+0.1C_B

10

Fast mode

t_FDA

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

Standard mode

20

160

4

µs

ns

pF

t_SU; t_STO

Setup time for STOP condition

Capacitive load for SDA and SCL

Fast mode

600

High-speed mode

160

C_B

400

I²C Timing Diagrams

SDA

t

t_f

SU;DAT

t_LOW

t

t_r

t_HD;STA

t

t_r

t_f

SP

BUF

SCL

t_HD;STA

t

SU;STA

SU;STO

t_HIGH

t_HD;DAT

S

P

S

Sr

Figure 32. Serial Interface Timing for FS Mode

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Sr

Sr P

t

rDA

t

fDA

SDAH

t

HD;DAT

SU;STO

t

SU;STA

t

HD;STA

SU;DAT

SCLH

t

fCL1

(1)

t

rCL1

t

rCL1

(1)

t

HIGH

LOW

HIGH

= MCS current source pull-up

= R resister pull-up

P

Figure 33. Serial Interface Timing for HS Mode

REGISTER DESCRIPTION

Table 5. Status/Control Register (Read/Write)

Memory Location: 00, Reset State: x1xx 0xxx

BIT

NAME

READ/WRITE

FUNCTION

Write: TMR_RST function, write "1" to reset the safety timer (auto clear)

Read: OTG pin status, 0-OTG pin at Low level, 1-OTG pin at High level

B7 (MSB)

TMR_RST/OTG

Read/Write

B6

B5

B4

B3

B2

B1

EN_STAT

STAT2

Read/Write

Read Only

0-Disable STAT pin function, 1-Enable STAT pin function (default 1)

00-Ready, 01-Charge in progress, 10-Charge done, 11-Fault

1-Boost mode, 0-Not in boost mode

STAT1

BOOST

FAULT_3

FAULT_2

Charge mode: 000-Normal, 001-VBUS OVP, 010-Sleep mode, 011-Poor input

source or VBUS < UVLO, 100-Battery OVP, 101-Thermal shutdown, 110-Timer

fault, 111-No battery

Boost mode: 000-Normal, 001-VBUS OVP, 010-Over load, 011-Battery voltage

is too low, 100-Battery OVP, 101-Thermal shutdown, 110-Timer fault, 111-NA

B1 (LSB)

FAULT_1

Read Only

Table 6. Control Register (Read/Write)

Memory Location: 01, Reset State: 0011 0000 (30H)

BIT

NAME

READ/WRITE

FUNCTION

B7 (MSB)

Iin_Limit_2

Read/Write

00-USB host with 100-mA current limit, 01-USB host with 500-mA current limit,

10-USB host/charger with 800-mA current limit, 11-No input current limit

(default 00)

B6

Iin_Limit_1

Read/Write

B5

B4

VLOWV_2⁽¹⁾

VLOWV_1⁽¹⁾

Read/Write

200-mV weak battery voltage threshold (default 1)

100-mV weak battery voltage threshold (default 1)

1-Enable charge current termination, 0-Disable charge current termination

(default 0)

B3

TE

Read/Write

B2

B1

CE

Read/Write

1-Charger is disabled, 0-Charger enabled (default 0)

HZ_MODE

1-High impedance mode, 0-Not high impedance mode (default 0)

(1) The range of the weak battery voltage threshold (V_(LOWV)) is 3.4 V to 3.7 V and step of 100 mV (default of 3.7 V).

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Table 6. Control Register (Read/Write)

Memory Location: 01, Reset State: 0011 0000 (30H) (continued)

BIT

NAME

READ/WRITE

FUNCTION

1-Boost mode, 0-Charger mode (default 0)

B1 (LSB)

OPA_MODE

Read/Write

Table 7. Control/Battery Voltage Register (Read/Write)

Memory Location: 02, Reset State: 0000 1010 (0AH)

BIT

B7 (MSB)

B6

NAME

V_O(REG5)

V_O(REG4)

V_O(REG3)

V_O(REG2)

V_O(REG1)

V_O(REG0)

OTG_PL

OTG_EN

READ/WRITE

Read/Write

FUNCTION

Battery regulation voltage: 640mV (default 0)

Battery regulation voltage: 320mV (default 0)

Battery regulation voltage: 160mV (default 0)

Battery regulation voltage: 80mV (default 0)

Battery regulation voltage: 40mV (default 1)

Battery regulation voltage: 20mV (default 0)

1-Active at High level, 0-Active at Low level (default 1)

1-Enable OTG Pin, 0-Disable OTG pin (default 0)

B5

B4

B3

B2

B1

B1 (LSB)

Charge voltage range is 3.5 V to 4.44 V with the offset of 3.5 V and step of 20 mV (default is 3.54 V).

Table 8. Vender/Part/Revision Register (Read only)

Memory Location: 03, Reset State: 0100 x001

BIT

B7 (MSB)

B6

NAME

Vender2

Vender1

Vender0

PN1

READ/WRITE

Read Only

FUNCTION

Vender Code: bit 2 (default 0)

Vender Code: bit 1 (default 1)

Vender Code: bit 0 (default 0)

B5

B4

Part Number Code: bit 1 (default 0)

B3

PN0

Part Number Code: bit 0 (default 0 for bq24151, default 1 for bq24152)

B2

Revision2

Revision1

Revision0

000: Revision 1.0;

001: Revision 1.1;

010: Revision 1.2;

011-111: Future Revisions

B1

B1 (LSB)

Table 9. Battery Termination/Fast Charge Current Register (Read/Write)

Memory Location: 04, Reset State: 1000 1001 (89H)

BIT

NAME

READ/WRITE

FUNCTION

Write: 1-Charger in reset mode, 0-No effect

Read: always get "1"

B7 (MSB)

Reset

Read/Write

B6

B5

V_I(CHRG2)

V_I(CHRG1)

V_I(CHRG0)

NA

Read/Write

Charge current sense voltage: 27.2mV (default 0)

Charge current sense voltage: 13.6mV(default 0)

Charge current sense voltage: 6.8mV (default 0)

NA

B4

B3

B2

V_I(TERM2)

V_I(TERM1)

V_I(TERM0)

Termination current sense voltage: 13.6mV (default 0)

Termination current sense voltage: 6.8mV (default 0)

Termination current sense voltage: 3.4mV (default 1)

B1

B1 (LSB)

Default charge current is 55 0mA and default termination current is 100 mA, if a 68-mΩ sensing resistor is used.

Both the termination current range and charge current range are depending on the sensing resistor R_(SNS)). The

termination current step (I_{O(TERM_STEP)}) is calculated using Equation 2:

V

I(TERM0)

I

=

O(TERM_STEP)

R

(SNS)

(2)

29

Table 10 shows the termination current settings with two sensing resistors.

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Table 10. Termination Current Settings for 68-mΩ and 100-mΩ Sense Resistors

I_(TERM)(mA)

R_(SNS)= 68mΩ

I_(TERM)(mA)

R_(SNS)= 100mΩ

BIT

V_I(TERM)(mV)

V_I(TERM2)

V_I(TERM1)

V_I(TERM0)

Offset

13.6

6.8

3.4

200

100

50

136

68

34

50

34

The charge current step (I_{O(CHARGE_STEP)}) is calculated using Equation 3:

V

I(CHRG0)

I

=

O(CHARGE_STEP)

R

(SNS)

(3)

Table 11 shows the charge current settings with two sensing resistors.

Table 11. Charge Current Settings for 68-mΩ and 100-mΩ Sense Resistors

I_O(CHARGE)(mA)

R_(SNS)= 68mΩ

I_O(CHARGE)(mA)

R_(SNS)= 100mΩ

BIT

V_I(REG)(mV)

V_I(CHRG2)

V_I(CHRG1)

V_I(CHRG0)

Offset

27.2

13.6

6.8

400

200

100

550

272

136

68

37.4

374

DESIGN EXAMPLE FOR TYPICAL APPLICATION CIRCUITS

Systems Design Specifications:

•

VBUS = 5 V

V_(BAT)= 4.2 V (1-Cell)

I_(charge)= 1.25 A

Inductor ripple current = 30% of fast charge current

1. Determine the inductor value (L_OUT) for the specified charge current ripple:

VBAT ´ (VBUS - VBAT)

L

=

OUT

VBUS ´ f ´ DI

L

, the worst case is when battery voltage is as close as to half of the input

voltage.

2.5 ´ (5 - 2.5)

L

=

OUT

6

5 ´ (3 ´ 10 ) ´ 1.25 ´ 0.3

L_OUT= 1.11 µH

Select the output inductor to standard 1 µH. Calculate the total ripple current with using the 1 µH inductor:

VBAT ´ (VBUS - VBAT)

DI =

L

VBUS ´ f ´ L

OUT

2.5 ´ (5 - 2.5)

DI =

L

6

-6

5 ´ (3 ´ 10 ) ´ (1 ´ 10

)

ΔI_L= 0.42 A

Calculate the maximum output current:

30

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Product Folder Link(s): bq24152

bq24152

www.ti.com ...................................................................................................................................................................................................... SLUS847–JUNE 2008

DI

L

I

= I +

OUT

LPK

2

0.42

2

I

= 1.25 +

LPK

I_LPK= 1.46 A

Select 2.5mm by 2.0mm 1-µH 1.5-A surface mount multi-layer inductor. The suggested inductor part

numbers are shown as following.

Table 12. Inductor Part Numbers

PART NUMBER

LQM2HPN1R0MJ0

MIPS2520D1R0

MDT2520-CN1R0M

CP1008

INDUCTANCE

1 µH

SIZE

MANUFACTURER

muRata

2.5 x 2.0 mm

1 µH

FDK

1 µH

TOKO

1 µH

Inter-Technical

2. Determine the output capacitor value C_OUTusing 40 kHz as the resonant frequency:

1

f

=

o

2p ´

L

´ C

OUT

1

C

=

OUT

2

4p ´ f

2

´ L

0

OUT

1

C

=

OUT

2

3 2

-6

4p ´ (40 ´ 10 ) ´ (1 ´ 10 )

C_OUT= 15.8 µF

Select two 0603 X5R 6.3V 10-µF ceramic capacitors in parallel i.e., muRata GRM188R60J106M.

3. Determine the sense resistor using the following equation:

V

(RSNS)

R

=

(SNS)

I

(CHARGE)

The maximum sense voltage across sense resistor is 85 mV. In order to get a better current regulation

accuracy, V_(RSNS)should equal 85 mV, and calculate the value for the sense resistor.

85mV

R

=

(SNS)

1.25A

R_(SNS)= 68 mΩ

This is a standard value. If it is not a standard value, then choose the next close value and calculate the real

charge current. Calculate the power dissipation on the sense resistor:

P_(RSNS)= I_(CHARGE)²× R_(SNS)

P_(RSNS)= 125²× 0.068

P_(RSNS)= 0.106 W

Select 0402 0.125-W 68-mΩ 2% sense resistor, i.e. Panasonic ERJ2BWGR068.

4. Measured efficiency and total power loss for different inductors are shown in Figure 34.

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31

Product Folder Link(s): bq24152

bq24152

SLUS847–JUNE 2008 ...................................................................................................................................................................................................... www.ti.com

Battery Charge Efficiency

Battery Charge Loss

90

89

88

87

86

85

84

800

700

600

T =25°C,

A

TOKO

VBUS = 5 V,

VBAT = 3 V

VBUS = 5 V,

VBAT = 3 V

FDK

muRata

Inter-Technical

muRata

500

400

300

TOKO

FDK

Inter-Technical

200

100

83

82

500 600 700 800 900 1000 1100 1200 1300

Charge Current - mA

500 600 700 800 900 1000 1100 1200 1300

Charge Current - mA

Figure 34. Measured Efficiency and Power Loss

PCB LAYOUT CONSIDERATION

It is important to pay special attention to the PCB layout. The following provides some guidelines:

•

To obtain optimal performance, the power input capacitors, connected from input to PGND, should be placed

as close as possible to the bq24152. The output inductor should be placed close to the IC and the output

capacitor connected between the inductor and PGND of the IC. The intent is to minimize the current path loop

area from the SW pin through the LC filter and back to the PGND pin. To prevent high frequency oscillation

problems, proper layout to minimize high frequency current path loop is critical (see Figure 35). The sense

resistor should be adjacent to the junction of the inductor and output capacitor. Route the sense leads

connected across the RSNS back to the IC, close to each other (minimize loop area) or on top of each other

on adjacent layers (do not route the sense leads through a high-current path, see Figure 36).

•

Place all decoupling capacitor close to their respective IC pin and as close as to PGND (do not place

components such that routing interrupts power stage currents). All small control signals should be routed

away from the high current paths.

The PCB should have a ground plane (return) connected directly to the return of all components through vias

(two vias per capacitor for power-stage capacitors, two vias for the IC PGND, one via per capacitor for

small-signal components). A star ground design approach is typically used to keep circuit block currents

isolated (high-power/low-power small-signal) which reduces noise-coupling and ground-bounce issues. A

single ground plane for this design gives good results. With this small layout and a single ground plane, there

is no ground-bounce issue, and having the components segregated minimizes coupling between signals.

•

The high-current charge paths into VBUS, PMID and from the SW pins must be sized appropriately for the

maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be

connected to the ground plane to return current through the internal low-side FET.

L1

R1

V

VBUS

BAT

SW

High

Frequency

BAT

V

IN

Current

Path

PMID

C2

PGND

C3

C1

Figure 35. High Frequency Current Path

32

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bq24152

www.ti.com ...................................................................................................................................................................................................... SLUS847–JUNE 2008

Charge Current Direction

R

SNS

To Inductor

To Capacitor and battery

Current Sensing Direction

To CSIN and CSOUT pin

Figure 36. Sensing Resistor PCB Layout

PACKAGE SUMMARY

WCSP PACKAGE

(Top View)

CHIP SCALE PACKAGE

(Top Side Symbol For bq24152)

A1

B1

C1

A2

B2

A3

A4

B4

B3

C3

TIYMLLLLS

bq24152

C2

C4

D

D1

E1

D2

E2

D3

E3

D4

E4

0-Pin A1 Marker, TI-TI Letters, YM- Year Month

Date Code, LLLL-Lot Trace Code, S-Assembly

Site Code

E

CHIP SCALE PACKAGING DIMENSIONS

The bq24152 device is available in a 20-bump chip scale package (YFF, NanoFree^TM). The package

dimensions are:

· D = 1.976 ± 0.05 mm

· E = 1.924 ± 0.05 mm

Submit Documentation Feedback

33

Product Folder Link(s): bq24152

PACKAGE OPTION ADDENDUM

www.ti.com

30-Jun-2008

PACKAGING INFORMATION

Orderable Device

BQ24152YFFR

BQ24152YFFT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

DSBGA

YFF

20

3000 Green (RoHS &

no Sb/Br)

SnAgCu

Level-1-260C-UNLIM

DSBGA

YFF

20

250 Green (RoHS &

no Sb/Br)

SnAgCu

Level-1-260C-UNLIM

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

25-Jun-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

BQ24152YFFR

BQ24152YFFT

DSBGA

YFF

20

3000

250

178.0

8.4

2.18

0.81

4.0

8.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

25-Jun-2008

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ24152YFFR

BQ24152YFFT

DSBGA

YFF

20

3000

250

217.0

193.0

35.0

Pack Materials-Page 2

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

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型号：	LQM2HPN1R0MJ0
厂家：	TEXAS INSTRUMENTS
描述：	Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and USB-OTG Support 完全集成开关模式单节锂离子电池充电器与USB完全遵守和USB -OTG支持电池开关
文件：	总38页 (文件大小：2499K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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