LT1054CP_技术文档

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SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

P PACKAGE

(TOP VIEW)

D

Output Current . . . 100 mA

Low Loss . . . 1.1 V at 100 mA

Operating Range . . . 3.5 V to 15 V

FB/SD

CAP+

GND

V

CC

OSC

1

2

3

4

8

7

6

5

Reference and Error Amplifier for

Regulation

V

REF

CAP−

V

OUT

External Shutdown

External Oscillator Synchronization

Devices Can Be Paralleled

DW PACKAGE

(TOP VIEW)

Pin-to-Pin Compatible With the

LTC1044/7660

NC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

description/ordering information

V

FB/SD

CAP+

GND

CAP−

NC

CC

OSC

The LT1054 is a bipolar, switched-capacitor

voltage converter with regulator. It provides higher

output current and significantly lower voltage

losses than previously available converters. An

V

REF

V

OUT

NC

adaptive-switch

drive

scheme

optimizes

efficiency over a wide range of output currents.

Total voltage drop at 100-mA output current

typically is 1.1 V. This applies to the full

supply-voltage range of 3.5 V to 15 V. Quiescent

current typically is 2.5 mA.

NC − No internal connection

The LT1054 also provides regulation, a feature previously not available in switched-capacitor voltage

converters. By adding an external resistive divider, a regulated output can be obtained. This output is regulated

against changes in both input voltage and output current. The LT1054 also can be shut down by grounding the

feedback terminal. Supply current in shutdown typically is 100 µA.

The internal oscillator of the LT1054 runs at a nominal frequency of 25 kHz. The oscillator terminal can be used

to adjust the switching frequency or to externally synchronize the LT1054.

The LT1054C is characterized for operation over a free-air temperature range of 0°C to 70°C. The LT1054I is

characterized for operation over a free-air temperature range of −40°C to 85°C.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

T

A

PDIP (P)

Tube of 50

Tube of 40

Reel of 2000

Tube of 50

Tube of 40

Reel of 2000

LT1054IP

LT1054IDW

LT1054IDWR

LT1054CP

−40°C to 85°C

0°C to 70°C

SOIC (DW)

PDIP (P)

LT1054I

LT1054CP

LT1054C

LT1054CDW

LT1054CDWR

SOIC (DW)

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

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Copyright  2004, Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

functional block diagram

V

REF

V

CC

6

8

2.5 V

Ref

R

Drive

2

4

+

−

CAP +

1

7

†

FB/SD

OSC

C

IN

Q

OSC

CAP −

Q

Drive

3

GND

†

C

OUT

5

V

OUT

Drive

†

External capacitors

Pin numbers shown are for the P package.

‡

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V

CC

Input voltage range, V : FB/SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to V

I

CC

OSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to V

ref

Junction temperature, T (see Note 2): LT1054C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C

J

LT1054I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135°C

Package thermal impedance, θ (see Notes 3 and 4): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W

JA

P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C

Storage temperature range, T

stg

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The absolute maximum supply-voltage rating of 16 V is for unregulated circuits. For regulation-mode circuits with V

rating may be increased to 20 V.

≤ 15 V, this

OUT

2. The devices are functional up to the absolute maximum junction temperature.

3. Maximum power dissipation is a function of T (max), θ , and T . The maximum allowable power dissipation at any allowable

JA

J

A

ambient temperature is P = (T (max) − T )/θ . Operating at the absolute maximum T of 150°C can impact reliability.

D

J

A

JA

J

4. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions

MIN

3.5

0

MAX

15

UNIT

V

Supply voltage

V

CC

LT1054C

LT1054I

70

T

A

Operating free-air temperature range

°C

−40

85

2

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SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

electrical characteristics over recommended operating conditions (unless otherwise noted)

LT1054C

LT1054I

†

PARAMETER

TEST CONDITIONS

UNIT

T

A

‡

MIN TYP

MAX

−5.2

25

V

O

Regulated output voltage

Input regulation

V

CC

V

CC

V

CC

= 7 V, T = 25°C, R = 500 Ω, See Note 5

25°C

−4.7

−5

5

V

J

L

= 7 V to 12 V, R = 500 Ω, See Note 5

Full range

mV

L

Output regulation

= 7 V, R = 100 Ω to 500 Ω, See Note 5

10

50

L

I

= 10 mA

0.35

1.1

10

0.55

1.6

Voltage loss,

O

C = C = 100-µF tantalum

Full range

V

I

O

V

CC

− |V  (see Note 6)

O

I

= 100 mA

Output resistance

∆I = 10 mA to 100 mA,

O

See Note 7

Full range

25°C

15

Ω

Oscillator frequency

V

CC

= 3.5 V to 15 V

15

2.35

2.25

25

35

kHz

2.5

2.65

2.75

V

ref

Reference voltage

I

= 60 µA

V

(REF)

Full range

25°C

Maximum switch current

300

2.5

3

mA

V

= 3.5 V

= 15 V

4

5

CC

I

Supply current

I = 0

O

Full range

mA

CC

Supply current in shutdown

V

= 0 V

100

200

µA

(FB/SD)

†

‡

Full range is 0°C to 70°C for the LT1054C and −40°C to 85°C for the LT1054I.

All typical values are at T = 25°C.

A

NOTES: 5. All regulation specifications are for a device connected as a positive-to-negative converter/regulator with R1 = 20 kΩ, R2 = 102.5 kΩ,

external capacitor C = 10 µF (tantalum), external capacitor C = 100 µF (tantalum) and C1 = 0.002 µF (see Figure 15).

IN OUT

6. For voltage-loss tests, the device is connected as a voltage inverter, with terminals 1, 6, and 7 unconnected. The voltage losses

may be higher in other configurations. C and C are external capacitors.

IN OUT

7. Output resistance is defined as the slope of the curve (∆V versus ∆I ) for output currents of 10 mA to 100 mA. This represents

O

the linear portion of the curve. The incremental slope of the curve is higher at currents less than 10 mA due to the characteristics

of the switch transistors.

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SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

Shutdown threshold voltage vs Free-air temperature

Supply current vs Input voltage

1

2

Oscillator frequency vs Free-air temperature

Supply current in shutdown vs Input voltage

Average supply current vs Output current

Output voltage loss vs Input capacitance

Output voltage loss vs Oscillator frequency (10 µF)

Output voltage loss vs Oscillator frequency (100 µF)

Regulated output voltage vs Free-air temperature

Reference voltage change vs Free-air temperature

Voltage loss vs Output current

3

4

5

6

7

8

9

10

11

Table of Figures

FIGURE

12

Switched-Capacitor Building Block

Switched-Capacitor Equivalent Circuit

13

Circuit With Load Connected From V

External-Clock System

to V

OUT

14

CC

15

Basic Regulation Configuration

16

Power-Dissipation-Limiting Resistor in Series With C

Motor-Speed Servo

17

IN

18

Basic Voltage Inverter

19

Basic Voltage Inverter/Regulator

Negative-Voltage Doubler

20

21

Positive-Voltage Doubler

22

100-mA Regulating Negative Doubler

Dual-Output Voltage Doubler

5-V to 12-V Converter

23

24

25

Strain-Gage Bridge Signal Conditioner

3.5-V to 5-V Regulator

26

27

Regulating 200-mA +12-V to −5-V Converter

Digitally Programmable Negative Supply

28

29

Positive Doubler With Regulation (5-V to 8-V Converter)

Negative Doubler With Regulator

30

31

4

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SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

†

TYPICAL CHARACTERISTICS

SHUTDOWN THRESHOLD VOLTAGE

SUPPLY CURRENT

vs

FREE-AIR TEMPERATURE

INPUT VOLTAGE

0.6

0.5

0.4

0.3

0.2

0.1

0

5

4

3

2

I

O

= 0

V

(FB/SD)

1

0

−50

−25

0

25

50

75

100

0

5

10

15

V

CC

− Input Voltage − V

T

A

− Free-Air Temperature − °C

Figure 1

Figure 2

OSCILLATOR FREQUENCY

vs

FREE-AIR TEMPERATURE

SUPPLY CURRENT IN SHUTDOWN

vs

INPUT VOLTAGE

35

33

120

100

80

60

40

20

0

31

29

27

25

V

) = 0

(FB/SD

V

= 15 V

CC

V

= 3.5 V

CC

23

21

19

17

15

−50

−25

0

25

50

75

100

0

5

10

15

V

CC

− Input Voltage − V

T

A

− Free-Air Temperature − °C

Figure 3

Figure 4

†

Data at high and low temperatures are applicable only within the recommended operating free-air temperature range.

5

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SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

TYPICAL CHARACTERISTICS

AVERAGE SUPPLY CURRENT

OUTPUT VOLTAGE LOSS

vs

INPUT CAPACITANCE

vs

OUTPUT CURRENT

140

120

100

1.4

1.2

1.0

I

O

= 100 mA

80

60

0.8

0.6

I

= 50 mA

= 10 mA

O

40

0.4

Inverter Configuration

20

0

0.2

0

C

f

= 100-µF Tantalum

= 25 kHz

OUT

OSC

0

20

40

60

80

100

0

10 20 30 40 50 60 70 80 90 100

Input Capacitance − µF

I

O

− Output Current − mA

Figure 5

Figure 6

OUTPUT VOLTAGE LOSS

vs

OSCILLATOR FREQUENCY

OUTPUT VOLTAGE LOSS

vs

OSCILLATOR FREQUENCY

2.5

2.25

2

2.5

2.25

2

Inverter Configuration

C

= 100-µF Tantalum

C

= 10-µF Tantalum

= 100-µF Tantalum

IN

OUT

IN

OUT

1.75

1.5

1.25

1

1.5

1.25

1

I

= 100 mA

O

I

= 100 mA

= 50 mA

= 10 mA

O

I

= 50 mA

= 10 mA

O

I

O

0.75

0.5

0.75

0.5

O

I

0.25

0

0.25

0

1

10

100

1

10

100

Oscillator Frequency − kHz

Figure 7

Figure 8

6

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SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

†

TYPICAL CHARACTERISTICS

REFERENCE VOLTAGE CHANGE

vs

REGULATED OUTPUT VOLTAGE

vs

FREE-AIR TEMPERATURE

−4.7

−4.8

100

80

−4.9

−5

60

40

−5.1

20

0

−11.6

−11.8

−12

−20

−40

−60

V

REF

at 0 = 2.500 V

−12.2

−12.4

−12.6

−80

−100

−50

−25

T

0

25

50

75

100

−50

−25

0

25

50

75

100 125

T

A

− Free-Air Temperature − °C

A

Figure 9

Figure 10

VOLTAGE LOSS

vs

OUTPUT CURRENT

2

3.5 V ≤ V

CC

≤ 15 V

1.8 C = C = 100 µF

i

o

1.6

1.4

1.2

1

T

J

= 125°C

T

J

= 25°C

0.8

0.6

0.4

0.2

T

J

= −55°C

0

10 20 30 40 50 60 70 80 90 100

Output Current − mA

Figure 11

†

Data at high and low temperatures are applicable only within the recommended operating free-air temperature range.

7

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SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

PRINCIPLES OF OPERATION

A review of a basic switched-capacitor building block is helpful in understanding the operation of the LT1054. When

the switch shown in Figure 12 is in the left position, capacitor C1 charges to the voltage at V1. The total charge on

C1 is q1 = C1V1. When the switch is moved to the right, C1 is discharged to the voltage at V2. After this discharge

time, the charge on C1 is q2 = C1V2. The charge has been transferred from the source V1 to the output V2. The

amount of charge transferred is shown in equation 1.

Dq + q1 * q2 + C1(V1 * V2)

If the switch is cycled f times per second, the charge transfer per unit time (i.e., current) is as shown in equation 2.

I + f Dq + f C1(1 * V2)

(1)

(2)

To obtain an equivalent resistance for a switched-capacitor network, this equation can be rewritten in terms of voltage

and impedance equivalence as shown in equation 3.

V1 * V2

1ńfC1

V1 * V2

R_EQUIV

I +

+

ǒ

Ǔ

(3)

V1

V2

L

f

R

C1

C2

Figure 12. Switched-Capacitor Building Block

A new variable, R

, is defined as R

= 1 ÷ fC1. The equivalent circuit for the switched-capacitor network is

EQUIV

shown in Figure 13. The LT1054 has the same switching action as the basic switched-capacitor building block. Even

though this simplification does not include finite switch-on resistance and output-voltage ripple, it provides an insight

into how the device operates.

R

EQUIV

V1

V2

C2

R

L

1

fC1

R_EQUIV

+

Figure 13. Switched-Capacitor Equivalent Circuit

These simplified circuits explain voltage loss as a function of oscillator frequency (see Figure 7). As oscillator

frequency is decreased, the output impedance eventually is dominated by the 1/fC1 term, and voltage losses rise.

Voltage losses also rise as oscillator frequency increases. This is caused by internal switching losses that occur due

to some finite charge being lost on each switching cycle. This charge loss per-unit-cycle, when multiplied by the

switching frequency, becomes a current loss. At high frequency, this loss becomes significant and voltage losses

again rise.

The oscillator of the LT1054 is designed to operate in the frequency band where voltage losses are at a minimum.

8

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SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

PRINCIPLES OF OPERATION

Supply voltage V

and then transfers charge to C

frequency. During the time that C is charging, the peak supply current is approximately 2.2 times the output current.

During the time that C is delivering a charge to C

alternately charges C to the input voltage when C is switched in parallel with the input supply

IN IN

CC

when C is switched in parallel with C

. Switching occurs at the oscillator

OUT

IN

OUT

IN

, the supply current drops to approximately 0.2 times the output

IN

OUT

current. An input supply bypass capacitor supplies part of the peak input current drawn by the LT1054 and averages

the current drawn from the supply. A minimum input-supply bypass capacitor of 2 µF, preferably tantalum or some

other low equivalent-series-resistance (ESR) type, is recommended. A larger capacitor is desirable in some cases.

An example of this would be when the actual input supply is connected to the LT1054 through long leads or when

the pulse currents drawn by the LT1054 might affect other circuits through supply coupling.

In addition to being the output terminal, V

is tied to the substrate of the device. Special care must be taken in

OUT

LT1054 circuits to avoid making V

positive with respect to any of the other terminals. For circuits with the output

or from some external positive supply voltage to V

OUT

load connected from V

to V

, an external transistor must

CC

OUT

be added (see Figure 14). This transistor prevents V

from being pulled above GND during startup. Any small

OUT

general-purpose transistor such as a 2N2222 or a 2N2219 device can be used. Resistor R1 should be chosen to

provide enough base drive to the external transistor so that it is saturated under nominal output voltage and maximum

output current conditions.

Ť

Ǔ

b

ǒ

V_OUT

R1 v

I_OUT

(4)

V

IN

1

2

8

7

6

5

FB/SD

CAP+

GND

V

Load

CC

V

OUT

OSC

R1

LT1054

3

4

+

C

V

REF

IN

CAP−

V

OUT

C

OUT

+

Pin numbers shown are for the P package.

Figure 14. Circuit With Load Connected from V

to V

OUT

CC

9

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SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

PRINCIPLES OF OPERATION

The voltage reference (V ) output provides a 2.5-V reference point for use in LT1054-based regulator circuits. The

ref

temperature coefficient (TC) of the reference voltage has been adjusted so that the TC of the regulated output voltage

is near zero. As seen in the typical performance curves, this requires the reference output to have a positive TC. This

nonzero drift is necessary to offset a drift term inherent in the internal reference divider and comparator network tied

to the feedback terminal. The overall result of these drift terms is a regulated output that has a slight positive TC at

output voltages below 5 V and a slight negative TC at output voltages above 5 V. For regulator feedback networks,

reference output current should be limited to approximately 60 µA. V draws approximately 100 µA when shorted

ref

to ground and does not affect the internal reference/regulator. This terminal also can be used as a pullup for LT1054

circuits that require synchronization.

CAP+ is the positive side of input capacitor C and is driven alternately between V

and ground. When driven to

IN

CC

V

, CAP+ sources current from V . When driven to ground, CAP+ sinks current to ground. CAP− is the negative

CC

side of the input capacitor and is driven alternately between ground and V

current to ground. When driven to V

. When driven to ground, CAP− sinks

OUT

, CAP− sources current from C

. In all cases, current flow in the switches

OUT

is unidirectional, as should be expected when using bipolar switches.

OSC can be used to raise or lower the oscillator frequency or to synchronize the device to an external clock. Internally,

OSC is connected to the oscillator timing capacitor (C ≈ 150 pF), which is charged and discharged alternately by

t

current sources of 7 µA, so that the duty cycle is approximately 50%. The LT1054 oscillator is designed to run in

the frequency band where switching losses are minimized. However, the frequency can be raised, lowered, or

synchronized to an external system clock if necessary.

The frequency can be increased by adding an external capacitor (C2 in Figure 15) in the range of 5−20 pF from CAP+

to OSC. This capacitor couples a charge into C at the switch transitions. This shortens the charge and discharge

t

times and raises the oscillator frequency. Synchronization can be accomplished by adding an external pullup resistor

from OSC to V . A 20-kΩ pullup resistor is recommended. An open-collector gate or an npn transistor then can be

ref

used to drive OSC at the external clock frequency as shown in Figure 15.

The frequency can be lowered by adding an external capacitor (C in Figure 15) from OSC to ground. This increases

1

the charge and discharge times, which lowers the oscillator frequency.

C2

1

2

3

4

8

7

6

5

FB/SD

CAP+

GND

V

IN

CC

OSC

LT1054

+

V

REF

C1

CAP−

V

OUT

Pin numbers shown are for the P package.

Figure 15. External-Clock System

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SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

regulation

The feedback/shutdown (FB/SD) terminal has two functions. Pulling FB/SD below the shutdown threshold

(≈ 0.45 V) puts the device into shutdown. In shutdown, the reference/regulator is turned off and switching stops.

The switches are set such that both C and C

are discharged through the output load. Quiescent current

IN

OUT

in shutdown drops to approximately 100 µA. Any open-collector gate can be used to put the LT1054 into

shutdown. For normal (unregulated) operation, the device will restart when the external gate is shut off. In

LT1054 circuits that use the regulation feature, the external resistor divider can provide enough pulldown to keep

the device in shutdown until the output capacitor (C

) has fully discharged. For most applications, where the

OUT

LT1054 is run intermittently, this does not present a problem because the discharge time of the output capacitor

is short compared to the off time of the device. In applications where the device has to start up before the output

capacitor (C

) has fully discharged, a restart pulse must be applied to FB/SD of the LT1054. Using the circuit

OUT

shown in Figure 16, the restart signal can be either a pulse (t > 100 µs) or a logic high. Diode coupling the restart

p

signal into FB/SD allows the output voltage to rise and regulate without overshoot. The resistor divider R3/R4

shown in Figure 16 should be chosen to provide a signal level at FB/SD of 0.7−1.1 V.

FB/SD also is the inverting input of the LT1054 error amplifier and, as such, can be used to obtain a regulated

output voltage.

R3

R4

V

IN

2.2 µF

1

2

3

4

8

7

6

5

+

FB/SD

CAP+

GND

V

CC

OSC

LT1054

C

10-µF

Tantalum

IN

R1

R2

+

V

REF

CAP−

V

OUT

Restart

Shutdown

V

OUT

C1

For example: To get V = −5 V, referenced to the ground terminal of the LT1054

O

Ť

V_OUT

C

|

–5 V

OUT

100-µF

Tantalum

†

R2 + R1

) 1 + 20 kW

) 1

+ 102.6 kW

ǒ Ǔ ǒ Ǔ

V

2.5 V

^REF* 40 mV

* 40 mV

+

2

Where: R1 = 20 kΩ

V

= 2.5 V Nominal

REF

Choose the closest 1% value.

Pin numbers shown are for the P package.

†

Figure 16. Basic Regulation Configuration

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SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

regulation (continued)

The error amplifier of the LT1054 drives the pnp switch to control the voltage across the input capacitor (C ),

IN

which determines the output voltage. When the reference and error amplifier of the LT1054 are used, an external

resistive divider is all that is needed to set the regulated output voltage. Figure 16 shows the basic regulator

configuration and the formula for calculating the appropriate resistor values. R1 should be 20 kΩ or greater

because the reference current is limited to 100 µA. R2 should be in the range of 100 kΩ to 300 kΩ. Frequency

compensation is accomplished by adjusting the ratio of C to C

IN

OUT.

For best results, this ratio should be approximately 1:10. Capacitor C1, required for good load regulation, should

be 0.002 µF for all output voltages.

The functional block diagram shows that the maximum regulated output voltage is limited by the supply voltage.

For the basic configuration, V

 referenced to the ground terminal of the LT1054 must be less than the total

OUT

of the supply voltage minus the voltage loss due to the switches. The voltage loss versus output current due

to the switches can be found in the typical performance curves. Other configurations, such as the negative

doubler, can provide higher voltages at reduced output currents.

capacitor selection

While the exact values of C and C

tantalum, are necessary to minimize voltage losses at high currents. For C , the effect of the ESR of the

capacitor is multiplied by four, because switch currents are approximately two times higher than output current.

are noncritical, good-quality low-ESR capacitors, such as solid

IN

OUT

IN

Losses occur on both the charge and discharge cycle, which means that a capacitor with 1 Ω of ESR for C

IN

has the same effect as increasing the output impedance of the LT1054 by 4 Ω. This represents a significant

increase in the voltage losses. C alternately is charged and discharged at a current approximately equal

OUT

to the output current. The ESR of the capacitor causes a step function to occur in the output ripple at the switch

transitions. This step function degrades the output regulation for changes in output load current and should be

avoided. A technique used to gain both low ESR and reasonable cost is to parallel a smaller tantalum capacitor

with a large aluminum electrolytic capacitor.

output ripple

The peak-to-peak output ripple is determined by the output capacitor and the output current values.

Peak-to-peak output ripple is approximated as:

I_OUT

2fC_OUT

DV +

(5)

Where:

∆V = peak-to-peak ripple

= oscillator frequency

f

OSC

For output capacitors with significant ESR, a second term must be added to account for the voltage step at the

switch transitions. This step is approximately equal to:

ǒ

Ǔǒ Ǔ

2I_OUTESR of C_OUT

(6)

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SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

power dissipation

The power dissipation of any LT1054 circuit must be limited so that the junction temperature of the device does

not exceed the maximum junction-temperature ratings. The total power dissipation is calculated from two

components–the power loss due to voltage drops in the switches, and the power loss due to drive-current

losses. The total power dissipated by the LT1054 is calculated as:

Ť

Ǔ

ǒ

Ǔǒ

Ǔ

(

)

P [ V_CC* V_OUTI_OUT) V_CCI_OUT0.2

(7)

where both V and V are referenced to ground. The power dissipation is equivalent to that of a linear

CC

OUT

regulator. Limited power-handling capability of the LT1054 packages causes limited output-current

requirements, or steps can be taken to dissipate power external to the LT1054 for large input or output

differentials. This is accomplished by placing a resistor in series with C as shown in Figure 17. A portion of

IN

the input voltage is dropped across this resistor without affecting the output regulation. Since switch current is

approximately 2.2 times the output current and the resistor causes a voltage drop when C is both charging

IN

and discharging, the resistor chosen is as shown:

V_X

4.4 I_OUT

R_X+

(8)

Where:

V

≈ V

− [(LT1054 voltage loss)(1.3) + |V

|]

OUT

X

CC

and

I

= maximum required output current

OUT

The factor of 1.3 allows some operating margin for the LT1054.

When using a 12-V to −5-V converter at 100-mA output current, calculate the power dissipation without an

external resistor.

(

|

|)(

)

(

)(

)

P + 12 V * *5 V 100 mA ) 12 V 100 mA 0.2

P + 700 mW ) 240 mW + 940 mW

(9)

V

IN

1

8

7

6

5

FB/SD

CAP+

GND

V

CC

Rx

2

3

4

OSC

LT1054

R1

R2

+

C

V

REF

IN

CAP−

V

OUT

V

OUT

C1

C

OUT

+

Pin numbers shown are for the P package.

Figure 17. Power-Dissipation-Limiting Resistor in Series With C

IN

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SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

power dissipation (continued)

At R

of 130°C/W for a commercial plastic device, a junction temperature rise of 122°C occurs. The device

θJA

exceeds the maximum junction temperature at an ambient temperature of 25°C. To calculate the power

dissipation with an external resistor (R ), determine how much voltage can be dropped across R . The

maximum voltage loss of the LT1054 in the standard regulator configuration at 100 mA output current is 1.6 V.

X

[(

)(

)

|

|]

V_X+ 12 V * 1.6 V 1.3 ) *5 V + 4.9 V

(10)

and

4.9 V

4.4 100 mA

R_X+

+ 11 W

(

)(

)

(11)

The resistor reduces the power dissipated by the LT1054 by (4.9 V)(100 mA) = 490 mW. The total power

dissipated by the LT1054 is equal to (940 mW − 490 mW) = 450 mW. The junction-temperature rise is 58°C.

Although commercial devices are functional up to a junction temperature of 125°C, the specifications are tested

to a junction temperature of 100°C. In this example, this means limiting the ambient temperature to 42°C. To

allow higher ambient temperatures, the thermal resistance numbers for the LT1054 packages represent

worst-case numbers, with no heat sinking and still air. Small clip-on heat sinks can be used to lower the thermal

resistance of the LT1054 package. Airflow in some systems helps to lower the thermal resistance. Wide printed

circuit board traces from the LT1054 leads help remove heat from the device. This is especially true for plastic

packages.

10 V

100 kΩ

1N4002

1

8

7

100-kΩ

V

CC

FB/SD

CAP+

GND

Speed Control

+

5 µF

2

3

OSC

LT1054

−

+

−

6

5

10 µF

V

REF

+

1N5817

4

V

OUT

CAP−

Tach

Motor

NOTE: Motor-Tach is Canon CKT26-T5-3SAE.

Pin numbers shown are for the P package.

Figure 18. Motor-Speed Servo

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SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

1

2

8

7

6

5

V

FB/SD

CAP+

GND

V

CC

IN

+

2 µF

OSC

LT1054

3

4

+

V

REF

10 µF

−V

OUT

CAP−

V

OUT

100 µF

+

Pin numbers shown are for the P package.

Figure 19. Basic Voltage Inverter

1

8

7

V

IN

FB/SD

CAP+

GND

V

CC

+

2 µF

2

OSC

R1

20 kΩ

LT1054

6

5

3

4

+

V

REF

10 µF

R2

CAP−

V

OUT

V

OUT

0.002 µF

+

100 µF

Ť_V

Ť

V_OUT

OUT

ǒ Ǔ

R2 + R1

) 1 + 20 kW

) 1

ǒ Ǔ

V

1.21 V

^REF* 40 mV

2

Pin numbers shown are for the P package.

Figure 20. Basic Voltage Inverter/Regulator

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SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

1

2

3

4

8

7

6

5

+

−

FB/SD

CAP+

GND

V

CC

V

OUT

OSC

+

LT1054

10 µF

V

IN

V

REF

Q

X

2 µF

+

CAP−

V

OUT

R

X

100 µF

+

V

= −3.5 V to −15 V

IN

= 2 V + (LT1054 Voltage Loss) + (Q Saturation Voltage)

OUT

IN

X

V

IN

Pin numbers shown are for the P package.

Figure 21. Negative-Voltage Doubler

V

IN

3.5 V to 15 V

1N4001

+

10 µF

100 µF

V

OUT

8

7

6

5

1

FB/SD

CAP+

GND

V

CC

+

−

2

3

4

2 µF

OSC

LT1054

V

REF

V

= 3.5 V to 15 V

≈ 2 V − (V + 2 V

IN

= LT1054 Voltage Loss

IN

CAP−

V

OUT

V

)

Diode

OUT

L

Pin numbers shown are for the P package.

Figure 22. Positive-Voltage Doubler

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SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

V

IN

3.5 V to 15 V

+

2.2 µF

1

2

3

4

8

7

6

5

1

8

7

6

5

FB/SD

V

CC

FB/SD

CAP+

V

CC

HP5082-2810

2

CAP+ of

LT1054 #1

V

OUT

SET

CAP+

OSC

10 µF

LT1054 #2

+

10 µF

+

LT1054 #1

GND

3

4

GND

V

REF

V

REF

+

20 kΩ

10 µF

R1

40 kΩ

CAP−

V

OUT

CAP−

+

OUT

10 µF

+

10 µF

1N4002

0.002 µF

10 µF

+

R2

500 kΩ

1N4002

V

OUT

≅ 100 mA MAX

I

OUT

1N4002

100 µF

+

V

= 3.5 V to 15 V

IN

MAX ≈ −2 V + [LT1054 Voltage Loss +2 (V

)]

OUT

IN Diode

Ť_V

Ť

) 1

Ť_V

Ť

OUT

R2 + R1

) 1 + R1

ǒ Ǔ

V

1.21 V

^REF* 40 mV

2

Pin numbers shown are for the P package.

Figure 23. 100-mA Regulating Negative Doubler

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SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

V

I

3.5 V to 15 V

1N4001

+

−

+

+V

O

100 µF

+

1

2

8

7

10 µF

FB/SD

V

CC

CAP+

GND

OSC

LT1054

3

4

6

+

V

REF

10 µF

100 µF

5

+

V

OUT

CAP−

1N4001

−

+

V = 3.5 V to 15 V

I

1N4001

−V

O

100 µF

+

+V ≈ 2 V − (V + 2 V

) −V ≈ −2 V + (V + 2 V )

Diode

O

L

IN Diode

L

O

I

L

V

= LT1054 Voltage Loss

Pin numbers shown are for the P package.

Figure 24. Dual-Output Voltage Doubler

V = 5 V

I

+

5 µF

1N914

V

+12 V

O ≈

= 25 mA

I

O

1

2

3

4

8

FB/SD

CAP+

V

CC

+

100 µF

10 µF

1

8

7

6

OSC

FB/SD

V

CC

LT1054 #1

2

CAP− of

LT1054 #1

7

6

+

OSC

GND

V

REF

CAP+

GND

10 µF

LT1054 #2

10 µF

5 µF

5

3

4

2N2219

CAP−

V

REF

OUT

20 kΩ

5

100 µF

V

I

≈ −12 V

= 25 mA

O

+

1 kΩ

CAP−

V

OUT

100 µF

+

Pin numbers shown are for the P package.

Figure 25. 5-V to 12-V Converter

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SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

5 V

10 kΩ

+

Input TTL or

CMOS Low

for On

10 µF

10 kΩ

40 Ω

2N2907

Zero Trim

10 kΩ

Gain Trim

5 kΩ

8

301 kΩ

0.022 µF

1 MΩ

100 kΩ

5 kΩ

2

3

6

5

A2

1/2

LT1013

−

1/2

LT1013

7

1

V

OUT

100 kΩ

10 kΩ

+

350 Ω

A1

4

1 µF

200 kΩ

1

8

7

6

5

V

FB/SD

5 V

CC

2

3

4

CAP+

GND

OSC

LT1054 #1

+

3 kΩ

10 µF

2N2222

V

REF

+

100-µF

Adjust Gain Trim For 3 V Out From

Full-Scale Bridge Output of 24 mV

Tantalum

V

OUT

CAP−

Pin numbers shown are for the P package.

Figure 26. Strain-Gage Bridge Signal Conditioner

19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂꢃ ꢄꢅ

ꢆ ꢇꢈ ꢁ ꢉꢊ ꢋꢌ ꢍꢉ ꢎ ꢏꢎꢉ ꢈ ꢁꢐ ꢑ ꢒ ꢐꢀꢁꢎꢓ ꢋ ꢉꢐ ꢔ ꢒꢋꢑꢁ ꢋ ꢑꢆ

ꢇꢈ ꢁ ꢊ ꢑ ꢋꢓꢕ ꢀ ꢎꢁꢐ ꢑꢆ

SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

V

I

3.5 V to 5.5 V

1

2

3

8

7

6

5

20 kΩ

FB/SD

CAP+

V

CC

OSC

+

LTC1044

1 µF

1N914

(All)

GND

V

REF

1

2

3

8

7

6

5

4

FB/SD

CAP+

V

CC

CAP−

V

OUT

+

5 µF

R1

R2

OSC

125 kΩ

LT1054

+

20 kΩ

10 µF

GND

V

REF

+

1 µF

+

0.002 µF

R2

125 kΩ

V

O

3 kΩ

4

100 µF

CAP−

V

OUT

−

V = 3.5 V to 5.5 V

I

O

V

I

= 5 V

MAX = 50 mA

2N2219

1N914

Ť_V

Ť

) 1

Ť_V

Ť

1N5817

OUT

R2 + R1

) 1 + R1

ǒ Ǔ

V

1.21 V

^REF* 40 mV

2

Pin numbers shown are for the P package.

Figure 27. 3.5-V to 5-V Regulator

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢆꢇ ꢈ ꢁꢉ ꢊꢋꢌꢍꢉ ꢎꢏꢎꢉꢈ ꢁꢐ ꢑ ꢒꢐ ꢀꢁꢎꢓ ꢋ ꢉꢐ ꢔ ꢒꢋ ꢑꢁ ꢋꢑ

ꢇ ꢈꢁ ꢊ ꢑꢋꢓ ꢕ ꢀꢎꢁꢐ ꢑ

SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

12 V

5 µF

+

1

2

3

4

8

7

6

5

1

8

7

6

5

FB/SD

CAP+

V

FB/SD

CAP+

V

CC

HP5082-2810

10 Ω

1/2 W

2

3

4

OSC

R1

39.2 kΩ

+

LT1054 #1

LT1054 #2

10 Ω

1/2 W

10 µF

GND

V

REF

GND

V

REF

0.002 µF

+

20 kΩ

R2

200 kΩ

CAP−

V

OUT

CAP−

V

OUT

+

10 µF

V

I

= −5 V

= 0-200 mA

O

200 µF

Ť_V

Ť

Ť_V

Ť

+

OUT

R2 + R1

) 1 + R1

) 1

ǒ Ǔ

V

1.21 V

^REF* 40 mV

2

Pin numbers shown are for the P package.

Figure 28. Regulating 200-mA +12-V to −5-V Converter

15 V

5 µF

+

11

13

20 kΩ

16

Digital

Input

AD558

14

2.5 V

LT1004-2.5

15

1

2

3

8

7

6

5

12

FB/SD

CAP+

V

CC

20 kΩ

OSC

LT1054

+

GND

V

REF

10 µF

4

V

O

= −V (Programmed)

I

CAP−

V

OUT

100 µF

+

Pin numbers shown are for the P package.

Figure 29. Digitally Programmable Negative Supply

21

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂꢃ ꢄꢅ

ꢆ ꢇꢈ ꢁ ꢉꢊ ꢋꢌ ꢍꢉ ꢎ ꢏꢎꢉ ꢈ ꢁꢐ ꢑ ꢒ ꢐꢀꢁꢎꢓ ꢋ ꢉꢐ ꢔ ꢒꢋꢑꢁ ꢋ ꢑꢆ

ꢇꢈ ꢁ ꢊ ꢑ ꢋꢓꢕ ꢀ ꢎꢁꢐ ꢑꢆ

SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

V = 5 V

I

2 µF

+

50 kΩ

1

2

3

4

8

1N5817

10 µF

FB/SD

CAP+

V

CC

1N5817

7

6

5

V

8 V

O

+

OSC

+

LT1054

10 kΩ

100 µF

0.03 µF

10 kΩ

5 V

1/2

GND

V

REF

5.5 kΩ

10 kΩ

CAP−

V

OUT

−

LT1013

+

2.5 kΩ

0.1 µF

Pin numbers shown are for the P package.

Figure 30. Positive Doubler With Regulation (5-V to 8-V Converter)

V

I

3.5 V to 15 V

2 µF

1

2

3

8

+

FB/SD

CAP+

GND

V

CC

7

6

5

OSC

R1

60 kΩ

LT1054

+

10 µF

V

REF

100 µF

4

+

CAP−

V

OUT

R2

1 MΩ

+

0.002 µF

1N4001

−V

O

V = 3.5 V to 15 V

I

100 µF

V

O

V

L

MAX ≈ 2 V + (V + 2 V )

IN Diode

= LT1054 Voltage Loss

L

+

Ť_V

Ť

Ť_VŤ

) 1 + R1 ) 1

OUT

R2 + R1

ǒ Ǔ

V

1.21 V

^REF* 40 mV

2

Pin numbers shown are for the P package.

Figure 31. Negative Doubler With Regulator

22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

11-Feb-2005

PACKAGING INFORMATION

Orderable Device

LT1054CDW

LT1054CDWR

LT1054CP

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

DW

16

8

40

2000

50

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

SOIC

PDIP

SOIC

PDIP

DW

P

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

Pb-Free

(RoHS)

Call TI

Level-NC-NC-NC

LT1054IDW

LT1054IDWR

LT1054IP

DW

P

16

8

40

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

2000

50

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

Pb-Free

(RoHS)

Call TI

Level-NC-NC-NC

LT1054Y

OBSOLETE XCEPT

Y

0

None

Call TI

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,

including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MPDI001A – JANUARY 1995 – REVISED JUNE 1999

P (R-PDIP-T8)

PLASTIC DUAL-IN-LINE

0.400 (10,60)

0.355 (9,02)

8

5

0.260 (6,60)

0.240 (6,10)

1

4

0.070 (1,78) MAX

0.325 (8,26)

0.300 (7,62)

0.020 (0,51) MIN

0.015 (0,38)

Gage Plane

0.200 (5,08) MAX

Seating Plane

0.010 (0,25) NOM

0.125 (3,18) MIN

0.100 (2,54)

0.021 (0,53)

0.430 (10,92)

MAX

0.010 (0,25)

M

0.015 (0,38)

4040082/D 05/98

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001

For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process

in which TI products or services are used. Information published by TI regarding third-party products or services

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.

Use of such information may require a license from a third party under the patents or other intellectual property

of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction

of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for

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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

product or service voids all express and any implied warranties for the associated TI product or service and

is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	LT1054CP
厂家：	TEXAS INSTRUMENTS
描述：	SWITCHED-CAPACITOR VOLTAGE CONVERTERS WITH REGULATORS 与监管机构的开关电容电压转换器转换器稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管
文件：	总26页 (文件大小：442K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT1054CP [TI]

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