M430F4152_技术文档

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

D

Low Supply-Voltage Range, 1.8 V to 3.6 V

D

Integrated LCD Driver With Contrast

Control for Up to 144 Segments

Basic Timer With Real Time Clock Feature

Brownout detector

On-Chip Comparator for Analog Signal

Compare Function or Slope A/D

10-Bit 200-ksps Analog-to-Digital (A/D)

Converter With Internal Reference,

Sample-and-Hold, Autoscan, and Data

Transfer Controller

Serial Onboard Programming,

No External Programming Voltage Needed

Programmable Code Protection by Security

Fuse

Bootstrap Loader

On-Chip Emulation Module

Family Members Include:

MSP430F4152: 16KB+256B Flash Memory

512B RAM

MSP430F4132: 8KB+256B Flash Memory

512B RAM

Available in 64-Pin QFP Package and

48-Pin QFN Package (See Available

Options)

For Complete Module Descriptions, See

The MSP430x4xx Family User’s Guide,

Literature Number SLAU056

Ultralow Power Consumption

Active Mode: 220 µA at 1 MHz, 2.2 V

Standby Mode: 0.9 µA

Off Mode (RAM Retention): 0.1 µA

Five Power-Saving Modes

Wake-Up From Standby Mode in Less

Than 6 µs

-- Internal Very Low Power,

Low-Frequency Oscillator

16-Bit RISC Architecture,

125-ns Instruction Cycle Time

16-Bit Timer_A With Three

Capture/Compare Registers

16-Bit Timer_A With Five Capture/Compare

Registers

Two Universal Serial Communication

Interfaces (USCIs)

USCI_A0

-- Enhanced UART Supporting

Auto-Baudrate Detection

-- IrDA Encoder and Decoder

-- Synchronous SPI

USCI_B0

D

-- I 2 C

-- Synchronous SPI

Supply Voltage Supervisor/Monitor With

Programmable Level Detection

D

description

The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low power

modes, is optimized to achieve extended battery life in portable measurement applications. The device features

a powerful 16-bit RISC CPU, 16-bit registers, and constant generator that contribute to maximum code

efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less

than 6 µs.

The MSP430F41x2 is a microcontroller configuration with two 16-bit timers, a basic timer with a real--time clock,

a 10-bit A/D converter, a versatile analog comparator, two universal serial communication interfaces, up to 48

I/O pins, and a liquid crystal display driver.

Typical applications for this device include analog and digital sensor systems, remote controls, thermostats,

digital timers, hand-held meters, etc.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range

from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage

because very small parametric changes could cause the device not to meet its published specifications. These devices have limited

built-in ESD protection.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Copyright  2010, Texas Instruments Incorporated

1

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

†

AVAILABLE OPTIONS

PACKAGED DEVICES

‡

T

A

PLASTIC 64-PIN QFP (PM)

PLASTIC 48-PIN QFN (RGZ)

MSP430F4152IPM

MSP430F4132IPM

MSP430F4152IRGZ

MSP430F4132IRGZ

-- 4 0 °C to 85°C

†

‡

For the most current package and ordering information, see the Package Option

Addendum at the end of this document, or see the TI web site at www.ti.com.

Package drawings, thermal data, and symbolization are available at

www.ti.com/packaging.

DEVELOPMENT TOOL SUPPORT

All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging

and programming through easy to use development tools. Recommended hardware options include the

following:

D

Debugging and Programming Interface

-- MSP-FET430UIF (USB)

-- MSP-FET430PIF (Parallel Port)

Debugging and Programming Interface with Target Board

-- MSP-FET430U64A (PM package)

Production Programmer

D

-- MSP-GANG430

2

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

pin designation, MSP430F41x2IPM (QFP)

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

P6.1/UCB0SOMI/UCB0SCL

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P1.5/TA0CLK/CAOUT/S26

P1.6/ACLK/CA0

P1.7/TA0CLK/CAOUT/CA1

P7.6/TA0.2/S25

P5.0/TA1.1/S24

R33/LCDCAP

P6.2/UCB0SIMO/UCB0SDA

2

P6.3/UCB0STE/UCA0CLK/A3/CA5/Ve_REF-/V_REF-

3

P6.4/UCB0CLK/UCA0STE/A4/CA6/Ve_REF+/V_REF+

4

P6.5/UCA0RXD/UCA0SOMI/A5

5

P6.6/UCA0TXD/UCA0SIMO/A6

6

DV_CC

XIN

7

P5.1/R23

64-pin

8

P5.2/R13/LCDREF

P5.3/R03

PM PACKAGE

(TOP VIEW)

XOUT

9

DV_SS

10

11

12

13

14

15

16

P5.4/COM3

P6.7/A7/CA7/SVSIN

P4.7/ADC10CLK/S0

P4.6/S1

P5.5/COM2

P5.6/COM1

P5.7/COM0

P4.5/S2

P3.0/TA1.2/S23

P3.1/TA1.3/S22

P3.2/TA1.4/S21

P4.4/S3

P4.3/S4

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

†

pin designation, MSP430F41x2IRGZ (QFN)

48 47 46 45 44 43 42 41 40 39 38 37

1

2

3

4

5

6

7

8

36

35

34

33

32

31

30

29

28

27

26

25

P6.1

P6.2

DV_CC

XIN

XOUT

P1.1/TA0.0/MCLK/S30

P1.5/TA0CLK/CAOUT/S26

P1.6/ACLK/CA0

P1.7/TA0CLK/CAOUT/CA1

R33/LCDCAP

48-pin

DV_SS

P5.1/R23

RGZ PACKAGE

(TOP VIEW)

P6.7/A7/CA7/SVSIN

P4.7/ADC10CLK/S0

P4.6/S1

P5.2/R13/LCDREF

P5.3/R03

P5.4/COM3

9

10

11

12

P4.5/S2

P5.5/COM2

P4.4/S3

P5.6/COM1

P4.3/S4

P5.7/COM0

13 14 15 16 17 18 19 20 21 22 23 24

†

“Not available” pins in the 48-pin package should be initialized to output direction.

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

functional block diagram

XIN

XOUT

DVCC

DVSS

RAM

AVCC

AVSS

P1.x/P2.x

2x8

P3.x/P4.x

2x8

P5.x/P6.x

2x8

P7.x

1x7

ACLK

Oscillators

FLL+

VLO

Ports

P1/P2

ADC10

USCI A0

UART/

LIN,

Port

P7

Ports

P3/P4

Ports

P5/P6

SMCLK

Flash

10--bit

8 Channels

Autoscan

DTC

IrDA, SPI

2x8 I/O

Interrupt

capability

16kB

8kB

512B

1x7 I/O

2x8 I/O

MCLK

USCI B0

SPI, I2C

CPU

64kB

MAB

incl. 16

Registers

MDB

EEM

Brownout

Protection

LCD_A

144

Segments

1,2,3,4

Mux

Basic

Timer &

Real--

Time

Watchdog

WDT+

Timer_A3

Timer _A5

Comparator

_A+

JTAG

Interface

3 CC

Registers

5 CC

Registers

SVS,

SVM

15--Bit

Clock

S p y --B i --

Wire

RST/NMI

NOTE: The USCI A0 and USCI B0 cannot be used in the 48-pin package options (RGZ).

5

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

Terminal Functions

TERMINAL

NO.

I/O

DESCRIPTION

NAME

64

48

General-purpose digital I/O pin

I/O Timer0_A3, capture: CCI0A input, compare: Out0 output

LCD segment output

P1.0/TA0.0/S31

53

52

51

50

49

48

47

46

37

36

--

General-purpose digital I/O pin

Timer0_A3, capture: CCI0B input

MCLK signal output

LCD segment output

P1.1/TA0.0/

MCLK/S30

I/O

General-purpose digital I/O pin

I/O Timer0_A3, capture: CCI1A input, compare: Out1 output

LCD segment output

P1.2/TA0.1/S29

General-purpose digital I/O pin

Timer1_A5, capture: CCI0B input

SVS comparator output

LCD segment output

P1.3/TA1.0/

SVSOUT/S28

--

I/O

General-purpose digital I/O pin/

I/O Timer1_A5, capture: CCI0A input, compare: Out0 output

LCD segment output

P1.4/TA1.0/S27

--

General-purpose digital I/O pin

Timer0_A3, clock signal TACLK input

Comparator_A output

LCD segment output

P1.5/TA0CLK/

CAOUT/S26

35

34

33

I/O

General-purpose digital I/O pin

I/O Comparator_A input 0

ACLK signal output

P1.6/ACLK/CA0

General-purpose digital I/O pin

Timer0_A3, clock signal TACLK input

Comparator_A output

Comparator_A input 1

P1.7/TA0CLK

CAOUT/CA1

I/O

General-purpose digital I/O pin

I/O Timer1_A5, compare: Out1 Output

LCD segment output

P2.0/TA1.1/S15

P2.1/TA1.2/S14

P2.2/TA1.3/S13

P2.3/TA1.4/S12

27

26

25

24

23

22

21

20

General-purpose digital I/O pin

I/O Timer1_A5, compare: Out2 Output

LCD segment output

General-purpose digital I/O pin

I/O Timer1_A5, compare: Out3 Output

LCD segment output

General-purpose digital I/O pin

I/O Timer1_A5, compare: Out4 output

LCD segment output

General-purpose digital I/O pin

P2.4/S11

P2.5/S10

P2.6/S9

P2.7/S8

23

22

21

20

19

18

17

16

I/O

LCD segment output

General-purpose digital I/O pin

LCD segment output

I/O

General-purpose digital I/O pin

LCD segment output

I/O

General-purpose digital I/O pin

LCD segment output

I/O

6

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

Terminal Functions (continued)

TERMINAL

NO.

I/O

DESCRIPTION

NAME

64

48

General-purpose digital I/O pin

I/O Timer1_A5, capture: CCI2A input, compare: Out2 output

LCD segment output

P3.0/TA1.2/S23

P3.1/TA1.3/S22

P3.2/TA1.4/S21

35

--

General-purpose digital I/O pin

I/O Timer1_A5, capture: CCI3A input, compare: Out3 output

LCD segment output

34

33

General-purpose digital I/O pin

I/O Timer1_A5, capture: CCI4A input, compare: Out4 output

LCD segment output

General-purpose digital I/O pin

P3.3/TA0.0/

Timer0_A3, compare: Out0 output

32

31

--

I/O

TA1CLK/S20

Timer1_A5, clock signal TACLK input

LCD segment output

General-purpose digital I/O pin

I/O Comparator_A output

LCD segment output

P3.4/CAOUT/S19

24

General-purpose digital I/O pin

P3.5/S18

P3.6/S17

P3.7/S16

P4.0/S7

P4.1/S6

P4.2/S5

P4.3/S4

P4.4/S3

P4.5/S2

P4.6/S1

30

29

28

19

18

17

16

15

14

13

--

I/O

LCD segment output

General-purpose digital I/O pin

LCD segment output

--

I/O

General-purpose digital I/O pin

LCD segment output

--

I/O

General-purpose digital I/O pin

LCD segment output

15

14

13

12

11

10

9

I/O

General-purpose digital I/O pin

LCD segment output

I/O

General-purpose digital I/O pin

LCD segment output

I/O

General-purpose digital I/O pin

LCD segment output

I/O

General-purpose digital I/O pin

LCD segment output

I/O

General-purpose digital I/O pin

LCD segment output

I/O

General-purpose digital I/O pin

LCD segment output

I/O

General-purpose digital I/O pin

I/O ADC10, conversion clock

LCD segment output

P4.7/ADC10CLK/

S0

12

44

8

--

General-purpose digital I/O pin

I/O Timer1_A5, capture: CCI1A input, compare: Out1 output

LCD segment output

P5.0/TA1.1/S24

Capacitor connection for LCD charge pump

I/O

LCDCAP/R33

P5.1/R23

43

42

32

31

input port of the most positive analog LCD level (V4)

General-purpose digital I/O pin

I/O

input port of the second most positive analog LCD level (V3)

General-purpose digital I/O pin

P5.2/LCDREF/

R13

41

30

I/O External LCD reference voltage input

input port of the third most positive analog LCD level (V3 or V2)

7

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

Terminal Functions (continued)

TERMINAL

NAME

NO.

I/O

DESCRIPTION

64

48

General-purpose digital I/O pin

P5.3/R03

40

29

28

27

26

25

I/O

input port of the fourth most positive analog LCD level (V1)

General-purpose digital I/O pin

common output, COM0--3 are used for LCD backplanes

P5.4/COM3

P5.5/COM2

P5.6/COM1

P5.7/COM0

39

38

37

36

General-purpose digital I/O pin

common output, COM0--3 are used for LCD backplanes

General-purpose digital I/O pin

common output, COM0--3 are used for LCD backplanes

General-purpose digital I/O pin

common output, COM0--3 are used for LCD backplanes

General-purpose digital I/O pin

†

P6.0/TA1.2/A2 /

CA4

Timer1_A5, compare: Out2 output

63

47

I/O

†

ADC10 analog input A2

Comparator_A input 4

P6.1/

General-purpose digital I/O pin

2

†

UCB0SOMI /

1

2

1

2

I/O

2

†

USCI B0 slave out/master in in SPI mode, SCL I C clock in I C mode

†

UCB0SCL

P6.2/

General-purpose digital I/O pin

†

UCB0SIMO /

2

†

USCI B0 slave in/master out in SPI mode, SDA I C data in I C mode

†

UCB0SDA

General-purpose digital I/O pin

P6.3/UCB0STE/

UCA0CLK/A3/

USCI B0 slave transmit enable/USCI A0 clock input/output

ADC10 analog input A3 / negative reference

Comparator_A input 5

3

4

--

I/O

CA5/V

/V

eref-- ref--

General-purpose digital I/O pin

P6.4/UCB0CLK/

UCA0STE/A4/

USCI B0 clock input/output, USCI A0 slave transmit enable

ADC10 analog input A4/ positive reference

Comparator_A input 6

CA6/V

/V

eref+ ref+

General-purpose digital I/O pin

I/O USCI A0 receive data input in UART mode, slave data out/master in in SPI mode

ADC10 analog input A5

P6.5/UCA0RXD/

UCA0SOMI/A5

5

6

--

General-purpose digital I/O pin

I/O USCI A0 transmit data output in UART mode, slave data in/master out SPI mode

ADC10 analog input A6

P6.6/UCA0TXD/

UCA0SIMO/A6

General-purpose digital I/O pin

P6.7/A7/CA7/

SVSIN

ADC10 analog input A7

11

54

7

I/O

Comparator_A input 7

SVS input

P7.0/TDO/TDI/

S32

38

I/O General-purpose digital I/O pin

JTAG test data output terminal or test data input in programming an test

LCD segment output

P7.1/TDI/TCLK/

S33

55

56

39

40

I/O General-purpose digital I/O pin

JTAG test data input or test clock input in programming an test

LCD segment output

P7.2/TMS/S34

I/O General-purpose digital I/O pin

JTAG test mode select, input terminal for device programming and test

LCD segment output

†

64-pin package devices only

8

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

Terminal Functions (continued)

TERMINAL

NO.

I/O

DESCRIPTION

NAME

64

48

P7.3/TCK/S35

57

41

I/O General-purpose digital I/O pin

Test clock input for device programming and test

LCD segment output

General-purpose digital I/O pin

Timer1_A5, capture: CCI4B input, compare: Out4 output

ADC10 analog input A0

P7.4/TA1.4/

A0/CA2

60

44

I/O

Comparator_A input 2

General-purpose digital I/O pin

Timer1_A5, capture: CCI3B input, compare: Out3 output

ADC10 analog input A1

P7.5/TA1.3/

A1/CA3

61

45

--

Comparator_A input 3

General-purpose digital I/O pin

I/O Timer0_A3, capture: CCI2A input, compare: Out2 output

LCD segment output

P7.6/TA0.2/S25

AV

64

62

7

48

46

3

Analog supply voltage, positive terminal

CC

SS

Analog supply voltage, negative terminal

DV

Digital supply voltage, positive terminal. Supplies all digital parts.

Digital supply voltage, negative terminal. Supplies all digital parts.

CC

SS

10

9

6

XOUT

XIN

5

O

I

Output port for crystal oscillator XT1. Standard or watch crystals can be connected.

Input port for crystal oscillator XT1. Standard or watch crystals can be connected.

8

4

RST/NMI/

SBWTDIO

58

42

I

Reset or nonmaskable interrupt input

Spy-Bi-Wire test data input/output during programming and test

TEST/SBWTCLK

Thermal Pad

59

43

I

Selects test mode for JTAG pins on Port7. The device protection fuse is connected to TEST.

NA

NA QFN package pad (RGZ package only). Connection to DV is recommended.

SS

9

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

short-form description

CPU

Program Counter

Stack Pointer

PC/R0

The MSP430 CPU has a 16-bit RISC architecture

that is highly transparent to the application. All

operations, other than program-flow instructions,

are performed as register operations in

conjunction with seven addressing modes for

source operand and four addressing modes for

destination operand.

SP/R1

Status Register

SR/CG1/R2

Constant Generator

CG2/R3

R4

General-Purpose Register

The CPU is integrated with 16 registers that

provide reduced instruction execution time. The

register-to-register operation execution time is

one cycle of the CPU clock.

R5

R6

R7

Four of the registers, R0 to R3, are dedicated as

program counter, stack pointer, status register,

and constant generator, respectively. The

remaining registers are general-purpose

registers.

R8

R9

Peripherals are connected to the CPU using data,

address, and control buses and can be handled

with all instructions.

R10

R11

instruction set

R12

R13

The instruction set consists of 51 instructions with

three formats and seven address modes. Each

instruction can operate on word and byte data.

Table 1 shows examples of the three types of

instruction formats; Table 2 shows the address

modes.

R14

R15

Table 1. Instruction Word Formats

Dual operands, source-destination

Single operands, destination only

Relative jump, un/conditional

e.g., ADD R4,R5

R4 + R5 ------> R5

e.g., CALL

e.g., JNE

R8

PC ---->(TOS), R8----> PC

Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

ADDRESS MODE

Register

S

D

SYNTAX

MOV Rs,Rd

EXAMPLE

MOV R10,R11

MOV 2(R5),6(R6)

OPERATION

F

R10 —> R11

Indexed

MOV X(Rn),Y(Rm)

MOV EDE,TONI

MOV & MEM, & TCDAT

MOV @Rn,Y(Rm)

M(2+R5) —> M(6+R6)

M(EDE) —> M(TONI)

M(MEM) —> M(TCDAT)

M(R10) —> M(Tab+R6)

Symbolic (PC relative)

Absolute

Indirect

MOV @R10,Tab(R6)

MOV @R10+,R11

MOV #45,TONI

Indirect

autoincrement

M(R10) —> R11

R10 + 2 —> R10

F

MOV @Rn+,Rm

MOV #X,TONI

Immediate

F

#45 —> M(TONI)

NOTE: S = source, D = destination

10

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

operating modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt

event can wake up the device from any of the five low-power modes, service the request, and restore back to

the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

D

Active mode (AM)

-- All clocks are active

D

Low-power mode 0 (LPM0)

-- CPU is disabled

-- ACLK and SMCLK remain active

-- FLL+ loop control remains active

Low-power mode 1 (LPM1)

D

-- CPU is disabled

-- ACLK and SMCLK remain active

-- FLL+ loop control is disabled

Low-power mode 2 (LPM2)

-- CPU is disabled

-- MCLK, FLL+ loop control, and DCOCLK are disabled

-- DCO’s dc generator remains enabled

-- ACLK remains active

D

Low-power mode 3 (LPM3)

-- CPU is disabled

-- MCLK, FLL+ loop control, and DCOCLK are disabled

-- DCO’s dc generator is disabled

-- ACLK remains active

Low-power mode 4 (LPM4)

-- CPU is disabled

-- ACLK is disabled

-- MCLK, FLL+ loop control, and DCOCLK are disabled

-- DCO’s dc generator is disabled

-- Crystal oscillator is stopped

11

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0.

The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

If the reset vector (located at address 0xFFFE) contains 0xFFFF (e.g., flash is not programmed), the CPU goes

into LPM4 immediately after power-up.

WORD

ADDRESS

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT

PRIORITY

Power-Up

External Reset

PORIFG

RSTIFG

WDTIFG

KEYV

Watchdog

Reset

0xFFFE

15, highest

Flash Memory

PC Out--of--Range (see Note 4)

(see Note 1)

NMI

NMIIFG (see Notes 1 and 3)

OFIFG (see Notes 1 and 3)

ACCVIFG (see Notes 1, 2, and 4)

(Non)maskable

Oscillator Fault

0xFFFC

14

Flash Memory Access Violation

Timer_A5

TA1CCR0 CCIFG0 (see Note 2)

Maskable

0xFFFA

0xFFF8

13

12

TA1CCR1 to TACCR4 CCIFGs,

and TAIFG (see Notes 1 and 2)

Timer_A5

Maskable

Comparator_A+

CAIFG

Maskable

0xFFF6

0xFFF4

11

10

Watchdog Timer+

WDTIFG

UCA0RXIFG (see Note 1),

UCB0RXIFG (SPI mode), or

UCB0STAT UCALIFG, UCNACKIFG, UCSTTIFG,

UCSTPIFG (I2C mode)

USCI_A0/B0 Receive

USCI_A0/B0 Transmit

Maskable

0xFFF2

9

(see Note 1)

UCA0TXIFG (see Note 1),

UCB0TXIFG (SPI mode), or

UCB0RXIFG and UCB0TXIFG (I2C mode)

(see Note 1)

Maskable

0xFFF0

8

ADC10

ADC10IFG (see Note 2)

Maskable

0xFFEE

0xFFEC

7

6

Timer_A3

TACCR0 CCIFG0 (see Note 2)

TACCR1 CCIFG1 and TACCR2 CCIFG2,

TAIFG (see Notes 1 and 2)

Timer_A3

Maskable

0xFFEA

5

I/O Port P1 (Eight Flags)

P1IFG.0 to P1IFG.7 (see Notes 1 and 2)

0xFFE8

0xFFE6

0xFFE4

0xFFE2

0xFFE0

4

3

2

1

I/O Port P2 (Eight Flags)

Basic Timer1/RTC

P2IFG.0 to P2IFG.7 (see Notes 1 and 2)

BTIFG

Maskable

0, lowest

NOTES: 1. Multiple source flags

2. Interrupt flags are located in the module.

3. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).

(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

4. Access and key violations, KEYV and ACCVIFG.

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

special function registers

Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits

not allocated to a functional purpose are not physically present in the device. This arrangement provides simple

software access.

interrupt enable 1 and 2

Address

00h

7

6

5

4

3

2

1

0

ACCVIE

rw--0

NMIIE

rw--0

OFIE

rw--0

WDTIE

rw--0

WDTIE

Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog

timer is configured in interval timer mode.

OFIE

Oscillator fault enable

NMIIE

ACCVIE

(Non)maskable interrupt enable

Flash access violation interrupt enable

Address

01h

7

6

5

4

3

2

1

0

BTIE

rw--0

UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE

rw--0 rw--0 rw--0 rw--0

UCA0RXIE

UCA0TXIE

UCB0RXIE

UCB0TXIE

BTIE

USCI_A0 receive interrupt enable

USCI_A0 transmit interrupt enable

USCI_B0 receive interrupt enable

USCI_B0 transmit interrupt enable

Basic timer interrupt enable

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

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interrupt flag register 1 and 2

Address

02h

7

6

5

4

3

2

1

0

NMIIFG

rw--0

RSTIFG

rw--(0)

PORIFG

rw--(1)

OFIFG

rw--1

WDTIFG

rw--(0)

WDTIFG

Set on watchdog timer overflow (in watchdog mode) or security key violation.

Reset on V_CCpower-up or a reset condition at RST/NMI pin in reset mode.

OFIFG

Flag set on oscillator fault

RSTIFG

External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset

on V_CCpower-up.

PORIFG

NMIIFG

Power-on interrupt flag. Set on V_CCpower--up.

Set via RST/NMI-pin

Address

03h

7

6

5

4

3

2

1

0

UCB0

TXIFG

UCB0

RXIFG

UCA0

TXIFG

UCA0

RXIFG

BTIFG

rw--0

rw--1

rw--0

rw--1

rw--0

UCA0RXIFG USCI_A0 receive interrupt flag

UCA0TXIFG USCI_A0 transmit interrupt flag

UCB0RXIFG USCI_B0 receive interrupt flag

UCB0TXIFG

BTIFG

USCI_B0 transmit interrupt flag

Basic Timer1 interrupt flag

Legend

rw:

rw-0,1:

rw-(0,1):

Bit can be read and written.

Bit can be read and written. It is Reset or set by PUC.

Bit can be read and written. It is Reset or set by POR.

SFR bit is not present in device

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

memory organization

MSP430F4152

MSP430F4132

Memory

Main: interrupt vector

Main: code memory

Size

Flash

16KB

0FFFFh -- 0FFE0h

0FFFFh -- 0C000h

8KB

0FFFFh -- 0FFE0h

0FFFFh -- 0E000h

Information memory

Boot memory

RAM

Size

256 Byte

Flash

010FFh -- 01000h

Size

ROM

1KB

0FFFh -- 0C00h

1KB

0FFFh -- 0C00h

Size

512B

03FFh -- 0200h

512B

03FFh -- 0200h

Peripherals

16-bit

8-bit

8-bit SFR

01FFh -- 0100h

0FFh -- 010h

0Fh -- 00h

01FFh -- 0100h

0FFh -- 010h

0Fh -- 00h

bootstrap loader (BSL)

The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access

to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the

features of the BSL and its implementation, see the MSP430 Memory Programming User’s Guide, literature

number SLAU265.

BSL FUNCTION

Data transmit

Data receive

PM PACKAGE PINS

53 -- P1.0

RGZ PACKAGE PINS

37 -- P1.0

52 -- P1.1

36 -- P1.1

flash memory (Flash)

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The

CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

D

Flash memory has n segments of main memory and four segments of information memory (A to D) of

64 bytes each. Each segment in main memory is 512 bytes in size.

D

Segments 0 to n may be erased in one step, or each segment may be individually erased.

Segments A to D can be erased individually, or as a group with segments 0 to n.

Segments A to D are also called information memory.

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all

instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number

SLAU056.

oscillator and system clock

The clock system in the MSP430F41x2 is supported by the FLL+ module that includes support for a 32768-Hz

watch crystal oscillator, an internal very low-power low--frequency oscillator, an internal digitally-controlled

oscillator (DCO), and an 8-MHz high-frequency crystal oscillator (XT1). The FLL+ clock module is designed to

meet the requirements of both low system cost and low power consumption. The FLL+ features a digital

frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency

to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock

source and stabilizes in less than 6 µs. The FLL+ module provides the following clock signals:

D

Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or a very

low-power LF oscillator

D

Main clock (MCLK), the system clock used by the CPU

Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules

ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8

brownout, supply voltage supervisor

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on

and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user

selectable level and supports both supply voltage supervision (the device is automatically reset) and supply

voltage monitoring (SVM, the device is not automatically reset).

The CPU begins code execution after the brownout circuit releases the device reset. However, V_CCmay not

have ramped to V_CC(min)at that time. The user must insure the default FLL+ settings are not changed until V_CC

reaches V_CC(min). If desired, the SVS circuit can be used to determine when V_CCreaches V_CC(min)

.

digital I/O

There are seven 8-bit I/O ports implemented—ports P1 through P7. Port P7 is a 7-bit I/O port.

D

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt conditions is possible.

Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.

Read/write access to port-control registers is supported by all instructions.

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

watchdog timer (WDT+)

The primary function of the WDT+ module is to perform a controlled system restart after a software problem

occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed

in an application, the module can be configured as an interval timer and can generate interrupts at selected time

intervals.

Basic Timer1 and Real-Time Clock (RTC)

The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both

timers can be read and written by software. The Basic Timer1 is extended to provide an integrated real-time

clock (RTC). An internal calendar compensates for month with less than 31 days and includes leap year

correction.

LCD_A driver with regulated charge pump

The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A

controller has dedicated data memory to hold segment drive information. Common and segment signals are

generated as defined by the mode. Static, 2--MUX, 3--MUX, and 4--MUX LCDs are supported by this peripheral.

The module can provide a LCD voltage independent of the supply voltage via an integrated charge pump.

Furthermore it is possible to control the level of the LCD voltage and thus contrast in software.

Timer0_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple

capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

TIMER_A3 SIGNAL CONNECTIONS

MODULE

OUTPUT

SIGNAL

INPUT PIN NUMBER

OUTPUT PIN NUMBER

DEVICE INPUT

SIGNAL

MODULE

INPUT NAME

MODULE

BLOCK

PM

RGZ

PM

RGZ

48 -- P1.5

46 -- P1.7

35 -- P1.5

33 -- P1.7

TA0CLK

TACLK

ACLK

SMCLK

TA0CLK

TA0.0

ACLK

SMCLK

TACLK

CCI0A

CCI0B

GND

Timer

NA

48 -- P1.5

53 -- P1.0

52 -- P1.1

35 -- P1.5

37 -- P1.0

36 -- P1.1

53 -- P1.0

32 -- P3.3

37 -- P1.0

--

TA0.0

CCR0

CCR1

CCR2

TA0

TA1

TA2

DV

SS

CC

V

CC

51 -- P1.2

45 -- P7.6

--

TA0.1

CCI1A

CCI1B

GND

51 -- P1.2

CAOUT (internal)

ADC10 (internal)

--

DV

SS

CC

V

CC

TA0.2

CCI2A

CCI2B

GND

45 -- P7.6

ACLK (internal)

DV

SS

CC

V

CC

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

Timer1_A5

Timer_A5 is a 16-bit timer/counter with five capture/compare registers. Timer_A5 can support multiple

capture/compares, PWM outputs, and interval timing. Timer_A5 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

TIMER_A5 SIGNAL CONNECTIONS

MODULE

OUTPUT

SIGNAL

INPUT PIN NUMBER

OUTPUT PIN NUMBER

DEVICE INPUT

SIGNAL

MODULE

INPUT NAME

MODULE

BLOCK

PM

RGZ

PM

RGZ

32 -- P3.3

--

TA1CLK

ACLK

TACLK

ACLK

Timer

CCR0

CCR1

CCR2

CCR3

CCR4

NA

TA0

TA1

TA2

TA3

TA4

SMCLK

TA1CLK

TA1.0

SMCLK

TACLK

CCI0A

CCI0B

GND

32 -- P3.3

49 -- P1.4

50 -- P1.3

--

49 -- P1.4

--

TA1.0

ADC10 (internal)

DV

SS

CC

V

CC

44 -- P5.0

35 -- P3.0

--

TA1.1

CCI1A

CCI1B

GND

44 -- P5.0

27 -- P2.0

--

CAOUT (internal)

23 -- P2.0

DV

ADC10 (internal)

SS

CC

V

CC

TA1.2

CCI2A

CCI2B

GND

35 -- P3.0

26 -- P2.1

63 -- P6.0

--

ACLK (internal)

22 -- P2.1

47 -- P6.0

DV

SS

CC

V

CC

34 -- P3.1

61 -- P7.5

--

TA1.3

CCI3A

CCI3B

GND

34 -- P3.1

25 -- P2.2

61 -- P7.5

--

45 -- P7.5

21 -- P2.2

45 -- P7.5

DV

SS

CC

V

CC

33 -- P3.2

60 -- P7.4

--

TA1.4

CCI4A

CCI4B

GND

33 -- P3.2

24 -- P2.3

60 -- P7.4

--

44 -- P7.4

20 -- P2.3

44 -- P7.4

DV

SS

CC

V

CC

universal serial communication interface (USCI) (USCI_A0, USCI_B0)

The USCI module is used for serial data communication. The USCI module supports synchronous

communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols like UART,

enhanced UART with automatic baudrate detection (LIN), and IrDA.

USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.

USCI_B0 provides support for SPI (3 or 4 pin) and I2C.

Comparator_A+

The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,

battery-voltage supervision, and monitoring of external analog signals.

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

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ADC10

The ADC10 module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR

core, sample select control, reference generator, and data transfer controller (DTC) for automatic conversion

result handling, allowing ADC samples to be converted and stored without any CPU intervention.

peripheral file map

PERIPHERALS WITH WORD ACCESS

Watchdog

Timer0_A3

Watchdog timer control

WDTCTL

0120h

Capture/compare register 2

Capture/compare register 1

Capture/compare register 0

Timer_A register

Capture/compare control 2

Capture/compare control 1

Capture/compare control 0

Timer_A control

TA0CCR2

TA0CCR1

TA0CCR0

TA0R

TA0CCTL2

TA0CCTL1

TA0CCTL0

TA0CTL

0176h

0174h

0172h

0170h

0166h

0164h

0162h

0160h

012Eh

Timer_A interrupt vector

TA0IV

Timer1_A5

Capture/compare register 4

Capture/compare register 3

Capture/compare register 2

Capture/compare register 1

Capture/compare register 0

Timer_A register

Capture/compare control 4

Capture/compare control 3

Capture/compare control 2

Capture/compare control 1

Capture/compare control 0

Timer_A control

TA1CCR4

TA1CCR3

TA1CCR2

TA1CCR1

TA1CCR0

TA1R

TA1CCTL4

TA1CCTL3

TA1CCTL2

TA1CCTL1

TA1CCTL0

TA1CTL

019A

0198

0196h

0194h

0192h

0190h

018A

0188

0186h

0184h

0182h

0180h

011Eh

012Ch

012Ah

0128h

Timer_A interrupt vector

Flash control 3

Flash control 2

TA1IV

FCTL3

FCTL2

FCTL1

Flash

Flash control 1

ADC10

ADC data transfer start address

ADC memory

ADC control register 1

ADC control register 0

ADC analog enable 0

ADC analog enable 1

ADC data transfer control register 1

ADC data transfer control register 0

ADC10SA

01BCh

01B4h

01B2h

01B0h

004Ah

004Bh

0049h

0048h

ADC10MEM

ADC10CTL1

ADC10CTL0

ADC10AE0

ADC10AE1

ADC10DTC1

ADC10DTC0

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

peripheral file map (continued)

PERIPHERALS WITH BYTE ACCESS

LCD_A

LCD Voltage Control 1

LCD Voltage Control 0

LCD Voltage Port Control 1

LCD Voltage Port Control 0

LCD memory 20

:

LCDAVCTL1

LCDAVCTL0

LCDAPCTL1

LCDAPCTL0

LCDM20

:

0AFh

0AEh

0ADh

0ACh

0A4h

:

LCD memory 16

LCD memory 15

:

LCDM16

LCDM15

:

0A0h

09Fh

:

LCD memory 1

LCD control and mode

LCDM1

LCDACTL

091h

090h

USCI A0/B0

USCI A0 auto baud rate control

USCI A0 transmit buffer

USCI A0 receive buffer

USCI A0 status

USCI A0 modulation control

USCI A0 baud rate control 1

USCI A0 baud rate control 0

USCI A0 control 1

UCA0ABCTL

UCA0TXBUF

UCA0RXBUF

UCA0STAT

UCA0MCTL

UCA0BR1

UCA0BR0

UCA0CTL1

UCA0CTL0

UCA0IRRCTL

UCA0IRTCTL

UCB0TXBUF

UCB0RXBUF

UCB0STAT

UCB0CIE

UCB0BR1

UCB0BR0

UCB0CTL1

UCB0CTL0

UCB0SA

UCB0OA

CAPD

CACTL2

CACTL1

0x005D

0x0067

0x0066

0x0065

0x0064

0x0063

0x0062

0x0061

0x0060

0x005F

0x005E

0x006F

0x006E

0x006D

0x006C

0x006B

0x006A

0x0069

0x0068

0x011A

0x0118

05Bh

USCI A0 control 0

USCI A0 IrDA receive control

USCI A0 IrDA transmit control

USCI B0 transmit buffer

USCI B0 receive buffer

USCI B0 status

USCI B0 I2C Interrupt enable

USCI B0 baud rate control 1

USCI B0 baud rate control 0

USCI B0 control 1

USCI B0 control 0

USCI B0 I2C slave address

USCI B0 I2C own address

Comparator_A port disable

Comparator_A control2

Comparator_A control1

Comparator_A+

05Ah

059h

Brownout, SVS

FLL+ Clock

SVS control register (Reset by brownout signal) SVSCTL

056h

FLL+ Control 2

FLL+ Control 1

FLL_CTL2

FLL_CTL1

055h

054h

FLL+ Control 0

FLL_CTL0

SCFQCTL

SCFI1

053h

052h

051h

050h

System clock frequency control

System clock frequency integrator

SCFI0

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

peripheral file map (continued)

PERIPHERALS WITH BYTE ACCESS

RTC

(Basic Timer1)

Real Time Clock Year High Byte

RTCYEARH

RTCYEARL

RTCMON

RTCDAY

BTCNT2

04Fh

04Eh

04Dh

04Ch

047h

046h

045h

Real Time Clock Year Low Byte

Real Time Clock Month

Real Time Clock Day of Month

Basic Timer1 Counter

Real Time Counter 4

BTCNT1

RTCNT4

(Real Time Clock Day of Week)

Real Time Counter 3

(Real Time Clock Hour)

Real Time Counter 2

(Real Time Clock Minute)

Real Time Counter 1

(RTCDOW)

RTCNT3

(RTCHOUR)

RTCNT2

(RTCMIN)

RTCNT1

044h

043h

042h

(Real Time Clock Second)

Real Time Clock Control

Basic Timer1 Control

(RTCSEC)

RTCCTL

BTCTL

041h

040h

Port P7

Port P6

Port P5

Port P4

Port P3

Port P2

Port P7 selection

Port P7 direction

Port P7 output

P7SEL

P7DIR

P7OUT

P7IN

03Bh

03Ah

039h

038h

037h

036h

035h

034h

033h

032h

031h

030h

01Fh

01Eh

01Dh

01Ch

01Bh

01Ah

019h

018h

02Eh

02Dh

02Ch

02Bh

02Ah

029h

028h

Port P7 input

Port P6 selection

Port P6 direction

Port P6 output

P6SEL

P6DIR

P6OUT

P6IN

Port P6 input

Port P5 selection

Port P5 direction

Port P5 output

P5SEL

P5DIR

P5OUT

P5IN

Port P5 input

Port P4 selection

Port P4 direction

Port P4 output

P4SEL

P4DIR

P4OUT

P4IN

Port P4 input

Port P3 selection

Port P3 direction

Port P3 output

P3SEL

P3DIR

P3OUT

P3IN

Port P3 input

Port P2 selection

Port P2 interrupt enable

Port P2 interrupt-edge select

Port P2 interrupt flag

Port P2 direction

Port P2 output

P2SEL

P2IE

P2IES

P2IFG

P2DIR

P2OUT

P2IN

Port P2 input

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

peripheral file map (continued)

PERIPHERALS WITH BYTE ACCESS (CONTINUED)

Port P1

Port P1 selection register

Port P1 interrupt enable

Port P1 interrupt-edge select

Port P1 interrupt flag

Port P1 direction

P1SEL

P1IE

026h

025h

024h

023h

022h

021h

020h

P1IES

P1IFG

P1DIR

P1OUT

P1IN

Port P1 output

Port P1 input

Special functions SFR interrupt flag 2

SFR interrupt flag 1

IFG2

IFG1

IE2

003h

002h

001h

000h

SFR interrupt enable 2

SFR interrupt enable 1

IE1

22

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

absolute maximum ratings over operating free-air temperature (unless otherwise noted)^†

Voltage applied at V_CCto V_SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4.1 V

Voltage applied to any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to V_CC+ 0.3 V

Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA

Storage temperature, T_stg

:

Unprogrammed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --55°C to 150°C

Programmed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --55°C to 85°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltages referenced to V

The JTAG fuse-blow voltage, V , is allowed to exceed the absolute maximum rating. The voltage is

SS.

FB

applied to the TEST pin when blowing the JTAG fuse.

recommended operating conditions

MIN

1.8

2.2

0

NOM

MAX

3.6

0

UNIT

V

Supply voltage during program execution, V (AV = DV = V )

CC

Supply voltage during flash memory programming, V (AV = DV = V )

CC

V

CC

Supply voltage, V (AV = DV = V

)

SS

V

SS

Operating free-air temperature range, T

-- 4 0

85

°C

A

LF selected,

XTS_FLL = 0

Watch crystal

Ceramic resonator

Crystal

32.768

kHz

MHz

XT1 selected,

XTS_FLL = 1

LFXT1 crystal frequency, f

(see Note 1)

(LFXT1)

0.45

1

6

XT1 selected,

XTS_FLL = 1

V

= 1.8 V

= 3.0 V

dc

4.15

8

CC

Processor frequency (signal MCLK), f

MHz

(System)

NOTES: 1. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.

f_System(MHz)

8 MHz

Supply voltage range,

MSP430F41x2, during

program execution

Supply voltage range, MSP430F41x2,

during flash memory programming

4.15 MHz

1.8

2.2

3.0

3.6

Supply Voltage - V

Figure 1. Frequency vs Supply Voltage

23

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted)

supply current into AV_CC+ DV_CCexcluding external current

PARAMETER

T

A

V

MIN

TYP

MAX

UNIT

CC

Active mode (see Note 1),

2.2 V

3 V

220

295

f

= f

= 1 MHz,

(SMCLK)

(MCLK)

(ACLK)

XTS=0, SELM=(0,1)

I

-- 4 0 °C to 85°C

µA

(AM)

= 32768 Hz,

350

398

2.2 V

3 V

33

50

60

92

I

Low-power mode 0 (LPM0) (see Note 1)

--40°C to 85°C

-- 4 0 °C to 85°C

µA

(LPM0)

(LPM2)

Low-power mode 2 (LPM2),

f(MCLK) = f (SMCLK) = 0 MHz,

f(ACLK) = 32768 Hz, SCG0 = 0 (see Note 2)

2.2 V

3 V

6

7

13

15

-- 4 0 °C

25°C

60°C

85°C

-- 4 0 °C

25°C

60°C

85°C

-- 4 0 °C

25°C

85°C

-- 4 0 °C

25°C

85°C

-- 4 0 °C

25°C

60°C

85°C

-- 4 0 °C

25°C

60°C

85°C

0.85

0.90

1.15

2.15

1.0

1.1

1.4

2.5

1.8

2.1

3.6

2.1

2.3

4.1

0.1

0.35

1.1

0.1

0.8

1.9

1.4

1.2

1.4

3.0

1.5

1.9

3.5

3.3

3.2

5.0

3.6

5.5

0.5

0.9

2.5

0.8

1.2

3.5

Low-power mode 3 (LPM3),

2.2 V

3 V

f

= f

= 0 MHz,

(MCLK)

(ACLK)

(SMCLK)

= 32768 Hz, SCG0 = 1,

Basic Timer1 enabled , ACLK selected,

LCD_A enabled, LCDCPEN = 0,

(static mode, f

(see Notes 2 and 3)

I

µA

(LPM3)

(LPM4)

= f

/32)

LCD

(ACLK)

Low-power mode 3 (LPM3),

f

= f

= 0 MHz,

2.2 V

3 V

(MCLK)

(ACLK)

(SMCLK)

= 32768 Hz, SCG0 = 1,

Basic Timer1 enabled , ACLK selected,

LCD_A enabled, LCDCPEN = 0,

(4-mux mode, f

(see Notes 2 and 3)

= f

/32)

LCD

(ACLK)

2.2 V

3 V

Low-power mode 4 (LPM4),

f

= 0 MHz, f

= 0 MHz,

(MCLK)

(ACLK)

(SMCLK)

= 0 Hz, SCG0 = 1 (see Note 2)

NOTES: 1. Timer_A is clocked by f

= 1 MHz. All inputs are tied to 0 V or to V . Outputs do not source or sink any current.

CC

(DCOCLK)

2. All inputs are tied to 0 V or to V . Outputs do not source or sink any current.

3. The LPM3 currents are characterized with a Micro Crystal CC4V--T1A (9 pF) crystal and OSCCAPx = 01h.

24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

typical characteristics -- LPM4 current

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Vcc = 3.6V

Vcc = 3.0V

Vcc = 2.2V

Vcc = 1.8V

--40.0 --20.0 0.0

20.0 40.0 60.0 80.0 100.0

-- Temperature -- °C

T

A

Figure 2. I_LPM4-- LPM4 Current vs Temperature

25

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

Schmitt-trigger inputs -- ports P1, P2, P3, P4, P5, P6, and P7, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)

PARAMETER

V

MIN

1.1

1.5

0.4

0.9

0.3

0.5

MAX

1.55

1.98

0.9

UNIT

CC

2.2 V

3 V

V

Positive-going input threshold voltage

V

IT+

IT--

hys

2.2 V

3 V

Negative-going input threshold voltage

Input voltage hysteresis (V -- V

V

1.3

2.2 V

3 V

1.1

)

IT--

IT+

1

inputs Px.y, TAx

PARAMETER

TEST CONDITIONS

V

MIN

62

MAX

UNIT

CC

2.2 V

3 V

Port P1, P2: P1.x to P2.x, external trigger signal

for the interrupt flag (see Note 1)

t

f

External interrupt timing

Timer_A capture timing

ns

(int)

50

2.2 V

3 V

62

TA0, TA1, TA2

ns

(cap)

50

2.2 V

3 V

8

10

8

Timer_A clock frequency externally

applied to pin

TACLK, INCLK: t = t

(L)

MHz

(TAext)

(H)

2.2 V

3 V

Timer_A, clock frequency

SMCLK or ACLK signal selected

(TAint)

10

NOTES: 1. The external signal sets the interrupt flag every time the minimum t

parameters are met. It may be set even with trigger signals

(int)

shorter than t

.

(int)

leakage current -- ports P1, P2, P3, P4, P5, P6, and P7 (see Note 1)

PARAMETER

TEST CONDITIONS

V

MIN

MAX

UNIT

CC

I

Leakage current

Port Px

V

(see Note 2)

(Px.y)

2.2 V/3 V

±50

nA

lkg(Px.y)

NOTES: 1. The leakage current is measured with V or V applied to the corresponding pin(s), unless otherwise noted.

SS

CC

2. The port pin must be selected as input.

26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

outputs -- ports P1, P2, P3, P4, P5, P6, and P7

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

I

= --1.5 mA,

= --6 mA,

= --1.5 mA,

= --6 mA,

= 1.5 mA,

= 6 mA,

V

= 2.2 V

= 3 V

(see Note 1)

(see Note 2)

(see Note 1)

(see Note 2)

(see Note 1)

(see Note 2)

(see Note 1)

(see Note 2)

V

--0.25

V

OH(max)

OL(max)

CC

V

-- 0 . 6

CC

V

High-level output voltage

V

OH

V

--0.25

CC

= 3 V

V

-- 0 . 6

CC

= 2.2 V

= 3 V

V

+0.25

SS

V

+0.6

SS

Low-level output voltage

V

OL

= 1.5 mA,

= 6 mA,

V

+0.25

SS

= 3 V

V

+0.6

SS

NOTES: 1. The maximum total current, I

specified voltage drop.

and I

for all outputs combined, should not exceed ±12 mA to satisfy the maximum

OH(max)

OL(max),

2. The maximum total current, I

specified voltage drop.

and I

for all outputs combined, should not exceed ±48 mA to satisfy the maximum

OH(max)

OL(max),

output frequency

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MHz

f

(x = 1, 2, 3, 4, 5, 6, 7, 0 ≤ y ≤ 7)

C

= 20 pF, I = ±1.5 mA

V

= 2.2 V / 3 V

dc

f

(Px.y)

L

CC

System

P1.1/TA0.0/MCLK/S30

= 20 pF

(MCLK)

L

System

f

= f

40%

60%

(MCLK)

(XT1)

P1.1/TA0.0/MCLK/S30,

t

Duty cycle of output frequency

C

V

= 20 pF,

50%--

15 ns

50%+

15 ns

(Xdc)

L

CC

50%

(DCOCLK)

= 2.2 V / 3 V

27

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

outputs -- ports Px (continued)

TYPICAL LOW-LEVEL OUTPUT CURRENT

vs

LOW-LEVEL OUTPUT VOLTAGE

30

25

20

15

10

5

50

45

40

35

30

25

20

15

10

5

V

= 2.2 V

V

= 3 V

CC

T

= --40°C

CC

P1.0

A

T

= --40°C

A

P1.0

T

A

= 25°C

T

= 25°C

A

T

A

= 85°C

T

A

= 85°C

0

0.0

0

0.0

0.5

1.0

1.5

2.0

2.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V

-- Low-Level Output Voltage -- V

V

-- Low-Level Output Voltage -- V

OL

Figure 3

Figure 4

TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs

HIGH-LEVEL OUTPUT VOLTAGE

0.0

-- 5 . 0

0.0

V

= 2.2 V

V

= 3 V

CC

P1.0

CC

P1.0

-- 5 . 0

--10.0

--15.0

--20.0

--25.0

--30.0

--35.0

--40.0

--45.0

--50.0

--55.0

--60.0

--65.0

--10.0

--15.0

--20.0

--25.0

--30.0

--35.0

T

= 25°C

A

T

A

= 85°C

T

A

= 25°C

T

= 85°C

A

T

= --40°C

A

T

= --40°C

A

0.0

0.5

1.0

1.5

2.0

2.5

0.0

0.5

V

1.0

1.5

2.0

2.5

3.0

3.5

V

-- High-Level Output Voltage -- V

OH

Figure 5

Figure 6

28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

wake-up LPM3

PARAMETER

TEST CONDITIONS

f = 1 MHz

MIN

MAX

UNIT

6

f = 2 MHz

f = 3 MHz

t

Delay time

V

= 2.2 V/3 V

CC

µs

d(LPM3)

POR/brownout reset (BOR) (see Note 1)

PARAMETER

TEST CONDITIONS

MIN

TYP

0.7 × V

MAX

UNIT

µs

t

2000

d(BOR)

V

dV /dt ≤ 3 V/s (see Figure 7)

V

CC(start)

CC

(B_IT--)

Brownout

(see Note 2)

V

dV /dt ≤ 3 V/s (see Figure 7)

CC

1.71

V

mV

(B_IT--)

CC

hys(B_IT--)

Pulse length needed at RST/NMI pin to accepted reset internally,

= 2.2 V/3 V

t

2

µs

(reset)

V

CC

NOTES: 1. The current consumption of the brownout module is already included in the I current consumption data.

CC

The voltage level V

+ V

is ≤ 1.8V.

(B_IT--)

hys(B_IT--)

2. During power up, the CPU begins code execution following a period of t

after V = V

+ V

. The default FLL+

hys(B_IT--)

d(BOR)

CC

(B_IT--)

settings must not bechangeduntil V ≥ V

, where V

is the minimum supply voltage for the desired operating frequency.

CC

CC(min)

See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout.

typical characteristics

V

CC

V

hys(B_IT--)

V

(B_IT--)

V

CC(start)

1

0

t

d(BOR)

Figure 7. POR/Brownout Reset (BOR) vs Supply Voltage

29

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

typical characteristics (continued)

V

t

CC

pw

2

3 V

V

= 3 V

CC

Typical Conditions

1.5

1

V

CC(min)

0.5

0

0.001

1

1000

1 ns

-- Pulse Width -- µs

t

pw

-- Pulse Width -- µs

t

pw

Figure 8. V_(CC)minLevel With a Square Voltage Drop to Generate a POR/Brownout Signal

V

t

CC

pw

2

1.5

1

3 V

V

= 3 V

CC

Typical Conditions

V

CC(min)

0.5

0

t = t

f

r

0.001

1

1000

t

f

t

r

t

pw

-- Pulse Width -- µs

t

pw

-- Pulse Width -- µs

Figure 9. V_CC(min)Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal

30

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted)

SVS (supply voltage supervisor/monitor)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

150

2000

200

12

UNIT

µs

dV /dt > 30 V/ms (see Figure 10)

5

CC

t

(SVSR)

dV /dt ≤ 30 V/ms

CC

t

SVS , switch from VLD = 0 to VLD ≠ 0, V = 3 V

20

µs

d(SVSon)

settle

ON

CC

‡

VLD ≠ 0

µs

V

VLD ≠ 0, V /dt ≤ 3 V/s (see Figure 10)

1.55

120

1.7

V

(SVSstart)

CC

VLD = 1

70

210

mV

V

/dt ≤ 3 V/s (see Figure 10)

/dt ≤ 3 V/s (see Figure 10),

V

(SVS_IT--)

×

CC

(SVS_IT--)

VLD = 2 to 14

0.001

0.016

V

×

hys(SVS_IT-- )

CC

VLD = 15

4.4

20

mV

External voltage applied on A7

VLD = 1

VLD = 2

VLD = 3

VLD = 4

VLD = 5

VLD = 6

VLD = 7

VLD = 8

VLD = 9

VLD = 10

VLD = 11

VLD = 12

VLD = 13

VLD = 14

1.8

1.9

2.1

2.2

2.3

2.4

2.5

2.65

2.8

2.9

3.05

3.2

2.05

2.25

2.37

2.48

2.6

2.71

2.86

3

1.94

2.05

2.14

2.24

2.33

2.46

2.58

2.69

2.83

2.94

3.11

3.24

3.43

V

/dt ≤ 3 V/s (see Figure 10 and Figure 11)

CC

V

(SVS_IT--)

3.13

3.29

3.42

†

3.35

3.5

3.61

3.76

3.99

†

3.7

/dt ≤ 3 V/s (see Figure 10 and Figure 11),

External voltage applied on A7

CC

VLD = 15

1.1

1.2

10

1.3

15

I

CC(SVS)

VLD ≠ 0, V = 2.2 V/3 V

µA

CC

(see Note 1)

†

‡

The recommended operating voltage range is limited to 3.6 V.

is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere

t

settle

between 2 and 15. The overdrive is assumed to be > 50 mV.

NOTE 1: The current consumption of the SVS module is not included in the I current consumption data.

CC

31

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

typical characteristics

Software sets VLD > 0:

SVS is active

AV

CC

V

hys(SVS_IT--)

V

(SVS_IT--)

V

(SVSstart)

V

hys(B_IT--)

V

(B_IT--)

V

CC(start)

Brown-

out

Brownout

Region

Brownout

1

0

t

SVS out

1

d(BOR)

SVS Circuit is Active From VLD > to V < V(

CC

B_IT--)

0

t

d(SVSon)

d(SVSR)

Set POR

1

undefined

0

Figure 10. SVS Reset (SVSR) vs Supply Voltage

V

CC

t

pw

3 V

2

Rectangular Drop

V

CC(min)

1.5

1

Triangular Drop

1 ns

V

t

CC

pw

0.5

0

3 V

1

10

100

1000

t

pw

-- Pulse Width -- µs

V

CC(min)

t = t

f

r

t

f

t

r

t -- Pulse Width -- µs

Figure 11. V_CC(min): Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal (VLD = 1)

32

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted)

DCO

PARAMETER

TEST CONDITIONS

V

MIN

TYP

MAX

UNIT

CC

N

= 01E0h, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2,

(DCO)

DCOPLUS = 0

f

2.2 V/3 V

1

MHz

(DCOCLK)

(DCO2)

2.2 V

3 V

0.3

2.5

2.7

0.7

0.8

5.7

6.5

1.2

1.3

9

0.65

0.7

5.6

6.1

1.3

1.5

10.8

12.1

2

1.25

1.3

10.5

11.3

2.3

2.5

18

f

FN_8 = FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1

MHz

2.2 V

3 V

FN_8 = FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1 (see Note 1)

FN_8 = FN_4 = FN_3 = 0, FN_2 = 1, DCOPLUS = 1

(DCO27)

(DCO2)

2.2 V

3 V

2.2 V

3 V

FN_8 = FN_4 = FN_3 = 0, FN_2 = 1, DCOPLUS = 1 (see Note 1)

FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1

FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1 (see Note 1)

FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1

FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1 (see Note 1)

FN_8 = 1, FN_4 = FN_3 = FN_2 = x, DCOPLUS = 1

(DCO27)

(DCO2)

20

2.2 V

3 V

3

2.2

15.5

17.9

2.8

3.4

21.5

26.6

4.2

6.3

32

3.5

25

2.2 V

3 V

(DCO27)

(DCO2)

10.3

1.8

2.1

13.5

16

28.5

4.2

5.2

33

2.2 V

3 V

2.2 V

3 V

(DCO27)

(DCO2)

41

2.2 V

3 V

2.8

4.2

21

6.2

9.2

46

2.2 V

3 V

FN_8 = 1,FN_4 = FN_3 = FN_2 = x, DCOPLUS = 1 (see Note 1)

Step size between adjacent DCO taps:

(DCO27)

30

46

70

1 < TAP ≤ 20

TAP = 27

2.2 V

3 V

1.06

1.07

–0.2

1.11

1.17

-- 0 . 6

S

n

S

= f

/ f , (see Figure 13 for taps 21 to 27)

DCO(Tap n+1) DCO(Tap n)

n

–0.4

Temperature drift, N

D = 2, DCOPLUS = 0

= 01E0h, FN_8 = FN_4 = FN_3 = FN_2 = 0,

(DCO)

D

%/_C

t

Drift with V variation, N

FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0

= 01E0h,

(DCO)

CC

0

5

15

%/V

V

NOTES: 1. Do not exceed the maximum system frequency.

f

(DCO)

f

°

(DCO20 C)

(DCO3V)

1.0

0

1.8

2.4

3.0

3.6

-- 4 0

-- 2 0

0

20

40

60

85

V

-- V

T -- °C

A

CC

Figure 12. DCO Frequency vs Supply Voltage V_CCand vs Ambient Temperature

33

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

1.17

Max

1.11

1.07

1.06

Min

1

20

27

DCO Tap

Figure 13. DCO Tap Step Size

Legend

Tolerance at Tap 27

DCO Frequency

Adjusted by Bits

9

5

2

to 2 in SCFI1 {N

}

{DCO}

Tolerance at Tap 2

Overlapping DCO Ranges:

Uninterrupted Frequency Range

FN_2=0

FN_3=0

FN_4=0

FN_8=0

FN_2=1

FN_3=0

FN_4=0

FN_8=0

FN_2=x

FN_3=x

FN_4=1

FN_8=0

FN_2=x

FN_3=1

FN_4=0

FN_8=0

FN_3=x

FN_4=x

FN_8=1

Figure 14. Five Overlapping DCO Ranges Controlled by FN_x Bits

34

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted)

crystal oscillator, LFXT1, low-frequency modes (see Note 4)

PARAMETER

TEST CONDITIONS

XTS = 0, LFXT1Sx = 0 or 1

XTS = 0, LFXT1Sx = 0,

V

MIN

TYP

MAX UNIT

CC

LFXT1 oscillator crystal

frequency, LF mode 0, 1

f

1.8 V to 3.6 V

32768

Hz

LFXT1,LF

f

= 32768 kHz,

500

200

LFXT1,LF

C

L,eff

= 6 pF

Oscillation allowance for

LF crystals

OA

kΩ

LF

XTS = 0, LFXT1Sx = 0,

= 32768 kHz,

f

LFXT1,LF

C

L,eff

= 12 pF

XTS = 0, XCAPx = 0

XTS = 0, XCAPx = 1

XTS = 0, XCAPx = 2

XTS = 0, XCAPx = 3

1

5.5

8.5

11

Integrated effective load

capacitance, LF mode

(see Note 1)

C

L,eff

pF

XTS = 0,

Duty cycle

LF mode

Measured at P1.6/ACLK,

2.2 V/3 V

30

10

50

70

%

f

= 32768Hz

LFXT1,LF

Oscillator fault frequency,

LF mode (see Note 3)

XTS = 0, XCAPx = 0.

LFXT1Sx = 3 (see Note 2)

f

10000

Hz

Fault,LF

NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a

correct setup the effective load capacitance should always match the specification of the used crystal.

2. Measured with logic level input frequency but also applies to operation with crystals.

3. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and

frequencies in between might set the flag.

4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.

-- Keep the trace between the device and the crystal as short as possible.

-- Design a good ground plane around the oscillator pins.

-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

-- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.

-- If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

-- Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other

documentation. This signal is no longer required for the serial programming adapter.

35

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted)

crystal oscillator, LFXT1, high frequency modes

PARAMETER

TEST CONDITIONS

V

MIN

0.45

1

TYP

MAX UNIT

CC

Ceramic resonator

1.8 V to 3.6 V

6

f

LFXT1 oscillator crystal frequency

MHz

6

LFXT1

Crystal resonator

See Note 2

Integrated effective load capacitance,

HF mode (see Note 1)

C

L,eff

1

pF

Duty cycle

Measured at P1.6/ACLK

2.2 V/3 V

40

50

60

%

NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a

correct setup the effective load capacitance should always match the specification of the used crystal.

2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

internal very low power, low-frequency oscillator (VLO)

PARAMETER

TEST CONDITIONS

= --40°C to 85°C

A

V

MIN

TYP

12

MAX UNIT

CC

f

VLO frequency

T

2.2 V/3 V

4

20

kHz

%/°C

%/V

VLO

df

/dT

/dV

VLO frequency temperature drift

VLO frequency supply voltage drift

See Note

0.5

4

VLO

See Note 2

1.8V to 3.6V

CC

NOTES: 1. Calculated using the box method:

I Version: (MAX(--40_C to 85_C) -- MIN(--40_C to 85_C))/MIN(--40_C to 85_C)/(85_C -- (--40_C))

2. Calculated using the box method: (MAX(1.8 V to 3.6 V) -- MIN(1.8 V to 3.6 V))/MIN(1.8 V to 3.6 V)/(3.6 V -- 1.8 V)

RAM

PARAMETER

TEST CONDITIONS

CPU halted

MIN

MAX

UNIT

VRAMh

See Note 1

1.6

V

NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution

should take place during this supply voltage condition.

36

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

LCD_A

PARAMETER

TEST CONDITIONS

V

MIN

2.2

TYP

MAX UNIT

CC

Charge pump enabled

V

Supply voltage range

3.6

V

CC(LCD)

(LCDCPEN = 1, VLCDx > 0000)

Charge pump enabled

C

LCD

Capacitor on LCDCAP (see Note 1)

4.7

µF

(LCDCPEN = 1, VLCDx > 0000)

V

=3V, LCDCPEN = 1,

LCD(typ)

VLCDx= 1000, all segments on

= f /32

f

I

Average supply current (see Note 2)

2.2 V

3.8

µA

LCD

ACLK

CC(LCD)

LCD

no LCD connected (see Note 3)

= 25°C

T

A

f

LCD frequency

LCD voltage

1.1 kHz

V

VLCDx = 0000

VLCDx = 0001

VLCDx = 0010

VLCDx = 0011

VLCDx = 0100

VLCDx = 0101

VLCDx = 0110

VLCDx = 0111

VLCDx = 1000

VLCDx = 1001

VLCDx = 1010

VLCDx = 1011

VLCDx = 1100

VLCDx = 1101

VLCDx = 1110

VLCDx = 1111

V

LCD

CC

2.60

2.66

2.72

2.78

2.84

2.90

2.96

3.02

3.08

3.14

3.20

3.26

3.32

3.38

3.44

3.60

10

V

= 3 V, LCDCPEN = 1,

LCD

R

LCD driver output impedance

2.2 V

kΩ

LCD

VLCDx = 1000, I

= ±10 µA

LOAD

NOTES: 1. Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device.

2. Refer to the supply current specifications I

for additional current specifications with the LCD_A module active.

(LPM3)

3. Connecting an actual display will increase the current consumption depending on the size of the LCD.

37

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

Comparator_A+ (see Note 1)

PARAMETER

TEST CONDITIONS

V

MIN

TYP

25

MAX

40

UNIT

CC

2.2 V

3 V

I

CAON = 1, CARSEL = 0, CAREF = 0

µA

(CC)

45

30

45

60

50

80

2.2 V

3 V

CAON = 1, CARSEL = 0, CAREF = 1/2/3,

No load at P1.6/CA0 and P1.7/CA1

µA

(Refladder/RefDiode)

Voltage @ 0.25 V

node

PCA0 = 1, CARSEL = 1, CAREF = 1,

No load at P1.6/CA0 and P1.7/CA1

CC

V

2.2 V / 3 V

2.2V / 3 V

0.23

0.47

0.24

0.48

0.25

0.5

(Ref025)

(Ref050)

V

CC

Voltage @ 0.5 V

PCA0 = 1, CARSEL = 1, CAREF = 2,

No load at P1.6/CA0 and P1.7/CA1

CC

V

CC

PCA0 = 1, CARSEL = 1, CAREF = 3,

No load at P1.6/CA0 and P1.7/CA1,

A

2.2 V

3 V

390

400

480

490

540

550

See Figure 15 and

Figure 16

V

mV

V

(RefVT)

IC

T

= 85°C

Common-mode input

voltage range

CAON = 1

2.2 V / 3 V

0

V

-- 1

30

CC

V -- V

Offset voltage

See Note 2

CAON = 1

2.2 V / 3 V

2.2 V

-- 3 0

0

mV

p

S

V

Input hysteresis

0.7

165

120

1.9

1.4

300

240

2.8

hys

80

70

1.4

0.9

T

A

= 25°C,

ns

Overdrive 10 mV, without filter: CAF = 0

3 V

t

(see Note 3)

(response LH and HL)

2.2 V

T

= 25°C

A

µs

Overdrive 10 mV, with filter: CAF = 1

3 V

1.5

2.2

NOTES: 1. The leakage current for the Comparator_A terminals is identical to I

specification.

lkg(Px.x)

2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.

The two successive measurements are then summed together.

3. The response time is measured at P1.6/CA0 with an input voltage step and the Comparator_A already enabled (CAON=1). If CAON

is set at the same time, a settling time of up to 300ns is added to the response time.

38

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

typical characteristics

REFERENCE VOLTAGE

vs

FREE-AIR TEMPERATURE

REFERENCE VOLTAGE

vs

FREE-AIR TEMPERATURE

650

600

550

500

450

400

650

600

550

500

450

400

V

= 3 V

CC

V

= 2.2 V

CC

Typical

-- 4 5

-- 2 5

-- 5

1 5

3 5

5 5

7 5

9 5

-- 4 5

-- 2 5

-- 5

1 5

3 5

5 5

7 5

9 5

T

A

-- Free-Air Temperature -- °C

T

A

-- Free-Air Temperature -- °C

Figure 15. V_(RefVT)vs Temperature

Figure 16. V_(RefVT)vs Temperature

0 V

V

CC

CAF

0

1

CAON

To Internal

Modules

Low-Pass Filter

0

1

0

1

+

_

V+

V--

CAOUT

Set CAIFG

Flag

τ ≈ 2 µs

Figure 17. Block Diagram of Comparator_A Module

V

CAOUT

Overdrive

V--

400 mV

V+

t

(response)

Figure 18. Overdrive Definition

39

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

10-bit ADC, power supply and input range conditions (see Note )

PARAMETER

TEST CONDITIONS

V

MIN

2.2

TYP

MAX UNIT

CC

Analog supply voltage

range

V

= 0 V

SS

3.6

V

CC

Analog input voltage

range (see Note 2)

All Ax terminals,

Analog inputs selected in ADC10AE register

V

Ax

0

V

CC

f

5 MHz,

2.2 V

3 V

0.52

0.6

1.05

1.2

ADC10CLK =

ADC10ON = 1, REFON = 0

ADC10 supply current

(see Note 3)

I

mA

ADC10

ADC10SHT0 = 1, ADC10SHT1 = 0, ADC10DIV = 0

f

5 MHz,

ADC10CLK =

ADC10ON = 0, REF2_5V = 0,

REFON = 1, REFOUT = 0

2.2 V/3 V

3 V

Reference supply

current, reference buffer

disabled (see Note 4)

I

0.25

1.1

0.4

REF+

f

5 MHz,

ADC10CLK =

ADC10ON = 0, REF2_5V = 1,

REFON = 1, REFOUT = 0

f

5 MHz,

ADC10CLK =

Reference buffer supply

current with

ADC10SR = 0

(see Note 4)

2.2 V/3 V

1.4

1.8

mA

ADC10ON = 0,

REFON = 1, REF2_5V = 0,

REFOUT = 1,

I

REFB,0

REFB,1

ADC10SR = 0

f

5 MHz,

ADC10CLK =

2.2 V/3 V

0.5

0.7

0.8

mA

Reference buffer supply

current with

ADC10SR = 1

(see Note 4)

ADC10ON = 0,

REFON = 1,

REF2_5V = 0,

REFOUT = 1,

ADC10SR = 1

C

R

Input capacitance

Only one terminal Ax selected at a time

27

pF

I

Input MUX ON

resistance

0V ≤ V ≤ V

2.2 V/3 V

2000

Ω

I

Ax

CC

NOTES: 1. The leakage current is defined in the leakage current table with Px.x/Ax parameter.

2. The analog input voltage range must be within the selected reference voltage range V to V for valid conversion results.

R+

R--

.

3. The internal reference supply current is not included in current consumption parameter I

ADC10

4. The internal reference current is supplied via terminal V . Consumption is independent of the ADC10ON control bit, unless a

CC

conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.

40

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

10-bit ADC, built-in voltage reference

PARAMETER

TEST CONDITIONS

≤ 1 mA, REF2_5V = 0

≤ 0.5 mA, REF2_5V = 1

≤ 1 mA, REF2_5V = 1

V

MIN TYP

MAX UNIT

CC

I

2.2

2.8

2.9

VREF+

Positive built-in reference analog

supply voltage range

V

CC,REF+

2.2 V/

3 V

I

≤ I

max, REF2_5V = 0

1.41

2.35

1.5

1.59

V

VREF+

Positive built-in reference voltage

REF+

max, REF2_5V = 1

3 V

2.2 V

3 V

2.5

2.65

±0.5

±1

I

Maximum V

load current

REF+

mA

LD,VREF+

I

500 µA ± 100 µA,

VREF+ =

2.2 V/

3 V

Analog input voltage V ≈ 0.75 V,

±2

LSB

Ax

REF2_5V = 0

V

load regulation

REF+

I

500 µA ± 100 µA,

VREF+ =

Analog input voltage V ≈ 1.25 V,

3 V

LSB

Ax

REF2_5V = 1

I

= 100 µA→900 µA,

ADC10SR = 0

ADC10SR = 1

3 V

3V

400

VREF+

load regulation response

REF+

time

V

≈ 0.5 x V

Error of

ns

Ax

REF+,

2000

conversion result ≤ 1 LSB

Max. capacitance at pin V

(see Note 1)

I

≤ ±1 mA,

2.2 V/

3 V

REF+

VREF+

C

VREF+

100

pF

REFON = 1, REFOUT = 1

I

const. with 0 mA ≤ I

≤ 1 mA

VREF+

2.2 V/

3 V

VREF+ =

TC

Temperature coefficient

±100 ppm/°C

REF+

(see Note 3)

I 0.5 mA, REF2_5V = 0,

VREF+ =

Settling time of internal reference

voltage (see Note 2)

3.6 V

30

1

µs

t

REFON

REFON = 0 → 1

I

0.5 mA,

VREF+ =

ADC10SR = 0 2.2 V

ADC10SR = 1 2.2 V

REF2_5V = 0,

REFON = 1,

2.5

2

REFBURST = 1

Settling time of reference buffer

(see Note 2)

µs

REFBURST

I

0.5 mA,

VREF+ =

ADC10SR = 0

3 V

REF2_5V = 1,

REFON = 1,

ADC10SR = 1

operational

3 V

4.5

to

REFBURST = 1

NOTES: 1. The

capacitance

applied

to

the

/V

internal

buffer

amplifier,

if

switched

terminal

P6.4/UCB0CLK/UCA0STE/A4/CA6/V

otherwise.

(REFOUT = 1), must be limited; the reference buffer may become unstable,

eref+ ref+

2. The condition is that the error in a conversion started after t

3. Calculated using the box method: ((MAX(V

or t

is less than ±0.5 LSB.

RefBuf

REFON

(T)) -- MIN(V

(T))) / MIN(V

(T)) / (T

-- T

)

REF

MAX

MIN

41

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

10-bit ADC, external reference (see Note 1)

PARAMETER

TEST CONDITIONS

> V

V

MIN

1.4

TYP

MAX UNIT

CC

V

,

eREF--

eREF+

V

CC

SREF1 = 1, SREF0 = 0

Positive external reference input

voltage range (see Note 2)

V

eREF+

V

eREF--

≤ V ≤ (V -- 0.15 V)

eREF+

CC

1.4

0

3.0

1.2

SREF1 = 1, SREF0 = 1 (see Note 3)

Negative external reference input

voltage range (see Note 4)

V

eREF--

V

eREF+

> V

V

eREF--

Differential external reference input

voltage range

∆V

eREF

V

eREF+

> V

(see Note 5)

1.4

V

CC

eREF--

∆V

= V

-- V

eREF

eREF+ eREF--

0V ≤ V

≤ V

,

CC

eREF+

2.2 V/3 V

±1

SREF1 = 1, SREF0 = 0

I

Static input current into V

µA

VeREF+

VeREF--

eREF+

0V ≤ V ≤ (V -- 0.15 V) ≤ 3 V,

eREF+

CC

2.2 V/3 V

0

SREF1 = 1, SREF0 = 1 (see Note 3)

0V ≤ V ≤ V

±1

eREF--

CC

NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, C , is also

I

the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the

recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.

2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

3. Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer

supply current I

. The current consumption can be limited to the sample and conversion period with REBURST = 1.

REFB

4. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

accuracy requirements.

5. The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied

with reduced accuracy requirements.

42

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

10-bit ADC, timing parameters

PARAMETER

TEST CONDITIONS

V

MIN

TYP

MAX UNIT

CC

For specified

ADC10SR = 0

ADC10SR = 1

2.2 V/3 V

0.45

6.3

MHz

1.5

performance of

ADC10 linearity

parameters

f

ADC10 input clock frequency

ADC10CLK

ADC10OSC

0.45

3.7

ADC10DIVx = 0, ADC10SSELx = 0

ADC10 built-in oscillator frequency

6.3 MHz

f

ADC10CLK = ADC10OSC

ADC10 built-in oscillator,

ADC10SSELx = 0

ADC10CLK = ADC10OSC

2.2 V/3 V

2.06

3.51

µs

f

t

Conversion time

CONVERT

ADC10ON

13×

f

from ACLK, MCLK or

ADC10CLK

SMCLK: ADC10SSELx ≠ 0

ADC10DIV×

µs

1/f

ADC10CLK

Turn on settling time of the ADC

See Note 1

100

ns

NOTE 1: The condition is that the error in a conversion started after t

settled.

is less than ±0.5 LSB. The reference and input signals are already

ADC10ON

10-bit ADC, linearity parameters

PARAMETER

TEST CONDITIONS

V

MIN

TYP

MAX UNIT

±1 LSB

±2 LSB

CC

E

Integral linearity error

Differential linearity error

Offset error

2.2 V/3 V

2.2 V

I

D

O

Source impedance R < 100 Ω

S

SREFx = 010, Unbuffered external reference, V

1.5 V

2.5 V

±1.1

eREF+ =

SREFx = 010, Unbuffered external reference, V

3 V

eREF+ =

SREFx = 011, Buffered external reference (see Note 2),

1.5 V

Gain error

E

2.2 V

3 V

±1.1

±4 LSB

±3 LSB

G

V

eREF+ =

SREFx = 011, Buffered external reference (see Note 2),

2.5 V

V

eREF+ =

SREFx = 010, Unbuffered external reference, V

1.5 V

2.5 V

2.2 V

3 V

±2

±5 LSB

eREF+ =

SREFx = 010, Unbuffered external reference, V

SREFx = 011, Buffered external reference (see Note 2),

1.5 V

Total unadjusted error

2.2 V

3 V

±2

±7 LSB

±6 LSB

T

V

eREF+ =

SREFx = 011, Buffered external reference (see Note 2),

2.5 V

V

eREF+ =

NOTE 1: The reference buffer’s offset adds to the gain and total unadjusted error.

43

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

10-bit ADC, temperature sensor and built-in V_MID

PARAMETER

TEST CONDITIONS

V

MIN

TYP

40

MAX

120

UNIT

CC

2.2 V

3 V

Temperature sensor supply

current (see Note )

REFON = 0, INCHx = 0Ah,

I

µA

SENSOR

ADC10ON = 1, T = 25_C

A

60

160

ADC10ON = 1, INCHx = 0Ah

(see Note 2)

2.2 V/3 V

3.55

mV/°C

mV

TC

SENSOR

ADC10ON = 1, INCHx = 0Ah

(see Note 2)

V

Sensor offset voltage

--100

100

1395

1185

1095

Offset,Sensor

Temperature sensor voltage

2.2 V/3 V

1195

985

895

1295

1085

995

mV

at T = 85°C

A

Temperature sensor voltage

Sensor output voltage

(see Note 3)

V

Sensor

at T = 25°C

A

mV

Temperature sensor voltage

at T = 0°C

A

Sample time required if

channel 10 is selected (see

Note 4)

ADC10ON = 1, INCHx = 0Ah,

2.2 V/3 V

30

µs

t

I

Sensor(sample)

VMID

Error of conversion result ≤ 1 LSB

2.2 V

3 V

NA

Current into divider at

channel11 (see Note 5)

ADC10ON = 1, INCHx = 0Bh

ADC10ON = 1, INCHx = 0Bh,

µA

2.2 V

3 V

1.06

1.46

1.1

1.5

1.14

1.54

V

t

V

divider at channel 11

CC

V

MID

V

is ≈0.5 x V

MID

CC

Sample time required if

channel 11 is selected

(see Note 6)

2.2 V

3 V

1400

1220

ADC10ON = 1, INCHx = 0Bh,

Error of conversion result ≤ 1 LSB

ns

VMID(sample)

NOTES: 1. The sensor current I

is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON = 1 and INCH = 0Ah and sample signal

SENSOR

is high). When REFON = 1, I

sensor input (INCH = 0Ah).

2. The following formula can be used to calculate the temperature sensor output voltage:

is included in I

. When REFON = 0, I

applies during conversion of the temperature

SENSOR

REF+

SENSOR

V

= TC

( 273 + T [°C] ) + V

[mV] or

Sensor,typ

Sensor

Offset,sensor

(T = 0°C) [mV]

T [°C] + V

Sensor

A

3. Results based on characterization and/or production test, not TC

or V

.

Offset,sensor

Sensor

4. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t

.

SENSOR(on)

5. No additional current is needed. The V

is used during sampling.

MID

6. The on-time t

is included in the sampling time t

; no additional on time is needed.

VMID(on)

VMID(sample)

Timer0_A3, Timer1_A5

PARAMETER

TEST CONDITIONS

V

MIN

MAX UNIT

CC

Internal: SMCLK, ACLK,

2.2 V

3 V

8

f

t

Timer_A clock frequency

Timer_A, capture timing

MHz

10

External: TACLK, INCLK,

TA

Duty cycle = 50% ±10%

TA0, TA1, TA2

2.2 V/3 V

20

ns

TA,cap

44

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

USCI (UART mode)

PARAMETER

TEST CONDITIONS

V

MIN

TYP

MAX UNIT

CC

Internal: SMCLK, ACLK

External: UCLK

Duty cycle = 50% ± 10%

f

USCI input clock frequency

f

MHz

USCI

SYSTEM

Maximum BITCLK clock frequency

(equals baudrate in MBaud)

(see Note 1)

fmax,

2.2V /3 V

2

MHz

ns

BITCLK

2.2 V

3 V

50

150

100

UART receive deglitch time

(see Note 2)

t

τ

NOTES: 1. The DCO wake-up time must be considered in LPM3/4 for baudrates above 1 MHz.

2. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed.

USCI (SPI master mode) (see Figure 19 and Figure 20)

PARAMETER

TEST CONDITIONS

V

MIN

MAX UNIT

CC

SMCLK, ACLK

f

t

USCI input clock frequency

f

MHz

ns

USCI

SYSTEM

Duty cycle = 50% ± 10%

2.2 V

3 V

110

75

0

SOMI input data setup time

SOMI input data hold time

SU,MI

2.2 V

3 V

ns

HD,MI

0

2.2 V

3 V

30

20

UCLK edge to SIMO valid,

SIMO output data valid time

ns

VALID,MO

C

L

= 20 pF

1

NOTE: f_UCxCLK

=

with t_LO∕HI≥ max(t_{VALID,MO(USCI)}+ t_{SU,SI(Slave),}

t

_SU,MI(USCI)+ t_{VALID,SO(Slave)}).

2t_LO∕HI

For the slave’s parameters t

and t

refer to the SPI parameters of the attached slave.

VALID,SO(Slave)

SU,SI(Slave)

USCI (SPI slave mode) (see Figure 21 and Figure 22)

PARAMETER

TEST CONDITIONS

V

MIN

TYP

MAX UNIT

CC

STE lead time

t

2.2 V/3 V

50

ns

STE,LEAD

STE,LAG

STE,ACC

STE,DIS

STE low to clock

STE lag time

Last clock to STE high

10

ns

STE access time

STE low to SOMI data out

50

STE disable time

STE high to SOMI high impedance

2.2 V

3 V

20

15

10

t

SIMO input data setup time

SIMO input data hold time

ns

SU,SI

2.2 V

3 V

ns

HD,SI

2.2 V

3 V

75

50

110

UCLK edge to SOMI valid,

= 20 pF

SOMI output data valid time

ns

75

VALID,SO

C

L

1

NOTE: f_UCxCLK

=

with t_LO∕HI≥ max(t_{VALID,MO(Master)}+ t_SU,SI(USCI),t_{SU,MI(Master)}+ t_{VALID,SO(USCI)}).

2t_LO∕HI

For the master’s parameters t

and t

refer to the SPI parameters of the attached master.

VALID,MO(Master)

SU,MI(Master)

45

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

1/f

UCxCLK

CKPL=0

CKPL=1

UCLK

t

LO/HI

SU,MI

t

HD,MI

SOMI

SIMO

t

VALID,MO

Figure 19. SPI Master Mode, CKPH = 0

1/f

UCxCLK

CKPL=0

CKPL=1

UCLK

t

LO/HI

t

HD,MI

t

SU,MI

SOMI

SIMO

t

VALID,MO

Figure 20. SPI Master Mode, CKPH = 1

46

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

t

STE,LAG

STE,LEAD

STE

1/f

UCxCLK

CKPL=0

CKPL=1

UCLK

t

LO/HI

SU,SI

t

HD,SI

SIMO

SOMI

t

STE,DIS

STE,ACC

VALID,SO

Figure 21. SPI Slave Mode, CKPH = 0

t

STE,LAG

STE,LEAD

STE

1/f

UCxCLK

CKPL=0

CKPL=1

UCLK

t

LO/HI

t

HD,SI

t

SU,SI

SIMO

SOMI

t

STE,DIS

STE,ACC

VALID,SO

Figure 22. SPI Slave Mode, CKPH = 1

47

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

USCI (I2C mode) (see Figure 23)

PARAMETER

TEST CONDITIONS

V

MIN

TYP

MAX UNIT

MHz

CC

Internal: SMCLK, ACLK

External: UCLK

Duty cycle = 50% ± 10%

f

USCI input clock frequency

f

SYSTEM

USCI

f

t

SCL clock frequency

2.2 V/3 V

2.2 V

0

4.0

0.6

4.7

0.6

0

400 kHz

SCL

f

≤ 100kHz

> 100kHz

≤ 100kHz

> 100kHz

us

ns

us

SCL

Hold time (repeated) START

HD,STA

t

Setup time for a repeated START

SU,STA

t

Data hold time

HD,DAT

SU,DAT

SU,STO

Data set--up time

Setup time for STOP

250

4.0

50

150

100

600

ns

Pulse width of spikes suppressed by

input filter

t

SP

3 V

50

t

SU,STA HD,STA

HD,STA

SDA

SCL

1/f

t

SP

SCL

t

SU,STO

SU,DAT

t

HD,DAT

Figure 23. I2C Mode Timing

48

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

flash memory

TEST

CONDITIONS

PARAMETER

V

MIN NOM

MAX

UNIT

CC

V

CC(PGM/

ERASE)

Program and Erase supply voltage

Flash Timing Generator frequency

2.2

3.6

V

f

I

t

257

476

5

kHz

mA

FTG

Supply current from DV during program

2.5V/3.6V

3

PGM

CC

Supply current from DV during erase

CC

3

7

mA

ERASE

CPT

Cumulative program time

Cumulative mass erase time

Program/Erase endurance

Data retention duration

see Note 1

see Note 2

10

ms

200

ms

CMErase

4

5

10

100

10

cycles

years

t

T = 25°C

J

Retention

t

Word or byte program time

35

30

Word

st

Block program time for 1 byte or word

Block, 0

Block program time for each additional byte or word

Block program end-sequence wait time

Mass erase time

21

Block, 1-63

Block, End

Mass Erase

Seg Erase

see Note 3

t

FTG

6

5297

4819

Segment erase time

NOTES: 1. The cumulative program time must not be exceeded when writingto a64--byte flashblock. This parameter applies to all programming

methods: individual word/byte write and block write modes.

2. The mass erase duration generated by the flash timing generator is at least 11.1 ms ( = 5297x1 / f , max = 5297 x 1 / 476 kHz).

FTG

To achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is

met. (A worst case minimum of 19 cycles is required.)

3. These values are hardwired into the Flash Controller’s state machine (t

= 1 / f

).

FTG

JTAG and Spy-Bi-Wire interface

TEST

CONDITIONS

PARAMETER

V

MIN

TYP

MAX

UNIT

CC

f

t

Spy-Bi-Wire input frequency

2.2 V/3 V

0

8

MHz

us

SBW

Spy-Bi-Wire low clock pulse length

0.025

15

SBW,Low

Spy-Bi-Wire enable time,

TEST high to acceptance of first clock edge

(see Note 1)

t

2.2 V/3 V

1

us

SBW,En

t

f

Spy-Bi-Wire return to normal operation time

2.2 V/3 V

2.2 V

15

0

100

5

us

SBW,Ret

TCK

MHz

kΩ

TCK input frequency (see Note 2)

3 V

0

10

90

R

Internal pulldown resistance on TEST

2.2 V/3 V

25

60

Internal

NOTES: 1. Tools accessing the Spy-Bi-Wire interface need to wait for the maximum t

before applying the first SBWCLK clock edge.

time after pulling the TEST/SBWCLK pin high

SBW,En

2.

f

may be restricted to meet the timing requirements of the module selected.

TCK

49

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

JTAG fuse (see Note 1)

TEST

CONDITIONS

PARAMETER

V

MIN

MAX

UNIT

CC

V

Supply voltage during fuse-blow condition

Voltage level on TDI/TCLK for fuse-blow

Supply current into TDI/TCLK during fuse blow

Time to blow fuse

T

A

= 25°C

2.5

6

V

CC(FB)

FB

7

100

1

I

t

mA

ms

FB

NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched

to bypass mode.

50

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

APPLICATION INFORMATION

Port P1 pin schematic: P1.0 to P1.4, input/output with Schmitt trigger

Pad Logic

LCDS24/28

Segment Sy

P1DIR.x

0

1

Direction

0: Input

1: Output

P1OUT.x

0

1

Module X OUT

P1.0/TA0.0/S31

P1.1/TA0.0/MCLK/S30

P1.2/TA0.1/S29

Bus

Keeper

EN

P1SEL.x

P1IN.x

P1.3/TA1.0/SVSOUT/S28

P1.4/TA1.0/S27

EN

Module X IN

P1IRQ.x

D

P1IE.x

EN

Set

Q

P1IFG.x

P1SEL.x

P1IES.x

Interrupt

Edge Select

51

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

Port P1 (P1.0 to P1.4) pin functions

CONTROL BITS / SIGNALS

PIN NAME (P1.X)

P1.0/TA0.0/S31

X

FUNCTION

LCDS24

P1DIR.x

P1SEL.x

LCDS28

0

P1.x (I/O)

I: 0, O: 1

0

1

x

0

1

x

0

1

x

0

1

x

0

1

x

0

Timer0_A3.CCI0A

Timer0_A3.TA0

S31

0

1

0

x

1 (LCDS28)

P1.1/TA0.0/MCLK/S30

P1.2/TA0.1/S29

1

2

3

4

P1.x (I/O)

I: 0, O: 1

0

Timer0_A3.CCI0B

MCLK

0

1

0

S30

x

1 (LCDS28)

P1.x (I/O)

I: 0, O: 1

0

Timer0_A3.CCI1A

Timer0_A3.TA1

S29

0

1

0

x

1 (LCDS28)

P1.3/TA1.0/SVSOUT/S28

P1.4/TA1.0/S27

P1.x (I/O)

I: 0, O: 1

0

Timer1_A5.CCI0B

SVSOUT

0

1

0

S28

x

1 (LCDS28)

P1.x (I/O)

I: 0, O: 1

0

Timer1_A5.CCI0A

Timer1_A5.TA0

S27

0

1

x

0

1 (LCDS24)

NOTES: 1. x: Don’t care

52

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

APPLICATION INFORMATION

Port P1 pin schematic: P1.5, input/output with Schmitt trigger

Pad Logic

LCDS24

Segment Sy

P1DIR.x

0

1

Direction

0: Input

1: Output

P1OUT.x

0

1

Module X OUT

P1SEL.x

P1.5/TA0CLK/

CAOUT/S26

Bus

Keeper

EN

P1IN.x

from TA0CLK of P1.7

TA0CLK

EN

D

P1IE.x

EN

Set

P1IRQ.x

Q

P1IFG.x

P1SEL.x

P1IES.x

Interrupt

Edge Select

Port P1 (P1.5) pin functions

CONTROL BITS / SIGNALS

PIN NAME (P1.X)

X

FUNCTION

LCDS24

LCDS28

P1DIR.x

P1SEL.x

P1.5/TA0CLK/CAOUT/S26

5

P1.x (I/O)

I: 0, O: 1

0

1

x

0

Timer0_A3.TACLK

CAOUT

0

1

x

0

S26

1 (LCDS24)

NOTES: 1. x: Don’t care

2. The input TA0CLK of P1.5 and P1.7 are logically ORed. Therefore only one of them should be enabled at a time to feed in TA0CLK.

53

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

APPLICATION INFORMATION

Port P1 pin schematic: P1.6, input/output with Schmitt trigger

Pad Logic

To Comparator_A

From Comparator_A

CAPD.y

P1DIR.x

0

1

Direction

0: Input

1: Output

P1OUT.x

0

1

Module Out

P1.6/ACLK/CA0

Bus

Keeper

EN

P1SEL.x

P1IN.x

EN

D

Module X IN

P1IRQ.x

P1IE.x

EN

Set

Q

P1IFG.x

P1SEL.x

P1IES.x

Interrupt

Edge Select

Port P1 (P1.6) pin functions

CONTROL BITS / SIGNALS

PIN NAME (P1.X)

X

FUNCTION

CAPD

P1DIR.x

P1SEL.x

P1.6/ACLK/CA0

6

P1.x (I/O)

ACLK

0

I: 0, O: 1

0

1

x

0

1

x

CA0

1 (CAPD.0)

NOTES: 1. x: Don’t care

54

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

APPLICATION INFORMATION

Port P1 pin schematic: P1.7, input/output with Schmitt trigger

Pad Logic

To Comparator_A

From Comparator_A

CAPD.y

P1DIR.x

0

1

Direction

0: Input

1: Output

P1OUT.x

0

1

Module Out

P1.7/TA0CLK/

CAOUT/CA1

Bus

Keeper

EN

P1SEL.x

P1IN.x

EN

D

TA0CLK

to P1.5

P1IE.x

EN

Set

P1IRQ.x

Q

P1IFG.x

P1SEL.x

P1IES.x

Interrupt

Edge Select

Port P1 (P1.7) pin functions

CONTROL BITS / SIGNALS

PIN NAME (P1.X)

X

FUNCTION

CAPD

P1DIR.x

P1SEL.x

P1.7/TA0CLK/CAOUT/CA1

7

P1.x (I/O)

0

I: 0, O: 1

0

1

x

Timer0_A3.TACLK

CAOUT

0

1

x

0

CA1

1 (CAPD.1)

NOTES: 1. x: Don’t care

2. The input TA0CLK of P1.5 and P1.7 are combined by a logical OR. Therefore, only one of them should be enabled at a time to feed

in TA0CLK.

55

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

APPLICATION INFORMATION

Port P2 pin schematic: P2.0 to P2.7 input/output with Schmitt trigger

Pad Logic

LCDS8/12

Segment Sy

P2DIR.x

0

1

Direction

0: Input

1: Output

P2OUT.x

0

1

Module X OUT

P2.0/TA1.1/S15

P2.1/TA1.2/S14

P2.2/TA1.3/S13

P2.3/TA1.4/S12

P2.4/S11

Bus

Keeper

EN

P2SEL.x

P2IN.x

P2.5/S10

EN

P2.6/S9

P2.7/S8

Module X IN

P2IRQ.x

D

P2IE.x

EN

Set

Q

P2IFG.x

P2SEL.x

P2IES.x

Interrupt

Edge Select

56

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

Port P2 (P2.0 to P2.7) pin functions

CONTROL BITS / SIGNALS

LCDS8

PIN NAME (P2.X)

X

FUNCTION

P2DIR.x

P2SEL.x

LCDS12

P2.0/TA1.1/S15

0

P2.x (I/O)

Timer1_A5.TA1

S15

I: 0, O: 1

0

1

x

0

1

x

0

1

x

0

1

x

0

x

0

x

0

x

0

x

0

1

0

x

1 (LCDS12)

P2.1/TA1.2/S14

P2.2/TA1.3/S13

P2.3/TA1.4/S12

1

2

3

P2.x (I/O)

Timer1_A5.TA2

S14

I: 0, O: 1

0

1

0

x

1 (LCDS12)

P2.x (I/O)

Timer1_A5.TA3

S13

I: 0, O: 1

0

1

0

x

1 (LCDS12)

P2.x (I/O)

Timer1_A5.TA4

S12

I: 0, O: 1

0

1

0

x

1 (LCDS12)

P2.4/S11

P2.5/S10

P2.6/S9

P2.7/S8

4

5

6

7

P2.x (I/O)

S11

I: 0, O: 1

0

x

1 (LCDS8)

P2.x (I/O)

S10

I: 0, O: 1

0

x

1 (LCDS8)

0

P2.x (I/O)

S9

I: 0, O: 1

x

I: 0, O: 1

x

1 (LCDS8)

0

P2.x (I/O)

S8

1 (LCDS8)

NOTES: 1. x: Don’t care

57

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

APPLICATION INFORMATION

Port P3 pin schematic: P3.0 to P3.7 input/output with Schmitt trigger

Pad Logic

LCDS16/20

Segment Sy

P3DIR.x

0

1

Direction

0: Input

1: Output

P3OUT.x

0

1

Module X OUT

P3.0/TA1.2/S23

P3.1/TA1.3/S22

P3.2/TA1.4/S21

P3.3/TA0.0/TA1CLK/S20

P3.4/CAOUT/S19

P3.5/S18

Bus

Keeper

EN

P3SEL.x

P3IN.x

EN

D

P3.6/S17

P3.7/S16

Module X IN

58

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

Port P3 (P3.0 to P3.7) pin functions

CONTROL BITS / SIGNALS

LCDS16

PIN NAME (P3.X)

P3.0/TA1.2/S23

X

FUNCTION

P3DIR.x

P3SEL.x

LCDS20

0

P3.x (I/O)

Timer1_A5.CCI2A

Timer1_A5.TA2

S23

I: 0, O: 1

0

1

x

0

1

x

0

1

x

0

1

x

0

1

x

0

x

0

x

0

x

0

1

0

x

1 (LCDS20)

P3.1/TA1.3/S22

1

2

3

4

P3.x (I/O)

Timer1_A5.CCI3A

Timer1_A5.TA3

S22

I: 0, O: 1

0

1

0

x

1 (LCDS20)

P3.2/TA1.4/S21

P3.x (I/O)

Timer1_A5.CCI4A

Timer1_A5.TA4

S21

I: 0, O: 1

0

1

0

x

1 (LCDS20)

P3.3/TA0.0/TA1CLK/S20

P3.4/CAOUT/S19

P3.x (I/O)

Timer1_A5.TACLK

Timer0_A3.TA0

S20

I: 0, O: 1

0

1

0

x

1 (LCDS20)

P3.x (I/O)

CAOUT

I: 0, O: 1

0

1

0

S19

x

1 (LCDS16)

P3.5/S18

5

6

7

P3.x (I/O)

S18

I: 0, O: 1

0

x

1 (LCDS16)

0

P3.6/S17

P3.x (I/O)

S17

I: 0, O: 1

x

I: 0, O: 1

x

1 (LCDS16)

0

P3.7/S16

P3.x (I/O)

S16

1 (LCDS16)

NOTES: 1. x: Don’t care

59

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

APPLICATION INFORMATION

Port P4 pin schematic: P4.0 to P4.7 input/output with Schmitt trigger

LCDS0/4

Pad Logic

Segment Sy

P4DIR.x

0

1

Direction

0: Input

1: Output

P4OUT.x

0

1

Module X Out

P4.0/S7

P4.1/S6

Bus

Keeper

EN

P4SEL.x

P4IN.x

P4.2/S5

P4.3/S4

P4.4/S3

P4.5/S2

P4.6/S1

P4.7/ADC10CLK/S0

Port P4 (P4.0 to P4.7) pin functions

CONTROL BITS / SIGNALS

PIN NAME (P4.X)

P4.0/S7

X

FUNCTION

LCDS4

P4DIR.x

P4SEL.x

LCDS0

0

P4.x (I/O)

S7

I: 0, O: 1

0

x

0

x

0

x

0

x

0

x

0

x

0

x

0

1

x

0

x

1 (LCDS4)

P4.1/S6

1

2

3

4

5

6

7

P4.x (I/O)

S6

I: 0, O: 1

0

x

1 (LCDS4)

P4.2/S5

P4.x (I/O)

S5

I: 0, O: 1

0

x

1 (LCDS4)

P4.3/S4

P4.x (I/O)

S4

I: 0, O: 1

0

x

1 (LCDS4)

P4.4/S3

P4.x (I/O)

S3

I: 0, O: 1

0

x

1 (LCDS0)

P4.5/S2

P4.x (I/O)

S2

I: 0, O: 1

0

x

1 (LCDS0)

P4.6/S1

P4.x (I/O)

S1

I: 0, O: 1

0

x

1 (LCDS0)

P4.7/ADC10CLK/S0

P4.x (I/O)

ADC10CLK

S0

I: 0, O: 1

0

1

x

1 (LCDS0)

NOTES: 1. x: Don’t care

60

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

APPLICATION INFORMATION

Port P5 pin schematic: P5.0, input/output with Schmitt trigger

Pad Logic

LCDS24

Segment Sy

P5DIR.x

0

1

Direction

0: Input

1: Output

P5OUT.x

0

1

Module X OUT

P5.0/TA1.1/S24

Bus

Keeper

EN

P5SEL.x

P5IN.x

EN

D

Module X IN

Port P5 (P5.0) pin functions

CONTROL BITS / SIGNALS

PIN NAME (P5.X)

X

FUNCTION

P5DIR.x

P5SEL.x

LCDS24

P5.0/TA1.1/S24

0

P5.x (I/O)

I: 0, O: 1

0

1

x

0

1

Timer1_A5.CCI1A

Timer1_A5.TA1

S24

0

1

x

NOTES: 1. x: Don’t care

61

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

APPLICATION INFORMATION

Port P5 pin schematic: P5.1 to P5.7, input/output with Schmitt trigger

Pad Logic

LCD Signal

P5DIR.x

0

1

Direction

0: Input

1: Output

P5OUT.x

0/1

0

1

P5.1/R23

P5.2/R13LCDREF

P5.3/R03

Bus

Keeper

EN

P5SEL.x

P5IN.x

P5.4/COM3

P5.5/COM2

P5.6/COM1

P5.7/COM0

Port P5 (P5.1 to P5.7) pin functions

CONTROL BITS / SIGNALS

PIN NAME (P5.X)

X

FUNCTION

P5DIR.x

P5SEL.x

P5.1/R23

1

P5.x (I/O)

R23

I: 0, O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

x

P5.2/LCDREF/R13

P5.3/R03

2

3

4

5

6

7

P5.x (I/O)

R13 or LCDREF

P5.x (I/O)

R03

I: 0, O: 1

x

I: 0, O: 1

x

P5.4/COM3

P5.5/COM2

P5.6/COM1

P5.7/COM0

P5.x (I/O)

COM3

I: 0, O: 1

x

P5.x (I/O)

COM2

I: 0, O: 1

x

P5.x (I/O)

COM1

I: 0, O: 1

x

I: 0, O: 1

x

P5.x (I/O)

COM0

NOTES: 1. x: Don’t care

62

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

APPLICATION INFORMATION

Port P6 pin schematic: P6.0, input/output with Schmitt trigger

Pad Logic

To Comparator_A

From Comparator_A

CAPD.4

ADC10AE0.2

INCH=2

To ADC10

P6DIR.x

0

1

Direction

0: Input

1: Output

P6OUT.x

0

1

Module Out

P6.0/TA1.2/A2/CA4

Bus

Keeper

EN

P6SEL.x

P6IN.x

EN

D

Module X IN

Port P6 (P6.0) pin functions

CONTROL BITS / SIGNALS

PIN NAME (P6.X)

X

FUNCTION

CAPD

ADC10AE0.y

P6DIR.x

P6SEL.x

P6.0/TA1.2/A2/CA4

0

P6.x (I/O)

0

I: 0, O: 1

0

1

x

Timer1_A5.TA2

0

1 (y=2)

x

1

x

A2

x

CA4

1 (CAPD.4)

NOTES: 1. x: Don’t care

63

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

APPLICATION INFORMATION

Port P6 pin schematic: P6.1 and P6.2, inpututput with Schmitt trigger

Pad Logic

P6DIR.x

0

1

Direction

0: Input

1: Output

Module

direction

P6OUT.x

0

1

Module X OUT

P6.1/UCB0SOMI/UCB0SCL

P6.2/UCB0SIMO/UCB0SDA

P6SEL.x

P6IN.x

EN

D

Module X IN

Port P6 (P6.1 and P6.2) pin functions

CONTROL BITS / SIGNALS

PIN NAME (P6.X)

X

FUNCTION

P6DIR.x

P6SEL.x

P6.1/UCB0SOMI/UCB0SCL

1

P6.x (I/O)

I: 0, O: 1

0

1

0

1

UCB0SOMI/UCB0SCL (see Note 2)

P6.x (I/O)

x

I: 0, O: 1

x

P6.2/UCB0SIMO/UCB0SDA

NOTES: 1. x: Don’t care

2

UCB0SIMO/UCB0SDA (see Note 2)

2. The pin direction is controlled by the USCI module.

64

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

APPLICATION INFORMATION

Port P6 pin schematic: P6.3 and P6.4, input/output with Schmitt trigger

Pad Logic

To Comparator_A

From Comparator_A

CAPD.5/6

ADC10AE0.3/4

INCH=3/4

To ADC10

P6DIR.x

0

1

Direction

0: Input

from Module

1: Output

P6OUT.x

0

1

Module Out

P6.3/UCB0STE/

UCA0CLK/A3/CA5/

V_eref-/V_ref-

Bus

Keeper

EN

P6SEL.x

P6IN.x

P6.4/UCB0CLK/

UCA0STE/A4/CA6/

V_eref+/V_ref+

EN

D

Module X IN

Port P6 (P6.3 and P6.4) pin functions

CONTROL BITS / SIGNALS

PIN NAME (P6.X)

X

FUNCTION

CAPD

ADC10AE0.y

P6DIR.x

P6SEL.x

P6.3/UCB0STE/

3

P6.x (I/O)

UCB0STE/UCA0CLK (see Note 2)

0

I: 0, O: 1

0

1

x

0

1

x

UCA0CLK/A3/CA5/

0

x

/V

eref-- ref--

A3/V

CA5

/V

x

1 (y=3)

x

eref-- ref--

1 (CAPD.5)

x

P6.4/UCB0CLK/

4

P6.x (I/O)

0

I: 0, O: 1

UCA0STE/A4/CA6/

UCB0CLK/UCA0STE (see Note 2)

0

1 (y=4)

x

/V

eref+ ref+

A4/V

CA6

/V

x

eref+ ref+

1 (CAPD.6)

NOTES: 1. x: Don’t care

2. The pin direction is controlled by the USCI module.

65

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

APPLICATION INFORMATION

Port P6 pin schematic: P6.5 and P6.6, input/output with Schmitt trigger

INCHx = 5/6

To ADC10

Pad Logic

ADC10AE0.5/6

P6DIR.x

0

1

Direction

0: Input

Module

direction

1: Output

P6OUT.x

0

1

Module X OUT

P6.5/UCA0RXD/

UCA0SOMI/A5

P6.6/UCA0TXD/

UCA0SIMO/A6

Bus

Keeper

EN

P6SEL.x

P6IN.x

EN

D

Module X IN

Port P6 (P6.5 and P6.6) pin functions

CONTROL BITS / SIGNALS

PIN NAME (P6.X)

X

FUNCTION

ADC10AE0.y

P6DIR.x

P6SEL.x

P6.5/UCA0RXD/

UCA0SOMI/A5

5

P6.x (I/O)

0

I: 0, O: 1

0

1

x

0

1

x

UCA0RXD/UCA0SOMI (see Note 2)

0

1 (y=5)

0

x

A5

x

P6.6/UCA0TXD/

UCA0SIMO/A6

6

P6.x (I/O)

I: 0, O: 1

UCA0TXD/UCA0SIMO (see Note 2)

A6

0

x

1 (y=6)

NOTES: 1. x: Don’t care

2. The pin direction is controlled by the USCI module.

66

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

APPLICATION INFORMATION

Port P6 pin schematic: P6.7, input/output with Schmitt trigger

Pad Logic

to SVS Mux

VLD = 15

To Comparator_A

From Comparator_A

CAPD.7

ADC10AE0.7

INCH=7

To ADC10

P6DIR.x

0

1

Direction

0: Input

1: Output

P6OUT.x

0/1

0

1

P6.7/A7/CA7/SVSIN

Bus

Keeper

EN

P6SEL.x

P6IN.x

Port P6 (P6.7) pin functions

CONTROL BITS / SIGNALS

PIN NAME (P6.X)

X

FUNCTION

VLDx = 15

CAPD

ADC10AE0

P6DIR.x

P6SEL.x

P6.7/A7/CA7/SVSIN

7

P7.x (I/O)

0

1

0

I: 0, O: 1

0

x

A7

x

1 (y = 7)

x

CA7

SVSIN

1 (CAPD.7)

0

x

0

NOTES: 1. x: Don’t care

67

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

/APPLICATION INFORMATION

Port P7 pin schematic: P7.0 to P7.3, input/output with Schmitt trigger

Pad Logic

Sy

LCDS32

P7DIR.x

0

1

Direction

0: Input

1: Output

P7OUT.x

0/1

0

1

P7.0/TDO/TDI/S32

P7.1/TDI/TCLK/S33

P7.2/TMS/S34

Bus

Keeper

EN

P7SEL.x

P7IN.x

P7.3/TCK/S35

To JTAG

From JTAG

Port P7 (P7.0 to P7.3) pin functions

CONTROL BITS / SIGNALS

PIN NAME (P7.X)

X

FUNCTION

JTAG Mode

P7DIR.x

P7SEL.x

LCDS32

P7.0/TDO/TDI/S32

0

P7.x (I/O)

0

1

0

1

0

1

0

1

0

I: 0, O: 1

0

x

0

x

0

x

0

x

0

x

1

0

x

1

0

x

1

0

x

1

TDO/TDI (see Note 1)

S32

x

P7.1/TDI/TCLK/S33

P7.2/TMS/S34

1

2

3

P7.x (I/O)

I: 0, O: 1

TDI/TCLK (see Note 1)

S33

x

P7.x (I/O)

I: 0, O: 1

TMS (see Note 1)

S34

x

P7.3/TCK/S35

P7.3 (I/O)

I: 0, O: 1

TCK (see Note 1)

S35

x

NOTES: 1. In JTAG Mode the internal pullup/pulldown resistors are disabled.

2. X: Don’t care.

68

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

APPLICATION INFORMATION

Port P7 pin schematic: P7.4 and P7.5, input/output with Schmitt trigger

Pad Logic

To Comparator_A

From Comparator_A

CAPD.2/3

ADC10AE0.0/1

INCH=0/1

To ADC10

P7DIR.x

0

1

Direction

0: Input

1: Output

P7OUT.x

0

1

Module Out

P7.4/TA1.4/A0/CA2

P7.5/TA1.3/A1/CA3

Bus

Keeper

EN

P7SEL.x

P7IN.x

EN

D

Module X IN

Port P7 (P7.4 and P7.5) pin functions

CONTROL BITS / SIGNALS

PIN NAME (P7.X)

X

FUNCTION

CAPD

ADC10AE0.y

P7DIR.x

P7SEL.x

P7.4/TA1.4/A0/CA2

4

P7.x (I/O)

0

I: 0, O: 1

0

1

x

0

1

x

Timer1_A5.TA4

0

1

Timer1_A5.CCI4B

0

A0

x

1 (y=0)

x

CA2

1 (CAPD.2)

x

P7.5/TA1.3/A1/CA3

5

P7.x (I/O)

Timer1_A5.TA3

Timer1_A5.CCI3B

A1

0

I: 0, O: 1

0

1

0

x

0

1 (y=1)

x

CA3

1 (CAPD.3)

NOTES: 1. x: Don’t care

69

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

APPLICATION INFORMATION

Port P7 pin schematic: P7.6, input/output with Schmitt trigger

Pad Logic

LCDS24

Segment Sy

P7DIR.x

0

1

Direction

0: Input

1: Output

P7OUT.x

0

1

Module X OUT

P7.6/TA0.2/S25

Bus

Keeper

EN

P7SEL.x

P7IN.x

EN

D

Module X IN

Port P7 (P7.6) pin functions

CONTROL BITS / SIGNALS

PIN NAME (P7.X)

X

FUNCTION

P7DIR.x

P7SEL.x

LCDS24

P7.6/TA0.2/S25

6

P7.x (I/O)

I: 0, O: 1

0

1

x

0

1

Timer0_A3.CCI2A

Timer0_A3.TA2

S25

0

1

x

NOTES: 1. x: Don’t care

70

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

APPLICATION INFORMATION

JTAG pins: TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger

TDO

Controlled by JTAG

JTAG

TDO/TDI

Controlled

by JTAG

DV

CC

TDI

Fuse

Burn & Test

Fuse

Test

and

TDI/TCLK

DV

CC

Emulation

Module

TMS

TCK

TMS

TCK

DV

CC

During Programming Activity and

During Blowing of the Fuse, Pin

TDO/TDI Is Used to Apply the Test

Input Data for JTAG Circuitry

JTAG fuse check mode

For details on the JTAG fuse check mode, see the MSP430 Memory Programming User’s Guide (SLAU265)

chapter ”Fuse Check and Reset of the JTAG State Machine (TAP Controller)”.

71

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648D -- APRIL 2009 -- REVISED SEPTEMBER 2010

Data Sheet Revision History

LITERATURE

NUMBER

SUMMARY

SLAS648

Production Data release

Changed TDI/TCLK to TEST in Note 1 of “absolute maximum ratings” table (page 23)

SLAS648A

Changed lower limit of Storage temperature, Programmed device from --40°C to --55°C in “absolute maximum ratings”

table (page 23)

Corrected Timer_A3 Signal Connections and Timer_A5 Signal Connections tables (pages 17, 18)

SLAS648B

SLAS648C

Removed bullet indicating that Segment A contains calibration data (page 15)

Added note to functional block diagram (page 5)

In “absolute maximum ratings” table, changed LFXT1 crystal frequency, f

MIN from 450 to 0.45 MHz (with

(LFXT1)

ceramic resonator) and from 1000 to 1 MHz (with crystal) (page 23)

SLAS648D

In “crystal oscillator, LFXT1, high frequency modes” table, changed f

crystal resonator (page 36)

MAX from 8 to 6 MHz for both ceramic and

LFXT1

72

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Oct-2010

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

MSP430F4132IPMR

MSP430F4152IPMR

LQFP

PM

64

1000

330.0

24.4

12.3

2.5

16.0

24.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Oct-2010

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

MSP430F4132IPMR

MSP430F4152IPMR

LQFP

PM

64

1000

346.0

41.0

Pack Materials-Page 2

MECHANICAL DATA

MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996

PM (S-PQFP-G64)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

M

0,08

33

48

49

32

64

17

0,13 NOM

1

16

7,50 TYP

Gage Plane

10,20

SQ

9,80

0,25

12,20

SQ

0,05 MIN

0°–7°

11,80

1,45

1,35

0,75

0,45

Seating Plane

0,08

1,60 MAX

4040152/C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

D. May also be thermally enhanced plastic with leads connected to the die pads.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	M430F4152
厂家：	TEXAS INSTRUMENTS
描述：	- 12号的铝制车身绘（ RAL 7032 ）
文件：	总81页 (文件大小：1552K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M430F4152 [TI]

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