M430F5438AMZCARET_技术文档

MSP430F5438A-ET

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SLASEU5A – OCTOBER 2019 – REVISED FEBRUARY 2021

MSP430F5438A-ET Mixed-Signal Controller

•

16-bit timer TA0, Timer_A with five capture/

compare registers

16-bit timer TA1, Timer_A with three capture/

compare registers

16-bit timer TB0, Timer_B with seven capture/

compare shadow registers

Up to four universal serial communication

interfaces

1 Features

•

Extended temperature version -ET uses silicon

revision H

Low supply voltage range:

3.6 V down to 1.8 V

Ultralow power consumption

– Active mode (AM):

all system clocks active

230 µA/MHz at 8 MHz, 3.0 V, flash program

execution (typical)

110 µA/MHz at 8 MHz, 3.0 V, RAM program

execution (typical)

– USCI_A0, USCI_A1, USCI_A2, and USCI_A3

each supporting

•

Enhanced UART supporting automatic

baud-rate detection

•

IrDA encoder and decoder

Synchronous SPI

– Standby mode (LPM3):

real-time clock with crystal, watchdog, and

supply supervisor operational, full RAM

retention, fast wake-up:

1.7 µA at 2.2 V, 2.1 µA at 3.0 V (typical)

low-power oscillator (VLO), general-purpose

counter, watchdog, and supply supervisor

operational, full RAM retention, fast wake-up:

1.2 µA at 3.0 V (typical)

– USCI_B0, USCI_B1, USCI_B2, and USCI_B3

each supporting

•

I²C

Synchronous SPI

•

12-bit analog-to-digital converter (ADC)

– Internal reference

– Sample-and-hold

– Off mode (LPM4):

– Autoscan feature

full RAM retention, supply supervisor

operational, fast wake-up:

1.2 µA at 3.0 V (typical)

– 14 external channels, 2 internal channels

Hardware multiplier supporting 32-bit operations

Serial onboard programming, no external

programming voltage needed

•

– Shutdown mode (LPM4.5):

0.1 µA at 3.0 V (typical)

•

3-channel internal DMA

•

Wake-up from standby mode in 3.5 µs (typical)

16-bit RISC architecture

Basic timer with real-time clock feature

Wide operational range: –40°C to 125°C (Q temp),

–55°C to 125°C (M temp) (some noted parameters

specified for –40°C to 85°C only)

Available SnAgCu (ZCA) or SnPb (GCA) ball

material

– Extended memory

– Up to 25-MHz system clock

Flexible power management system

– Fully integrated LDO with programmable

regulated core supply voltage

– Supply voltage supervision, monitoring, and

brownout

•

2 Applications

•

Supports defense, aerospace, and medical

applications

Unified clock system

– FLL control loop for frequency stabilization

– Low-power low-frequency internal clock source

(VLO)

– Controlled baseline

– One assembly and test site

– One fabrication site

– Low-frequency trimmed internal reference

source (REFO)

– Available in extended (–55°C to 125°C)

temperature range

– 32-kHz crystals

– High-frequency crystals up to 32 MHz ¹

– Extended product life cycle

– Extended product-change notification

– Product traceability

1

Use of crystals is not ensured above 85°C for both 32-kHz and high-frequency crystals.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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3 Description

The MSP430F5438A-ET is an ultralow-power microcontroller. The architecture, combined with extensive low-

power modes, is optimized to achieve extended battery life in portable measurement applications. The device

features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code

efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in

3.5 µs (typical).

The MSP430F5438A-ET is a microcontroller configuration with three 16-bit timers, a high-performance 12-bit

analog-to-digital converter (ADC), up to 4 universal serial communication interfaces (USCIs), a hardware

multiplier, a DMA, a real-time clock (RTC) module with alarm capabilities, and up to 87 I/O pins. For complete

module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide.

Typical applications for this device include analog and digital sensor systems, digital motor control, remote

controls, thermostats, digital timers, and hand-held meters.

Device Information

PART NUMBER ⁽¹⁾

M430F5438AQZCARET

PACKAGE

BODY SIZE ⁽²⁾

7 mm × 7 mm

nFBGA (113)

M430F5438AMZCARET

M430F5438AQGCARET

M430F5438AMGCARET

M430F5438AQZQWRET⁽³⁾

nFBGA (113)

MicroStar Junior^™BGA (113)

(1) For the most current part, package, and ordering information, see the Package Option Addendum in Mechanical, Packaging, and

Orderable Information, or see the TI website at www.ti.com.

(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Mechanical,

Packaging, and Orderable Information.

(3) All orderable part numbers in the ZQW (MicroStar Junior BGA) package have been changed to a status of Last Time Buy. Visit the

Product life cycle page for details on this status.

2

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4 Functional Block Diagram

Figure 4-1 shows the functional block diagram.

PA

PB

PC

PD

PE

PF

P11.x

XIN XOUT

DVCC DVSS AVCC AVSS

RST/NMI

P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x P10.x

XT2IN

I/O Ports

Power

Management

ACLK

SMCLK

I/O Ports

P3, P4

2×8 I/Os

I/O Ports

P5, P6

2×8 I/Os

I/O Ports

P7, P8

2×8 I/Os

I/O Ports

P9, P10

2×8 I/Os

I/O Ports

P11

1×3 I/Os

Unified

Clock

System

P1, P2

2×8 I/Os

Interrupt

Capability

256KB

192KB

128KB

SYS

16KB

RAM

XT2OUT

Watchdog

LDO

SVM, SVS

Brownout

PB

1×16 I/Os

PC

1×16 I/Os

PD

1×16 I/Os

PE

1×16 I/Os

PF

1×3 I/Os

Flash

PA

1×16 I/Os

MCLK

MAB

MDB

CPUXV2

and

Working

Registers

DMA

3 Channel

EEM

(L: 8+2)

ADC12_A

USCI0,1,2,3

12 bit

200 ksps

TA0

TA1

TB0

USCI_Ax:

UART,

IrDA, SPI

JTAG,

SBW

Interface

RTC_A

MPY32

CRC16

REF

Timer_A

5 CC

Registers

Timer_A

3 CC

Registers

Timer_B

7 CC

Registers

16 channels

(14 ext, 2 int)

Autoscan

UCSI_Bx:

SPI, I²C

Figure 4-1. MSP430F5438-ET Functional Block Diagram

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................2

4 Functional Block Diagram.............................................. 3

5 Revision History.............................................................. 4

6 Terminal Configuration and Functions..........................5

6.1 Pin Diagram................................................................ 5

6.2 Signal Descriptions..................................................... 5

7 Specifications................................................................ 10

7.1 Absolute Maximum Ratings...................................... 10

7.2 Recommended Operating Conditions.......................11

7.3 Active Mode Supply Current Into V_CCExcluding

7.26 Wakeup From Low-Power Modes and Reset......... 25

7.27 Timer_A...................................................................26

7.28 Timer_B...................................................................26

7.29 USCI (UART Mode) Recommended Operating

Conditions................................................................... 26

7.30 USCI (UART Mode)................................................ 26

7.31 USCI (SPI Master Mode) Recommended

Operating Conditions...................................................26

7.32 USCI (SPI Master Mode)........................................ 27

7.33 USCI (SPI Slave Mode).......................................... 29

7.34 USCI (I²C Mode).....................................................31

7.35 12-Bit ADC, Power Supply and Input Range

External Current.......................................................... 12

Conditions................................................................... 32

7.36 12-Bit ADC, Timing Parameters..............................32

7.37 12-Bit ADC, Linearity Parameters Using an

External Reference Voltage or AVCC as

Reference Voltage.......................................................33

7.38 12-Bit ADC, Linearity Parameters Using the

7.4 Low-Power Mode Supply Currents (Into V_CC

)

Excluding External Current..........................................12

7.5 Thermal Resistance Characteristics......................... 13

7.6 Schmitt-Trigger Inputs – General Purpose I/O..........13

7.7 Inputs – Ports P1 and P2..........................................13

7.8 Leakage Current – General Purpose I/O.................. 14

7.9 Outputs – General Purpose I/O (Full Drive

Internal Reference Voltage..........................................33

7.39 12-Bit ADC, Temperature Sensor and Built-In

Strength)......................................................................14

7.10 Outputs – General Purpose I/O (Reduced Drive

Strength)......................................................................14

7.11 Output Frequency – General Purpose I/O.............. 15

7.12 Typical Characteristics – Outputs, Reduced

V_MID............................................................................34

7.40 REF, External Reference........................................ 34

7.41 REF, Built-In Reference.......................................... 35

7.42 Flash Memory......................................................... 36

7.43 JTAG and Spy-Bi-Wire Interface.............................36

8 Detailed Description......................................................37

8.1 CPU.......................................................................... 37

8.2 Operating Modes...................................................... 38

8.3 Interrupt Vector Addresses....................................... 39

8.4 Memory Organization................................................40

8.5 Bootloader (BSL)...................................................... 41

8.6 JTAG Operation........................................................ 41

8.7 Flash Memory........................................................... 42

8.8 RAM Memory............................................................42

8.9 Peripherals................................................................42

8.10 Device Descriptors (TLV)........................................85

9 Device and Documentation Support............................88

9.1 Trademarks...............................................................88

9.2 Electrostatic Discharge Caution................................88

9.3 Support Resources................................................... 88

9.4 Glossary....................................................................88

Drive Strength (PxDS.y = 0)........................................15

7.13 Typical Characteristics – Outputs, Full Drive

Strength (PxDS.y = 1)................................................. 16

7.14 Crystal Oscillator, XT1, Low-Frequency Mode........17

7.15 Crystal Oscillator, XT1, High-Frequency Mode.......18

7.16 Crystal Oscillator, XT2............................................ 20

7.17 Internal Very-Low-Power Low-Frequency

Oscillator (VLO)...........................................................21

7.18 Internal Reference, Low-Frequency Oscillator

(REFO)........................................................................21

7.19 DCO Frequency......................................................21

7.20 PMM, Brownout Reset (BOR).................................23

7.21 PMM, Core Voltage.................................................23

7.22 PMM, SVS High Side..............................................23

7.23 PMM, SVM High Side............................................. 24

7.24 PMM, SVS Low Side...............................................25

7.25 PMM, SVM Low Side..............................................25

5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (October 2019) to Revision A (February 2021)

Page

•

Updated the numbering format for tables, figures, and cross references throughout the document..................1

Added information for nFBGA (ZCA and GCA) packages; added a note the status of the MicroStar Junior

BGA (ZQW) package..........................................................................................................................................1

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6 Terminal Configuration and Functions

6.1 Pin Diagram

Figure 6-1 shows the pinout for the 113-pin ZCA, GCA, and ZQW packages. Only the default signal names are

shown here; for all multiplexed signals, see Section 6.2.

P6.4

A1

P6.2

A2

RST

A3

PJ.1

A4

P5.3

A5

P5.2 P11.2 P11.0 P10.6 P10.4 P10.1 P9.7

A6

A7

A8

A9

A10

A11

A12

P6.6

B1

P6.3

B2

P6.1

B3

PJ.3

B4

PJ.0 DVSS4 DVCC4 P10.7 P10.5 P10.3 P9.6

P9.5

B12

B5

B6

B7

B8

B9

B10

B11

P7.5

C1

P6.7

C2

P9.4

C11

P9.2

C12

C3

P5.0

D1

P7.6

D2

P6.0

D4

PJ.2 TEST P11.1 P10.2 P10.0

P9.0

D11

P8.7

D12

D5

E5

F5

G5

H5

D6

D7

D8

E8

F8

G8

H8

D9

P5.1 AVCC

E1 E2

P6.5

E4

P9.3

E9

P8.6 DVCC2

E11 E12

E6

E7

P7.0 AVSS

F1 F2

P7.4

F4

P9.1

F9

P8.5 DVSS2

F11 F12

P7.1 DVSS1

G1 G2

P7.7

G4

P8.3

G9

P8.4 VCORE

G11

G12

P1.0 DVCC1

P1.1

H4

P8.0

H9

P8.1

H11

P8.2

H12

H1

H2

H6

H7

P1.3

J1

P1.4

J2

P1.2

J4

P2.7

J5

P3.2

J6

P3.5

J7

P4.0

J8

P5.5

J9

P7.2

J11

P7.3

J12

P1.5

K1

P1.6

K2

P5.6

K11

P5.7

K12

P1.7

L1

P2.1

L2

P2.3

L3

P2.5

L4

P3.0

L5

P3.3

L6

P3.4

L7

P3.7

L8

P4.2

L9

P4.3

L10

P4.5

L11

P5.4

L12

P2.0

M1

P2.2

M2

P2.4

M3

P2.6

M4

P3.1 DVSS3 DVCC3 P3.6

M7

M5 M6 M8

P4.1

M9

P4.4

M10

P4.6

M11

P4.7

M12

Figure 6-1. 113-Pin ZCA, GCA or ZQW Package (Top View)

6.2 Signal Descriptions

Table 6-1 describes the signals.

Table 6-1. Signal Descriptions

SIGNAL NAME

NO.

I/O

DESCRIPTION

General-purpose digital I/O

Analog input A4 – ADC

P6.4/A4

P6.5/A5

P6.6/A6

P6.7/A7

A1

I/O

General-purpose digital I/O

Analog input A5 – ADC

E4

B1

C2

F4

C1

D2

G4

General-purpose digital I/O

Analog input A6 – ADC

General-purpose digital I/O

Analog input A7 – ADC

General-purpose digital I/O

Analog input A12 –ADC

P7.4/A12

P7.5/A13

P7.6/A14

P7.7/A15

General-purpose digital I/O

Analog input A13 – ADC

General-purpose digital I/O

Analog input A14 – ADC

General-purpose digital I/O

Analog input A15 – ADC

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Table 6-1. Signal Descriptions (continued)

SIGNAL NAME

NO.

I/O

DESCRIPTION

General-purpose digital I/O

Analog input A8 – ADC

Output of reference voltage to the ADC

Input for an external reference voltage to the ADC

P5.0/A8/VREF+/VeREF+

D1

I/O

General-purpose digital I/O

Analog input A9 – ADC

Negative terminal for the ADC's reference voltage for both sources, the internal

reference voltage, or an external applied reference voltage

P5.1/A9/VREF-/VeREF-

E1

AVCC

AVSS

E2

F2

Analog power supply

Analog ground supply

General-purpose digital I/O

Input terminal for crystal oscillator XT1

P7.0/XIN

F1

I/O

General-purpose digital I/O

Output terminal of crystal oscillator XT1

P7.1/XOUT

G1

DVSS1

DVCC1

G2

H2

Digital ground supply

Digital power supply

General-purpose digital I/O with port interrupt

TA0 clock signal TACLK input

ACLK output (divided by 1, 2, 4, 8, 16, or 32)

P1.0/TA0CLK/ACLK

P1.1/TA0.0

H1

H4

J4

I/O

General-purpose digital I/O with port interrupt

TA0 CCR0 capture: CCI0A input, compare: Out0 output

BSL transmit output

General-purpose digital I/O with port interrupt

TA0 CCR1 capture: CCI1A input, compare: Out1 output

BSL receive input

P1.2/TA0.1

General-purpose digital I/O with port interrupt

TA0 CCR2 capture: CCI2A input, compare: Out2 output

P1.3/TA0.2

P1.4/TA0.3

P1.5/TA0.4

J1

J2

K1

I/O

General-purpose digital I/O with port interrupt

TA0 CCR3 capture: CCI3A input compare: Out3 output

General-purpose digital I/O with port interrupt

TA0 CCR4 capture: CCI4A input, compare: Out4 output

General-purpose digital I/O with port interrupt

SMCLK output

P1.6/SMCLK

P1.7

K2

L1

I/O

General-purpose digital I/O with port interrupt

TA1 clock signal TA1CLK input

MCLK output

P2.0/TA1CLK/MCLK

M1

I/O

General-purpose digital I/O with port interrupt

TA1 CCR0 capture: CCI0A input, compare: Out0 output

P2.1/TA1.0

P2.2/TA1.1

P2.3/TA1.2

L2

M2

L3

I/O

General-purpose digital I/O with port interrupt

TA1 CCR1 capture: CCI1A input, compare: Out1 output

General-purpose digital I/O with port interrupt

TA1 CCR2 capture: CCI2A input, compare: Out2 output

General-purpose digital I/O with port interrupt

RTCCLK output

P2.4/RTCCLK

P2.5

M3

L4

I/O

General-purpose digital I/O with port interrupt

ACLK output (divided by 1, 2, 4, 8, 16, or 32)

P2.6/ACLK

M4

General-purpose digital I/O with port interrupt

Conversion clock output ADC

DMA external trigger input

P2.7/ADC12CLK/DMAE0

P3.0/UCB0STE/UCA0CLK

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J5

L5

I/O

General-purpose digital I/O

Slave transmit enable – USCI_B0 SPI mode

Clock signal input – USCI_A0 SPI slave mode

Clock signal output – USCI_A0 SPI master mode

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Table 6-1. Signal Descriptions (continued)

SIGNAL NAME

NO.

I/O

DESCRIPTION

General-purpose digital I/O

P3.1/UCB0SIMO/UCB0SDA

P3.2/UCB0SOMI/UCB0SCL

M5

I/O

Slave in, master out – USCI_B0 SPI mode

I2C data – USCI_B0 I2C mode

General-purpose digital I/O

Slave out, master in – USCI_B0 SPI mode

I2C clock – USCI_B0 I2C mode

J6

L6

I/O

General-purpose digital I/O

Clock signal input – USCI_B0 SPI slave mode

Clock signal output – USCI_B0 SPI master mode

Slave transmit enable – USCI_A0 SPI mode

P3.3/UCB0CLK/UCA0STE

DVSS3

DVCC3

M6

M7

Digital ground supply

Digital power supply

General-purpose digital I/O

P3.4/UCA0TXD/UCA0SIMO

P3.5/UCA0RXD/UCA0SOMI

L7

J7

I/O

Transmit data – USCI_A0 UART mode

Slave in, master out – USCI_A0 SPI mode

General-purpose digital I/O

Receive data – USCI_A0 UART mode

Slave out, master in – USCI_A0 SPI mode

General-purpose digital I/O

Slave transmit enable – USCI_B1 SPI mode

Clock signal input – USCI_A1 SPI slave mode

Clock signal output – USCI_A1 SPI master mode

P3.6/UCB1STE/UCA1CLK

P3.7/UCB1SIMO/UCB1SDA

M8

L8

I/O

General-purpose digital I/O

Slave in, master out – USCI_B1 SPI mode

I2C data – USCI_B1 I2C mode

General-purpose digital I/O

TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

P4.0/TB0.0

P4.1/TB0.1

P4.2/TB0.2

P4.3/TB0.3

P4.4/TB0.4

P4.5/TB0.5

P4.6/TB0.6

J8

M9

I/O

General-purpose digital I/O

TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

General-purpose digital I/O

TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

L9

General-purpose digital I/O

TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output

L10

M10

L11

M11

General-purpose digital I/O

TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output

General-purpose digital I/O

TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output

General-purpose digital I/O

TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output

General-purpose digital I/O

TB0 clock input

SMCLK output

P4.7/TB0CLK/SMCLK

M12

L12

I/O

General-purpose digital I/O

Slave out, master in – USCI_B1 SPI mode

I2C clock – USCI_B1 I2C mode

P5.4/UCB1SOMI/UCB1SCL

General-purpose digital I/O

Clock signal input – USCI_B1 SPI slave mode

Clock signal output – USCI_B1 SPI master mode

Slave transmit enable – USCI_A1 SPI mode

P5.5/UCB1CLK/UCA1STE

J9

I/O

General-purpose digital I/O

P5.6/UCA1TXD/UCA1SIMO

P5.7/UCA1RXD/UCA1SOMI

K11

K12

I/O

Transmit data – USCI_A1 UART mode

Slave in, master out – USCI_A1 SPI mode

General-purpose digital I/O

Receive data – USCI_A1 UART mode

Slave out, master in – USCI_A1 SPI mode

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Table 6-1. Signal Descriptions (continued)

SIGNAL NAME

NO.

I/O

DESCRIPTION

General-purpose digital I/O

P7.2/TB0OUTH/SVMOUT

J11

I/O

Switch all PWM outputs high impedance – Timer TB0

SVM output

General-purpose digital I/O

TA1 CCR2 capture: CCI2B input, compare: Out2 output

P7.3/TA1.2

P8.0/TA0.0

P8.1/TA0.1

P8.2/TA0.2

P8.3/TA0.3

P8.4/TA0.4

VCORE⁽²⁾

J12

H9

I/O

General-purpose digital I/O

TA0 CCR0 capture: CCI0B input, compare: Out0 output

General-purpose digital I/O

TA0 CCR1 capture: CCI1B input, compare: Out1 output

H11

H12

G9

General-purpose digital I/O

TA0 CCR2 capture: CCI2B input, compare: Out2 output

General-purpose digital I/O

TA0 CCR3 capture: CCI3B input, compare: Out3 output

General-purpose digital I/O

TA0 CCR4 capture: CCI4B input, compare: Out4 output

G11

G12

Regulated core power supply output (internal use only, no external current

loading)

DVSS2

DVCC2

F12

E12

Digital ground supply

Digital power supply

General-purpose digital I/O

TA1 CCR0 capture: CCI0B input, compare: Out0 output

P8.5/TA1.0

F11

I/O

General-purpose digital I/O

TA1 CCR1 capture: CCI1B input, compare: Out1 output

P8.6/TA1.1

P8.7

E11

D12

I/O

General-purpose digital I/O

Slave transmit enable – USCI_B2 SPI mode

Clock signal input – USCI_A2 SPI slave mode

Clock signal output – USCI_A2 SPI master mode

P9.0/UCB2STE/UCA2CLK

D11

I/O

General-purpose digital I/O

P9.1/UCB2SIMO/UCB2SDA

P9.2/UCB2SOMI/UCB2SCL

F9

I/O

Slave in, master out – USCI_B2 SPI mode

I2C data – USCI_B2 I2C mode

General-purpose digital I/O

Slave out, master in – USCI_B2 SPI mode

I2C clock – USCI_B2 I2C mode

C12

General-purpose digital I/O

Clock signal input – USCI_B2 SPI slave mode

Clock signal output – USCI_B2 SPI master mode

Slave transmit enable – USCI_A2 SPI mode

P9.3/UCB2CLK/UCA2STE

E9

I/O

General-purpose digital I/O

P9.4/UCA2TXD/UCA2SIMO

P9.5/UCA2RXD/UCA2SOMI

C11

B12

I/O

Transmit data – USCI_A2 UART mode

Slave in, master out – USCI_A2 SPI mode

General-purpose digital I/O

Receive data – USCI_A2 UART mode

Slave out, master in – USCI_A2 SPI mode

P9.6

P9.7

B11

A12

I/O

General-purpose digital I/O

Slave transmit enable – USCI_B3 SPI mode

Clock signal input – USCI_A3 SPI slave mode

Clock signal output – USCI_A3 SPI master mode

P10.0/UCB3STE/UCA3CLK

P10.1/UCB3SIMO/UCB3SDA

D9

I/O

General-purpose digital I/O

Slave in, master out – USCI_B3 SPI mode

I2C data – USCI_B3 I2C mode

A11

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Table 6-1. Signal Descriptions (continued)

SIGNAL NAME

NO.

I/O

DESCRIPTION

General-purpose digital I/O

P10.2/UCB3SOMI/UCB3SCL

P10.3/UCB3CLK/UCA3STE

D8

I/O

Slave out, master in – USCI_B3 SPI mode

I2C clock – USCI_B3 I2C mode

General-purpose digital I/O

Clock signal input – USCI_B3 SPI slave mode

Clock signal output – USCI_B3 SPI master mode

Slave transmit enable – USCI_A3 SPI mode

B10

I/O

General-purpose digital I/O

P10.4/UCA3TXD/UCA3SIMO

P10.5/UCA3RXD/UCA3SOMI

A10

B9

I/O

Transmit data – USCI_A3 UART mode

Slave in, master out – USCI_A3 SPI mode

General-purpose digital I/O

Receive data – USCI_A3 UART mode

Slave out, master in – USCI_A3 SPI mode

P10.6

P10.7

A9

B8

I/O

General-purpose digital I/O

ACLK output (divided by 1, 2, 4, 8, 16, or 32)

P11.0/ACLK

P11.1/MCLK

P11.2/SMCLK

A8

D7

A7

I/O

General-purpose digital I/O

MCLK output

General-purpose digital I/O

SMCLK output

DVCC4

DVSS4

B7

B6

Digital power supply

Digital ground supply

General-purpose digital I/O

Input terminal for crystal oscillator XT2

P5.2/XT2IN

A6

A5

D6

B5

A4

D5

B4

I/O

I

General-purpose digital I/O

Output terminal of crystal oscillator XT2

P5.3/XT2OUT

TEST/SBWTCK⁽³⁾

PJ.0/TDO⁽⁴⁾

Test mode pin – Selects four wire JTAG operation.

Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated

General-purpose digital I/O

JTAG test data output port

I/O

General-purpose digital I/O

JTAG test data input or test clock input

PJ.1/TDI/TCLK⁽⁴⁾

PJ.2/TMS⁽⁴⁾

General-purpose digital I/O

JTAG test mode select

General-purpose digital I/O

JTAG test clock

PJ.3/TCK⁽⁴⁾

Reset input active low

Non-maskable interrupt input

RST/NMI/SBWTDIO⁽³⁾

A3

I/O

Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated.

General-purpose digital I/O

Analog input A0 – ADC

P6.0/A0

P6.1/A1

P6.2/A2

D4

B3

A2

I/O

General-purpose digital I/O

Analog input A1 – ADC

General-purpose digital I/O

Analog input A2 – ADC

General-purpose digital I/O

Analog input A3 – ADC

P6.3/A3

B2

(1)

Reserved

(1) C3, E5, E6, E7, E8, F5, F8, G5, G8, H5, H6, H7, H8 are reserved and should be connected to ground.

(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended

capacitor value, C_VCORE

.

(3) See Section 8.5 and Section 8.6 for use with BSL and JTAG functions, respectively.

(4) See Section 6.2 for use with JTAG function.

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

Voltage applied at V_CCto V_SS

–0.3 V to 4.1 V

Voltage applied to any pin (excluding VCORE) ⁽²⁾

Diode current at any device pin

–0.3 V to V_CC+ 0.3 V

±2 mA

(3)

Storage temperature range, T_stg

–55°C to 125°C

125°C

Maximum junction temperature, T_J

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS. VCORE is for internal device use only. No external DC loading or voltage should be applied.

(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

100.00

10.00

1.00

80

85

90

95

100

105

110

115

120

125

130

Operating Junction Temperature, T_J(°C)

A. See data sheet for absolute maximum and minimum recommended operating conditions.

B. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).

C. The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the dominant failure

mechanism affecting device wearout for the specific device process and design characteristics.

Figure 7-1. Electromigration Fail Mode Derating Chart

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7.2 Recommended Operating Conditions

typical values are specified at V_CC= 3.3 V and T_A= 25°C (unless otherwise noted)

MIN NOM MAX UNIT

Supply voltage during program execution and flash programming

V_CC

1.8

3.6

V

(1) (2)

(AV_CC= DV_CC1/2/3/4= DV_CC

)

V_SS

T_A

Supply voltage (AV_SS= DV_SS1/2/3/4= DV_SS

Operating free-air temperature

)

0

Q temperature

M temperature

Q temperature

M temperature

-40

-55

-40

-55

125

°C

T_J

Operating junction temperature

°C

nF

C_VCORERecommended capacitor at VCORE

470

C_DVCC

C_VCORE

/

Capacitor ratio of DVCC to VCORE

10

PMMCOREVx = 0, 1.8 V ≤ V_CC≤ 3.6 V

PMMCOREVx = 1, 2.0 V ≤ V_CC≤ 3.6 V

PMMCOREVx = 2, 2.2 V ≤ V_CC≤ 3.6 V

PMMCOREVx = 3, 2.4 V ≤ V_CC≤ 3.6 V

0

8.0

12.0

20.0

25.0

Processor frequency (maximum

f_SYSTEMMCLK frequency) ^{(3) (4)}

(see Figure 7-2)

MHz

(1) It is recommended to power AV_CCand DV_CCfrom the same source. A maximum difference of 0.3 V between AV_CCand DV_CCcan be

tolerated during power up and operation.

(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the SVS threshold parameters for the

exact values and further details.

(3) The MSP430 CPU is clocked directly with MCLK. Both the high and low phases of MCLK must not exceed the pulse duration of the

specified maximum frequency.

(4) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

25

3

20

2, 3

2

12

8

1, 2

1, 2, 3

1

0

0, 1

0, 1, 2

0, 1, 2, 3

0

1.8

2.0

2.2

2.4

3.6

Supply Voltage - V

NOTE: The numbers within the fields denote the supported PMMCOREVx settings.

Figure 7-2. Frequency vs Supply Voltage

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7.3 Active Mode Supply Current Into V_CCExcluding External Current

over recommended operating free-air temperature (unless otherwise noted)^{(1) (2) (3)}

FREQUENCY (f_DCO= f_MCLK= f_SMCLK

)

1 MHz

8 MHz 12 MHz 20 MHz

25 MHz

EXECUTION

MEMORY

PARAMETER

V_CC

3.0 V

UNIT

mA

TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX

0

1

2

3

0

1

2

3

0.29 0.45 2.08 2.30

0.32

0.33

0.35

2.08

2.24

2.36

3.10

3.50

3.70

I_{AM, Flash}

Flash

RAM

6.37

6.75

8.90

4.50

14

8

0.17 0.30 0.90 1.10

0.18

0.19

0.20

1.00

1.13

1.20

1.47

1.68

1.78

I_{AM, RAM}

mA

2.82

3.00

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external

load capacitance are chosen to closely match the required 12.5 pF.

(3) Characterized with program executing typical data processing.

f_ACLK= 32768 Hz, f_DCO= f_MCLK= f_SMCLKat specified frequency.

XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.

7.4 Low-Power Mode Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)^{(1) (2)}

-55°C

-40°C

25°C

125°C

PARAMETER

V_CC

PMMCOREVx

UNIT

µA

TYP MAX

2.2 V

3.0 V

2.2 V

3.0 V

0

3

0

3

0

1

2

0

1

2

3

0

1

2

3

0

1

2

3

69

73

93

100

69

73

93

100

69

73

93

100

85

90

150

30

I_LPM0,1MHzLow-power mode 0^{(3) (9)}

11

15.5

17.5

11

15.5

17.5

11

15.5

17.5

12.5

8.5

9.9

10.1

7.1

10.5

10.6

11.8

7.5

8

I_LPM2

Low-power mode 2^{(4) (9)}

µA

11.7

1.4

1.5

1.8

1.9

2.0

1.0

1.1

1.2

1.1

1.2

1.3

0.10

11.7

1.4

1.5

1.8

1.9

2.0

1.0

1.1

1.2

1.1

1.2

1.3

0.10

11.7

1.7

1.8

2.0

2.1

2.3

2.4

2.3

1.2

1.3

1.4

1.2

1.3

0.10

34

2.2 V

Low-power mode 3,

crystal mode^{(5) (9)}

I_LPM3,XT1LF

2.4

21

µA

3.0 V

2.6

34

32

1.42

Low-power mode 3,

VLO mode^{(6) (9)}

I_LPM3,VLO

3.0 V

8.5

7.5

8

1.62

1.35

32

30

I_LPM4

Low-power mode 4^{(7) (9)}3.0 V

µA

8.5

0.75

1.52

0.16

32

5

I_LPM4.5

Low-power mode 4.5⁽⁸⁾

3.0 V

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external

load capacitance are chosen to closely match the required 12.5 pF.

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(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); f_ACLK= 32768 Hz, f_MCLK= 0 MHz, f_SMCLK= f_DCO= 1 MHz

(4) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); f_ACLK= 32768 Hz, f_MCLK= 0 MHz, f_SMCLK= f_DCO= 0 MHz; DCO setting = 1

MHz operation, DCO bias generator enabled.

(5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); f_ACLK= 32768 Hz, f_MCLK= f_SMCLK= f_DCO= 0 MHz

(6) Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); f_ACLK= f_VLO, f_MCLK= f_SMCLK= f_DCO= 0 MHz

(7) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); f_DCO= f_ACLK= f_MCLK= f_SMCLK= 0 MHz

(8) Internal regulator disabled. No data retention.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5); f_DCO= f_ACLK= f_MCLK= f_SMCLK= 0 MHz

(9) Current for brownout, high side supervisor (SVS_H) normal mode included. Low side supervisor and monitors disabled (SVS_L, SVM_L).

High side monitor disabled (SVM_H). RAM retention enabled.

7.5 Thermal Resistance Characteristics

MSP430F5438A-ET

THERMAL METRIC^{(1) (2)}

ZCA

GCA

ZQW

UNIT

113 PINS

θ_JA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

36.2

13.5

14.5

0.3

43.6

16.6

17.8

0.3

θ_JCtop

θ_JB

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

ψ_JB

14.3

15.1

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

7.6 Schmitt-Trigger Inputs – General Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

1.8 V

3 V

MIN

0.75

1.45

0.40

0.70

0.25

0.35

TYP

MAX UNIT

1.45

V

2.15

V_IT+

V_IT–

V_hys

Positive-going input threshold voltage

1.8 V

3 V

1.05

V

1.7

Negative-going input threshold voltage

1.8 V

3 V

0.9

V

1.05

Input voltage hysteresis (V_IT+– V_IT–

)

For pullup: V_IN= V_SS

For pulldown: V_IN= V_CC

R_Pull

C_I

Pullup or pulldown resistor⁽²⁾

Input capacitance

21

35

5

51

kΩ

pF

V_IN= V_SSor V_CC

(1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).

(2) Also applies to the RST pin when the pullup or pulldown resistor is enabled.

7.7 Inputs – Ports P1 and P2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP MAX UNIT

Port P1, P2: P1.x to P2.x, External trigger pulse

duration to set interrupt flag

t_(int)

External interrupt timing⁽²⁾

2.2 V, 3 V

20 ns

(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.

(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t_(int)is met. It may be set by trigger signals

shorter than t_(int)

.

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7.8 Leakage Current – General Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

(1) (2)

I_lkg(Px.y)

High-impedance leakage current

1.8 V, 3 V

±50

nA

(1) The leakage current is measured with V_SSor V_CCapplied to the corresponding pin, unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is

disabled.

7.9 Outputs – General Purpose I/O (Full Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_(OHmax)= –3 mA⁽¹⁾

V_CC

MIN

V_CC– 0.35

V_CC– 0.70

V_CC– 0.35

V_CC– 0.70

MAX UNIT

V_CC

1.8 V

I_(OHmax)= –10 mA⁽²⁾

I_(OHmax)= –5 mA⁽¹⁾

I_(OHmax)= –15 mA⁽²⁾

I_(OLmax)= 3 mA⁽¹⁾

I_(OLmax)= 10 mA⁽²⁾

I_(OLmax)= 5 mA⁽¹⁾

I_(OLmax)= 15 mA⁽²⁾

V_CC

V_OH

High-level output voltage

V

V_CC

3 V

1.8 V

3 V

V_CC

V_SSV_SS+ 0.35

V_SSV_SS+ 0.70

V_SSV_SS+ 0.35

V_SSV_SS+ 0.70

V_OL

Low-level output voltage

V

(1) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage

drop specified.

(2) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage

drop specified.

7.10 Outputs – General Purpose I/O (Reduced Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽³⁾

PARAMETER

TEST CONDITIONS

I_(OHmax)= –1 mA⁽¹⁾

V_CC

MIN

V_CC– 0.35

V_CC– 0.70

V_CC– 0.35

V_CC– 0.70

MAX UNIT

V_CC

1.8 V

I_(OHmax)= –3 mA⁽²⁾

I_(OHmax)= –2 mA⁽¹⁾

I_(OHmax)= –6 mA⁽²⁾

I_(OLmax)= 1 mA⁽¹⁾

I_(OLmax)= 3 mA⁽²⁾

I_(OLmax)= 2 mA⁽¹⁾

I_(OLmax)= 6 mA⁽²⁾

V_CC

V_OH

High-level output voltage

V

V_CC

3.0 V

1.8 V

3.0 V

V_CC

V_SSV_SS+ 0.35

V_SSV_SS+ 0.70

V_SSV_SS+ 0.35

V_SSV_SS+ 0.70

V_OL

Low-level output voltage

V

(1) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage

drop specified.

(2) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage

drop specified.

(3) Selecting reduced drive strength may reduce EMI.

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7.11 Output Frequency – General Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

V_CC= 1.8 V,

PMMCOREVx = 0

16

Port output frequency

(with load)

f_Px.y

P1.6/SMCLK ^{(1) (2)}

MHz

25

V_CC= 3 V,

PMMCOREVx = 3

V_CC= 1.8 V,

PMMCOREVx = 0

P1.0/TA0CLK/ACLK

P1.6/SMCLK

16

f_{Port_CLK}

Clock output frequency

MHz

25

P2.0/TA1CLK/MCLK

V_CC= 3 V,

PMMCOREVx = 3

C_L= 20 pF⁽²⁾

(1) A resistive divider with 2 × R1 between V_CCand V_SSis used as load. The output is connected to the center tap of the divider. For full

drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. C_L= 20 pF is connected to the output to V_SS

.

(2) The output voltage reaches at least 10% and 90% V_CCat the specified toggle frequency.

7.12 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

25.0

20.0

15.0

10.0

5.0

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0.0

T_A= 25°C

T_A= 85°C

V_CC= 3.0 V

Px.y

V_CC= 1.8 V

Px.y

T_A= 25°C

T_A= 85°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

V_OL– Low-Level Output Voltage – V

Figure 7-4. Typical Low-Level Output Current vs Low-Level

Output Voltage

Figure 7-3. Typical Low-Level Output Current vs Low-Level

Output Voltage

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7.12 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0) (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

0.0

−1.0

−2.0

−3.0

−4.0

−5.0

−6.0

−7.0

−8.0

V_CC= 3.0 V

Px.y

V_CC= 1.8 V

Px.y

−5.0

−10.0

−15.0

−20.0

−25.0

T_A= 85°C

T_A= 25°C

T_A= 85°C

T_A= 25°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

V_OH– High-Level Output Voltage – V

Figure 7-5. Typical High-Level Output Current vs High-Level

Output Voltage

Figure 7-6. Typical High-Level Output Current vs High-Level

Output Voltage

7.13 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

60.0

24

20

16

12

8

T_A= 25°C

T_A= 85°C

V_CC= 1.8 V

Px.y

V_CC= 3.0 V

Px.y

55.0

50.0

45.0

40.0

35.0

30.0

25.0

20.0

15.0

10.0

5.0

T_A= 25°C

T_A= 85°C

4

0.0

0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

V_OL– Low-Level Output Voltage – V

Figure 7-7. Typical Low-Level Output Current vs Low-Level

Output Voltage

Figure 7-8. Typical Low-Level Output Current vs Low-Level

Output Voltage

16

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7.13 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1) (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

0.0

−5.0

0

V_CC= 1.8 V

Px.y

V_CC= 3.0 V

Px.y

−10.0

−15.0

−20.0

−25.0

−30.0

−35.0

−40.0

−45.0

−50.0

−55.0

−60.0

−4

−8

−12

−16

−20

T_A= 85°C

T_A= 25°C

0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

1.0

1.5

2.0

V_OH– High-Level Output Voltage – V

Figure 7-9. Typical High-Level Output Current vs High-Level

Output Voltage

Figure 7-10. Typical High-Level Output Current vs High-Level

Output Voltage

7.14 Crystal Oscillator, XT1, Low-Frequency Mode

over recommended ranges of supply voltage and T_J= –40°C to 85°C (unless otherwise noted)^{(1) (2)}

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 1,

T_A= 25°C

0.075

Differential XT1 oscillator crystal

current consumption from lowest

drive setting, LF mode

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 2,

T_A= 25°C

ΔI_DVCC.LF

3.0 V

0.170

µA

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 3,

T_A= 25°C

0.290

XT1 oscillator crystal frequency,

LF mode

f_XT1,LF0

XTS = 0, XT1BYPASS = 0

32768

Hz

XT1 oscillator logic-level square-

wave input frequency, LF mode

f_XT1,LF,SW

XTS = 0, XT1BYPASS = 1 ^{(3) (4)}

10 32.768

210

50 kHz

XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 0,

f_XT1,LF= 32768 Hz, C_L,eff= 6 pF

Oscillation allowance for

LF crystals ⁽⁵⁾

OA_LF

kΩ

pF

XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 1,

f_XT1,LF= 32768 Hz, C_L,eff= 12 pF

300

XTS = 0, XCAPx = 0 ⁽⁷⁾

XTS = 0, XCAPx = 1

XTS = 0, XCAPx = 2

XTS = 0, XCAPx = 3

2

5.5

Integrated effective load

capacitance, LF mode ⁽⁶⁾

C_L,eff

8.5

12.0

XTS = 0, Measured at ACLK,

f_XT1,LF= 32768 Hz

Duty cycle, LF mode

30

10

70

%

Oscillator fault frequency, LF mode

f_Fault,LF

XTS = 0 ⁽⁹⁾

10000

Hz

(8)

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7.14 Crystal Oscillator, XT1, Low-Frequency Mode (continued)

over recommended ranges of supply voltage and T_J= –40°C to 85°C (unless otherwise noted)^{(1) (2)}

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 0,

T_A= 25°C, C_L,eff= 6 pF

1000

t_START,LF

Startup time, LF mode

3.0 V

ms

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 3,

T_A= 25°C, C_L,eff= 12 pF

500

(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.

•

Keep the trace between the device and the crystal as short as possible.

Design a good ground plane around the oscillator pins.

Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.

If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.

(2) Use of crystal oscillator is not ensured above 85°C. It is recommended that an external digital clock source or other internally

generated clock source.

(3) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined

in the Schmitt-trigger Inputs section of this data sheet.

(4) Maximum frequency of operation of the entire device cannot be exceeded.

(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the

XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following

guidelines, but should be evaluated based on the actual crystal selected for the application:

•

For XT1DRIVEx = 0, C_L,eff≤ 6 pF.

For XT1DRIVEx = 1, 6 pF ≤ C_L,eff≤ 9 pF.

For XT1DRIVEx = 2, 6 pF ≤ C_L,eff≤ 10 pF.

For XT1DRIVEx = 3, C_L,eff≥ 6 pF.

(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the used crystal.

(7) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

(8) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(9) Measured with logic-level input frequency but also applies to operation with crystals.

7.15 Crystal Oscillator, XT1, High-Frequency Mode

over recommended ranges of supply voltage and T_J= –40°C to 85°C (unless otherwise noted)^{(1) (2)}

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

f_OSC= 4 MHz,

XTS = 1, XOSCOFF = 0,

XT1BYPASS = 0, XT1DRIVEx = 0,

T_A= 25°C

200

f_OSC= 12 MHz,

XTS = 1, XOSCOFF = 0,

XT1BYPASS = 0, XT1DRIVEx = 1,

T_A= 25°C

260

325

450

XT1 oscillator crystal current,

HF mode

I_DVCC.HF

3.0 V

µA

f_OSC= 20 MHz,

XTS = 1, XOSCOFF = 0,

XT1BYPASS = 0, XT1DRIVEx = 2,

T_A= 25°C

f_OSC= 32 MHz,

XTS = 1, XOSCOFF = 0,

XT1BYPASS = 0, XT1DRIVEx = 3,

T_A= 25°C

XT1 oscillator crystal frequency,

HF mode 0

XTS = 1,

f_XT1,HF0

4

8

MHz

XT1BYPASS = 0, XT1DRIVEx = 0 ⁽³⁾

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7.15 Crystal Oscillator, XT1, High-Frequency Mode (continued)

over recommended ranges of supply voltage and T_J= –40°C to 85°C (unless otherwise noted)^{(1) (2)}

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

XT1 oscillator crystal frequency,

HF mode 1

XTS = 1,

f_XT1,HF1

f_XT1,HF2

f_XT1,HF3

8

16 MHz

XT1BYPASS = 0, XT1DRIVEx = 1 ⁽³⁾

XT1 oscillator crystal frequency,

HF mode 2

XTS = 1,

16

24

24 MHz

32 MHz

XT1BYPASS = 0, XT1DRIVEx = 2 ⁽³⁾

XT1 oscillator crystal frequency,

HF mode 3

XTS = 1,

XT1BYPASS = 0, XT1DRIVEx = 3 ⁽³⁾

XT1 oscillator logic-level square-

wave input frequency, HF mode,

bypass mode

XTS = 1,

f_XT1,HF,SW

0.7

32 MHz

XT1BYPASS = 1 ^{(3) (4)}

XTS = 1,

XT1BYPASS = 0, XT1DRIVEx = 0,

f_XT1,HF= 6 MHz, C_L,eff= 15 pF

450

320

200

0.5

XTS = 1,

XT1BYPASS = 0, XT1DRIVEx = 1,

f_XT1,HF= 12 MHz, C_L,eff= 15 pF

Oscillation allowance for

HF crystals ⁽⁵⁾

OA_HF

Ω

XTS = 1,

XT1BYPASS = 0, XT1DRIVEx = 2,

f_XT1,HF= 20 MHz, C_L,eff= 15 pF

XTS = 1,

XT1BYPASS = 0, XT1DRIVEx = 3,

f_XT1,HF= 32 MHz, C_L,eff= 15 pF

f_OSC= 6 MHz, XTS = 1,

XT1BYPASS = 0, XT1DRIVEx = 0,

T_A= 25°C, C_L,eff= 15 pF

t_START,HF

Startup time, HF mode

3.0 V

ms

pF

f_OSC= 20 MHz, XTS = 1,

XT1BYPASS = 0, XT1DRIVEx = 2,

T_A= 25°C, C_L,eff= 15 pF

0.3

Integrated effective load

C_L,eff

XTS = 1

1

capacitance, HF mode ^{(6) (7)}

XTS = 1, Measured at ACLK,

f_XT1,HF2= 20 MHz

Duty cycle, HF mode

40

30

50

60

%

Oscillator fault frequency, HF mode

f_Fault,HF

XTS = 1 ⁽⁹⁾

300 kHz

(8)

(1) To improve EMI on the XT1 oscillator the following guidelines should be observed.

•

Keep the traces between the device and the crystal as short as possible.

Design a good ground plane around the oscillator pins.

Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.

If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.

(2) Use of crystal oscillator is not ensured above 85°C. It is recommended that an external digital clock source or other internally

generated clock source.

(3) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device

operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.

(4) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined

in the Schmitt-trigger Inputs section of this data sheet.

(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.

(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the used crystal.

(7) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. In general, an effective load capacitance

of up to 18 pF can be supported.

(8) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(9) Measured with logic-level input frequency but also applies to operation with crystals.

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7.16 Crystal Oscillator, XT2

over recommended ranges of supply voltage and T_J= –40°C to 85°C (unless otherwise noted)^{(1) (2) (3)}

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

f_OSC= 4 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 0,

T_A= 25°C

200

f_OSC= 12 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 1,

T_A= 25°C

260

325

450

XT2 oscillator crystal current

consumption

I_DVCC.XT2

3.0 V

µA

f_OSC= 20 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 2,

T_A= 25°C

f_OSC= 32 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 3,

T_A= 25°C

XT2 oscillator crystal frequency,

mode 0

f_XT2,HF0

f_XT2,HF1

f_XT2,HF2

f_XT2,HF3

f_XT2,HF,SW

XT2DRIVEx = 0, XT2BYPASS = 0 ⁽⁴⁾

XT2DRIVEx = 1, XT2BYPASS = 0 ⁽⁴⁾

XT2DRIVEx = 2, XT2BYPASS = 0 ⁽⁴⁾

XT2DRIVEx = 3, XT2BYPASS = 0 ⁽⁴⁾

XT2BYPASS = 1 ^{(4) (5)}

4

8

MHz

XT2 oscillator crystal frequency,

mode 1

16 MHz

24 MHz

32 MHz

XT2 oscillator crystal frequency,

mode 2

16

24

0.7

XT2 oscillator crystal frequency,

mode 3

XT2 oscillator logic-level square-

wave input frequency, bypass mode

XT2DRIVEx = 0, XT2BYPASS = 0,

f_XT2,HF0= 6 MHz, C_L,eff= 15 pF

450

320

200

XT2DRIVEx = 1, XT2BYPASS = 0,

f_XT2,HF1= 12 MHz, C_L,eff= 15 pF

Oscillation allowance for

HF crystals ⁽⁶⁾

OA_HF

Ω

XT2DRIVEx = 2, XT2BYPASS = 0,

f_XT2,HF2= 20 MHz, C_L,eff= 15 pF

XT2DRIVEx = 3, XT2BYPASS = 0,

f_XT2,HF3= 32 MHz, C_L,eff= 15 pF

f_OSC= 6 MHz

XT2BYPASS = 0, XT2DRIVEx = 0,

T_A= 25°C, C_L,eff= 15 pF

0.5

0.3

t_START,HF

Startup time

3.0 V

ms

pF

f_OSC= 20 MHz

XT2BYPASS = 0, XT2DRIVEx = 2,

T_A= 25°C, C_L,eff= 15 pF

Integrated effective load

C_L,eff

1

capacitance, HF mode ^{(2) (7)}

Duty cycle

Measured at ACLK, f_XT2,HF2= 20 MHz

XT2BYPASS = 1 ⁽⁹⁾

40

30

50

60

%

f_Fault,HF

Oscillator fault frequency ⁽⁸⁾

300 kHz

(1) Use of crystal oscillator is not ensured above 85°C. It is recommended that an external digital clock source or other internally

generated clock source.

(2) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. In general, an effective load capacitance

of up to 18 pF can be supported.

(3) To improve EMI on the XT2 oscillator the following guidelines should be observed.

•

Keep the traces between the device and the crystal as short as possible.

Design a good ground plane around the oscillator pins.

Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.

Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.

Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.

If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.

(4) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device

operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.

20

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(5) When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined

in the Schmitt-trigger Inputs section of this data sheet.

(6) Oscillation allowance is based on a safety factor of 5 for recommended crystals.

(7) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the used crystal.

(8) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(9) Measured with logic-level input frequency but also applies to operation with crystals.

7.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

VLO frequency

VLO frequency temperature drift

TEST CONDITIONS

V_CC

MIN

TYP

9.4

0.5

4

MAX UNIT

14 kHz

%/°C

f_VLO

Measured at ACLK

1.8 V to 3.6 V

5

df_VLO/d_T

Measured at ACLK ⁽¹⁾

Measured at ACLK ⁽²⁾

Measured at ACLK

df_VLO/dV_CCVLO frequency supply voltage drift

Duty cycle

%/V

40

50

60

%

(1) Calculated using the box method:

Q temperature: (MAX(–40 to 125°C) – MIN(–40 to 125°C)) / MIN(–40 to 125°C) / (125°C – (–40°C))

M temperature: (MAX(–55 to 125°C) – MIN(–55 to 125°C)) / MIN(–55 to 125°C) / (125°C – (–55°C))

(2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)

7.18 Internal Reference, Low-Frequency Oscillator (REFO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

3

MAX UNIT

I_REFO

REFO oscillator current consumption T_A= 25°C

1.8 V to 3.6 V

3 V

µA

Hz

REFO frequency calibrated

Measured at ACLK

32768

±3.5

±1.5

0.01

1.0

f_REFO

Full temperature range

T_A= 25°C

REFO absolute tolerance calibrated

%

df_REFO/d_T

REFO frequency temperature drift

Measured at ACLK ⁽¹⁾

1.8 V to 3.6 V

%/°C

%/V

df_REFO/dV_CC

REFO frequency supply voltage drift Measured at ACLK ⁽²⁾

Duty cycle

Measured at ACLK

40%/60% duty cycle

40

50

60

%

t_START

REFO startup time

25

µs

(1) Calculated using the box method:

Q temperature: (MAX(-40 to 125°C) – MIN(-40 to 125°C)) / MIN(-40 to 125°C) / (125°C – (-40°C))

M temperature: (MAX(-55 to 125°C) – MIN(-55 to 125°C)) / MIN(-55 to 125°C) / (125°C – (-55°C))

(2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)

7.19 DCO Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

DCORSELx = 0, DCOx = 0, MODx = 0

DCORSELx = 0, DCOx = 31, MODx = 0

DCORSELx = 1, DCOx = 0, MODx = 0

DCORSELx = 1, DCOx = 31, MODx = 0

DCORSELx = 2, DCOx = 0, MODx = 0

DCORSELx = 2, DCOx = 31, MODx = 0

DCORSELx = 3, DCOx = 0, MODx = 0

DCORSELx = 3, DCOx = 31, MODx = 0

DCORSELx = 4, DCOx = 0, MODx = 0

DCORSELx = 4, DCOx = 31, MODx = 0

MIN

0.065

0.65

0.10

1.42

0.27

3.12

0.59

6.02

1.25

12.25

TYP

MAX UNIT

0.25 MHz

1.75 MHz

0.41 MHz

3.5 MHz

f_DCO(0,0)

f_DCO(0,31)

f_DCO(1,0)

f_DCO(1,31)

f_DCO(2,0)

f_DCO(2,31)

f_DCO(3,0)

f_DCO(3,31)

f_DCO(4,0)

f_DCO(4,31)

DCO frequency (0, 0)⁽¹⁾

DCO frequency (0, 31)⁽¹⁾

DCO frequency (1, 0)⁽¹⁾

DCO frequency (1, 31)⁽¹⁾

DCO frequency (2, 0)⁽¹⁾

DCO frequency (2, 31)⁽¹⁾

DCO frequency (3, 0)⁽¹⁾

DCO frequency (3, 31)⁽¹⁾

DCO frequency (4, 0)⁽¹⁾

DCO frequency (4, 31)⁽¹⁾

0.8 MHz

7.43 MHz

1.56 MHz

14.05 MHz

3.25 MHz

28.25 MHz

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7.19 DCO Frequency (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

DCORSELx = 5, DCOx = 0, MODx = 0

DCORSELx = 5, DCOx = 31, MODx = 0

DCORSELx = 6, DCOx = 0, MODx = 0

DCORSELx = 6, DCOx = 31, MODx = 0

DCORSELx = 7, DCOx = 0, MODx = 0

DCORSELx = 7, DCOx = 31, MODx = 0

MIN

TYP

MAX UNIT

6.05 MHz

f_DCO(5,0)

f_DCO(5,31)

f_DCO(6,0)

f_DCO(6,31)

f_DCO(7,0)

f_DCO(7,31)

DCO frequency (5, 0)⁽¹⁾

DCO frequency (5, 31)⁽¹⁾

DCO frequency (6, 0)⁽¹⁾

DCO frequency (6, 31)⁽¹⁾

DCO frequency (7, 0)⁽¹⁾

DCO frequency (7, 31)⁽¹⁾

2.45

23.65

4.55

54.15 MHz

10.75 MHz

88.05 MHz

19.65 MHz

135.05 MHz

38.95

8.45

59.95

Frequency step between range

DCORSEL and DCORSEL + 1

S_DCORSEL

S_DCO

S_RSEL= f_{DCO(DCORSEL+1,DCO)}/f_{DCO(DCORSEL,DCO)}

1.2

2.3 ratio

Frequency step between tap

DCO and DCO + 1

S_DCO= f_{DCO(DCORSEL,DCO+1)}/f_{DCO(DCORSEL,DCO)}

Measured at SMCLK

1.02

40

1.12 ratio

Duty cycle

50

0.1

1.9

60

%

DCO frequency temperature

drift⁽²⁾

df_DCO/dT

f_DCO= 1 MHz

%/°C

%/V

df_DCO/dV_CC

DCO frequency voltage drift⁽³⁾

f_DCO= 1 MHz

(1) When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, f_DCO, should be set to reside within the

range of f_{DCO(n, 0),MAX}≤ f_DCO≤ f_{DCO(n, 31),MIN}, where f_{DCO(n, 0),MAX}represents the maximum frequency specified for the DCO frequency,

range n, tap 0 (DCOx = 0) and f_{DCO(n,31),MIN}represents the minimum frequency specified for the DCO frequency, range n, tap 31

(DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual

f_DCOfrequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the

selected range is at its minimum or maximum tap setting.

(2) Calculated using the box method:

Q temperature: (MAX(–40 to 125°C) – MIN(–40 to 125°C)) / MIN(–40 to 125°C) / (125°C – (–40°C))

M temperature: (MAX(–55 to 125°C) – MIN(–55 to 125°C)) / MIN(–55 to 125°C) / (125°C – (–55°C))

(3) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)

100

V_CC= 3.0 V

T_A= 25°C

10

DCOx = 31

1

DCOx = 0

0.1

0

1

2

3

4

5

6

7

DCORSEL

Figure 7-11. Typical DCO Frequency

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7.20 PMM, Brownout Reset (BOR)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

| dDV_CC/d_t| < 3 V/s

MIN

TYP

MAX UNIT

BOR_Hon voltage,

DV_CCfalling level

V(DV_CC_BOR_IT–)

1.47

1.52

V

BOR_Hoff voltage,

DV_CCrising level

V(DV_CC_BOR_IT+)

V(DV_CC_BOR_hys)

t_RESET

0.78

58

2

1.30

BOR_Hhysteresis

275 mV

µs

Pulse duration required at

RST/NMI pin to accept a reset

7.21 PMM, Core Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Core voltage, active mode,

PMMCOREV = 3

V_CORE3(AM)

V_CORE2(AM)

V_CORE1(AM)

V_CORE0(AM)

V_CORE3(LPM)

V_CORE2(LPM)

V_CORE1(LPM)

V_CORE0(LPM)

2.4 V ≤ DV_CC≤ 3.6 V

1.90

V

Core voltage, active mode,

PMMCOREV = 2

2.2 V ≤ DV_CC≤ 3.6 V

2.0 V ≤ DV_CC≤ 3.6 V

1.8 V ≤ DV_CC≤ 3.6 V

2.4 V ≤ DV_CC≤ 3.6 V

2.2 V ≤ DV_CC≤ 3.6 V

2.0 V ≤ DV_CC≤ 3.6 V

1.8 V ≤ DV_CC≤ 3.6 V

1.80

1.60

1.40

1.94

1.84

1.64

1.44

V

Core voltage, active mode,

PMMCOREV = 1

Core voltage, active mode,

PMMCOREV = 0

Core voltage, low-current

mode, PMMCOREV = 3

Core voltage, low-current

mode, PMMCOREV = 2

Core voltage, low-current

mode, PMMCOREV = 1

Core voltage, low-current

mode, PMMCOREV = 0

7.22 PMM, SVS High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

SVSHE = 0, DV_CC= 3.6 V

0

200

nA

µA

I_(SVSH)

SVS current consumption

SVSHE = 1, DV_CC= 3.6 V, SVSHFP = 0

SVSHE = 1, DV_CC= 3.6 V, SVSHFP = 1

SVSHE = 1, SVSHRVL = 0

1.5

1.55

1.77

1.96

2.07

1.60

1.86

2.05

2.18

2.30

2.50

2.85

1.68

1.88

2.08

2.18

1.74

1.94

2.14

2.30

2.40

2.70

3.10

1.8

2

SVSHE = 1, SVSHRVL = 1

V_{(SVSH_IT–)}

SVS_Hon voltage level ⁽¹⁾

V

SVSHE = 1, SVSHRVL = 2

2.23

2.33

1.87

2.09

2.3

SVSHE = 1, SVSHRVL = 3

SVSHE = 1, SVSMHRRL = 0

SVSHE = 1, SVSMHRRL = 1

SVSHE = 1, SVSMHRRL = 2

SVSHE = 1, SVSMHRRL = 3

SVSHE = 1, SVSMHRRL = 4

SVSHE = 1, SVSMHRRL = 5

SVSHE = 1, SVSMHRRL = 6

SVSHE = 1, SVSMHRRL = 7

2.44

2.57

2.9

V_{(SVSH_IT+)}

SVS_Hoff voltage level ⁽¹⁾

V

3.25

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7.22 PMM, SVS High Side (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SVSHE = 1, dV_DVCC/dt = 10 mV/µs, SVSHFP = 1

SVSHE = 1, dV_DVCC/dt = 1 mV/µs, SVSHFP = 0

SVSHE = 0 → 1, SVSHFP = 1

MIN

TYP MAX UNIT

2.5

t_pd(SVSH)

SVS_Hpropagation delay

µs

20

12.5

µs

100

t_(SVSH)

SVS_Hon or off delay time

DV_CCrise time

SVSHE = 0 → 1, SVSHFP = 0

dV_DVCC/dt

0

1000 V/s

(1) The SVS_Hsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage

Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide.on recommended settings and use.

7.23 PMM, SVM High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

SVMHE = 0, DV_CC= 3.6 V

0

200

1.5

nA

µA

I_(SVMH)

SVM_Hcurrent consumption

SVMHE= 1, DV_CC= 3.6 V, SVMHFP = 0

SVMHE = 1, DV_CC= 3.6 V, SVMHFP = 1

SVMHE = 1, SVSMHRRL = 0

1.61

1.86

2.05

2.18

2.30

2.50

2.85

1.74

1.94

2.14

2.30

2.40

2.70

3.10

3.75

2.5

1.87

2.09

2.30

2.44

2.58

2.93

3.25

SVMHE = 1, SVSMHRRL = 1

SVMHE = 1, SVSMHRRL = 2

SVMHE = 1, SVSMHRRL = 3

V_(SVMH)

SVM_Hon or off voltage level ⁽¹⁾

SVMHE = 1, SVSMHRRL = 4

V

SVMHE = 1, SVSMHRRL = 5

SVMHE = 1, SVSMHRRL = 6

SVMHE = 1, SVSMHRRL = 7

SVMHE = 1, SVMHOVPE = 1

SVMHE = 1, dV_DVCC/dt = 10 mV/µs, SVMHFP = 1

SVMHE = 1, dV_DVCC/dt = 1 mV/µs, SVMHFP = 0

SVMHE = 0 → 1, SVMHFP = 1

SVMHE = 0 → 1, SVMHFP = 0

t_pd(SVMH)

SVM_Hpropagation delay

SVM_Hon or off delay time

µs

20

12.5

100

t_(SVMH)

(1) The SVM_Hsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage

Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide.on recommended settings and use.

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7.24 PMM, SVS Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

SVSLE = 0, PMMCOREV = 2

0

200

1.5

nA

µA

I_(SVSL)

SVS_Lcurrent consumption

SVSLE = 1, PMMCOREV = 2, SVSLFP = 0

SVSLE = 1, PMMCOREV = 2, SVSLFP = 1

SVSLE = 1, dV_CORE/dt = 10 mV/µs, SVSLFP = 1

SVSLE = 1, dV_CORE/dt = 1 mV/µs, SVSLFP = 0

SVSLE = 0 → 1, dV_CORE/dt = 10 mV/µs, SVSLFP = 1

SVSLE = 0 → 1, dV_CORE/dt = 1 mV/µs, SVSLFP = 0

2.5

t_pd(SVSL)

SVS_Lpropagation delay

SVS_Lon or off delay time

µs

20

12.5

100

t_(SVSL)

7.25 PMM, SVM Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

SVMLE = 0, PMMCOREV = 2

0

200

1.5

nA

µA

I_(SVML)

SVM_Lcurrent consumption

SVMLE= 1, PMMCOREV = 2, SVMLFP = 0

SVMLE= 1, PMMCOREV = 2, SVMLFP = 1

SVMLE = 1, dV_CORE/dt = 10 mV/µs, SVMLFP = 1

SVMLE = 1, dV_CORE/dt = 1 mV/µs, SVMLFP = 0

SVMLE = 0 → 1, dV_CORE/dt = 10 mV/µs, SVMLFP = 1

SVMLE = 0 → 1, dV_CORE/dt = 1 mV/µs, SVMLFP = 0

2.5

t_pd(SVML)

SVM_Lpropagation delay

SVM_Lon or off delay time

µs

20

12.5

100

t_(SVML)

7.26 Wakeup From Low-Power Modes and Reset

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

f_MCLK≥ 4.0 MHz

PMMCOREV = SVSMLRRL = n

MIN

TYP

MAX UNIT

3.5

4.5

7.5

Wake-up time from LPM2,

t_WAKE-UP-FAST

LPM3, or LPM4 to active mode (where n = 0, 1, 2, or 3),

µs

1.0 MHz < f_MCLK

< 4.0 MHz

(1) (2)

9.5

SVSLFP = 1

Wake-up time from LPM2,

PMMCOREV = SVSMLRRL = n

t_WAKE-UP-SLOW

LPM3 or LPM4 to active mode (where n = 0, 1, 2, or 3),

150

170

µs

(3)

SVSLFP = 0

Wake-up time from LPM4.5 to

active mode ⁽⁴⁾

t_WAKE-UP-LPM5

t_{WAKE-UP-RESET}

2

3.5

ms

Wake-up time from RST or

BOR event to active mode ⁽⁴⁾

(1) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance

mode of the low side supervisor (SVS_L) and low side monitor (SVM_L). Fastest wakeup times are possible with SVS_Land SVM_Lin full

performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVS_Land SVM_Lwhile

operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the

MSP430F5xx and MSP430F6xx Family User's Guide.

(2) Ensured only until T_J= 85°C.

(3) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance

mode of the low side supervisor (SVS_L) and low side monitor (SVM_L). In this case, the SVS_Land SVM_Lare in normal mode (low

current) mode when operating in AM, LPM0, and LPM1. Various options are available for SVS_Land SVM_Lwhile operating in LPM2,

LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430F5xx and MSP430F6xx

Family User's Guide.

(4) This value represents the time from the wakeup event to the reset vector execution.

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7.27 Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK,

External: TACLK,

Duty cycle = 50% ± 10%

1.8 V/

3.0 V

f_TA

Timer_A input clock frequency

25 MHz

All capture inputs,

Minimum pulse duration required for capture

1.8 V/

3.0 V

t_TA,cap

Timer_A capture timing

20

ns

7.28 Timer_B

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK,

External: TBCLK,

Duty cycle = 50% ± 10%

1.8 V/

3.0 V

f_TB

Timer_B input clock frequency

25 MHz

All capture inputs,

Minimum pulse duration required for capture

1.8 V/

3.0 V

t_TB,cap

Timer_B capture timing

20

ns

7.29 USCI (UART Mode) Recommended Operating Conditions

PARAMETER

TEST CONDITIONS

Internal: SMCLK, ACLK,

V_CC

MIN

TYP

MAX UNIT

f_USCI

USCI input clock frequency

External: UCLK,

f_SYSTEMMHz

Duty cycle = 50% ± 10%

BITCLK clock frequency

(equals baud rate in MBaud)

f_BITCLK

1 MHz

7.30 USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

V_CC

2.2 V

3 V

MIN

TYP

MAX UNIT

50

600

ns

620

t_τ

UART receive deglitch time ⁽¹⁾

48

(1) Pulses on the UART receive input (UCxRX) that are shorter than the UART receive deglitch time are suppressed. To ensure that

pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time.

7.31 USCI (SPI Master Mode) Recommended Operating Conditions

PARAMETER

TEST CONDITIONS

Internal: SMCLK, ACLK

V_CC

MIN

TYP

MAX UNIT

f_USCI

USCI input clock frequency

f_SYSTEMMHz

Duty cycle = 50% ± 10%

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7.32 USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

SMCLK, ACLK,

f_USCI

USCI input clock frequency

f_SYSTEMMHz

Duty cycle = 50% ± 10%

PMMCOREV = 0

1.8 V

3.0 V

2.4 V

3.0 V

1.8 V

3.0 V

2.4 V

3.0 V

1.8 V

3.0 V

2.4 V

3.0 V

1.8 V

3.0 V

2.4 V

3.0 V

55

38

30

25

0

ns

t_SU,MI

SOMI input data setup time

SOMI input data hold time

SIMO output data valid time⁽²⁾

SIMO output data hold time⁽³⁾

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

0

t_HD,MI

0

20

ns

18

UCLK edge to SIMO valid,

C_L= 20 pF, PMMCOREV = 0

t_VALID,MO

16

ns

15

UCLK edge to SIMO valid,

C_L= 20 pF, PMMCOREV = 3

-10

-8

C_L= 20 pF, PMMCOREV = 0

C_L= 20 pF, PMMCOREV = 3

ns

t_HD,MO

-10

-8

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI≥ max(t_{VALID,MO(USCI)}+ t_SU,SI(Slave), t_SU,MI(USCI)+ t_{VALID,SO(Slave)}).

For the slave parameters t_SU,SI(Slave)and t_{VALID,SO(Slave)}, see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams

in Figure 7-12 and Figure 7-13.

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure

7-12 and Figure 7-13.

1/f_UCxCLK

CKPL = 0

UCLK

CKPL = 1

t_LO/HI

t_SU,MI

t_HD,MI

SOMI

SIMO

t_HD,MO

t_VALID,MO

Figure 7-12. SPI Master Mode, CKPH = 0

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1/f_UCxCLK

CKPL = 0

UCLK

CKPL = 1

t_LO/HI

t_HD,MI

t_SU,MI

SOMI

SIMO

t_HD,MO

t_VALID,MO

Figure 7-13. SPI Master Mode, CKPH = 1

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7.33 USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

11

8

TYP

MAX UNIT

1.8 V

3.0 V

2.4 V

3.0 V

1.8 V

3.0 V

2.4 V

3.0 V

1.8 V

3.0 V

2.4 V

3.0 V

1.8 V

3.0 V

2.4 V

3.0 V

1.8 V

3.0 V

2.4 V

3.0 V

1.8 V

3.0 V

2.4 V

3.0 V

1.8 V

3.0 V

2.4 V

3.0 V

1.8 V

3.0 V

2.4 V

3.0 V

PMMCOREV = 0

ns

t_STE,LEAD

t_STE,LAG

t_STE,ACC

t_STE,DIS

t_SU,SI

STE lead time, STE low to clock

7

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

ns

6

3

STE lag time, Last clock to STE high

3

66

ns

50

STE access time, STE low to SOMI data

out

36

ns

30

ns

23

STE disable time, STE high to SOMI high

impedance

16

ns

13

5

2

5

ns

SIMO input data setup time

SIMO input data hold time

SOMI output data valid time⁽²⁾

SOMI output data hold time⁽³⁾

t_HD,SI

76

ns

60

UCLK edge to SOMI valid,

C_L= 20 pF, PMMCOREV = 0

t_VALID,SO

44

ns

40

UCLK edge to SOMI valid,

C_L= 20 pF, PMMCOREV = 3

18

12

10

8

C_L= 20 pF, PMMCOREV = 0

C_L= 20 pF, PMMCOREV = 3

ns

t_HD,SO

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI≥ max(t_{VALID,MO(Master)}+ t_SU,SI(USCI), t_{SU,MI(Master)}+ t_{VALID,SO(USCI)}).

For the master parameters t_{SU,MI(Master)}and t_{VALID,MO(Master)}, refer to the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams

in Figure 7-14 and Figure 7-15.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure

7-14 and Figure 7-15.

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t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

UCLK

CKPL = 1

t_SU,SI

t_LO/HI

t_HD,SI

SIMO

SOMI

t_HD,SO

t_VALID,SO

t_STE,ACC

t_STE,DIS

Figure 7-14. SPI Slave Mode, CKPH = 0

t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LO/HI

t_HD,SI

t_SU,SI

SIMO

SOMI

t_HD,MO

t_VALID,SO

t_STE,ACC

t_STE,DIS

Figure 7-15. SPI Slave Mode, CKPH = 1

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7.34 USCI (I²C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 7-16)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK,

External: UCLK,

f_USCI

USCI input clock frequency

f_SYSTEMMHz

Duty cycle = 50% ± 10%

f_SCL

SCL clock frequency

2.2 V, 3 V

0

4.0

0.6

4.7

0.6

0

400 kHz

µs

f_SCL≤ 100 kHz

f_SCL> 100 kHz

f_SCL≤ 100 kHz

f_SCL> 100 kHz

t_HD,STA

Hold time (repeated) START

t_SU,STA

Setup time for a repeated START

2.2 V, 3 V

µs

t_HD,DAT

t_SU,DAT

Data hold time

Data setup time

2.2 V, 3 V

ns

250

4.0

0.6

50

f_SCL≤ 100 kHz

f_SCL> 100 kHz

t_SU,STO

Setup time for STOP

2.2 V, 3 V

µs

2.2 V

3 V

600

ns

600

Pulse duration of spikes suppressed by input

filter

t_SP

50

t_HD,STA

t_SU,STA

t_HD,STA

t_BUF

SDA

SCL

t_LOW

t_HIGH

t_SP

t_SU,DAT

t_SU,STO

t_HD,DAT

Figure 7-16. I2C Mode Timing

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7.35 12-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

2.2

0

TYP

AVCC and DVCC are connected together,

AVSS and DVSS are connected together,

V_(AVSS)= V_(DVSS)= 0 V

AV_CC

Analog supply voltage

3.6

V

V_(Ax)

Analog input voltage range⁽²⁾All ADC12 analog input pins Ax

AV_CC

200

V

2.2 V

3 V

125

150

Operating supply current into

f_ADC12CLK= 5.0 MHz⁽⁴⁾

AVCC terminal⁽³⁾

I_{ADC12_A}

µA

270

Only one terminal Ax can be selected at one

time

C_I

R_I

Input capacitance

2.2 V

20

pF

Ω

Input MUX ON resistance

0 V ≤ V_Ax≤ AVCC

200

(1) The leakage current is specified by the digital I/O input leakage.

(2) The analog input voltage range must be within the selected reference voltage range V_R+to V_R–for valid conversion results. If the

reference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling

capacitors are required. See Section 7.40 and Section 7.41.

(3) The internal reference supply current is not included in current consumption parameter I_{ADC12_A}

(4) ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0.

.

7.36 12-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

For specified performance of ADC12 linearity

parameters using an external reference voltage or

AVCC as reference. ⁽¹⁾

0.45

4.8

5.0

f_ADC12CLK

ADC conversion clock

For specified performance of ADC12 linearity

parameters using the internal reference. ⁽²⁾

2.2 V, 3 V

MHz

4.0

0.45

4.2

2.4

4.8

For specified performance of ADC12 linearity

parameters using the internal reference. ⁽³⁾

2.7

Internal ADC12 oscillator

f_ADC12OSC

t_CONVERT

t_Sample

ADC12DIV = 0, f_ADC12CLK= f_ADC12OSC

2.2 V, 3 V

5.4 MHz

3.1

(4)

REFON = 0, Internal oscillator,

ADC12OSC used for ADC conversion clock

2.4

Conversion time

Sampling time

µs

External f_ADC12CLKfrom ACLK, MCLK, or SMCLK,

ADC12SSEL ≠ 0

(5)

R_S= 400 Ω, R_I= 1000 Ω, C_I= 20 pF,

2.2 V, 3 V

1000

ns

(6)

τ = [R_S+ R_I] × C_I

(1) REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0,

SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the

specified performance of the ADC12 linearity is ensured with f_ADC12CLKmaximum of 5.0 MHz.

(2) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1

(3) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when

using the ADC12OSC divided by 2.

(4) The ADC12OSC is sourced directly from MODOSC inside the UCS.

(5) 13 × ADC12DIV × 1/f_ADC12CLK

(6) Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:

t_Sample= ln(2ⁿ⁺¹) x (R_S+ R_I) × C_I+ 800 ns, where n = ADC resolution = 12, R_S= external source resistance

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7.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as

Reference Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Integral linearity error ⁽¹⁾

Differential linearity error ⁽¹⁾

Offset error ⁽³⁾

TEST CONDITIONS

1.4 V ≤ dVREF ≤ 1.6 V ⁽²⁾

V_CC

MIN

TYP

±2.0

±1.7

±1.0

±2.0

±3.5

MAX UNIT

LSB

E_I

2.2 V, 3 V

1.6 V < dVREF ⁽²⁾

(2)

E_D

E_O

E_G

E_T

2.2 V, 3 V

LSB

dVREF ≤ 2.2 V ⁽²⁾

LSB

dVREF > 2.2 V ⁽²⁾

Gain error ⁽³⁾

LSB

(2)

dVREF ≤ 2.2 V ⁽²⁾

dVREF > 2.2 V ⁽²⁾

Total unadjusted error

LSB

(1) Parameters are derived using the histogram method.

(2) The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = V_R+- V_R-, V_R+< AVCC, V_R-> AVSS.

Unless otherwise mentioned, dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω and two decoupling capacitors,

10 µF and 100 nF, should be connected to VREF to decouple the dynamic current. See also the MSP430F5xx and MSP430F6xx

Family User's Guide.

(3) Parameters are derived using a best fit curve.

7.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS ⁽¹⁾

V_CC

MIN

TYP

±1.7

MAX UNIT

ADC12SR = 0, REFOUT = 1

f_ADC12CLK≤ 4.0 MHz

f_ADC12CLK≤ 2.7 MHz

f_ADC12CLK≤ 4.0 MHz

f_ADC12CLK≤ 2.7 MHz

f_ADC12CLK≤ 4.0 MHz

f_ADC12CLK≤ 2.7 MHz

f_ADC12CLK≤ 4.0 MHz

f_ADC12CLK≤ 2.7 MHz

f_ADC12CLK≤ 4.0 MHz

Integral linearity

error ⁽²⁾

E_I

2.2 V, 3 V

LSB

ADC12SR = 0, REFOUT = 0

ADC12SR = 0, REFOUT = 1

ADC12SR = 0, REFOUT = 0

ADC12SR = 0, REFOUT = 1

ADC12SR = 0, REFOUT = 0

ADC12SR = 0, REFOUT = 1

ADC12SR = 0, REFOUT = 0

ADC12SR = 0, REFOUT = 1

±2.5

+1.5

Differential

E_D

2.2 V, 3 V

+1.0

LSB

linearity error ⁽²⁾

+2.5

±4.0

E_O

E_G

Offset error ⁽³⁾

Gain error ⁽³⁾

2.2 V, 3 V

LSB

±4.0

±2.5

LSB

VREF

LSB

±1.5% ⁽⁴⁾

Total

±5

E_T

unadjusted

error

2.2 V, 3 V

ADC12SR = 0, REFOUT = 0

f_ADC12CLK≤ 2.7 MHz

±1.5% ⁽⁴⁾

VREF

(1) The internal reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 1. dVREF = V_R+- V_R-

.

(2) Parameters are derived using the histogram method.

(3) Parameters are derived using a best fit curve.

(4) The gain error and total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In this

mode the reference voltage used by the ADC12_A is not available on a pin.

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7.39 12-Bit ADC, Temperature Sensor and Built-In V_MID

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

2.2 V

3 V

MIN

TYP

680

2.25

MAX UNIT

ADC12ON = 1, INCH = 0Ah,

T_A= 0°C

V_SENSOR

See ⁽²⁾

mV

2.2 V

3 V

TC_SENSOR

ADC12ON = 1, INCH = 0Ah

mV/°C

2.2 V

3 V

100

Sample time required if

channel 10 is selected ⁽³⁾

ADC12ON = 1, INCH = 0Ah,

Error of conversion result ≤ 1 LSB

t_{SENSOR(sample)}

µs

AV_CCdivider at channel 11,

V_AVCCfactor

ADC12ON = 1, INCH = 0Bh

0.48

0.5

0.52 V_AVCC

V_MID

2.2 V

3 V

1.04

1.44

1.1

1.5

1.14

V

1.56

AV_CCdivider at channel 11

Sample time required if

channel 11 is selected ⁽⁴⁾

ADC12ON = 1, INCH = 0Bh,

Error of conversion result ≤ 1 LSB

t_VMID(sample)

2.2 V, 3 V

1000

ns

(1) The temperature sensor is provided by the REF module. See the REF module parametric I_REF+regarding the current consumption of

the temperature sensor.

(2) The temperature sensor offset can be significant. A single-point calibration is recommended to minimize the offset error of the built-in

temperature sensor. The TLV structure contains calibration values for 30°C ± 3°C and 85°C ± 3°C for each of the available reference

voltage levels. The sensor voltage can be computed as V_SENSE= TC_SENSOR* (Temperature,°C) + V_SENSOR, where TC_SENSORand

V_SENSORcan be computed from the calibration values for higher accuracy. See also the MSP430F5xx and MSP430F6xx Family User's

Guide.

(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t_SENSOR(on)

(4) The on-time t_VMID(on)is included in the sampling time t_VMID(sample); no additional on time is needed.

.

7.40 REF, External Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Positive external reference

voltage input

(1)

V_eREF+

V_eREF+> V_REF–/V_eREF–

1.4

AV_CC

1.2

V

Negative external reference

voltage input

(2)

V_REF–/V_eREF–

V_eREF+> V_REF–/V_eREF–

0

(V_eREF+

V_REF–/V_eREF–

–

Differential external reference

voltage input

(3)

V_eREF+> V_REF–/V_eREF–

1.4 V ≤ V_eREF+≤ V_AVCC

1.4

AV_CC

)

,

V_eREF–= 0 V, f_ADC12CLK= 5 MHz,

T_J= 25°C

ADC12SHTx = 1h,

2.2 V, 3 V

±26

µA

I_VeREF+,

I_{VREF–/VeREF–}

Conversion rate 200 ksps

Static input current

1.4 V ≤ V_eREF+≤ V_AVCC

,

V_eREF–= 0 V, f_ADC12CLK= 5 MHz,

ADC12SHTx = 8h,

Conversion rate 20 ksps

-2.5

2.5

µA

µF

Capacitance at V_REF+and V_REF-

terminals

C_VREF+/-

See ⁽⁴⁾

10

(1) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

(2) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

accuracy requirements.

(3) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with

reduced accuracy requirements.

(4) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external

reference source if it is used for the ADC12_A. See also the MSP430F5xx and MSP430F6xx Family User's Guide.

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7.41 REF, Built-In Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

REFVSEL = {2} for 2.5 V,

REFON = REFOUT = 1, I_VREF+= 0 A

3 V

2.50 ±2.5%

1.98 ±2.5%

1.49 ±2.5%

Positive built-in reference

voltage output

REFVSEL = {1} for 2.0 V,

REFON = REFOUT = 1, I_VREF+= 0 A

V_REF+

3 V

V

REFVSEL = {0} for 1.5 V,

REFON = REFOUT = 1, I_VREF+= 0 A

2.2 V, 3 V

REFVSEL = {0} for 1.5 V

REFVSEL = {1} for 2.0 V

REFVSEL = {2} for 2.5 V

2.2

2.3

2.8

AV_CCminimum voltage,

Positive built-in reference

active

AV_CC(min)

ADC12SR = 1, REFON = 1, REFOUT = 0,

REFBURST = 0

3 V

70

µA

mA

µA

ADC12SR = 1, REFON = 1, REFOUT = 1,

REFBURST = 0

0.45

Operating supply current into

AV_CCterminal ^{(2) (3)}

I_REF+

ADC12SR = 0, REFON = 1, REFOUT = 0,

REFBURST = 0

210

350

2

ADC12SR = 0, REFON = 1, REFOUT = 1,

REFBURST = 0

0.95

mA

REFVSEL = (0, 1, 2}

Load-current regulation, V_REFI_VREF+= +10 µA/–1000 µA

I_L(VREF+)

2500

µV/mA

pF

₊terminal ⁽⁴⁾

AV_CC= AV_{CC (min)}for each reference level,

REFVSEL = (0, 1, 2}, REFON = REFOUT = 1

Capacitance at VREF+

terminals

C_VREF+

REFON = REFOUT = 1

20

100

I_VREF+= 0 A,

REFVSEL = (0, 1, 2}, REFON = 1,

REFOUT = 0 or 1

Temperature coefficient of

built-in reference ⁽⁵⁾

ppm/

°C

TC_REF+

30

AV_CC= AV_{CC (min)}- AV_CC(max), T_J= 25°C,

REFVSEL = (0, 1, 2}, REFON = 1,

REFOUT = 0 or 1

Power supply rejection ratio

(DC)

PSRR_DC

PSRR_AC

120

µV/V

AV_CC= AV_{CC (min)}- AV_CC(max), T_J= 25°C,

Power supply rejection ratio f = 1 kHz, ΔVpp = 100 mV,

6.4

75

mV/V

(AC)

REFVSEL = (0, 1, 2}, REFON = 1,

REFOUT = 0 or 1

AV_CC= AV_{CC (min)}- AV_CC(max)

,

REFVSEL = (0, 1, 2}, REFOUT = 0,

REFON = 0 → 1

Settling time of reference

voltage ⁽⁶⁾

t_SETTLE

µs

AV_CC= AV_{CC (min)}- AV_CC(max)

,

C_VREF= C_VREF(max),

REFVSEL = (0, 1, 2}, REFOUT = 1,

REFON = 0 → 1

(1) The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers,

one smaller and one larger for driving the V_REF+terminal. When REFOUT = 1, the reference is available at the V_REF+terminal, as well

as, used as the reference for the conversion and utilizes the larger buffer. When REFOUT = 0, the reference is only used as the

reference for the conversion and utilizes the smaller buffer.

(2) The internal reference current is supplied via terminal AV_CC. Consumption is independent of the ADC12ON control bit, unless a

conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current

contribution of the larger buffer without external load.

(3) The temperature sensor is provided by the REF module. Its current is supplied via terminal AV_CCand is equivalent to I_REF+with

REFON =1 and REFOUT = 0.

(4) Contribution only due to the reference and buffer including package. This does not include resistance due to PCB trace, etc.

(5) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C)/(85°C – (–40°C)).

(6) The condition is that the error in a conversion started after t_REFONis less than ±0.5 LSB. The settling time depends on the external

capacitive load when REFOUT = 1.

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7.42 Flash Memory

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

DV_{CC(PGM/ERASE)}Program and erase supply voltage

1.8

3.6

7

V

I_PGM

Average supply current from DVCC during program

3

mA

I_ERASE

Average supply current from DVCC during erase

7

Average supply current from DVCC during mass erase or

bank erase

I_MERASE, I_BANK

t_CPT

7

mA

Cumulative program time

See ⁽¹⁾

16

ms

cycles

years

µs

Program and erase endurance

Data retention duration ⁽²⁾

T_J= -40°C to 105°C

T_J= 25°C

See ⁽³⁾

10⁴

100

64

10⁵

t_Retention

t_Word

Word or byte program time

85

65

t_{Block, 0}

Block program time for first byte or word

See ⁽³⁾

49

µs

Block program time for each additional byte or word, except

for last byte or word

t_{Block, 1–(N–1)}

t_{Block, N}

See ⁽³⁾

37

55

23

49

73

32

µs

Block program time for last byte or word

Erase time for segment, mass erase, and bank erase when

available.

t_Erase

ms

MCLK frequency in marginal read mode

(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)

f_MCLK,MGR

0

1

MHz

(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming

methods: individual word/byte write and block write modes.

(2) These values are hardwired into the flash controller's state machine.

(3) The data retention specification is based on qualification stress testing at 170°C for 420 hours with temperature derating based on an

Arrhenius model with activation energy of 0.6 eV. Additional flash retention documentation is provided in application report SLAA392.

7.43 JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

V_CC

MIN

TYP

MAX UNIT

f_SBW

Spy-Bi-Wire input frequency

2.2 V, 3 V

0

20 MHz

t_SBW,Low

t_{SBW, En}

t_SBW,Rst

Spy-Bi-Wire low clock pulse duration

0.025

15

1

µs

Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) ⁽¹⁾

Spy-Bi-Wire return to normal operation time

15

0

100

5

µs

2.2 V

3 V

MHz

f_TCK

TCK input frequency, 4-wire JTAG ⁽²⁾

Internal pulldown resistance on TEST

0

10 MHz

80 kΩ

R_internal

2.2 V, 3 V

45

60

(1) Tools accessing the Spy-Bi-Wire interface must wait for the t_SBW,Entime after pulling the TEST/SBWTCK pin high before applying the

first SBWTCK clock edge.

(2) f_TCKmay be restricted to meet the timing requirements of the module selected.

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8 Detailed Description

8.1 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,

other than program-flow instructions, are performed as register operations in conjunction with seven addressing

modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register

operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant

generator, respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all

instructions.

The instruction set consists of the original 51 instructions with three formats and seven address modes and

additional instructions for the expanded address range. Each instruction can operate on word and byte data.

Program Counter

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R4

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15

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8.2 Operating Modes

The MCU has one active mode and six software selectable low-power modes of operation. An interrupt event

can wake up the device from any of the low-power modes, service the request, and restore back to the low-

power mode on return from the interrupt program.

The following seven operating modes can be configured by software:

•

Active mode (AM)

– All clocks are active

•

Low-power mode 0 (LPM0)

– CPU is disabled

– ACLK and SMCLK remain active, MCLK is disabled

– FLL loop control remains active

Low-power mode 1 (LPM1)

•

– CPU is disabled

– FLL loop control is disabled

– ACLK and SMCLK remain active, MCLK is disabled

Low-power mode 2 (LPM2)

– CPU is disabled

– MCLK and FLL loop control and DCOCLK are disabled

– DCO's dc-generator remains enabled

– ACLK remains active

•

Low-power mode 3 (LPM3)

– CPU is disabled

– MCLK, FLL loop control, and DCOCLK are disabled

– DCO's dc generator is disabled

– ACLK remains active

Low-power mode 4 (LPM4)

– CPU is disabled

– ACLK is disabled

– MCLK, FLL loop control, and DCOCLK are disabled

– DCO's dc generator is disabled

– Crystal oscillator is stopped

– Complete data retention

•

Low-power mode 4.5 (LPM4.5)

– Internal regulator disabled

– No data retention

– Wakeup from RST, digital I/O

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8.3 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The

vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 8-1. Interrupt Sources, Flags, and Vectors

WORD

ADDRESS

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT

PRIORITY

System Reset

Power-Up

External Reset

WDTIFG, KEYV (SYSRSTIV) ^{(1) (2)}

Reset

0FFFEh

63, highest

Watchdog Timeout, Password Violation

Flash Memory Password Violation

PMM Password Violation

System NMI

PMM

Vacant Memory Access

JTAG Mailbox

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG,

VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV)

(Non)maskable

0FFFCh

0FFFAh

62

61

(1)

User NMI

NMI

Oscillator Fault

NMIIFG, OFIFG, ACCVIFG (SYSUNIV) ^{(1) (2)}

TBCCR0 CCIFG0 ⁽³⁾

Flash Memory Access Violation

TB0

Maskable

0FFF8h

0FFF6h

60

59

TBCCR1 CCIFG1 to TBCCR6 CCIFG6,

TBIFG (TBIV) ^{(1) (3)}

Watchdog Timer_A Interval Timer Mode

USCI_A0 Receive and Transmit

USCI_B0 Receive and Transmit

ADC12_A

WDTIFG

Maskable

0FFF4h

0FFF2h

0FFF0h

0FFEEh

0FFECh

58

57

56

55

54

UCA0RXIFG, UCA0TXIFG (UCA0IV) ^{(1) (3)}

UCB0RXIFG, UCB0TXIFG (UCB0IV) ^{(1) (3)}

ADC12IFG0 to ADC12IFG15 (ADC12IV) ^{(1) (3)}

TA0CCR0 CCIFG0 ⁽³⁾

TA0

TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,

TA0IFG (TA0IV) ^{(1) (3)}

TA0

Maskable

0FFEAh

53

USCI_A2 Receive and Transmit

UCA2RXIFG, UCA2TXIFG (UCA2IV) ^{(1) (3)}

UCB2RXIFG, UCB2TXIFG (UCB2IV) ^{(1) (3)}

DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) ^{(1) (3)}

TA1CCR0 CCIFG0 ⁽³⁾

Maskable

0FFE8h

0FFE6h

0FFE4h

0FFE2h

52

51

50

49

USCI_B2 Receive and Transmit

DMA

TA1

TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,

TA1IFG (TA1IV) ^{(1) (3)}

TA1

Maskable

0FFE0h

48

I/O Port P1

P1IFG.0 to P1IFG.7 (P1IV) ^{(1) (3)}

UCA1RXIFG, UCA1TXIFG (UCA1IV) ^{(1) (3)}

UCB1RXIFG, UCB1TXIFG (UCB1IV) ^{(1) (3)}

UCA3RXIFG, UCA3TXIFG (UCA3IV) ^{(1) (3)}

UCB3RXIFG, UCB3TXIFG (UCB3IV) ^{(1) (3)}

P2IFG.0 to P2IFG.7 (P2IV) ^{(1) (3)}

Maskable

0FFDEh

0FFDCh

0FFDAh

0FFD8h

0FFD6h

0FFD4h

47

46

45

44

43

42

USCI_A1 Receive and Transmit

USCI_B1 Receive and Transmit

USCI_A3 Receive and Transmit

USCI_B3 Receive and Transmit

I/O Port P2

RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG,

RT1PSIFG (RTCIV) ^{(1) (3)}

RTC_A

Maskable

0FFD2h

41

0FFD0h

⋮

40

Reserved

Reserved ⁽⁴⁾

⋮

0FF80h

0, lowest

(1) Multiple source flags.

(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.

(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

(3) Interrupt flags are located in the module.

(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To

maintain compatibility with other devices, it is recommended to reserve these locations.

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8.4 Memory Organization

MSP430F5438A

Memory (flash)

Main: interrupt vector

Main: code memory

Total Size

Flash

256 KB

00FFFFh–00FF80h

045BFFh–005C00h

Flash

Bank D

Bank C

Bank B

Bank A

64 KB

03FFFFh–030000h

64 KB

02FFFFh–020000h

Main: code memory

64 KB

01FFFFh–010000h

64 KB

045BFFh–040000h

00FFFFh–005C00h

Size

16 KB

Sector 3

4 KB

005BFFh–004C00h

Sector 2

Sector 1

Sector 0

Info A

4 KB

RAM

004BFFh–003C00h

4 KB

003BFFh–002C00h

4 KB

002BFFh–001C00h

128 B

0019FFh–001980h

Info B

128 B

00197Fh–001900h

Information memory (flash)

Info C

Info D

BSL 3

BSL 2

BSL 1

BSL 0

Size

128 B

0018FFh–001880h

128 B

00187Fh–001800h

512 B

0017FFh–001600h

512 B

0015FFh–001400h

Bootstrap loader (BSL) memory (Flash)

512 B

0013FFh–001200h

512 B

0011FFh–001000h

4KB

Peripherals

000FFFh–000000h

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8.5 Bootloader (BSL)

The BSL lets users program the flash memory or RAM using a UART serial interface. Access to the device

memory through the BSL is protected by an user-defined password. Use of the BSL requires four pins as shown

in Table 8-2. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins.

For complete description of the features of the BSL and its implementation, see the MSP430™ Flash Devices

Bootloader (BSL) User's Guide.

Table 8-2. BSL Pin Requirements and Functions

DEVICE SIGNAL

BSL FUNCTION

Entry sequence signal

Data transmit

RST/NMI/SBWTDIO

TEST/SBWTCK

P1.1

P1.2

VCC

VSS

Data receive

Power supply

Ground supply

8.6 JTAG Operation

8.6.1 JTAG Standard Interface

The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving

data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the

JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430

development tools and device programmers. The JTAG pin requirements are shown in Table 8-3. For further

details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's

Guide. For the description of the Spy-Bi-Wire interface and its implementation, see the MSP430 Programming

With the JTAG Interface User's Guide.

Table 8-3. JTAG Pin Requirements and Functions

DEVICE SIGNAL

DIRECTION

FUNCTION

JTAG clock input

JTAG state control

JTAG data input/TCLK input

JTAG data output

Enable JTAG pins

External reset

PJ.3/TCK

IN

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

IN

OUT

IN

TEST/SBWTCK

RST/NMI/SBWTDIO

VCC

IN

Power supply

VSS

Ground supply

8.6.2 Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. Spy-

Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire

interface pin requirements are shown in Table 8-4. For further details on interfacing to development tools and

device programmers, see the MSP430 Hardware Tools User's Guide. For the description of the Spy-Bi-Wire

interface and its implementation, see the MSP430 Programming With the JTAG Interface User's Guide.

Table 8-4. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL

TEST/SBWTCK

RST/NMI/SBWTDIO

VCC

DIRECTION

FUNCTION

Spy-Bi-Wire clock input

Spy-Bi-Wire data input/output

Power supply

IN

IN, OUT

VSS

Ground supply

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8.7 Flash Memory

The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the

CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the

flash memory include:

•

Flash memory has n segments of main memory and four segments of information memory (A to D) of

128 bytes each. Each segment in main memory is 512 bytes in size.

•

Segments 0 to n may be erased in one step, or each segment may be individually erased.

Segments A to D can be erased individually. Segments A to D are also called information memory.

Segment A can be locked separately.

8.8 RAM Memory

The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,

however all data is lost. Features of the RAM memory include:

•

RAM memory has n sectors. The size of a sector can be found in Memory Organization.

Each sector 0 to n can be complete disabled; however, data retention is lost.

Each sector 0 to n automatically enters low-power retention mode when possible.

For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.

8.9 Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all

instructions. For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide.

8.9.1 Digital I/O

There are up to ten 8-bit I/O ports implemented: For 100-pin options, P1 through P10 are complete. P11 contains

three individual I/O ports. For 80-pin options, P1 through P7 are complete. P8 contains seven individual I/O

ports. P9 through P11 do not exist. Port PJ contains four individual I/O ports, common to all devices.

•

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt conditions is possible.

Pullup or pulldown on all ports is programmable.

Drive strength on all ports is programmable.

Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1 and P2.

Read/write access to port-control registers is supported by all instructions.

Ports can be accessed byte-wise (P1 through P11) or word-wise in pairs (PA through PF).

8.9.2 Oscillator and System Clock

The clock system in the MSP430x5xx family of devices is supported by the Unified Clock System (UCS) module

that includes support for a 32-kHz watch crystal oscillator (XT1 LF mode), an internal very-low-power low-

frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal digitally

controlled oscillator (DCO), and a high-frequency crystal oscillator (XT1 HF mode or XT2). The UCS module is

designed to meet the requirements of both low system cost and low power consumption. The UCS module

features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the

DCO frequency to a programmable multiple of the selected FLL reference frequency. The internal DCO provides

a fast turn-on clock source and stabilizes in less than 5 µs. The UCS module provides the following clock

signals:

•

Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal, a high-frequency crystal, the internal low-

frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally controlled

oscillator DCO.

•

Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made

available to ACLK.

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•

Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by

same sources made available to ACLK.

•

ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

8.9.3 Power Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains

programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor

(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is

implemented to provide the proper internal reset signal to the device during power-on and power-off. The

SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply

voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not

automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.

8.9.4 Hardware Multiplier (MPY)

The multiplication operation is supported by a dedicated peripheral module. The module performs operations

with 32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned

multiplication as well as signed and unsigned multiply and accumulate operations.

8.9.5 Real-Time Clock (RTC_A)

The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated real-

time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers that

can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar mode

integrates an internal calendar which compensates for months with less than 31 days and includes leap year

correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware.

8.9.6 Watchdog Timer (WDT_A)

The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a

software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog

function is not needed in an application, the module can be configured as an interval timer and can generate

interrupts at selected time intervals.

8.9.7 System Module (SYS)

The SYS module handles many of the system functions within the device. These include power on reset and

power up clear handling, NMI source selection and management, reset interrupt vector generators, boot strap

loader entry mechanisms, as well as, configuration management (device descriptors). It also includes a data

exchange mechanism via JTAG called a JTAG mailbox that can be used in the application.

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Table 8-5. System Module Interrupt Vector Registers

INTERRUPT VECTOR REGISTER

ADDRESS

INTERRUPT EVENT

No interrupt pending

Brownout (BOR)

RST/NMI (POR)

PMMSWBOR (BOR)

Wakeup from LPMx.5

Security violation (BOR)

SVSL (POR)

VALUE

00h

PRIORITY

SYSRSTIV, System Reset

019Eh

02h

Highest

04h

06h

08h

0Ah

0Ch

SVSH (POR)

0Eh

SVML_OVP (POR)

SVMH_OVP (POR)

PMMSWPOR (POR)

WDT timeout (PUC)

WDT password violation (PUC)

KEYV flash password violation (PUC)

Reserved

10h

12h

14h

16h

18h

1Ah

1Ch

Peripheral area fetch (PUC)

PMM password violation (PUC)

Reserved

1Eh

20h

22h to 3Eh

00h

Lowest

Highest

SYSSNIV, System NMI

019Ch

No interrupt pending

SVMLIFG

02h

SVMHIFG

04h

SVSMLDLYIFG

SVSMHDLYIFG

VMAIFG

06h

08h

0Ah

JMBINIFG

0Ch

JMBOUTIFG

0Eh

SVMLVLRIFG

10h

SVMHVLRIFG

12h

Reserved

14h to 1Eh

00h

Lowest

Highest

SYSUNIV, User NMI

019Ah

No interrupt pending

NMIFG

02h

OFIFG

04h

ACCVIFG

06h

Reserved

08h

Reserved

0Ah to 1Eh

Lowest

8.9.8 DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention.

For example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM.

Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces

system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move

data to or from a peripheral.

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Table 8-6. DMA Trigger Assignments

CHANNEL

TRIGGER

0

1

2

0

DMAREQ

1

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

Reserved

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

Reserved

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

Reserved

2

3

4

5

6

7

8

Reserved

9

Reserved

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Reserved

UCA0RXIFG

UCA0TXIFG

UCB0RXIFG

UCB0TXIFG

UCA1RXIFG

UCA1TXIFG

UCB1RXIFG

UCB1TXIFG

ADC12IFGx

Reserved

UCA0RXIFG

UCA0TXIFG

UCB0RXIFG

UCB0TXIFG

UCA1RXIFG

UCA1TXIFG

UCB1RXIFG

UCB1TXIFG

ADC12IFGx

Reserved

UCA0RXIFG

UCA0TXIFG

UCB0RXIFG

UCB0TXIFG

UCA1RXIFG

UCA1TXIFG

UCB1RXIFG

UCB1TXIFG

ADC12IFGx

Reserved

MPY ready

DMA2IFG

MPY ready

DMA0IFG

MPY ready

DMA1IFG

DMAE0

8.9.9 Universal Serial Communication Interface (USCI)

The USCI modules are used for serial data communication. The USCI module supports synchronous

communication protocols such as SPI (3 or 4 pin) and I²C, and asynchronous communication protocols such as

UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions,

A and B.

The USCI_An module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, or IrDA.

The USCI_Bn module provides support for SPI (3 pin or 4 pin) or I2C.

The MSP430F5438A, MSP430F5436A, and MSP430F5419A include four complete USCI modules (n = 0 to 3).

The MSP430F5437A, MSP430F5435A, and MSP430F5418A include two complete USCI modules (n = 0 to 1).

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8.9.10 TA0

TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. It can support multiple capture/

compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be

generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 8-7. TA0 Signal Connections

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

INPUT PIN

NUMBER

DEVICE INPUT MODULE INPUT

MODULE

BLOCK

OUTPUT PIN NUMBER

SIGNAL

17, H1-P1.0

TA0CLK

ACLK

TACLK

ACLK

Timer

CCR0

NA

SMCLK

TA0CLK

TA0.0

SMCLK

TACLK

CCI0A

CCI0B

17, H1-P1.0

18, H4-P1.1

57, H9-P8.0

18, H4-P1.1

57, H9-P8.0

TA0.0

TA0

TA0.0

ADC12 (internal)

ADC12SHSx = {1}

DV_SS

GND

DV_CC

TA0.1

DV_SS

DV_CC

TA0.2

DV_SS

DV_CC

TA0.3

DV_SS

DV_CC

TA0.4

DV_SS

DV_CC

V_CC

CCI1A

CCI1B

GND

19, J4-P1.2

58, H11-P8.1

CCR1

CCR2

CCR3

CCR4

TA1

TA2

TA3

TA4

TA0.1

TA0.2

TA0.3

TA0.4

V_CC

20, J1-P1.3

CCI2A

CCI2B

GND

20, J1-P1.3

59, H12-P8.2

V_CC

21, J2-P1.4

60, G9-P8.3

CCI3A

CCI3B

GND

21, J2-P1.4

60, G9-P8.3

V_CC

22, K1-P1.5

CCI4A

CCI4B

GND

22, K1-P1.5

61, G11-P8.4

V_CC

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8.9.11 TA1

TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple

capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may

be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 8-8. TA1 Signal Connections

INPUT PIN

NUMBER

DEVICE INPUT

SIGNAL

MODULE INPUT

SIGNAL

MODULE

OUTPUT SIGNAL

DEVICE OUTPUT

SIGNAL

OUTPUT PIN

NUMBER

MODULE BLOCK

25, M1-P2.0

TA1CLK

ACLK

SMCLK

TA1CLK

TA1.0

DV_SS

TACLK

ACLK

SMCLK

TACLK

CCI0A

CCI0B

GND

Timer

NA

TA0

TA1

TA2

NA

25, M1-P2.0

26, L2-P2.1

65, F11-P8.5

26, L2-P2.1

65, F11-P8.5

CCR0

CCR1

CCR2

TA1.0

TA1.1

TA1.2

DV_CC

V_CC

27, M2-P2.2

66, E11-P8.6

TA1.1

DV_SS

CCI1A

CCI1B

GND

27, M2-P2.2

66, E11-P8.6

DV_CC

V_CC

28, L3-P2.3

56, J12-P7.3

TA1.2

DV_SS

CCI2A

CCI2B

GND

28, L3-P2.3

56, J12-P7.3

DV_CC

V_CC

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8.9.12 TB0

TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It can support multiple

capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may

be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 8-9. TB0 Signal Connections

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

INPUT PIN

NUMBER

DEVICE INPUT MODULE INPUT

MODULE

BLOCK

OUTPUT PIN NUMBER

SIGNAL

50, M12-P4.7

TB0CLK

ACLK

TBCLK

ACLK

Timer

CCR0

NA

SMCLK

TB0CLK

TB0.0

SMCLK

TBCLK

CCI0A

50, M12-P4.7

43, J8-P4.0

ADC12 (internal)

ADC12SHSx = {2}

43, J8-P4.0

TB0.0

CCI0B

TB0

TB0.0

DV_SS

DV_CC

TB0.1

GND

V_CC

44, M9-P4.1

CCI1A

44, M9-P4.1

ADC12 (internal)

ADC12SHSx = {3}

TB0.1

CCI1B

CCR1

TB1

TB0.1

DV_SS

DV_CC

GND

V_CC

45, L9-P4.2

TB0.2

DV_SS

CCI2A

CCI2B

GND

V_CC

45, L9-P4.2

46, L10-P4.3

47, M10-P4.4

48, L11-P4.5

49, M11-P4.6

CCR2

CCR3

CCR4

CCR5

CCR6

TB2

TB3

TB4

TB5

TB6

TB0.2

TB0.3

TB0.4

TB0.5

TB0.6

DV_CC

46, L10-P4.3

TB0.3

DV_SS

CCI3A

CCI3B

GND

V_CC

DV_CC

47, M10-P4.4

TB0.4

DV_SS

CCI4A

CCI4B

GND

V_CC

DV_CC

48, L11-P4.5

TB0.5

DV_SS

CCI5A

CCI5B

GND

V_CC

DV_CC

49, M11-P4.6

TB0.6

ACLK (internal)

DV_SS

CCI6A

CCI6B

GND

V_CC

DV_CC

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8.9.13 ADC12_A

The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR

core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversion-

and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU

intervention.

8.9.14 CRC16

The CRC16 module produces a signature based on a sequence of entered data values and can be used for data

checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.

8.9.15 REF Voltage Reference

The reference module (REF) is responsible for generation of all critical reference voltages that can be used by

the various analog peripherals in the device.

8.9.16 Embedded Emulation Module (EEM) (L Version)

The EEM supports real-time in-system debugging. The L version of the EEM implemented on all devices has the

following features:

•

Eight hardware triggers or breakpoints on memory access

Two hardware trigger or breakpoint on CPU register write access

Up to ten hardware triggers can be combined to form complex triggers or breakpoints

Two cycle counters

Sequencer

State storage

Clock control on module level

8.9.17 Peripheral File Map

Table 8-10. Peripherals

OFFSET ADDRESS

RANGE

MODULE NAME

BASE ADDRESS

Special Functions (see Table 8-11)

PMM (see Table 8-12)

0100h

0120h

0140h

0150h

0158h

015Ch

0160h

0180h

01B0h

0200h

0220h

0240h

0260h

0280h

02A0h

0320h

0340h

0380h

03C0h

04A0h

04C0h

000h - 01Fh

000h - 010h

000h - 00Fh

000h - 007h

000h - 001h

000h - 01Fh

000h - 001h

000h - 01Fh

000h - 00Bh

000h - 00Ah

000h - 01Fh

000h - 02Eh

000h - 01Bh

000h - 02Fh

Flash Control (see Table 8-13)

CRC16 (see Table 8-14)

RAM Control (see Table 8-15)

Watchdog (see Table 8-16)

UCS (see Table 8-17)

SYS (see Table 8-18)

Shared Reference (see Table 8-19)

Port P1, P2 (see Table 8-20)

Port P3, P4 (see Table 8-21)

Port P5, P6 (see Table 8-22)

Port P7, P8 (see Table 8-23)

Port P9, P10 (see Table 8-24)

Port P11 (see Table 8-25)

Port PJ (see Table 8-26)

TA0 (see Table 8-27)

TA1 (see Table 8-28)

TB0 (see Table 8-29)

Real Timer Clock (RTC_A) (see Table 8-30)

32-bit Hardware Multiplier (see Table 8-31)

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Table 8-10. Peripherals (continued)

OFFSET ADDRESS

RANGE

MODULE NAME

BASE ADDRESS

DMA General Control (see Table 8-32)

DMA Channel 0 (see Table 8-32)

DMA Channel 1 (see Table 8-32)

DMA Channel 2 (see Table 8-32)

USCI_A0 (see Table 8-33)

USCI_B0 (see Table 8-34)

USCI_A1 (seeTable 8-35)

0500h

0510h

0520h

0530h

05C0h

05E0h

0600h

0620h

0640h

0660h

0680h

06A0h

0700h

000h - 00Fh

000h - 00Ah

000h - 01Fh

000h - 03Eh

USCI_B1 (see Table 8-36)

USCI_A2 (see Table 8-37)

USCI_B2 (see Table 8-38)

USCI_A3 (see Table 8-39)

USCI_B3 (see Table 8-40)

ADC12_A (see Table 8-41)

Table 8-11. Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION

REGISTER

OFFSET

SFR interrupt enable

SFR interrupt flag

SFRIE1

00h

02h

04h

SFRIFG1

SFR reset pin control

SFRRPCR

Table 8-12. PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION

REGISTER

OFFSET

PMM Control 0

PMMCTL0

00h

02h

04h

06h

0Ch

0Eh

10h

PMM control 1

PMMCTL1

SVSMHCTL

SVSMLCTL

PMMIFG

SVS high side control

SVS low side control

PMM interrupt flags

PMM interrupt enable

PMM power mode 5 control

PMMIE

PM5CTL0

Table 8-13. Flash Control Registers (Base Address: 0140h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Flash control 1

Flash control 3

Flash control 4

FCTL1

FCTL3

FCTL4

00h

04h

06h

Table 8-14. CRC16 Registers (Base Address: 0150h)

REGISTER DESCRIPTION

REGISTER

CRC data input

CRC16DI

00h

02h

04h

06h

CRC data input reverse byte

CRC initialization and result

CRC result reverse byte

CRCDIRB

CRCINIRES

CRCRESR

Table 8-15. RAM Control Registers (Base Address: 0158h)

REGISTER DESCRIPTION

REGISTER

OFFSET

RAM control 0

RCCTL0

00h

50

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Table 8-16. Watchdog Registers (Base Address: 015Ch)

REGISTER DESCRIPTION

REGISTER

OFFSET

Watchdog timer control

WDTCTL

00h

Table 8-17. UCS Registers (Base Address: 0160h)

REGISTER DESCRIPTION

REGISTER

UCS control 0

UCS control 1

UCS control 2

UCS control 3

UCS control 4

UCS control 5

UCS control 6

UCS control 7

UCS control 8

UCSCTL0

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

UCSCTL1

UCSCTL2

UCSCTL3

UCSCTL4

UCSCTL5

UCSCTL6

UCSCTL7

UCSCTL8

Table 8-18. SYS Registers (Base Address: 0180h)

REGISTER DESCRIPTION

REGISTER

OFFSET

System control

SYSCTL

00h

02h

06h

08h

0Ah

0Ch

0Eh

18h

1Ah

1Ch

1Eh

Bootstrap loader configuration area

JTAG mailbox control

SYSBSLC

SYSJMBC

SYSJMBI0

SYSJMBI1

SYSJMBO0

SYSJMBO1

SYSBERRIV

SYSUNIV

JTAG mailbox input 0

JTAG mailbox input 1

JTAG mailbox output 0

JTAG mailbox output 1

Bus Error vector generator

User NMI vector generator

System NMI vector generator

Reset vector generator

SYSSNIV

SYSRSTIV

Table 8-19. Shared Reference Registers (Base Address: 01B0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Shared reference control

REFCTL

00h

Table 8-20. Port P1, P2 Registers (Base Address: 0200h)

REGISTER DESCRIPTION

REGISTER

Port P1 input

P1IN

00h

02h

04h

06h

08h

0Ah

0Eh

18h

1Ah

1Ch

01h

03h

05h

07h

Port P1 output

Port P1 direction

P1OUT

P1DIR

P1REN

P1DS

P1SEL

P1IV

Port P1 pullup/pulldown enable

Port P1 drive strength

Port P1 selection

Port P1 interrupt vector word

Port P1 interrupt edge select

Port P1 interrupt enable

Port P1 interrupt flag

Port P2 input

P1IES

P1IE

P1IFG

P2IN

Port P2 output

P2OUT

P2DIR

P2REN

Port P2 direction

Port P2 pullup/pulldown enable

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Table 8-20. Port P1, P2 Registers (Base Address: 0200h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P2 drive strength

Port P2 selection

P2DS

P2SEL

P2IV

09h

0Bh

1Eh

19h

1Bh

1Dh

Port P2 interrupt vector word

Port P2 interrupt edge select

Port P2 interrupt enable

Port P2 interrupt flag

P2IES

P2IE

P2IFG

Table 8-21. Port P3, P4 Registers (Base Address: 0220h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P3 input

P3IN

00h

02h

04h

06h

08h

0Ah

01h

03h

05h

07h

09h

0Bh

Port P3 output

Port P3 direction

P3OUT

P3DIR

P3REN

P3DS

Port P3 pullup/pulldown enable

Port P3 drive strength

Port P3 selection

P3SEL

P4IN

Port P4 input

Port P4 output

P4OUT

P4DIR

P4REN

P4DS

Port P4 direction

Port P4 pullup/pulldown enable

Port P4 drive strength

Port P4 selection

P4SEL

Table 8-22. Port P5, P6 Registers (Base Address: 0240h)

REGISTER DESCRIPTION

REGISTER

Port P5 input

P5IN

00h

02h

04h

06h

08h

0Ah

01h

03h

05h

07h

09h

0Bh

Port P5 output

P5OUT

P5DIR

P5REN

P5DS

Port P5 direction

Port P5 pullup/pulldown enable

Port P5 drive strength

Port P5 selection

P5SEL

P6IN

Port P6 input

Port P6 output

P6OUT

P6DIR

P6REN

P6DS

Port P6 direction

Port P6 pullup/pulldown enable

Port P6 drive strength

Port P6 selection

P6SEL

Table 8-23. Port P7, P8 Registers (Base Address: 0260h)

REGISTER DESCRIPTION

REGISTER

Port P7 input

P7IN

00h

02h

04h

06h

08h

0Ah

01h

03h

05h

Port P7 output

P7OUT

P7DIR

P7REN

P7DS

Port P7 direction

Port P7 pullup/pulldown enable

Port P7 drive strength

Port P7 selection

Port P8 input

P7SEL

P8IN

Port P8 output

P8OUT

P8DIR

Port P8 direction

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Table 8-23. Port P7, P8 Registers (Base Address: 0260h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P8 pullup/pulldown enable

Port P8 drive strength

Port P8 selection

P8REN

P8DS

07h

09h

0Bh

P8SEL

Table 8-24. Port P9, P10 Registers (Base Address: 0280h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P9 input

P9IN

00h

02h

04h

06h

08h

0Ah

01h

03h

05h

07h

09h

0Bh

Port P9 output

P9OUT

P9DIR

P9REN

P9DS

Port P9 direction

Port P9 pullup/pulldown enable

Port P9 drive strength

Port P9 selection

P9SEL

P10IN

Port P10 input

Port P10 output

P10OUT

P10DIR

P10REN

P10DS

Port P10 direction

Port P10 pullup/pulldown enable

Port P10 drive strength

Port P10 selection

P10SEL

Table 8-25. Port P11 Registers (Base Address: 02A0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P11 input

P11IN

00h

02h

04h

06h

08h

0Ah

Port P11 output

P11OUT

P11DIR

P11REN

P11DS

Port P11 direction

Port P11 pullup/pulldown enable

Port P11 drive strength

Port P11 selection

P11SEL

Table 8-26. Port J Registers (Base Address: 0320h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port PJ input

PJIN

00h

02h

04h

06h

08h

Port PJ output

PJOUT

PJDIR

PJREN

PJDS

Port PJ direction

Port PJ pullup/pulldown enable

Port PJ drive strength

Table 8-27. TA0 Registers (Base Address: 0340h)

REGISTER DESCRIPTION

REGISTER

OFFSET

TA0 control

TA0CTL

00h

02h

04h

06h

08h

0Ah

10h

12h

14h

16h

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

Capture/compare control 3

Capture/compare control 4

TA0 counter register

TA0CCTL0

TA0CCTL1

TA0CCTL2

TA0CCTL3

TA0CCTL4

TA0R

Capture/compare register 0

Capture/compare register 1

Capture/compare register 2

TA0CCR0

TA0CCR1

TA0CCR2

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Table 8-27. TA0 Registers (Base Address: 0340h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

Capture/compare register 3

Capture/compare register 4

TA0 expansion register 0

TA0 interrupt vector

TA0CCR3

18h

1Ah

20h

2Eh

TA0CCR4

TA0EX0

TA0IV

Table 8-28. TA1 Registers (Base Address: 0380h)

REGISTER DESCRIPTION

REGISTER

OFFSET

TA1 control

TA1CTL

00h

02h

04h

06h

10h

12h

14h

16h

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

TA1 counter register

TA1CCTL0

TA1CCTL1

TA1CCTL2

TA1R

Capture/compare register 0

Capture/compare register 1

Capture/compare register 2

TA1 expansion register 0

TA1 interrupt vector

TA1CCR0

TA1CCR1

TA1CCR2

TA1EX0

TA1IV

Table 8-29. TB0 Registers (Base Address: 03C0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

TB0 control

TB0CTL

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

18h

1Ah

1Ch

1Eh

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

Capture/compare control 3

Capture/compare control 4

Capture/compare control 5

Capture/compare control 6

TB0 register

TB0CCTL0

TB0CCTL1

TB0CCTL2

TB0CCTL3

TB0CCTL4

TB0CCTL5

TB0CCTL6

TB0R

Capture/compare register 0

Capture/compare register 1

Capture/compare register 2

Capture/compare register 3

Capture/compare register 4

Capture/compare register 5

Capture/compare register 6

TB0 expansion register 0

TB0 interrupt vector

TB0CCR0

TB0CCR1

TB0CCR2

TB0CCR3

TB0CCR4

TB0CCR5

TB0CCR6

TB0EX0

TB0IV

Table 8-30. Real Time Clock Registers (Base Address: 04A0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

RTC control 0

RTCCTL0

00h

01h

02h

03h

08h

0Ah

0Ch

RTC control 1

RTCCTL1

RTCCTL2

RTCCTL3

RTCPS0CTL

RTCPS1CTL

RTCPS0

RTC control 2

RTC control 3

RTC prescaler 0 control

RTC prescaler 1 control

RTC prescaler 0

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Table 8-30. Real Time Clock Registers (Base Address: 04A0h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

RTC prescaler 1

RTCPS1

0Dh

0Eh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

RTC interrupt vector word

RTCIV

RTC seconds/counter register 1

RTC minutes/counter register 2

RTC hours/counter register 3

RTC day of week/counter register 4

RTC days

RTCSEC/RTCNT1

RTCMIN/RTCNT2

RTCHOUR/RTCNT3

RTCDOW/RTCNT4

RTCDAY

RTC month

RTCMON

RTC year low

RTCYEARL

RTC year high

RTCYEARH

RTCAMIN

RTC alarm minutes

RTC alarm hours

RTCAHOUR

RTCADOW

RTC alarm day of week

RTC alarm days

RTCADAY

Table 8-31. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

16-bit operand 1 – multiply

MPY

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

18h

1Ah

1Ch

1Eh

20h

22h

24h

26h

28h

2Ah

2Ch

16-bit operand 1 – signed multiply

16-bit operand 1 – multiply accumulate

16-bit operand 1 – signed multiply accumulate

16-bit operand 2

MPYS

MAC

MACS

OP2

16 × 16 result low word

RESLO

RESHI

16 × 16 result high word

16 × 16 sum extension register

SUMEXT

MPY32L

MPY32H

MPYS32L

MPYS32H

MAC32L

MAC32H

MACS32L

MACS32H

OP2L

32-bit operand 1 – multiply low word

32-bit operand 1 – multiply high word

32-bit operand 1 – signed multiply low word

32-bit operand 1 – signed multiply high word

32-bit operand 1 – multiply accumulate low word

32-bit operand 1 – multiply accumulate high word

32-bit operand 1 – signed multiply accumulate low word

32-bit operand 1 – signed multiply accumulate high word

32-bit operand 2 – low word

32-bit operand 2 – high word

OP2H

32 × 32 result 0 – least significant word

32 × 32 result 1

RES0

RES1

32 × 32 result 2

RES2

32 × 32 result 3 – most significant word

MPY32 control register 0

RES3

MPY32CTL0

Table 8-32. DMA Registers (Base Address DMA General Control: 0500h,

DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)

REGISTER DESCRIPTION

REGISTER

OFFSET

DMA channel 0 control

DMA0CTL

00h

02h

04h

DMA channel 0 source address low

DMA channel 0 source address high

DMA0SAL

DMA0SAH

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Table 8-32. DMA Registers (Base Address DMA General Control: 0500h,

DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

DMA channel 0 destination address low

DMA0DAL

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Eh

DMA channel 0 destination address high

DMA channel 0 transfer size

DMA channel 1 control

DMA0DAH

DMA0SZ

DMA1CTL

DMA1SAL

DMA1SAH

DMA1DAL

DMA1DAH

DMA1SZ

DMA channel 1 source address low

DMA channel 1 source address high

DMA channel 1 destination address low

DMA channel 1 destination address high

DMA channel 1 transfer size

DMA channel 2 control

DMA2CTL

DMA2SAL

DMA2SAH

DMA2DAL

DMA2DAH

DMA2SZ

DMA channel 2 source address low

DMA channel 2 source address high

DMA channel 2 destination address low

DMA channel 2 destination address high

DMA channel 2 transfer size

DMA module control 0

DMACTL0

DMACTL1

DMACTL2

DMACTL3

DMACTL4

DMAIV

DMA module control 1

DMA module control 2

DMA module control 3

DMA module control 4

DMA interrupt vector

Table 8-33. USCI_A0 Registers (Base Address: 05C0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI control 1

UCA0CTL1

00h

01h

06h

07h

08h

0Ah

0Ch

0Eh

10h

12h

13h

1Ch

1Dh

1Eh

USCI control 0

UCA0CTL0

UCA0BR0

USCI baud rate 0

USCI baud rate 1

UCA0BR1

USCI modulation control

USCI status

UCA0MCTL

UCA0STAT

UCA0RXBUF

UCA0TXBUF

UCA0ABCTL

UCA0IRTCTL

UCA0IRRCTL

UCA0IE

USCI receive buffer

USCI transmit buffer

USCI LIN control

USCI IrDA transmit control

USCI IrDA receive control

USCI interrupt enable

USCI interrupt flags

USCI interrupt vector word

UCA0IFG

UCA0IV

Table 8-34. USCI_B0 Registers (Base Address: 05E0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI synchronous control 1

USCI synchronous control 0

USCI synchronous bit rate 0

USCI synchronous bit rate 1

USCI synchronous status

UCB0CTL1

00h

01h

06h

07h

0Ah

UCB0CTL0

UCB0BR0

UCB0BR1

UCB0STAT

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Table 8-34. USCI_B0 Registers (Base Address: 05E0h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI synchronous receive buffer

USCI synchronous transmit buffer

USCI I2C own address

UCB0RXBUF

0Ch

0Eh

10h

12h

1Ch

1Dh

1Eh

UCB0TXBUF

UCB0I2COA

UCB0I2CSA

UCB0IE

USCI I2C slave address

USCI interrupt enable

USCI interrupt flags

UCB0IFG

USCI interrupt vector word

UCB0IV

Table 8-35. USCI_A1 Registers (Base Address: 0600h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI control 1

UCA1CTL1

00h

01h

06h

07h

08h

0Ah

0Ch

0Eh

10h

12h

13h

1Ch

1Dh

1Eh

USCI control 0

UCA1CTL0

UCA1BR0

USCI baud rate 0

USCI baud rate 1

UCA1BR1

USCI modulation control

USCI status

UCA1MCTL

UCA1STAT

UCA1RXBUF

UCA1TXBUF

UCA1ABCTL

UCA1IRTCTL

UCA1IRRCTL

UCA1IE

USCI receive buffer

USCI transmit buffer

USCI LIN control

USCI IrDA transmit control

USCI IrDA receive control

USCI interrupt enable

USCI interrupt flags

USCI interrupt vector word

UCA1IFG

UCA1IV

Table 8-36. USCI_B1 Registers (Base Address: 0620h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI synchronous control 1

USCI synchronous control 0

USCI synchronous bit rate 0

USCI synchronous bit rate 1

USCI synchronous status

UCB1CTL1

00h

01h

06h

07h

0Ah

0Ch

0Eh

10h

12h

1Ch

1Dh

1Eh

UCB1CTL0

UCB1BR0

UCB1BR1

UCB1STAT

UCB1RXBUF

UCB1TXBUF

UCB1I2COA

UCB1I2CSA

UCB1IE

USCI synchronous receive buffer

USCI synchronous transmit buffer

USCI I2C own address

USCI I2C slave address

USCI interrupt enable

USCI interrupt flags

UCB1IFG

USCI interrupt vector word

UCB1IV

Table 8-37. USCI_A2 Registers (Base Address: 0640h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI control 1

UCA2CTL1

00h

01h

06h

07h

08h

0Ah

USCI control 0

UCA2CTL0

UCA2BR0

UCA2BR1

UCA2MCTL

UCA2STAT

USCI baud rate 0

USCI baud rate 1

USCI modulation control

USCI status

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Table 8-37. USCI_A2 Registers (Base Address: 0640h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI receive buffer

UCA2RXBUF

0Ch

0Eh

10h

12h

13h

1Ch

1Dh

1Eh

USCI transmit buffer

USCI LIN control

UCA2TXBUF

UCA2ABCTL

UCA2IRTCTL

UCA2IRRCTL

UCA2IE

USCI IrDA transmit control

USCI IrDA receive control

USCI interrupt enable

USCI interrupt flags

UCA2IFG

USCI interrupt vector word

UCA2IV

Table 8-38. USCI_B2 Registers (Base Address: 0660h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI synchronous control 1

USCI synchronous control 0

USCI synchronous bit rate 0

USCI synchronous bit rate 1

USCI synchronous status

UCB2CTL1

00h

01h

06h

07h

0Ah

0Ch

0Eh

10h

12h

1Ch

1Dh

1Eh

UCB2CTL0

UCB2BR0

UCB2BR1

UCB2STAT

UCB2RXBUF

UCB2TXBUF

UCB2I2COA

UCB2I2CSA

UCB2IE

USCI synchronous receive buffer

USCI synchronous transmit buffer

USCI I2C own address

USCI I2C slave address

USCI interrupt enable

USCI interrupt flags

UCB2IFG

USCI interrupt vector word

UCB2IV

Table 8-39. USCI_A3 Registers (Base Address: 0680h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI control 1

UCA3CTL1

00h

01h

06h

07h

08h

0Ah

0Ch

0Eh

10h

12h

13h

1Ch

1Dh

1Eh

USCI control 0

UCA3CTL0

UCA3BR0

USCI baud rate 0

USCI baud rate 1

UCA3BR1

USCI modulation control

USCI status

UCA3MCTL

UCA3STAT

UCA3RXBUF

UCA3TXBUF

UCA3ABCTL

UCA3IRTCTL

UCA3IRRCTL

UCA3IE

USCI receive buffer

USCI transmit buffer

USCI LIN control

USCI IrDA transmit control

USCI IrDA receive control

USCI interrupt enable

USCI interrupt flags

USCI interrupt vector word

UCA3IFG

UCA3IV

Table 8-40. USCI_B3 Registers (Base Address: 06A0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI synchronous control 1

USCI synchronous control 0

USCI synchronous bit rate 0

USCI synchronous bit rate 1

USCI synchronous status

UCB3CTL1

00h

01h

06h

07h

0Ah

UCB3CTL0

UCB3BR0

UCB3BR1

UCB3STAT

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Table 8-40. USCI_B3 Registers (Base Address: 06A0h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI synchronous receive buffer

USCI synchronous transmit buffer

USCI I2C own address

UCB3RXBUF

0Ch

0Eh

10h

12h

1Ch

1Dh

1Eh

UCB3TXBUF

UCB3I2COA

UCB3I2CSA

UCB3IE

USCI I2C slave address

USCI interrupt enable

USCI interrupt flags

UCB3IFG

USCI interrupt vector word

UCB3IV

Table 8-41. ADC12_A Registers (Base Address: 0700h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Control register 0

ADC12CTL0

00h

02h

04h

0Ah

0Ch

0Eh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

22h

24h

26h

28h

2Ah

2Ch

2Eh

30h

32h

34h

36h

38h

3Ah

3Ch

Control register 1

ADC12CTL1

Control register 2

ADC12CTL2

Interrupt-flag register

ADC12IFG

Interrupt-enable register

Interrupt-vector-word register

ADC memory-control register 0

ADC memory-control register 1

ADC memory-control register 2

ADC memory-control register 3

ADC memory-control register 4

ADC memory-control register 5

ADC memory-control register 6

ADC memory-control register 7

ADC memory-control register 8

ADC memory-control register 9

ADC memory-control register 10

ADC memory-control register 11

ADC memory-control register 12

ADC memory-control register 13

ADC memory-control register 14

ADC memory-control register 15

Conversion memory 0

ADC12IE

ADC12IV

ADC12MCTL0

ADC12MCTL1

ADC12MCTL2

ADC12MCTL3

ADC12MCTL4

ADC12MCTL5

ADC12MCTL6

ADC12MCTL7

ADC12MCTL8

ADC12MCTL9

ADC12MCTL10

ADC12MCTL11

ADC12MCTL12

ADC12MCTL13

ADC12MCTL14

ADC12MCTL15

ADC12MEM0

ADC12MEM1

ADC12MEM2

ADC12MEM3

ADC12MEM4

ADC12MEM5

ADC12MEM6

ADC12MEM7

ADC12MEM8

ADC12MEM9

ADC12MEM10

ADC12MEM11

ADC12MEM12

ADC12MEM13

ADC12MEM14

Conversion memory 1

Conversion memory 2

Conversion memory 3

Conversion memory 4

Conversion memory 5

Conversion memory 6

Conversion memory 7

Conversion memory 8

Conversion memory 9

Conversion memory 10

Conversion memory 11

Conversion memory 12

Conversion memory 13

Conversion memory 14

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Table 8-41. ADC12_A Registers (Base Address: 0700h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

Conversion memory 15

ADC12MEM15

3Eh

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8.9.18 Input/Output Diagrams

8.9.18.1 Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger

Pad Logic

P1REN.x

DV_SS

DV_CC

0

1

P1DIR.x

0

1

Direction

0: Input

1: Output

P1OUT.x

0

1

Module X OUT

P1.0/TA0CLK/ACLK

P1.1/TA0.0

P1.2/TA0.1

P1.3/TA0.2

P1.4/TA0.3

P1.5/TA0.4

P1.6/SMCLK

P1.7

P1DS.x

0: Low drive

1: High drive

P1SEL.x

P1IN.x

EN

D

Module X IN

P1IRQ.x

P1IE.x

EN

Q

P1IFG.x

Set

P1SEL.x

P1IES.x

Interrupt

Edge

Select

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Table 8-42. Port P1 (P1.0 to P1.7) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P1.x)

x

FUNCTION

P1DIR.x

P1SEL.x

P1.0/TA0CLK/ACLK

0

P1.0 (I/O)

TA0.TA0CLK

ACLK

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P1.1/TA0.0

P1.2/TA0.1

P1.3/TA0.2

P1.4/TA0.3

P1.5/TA0.4

1

2

3

4

5

P1.1 (I/O)

TA0.CCI0A

TA0.0

I: 0; O: 1

0

1

P1.2 (I/O)

TA0.CCI1A

TA0.1

I: 0; O: 1

0

1

P1.3 (I/O)

TA0.CCI2A

TA0.2

I: 0; O: 1

0

1

P1.4 (I/O)

TA0.CCI3A

TA0.3

I: 0; O: 1

0

1

P1.5 (I/O)

TA0.CCI4A

TA0.4

I: 0; O: 1

0

1

P1.6/SMCLK

P1.7

6

7

P1.6 (I/O)

SMCLK

I: 0; O: 1

1

P1.7 (I/O)

I: 0; O: 1

62

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8.9.18.2 Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger

Pad Logic

P2REN.x

DV_SS

DV_CC

0

1

P2DIR.x

0

1

Direction

0: Input

1: Output

P2OUT.x

0

1

Module X OUT

P2.0/TA1CLK/MCLK

P2.1/TA1.0

P2.2/TA1.1

P2DS.x

0: Low drive

1: High drive

P2SEL.x

P2IN.x

P2.3/TA1.2

P2.4/RTCCLK

P2.5

P2.6/ACLK

EN

D

P2.7/ADC12CLK/DMAE0

Module X IN

P2IRQ.x

P2IE.x

EN

Q

P2IFG.x

Set

P2SEL.x

P2IES.x

Interrupt

Edge

Select

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Table 8-43. Port P2 (P2.0 to P2.7) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P2.x)

x

FUNCTION

P2DIR.x

P2SEL.x

P2.0/TA1CLK/MCLK

0

P2.0 (I/O)

TA1CLK

MCLK

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P2.1/TA1.0

P2.2/TA1.1

P2.3/TA1.2

P2.4/RTCCLK

1

2

3

4

P2.1 (I/O)

TA1.CCI0A

TA1.0

I: 0; O: 1

0

1

P2.2 (I/O)

TA1.CCI1A

TA1.1

I: 0; O: 1

0

1

P2.3 (I/O)

TA1.CCI2A

TA1.2

I: 0; O: 1

0

1

P2.4 (I/O)

RTCCLK

P2.5 (I/O)

P2.6 (I/O)

ACLK

I: 0; O: 1

1

P2.5

5

6

I: 0; O: 1

P2.6/ACLK

I: 0; O: 1

1

P2.7/ADC12CLK/DMAE0

7

P2.7 (I/O)

DMAE0

I: 0; O: 1

0

1

ADC12CLK

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8.9.18.3 Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger

Pad Logic

P3REN.x

DV_SS

DV_CC

0

1

P3DIR.x

0

1

Direction

0: Input

1: Output

P3OUT.x

0

1

Module X OUT

P3.0/UB0STE/UCA0CLK

P3.1/UCB0SIMO/UCB0SDA

P3.2/UCB0SOMI/UCB0SCL

P3.3/USC0CLK/UCA0STE

P3.4/UCA0TXD/UCA0SIMO

P3.5/UCA0RXD/UCA0SOMI

P3.6/UCB1STE/UCA1CLK

P3.7/UCB1SIMO/UCB1SDA

P3DS.x

0: Low drive

1: High drive

P3SEL.x

P3IN.x

EN

D

Module X IN

Table 8-44. Port P3 (P3.0 to P3.7) Pin Functions

CONTROL BITS/SIGNALS ⁽¹⁾

PIN NAME (P3.x)

x

FUNCTION

P3DIR.x

P3SEL.x

P3.0/UCB0STE/UCA0CLK

0

1

2

3

4

5

6

7

P3.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

UCB0STE/UCA0CLK ^{(2) (3)}

X

P3.1/UCB0SIMO/UCB0SDA

P3.2/UCB0SOMI/UCB0SCL

P3.3/UCB0CLK/UCA0STE

P3.4/UCA0TXD/UCA0SIMO

P3.5/UCA0RXD/UCA0SOMI

P3.6/UCB1STE/UCA1CLK

P3.7/UCB1SIMO/UCB1SDA

P3.1 (I/O)

I: 0; O: 1

UCB0SIMO/UCB0SDA ^{(2) (4)}

P3.2 (I/O)

X

I: 0; O: 1

UCB0SOMI/UCB0SCL ^{(2) (4)}

X

P3.3 (I/O)

I: 0; O: 1

UCB0CLK/UCA0STE ^{(2) (5)}

P3.4 (I/O)

X

I: 0; O: 1

UCA0TXD/UCA0SIMO ⁽²⁾

X

P3.5 (I/O)

I: 0; O: 1

UCA0RXD/UCA0SOMI ⁽²⁾

P3.6 (I/O)

X

I: 0; O: 1

X

UCB1STE/UCA1CLK ^{(2) (6)}

P3.7 (I/O)

I: 0; O: 1

X

UCB1SIMO/UCB1SDA ^{(2) (4)}

(1) X = Don't care

(2) The pin direction is controlled by the USCI module.

(3) If the I2C functionality is selected, the output drives only the logical 0 to V_SSlevel.

(4) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI B0 is forced to

3-wire SPI mode if 4-wire SPI mode is selected.

(5) UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI A0 is forced to

3-wire SPI mode if 4-wire SPI mode is selected.

(6) UCA1CLK function takes precedence over UCB1STE function. If the pin is required as UCA1CLK input or output, USCI B1 is forced to

3-wire SPI mode if 4-wire SPI mode is selected.

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8.9.18.4 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger

Pad Logic

P4REN.x

DV_SS

DV_CC

0

1

P4DIR.x

0

1

Direction

0: Input

1: Output

P4OUT.x

0

1

Module X OUT

P4.0/TB0.0

P4.1/TB0.1

P4.2/TB0.2

P4.3/TB0.3

P4.4/TB0.4

P4.5/TB0.5

P4DS.x

0: Low drive

1: High drive

P4SEL.x

P4IN.x

P4.6/TB0.6

P4.7/TB0CLK/SMCLK

EN

D

Module X IN

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Table 8-45. Port P4 (P4.0 to P4.7) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P4.x)

x

FUNCTION

P4DIR.x

P4SEL.x

P4.0/TB0.0

0

4.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

TB0.CCI0A and TB0.CCI0B

TB0.0 ⁽¹⁾

0

1

P4.1/TB0.1

1

2

3

4

5

6

7

4.1 (I/O)

I: 0; O: 1

TB0.CCI1A and TB0.CCI1B

TB0.1 ⁽¹⁾

0

1

P4.2/TB0.2

4.2 (I/O)

I: 0; O: 1

TB0.CCI2A and TB0.CCI2B

TB0.2 ⁽¹⁾

0

1

P4.3/TB0.3

4.3 (I/O)

I: 0; O: 1

TB0.CCI3A and TB0.CCI3B

TB0.3 ⁽¹⁾

0

1

P4.4/TB0.5

4.4 (I/O)

I: 0; O: 1

TB0.CCI4A and TB0.CCI4B

TB0.4 ⁽¹⁾

0

1

P4.5/TB0.5

4.5 (I/O)

I: 0; O: 1

TB0.CCI5A and TB0.CCI5B

TB0.5 ⁽¹⁾

0

1

P4.6/TB0.6

4.6 (I/O)

I: 0; O: 1

TB0.CCI6A and TB0.CCI6B

TB0.6 ⁽¹⁾

0

1

P4.7/TB0CLK/SMCLK

4.7 (I/O)

I: 0; O: 1

TB0CLK

0

1

SMCLK

(1) Setting TBOUTH causes all Timer_B configured outputs to be set to high impedance.

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8.9.18.5 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger

Pad Logic

To ADC12

INCHx = y

To/From

ADC12 Reference

P5REN.x

DV_SS

DV_CC

0

1

P5DIR.x

0

1

P5OUT.x

0

1

Module X OUT

P5.0/A8/VREF+/VeREF+

P5.1/A9/VREF–/VeREF–

P5DS.x

0: Low drive

1: High drive

P5SEL.x

P5IN.x

Bus

Keeper

EN

D

Module X IN

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Table 8-46. Port P5 (P5.0 and P5.1) Pin Functions

CONTROL BITS/SIGNALS ⁽¹⁾

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

P5SEL.x

REFOUT

P5.0/A8/VREF+/VeREF+

0

P5.0 (I/O) ⁽²⁾

A8/VeREF+ ⁽³⁾

A8/VREF+ ⁽⁴⁾

P5.1 (I/O) ⁽²⁾

A9/VeREF– ⁽⁵⁾

A9/VREF– ⁽⁶⁾

I: 0; O: 1

0

1

0

1

X

0

1

X

0

1

X

P5.1/A9/VREF–/VeREF–

1

I: 0; O: 1

X

(1) X = Don't care.

(2) Default condition.

(3) Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A. Channel A8, when

selected with the INCHx bits, is connected to the VREF+/VeREF+ pin.

(4) Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. The ADC12_A, VREF+ reference is available at the pin. Channel A8, when selected with the INCHx bits, is connected

to the VREF+/VeREF+ pin.

(5) Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A. Channel A9, when selected

with the INCHx bits, is connected to the VREF-/VeREF- pin.

(6) Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. The ADC12_A, VREF– reference is available at the pin. Channel A9, when selected with the INCHx bits, is connected

to the VREF-/VeREF- pin.

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8.9.18.6 Port P5, P5.2, Input/Output With Schmitt Trigger

Pad Logic

To XT2

P5REN.2

DV_SS

DV_CC

0

1

P5DIR.2

0

1

P5OUT.2

0

1

Module X OUT

P5.2/XT2IN

P5DS.2

0: Low drive

1: High drive

P5SEL.2

P5IN.2

Bus

Keeper

EN

D

Module X IN

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8.9.18.7 Port P5, P5.3, Input/Output With Schmitt Trigger

Pad Logic

To XT2

P5REN.3

DV_SS

DV_CC

0

1

P5DIR.3

0

1

P5OUT.3

0

1

Module X OUT

P5SEL.2

P5.3/XT2OUT

P5DS.3

0: Low drive

1: High drive

XT2BYPASS

P5SEL.3

P5IN.3

Bus

Keeper

EN

D

Module X IN

Table 8-47. Port P5 (P5.2 and P5.3) Pin Functions

CONTROL BITS/SIGNALS ⁽¹⁾

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

P5SEL.2

P5SEL.3

XT2BYPASS

P5.2/XT2IN

2

P5.2 (I/O)

I: 0; O: 1

0

1

0

1

X

0

1

X

0

1

XT2IN crystal mode ⁽²⁾

XT2IN bypass mode ⁽²⁾

P5.3 (I/O)

X

P5.3/XT2OUT

3

I: 0; O: 1

XT2OUT crystal mode ⁽³⁾

P5.3 (I/O) ⁽³⁾

X

(1) X = Don't care

(2) Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal

mode or bypass mode.

(3) Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as

general-purpose I/O.

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8.9.18.8 Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger

Pad Logic

P5REN.x

DV_SS

DV_CC

0

1

P5DIR.x

0

1

Direction

0: Input

1: Output

P5OUT.x

0

1

Module X OUT

P5.4/UCB1SOMI/UCB1SCL

P5.5/UCB1CLK/UCA1STE

P5.6/UCA1TXD/UCA1SIMO

P5.7/UCA1RXD/UCA1SOMI

P5DS.x

0: Low drive

1: High drive

P5SEL.x

P5IN.x

EN

D

Module X IN

Table 8-48. Port P5 (P5.4 to P5.7) Pin Functions

CONTROL BITS/SIGNALS ⁽¹⁾

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

I: 0; O: 1

X

P5SEL.x

P5.4/UCB1SOMI/UCB1SCL

4

5

6

7

P5.4 (I/O)

0

1

0

1

0

1

0

1

UCB1SOMI/UCB1SCL ^{(2) (3)}

P5.5/UCB1CLK/UCA1STE

P5.6/UCA1TXD/UCA1SIMO

P5.7/UCA1RXD/UCA1SOMI

P5.5 (I/O)

I: 0; O: 1

X

UCB1CLK/UCA1STE ^{(2) (4)}

P5.6 (I/O)

I: 0; O: 1

X

UCA1TXD/UCA1SIMO ⁽²⁾

P5.7 (I/O)

I: 0; O: 1

X

UCA1RXD/UCA1SOMI ⁽²⁾

(1) X = Don't care

(2) The pin direction is controlled by the USCI module.

(3) If the I2C functionality is selected, the output drives only the logical 0 to V_SSlevel.

(4) UCB1CLK function takes precedence over UCA1STE function. If the pin is required as UCB1CLK input or output, USCI A1 is forced to

3-wire SPI mode if 4-wire SPI mode is selected.

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8.9.18.9 Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger

Pad Logic

To ADC12

INCHx = y

P6REN.x

DV_SS

DV_CC

0

1

P6DIR.x

0

1

P6OUT.x

0

1

Module X OUT

P6.0/A0

P6.1/A1

P6.2/A2

P6.3/A3

P6.4/A4

P6.5/A5

P6.6/A6

P6.7/A7

P6DS.x

0: Low drive

1: High drive

P6SEL.x

P6IN.x

Bus

Keeper

EN

D

Module X IN

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Table 8-49. Port P6 (P6.0 to P6.7) Pin Functions

CONTROL BITS/SIGNALS ⁽¹⁾

PIN NAME (P6.x)

P6.0/A0

x

FUNCTION

P6DIR.x

P6SEL.x

INCHx

0

P6.0 (I/O)

A0 ^{(2) (3)}

I: 0; O: 1

0

X

0

X

0

X

1

X

2

X

3

X

4

X

5

X

6

X

7

X

P6.1/A1

P6.2/A2

P6.3/A3

P6.4/A4

P6.5/A5

P6.6/A6

P6.7/A7

1

2

3

4

5

6

7

P6.1 (I/O)

A1 ^{(2) (3)}

I: 0; O: 1

X

0

P6.2 (I/O)

A2 ^{(2) (3)}

I: 0; O: 1

X

0

P6.3 (I/O)

A3 ^{(2) (3)}

I: 0; O: 1

X

0

P6.4 (I/O)

A4 ^{(1) (2) (3)}

P6.5 (I/O)

A5 ^{(2) (3)}

I: 0; O: 1

X

0

I: 0; O: 1

X

I: 0; O: 1

X

0

P6.6 (I/O)

A6 ^{(2) (3)}

X

0

P6.7 (I/O)

A7 ^{(2) (3)}

I: 0; O: 1

X

(1) X = Don't care

(2) Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals.

(3) The ADC12_A channel Ax is connected internally to AV_SSif not selected via the respective INCHx bits.

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8.9.18.10 Port P7, P7.0, Input/Output With Schmitt Trigger

Pad Logic

To XT1

P7REN.0

DV_SS

DV_CC

0

1

P7DIR.0

0

1

P7OUT.0

0

1

Module X OUT

P7.0/XIN

P7DS.0

0: Low drive

1: High drive

P7SEL.0

P7IN.0

Bus

Keeper

EN

D

Module X IN

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8.9.18.11 Port P7, P7.1, Input/Output With Schmitt Trigger

Pad Logic

To XT1

P7REN.1

DV_SS

DV_CC

0

1

P7DIR.1

0

1

P7OUT.1

0

1

Module X OUT

P7SEL.0

P7.1/XOUT

P7DS.1

0: Low drive

1: High drive

XT1BYPASS

P7SEL.1

P7IN.1

Bus

Keeper

EN

D

Module X IN

Table 8-50. Port P7 (P7.0 and P7.1) Pin Functions

CONTROL BITS/SIGNALS ⁽¹⁾

PIN NAME (P7.x)

x

FUNCTION

P7DIR.x

P7SEL.0

P7SEL.1

XT1BYPASS

P7.0/XIN

0

P7.0 (I/O)

I: 0; O: 1

0

1

0

1

X

0

1

X

0

1

XIN crystal mode ⁽²⁾

XIN bypass mode ⁽²⁾

P7.1 (I/O)

X

P7.1/XOUT

1

I: 0; O: 1

XOUT crystal mode ⁽³⁾

P7.1 (I/O) ⁽³⁾

X

(1) X = Don't care

(2) Setting P7SEL.0 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P7.0 is configured for crystal

mode or bypass mode.

(3) Setting P7SEL.0 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.1 can be used as

general-purpose I/O.

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8.9.18.12 Port P7, P7.2 and P7.3, Input/Output With Schmitt Trigger

Pad Logic

P7REN.x

DV_SS

DV_CC

0

1

P7DIR.x

0

1

Direction

0: Input

1: Output

P7OUT.x

0

1

Module X OUT

P7.2/TB0OUTH/SVMOUT

P7.3/TA1.2

P7DS.x

0: Low drive

1: High drive

P7SEL.x

P7IN.x

EN

D

Module X IN

Table 8-51. Port P7 (P7.2 and P7.3) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P7.x)

x

FUNCTION

P7DIR.x

P7SEL.x

P7.2/TB0OUTH/SVMOUT

2

P7.2 (I/O)

TB0OUTH

SVMOUT

P7.3 (I/O)

TA1.CCI2B

TA1.2

I: 0; O: 1

0

1

0

1

0

1

P7.3/TA1.2

3

I: 0; O: 1

0

1

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8.9.18.13 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger

Pad Logic

To ADC12

INCHx = y

P7REN.x

DV_SS

DV_CC

0

1

P7DIR.x

0

1

P7OUT.x

0

1

Module X OUT

P7.4/A12

P7DS.x

0: Low drive

1: High drive

P7.5/A13

P7.6/A14

P7.7/A15

P7SEL.x

P7IN.x

Bus

Keeper

EN

D

Module X IN

Table 8-52. Port P7 (P7.4 to P7.7) Pin Functions

CONTROL BITS/SIGNALS ⁽¹⁾

PIN NAME (P7.x)

x

FUNCTION

P7DIR.x

P7SEL.x

INCHx

P7.4/A12

P7.5/A13

P7.6/A14

P7.7/A15

4

P7.4 (I/O)

I: 0; O: 1

0

X

0

X

12

X

A12 ^{(2) (3)}

P7.5 (I/O)

A13 ^{(2) (3)}

P7.6 (I/O)

A14 ^{(2) (3)}

P7.7 (I/O)

A15 ^{(2) (3)}

X

5

6

7

I: 0; O: 1

X

I: 0; O: 1

X

0

13

X

0

14

X

I: 0; O: 1

X

15

(1) X = Don't care

(2) Setting the P7SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals.

(3) The ADC12_A channel Ax is connected internally to AV_SSif not selected via the respective INCHx bits.

78

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8.9.18.14 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger

Pad Logic

P8REN.x

0

1

DV_SS

DV_CC

1

P8DIR.x

0

1

Direction

0: Input

1: Output

0

1

P8OUT.x

Module X OUT

P8.0/TA0.0

P8.1/TA0.1

P8.2/TA0.2

P8.3/TA0.3

P8.4/TA0.4

P8.5/TA1.0

P8.6/TA1.1

P8.7

P8DS.x

0: Low drive

1: High drive

P8SEL.x

P8IN.x

EN

D

Module X IN

Table 8-53. Port P8 (P8.0 to P8.7) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P8.x)

x

FUNCTION

P8DIR.x

P8SEL.x

P8.0/TA0.0

P8.1/TA0.1

P8.2/TA0.2

P8.3/TA0.3

P8.4/TA0.4

P8.5/TA1.0

P8.6/TA1.1

P8.7

0

P8.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

TA0.CCI0B

TA0.0

0

1

2

3

4

5

6

7

P8.1 (I/O)

TA0.CCI1B

TA0.1

I: 0; O: 1

0

1

P8.2 (I/O)

TA0.CCI2B

TA0.2

I: 0; O: 1

0

1

P8.3 (I/O)

TA0.CCI3B

TA0.3

I: 0; O: 1

0

1

P8.4 (I/O)

TA0.CCI4B

TA0.4

I: 0; O: 1

0

1

P8.5 (I/O)

TA1.CCI0B

TA1.0

I: 0; O: 1

0

1

P8.6 (I/O)

TA1.CCI1B

TA1.1

I: 0; O: 1

0

1

P8.7 (I/O)

I: 0; O: 1

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8.9.18.15 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger

Pad Logic

P9REN.x

DV_SS

DV_CC

0

1

P9DIR.x

0

1

Direction

0: Input

1: Output

P9OUT.x

0

1

Module X OUT

P9.0/UCB2STE/UCA2CLK

P9.1/UCB2SIMO/UCB2SDA

P9.2/UCB2SOMI/UCB2SCL

P9.3/UCB2CLK/UCA2STE

P9.4/UCA2TXD/UCA2SIMO

P9.5/UCA2RXD/UCA2SOMI

P9.6

P9DS.x

0: Low drive

1: High drive

P9SEL.x

P9IN.x

EN

D

P9.7

Module X IN

Table 8-54. Port P9 (P9.0 to P9.7) Pin Functions

CONTROL BITS/SIGNALS ⁽¹⁾

PIN NAME (P9.x)

x

FUNCTION

P9DIR.x

I: 0; O: 1

X

P9SEL.x

P9.0/UCB2STE/UCA2CLK

0

1

2

3

4

5

P9.0 (I/O)

0

1

0

1

0

1

0

1

0

1

0

1

0

UCB2STE/UCA2CLK ^{(2) (3)}

P9.1/UCB2SIMO/UCB2SDA

P9.2/UCB2SOMI/UCB2SCL

P9.3/UCB2CLK/UCA2STE

P9.4/UCA2TXD/UCA2SIMO

P9.5/UCA2RXD/UCA2SOMI

P9.1 (I/O)

I: 0; O: 1

X

UCB2SIMO/UCB2SDA ^{(2) (4)}

P9.2 (I/O)

I: 0; O: 1

X

UCB2SOMI/UCB2SCL ^{(2) (4)}

P9.3 (I/O)

I: 0; O: 1

X

UCB2CLK/UCA2STE ^{(2) (5)}

P9.4 (I/O)

I: 0; O: 1

X

UCA2TXD/UCA2SIMO ⁽²⁾

P9.5 (I/O)

I: 0; O: 1

X

UCA2RXD/UCA2SOMI ⁽²⁾

P9.6 (I/O)

P9.6

P9.7

6

7

I: 0; O: 1

P9.7 (I/O)

(1) X = Don't care

(2) The pin direction is controlled by the USCI module.

(3) UCA2CLK function takes precedence over UCB2STE function. If the pin is required as UCA2CLK input or output, USCI B2 is forced to

3-wire SPI mode if 4-wire SPI mode is selected.

(4) If the I2C functionality is selected, the output drives only the logical 0 to V_SSlevel.

(5) UCB2CLK function takes precedence over UCA2STE function. If the pin is required as UCB2CLK input or output, USCI A2 is forced to

3-wire SPI mode if 4-wire SPI mode is selected.

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8.9.18.16 Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger

Pad Logic

P10REN.x

DV_SS

DV_CC

0

1

P10DIR.x

0

1

Direction

0: Input

1: Output

P10OUT.x

0

1

Module X OUT

P10.0/UCB3STE/UCA3CLK

P10.1/UCB3SIMO/UCB3SDA

P10.2/UCB3SOMI/UCB3SCL

P10.3/UCB3CLK/UCA3STE

P10.4/UCA3TXD/UCA3SIMO

P10.5/UCA3RXD/UCA3SOMI

P10.6

P10DS.x

0: Low drive

1: High drive

P10SEL.x

P10IN.x

EN

D

P10.7

Module X IN

Table 8-55. Port P10 (P10.0 to P10.7) Pin Functions

CONTROL BITS/SIGNALS ⁽¹⁾

PIN NAME (P10.x)

x

FUNCTION

P10DIR.x

P10SEL.x

P10.0/UCB3STE/UCA3CLK

0

P10.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

UCB3STE/UCA3CLK ^{(2) (3)}

X

P10.1/UCB3SIMO/UCB3SDA

P10.2/UCB3SOMI/UCB3SCL

P10.3/UCB3CLK/UCA3STE

P10.4/UCA3TXD/UCA3SIMO

P10.5/UCA3RXD/UCA3SOMI

P10.6

1

2

3

4

5

6

7

P10.1 (I/O)

I: 0; O: 1

UCB3SIMO/UCB3SDA ^{(2) (4)}

P10.2 (I/O)

X

I: 0; O: 1

UCB3SOMI/UCB3SCL ^{(2) (4)}

X

P10.3 (I/O)

I: 0; O: 1

UCB3CLK/UCA3STE ^{(2) (5)}

P10.4 (I/O)

X

I: 0; O: 1

UCA3TXD/UCA3SIMO ⁽²⁾

X

P10.5 (I/O)

I: 0; O: 1

UCA3RXD/UCA3SOMI ⁽²⁾

P10.6 (I/O)

X

I: 0; O: 1

Reserved ⁽⁶⁾

X

I: 0; O: 1

x

P10.7

P10.7 (I/O)

Reserved ⁽⁶⁾

(1) X = Don't care

(2) The pin direction is controlled by the USCI module.

(3) UCA3CLK function takes precedence over UCB3STE function. If the pin is required as UCA3CLK input or output, USCI B3 is forced to

3-wire SPI mode if 4-wire SPI mode is selected.

(4) If the I2C functionality is selected, the output drives only the logical 0 to V_SSlevel.

(5) UCB3CLK function takes precedence over UCA3STE function. If the pin is required as UCB3CLK input or output, USCI A3 is forced to

3-wire SPI mode if 4-wire SPI mode is selected.

(6) The secondary function on these pins are reserved for factory test purposes. Application should keep the P10SEL.x of these ports

cleared to prevent potential conflicts with the application.

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8.9.18.17 Port P11, P11.0 to P11.2, Input/Output With Schmitt Trigger

Pad Logic

P11REN.x

0

1

DV_SS

DV_CC

1

P11DIR.x

0

1

Direction

0: Input

1: Output

P11OUT.x

0

1

Module X OUT

P11.0/ACLK

P11.1/MCLK

P11.2/SMCLK

P11DS.x

0: Low drive

1: High drive

P11SEL.x

P11IN.x

EN

D

Module X IN

Table 8-56. Port P11 (P11.0 to P11.2) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P11.x)

x

FUNCTION

P11DIR.x

P11SEL.x

P11.0/ACLK

P11.1/MCLK

P11.2/SMCLK

0

P11.0 (I/O)

ACLK

I: 0; O: 1

0

1

0

1

0

1

2

P11.1 (I/O)

MCLK

I: 0; O: 1

1

I: 0; O: 1

1

P11.2 (I/O)

SMCLK

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8.9.18.18 Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output

Pad Logic

PJREN.0

0

1

DV_SS

DV_CC

1

PJDIR.0

DVCC

0

1

PJOUT.0

0

1

From JTAG

PJ.0/TDO

PJDS.0

0: Low drive

1: High drive

From JTAG

PJIN.0

EN

D

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8.9.18.19 Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output

Pad Logic

PJREN.x

0

1

DV_SS

DV_CC

1

PJDIR.x

DVSS

0

1

PJOUT.x

0

1

From JTAG

PJ.1/TDI/TCLK

PJ.2/TMS

PJ.3/TCK

PJDS.x

0: Low drive

1: High drive

From JTAG

PJIN.x

EN

D

To JTAG

Table 8-57. Port PJ (PJ.0 to PJ.3) Pin Functions

CONTROL BITS/

SIGNALS ⁽¹⁾

PIN NAME (PJ.x)

x

FUNCTION

PJDIR.x

I: 0; O: 1

X

PJ.0/TDO

0

PJ.0 (I/O) ⁽²⁾

TDO ⁽³⁾

PJ.1/TDI/TCLK

PJ.2/TMS

1

2

3

PJ.1 (I/O) ⁽²⁾

TDI/TCLK ^{(3) (4)}

PJ.2 (I/O)⁽²⁾

TMS ^{(3) (4)}

I: 0; O: 1

X

I: 0; O: 1

X

PJ.3/TCK

PJ.3 (I/O) ⁽²⁾

TCK ^{(3) (4)}

I: 0; O: 1

X

(1) X = Don't care

(2) Default condition

(3) The pin direction is controlled by the JTAG module.

(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.

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8.10 Device Descriptors (TLV)

Table 8-58 lists the complete contents of the device descriptor tag-length-value (TLV) structure for each device

type.

Table 8-58. Device Descriptors ⁽¹⁾

DESCRIPTION

ADDRESS

01A00h

01A01h

01A02h

01A04h

01A05h

01A06h

01A07h

01A08h

01A09h

01A0Ah

01A0Eh

01A10h

01A12h

01A14h

01A15h

01A16h

01A18h

SIZE (bytes)

VALUE

06h

Info length

1

2

1

4

2

1

2

CRC length

06h

CRC value

per unit

05h

Info Block

Device ID

80h

Hardware revision

Firmware revision

Die Record Tag

Die Record length

Lot/Wafer ID

per unit

08h

0Ah

per unit

11h

Die Record

Die X position

Die Y position

Test results

ADC12 Calibration Tag

ADC12 Calibration length

ADC Gain Factor

ADC Offset

10h

per unit

ADC 1.5-V ReferenceTemp. Sensor

30°C

01A1Ah

01A1Ch

01A1Eh

01A20h

01A22h

01A24h

2

per unit

ADC 1.5-V ReferenceTemp. Sensor

85°C

ADC12 Calibration

ADC 2.0-V ReferenceTemp. Sensor

30°C

ADC 2.0-V ReferenceTemp. Sensor

85°C

ADC 2.5-V ReferenceTemp. Sensor

30°C

ADC 2.5-V ReferenceTemp. Sensor

85°C

REF Calibration Tag

REF Calibration length

REF 1.5-V Reference

REF 2.0-V Reference

REF 2.5-V Reference

01A26h

01A27h

01A28h

01A2Ah

01A2Ch

1

2

12h

06h

REF Calibration

per unit

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Table 8-58. Device Descriptors ⁽¹⁾(continued)

DESCRIPTION

ADDRESS

SIZE (bytes)

VALUE

02h

Peripheral Descriptor Tag

Peripheral Descriptor Length

Memory 1

Memory 2

Memory 3

Memory 4

Memory 5

delimiter

01A2Eh

1

2

0/1

1

2

01A2Fh

61h

08h8Ah

0Ch86h

0Eh30h

2Eh98h

NA

00h

Peripheral count

MSP430CPUXV2

SBW

21h

00h23h

00h0Fh

00h05h

00hFCh

00h1Fh

10h41h

02h30h

02h38h

01h3Ch

00h3Dh

00h44h

00h40h

01h48h

02h42h

03hA0h

05h51h

02h52h

02h53h

02h54h

02h55h

02h56h

08h5Fh

02h62h

04h61h

04h67h

0Eh68h

02h85h

04h47h

0Ch90h

04h90h

08hD1h

EEM-8

TI BSL

Package

SFR

PMM

FCTL

CRC16-straight

CRC16-bit reversed

RAMCTL

WDT_A

Peripheral Descriptor

UCS

SYS

REF

Port 1/2

Port 3/4

Port 5/6

Port 7/8

Port 9/10

Port 11/12

JTAG

TA0

TA1

TB0

RTC

MPY32

DMA-3

USCI_A/B

ADC12_A

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Table 8-58. Device Descriptors ⁽¹⁾(continued)

DESCRIPTION

TB0.CCIFG0

TB0.CCIFG1..6

WDTIFG

ADDRESS

SIZE (bytes)

VALUE

64h

65h

40h

90h

91h

D0h

60h

61h

94h

95h

46h

62h

63h

50h

92h

93h

96h

97h

51h

68h

00h

1

USCI_A0

USCI_B0

ADC12_A

TA0.CCIFG0

TA0.CCIFG1..4

USCI_A2

USCI_B2

DMA

Interrupts

TA1.CCIFG0

TA1.CCIFG1..2

P1

USCI_A1

USCI_B1

USCI_A3

USCI_B3

P2

RTC_A

delimiter

(1) NA = Not applicable.

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9 Device and Documentation Support

9.1 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

9.2 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

9.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

9.4 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

NFBGA - 1 mm max height

PLASTIC BALL GRID ARRAY

ZCA0113A

A

7.1

6.9

B

BALL A1 CORNER

7.1

6.9

1 MAX

C

SEATING PLANE

0.08 C

0.25

0.15

BALL TYP

5.5

TYP

(0.75) TYP

SYMM

M

L

K

J

(0.75) TYP

H

G

F

E

D

C

SYMM

5.5

TYP

0.35

0.25

113X Ø

B

A

0.15

0.05

C

A B

1

2

3

4

5

6

7

8

9 10 11 12

0.5 TYP

4225149/A 08/2019

NanoFree is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

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EXAMPLE BOARD LAYOUT

NFBGA - 1 mm max height

PLASTIC BALL GRID ARRAY

ZCA0113A

(0.5) TYP

1

2

3

4

5

6

7

8

9

10 11 12

A

B

C

D

E

F

113X (Ø0.25)

SYMM

G

H

J

K

L

M

SYMM

LAND PATTERN EXAMPLE

SCALE: 10X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

EXPOSED

METAL

(Ø 0.25)

METAL

(Ø 0.25)

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON- SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4225149/A 08/2019

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments

Literature number SNVA009 (www.ti.com/lit/snva009).

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EXAMPLE STENCIL DESIGN

NFBGA - 1 mm max height

PLASTIC BALL GRID ARRAY

ZCA0113A

(0.5) TYP

1

2

3

4

5

6

7

8

9

10 11 12

A

B

C

D

E

F

(R0.05)

SYMM

G

H

J

METAL TYP

113X ( 0.25)

K

L

M

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.100 mm THICK STENCIL

SCALE: 10X

4225149/A 08/2019

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party

intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,

costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s

applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	M430F5438AMZCARET
厂家：	TEXAS INSTRUMENTS
描述：	MSP430F5438A-ET Mixed-Signal Controller
文件：	总95页 (文件大小：2011K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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