MIPSZ20120D2R2 [TI]
High-Efficiency Power Solution Using DC/DC Converter With DVFS; 高效率电源解决方案使用DC / DC转换器DVFS
| 型号： | MIPSZ20120D2R2 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Efficiency Power Solution Using DC/DC Converter With DVFS |
| 文件： | 总9页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Application Report
SLVA341A–June 2009–Revised May 2010
High-Efficiency Power Solution Using DC/DC Converter
With DVFS
Andy Dykstra................................................................................. PMP - DC/DC Low-Power Converters
ABSTRACT
This reference design helps those desiring to design-in the TMS320C6742, TMS320C6746,
TMS320C6748 and OMAP-L138. This design, employing sequenced power supplies, describes a system
with an input voltage of 5 V, and uses a high-efficiency DC/DC Converters with integrated FETs and
DVFS for a small, simple system.
Sequenced power supply architectures are becoming commonplace in high-performance microprocessor
and digital signal processor (DSP) systems. To save power and increase processing speeds, processor
cores have smaller geometry cells and require lower supply voltages than the system bus voltages. Power
management in these systems requires special attention. This application note addresses these topics
and suggests solutions for output voltage sequencing.
Contents
1
2
3
4
Introduction .................................................................................................................. 2
Power Requirements ....................................................................................................... 2
Features ...................................................................................................................... 3
List of Material ............................................................................................................... 6
List of Figures
1
2
3
4
5
6
PMP4979 Reference Design Schematic.................................................................................
Optional Circuit for DVDD_A, DVDD_B, and DVDD_C................................................................
Sequencing in Start-Up Waveform .......................................................................................
Efficiency vs Output Current ..............................................................................................
Efficiency vs Output Current ..............................................................................................
Efficiency vs Output Current...............................................................................................
4
5
7
7
7
7
1
SLVA341A–June 2009–Revised May 2010
High-Efficiency Power Solution Using DC/DC Converter With DVFS
Copyright © 2009–2010, Texas Instruments Incorporated
Introduction
www.ti.com
1
Introduction
In dual voltage architectures, coordinated management of power supplies is necessary to avoid potential
problems and ensure reliable performance. Power supply designers must consider the timing and voltage
differences between core and I/O voltage supplies during power up and power down operations.
Sequencing refers to the order, timing, and differential in which the two voltage rails are powered up and
down. A system designed without proper sequencing may be at risk for two types of failures. The first of
these represents a threat to the long term reliability of the dual voltage device, while the second is more
immediate, with the possibility of damaging interface circuits in the processor or system devices such as
memory, logic or data converter ICs.
Another potential problem with improper supply sequencing is bus contention. Bus contention is a
condition when the processor and another device both attempt to control a bi-directional bus during power
up. Bus contention also may affect I/O reliability. Power supply designers must check the requirements
regarding bus contention for individual devices.
The power-on sequencing for the OMAP-L138, TMS320C6742, TMS320C6746, and TMS320C6748 are
shown in the Power Requirements table below. No specific voltage ramp rate is required for any of the
supplies as long as the 3.3-V rail never exceeds the 1.8-V rail by more than 2 V.
In order to reduce the power consumption of the processor core, Dynamic Voltage and Frequency Scaling
(DVFS) is used in the reference design. DVFS is a power management technique used while active
processing is going on in the system-on-chip (SoC) which matches the operating frequency of the
hardware to the performance requirement of the active application scenario. Whenever clock frequencies
are lowered, operating voltages are also lowered to achieve power savings. In the reference design,
TPS62353 is used which can scale its output voltage.
2
Power Requirements
The power requirements are as specify in the table.
(1) (2)
VOLTAGE
(V)
Imax
(mA)
SEQUENCING
ORDER
TIMING
DELAY
PIN NAME
RTC_CVDD
CVDD(4)
TOLERANCE
I/O
1.2
1.0 / 1.1 / 1.2
1.2
1
–25%, +10%
–9.75%, +10%
–5%, +10%
1(3)
Core
I/O
600
200
2
RVDD, PLL0_VDDA,
3
PLL1_VDDA, SATA_VDD,
USB_CVDD, USB0_VDDA12
I/O
USB0_VDDA18, USB1_VDDA18,
DDR_DVDD18, SATA_VDDR,
DVDD18
1.8
180
±5%
4
I/O
I/O
USB0_VDDA33, USB1_VDDA33
3.3
24
50 / 90(5)
±5%
±5%
5
DVDD3318_A, DVDD3318_B,
DVDD3318_C
1.8 / 3.3
4 / 5
(1)
(2)
If 1.8-V LVCMOS is used, power rails up with the 1.8-V rails. If 3.3 -V LVCMOS is used, power it up with the ANALOG33 rails
(VDDA33_USB0/1)
There is no specific required voltage ramp rate for any of the supplies LVCMOS33 (USB0_VDDA33, USB1_VDDA33) never
exceeds STATIC18 (USB0_VDDA18, USB1_VDDA18, DDR_DVDD18, SATA_VDDR, DVDD18) by more than 2 volts.
If RTC is not used/maintained on a separate supply, it can be included in the STATIC12 (fixed 1.2 V) group.
If using CVDD at fixed 1.2 V, all 1.2-V rails may be combined.
If DVDD3318_A, B, and C are powered independently, maximum power for each rail is 1/3 the above maximum power.
(3)
(4)
(5)
NanoFree is a trademark of Texas Instruments.
2
High-Efficiency Power Solution Using DC/DC Converter With DVFS
SLVA341A–June 2009–Revised May 2010
Copyright © 2009–2010, Texas Instruments Incorporated
www.ti.com
Features
3
Features
The design uses the following high-efficiency DC/DC Converter with integrated FETs .
INPUT VOLTAGE
~5V
HIGH EFFICIENCY AND
INTEGRATION
(w DVFS)
COMBINE RTC AND STATIC 1.2
Core 1.2 V at 600 mA
TPS62353
TPS62232
Static 1.2 V + VRTC at 251 mA
Static 1.8 V at 230 mA
TPS62231
Static 3.3 V at 115 mA
TPS71733 (DRV)
Here VRTC is included in the STATIC12 (fixed 1.2 V) group.
TPS62353
•
•
•
•
•
•
•
•
•
88% Efficiency at 3-MHz Operation
Output Peak Current up to 800 mA
3-MHz Fixed Frequency Operation
Best in Class Load and Line Transient
±2% PWM DC Voltage Accuracy
Efficiency Optimized Power-Save Mode
Transient Optimized Power-Save Mode
Fixed 1.2-V output eliminates need for external voltage-setting resistors
Available in a 10-Pin QFN (3 × 3 mm) 12-Pin NanoFree™ (CSP) Packaging
TPS62231 and TPS62232
•
•
•
•
•
•
3 MHz switch frequency
Up to 94% efficiency
Output Peak Current up to 500mA
Small External Output Filter Components (1 µH/ 4.7 µF)
Small 1 × 1,5 × 0,6-mm 3 SON Package
Fixed 1.8V and 1.2V output respectively eliminates need for external voltage-setting resistors
TPS71733
•
•
•
•
150-mA Low-Dropout Regulator with Enable
Low Noise: 30 mV typical (100 Hz to 100 kHz)
Excellent Load/Line Transient Response
Small SC70-5, 2-mm × 2-mm SON-6, and 1,5-mm × 1,5-mm SON-6 Packages
More information on the devices can be found from the data sheets:
•
•
•
TPS62353, http://focus.ti.com/lit/ds/symlink/tps62350.pdf
TPS71733, http://focus.ti.com/lit/ds/symlink/tps71733.pdf
TPS62231 and TPS62232, http://focus.ti.com/lit/ds/symlink/tps62230.pdf
3
SLVA341A–June 2009–Revised May 2010
High-Efficiency Power Solution Using DC/DC Converter With DVFS
Copyright © 2009–2010, Texas Instruments Incorporated
Features
www.ti.com
Figure 1. PMP4979 Reference Design Schematic
Proper sequencing is ensured in the design with the use of a enable pins. As required, Core 1.2 V at 600
mA comes first, followed by Static 1.2 V + VRTC at 251 mA, Static 1.8 V at 230 mA which in turn enable
the LDO and hence at last Static 3.3 V at 115 mA comes up.
4
High-Efficiency Power Solution Using DC/DC Converter With DVFS
SLVA341A–June 2009–Revised May 2010
Copyright © 2009–2010, Texas Instruments Incorporated
www.ti.com
Features
(1) Use three such LDOs to power up DVDDA, DVDDB, DVDDC (It can either be 1.8 V or 3.3 V)
(2) Rx = 0.499 MΩ, Ry = 1 MΩ for Vout = 1.8 V
(3) Rx = 1.8 MΩ, Ry = 1 MΩ for Vout = 3.3 V
(4) For proper sequencing of output, enable of the LDOs are fed either from 1.2-V output from 1.2-V output from
TPS62232 if DVDDX is 1.8 V or from 1.8-V output from TPS62231 if DVDDX is 3.3 V.
Figure 2. Optional Circuit for DVDD_A, DVDD_B, and DVDD_C
5
SLVA341A–June 2009–Revised May 2010
High-Efficiency Power Solution Using DC/DC Converter With DVFS
Copyright © 2009–2010, Texas Instruments Incorporated
List of Material
www.ti.com
4
List of Material
Count RefDes Value
Description
Size
603
Part Number
MFR
Area
2
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
J1
10 mF
10 mF
47 mF
22 mF
2.2 mF
4.7 mF
22 mF
2.2 F
Capacitor, Ceramic, 6.3V, X5R, 10%
Capacitor, Ceramic, 6.3V, X5R, 10%
Capacitor, Ceramic, 10V, X5R, 20%
Capacitor, Ceramic, 10V, X5R, 20%
Capacitor, Ceramic, 6.3V, X5R, 20%
Capacitor, Ceramic, 6.3V, X5R, 20%
Capacitor, Ceramic, 10V, X5R, 20%
Capacitor, Ceramic, 6.3V, X5R, 20%
Capacitor, Ceramic, 6.3V, X5R, 20%
Capacitor, Ceramic, 16V, X5R, 10%
Capacitor, Ceramic, 25V, X5R, 10%
Capacitor, Ceramic, 50V, X7R, 10%
C1608X5R0J106KT TDK
C1608X5R0J106KT TDK
C4532X5R1A476M TDK
5650
603
5650
1
2
2
2
1812
1210
402
43,360
83,600
2800
Std
Std
JDK105BJ225MV
JDK105BJ475MV
Std
Taiyo Yuden
Taiyo Yuden
Std
402
2800
1210
402
83,600
2800
JDK105BJ225MV
JDK105BJ475MV
C1608X5R1C225K
C1608X5R1E105K
C1608X7R1H103K
2510-6002UB
Taiyo Yuden
Taiyo Yuden
TDK
4.7 F
402
2800
1
1
1
1
2.2 F
603
5650
1.0 F
603
TDK
5650
0.01 F
2510-6002UB
603
TDK
5650
Connector, Male Straight 2x10 pin, 100mil
spacing, 4 Wall
0.338 × 0.788
3M
301.024
1
J2
PEC36SAAN
Header, Male 5-pin, 100mil spacing, (36-pin
strip)
0.100 inch × 5
PEC36SAAN
Sullins
60000
1
2
L1
L2
L3
R1
R2
R3
U1
1 H
Inductor, SMT, 1.6A, ±30%
Inductor, SMT, 0.7A, 230-mΩ
Inductor, SMT, 0.7A, 230-mΩ
Resistor, Chip, 1/16W, 1%
Resistor, Chip, 1/16W, 1%
Resistor, Chip, 1/16W, 1%
0.118 × 0.118
805
LPS3010-102NLC
MIPSZ20120D2R2
MIPSZ20120D2R2
Std
Coilcraft
FDK
FDK
Std
26,560
10160
10160
5650
2.2 H
2.2 H
1M
805
1
2
603
10k
603
Std
Std
5650
10k
603
Std
Std
5650
1
1
1
1
TPS62353YZG IC, 3MHz Synchronous Step Down Converter
with I2C, 800mA
CSP-12
TPS62353YZG
TI
12,000
U2
U3
U4
TPS62232DRY IC, 3MHz Ultra Small Step Down Converter, x.x QFN
V
TPS62232DRY
TPS62232DRY
TPS71728DCK
TI
TI
TI
6020
6020
18.6
TPS62231DRY IC, 3MHz Ultra Small Step Down Converter, x.x QFN
V
TPS71733DCK IC, 150mA, Low Iq, Wide Bandwidth, LDO
Linear Regulators
SC70
Notes: 1. These assemblies are ESD sensitive, ESD precautions shall be observed.
2. These assemblies must be clean and free from flux and all contaminants.
Use of no clean flux is not acceptable.
3. These assemblies must comply with workmanship standards IPC-A-610 Class 2.
4. Ref designators marked with an asterisk ('**') cannot be substituted.
All other components can be substituted with equivalent MFG's components.
6
High-Efficiency Power Solution Using DC/DC Converter With DVFS
SLVA341A–June 2009–Revised May 2010
Copyright © 2009–2010, Texas Instruments Incorporated
www.ti.com
List of Material
4.1 Test Result
The start-up waveform is shown in Figure 3, which specifies the sequencing order that is required.
Figure 3. Sequencing in Start-Up Waveform
100
90
80
70
60
50
100
V
= 2.3 V
LPFM/PWM
90
IN
80
V
= 2.7 V
70
60
50
40
30
20
IN
V
= 3.6 V
IN
V
= 4.2 V
IN
3-MHz PWM
FPFM/PWM
V
= 5 V
40
30
20
10
0
IN
MODE = GND,
= 1.2 V,
V
V
= 3.6 V
I
V
OUT
= 1.35 V
O
L = 2.2 mH MIPSZ2012 2R2 (2012 size),
= 4.7 mF
L = 1 mH
= 10 mF
C
10
0
OUT
C
O
0.1
1
10
100
1000
0.1
1
10
- Output Current - mA
100
1000
I
I
− Output Current − mA
O
O
Figure 4. Efficiency vs Output Current
Figure 5. Efficiency vs Output Current
7
SLVA341A–June 2009–Revised May 2010
High-Efficiency Power Solution Using DC/DC Converter With DVFS
Copyright © 2009–2010, Texas Instruments Incorporated
List of Material
www.ti.com
100
90
80
70
60
50
40
30
20
10
0
V
= 2.3 V
IN
V
= 2.7 V
IN
V
= 3.3 V
IN
V
= 3.6 V
IN
V
= 4.2 V
IN
V
= 5 V
IN
MODE = GND,
= 1.8 V,
V
OUT
L = 2.2 mH (MIPSA25202R2),
= 4.7 mF
C
OUT
0.1
1
I
10
- Output Current - mA
100
1000
O
Figure 6. Efficiency vs Output Current
8
High-Efficiency Power Solution Using DC/DC Converter With DVFS
SLVA341A–June 2009–Revised May 2010
Copyright © 2009–2010, Texas Instruments Incorporated
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