MM74C928N [TI]

CMOS SERIES, ASYN NEGATIVE EDGE TRIGGERED 16-BIT UP DISPLAY DRIVER COUNTER, PDIP18, PLASTIC, DIP-18;
MM74C928N
型号: MM74C928N
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

CMOS SERIES, ASYN NEGATIVE EDGE TRIGGERED 16-BIT UP DISPLAY DRIVER COUNTER, PDIP18, PLASTIC, DIP-18

驱动 光电二极管 逻辑集成电路 触发器
文件: 总8页 (文件大小:209K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
March 1988  
MM74C925, MM74C926, MM74C927, MM74C928  
4-Digit Counters with Multiplexed  
7-Segment Output Drivers  
General Description  
These CMOS counters consist of a 4-digit counter, an inter-  
nal output latch, NPN output sourcing drivers for a 7-seg-  
ment display, and an internal multiplexing circuitry with four  
multiplexing outputs. The multiplexing circuit has its own  
free-running oscillator, and requires no external clock. The  
counters advance on negative edge of clock. A high signal  
on the Reset input will reset the counter to zero, and reset  
the carry-out low. A low signal on the Latch Enable input will  
latch the number in the counters into the internal output  
latches. A high signal on Display Select input will select the  
number in the counter to be displayed; a low level signal on  
the Display Select will select the number in the output latch  
to be displayed.  
an overflow indicator which is high at 2000, and it goes back  
low only when the counter is reset. Thus, this is a 3(/2-digit  
counter.  
Features  
Y
Wide supply voltage range  
Guaranteed noise margin  
High noise immunity  
3V to 6V  
1V  
Y
Y
Y
0.45 V  
(typ.)  
40 mA  
CC  
High segment sourcing current  
@
b
e
5V  
V
CC  
1.6V, V  
CC  
Y
Internal multiplexing circuitry  
Design Considerations  
The MM74C925 is a 4-decade counter and has Latch En-  
able, Clock and Reset inputs.  
Segment resistors are desirable to minimize power dissipa-  
tion and chip heating. The DS75492 serves as a good digit  
driver when it is desired to drive bright displays. When using  
this driver with a 5V supply at room temperature, the display  
can be driven without segment resistors to full illumination.  
The user must use caution in this mode however, to prevent  
overheating of the device by using too high a supply voltage  
or by operating at high ambient temperatures.  
The MM74C926 is like the MM74C925 except that it has a  
display select and a carry-out used for cascading counters.  
The carry-out signal goes high at 6000, goes back low at  
0000.  
The MM74C927 is like the MM74C926 except the second  
most significant digit divides by 6 rather than 10. Thus, if the  
clock input frequency is 10 Hz, the display would read  
tenths of seconds and minutes (i.e., 9:59.9).  
The input protection circuitry consists of a series resistor,  
and a diode to ground. Thus input signals exceeding V  
CC  
The MM74C928 is like the MM74C926 except the most sig-  
nificant digit divides by 2 rather than 10 and the carry-out is  
will not be clamped. This input signal should not be allowed  
to exceed 15V.  
Connection Diagrams  
Dual-In-Line Package  
Dual-In-Line Package  
TL/F/5919–2  
TL/F/5919–1  
Top View  
Top View  
Order Number MM74C926,  
MM74C927 or MM74C928  
Order Number MM74C925  
C
1995 National Semiconductor Corporation  
TL/F/5919  
RRD-B30M105/Printed in U. S. A.  
Absolute Maximum Ratings (Note 1)  
If Military/Aerospace specified devices are required,  
please contact the National Semiconductor Sales  
Office/Distributors for availability and specifications.  
b a  
65 C to 150 C  
Storage Temperature Range  
Power Dissipation (P )  
§
D(MAX)  
§
vs T Graph  
Refer to P  
D
A
Operating V Range  
CC  
3V to 6V  
6.5V  
b
a
0.3V  
Voltage at Any Output Pin  
Voltage at Any Input Pin  
Operating Temperature  
GND 0.3V to V  
CC  
V
CC  
b
a
GND 0.3V to 15V  
Lead Temperature  
(Soldering, 10 seconds)  
260 C  
§
b
a
40 C to 85 C  
§
Range (T )  
A
§
s
s
a
b
DC Electrical Characteristics Min/Max limits apply at 40 C  
T
j
85 C, unless otherwise noted  
§
§
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max Units  
CMOS TO CMOS  
e
e
e
V
V
V
Logical ‘‘1’’ Input Voltage  
Logical ‘‘0’’ Input Voltage  
V
CC  
V
CC  
V
CC  
5V  
3.5  
V
IN(1)  
5V  
1.5  
V
IN(0)  
e b  
10 mA  
Logical ‘‘1’’ Output Voltage  
(Carry-Out and Digit Output  
Only)  
5V, I  
OUT(1)  
O
4.5  
V
e
e
e
10 mA  
V
Logical ‘‘0’’ Output Voltage  
Logical ‘‘1’’ Input Current  
Logical ‘‘0’’ Input Current  
Supply Current  
V
V
V
5V, I  
0.5  
1
V
OUT(0)  
CC  
CC  
CC  
O
e
I
I
I
5V, V  
5V, V  
15V  
0V  
0.005  
mA  
mA  
IN(1)  
IN  
IN  
e
e
e
b
b
1
0.005  
20  
IN(0)  
CC  
V
V
5V, Outputs Open Circuit,  
0V or 5V  
CC  
1000  
0.8  
mA  
e
IN  
CMOS/LPTTL INTERFACE  
e
e
e
b
V
V
V
Logical ‘‘1’’ Input Voltage  
Logical ‘‘0’’ Input Voltage  
V
CC  
V
CC  
V
CC  
4.75V  
4.75V  
4.75V,  
V
CC  
2
V
V
IN(1)  
IN(0)  
Logical ‘‘1’’ Output Voltage  
(Carry-Out and Digit  
Output Only)  
OUT(1)  
e b  
I
O
360 mA  
2.4  
V
V
e
e
4.75V, I  
O
V
Logical ‘‘0’’ Output Voltage  
V
CC  
360 mA  
0.4  
OUT(0)  
OUTPUT DRIVE  
Output Voltage (Segment  
e b  
e b  
e
e
e
T
j
b
b
1.6  
b
2
b
b
b
V
OUT  
I
65 mA, V  
40 mA, V  
5V, T  
25 C  
V
2
V
V
V
1.3  
1.2  
1.4  
V
V
V
§
100 C  
OUT  
OUT  
CC  
j
CC  
CC  
CC  
CC  
e
e
Sourcing Output)  
V
§
CC  
I
5V  
CC  
Ð
T
j
150 C  
V
§
CC  
e b  
e b  
e
e
e
T
j
R
Output Resistance (Segment  
Sourcing Output)  
I
I
65 mA, V  
40 mA, V  
5V, T  
25 C  
20  
30  
35  
32  
40  
50  
X
X
X
§
100 C  
ON  
OUT  
CC  
j
e
e
§
§
5V  
OUT  
CC  
Ð
T
j
150 C  
Output Resistance (Segment  
0.6  
0.8 %/ C  
§
Output) Temperature Coefficient  
e
e
e
e
e
I
Output Source Current  
(Digit Output)  
V
V
V
4.75V, V  
1.75V, T  
150 C  
§
SOURCE  
SOURCE  
SINK  
CC  
CC  
CC  
OUT  
j
b
b
2
1
mA  
mA  
mA  
e
e
j
I
I
Output Source Current  
(Carry-Out)  
5V, V  
0V, T  
25 C  
§
OUT  
b
b
3.3  
1.75  
e
e
Output Sink Current  
(All Outputs)  
5V, V  
V
, T  
CC  
25 C  
§
OUT  
j
1.75  
3.6  
i
Thermal Resistance  
MM74C925  
(Note 4)  
75  
70  
100  
90  
C/W  
C/W  
§
§
jA  
MM74C926, MM74C927, MM74C928  
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’  
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device  
operation.  
Note 2: Capacitance is guaranteed by periodic testing.  
Note 3: C determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note,  
PD  
AN-90.  
Note 4: i measured in free-air with device soldered into printed circuit board.  
jA  
2
e
e
50 pF, unless otherwise noted  
AC Electrical Characteristics* T  
25 C, C  
§
A
L
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
e
Square Wave Clock  
e
e
f
Maximum Clock Frequency  
V
5V,  
T
T
25 C  
§
100 C  
2
4
3
MHz  
MHz  
MAX  
CC  
j
1.5  
§
j
e
e
t , t  
r
Maximum Clock Rise or Fall Time  
Reset Pulse Width  
V
CC  
V
CC  
5V  
5V  
15  
ms  
f
e
e
t
T
T
25 C  
§
100 C  
250  
320  
100  
125  
ns  
ns  
WR  
j
§
j
e
e
e
e
e
e
e
t
t
t
t
f
Latch Enable Pulse Width  
V
V
V
V
V
5V  
5V  
5V  
5V  
5V  
T
T
25 C  
§
100 C  
250  
320  
100  
125  
ns  
ns  
WLE  
CC  
CC  
CC  
CC  
CC  
j
§
j
e
e
Clock to Latch Enable Set-Up Time  
Latch Enable to Reset Wait Time  
Reset to Latch Enable Set-Up Time  
T
T
25 C  
§
100 C  
2500  
3200  
1250  
1600  
ns  
ns  
SET(CK, LE)  
LR  
j
§
j
e
e
b
b
T
T
25 C  
§
100 C  
0
0
100  
100  
ns  
ns  
j
§
j
e
e
T
T
25 C  
§
100 C  
320  
400  
160  
ns  
ns  
SET(R, LE)  
MUX  
j
200  
1000  
5
§
j
Multiplexing Output Frequency  
Input Capacitance  
Hz  
pF  
C
Any Input (Note 2)  
IN  
*AC Parameters are guaranteed by DC correlated testing.  
Functional Description  
Reset  
@
V
OUT  
e
Ð Asynchronous, active high  
Segment Output Ð Current sourcing with 40 mA  
b
V
CC  
1.6V (typ.) Also, sink capability  
2 LTTL loads  
Display Select Ð High, displays output of counter  
Low, displays output of latch  
e
@
e
2 LTTL  
Digit Output  
Carry-Out  
Ð Current sourcing with 1 mA  
1.75V. Also, sink capability  
loads  
V
OUT  
Latch Enable  
Ð High, flow through condition  
Low, latch condition  
e
Clock  
Ð Negative edge sensitive  
Ð 2 LTTL loads. See carry-out waveforms.  
Typical Performance Characteristics  
Typical Average Segment  
Current vs Segment  
Typical Segment Current  
Maximum Power Dissipation  
TL/F/5919–3  
e
Note: V  
Voltage across digit driver  
D
3
Logic and Block Diagrams  
MM74C925  
MM74C926  
MM74C927  
MM74C928  
TL/F/5919–4  
TL/F/5919–5  
TL/F/5919–6  
TL/F/5919–7  
4
Logic and Block Diagrams (Continued)  
Segment Output Driver  
Input Protection  
TL/F/5919–9  
TL/F/5919–8  
Common Cathode LED Display  
Segment Identification  
TL/F/591910  
TL/F/591911  
Switching Time Waveforms  
Input Waveforms  
Multiplexing Output Waveforms  
TL/F/591912  
TL/F/591913  
e
T
1/f  
MUX  
5
Switching Time Waveforms (Continued)  
Carry-Out Waveforms  
TL/F/591914  
Physical Dimensions inches (millimeters)  
Ceramic Dual-In-Line Package (J)  
Order Number MM74C925J  
NS Package Number J16A  
6
Physical Dimensions inches (millimeters) (Continued)  
Ceramic Dual-In-Line Package (J)  
Order Number MM74C926J, MM74C927J or MM74C928J  
NS Package Number J18A  
Molded Dual-In-Line Package (N)  
Order Number MM74C925N  
NS Package Number N16E  
7
Physical Dimensions inches (millimeters) (Continued)  
Molded Dual-In-Line Package (N)  
Order Number MM74C926N, MM74C927N or MM74C928N  
NS Package Number N18A  
LIFE SUPPORT POLICY  
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or  
systems which, (a) are intended for surgical implant  
into the body, or (b) support or sustain life, and whose  
failure to perform, when properly used in accordance  
with instructions for use provided in the labeling, can  
be reasonably expected to result in a significant injury  
to the user.  
2. A critical component is any component of a life  
support device or system whose failure to perform can  
be reasonably expected to cause the failure of the life  
support device or system, or to affect its safety or  
effectiveness.  
National Semiconductor  
Corporation  
National Semiconductor  
Europe  
National Semiconductor  
Hong Kong Ltd.  
National Semiconductor  
Japan Ltd.  
a
1111 West Bardin Road  
Arlington, TX 76017  
Tel: 1(800) 272-9959  
Fax: 1(800) 737-7018  
Fax:  
(
49) 0-180-530 85 86  
@
13th Floor, Straight Block,  
Ocean Centre, 5 Canton Rd.  
Tsimshatsui, Kowloon  
Hong Kong  
Tel: (852) 2737-1600  
Fax: (852) 2736-9960  
Tel: 81-043-299-2309  
Fax: 81-043-299-2408  
Email: cnjwge tevm2.nsc.com  
a
a
a
a
Deutsch Tel:  
English Tel:  
Fran3ais Tel:  
Italiano Tel:  
(
(
(
(
49) 0-180-530 85 85  
49) 0-180-532 78 32  
49) 0-180-532 93 58  
49) 0-180-534 16 80  
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.  

相关型号:

MM74C929D

IC,SYNC SRAM,1KX1,CMOS,DIP,16PIN,CERAMIC
TI

MM74C929J

IC,SYNC SRAM,1KX1,CMOS,DIP,16PIN,CERAMIC
TI

MM74C929J-3/A+

IC,SYNC SRAM,1KX1,CMOS,DIP,16PIN,CERAMIC
TI

MM74C929N3

IC,SYNC SRAM,1KX1,CMOS,DIP,16PIN,PLASTIC
TI

MM74C93

4-Bit Decade Counter 4-Bit Binary Counter
FAIRCHILD

MM74C93

4-Bit Decade, Binary Counter
NSC

MM74C930D/A+

IC,SYNC SRAM,1KX1,CMOS,DIP,18PIN,CERAMIC
TI

MM74C930D3

IC,SYNC SRAM,1KX1,CMOS,DIP,18PIN,CERAMIC
TI

MM74C930J

IC,SYNC SRAM,1KX1,CMOS,DIP,18PIN,CERAMIC
TI

MM74C930J-3/A+

IC,SYNC SRAM,1KX1,CMOS,DIP,18PIN,CERAMIC
TI

MM74C930J/A+

IC,SYNC SRAM,1KX1,CMOS,DIP,18PIN,CERAMIC
TI

MM74C930J3

IC,SYNC SRAM,1KX1,CMOS,DIP,18PIN,CERAMIC
TI