MSC1202Y2RHHR [TI]
Precision Analog-to-Digital Converter (ADC) and Current-Output Digital Converter (DAC);
| 型号： | MSC1202Y2RHHR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Precision Analog-to-Digital Converter (ADC) and Current-Output Digital Converter (DAC) 时钟 微控制器 外围集成电路 |
| 文件： | 总92页 (文件大小：1417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SBAS317E − APRIL 2004 − REVISED MAY 2006
ꢀꢁ ꢂ ꢃꢄ ꢅꢄ ꢆꢇ ꢈ ꢇ ꢉꢊ ꢆꢋꢌ ꢍ ꢆꢌ ꢎ ꢄꢋ ꢄꢍ ꢉꢊ ꢏꢆ ꢇꢐꢂ ꢁ ꢍꢂ ꢁ ꢑ ꢈꢎ ꢏꢒ
ꢉ ꢇꢓ ꢏ ꢔ ꢁꢁ ꢂ ꢇꢍ ꢌ ꢕꢔ ꢍ ꢖꢔꢍ ꢎ ꢄꢋꢄ ꢍ ꢉꢊ ꢌ ꢍ ꢆꢌ ꢈꢇ ꢉꢊ ꢆꢋ ꢏꢆ ꢇꢐꢂ ꢁ ꢍꢂ ꢁ ꢑ ꢎꢈ ꢏꢒ
ꢗ ꢄꢍ ꢘ ꢙ ꢚꢛ ꢜ ꢝꢄ ꢃ ꢁ ꢆꢃꢆ ꢇꢍ ꢁꢆ ꢊꢊ ꢂ ꢁ ꢉꢇ ꢓ ꢞꢊ ꢉꢅ ꢘ ꢝ ꢂꢟ ꢆꢁ ꢠ
Peripheral Features
FEATURES
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
16 Digital I/O Pins
ANALOG FEATURES
Additional 32-Bit Accumulator
Two 16-Bit Timer/Counters
System Timers
D
MSC1200 and MSC1201:
− 24 Bits No Missing Codes
− 22 Bits Effective Resolution At 10Hz
− Low Noise: 75nV
Programmable Watchdog Timer
Full-Duplex USART
D
MSC1202:
− 16 Bits No Missing Codes
− 16 Bits Effective Resolution At 200Hz
− Noise: 600nV
Basic SPI
2
Basic I C
Power Management Control
D
D
D
D
D
D
D
D
D
D
D
PGA From 1 to 128
Precision On-Chip Voltage Reference
8 Diff/Single-Ended Channels (MSC1200)
6 Diff/Single-Ended Channels (MSC1201/02)
On-Chip Offset/Gain Calibration
Offset Drift: 0.1ppm/°C
Gain Drift: 0.5ppm/°C
On-Chip Temperature Sensor
Selectable Buffer Input
Signal-Source Open-Circuit Detect
8-Bit Current DAC
Internal Clock Divider
Idle Mode Current < 200mA
Stop Mode Current < 100nA
Digital Brownout Reset
Analog Low-Voltage Detect
20 Interrupt Sources
GENERAL FEATURES
D
D
Each Device Has Unique Serial Number
Packages:
− TQFP-48 (MSC1200)
− QFN-36 (MSC1201/02)
DIGITAL FEATURES
Microcontroller Core
D
D
D
Low Power: 3mW at 3.0V, 1MHz
D
8051-Compatible
High-Speed Core:
− 4 Clocks per Instruction Cycle
Industrial Temperature Range:
−40°C to +125°C
Power Supply: 2.7V to 5.25V
D
D
D
D
D
D
DC to 33MHz
On-Chip Oscillator
PLL with 32kHz Capability
Single Instruction 121ns
Dual Data Pointer
APPLICATIONS
D
D
D
D
D
D
D
D
D
D
D
Industrial Process Control
Instrumentation
Memory
Liquid/Gas Chromatography
Blood Analysis
D
D
D
D
D
D
D
4kB or 8kB of Flash Memory
Flash Memory Partitioning
Endurance 1M Erase/Write Cycles,
100-Year Data Retention
256 Bytes Data SRAM
In-System Serially Programmable
Flash Memory Security
Smart Transmitters
Portable Instruments
Weigh Scales
Pressure Transducers
Intelligent Sensors
Portable Applications
DAS Systems
1kB Boot ROM
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
ꢀꢣ ꢕ ꢎꢤ ꢏ ꢥꢦ ꢕꢧ ꢎ ꢈꢥꢈ ꢄꢇ ꢨꢆ ꢁ ꢟꢉ ꢍꢄꢆꢇ ꢄꢅ ꢃꢔ ꢁ ꢁ ꢂꢇꢍ ꢉꢅ ꢆꢨ ꢖꢔꢩ ꢊꢄꢃ ꢉꢍꢄ ꢆꢇ ꢓꢉ ꢍꢂꢪ ꢀꢁ ꢆꢓꢔ ꢃꢍꢅ
ꢃ ꢆꢇ ꢨꢆꢁ ꢟ ꢍꢆ ꢅ ꢖꢂ ꢃ ꢄ ꢨꢄ ꢃ ꢉ ꢍꢄ ꢆꢇꢅ ꢖ ꢂꢁ ꢍꢘꢂ ꢍꢂ ꢁ ꢟꢅ ꢆꢨ ꢥꢂꢫ ꢉꢅ ꢦꢇꢅ ꢍꢁ ꢔꢟ ꢂꢇꢍ ꢅ ꢅꢍ ꢉꢇꢓ ꢉꢁ ꢓ ꢗ ꢉꢁ ꢁ ꢉ ꢇꢍꢠꢪ
ꢀꢁ ꢆ ꢓꢔꢃ ꢍ ꢄꢆ ꢇ ꢖꢁ ꢆ ꢃ ꢂ ꢅ ꢅ ꢄꢇ ꢋ ꢓꢆ ꢂ ꢅ ꢇꢆꢍ ꢇꢂ ꢃꢂ ꢅꢅ ꢉꢁ ꢄꢊ ꢠ ꢄꢇꢃ ꢊꢔꢓ ꢂ ꢍꢂ ꢅꢍꢄ ꢇꢋ ꢆꢨ ꢉꢊ ꢊ ꢖꢉ ꢁ ꢉꢟ ꢂꢍꢂ ꢁ ꢅꢪ
Copyright 2004−2006, Texas Instruments Incorporated
www.ti.com
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SBAS317E − APRIL 2004 − REVISED MAY 2006
(1)
PACKAGE/ORDERING INFORMATION
FLASH MEMORY
(BYTES)
ADC RESOLUTION
(BITS)
PACKAGE
MARKING
PRODUCT
MSC1200Y2
MSC1200Y3
MSC1201Y2
MSC1201Y3
MSC1202Y2
MSC1202Y3
4k
8k
4k
8k
4k
8k
24
24
24
24
16
16
MSC1200Y2
MSC1200Y3
MSC1201Y2
MSC1201Y3
MSC1202Y2
MSC1202Y3
(1)
For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet, or refer to our
web site at www.ti.com.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handledwith appropriate precautions. Failure to observe
MSC120x FAMILY FEATURES
(1)
FEATURES
(2)
MSC120xY2
(2)
MSC120xY3
proper handling and installation procedures can cause damage.
Flash Program Memory (Bytes)
Flash Data Memory (Bytes)
Up to 4k
Up to 2k
256
Up to 8k
Up to 4k
256
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
Internal Scratchpad RAM (Bytes)
(1)
(2)
All peripheral features are the same on all devices; the flash memory size
is the only difference.
The last digit of the part number (N) represents the onboard flash size =
N
(2 )kBytes.
(1)
ABSOLUTE MAXIMUM RATINGS
MSC120x
UNITS
Analog Inputs
Momentary
100
10
mA
mA
V
Input current
Continuous
Input voltage
AGND − 0.3 to AV + 0.3
DD
Power Supply
DV
to DGND
to AGND
−0.3 to +6
−0.3 to +6
−0.3 to +0.3
V
V
DD
DD
AV
AGND to DGND
V
VREF to AGND
−0.3 to AV
DD
+ 0.3
+ 0.3
V
Digital input voltage to DGND
Digital output voltage to DGND
−0.3 to DV
V
DD
DD
−0.3 to DV
+ 0.3
V
Maximum junction temperature (T Max)
J
+150
°C
°C
°C
W
Operating temperature range
Storage temperature range
Package power dissipation
Output current, all pins
−40 to +125
−65 to +150
(T Max − T
)/q
J
AMBIENT JA
200
mA
s
Output pin short-circuit
10
High K (2s 2p)
Low K (1s)
21.9
103.7
21.9
°C/W
°C/W
°C/W
Junction to ambient (q
)
JA
Thermal resistance
Junction to case (q
)
JC
Digital Outputs
Output current
Continuous
100
100
300
mA
mA
mA
I/O source/sink current
Power pin maximum
(1)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for
extended periods may affect device reliability.
2
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www.ti.com
SBAS317E − APRIL 2004 − REVISED MAY 2006
ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications from T
to T
, DV
= +2.7V to +5.25V, f
= 15.625kHz, PGA = 1, Buffer ON, f
= 10Hz, ADC Bipolar Mode, and
MIN
MAX
DD
MOD
DATA
V
REF
≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted.
MSC120x
TYP
PARAMETER
CONDITION
MIN
MAX
UNITS
Analog Input (AIN0-AIN5, AINCOM)
Buffer OFF
Buffer ON
AGND − 0.1
AV + 0.1
V
V
DD
Analog Input Range
AGND + 50mV
AV − 1.5
DD
Full-Scale Input Voltage Range
Differential Input Impedance
Input Current
(In+) − (In−), Bipolar Mode
V /PGA
REF
V
(1)
Buffer OFF
7/PGA
MΩ
nA
Buffer ON
0.5
Fast Settling Filter
2
−3dB
0.469 • f
DATA
Sinc Filter
−3dB
0.318 • f
Bandwidth
DATA
DATA
3
Sinc Filter
−3dB
0.262 • f
Programmable Gain Amplifier
Input Capacitance
User-Selectable Gain Range
Buffer ON
1
128
7
0.5
2
pF
pA
µA
Input Leakage Current
Multiplexer Channel OFF, T = +25°C
Burnout Current Sources
ADC Offset DAC
Buffer ON
Offset DAC Range
V /(2 •PGA)
REF
V
Offset DAC Resolution
Offset DAC Full-Scale Gain Error
Offset DAC Full-Scale Gain Error Drift
System Performance
8
Bits
1.0
0.6
% of Range
ppm/°C
MSC1200, MSC1201
MSC1202
24
16
Bits
Bits
Bits
Bits
Resolution
MSC1200, MSC1201
MSC1202
22
16
ENOB
Output Noise
See Typical Characteristics
3
MSC1201, Sinc Filter, Decimation > 360
24
16
Bits
Bits
No Missing Codes
3
MSC1202, Sinc Filter
Integral Nonlinearity
Offset Error
End Point Fit, Differential Input
After Calibration
0.0004
1.5
0.0015
% of FSR
ppm of FS
ppm of FS/°C
%
(2)
Offset Drift
Before Calibration
After Calibration
0.1
(3)
Gain Error
0.005
0.5
(2)
Gain Error Drift
Before Calibration
ppm/°C
% of FS
% of FS
dB
System Gain Calibration Range
System Offset Calibration Range
80
120
50
−50
At DC, V = 0V
120
130
120
120
100
100
100
IN
f
f
f
f
f
= 60Hz, f
= 50Hz, f
= 60Hz, f
= 50Hz, f
= 60Hz, f
= 10Hz
= 50Hz
= 60Hz
= 50Hz
= 60Hz
dB
CM
CM
CM
CM
CM
DATA
DATA
DATA
DATA
DATA
Common-Mode Rejection
Normal-Mode Rejection
dB
dB
dB
dB
(4)
Power-Supply Rejection
(1)
At DC, dB = −20log(∆V /∆V
OUT
)
DD
, V = 0V
IN
dB
The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64).
Calibration can minimize these errors.
The gain self-calibration cannot have a REF IN+ of more than AV −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.
(2)
(3)
(4)
DD
∆V
OUT
is change in digital result.
3
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www.ti.com
SBAS317E − APRIL 2004 − REVISED MAY 2006
ELECTRICAL CHARACTERISTICS: AVDD = 5V (continued)
All specifications from T
to T
, DV
= +2.7V to +5.25V, f
= 15.625kHz, PGA = 1, Buffer ON, f = 10Hz, ADC Bipolar Mode, and
DATA
MIN
MAX
DD
MOD
V
REF
≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted.
MSC120x
TYP
PARAMETER
CONDITION
MIN
MAX
UNITS
Voltage Reference Input
(3)
DD
Reference Input Range
REF IN+, REF IN−
≡ (REFIN+) − (REFIN−)
AGND
0.1
AV
V
V
ADC V
REF
V
REF
2.5
115
1
AV
DD
V
REF
Common-Mode Rejection
At DC
dB
µA
Input Current
V
REF
= 2.5V, PGA = 1
On-Chip Voltage Reference
VREFH = 1, T = +25°C
2.49
1.23
2.5
1.25
8
2.51
1.27
V
V
Output Voltage
VREFH = 0
Short-Circuit Current Source
Short-Circuit Current Sink
Short-Circuit Duration
mA
µA
65
Sink or Source
Indefinite
0.4
Startup Time from Power ON
Temperature Sensor
C
= 0.1µF
ms
REFOUT
Temperature Sensor Voltage
T = +25°C
115
375
345
mV
MSC1200
µV/°C
µV/°C
Temperature Sensor Coefficient
MSC1201, MSC1202
IDAC Output Characteristics
IDAC Resolution
8
1
Bits
mA
Full-Scale Output Current
IDAC = 0FFh
IDAC = 00h
Maximum Short-Circuit Current Duration
Compliance Voltage
Indefinite
AV − 1.5
DD
V
IDAC Zero Code Current
IDAC INL
0
µA
1.3
LSB
Analog Power-Supply Requirements
Analog Power-Supply Voltage
AV
DD
4.75
5.0
< 1
5.25
V
BOR OFF, External Clock Mode, Analog OFF,
ALVD OFF, PDADC = PDIDAC = 1
Analog Current
nA
PGA = 1, Buffer OFF
PGA = 128, Buffer OFF
PGA = 1, Buffer ON
PGA = 128, Buffer ON
170
430
230
770
µA
µA
µA
µA
ADC Current
Analog
Power-Supply
Current
(I
)
ADC
V
Supply Current
)
REF
ADC ON
360
230
µA
µA
(I
VREF
I
Supply Current
)
DAC
IDAC = 00h
(I
IDAC
(1)
The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64).
Calibration can minimize these errors.
(2)
(3)
(4)
The gain self-calibration cannot have a REF IN+ of more than AV −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.
DD
∆V
OUT
is change in digital result.
4
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www.ti.com
SBAS317E − APRIL 2004 − REVISED MAY 2006
ELECTRICAL CHARACTERISTICS: AVDD = 3V
All specifications from T
to T
, DV
= +2.7V to +5.25V,
f
= 15.625kHz, PGA = 1, Buffer ON, f
= 10Hz, ADC Bipolar Mode, and
DATA
MIN
MAX
DD
MOD
V
REF
≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted.
MSC120x
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
Analog Input (AIN0-AIN5, AINCOM)
Buffer OFF
Buffer ON
AGND − 0.1
AV + 0.1
V
V
DD
Analog Input Range
AGND + 50mV
AV − 1.5
DD
Full-Scale Input Voltage Range
Differential Input Impedance
Input Current
(In+) − (In−), Bipolar Mode
V /PGA
REF
V
(1)
Buffer OFF
7/PGA
MΩ
nA
Buffer ON
0.5
Fast Settling Filter
2
−3dB
0.469 • f
DATA
Sinc Filter
−3dB
0.318 • f
Bandwidth
DATA
DATA
3
Sinc Filter
−3dB
0.262 • f
Programmable Gain Amplifier
Input Capacitance
User-Selectable Gain Range
Buffer ON
1
128
7
0.5
2
pF
pA
µA
Input Leakage Current
Multiplexer Channel Off, T = +25°C
Buffer ON
Burnout Current Sources
ADC Offset DAC
Offset DAC Range
V /(2•PGA)
REF
V
Offset DAC Resolution
Offset DAC Full-Scale Gain Error
Offset DAC Full-Scale Gain Error Drift
System Performance
8
Bits
1.5
% of Range
ppm/°C
0.6
MSC1200, MSC1201
MSC1202
24
16
Bits
Bits
Bits
Bits
Resolution
MSC1200, MSC1201
MSC1202
22
16
ENOB
Output Noise
See Typical Characteristics
3
MSC1200, MSC1201, Sinc Filter,
Decimation > 360
24
16
Bits
No Missing Codes
3
MSC1202, Sinc Filter
Bits
% of FSR
ppm of FS
ppm of FS/°C
%
Integral Nonlinearity
Offset Error
End Point Fit, Differential Input
After Calibration
0.0004
1.3
0.0015
(2)
Offset Drift
Before Calibration
After Calibration
0.1
(3)
Gain Error
0.005
0.5
(2)
Gain Error Drift
Before Calibration
ppm/°C
% of FS
% of FS
dB
System Gain Calibration Range
System Offset Calibration Range
80
120
50
−50
At DC, V = 0V
130
130
120
120
100
100
88
IN
f
f
f
f
f
= 60Hz, f
= 50Hz, f
= 60Hz, f
= 10Hz
= 50Hz
= 60Hz
= 50Hz
= 60Hz
dB
CM
CM
CM
SIG
SIG
DATA
DATA
DATA
Common-Mode Rejection
Normal-Mode Rejection
dB
dB
= 50Hz, f
= 60Hz, f
dB
DATA
dB
DATA
(4)
Power-Supply Rejection
(1)
At DC, dB = −20log(∆V
/∆V
OUT
)
DD
, V = 0V
IN
dB
The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64).
Calibration can minimize these errors.
(2)
(3)
(4)
The gain self-calibration cannot have a REF IN+ of more than AV −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.
DD
∆V
OUT
is change in digital result.
5
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www.ti.com
SBAS317E − APRIL 2004 − REVISED MAY 2006
ELECTRICAL CHARACTERISTICS: AVDD = 3V (continued)
All specifications from T
to T
, DV
= +2.7V to +5.25V,
f
= 15.625kHz, PGA = 1, Buffer ON, f = 10Hz, ADC Bipolar Mode, and
DATA
MIN
MAX
DD
MOD
V
REF
≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted.
MSC120x
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
Voltage Reference Input
(3)
DD
Reference Input Range
REF IN+, REF IN−
≡ (REFIN+) − (REFIN−)
AGND
0.1
AV
V
V
ADC V
REF
V
REF
1.25
110
0.5
AV
DD
V
REF
Common-Mode Rejection
At DC
dB
µA
Input Current
V
REF
= 1.25V, PGA = 1
On-Chip Voltage Reference
Output Voltage
VREFH = 0, T = +25°C
1.23
1.25
2.9
1.27
V
Short-Circuit Current Source
Short-Circuit Current Sink
Short-Circuit Duration
Startup Time from Power ON
Temperature Sensor
Temperature Sensor Voltage
mA
µA
60
Sink or Source
Indefinite
0.2
C
= 0.1µF
ms
REFOUT
T = +25°C
115
375
345
mV
MSC1200
µV/°C
µV/°C
Temperature Sensor Coefficient
MSC1201, MSC1202
IDAC Output Characteristics
IDAC Resolution
8
1
Bits
mA
Full-Scale Output Source Current
Maximum Short-Circuit Current Duration
Compliance Voltage
Indefinite
AV − 1.5
DD
V
IDAC Zero Code Current
IDAC INL
0
µA
1.5
LSB
Analog Power-Supply Requirements
Analog Power-Supply Voltage
AV
DD
2.7
3.3
< 1
3.6
V
BOR OFF, External Clock Mode, Analog OFF,
ALVD OFF, PDADC = PDIDAC = 1
Analog Current
nA
PGA = 1, Buffer OFF
PGA = 128, Buffer OFF
PGA = 1, Buffer ON
PGA = 128, Buffer ON
150
380
200
610
µA
µA
µA
µA
ADC Current
Analog
Power-Supply
Current
(I
)
ADC
VREF Supply Current
(I
ADC ON
330
220
µA
µA
)
VREF
IDAC Supply Current
(I
IDAC = 00h
)
IDAC
(1)
The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64).
Calibration can minimize these errors.
(2)
(3)
(4)
The gain self-calibration cannot have a REF IN+ of more than AV −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.
DD
∆V
OUT
is change in digital result.
6
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www.ti.com
SBAS317E − APRIL 2004 − REVISED MAY 2006
DIGITAL CHARACTERISTICS: DVDD = 2.7V to 5.25V
All specifications from T
otherwise specified.
to T
, FMCON = 10h, all digital outputs high, and PDCON = 00h (all peripherals ON) or PDCON = FFh (all peripherals OFF), unless
MIN
MAX
MSC120x
MIN
TYP
MAX
PARAMETER
CONDITIONS
UNITS
Digital Power-Supply Requirements
DV
2.7
3.3
0.7
0.6
4.7
4.3
3.6
V
DD
Normal Mode, f
Normal Mode, f
Normal Mode, f
Normal Mode, f
= 1MHz, All Peripherals ON
= 1MHz, All Peripherals OFF
= 8MHz, All Peripherals ON
= 8MHz, All Peripherals OFF
mA
mA
mA
mA
OSC
OSC
OSC
OSC
Digital Power-Supply Current
Internal Oscillator LF Mode (14.8MHz nominal),
All Peripherals ON
8.6
7.9
mA
mA
Internal Oscillator LF Mode (14.8MHz nominal),
All Peripherals OFF
Stop Mode, External Clock OFF
100
5.0
1.4
1.3
9.3
8.6
nA
V
DV
DD
4.75
5.25
Normal Mode, f
Normal Mode, f
= 1MHz, All Peripherals ON
= 1MHz, All Peripherals OFF
= 8MHz, All Peripherals ON
= 8MHz, All Peripherals OFF
mA
mA
mA
mA
OSC
OSC
OSC
OSC
Normal Mode, f
Normal Mode, f
Internal Oscillator LF Mode (14.8MHz nom), All
Peripherals ON
18
16
33
mA
mA
mA
Digital Power-Supply Current
Internal Oscillator LF Mode (14.8MHz nom), All
Peripherals OFF
Internal Oscillator HF Mode (29.5MHz nom), All
Peripherals ON
Internal Oscillator HF Mode (29.5MHz nom), All
Peripherals OFF
31
mA
nA
Stop Mode, External Clock OFF
100
Digital Input/Output (CMOS)
V
IH
V
IL
(except XIN pin)
0.6 • DV
DV
DD
V
V
DD
Logic Level
(except XIN pin)
DGND
0.2 • DV
DD
Ports 1 and 3, Input Leakage Current, Input
Mode
V
= DV
or V = 0V
0
µA
DD
IH
IH
I/O Pin Hysteresis
700
mV
V
I
I
I
I
= 1mA
DGND
0.4
OL
V
OL
, Ports 1 and 3, All Output Modes
= 30mA, 3V (20mA)
= 1mA
1.5
V
OL
OH
OH
DV − 0.4
DD
DV − 0.1
DD
DV
DD
V
V , Ports 1 and 3, Strong Drive Output
OH
= 30mA, 3V (20mA)
DV − 1.5
DD
V
Ports 1 and 3, Pull-Up Resistors
Tolerance = 25%
13
kΩ
FLASH MEMORY CHARACTERISTICS: DV
= 2.7V to 5.25V
DD
MSC120x
TYP
MIN
100,000
100
MAX
PARAMETER
CONDITIONS
UNITS
Flash Memory Endurance
Flash Memory Data Retention
Mass and Page Erase Time
Flash Memory Write Time
1,000,000
cycles
Years
ms
Set with FER Value in FTCON, from T
Set with FWR Value in FTCON
to T
10
30
MIN
MAX
40
µs
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SBAS317E − APRIL 2004 − REVISED MAY 2006
(1)
AC ELECTRICAL CHARACTERISTICS : DV
= 2.7V to 5.25V
DD
MSC120x
TYP
MIN
MAX
PARAMETER
CONDITION
UNITS
PHASE LOCK LOOP (PLL)
Input Frequency Range
PLL LF Mode
External Crystal/Clock Frequency (f
PLLDIV = 449 (default)
)
32.768
14.8
kHz
MHz
MHz
ms
OSC
PLL HF Mode
PLLDIV = 899 (must be set by user), DV
Within 1%
= 5V
29.5
DD
PLL Lock Time
2
1
INTERNAL OSCILLATOR (IO)
IO LF Mode
See Typical Characteristics
DV
DV
= 5V
= 5V
14.8
29.5
MHz
MHz
ms
DD
DD
IO HF Mode
IO Settling Time
Within 1%
(1)
Parameters are valid over operating temperature range, unless otherwise specified.
EXTERNAL CLOCK DRIVE CLK TIMING: SEE FIGURE 1
2.7V to 3.6V
MIN
4.75V to 5.25V
MAX
MIN
MAX
SYMBOL
PARAMETER
UNITS
External Clock Mode
(1)
f
External Crystal Frequency (f
)
1
0
20
20
12
1
0
33
33
12
MHz
MHz
MHz
ns
OSC
OSC
(1)
1/t
External Clock Frequency (f
)
OSC
OSC
External Ceramic Resonator Frequency (f
(1)
f
t
t
t
t
)
1
1
OSC
OSC
(2)
High Time
15
15
10
10
HIGH
LOW
R
(2)
Low Time
Rise Time
ns
(2)
(2)
5
5
5
5
ns
Fall Time
= one oscillator clock period for clock divider = 1.
ns
F
(1)
(2)
t
= 1/f
OSC
CLK
These values are characterized but not 100% production tested.
tHIGH
tR
tF
VIH
0.8V
VIH
0.8V
VIH
0.8V
VIH
0.8V
tLOW
tOSC
Figure 1. External Clock Drive CLK
SERIAL FLASH PROGRAMMING TIMING: SEE FIGURE 2
SYMBOL
PARAMETER
MIN
MAX
UNITS
t
t
t
t
t
RST width
2 t
—
5
ns
µs
ms
RW
RRD
RFD
RS
OSC
—
RST rise to P1.0 internal pull high
RST falling to CPU start
—
18
—
—
Input signal to RST falling setup time
RST falling to P1.0 hold time
t
ns
OSC
18
ms
RH
tRW
RST
tRRD
tRS
tRFD, tRH
P1.0/PROG
Ω
NOTE: P1.0 is internally pulled−up with ~11k during RST high.
Figure 2. Serial Flash Programming Timing
8
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SBAS317E − APRIL 2004 − REVISED MAY 2006
PIN CONFIGURATIONS
Top View
TQFP
48 47 46 45 44 43 42 41 40 39 38 37
NC(1)
DVDD
1
2
36
35
34
33
32
31
30
29
28
27
26
25
XIN
XOUT
DGND
RST
DVDD
3
DGND
4
DGND
5
P1.6/INT4
P1.5/INT3
P1.4/INT2/SS
P1.3/DIN
P1.2/DOUT
P1.1
NC(1)
6
MSC1200
NC(1)
7
NC(1)
8
9
AVDD
10
11
12
AGND
AGND
AINCOM
P1.0/PROG
NC(1)
13 14 15 16 17 18 19 20 21 22 23 24
NOTE: (1) NC pins should be left unconnected.
Top View
QFN
36 35 34 33 32 31 30 29 28
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
DVDD
XIN
DGND
XOUT
DGND
RST
P1.6/INT4
P1.5/INT3
P1.4/INT2/SS
P1.3/DIN
P1.2/DOUT
P1.1
MSC1201
MSC1202
NC(1)
AVDD
AGND
AGND
AINCOM
P1.0/PROG
10 11 12 13 14 15 16 17 18
NOTE: (1) NC pin should be left unconnected.
9
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SBAS317E − APRIL 2004 − REVISED MAY 2006
PIN ASSIGNMENTS
MSC1200
PIN #
MSC1201/1202
NAME
DESCRIPTION
PIN #
NC
1, 6, 7, 8, 16,
25, 47
5
No Connection. Leave unconnected.
XIN
2
1
2
The crystal oscillator pin XIN supports parallel resonant AT-cut fundamental frequency crystals and
ceramic resonators. XIN can also be an input if there is an external clock source instead of a crystal.
XIN must not be left floating.
XOUT
3
The crystal oscillator pin XOUT supports parallel resonant AT-cut fundamental frequency crystals and
ceramic resonators. XOUT serves as the output of the crystal amplifier.
DGND
RST
4, 33, 34, 48
3, 26
Digital Ground
5
9
4
Holding the reset input high for two t
periods will reset the device.
OSC
AV
DD
6
7, 8
9
Analog Power Supply
AGND
AINCOM
IDAC
10, 11
12
Analog Ground
Analog Input (can be analog common for single-ended inputs or analog input for differential inputs)
IDAC Output
13
10
REFOUT/REF IN+
REF IN−
AIN7
14
11
Internal Voltage Reference Output/Voltage Reference Positive Input (required C
Voltage Reference Negative Input (tie to AGND for internal voltage reference)
Analog Input Channel 7
= 0.1µF)
REF
15
12
17
—
AIN6
18
—
Analog Input Channel 6
AIN5
19
13
Analog Input Channel 5
AIN4
20
14
Analog Input Channel 4
AIN3
21
15
Analog Input Channel 3
AIN2
22
16
Analog Input Channel 2
AIN1
23
17
Analog Input Channel 1
AIN0
24
18
Analog Input Channel 0
P1.0−P1.7
26−32, 37
19−25, 28
Port 1 is a bidirectional I/O port (refer to P1DDRL, SFR AEh, and P1DDRH, SFR AFh, for port pin
configuration control).
The alternate functions for Port 1 are listed below.
Port
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Alternate Name(s)
PROG
N/A
Alternate Use
Serial programming mode (must be DGND on reset)
DOUT
DIN
Serial data out
Serial data in
INT2/SS
INT3
External interrupt 2 / Slave Select
External interrupt 3
External interrupt 4
External interrupt 5
INT4
INT5
DV
DD
35, 36, 46
38−45
27
Digital Power Supply
P3.0−P3.7
29−36
Port 3 is a bidirectional I/O port (refer to P3DDRL, SFR B3h, and P3DDRH, SFR B4h, for port pin
configuration control).
The alternate functions for Port 3 are listed below.
Port
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Name(s)
Alternate Use
RxD0
Serial port 0 input
TxD0
Serial port 0 output
INT0
External interrupt 0
INT1
External interrupt 1
T0
Timer 0 external input
Timer 1 external input
SCK / SCL / various clocks (refer to PASEL, SFR F2h)
T1
SCK/SCL/CLKS
N/A
10
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SBAS317E − APRIL 2004 − REVISED MAY 2006
TYPICAL CHARACTERISTICS: MSC1200 AND MSC1201 ONLY
AV
= +5V, DV
= +5V, f
OSC
= 8MHz, PGA = 1, f
MOD
= 15.625kHz, ADC Bipolar Mode, Buffer ON, and V ≡ (REF IN+) − (REF IN−) = +2.5V, unless
REF
DD
DD
otherwise specified.
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
EFFECTIVE NUMBER OF BITS vs DATA RATE
23
22
21
20
19
18
17
16
15
14
13
12
11
10
22
21
20
19
18
17
16
15
14
13
12
PGA8
PGA2
PGA4
PGA1
PGA1
PGA8
PGA32
PGA64
PGA128
PGA32
PGA64
PGA128
PGA16
Sinc3 Filter, Buffer OFF
Sinc3 Filter, Buffer OFF
1
0
0
10
100
Data Rate (SPS)
1000
2000
2000
0
0
0
500
1000
Decimation Ratio =
1500
fMOD
2000
fDATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
20
19
18
17
16
15
14
13
12
22
21
20
19
18
17
16
15
14
13
12
PGA8
PGA4
PGA8
PGA2
PGA4
PGA2
PGA1
PGA1
PGA32
PGA128
PGA16
PGA64
PGA128
PGA64
PGA32
PGA16
Sinc3 Filter, Buffer ON
AVDD = 3V, Sinc3 Filter,
VREF = 1.25V, Buffer OFF
500
1000
Decimation Ratio =
1500
2000
500
1000
Decimation Ratio =
1500
fMOD
fMOD
fDATA
fDATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
20
19
18
17
16
15
14
13
12
22
21
20
19
18
17
16
15
14
13
12
PGA2 PGA4
PGA1
PGA8
PGA4
PGA8
PGA2
PGA1
PGA16 PGA64
PGA32
PGA128
PGA32
PGA128
PGA64
PGA16
Sinc2 Filter
AVDD = 3V, Sinc3 Filter,
VREF = 1.25V, Buffer ON
500
1000
1500
2000
500
1000
Decimation Ratio =
1500
fMOD
fMOD
Decimation Ratio =
fDATA
fDATA
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SBAS317E − APRIL 2004 − REVISED MAY 2006
TYPICAL CHARACTERISTICS: MSC1200 AND MSC1201 ONLY (Continued)
AV
= +5V, DV
= +5V, f
OSC
= 8MHz, PGA = 1, f
MOD
= 15.625kHz, ADC Bipolar Mode, Buffer ON, and V ≡ (REF IN+) − (REF IN−) = +2.5V, unless
REF
DD
DD
otherwise specified.
FAST SETTLING FILTER
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO
EFFECTIVE NUMBER OF BITS vs fMOD
(set with ACLK)
20
19
18
17
16
15
14
13
12
11
10
25
20
15
10
5
Gain 1
fMOD = 203kHz
fMOD = 15.6kHz
fMOD = 31.25kHz
fMOD = 110kHz
Gain 16
Gain 128
fMOD = 62.5kHz
0
0
500
1000
1500
2000
100k
2.5
1
10
100
1k
10k
100k
Data Rate (SPS)
Decimation Value
EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK)
WITH FIXED DECIMATION
HISTOGRAM OF ADC OUTPUT DATA
25
20
15
10
5
4500
4000
3500
3000
2500
2000
1500
1000
500
DEC = 2020
DEC = 500
DEC = 50
DEC = 255
DEC = 20
DEC = 10
0
0
−
−
−
−
0.5
10
100
1k
10k
2
1.5
1
0
0.5
1
1.5
2
Data Rate (SPS)
ppm of FS
EFFECTIVE NUMBER OF BITS vs INPUT SIGNAL
(Internal and External VREF
NOISE vs INPUT SIGNAL
)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
22.0
21.5
21.0
20.5
20.0
19.5
19.0
18.5
18.0
External
Internal
−
−
−
−
−
−
0.5
2.5
1.5
0.5
0.5
1.5
2.5
1.5
0.5
1.5
2.5
VIN (V)
VIN (V)
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SBAS317E − APRIL 2004 − REVISED MAY 2006
TYPICAL CHARACTERISTICS: MSC1202 ONLY
AV
= +5V, DV
= +5V, f
OSC
= 8MHz, PGA = 1, f
MOD
= 15.625kHz, ADC Bipolar Mode, Buffer ON, and V ≡ (REF IN+) − (REF IN−) = +2.5V, unless
REF
DD
DD
otherwise specified.
EFFECTIVE NUMBER OF BITS
vs DATA RATE
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
20
19
18
17
16
15
14
13
12
11
10
20
19
18
17
16
15
14
13
12
11
PGA1
PGA128
PGA1
Sinc3 Filter, Buffer OFF
PGA128
Sinc3 Filter, Buffer OFF
10
0
0
0
500
1000
1500
2000
1
0
0
10
100
Data Rate (SPS)
1000
2000
2000
fMOD
Decimation Ratio =
fDATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
20
19
18
17
16
15
14
13
12
11
10
20
19
18
17
16
15
14
13
12
11
10
PGA1
PGA128
PGA1
PGA128
Sinc3 Filter, Buffer ON
AVDD = 3V, Sinc3 Filter,
VREF = 1.25V, Buffer OFF
500
1000
1500
2000
500
1000
Decimation Ratio =
1500
fMOD
fMOD
Decimation Ratio =
fDATA
fDATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
20
19
18
17
16
15
14
13
12
11
10
20
19
18
17
16
15
14
13
12
11
10
PGA1
PGA1
PGA128
PGA128
Sinc2 Filter
AVDD = 3V, Sinc3 Filter,
VREF = 1.25V, Buffer ON
500
1000
1500
fMOD
2000
500
1000
Decimation Ratio =
1500
fMOD
Decimation Ratio =
fDATA
fDATA
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SBAS317E − APRIL 2004 − REVISED MAY 2006
TYPICAL CHARACTERISTICS: MSC1202 ONLY (Continued)
AV
= +5V, DV
= +5V, f
OSC
= 8MHz, PGA = 1, f
MOD
= 15.625kHz, ADC Bipolar Mode, Buffer ON, and V
REF
≡ (REF IN+) − (REF IN−) = +2.5V, unless
DD
DD
otherwise specified.
FAST SETTLING FILTER
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO
EFFECTIVE NUMBER OF BITS vs fMOD
(set with ACLK)
20
19
18
17
16
15
14
13
12
11
10
20
16
12
8
fMOD = 203kHz
fMOD = 15.6kHz
fMOD = 31.25kHz
fMOD = 110kHz
Fast Settling Filter
fMOD = 62.5kHz
1k
4
0
500
1000
1500
fMOD
2000
1
10
100
10k
100k
Data Rate (SPS)
Decimation Ratio =
fDATA
EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK)
WITH FIXED DECIMATION
25
20
15
10
5
DEC > 100
DEC = 50
DEC = 20
DEC = 10
0
10
100
1k
10k
100k
Data Rate (SPS)
14
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SBAS317E − APRIL 2004 − REVISED MAY 2006
TYPICAL CHARACTERISTICS: ALL DEVICES
AV
= +5V, DV
= +5V, f
OSC
= 8MHz, PGA = 1, f
MOD
= 15.625kHz, ADC Bipolar Mode, Buffer ON, and V ≡ (REF IN+) − (REF IN−) = +2.5V, unless
REF
DD
DD
otherwise specified.
ADC INTEGRAL NONLINEARITY
vs INPUT VOLTAGE
ADC INTEGRAL NONLINEARITY
vs INPUT VOLTAGE
15
15
10
5
AVDD = 5V
VREF = 2.5V
Buffer OFF
AVDD = 5V
VREF = 2.5V
Buffer ON
−
_
40 C
−
_
40 C
10
5
_
+25 C
_
+25 C
−
_
55 C
0
0
_
+85 C
−
−
5
5
−
−
−
−
10
10
_
+125 C
_
+85 C
15
−
15
−
−
−
−
−
−
−
−
−
2.5 2.0 1.5 1.0 0.5
0
0.5 1.0 1.5 2.0 2.5
2.5 2.0 1.5 1.0 0.5
0
0.5 1.0 1.5 2.0 2.5
ADC Input Voltage (V)
ADC Input Voltage (V)
ADC INTEGRAL NONLINEARITY
vs INPUT SIGNAL
ADC INTEGRAL NONLINEARITY
vs VREF
15
10
5
30
25
20
15
10
5
VIN = VREF
Buffer OFF
VREF = AVDD = 5V
Buffer OFF
0
AVDD = 3V
−
5
10
15
AVDD = 5V
−
−
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VREF (V)
−
VIN
=
VREF
0
VIN = +VREF
VIN (V)
ADC INTEGRAL NONLINEARITY ERROR
vs PGA
ADC OFFSET vs TEMPERATURE
_
(Offset Calibration at 25 C Only)
50
45
40
35
30
25
20
15
10
5
15
10
5
AVDD = 5V
VREF = 2.5V
AVDD = 3V
AVDD = 5V
0
−
5
−
−
10
0
15
1
2
4
8
16
32
64
128
−
−
−
60
40 20
0
20 40
60
80 100 120 140
PGA Setting
_
Temperature ( C)
15
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SBAS317E − APRIL 2004 − REVISED MAY 2006
TYPICAL CHARACTERISTICS: ALL DEVICES (Continued)
AV
= +5V, DV
= +5V, f
OSC
= 8MHz, PGA = 1, f
MOD
= 15.625kHz, ADC Bipolar Mode, Buffer ON, and V
REF
≡ (REF IN+) − (REF IN−) = +2.5V, unless
DD
DD
otherwise specified.
ANALOG SUPPLY CURRENT
vs ANALOG SUPPLY VOLTAGE
ADC POWER−SUPPLY CURRENT
vs PGA
1.4
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
PGA = 128
DVDD = AVDD
VREF = 1.25V
_
+125 C
1.3
1.2
1.1
1.0
0.9
0.8
0.7
_
+85 C
AVDD = 5V, Buffer = ON
_
+25 C
AVDD = 3V, Buffer = ON
AVDD = 5V, Buffer = OFF
AVDD = 3V, Buffer = OFF
−
−
_
40 C
_
55 C
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1
2
4
8
16
32
64
128
Analog Supply Voltage (V)
PGA Setting
ADC OFFSET DAC:
ADC OFFSET DAC:
OFFSET vs TEMPERATURE
GAIN vs TEMPERATURE
14
12
10
8
6
4
1.00008
1.00006
1.00004
1.00002
1
2
0
−
−
−
−
2
4
6
8
0.99998
0.99996
0.99994
0.99992
−
−
−
−
10
12
14
16
−
−
−
−
−
−
20
60
40 20
0
+20 +40 +60 +80 +100 +120 +140
60
40
0
+20 +40 +60 +80 +100 +120 +140
_
_
Temperature ( C)
Temperature ( C)
DIGITAL SUPPLY CURRENT
vs EXTERNAL CLOCK FREQUENCY
DIGITAL SUPPLY CURRENT vs CLOCK DIVIDER
100
10
1
100
10
1
Divider Values
1
DVDD = 5V
Normal Mode
DVDD = 5V
Idle Mode
2
4
DVDD = 3V
Normal Mode
8
16
32
1024
DVDD = 3V
Idle Mode
0.1
0.1
1
10
100
1
10
Clock Frequency (MHz)
100
Clock Frequency (MHz)
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SBAS317E − APRIL 2004 − REVISED MAY 2006
TYPICAL CHARACTERISTICS: ALL DEVICES (Continued)
AV
= +5V, DV
= +5V, f
OSC
= 8MHz, PGA = 1, f
MOD
= 15.625kHz, ADC Bipolar Mode, Buffer ON, and V
≡ (REF IN+) − (REF IN−) = +2.5V, unless
DD
DD
REF
otherwise specified.
DIGITAL SUPPLY CURRENT
vs DIGITAL SUPPLY VOLTAGE
ADC NORMALIZED GAIN
vs PGA
101
100
99
11
PGA = 128
DVDD = AVDD
VREF = 1.25V
10
9
_
+125 C
External Reference
Buffer OFF
_
+85 C
8
_
+25 C
98
7
−
_
55 C
6
97
96
95
−
_
40 C
External Reference
Buffer ON
5
4
3
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1
2
4
8
16
32
64
128
PGA Setting
Digital Supply Voltage (V)
VOLTAGE REFERENCE INPUT CURRENT
vs PGA SETTING
VOLTAGE REFERENCE CHANGE
vs ANALOG SUPPLY VOLTAGE
40
35
30
25
20
15
10
5
101.0
100.8
100.6
100.4
100.2
100.0
99.8
VREF = 2.5V
fMOD = 62.5kHz
VREF = 1.25V
fMOD = 62.5kHz
VREF = 2.5V
fMOD = 15.6kHz
1.25V
VREF = 1.25V
fMOD = 15.6kHz
2.5V
99.6
99.4
99.2
0
99.0
2.5 2.75 3.0 3.25 3.5 3.75 4.0 4.25 4.5 4.75 5.0 5.25
Analog Supply Voltage (V)
1
2
4
8
16
32
64
128
PGA Gain
INTERNAL OSCILLATOR LOW−FREQUENCY MODE
vs TEMPERATURE
INTERNAL OSCILLATOR HIGH−FREQUENCY MODE
vs TEMPERATURE
16.0
15.5
15.0
14.5
14.0
13.5
13.0
12.5
12.0
32
31
30
29
28
27
26
5.25V
4.75V
5.25V
4.75V
3.3V
2.7V
−
−
−
−
−
−
40 20
60
40
20
0
20 40
60
80 100 120 140
60
0
20 40
60
80 100 120 140
_
_
Temperature ( C)
Temperature ( C)
17
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SBAS317E − APRIL 2004 − REVISED MAY 2006
TYPICAL CHARACTERISTICS: ALL DEVICES (Continued)
AV
= +5V, DV
= +5V, f
OSC
= 8MHz, PGA = 1, f
MOD
= 15.625kHz, ADC Bipolar Mode, Buffer ON, and V
REF
≡ (REF IN+) − (REF IN−) = +2.5V, unless
DD
DD
otherwise specified.
IDAC OUTPUT CURRENT AT TEMPERATURE
vs ANALOG SUPPLY VOLTAGE
IDAC OUTPUT CURRENT
vs IDAC OUTPUT VOLTAGE
1020
1010
1000
990
980
970
960
950
940
930
920
910
900
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
−
_
55 C
AVDD = 5V
−
_
40 C
_
+25 C
AVDD = 3V
_
+85 C
_
+125 C
IDAC = FFh
0.1
0
2.5 2.75 3.0 3.25 3.5 3.75 4.0 4.25 4.5 4.75 5.0 5.25
Analog Supply Voltage (V)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
IDAC Output Votage (V)
IDAC INTEGRAL NONLINEARITY
vs IDAC CODE
DIGITAL OUTPUT PIN VOLTAGE
2.0
1.5
1.0
0.5
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5V
Low
Output
3V
Low
Output
5V
3V
−
0.5
0
10
20
30
40
50
60
70
Output Current (mA)
IDAC Code
HISTOGRAM OF
TEMPERATURE SENSOR VALUES
22
20
18
16
14
12
10
8
6
4
2
0
Temperature Sensor Value (mV)
18
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SBAS317E − APRIL 2004 − REVISED MAY 2006
programmable sample rate. The ADC also has a
selectable filter that allows for high-resolution, single-cycle
conversions.
DESCRIPTION
The MSC1200Yx, MSC1201Yx, and MSC1202Yx are
completely integrated families of mixed-signal devices
incorporating a high-resolution, delta-sigma ADC, 8-bit
cuurent output DAC, input multiplexer, burnout detect
current sources, selectable buffered input, offset DAC,
programmable gain amplifier (PGA), temperature sensor,
voltage reference, 8-bit 8051 microcontroller, Flash
Program Memory, Flash Data Memory, and Data SRAM,
as shown in Figure 3. The MSC1200, MSC1201, and
MSC1202 will be referred to as the MSC120x in this
document, unless otherwise noted.
The microcontroller core is 8051 instruction set
compatible. The microcontroller core is an optimized 8051
core that executes up to three times faster than the
standard 8051 core, given the same clock source. This
design makes it possible to run the device at a lower
external clock frequency and achieve the same
performance at lower power than the standard 8051 core.
The MSC120x allow users to uniquely configure the Flash
Memory map to meet the needs of their applications. The
Flash is programmable down to +2.7V using serial
programming. Flash endurance is typically 1M
Erase/Write cycles.
On-chip peripherals include an additional 32-bit
summation register, basic SPI, basic I2C, USART, two
8-bit digital input/output ports,
a watchdog timer,
The parts have separate analog and digital supplies, which
can be independently powered from +2.7V to +5.25V. At
+3V operation, the power dissipation for the part is
typically less than 3mW. The MSC1200 is available in a
TQFP-48 package. The MSC1201 and MSC1202 are both
available in a QFN-36 package.
low-voltage detect, on-chip power-on reset, brownout
reset, timer/counters, system clock divider, PLL, on-chip
oscillator, and external or internal interrupts.
The devices accept differential or single-ended signals
directly from a transducer. The ADC provides 24 bits
(MSC1200/01) or 16 bits (MSC1202) of resolution and 24
bits (MSC1200/01) or 16 bits (MSC1202) of
no-missing-code performance using a Sinc3 filter with a
The MSC120x are designed for high-resolution
measurement applications in smart transmitters, industrial
process control, weigh scales, chromatography, and
portable instrumentation.
(1)
−
REF IN
AVDD AGND
AVDD
REFOUT/REFIN+
DVDD DGND
Burnout
Detect
Timers/
Counters
VREF
ALVD
DBOR
POR
Temperature
Sensor
8−Bit
Offset DAC
WDT
AIN0
AIN1
Alternate
Functions
AIN2
AIN3
Digital
Filter
Modulator
DIN
DOUT
SS
EXT (4)
BUF
PGA
AIN4
MUX
AIN5
PORT1
PORT3
AIN6(2)
AIN7(2)
AINCOM
4K or 8K
FLASH
32−Bit ACC
PROG
USART0
EXT (2)
T0
256 Bytes
SRAM
8051
SFR
T1
SCK/SCL/CLKS
Burnout
Detect
128 Bytes
System FLASH
On−Chip
Oscillator
RST
System
Clock
AGND
Divider
PLL
8−Bit IDAC
IDAC
XIN XOUT
−
NOTES: (1) REF IN must be tied to AGND when using internal VREF
.
(2) AIN6 and AIN7 available only on MSC1200.
Figure 3. Block Diagram
19
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SBAS317E − APRIL 2004 − REVISED MAY 2006
ENHANCED 8051 CORE
Single−Byte, Single−Cycle
Instruction
All instructions in the MSC120x families perform exactly
the same functions as they would in a standard 8051. The
effects on bits, flags, and registers are the same; however,
the timing is different. The MSC120x families use an
efficient 8051 core that results in an improved instruction
execution speed of between 1.5 and 3 times faster than the
original core for the same external clock speed (4 clock
cycles per instruction versus 12 clock cycles per
instruction, as shown in Figure 4). This efficiency
translates into an effective throughput improvement of
more than 2.5 times, using the same code and same
external clock speed. Therefore, a device frequency of
33MHz for the MSC120x actually performs at an
equivalent execution speed of 82.5MHz compared to the
standard 8051 core. This increased performance allows
the device to be tun at slower clock speeds, which reduces
system noise and power consumption, but provides
greater throughput. This performance difference can be
seen in Figure 5. The timing of software loops will be faster
with the MSC120x. However, the timer/counter operation
of the MSC120x may be maintained at 12 clocks per
increment or optionally run at 4 clocks per increment.
Internal
ALE
Internal
PSEN
Internal
AD0−AD7
Internal
A8−A15
4 Cycles
CLK
12 Cycles
ALE
PSEN
AD0−AD7
PORT 2
Single−Byte, Single−Cycle
Instruction
The MSC120x also provide dual data pointers (DPTRs).
Figure 5. Comparison of MSC120x Timing to
Standard 8051 Timing
fCLK
instr_cycle
cpu_cycle
n + 1
n + 2
C1
C2
C3
C4
C1
C2
C3
C4
C1
Figure 4. Instruction Timing Cycle
20
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Furthermore, improvements were made to peripheral
features that off-load processing from the core, and the
user, to further improve efficiency. These iprovements
allow for 32-bit addition, subtraction and shifting to be
accomplished in a few instruction cycles, compared to
hundreds of instruction cycles executed through software
implementation. For instance, 32-bit accumulation can be
done through the summation register to significantly
reduce the processing overhead for multiple-byte data
from the ADC or other sources.
differently than the MSC1200 or MSC1201.) This gives the
user the ability to add or subtract software functions and to
migrate between family members. Thus, the MSC120x
can become a standard device used across several
application platforms.
Family Development Tools
The MSC120x are fully compatible with the standard 8051
instruction set. This compatibility means that users can
develop software for the MSC120x with their existing 8051
development tools. Additionally, a complete, integrated
development environment is provided with each demo
board, and third-party developers also provide support.
Family Device Compatibility
The hardware functionality and pin configuration across
the MSC120x families are fully compatible. To the user, the
only difference between family members is the memory
configuration. This design makes migration between
family members simple. Code written for the MSC1200Y2,
MSC1201Y2, or MSC1202Y2 can be executed directly on an
MSC1200Y3, MSC1201Y3, or MSC1202Y3, respectively.
(However, the ADC registers for the MSC1202 are mapped
Power-Down Modes
The MSC120x can power several of the on-chip
peripherals and put the CPU into Idle mode. This is
accomplished by shutting off the clocks to those sections,
as shown in Figure 6.
fOSC
fSYS
SYSCLK
fCLK
STOP
C7
SCL/SCK
SPICON/
I2CCON
9A
PDCON.0
µ
s
Flash Write
FTCON
[3:0]
USEC
µ
µ
(30 s to 40 s)
EF Timing
FB
ms
Flash Erase
FTCON
[7:4]
MSECH
MSECL
(5ms to 11ms)
Timing
FC
EF
FD
milliseconds
interrupt
MSINT
FA
SECINT
seconds
interrupt
PDCON.1
F9
100ms
HMSEC
watchdog
WDTCON
FF
FE
PDCON.2
ADCON2
ADC Output Rate
divide
by 64
fDATA
fSAMP
fMOD
ADCON3
ACLK
F6
ADC Power Down
DF
DE
Decimation Ratio
Modulator Clock
ADCON0
DC
(see Figure 9)
PDCON.3
Timers 0/1
CPU Clock
USART0
IDLE
Figure 6. MSC120x Timing Chain and Clock Control
21
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SBAS317E − APRIL 2004 − REVISED MAY 2006
OVERVIEW
The MSC120x ADC structure is shown in Figure 7. The figure lists the components that make up the ADC, along with the
corresponding special function register (SFR) associated with each component.
AVDD
AIN0
AIN1
Burnout
Detect
REFIN+
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
fSAMP
Input
Multiplexer
MSC1200
Only
In+
Sample
and Hold
Σ
Buffer
PGA
−
In
AINCOM
Temperature
Sensor
Burnout
Detect
Offset
DAC
−
REFIN
D7h ADMUX
DCh ADCON0
F6h ACLK
E6h ODAC
AGND
A4h AIPOL.5
A4h AIPOL.6
A6h AIE.6
A7h AISTAT.6
fDATA
REFIN+ fMOD
A6h AIE.5
A7h AISTAT.5
FAST
VIN
ADC
Result Register
∆Σ
Modulator
SINC2
SINC3
AUTO
ADC
Σ
X
Summation
Block
Offset
Gain
Calibration
Register
Calibration
Register
Σ
−
REFIN
DDh ADCON1
DEh ADCON2
DFh ADCON3
OCR
GCR
ADRES
D3h D2h D1h
D6h D5h D4h
DBh(1) DAh D9h
SUMR
E5h E4h E3h E2h
NOTE: (1) For the MSC1202, this register is sign−extended (Bipolar mode) or zero−padded
(Unipolar mode) for the 16−bit result in registers DAh and D9h.
E1h
SSCON
Figure 7. MSC120x ADC Structure
22
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SBAS317E − APRIL 2004 − REVISED MAY 2006
ADC INPUT MULTIPLEXER
TEMPERATURE SENSOR
The input multiplexer provides for any combination of
differential inputs to be selected as the input channel, as
shown in Figure 8. For example, if AIN0 is selected as the
positive differential input channel, then any other channel
can be selected as the negative differential input channel.
With this method, it is possible to have up to six fully
differential input channels. It is also possible to switch the
polarity of the differential input pair to negate any offset
voltages. In addition, current sources are supplied that will
source or sink current to detect open or short circuits on the
pins.
On-chip diodes provide temperature sensing capability.
When the configuration register for the input mux is set to
all 1s, the diodes are connected to the inputs of the ADC.
All other channels are open. The internal device power
dissipation affects the temperature sensor reading. It is
recommended that the internal buffer be enabled for
temperature sensor measurements.
BURNOUT DETECT
When the Burnout Detect (BOD) bit is set in the ADC
control configuration register (ADCON0, SFR DCh), two
current sources are enabled. The current source on the
positive input channel sources approximately 2µA of
current. The current source on the negative input channel
sinks approximately 2µA. These current sources allow for
the detection of an open circuit (full-scale reading) or short
circuit (small differential reading) on the selected input
differential pair. The buffer should be on for sensor burnout
detection.
AIN0
AIN1
AVDD
µ
Burnout Detect (2 A)
AIN2
AIN3
AIN4
ADC INPUT BUFFER
The analog input impedance is always high, regardless of
PGA setting (when the buffer is enabled). With the buffer
enabled, the input voltage range is reduced and the analog
power-supply current is higher. If the limitation of input
voltage range is acceptable, then the buffer is always
preferred.
In+
Buffer
−
In
The input impedance of the MSC120x without the buffer is
7MΩ/PGA. The buffer is controlled by the state of the BUF
bit in the ADC control register (ADCON0, SFR DCh).
AIN5
AIN6(1)
AIN7(1)
µ
Burnout Detect (2 A)
Temperature Sensor
AVDD
AVDD
AGND
•
80
I
I
AINCOM
−
NOTE: (1) For MSC1201/MSC1202, AIN6 and AIN7 are tied to REFIN .
Figure 8. Input Multiplexer Configuration
23
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Table 1. ENOB versus PGA (Bipolar Mode)
ADC ANALOG INPUT
RMS
INPUT-REFERRED
When the buffer is not selected, the input impedance of the
analog input changes with ACLK clock frequency (ACLK,
SFR F6h) and gain (PGA). The relationship is:
MSC1200
MSC1201
ENOB
AT 10HZ
(BITS)
MSC1202
(1)
NOISE
ENOB
FULL-
SCALE
RANGE
(V)
(1)
MSC1200
UP TO
200HZ
(BITS)
MSC1202
MSC1201
(nV)
PGA
SETTING
1
Impedance (W) +
fSAMP @ CS
(mV)
1
2
2.5
21.7
21.5
21.4
21.2
20.8
20.4
20
16
1468
843
76.3
38.1
19.1
9.5
1.25
15.6
15.5
15.4
15.4
15.3
15.2
14.2
1MHz
ACLK Frequency
7MW
PGA
@ ǒ Ǔ
Impedance (W) + ǒ
Ǔ
AIN
4
0.625
0.313
0.156
0.078
0.039
0.019
452
8
259
fCLK
ACLK ) 1
16
32
64
128
(1)
171
4.8
where ACLK frequency (fACLK) +
113
2.4
74.5
74.5
24
12
fACLK
64
andfMOD
+
.
19
0.6
ENOB = Log (FSR/RMS Noise) = Log (2 ) − Log (σ
)
2
2
2
CODES
NOTE: The input impedance for PGA = 128 is the same as
= 24 − Log (σ
)
2
CODES
that for PGA = 64 (that is, 7MΩ/64).
ADC OFFSET DAC
Figure 9 shows the basic input structure of the MSC120x.
The analog output from the PGA can be offset by up to half
the full-scale range of the ADC by using the ODAC register
(SFR E6h). The ODAC (Offset DAC) register is an 8-bit
value; the MSB is the sign and the seven LSBs provide the
magnitude of the offset.
RSWITCH
Ω
(3k typical)
High Impedance
AIN
Ω
> 1G
ADC MODULATOR
CS
PGA
CS
Sampling Frequency = fSAMP
The modulator is a single-loop, 2nd-order system. The
modulator runs at a clock speed (fMOD) that is derived from
CLK using the value in the Analog Clock register (ACLK,
SFR F6h). The data output rate is:
1
2
9pF
PGA
fSAMP
fMOD
18pF
36pF
AGND
1, 2, 4
8
4 to 128
×
×
×
2
4
8
fMOD
fMOD
fMOD
fACLK
64
16
fMOD
=
fMOD
32
Data Rate + fDATA
+
Decimation Ratio
×
64, 128 16 fMOD
fCLK
fACLK
64
where fMOD
+
+
.
(ACLK ) 1) @ 64
and Decimation Ratio is set in [ADCON3:ADCON2]
Figure 9. Analog Input Structure (without Buffer)
ADC PGA
ADC CALIBRATION
The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128.
Using the PGA can actually improve the effective
resolution of the ADC. For instance, with a PGA of 1 on a
2.5V full-scale range (FSR), the ADC can resolve to
1.5µV. With a PGA of 128 on a 19mV FSR, the ADC can
resolve to 75nV. With a PGA of 1 on a 2.5V FSR, it would
require a 26-bit ADC to resolve 75nV, as shown in Table 1.
The offset and gain errors in the MSC120x, or the complete
system, can be reduced with calibration. Calibration is
controlled through the ADCON1 register (SFR DDh), bits
CAL2:CAL0. Each calibration process takes seven tDATA
periods (data conversion time) to complete. Therefore, it
takes 14 tDATA periods to complete both an offset and gain
calibration.
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SBAS317E − APRIL 2004 − REVISED MAY 2006
For system calibration, the appropriate signal must be
applied to the inputs. It then computes an offset that will
nullify offset in the system. The system gain calibration
requires a positive full-scale differential input signal. It then
computes a gain value to nullify gain errors in the system.
Each of these calibrations will take seven tDATA periods to
complete.
SINC3 FILTER RESPONSE
0
−20
(−3dB = 0.262 • fDATA
)
−40
Calibration should be performed after power on. It should
also be done after a change in temperature, decimation
ratio, buffer, power supply, voltage reference, or PGA. The
offset DAC will affect offset calibration; therefore, the value
of the offset should be zero before performing a calibration.
−60
−80
−100
−120
At the completion of calibration, the ADC Interrupt bit goes
high, which indicates the calibration is finished and valid
data is available.
0
1
2
3
4
5
fDATA
ADC DIGITAL FILTER
The Digital Filter can use either the Fast Settling, Sinc2, or
Sinc3 filter, as shown in Figure 10. In addition, the Auto
mode changes the Sinc filter after the input channel or
PGA is changed. When switching to a new channel, it will
use the Fast Settling filter for the next two conversions, the
first of which should be discarded. It will then use the Sinc2
followed by the Sinc3 filter to improve noise performance.
This combines the low-noise advantage of the Sinc3 filter
with the quick response of the Fast Settling Time filter. The
frequency response of each filter is shown in Figure 11.
SINC2 FILTER RESPONSE
(−3dB = 0.318 • fDATA
0
−20
)
−40
−60
−80
−100
−120
Adjustable Digital Filter
Sinc3
0
1
2
3
4
5
fDATA
Sinc2
Modulator
Data Out
FAST SETTLING FILTER RESPONSE
(−3dB = 0.469 • fDATA
0
−20
Fast Settling
)
FILTER SETTLING TIME
SETTLING TIME
−40
(1)
FILTER
(Conversion Cycles)
−60
3
2
Sinc
Sinc
Fast
3
2
1
−80
(1)
With synchronized channel changes.
−100
−120
AUTO MODE FILTER SELECTION
CONVERSION CYCLE
0
1
2
3
4
5
fDATA
1
2
3
4+
2
3
Fast
Fast
Sinc
Sinc
NOTE: fDATA = Data Output Rate = 1/tDATA
Figure 10. Filter Step Responses
Figure 11. Filter Frequency Responses
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SBAS317E − APRIL 2004 − REVISED MAY 2006
VOLTAGE REFERENCE
RESET
The MSC120x can use either an internal or external
voltage reference. The voltage reference selection is
controlled via ADC Control Register 0 (ADCON0, SFR
DCh). The default power-up configuration for the voltage
reference is 2.5V internal.
DThe MSC120x can be reset from the following sources:
Power-on reset
D
D
D
D
External reset
Software reset
The internal voltage reference can be selected as either
1.25V or 2.5V. The analog power supply (AVDD) must be
within the specified range for the selected internal voltage
reference. The valid ranges are: VREF = 2.5 internal
(AVDD = 3.3V to 5.25V) and VREF = 1.25 internal
(AVDD = 2.7V to 5.25V). If the internal VREF is selected,
then AGND must be connected to REFIN−. The
REFOUT/REFIN+ pin should also have a 0.1µF capacitor
connected to AGND as close as possible to the pin. If the
internal VREF is not used, then VREF should be disabled in
ADCON0.
Watchdog timer reset
Brownout reset
An external reset is accomplished by taking the RST pin
high for two t
periods, followed by taking the RST pin
OSC
low. A software reset is accomplished through the System
Reset register (SRTST, 0F7h). A watchdog timer reset is
enabled and controlled through Hardware Configuration
Register 0 (HCR0) and the Watchdog Timer register
(WDTCON, 0FFh). A brownout reset is enabled through
Hardware Configuration Register 1 (HCR1). Power-on
17
reset and external reset complete after 2 clock cycles,
If the external voltage reference is selected, it can be used
as either a single-ended input or differential input, for
ratiometric measures. When using an external reference,
it is important to note that the input current will increase for
using the internal oscillator in low-frequency mode.
Brownout reset, watchdog timer reset, and software reset
15
complete after 2 clock cycles, using the active clock
source.
V
REF with higher PGA settings and with a higher modulator
All sources of reset cause the digital pins to be pulled high
from the initiation of the reset procedure. For an external
reset, taking the RST pin high stops device operation
(crystal oscillation, internal oscillator, or PLL circuit
operation) and causes all digital pins to be pulled high from
that point. Taking the RST pin low initiates the reset
procedure.
frequency. The external voltage reference can be used
over the input range specified in the Electrical
Characteristics section.
IDAC
The 8-bit IDAC in the MSC120x provides a current source
that can be used for ratiometric measurements. The IDAC
operates from its own voltage reference and is not
dependent on the ADC voltage reference. The full-scale
output current of the IDAC is approximately 1mA (within
the compliance voltage range). The equation for the IDAC
output current is:
A recommended external reset circuit is shown in
Figure 12. The serial 10kΩ resistor is recommended for
any external reset circuit configuration. For proper
execution of the reset procedure, it is necessary to keep
the AV
supply above 2.0V during the reset procedure.
DD
DVDD
0.1 F
IDACOUT mA [ IDAC @ 3.9mA (at 25°C)
MSC120x
µ
Ω
10k
4
RST
The IDAC output voltage cannot exceed the compliance
voltage of AVDD − 1.5V.
Ω
1M
Figure 12. Typical Reset Circuit
Note that pin P1.0/PROG defines operation of the device
after reset. If P1.0/PROG is not connected or pulled high
during reset, the device will enter User Application mode
(UAM). If P1.0/PROG is pulled low during reset, the device
will enter Serial Flash Programming mode (SFPM). Refer
to the Electrical Characteristics section for timing
information.
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SBAS317E − APRIL 2004 − REVISED MAY 2006
By configuring the device prior to entering Idle mode,
further power reductions can be achieved (while in Idle
mode). These power reductions include powering down
peripherals not in use in the PDCON register (0F1h), and
reducing the system clock frequency by using the System
Clock Divider register (SYSCLK, 0C7h).
POWER ON RESET
The on-chip Power On Reset (POR) circuitry releases the
device from reset when DV
≈ 2.0V. The power supply
DD
ramp rate does not affect the POR. If the power supply falls
below 1.0V for longer than 200ms, the POR will execute.
If the power supply falls below 1.0V for less than 200ms,
unexpected operation may occur. If these conditions are
not met, the POR will not execute. For example, a negative
STOP MODE
spike on the DV supply that does not remain below 1.0V
DD
Stop mode is entered by setting the STOP bit in the Power
Control register (PCON, 087h). In Stop mode, all internal
clocks are halted. This mode has the lowest power
consumption. The device can be returned to active mode
only via an external reset or power-on reset (not a
brownout reset).
for at least 200ms, will not initiate a POR.
If the Digital Brownout Reset circuit is on, the POR circuit
has no effect.
DIGITAL BROWNOUT RESET
By configuring the device prior to entering Stop mode,
further power reductions can be achieved (while in Stop
mode). These power reductions include halting the
external clock into the device, configuring all digital I/O
pins as open drain with low output drive, disabling the ADC
The Digital Brownout Reset (DBOR) is enabled through
HCR1. If the conditions for proper POR are not met, the
DBOR can be used to ensure proper device operation. The
DBOR will hold the state of the device when the power
supply drops below the threshold level programmed in
HCR1, and then generate a reset when the supply rises
above the threshold level. Note that as the device is
released from reset and program execution begins, the
device current consumption may increase, which can
result in a power supply voltage drop, which may initiate
another brownout condition. Also, the DBOR comparison
is done against an analog reference; therefore, AVDD must
be within its valid operating range for DBOR to function.
buffer, disabling the internal V , and setting PDCON to
REF
0FFh to power down all peripherals.
In Stop mode, all digital pins retain their values.
POWER CONSUMPTION CONSIDERATIONS
The following suggestions will reduce current
consumption in the MSC120x devices:
The DBOR level should be chosen to match closely with
the application. That is, with a high external clock
frequency, the DBOR level should match the minimum
operating voltage range for the device or improper
operation may still occur.
1. Use the lowest supply voltage that will work in the
application for both AV and DV
.
DD
DD
2. Use the lowest clock frequency that will work in the
application.
3. Use Idle mode and the system clock divider
whenever possible. Note that the system clock
divider also affects the ADC clock.
ANALOG LOW-VOLTAGE DETECT
The MSC120x contain an analog low-voltage detect
circuit. When the analog supply drops below the value
programmed in LVDCON (SFR E7h), an interrupt is
generated, and/or the flag is set.
4. Avoid using 8051-compatible I/O mode on the I/O
ports. The internal pull-up resistors will draw current
when the outputs are low.
5. Use the delay line for Flash Memory control by
setting the FRCM bit in the FMCON register (SFR
EEh).
IDLE MODE
Idle mode is entered by setting the IDLE bit in the Power
Control register (PCON, 087h). In Idle mode, the CPU,
Timer0, Timer1, and USART are stopped, but all other
peripherals and digital pins remain active. The device can
be returned to active mode via an active internal or external
interrupt. This mode is typically used for reducing power
consumption between ADC samples.
6. Power down the internal oscillator in External Clock
mode by setting the PDICLK bit in the PDCON
register (SFR F1h).
7. Power down peripherals when they are not needed.
Refer to SFR PDCON, LVDCON, ADCON0, and
IDAC.
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Internal Oscillator
CLOCKS
In IOM, the CPU executes either in LF mode (if HCR2,
CLKSEL = 111) or high-frequency (HF) mode (if HCR2,
The MSC120x can operate in three separate clock modes:
Internal Oscillator mode (IOM), External Clock mode
(ECM), and Phase Lock Loop (PLL) mode. A block
diagram is shown in Figure 13. The clock mode for the
MSC120x is selected via the CLKSEL bits in HCR2. IO
low-frequency (LF) mode is the default mode for the
device.
CLKSEL = 110 and DV = 5.0V). In this mode, XIN must
DD
be grounded or tied to supply.
External Clock
In ECM (HCR2, CLKSEL = 011), the CPU can execute
from an external crystal, external ceramic resonator,
external clock, or external oscillator. If an external clock is
detected at startup, then the CPU will begin execution in
ECM after startup. If an external clock is not detected at
startup, then the device will revert to the mode shown in
Table 2.
Serial Flash Programming mode (SFPM) uses IO LF mode
(the HCR2 and CLKSEL bits have no effect). Table 2
shows the active clock mode for the various startup
conditions during User Application mode.
tOSC
STOP
Ω
100k
t
PLL/tIOM
tSYS
tCLK
Phase
Detector
XIN
Charge
Pump
VCO
SYSCLK
(1)
LF/HF
Mode Oscillator
Internal
PLL DAC
XOUT
PLLDIV
NOTE: (1) Disabled in PLL mode; therefore, an external resistor between XIN and XOUT is required.
Figure 13. Clock Block Diagram
Table 2. Active Clock Modes
(1)
STARTUP CONDITION
SELECTED CLOCK MODE
HCR2, CLKSEL2:0
ACTIVE CLOCK MODE (f
External Clock Mode
IO LF Mode
)
SYS
Active clock present at XIN
No clock present at XIN
N/A
External Clock Mode (ECM)
010
IO LF Mode
IO HF Mode
111
110
IO LF Mode
(2)
Internal Oscillator Mode (IOM)
N/A
IO HF Mode
Active 32.768kHz clock at XIN
No clock present at XIN
Active 32.768kHz clock at XIN
No clock present at XIN
PLL LF Mode
PLL LF Mode
PLL HF Mode
101
100
Nominal 50% of IO LF Mode
PLL HF Mode
(3)
PLL
Nominal 50% of IO HF Mode
(1)
(2)
(3)
Clock detection is only done at startup; refer to Serial Flash Programming Timing parameter t
XIN must not be left floating; it must be tied high or low or parasitic oscillation may occur.
in Figure 2.
RFD
PLL operation requires that both AV
and DV
are within their specified ranges.
DD
DD
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SBAS317E − APRIL 2004 − REVISED MAY 2006
PLL
XIN
In PLL mode (HCR2, CLKSEL = 101 or HCR2,
CLKSEL = 100), the CPU can execute from an external
32.768kHz crystal. This mode enables the use of a PLL
circuit that synthesizes the selected clock frequencies
(PLL LF mode or PLL HF mode). If an external clock is
detected at startup, then the CPU begins execution in PLL
mode after startup. If an external clock is not detected at
startup, then the device reverts to the mode shown in
Table 2. The status of the PLL can be determined by first
writing the PLLLOCK bit (enable) and then reading the
PLLLOCK status bit in the PLLH SFR.
C1
C2
XOUT
NOTE: Refer to the crystal manufacturer’s specification
for C1 and C2 values.
Figure 14. External Crystal Connection
The frequency of the PLL is preloaded with default
trimmed values. However, the PLL frequency can be
fine-tuned by writing to the PLLH and PLLL SFRs. The
equation for the PLL frequency is:
External Clock
XIN
PLL Frequency = ([PLLH:PLLL] + 1) • fOSC
where fOSC = 32.768kHz.
Figure 15. External Clock Connection
The default value for PLL LF mode is automatically loaded
into the PLLH and PLLL SFRs.
For different connections to external clocks, see Figure 14,
Figure 15, and Figure 16.
XIN
32pF
For PLL HF mode, the value of PLL[9:0] is automatically
doubled in hardware; however, since PLL[9:0] is writable,
it can also be modified by writing to the respective SFRs.
32.768kHz
XOUT
32pF
NOTE: Typical configuration is shown.
Figure 16. PLL Connection
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SBAS317E − APRIL 2004 − REVISED MAY 2006
D
D
Toggle SCK by setting and clearing the port pin.
SPI
Memory Write Pulse (WR) that is idle high.
Whenever an external memory write command
(MOVX) is executed, a pulse is seen on P3.6. This
method can be used only if CPOL is set to ‘1’.
The MSC120x implement a basic SPI interface that
includes the hardware for simple serial data transfers.
Figure 17 shows a block diagram of the SPI. The
peripheral supports master and slave modes, full duplex
data transfers, both clock polarities, both clock phases, bit
order, and slave select.
D
D
Memory Write Pulse toggle version. In this mode,
SCK toggles whenever an external write command
(MOVX) is executed.
The timing diagram for supported SPI data transfers is
shown in Figure 18.
T0_Out signal can be used as a clock. A pulse is
generated on SCK whenever Timer 0 expires. The
idle state of the signal is low, so this can be used
only if CPOL is cleared to ‘0’.
The I/O pins needed for data transfer are Data In (DIN),
Data Out (DOUT) and serial clock (SCK). The slave select
(SS) pin can also be used to control the output of data on
DOUT.
D
D
T0_Out toggle. SCK toggles whenever Timer 0
expires.
The DIN pin is used for shifting data in for both master and
slave modes.
T1_Out signal can be used as a clock. A pulse is
generated whenever Timer 1 expires. The idle state
of the signal is low, so this can be used only if CPOL
is cleared to ‘0’.
The DOUT pin is used for shifting data out for both master
and slave modes.
The SCK pin is used to synchronize the transfer of data for
both master and slave modes. SCK is always generated
by the master. The generation of SCK in master mode can
be done either in software (by simply toggling the port pin),
or by configuring the output on the SCK pin via PASEL
(SFR F2h). A list of the most common methods of
generating SCK follows, but the complete list of clock
sources can be found by referring to the PASEL SFR.
D
T1_Out toggle. SCK toggles whenever Timer 1
expires.
DOUT
SPI /I2C
Data Write
P1.2
DOUT
TX_CLK
SPICON
I2CCON
SS
P1.4
P3.6
SS
CNT_CLK
Logic
CNT INT
I2C INT
Counter
SCK/SCL
Start/Stop
Detect
Pad Control
SCK
I2C
Stretch
Control
P1.3
RX_CLK
DIN
SPI /I2C
Data Read
DIN
CLKS
(refer to PASEL, SFR F2h)
2
Figure 17. SPI/I C Block Diagram
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SBAS317E − APRIL 2004 − REVISED MAY 2006
SCK Cycle #
1
2
3
4
5
6
7
8
SCK (CPOL = 0)
SCK (CPOL = 1)
Sample Input
MSB
6
5
4
3
2
1
LSB
(CPHA = 0) Data Out
Sample Input
MSB
6
5
4
3
2
1
LSB
(CPHA = 1) Data Out
SS to Slave
Slave CPHA = 1 Transfer in Progress
Slave CPHA = 0 Transfer in Progress
2
1) SS Asserted
3
4
1
2) First SCK Edge
3) CNTIF Set (dependent on CPHA bit)
4) SS Negated
Figure 18. SPI Timing Diagram
The SS pin can be used to control the output of data on
DOUT when the MSC120x is in slave mode. The SS
function is enabled or disabled by the ESS bit of the
SPICON SFR. When enabled, the SS input of a slave
device must be externally asserted before a master device
can exchange data with the slave device. SS must be low
before data transactions and must stay low for the duration
of the transaction. When SS is high, data will not be shifted
into the shift register, nor will the counter increment. When
SPI is enabled, SS also controls the drive of the line DOUT
(P1.2). When SS is low in slave mode, the DOUT pin will
be driven and when SS is high, DOUT will be high
impedance.
Application Flow
This section explains the typical application usage flow of
SPI in master and slave modes.
Master Mode Application Flow
1. Configure the port pins.
2. Configure the SPI.
3. Assert SS to enable slave communication (if
applicable).
4. Write data to SPIDATA.
5. Generate eight SCKs.
6. Read the received data from SPIDATA.
The SPI generates interrupt ECNT (AIE.2) to indicate that
the transfer/reception of the byte is complete. The interrupt
goes high whenever the counter value is equal to 8
(indicating that eight SCKs have occurred). The interrupt
is cleared on reading or writing to the SPIDATA register.
During the data transfer, the actual counter value can be
read from the SPICON SFR.
Slave Mode Application Flow
1. Configure the ports pins.
2. Enable SS (if applicable).
3. Configure the SPI.
4. Write data to SPIDATA.
Power Down
5. Wait for the Count Interrupt (eight SCKs).
6. Read the data from SPIDATA.
The SPI is powered down by the PDSPI bit in the power
control register (PDCON). This bit needs to be cleared to
enable the SPI function. When the SPI is powered down,
pins P1.2, P1.3, P1.4, and P3.6 revert to general-purpose
I/O pins.
CAUTION:
If SPIDATA is not read before the next SPI
transaction, the ECNT interrupt will be removed
and the previous data will be lost.
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SBAS317E − APRIL 2004 − REVISED MAY 2006
2
(I2CCON.CNTSEL). This can be used for ACK/NACK
interrupt generation. For instance, the I2C interrupt can be
configured for 8-bit interrupt detection; on the eighth bit,
the interrupt is generated. During this interrupt, the clock
is stretched (SCL held low) if the DCS bit is set. The
interrupt can then be configured for 1-bit detection (which
terminates clock stretching). The ACK/NACK can be
written by the software, which will terminate clock
stretching. The next interrupt will be generated after the
ACK/NACK has been latched by the receiving device. The
interrupt is cleared on reading or writing to the I2CDATA
register. If I2CDATA is not read before the next data
transfer, the interrupt will be removed and the previous
data will be lost.
I C
The I/O pins needed for I2C transfer are serial clock (SCL)
and serial data (SDA—implemented by connecting DIN
and DOUT externally). The I2C transfer timing is shown in
Figure 19.
The MSC120x I2C supports:
2
1. Master or slave I C operation (control in software)
2. Standard or fast modes of transfer
3. Clock stretching
4. General call
When used in I2C mode, pins DIN (P1.3) and DOUT (P1.2)
should be tied together externally. The DIN pin should be
configured as an input pin and the DOUT pin should be
configured as open drain or standard 8051 by setting the
P1DDR (DOUT should be set high so that the bus is not
pulled low).
Master Operation
The source for the SCL is controlled in the PASEL register
or can be generated in software.
Transmit
The MSC120x I2C can generate two interrupts:
The serial data must be stable on the bus while SCL is
high. Therefore, the writing of serial data to I2CDATA must
be coordinated with the generation of the SCL, since SDA
transitions on the bus may be interpreted as a START or
STOP while SCL is high. The START and STOP
conditions on the bus must be generated in software. After
the serial data has been transmitted, the generation of the
ACK/NACK clock must be enabled by writing 0xFFh to
I2CDATA. This allows the master to read the state of
ACK/NACK.
2
1. I C interrupt for START/STOP interrupt (AIE.3)
2. CNT interrupt for bit counter interrupt (AIE.2)
The START/STOP interrupt is generated when a START
condition or STOP condition is detected on the bus. The bit
counter generates an interrupt on a complete (8-bit) data
transfer and also after the transfer of the ACK/NACK.
The bit counter for serial transfer is always incremented on
the falling edge of SCL and can be reset by reading or
writing to I2CDATA (SFR 9Bh) or when a START/STOP
condition is detected. The bit counter can be polled or used
as an interrupt. The bit counter interrupt occurs when the
bit counter value is equal to 8, indicating that eight bits of
data have been transferred. I2C mode also allows for
interrupt generation on one bit of data transfer
Receive
The serial data is latched into the receive buffer on the
rising edge of SCL. After the serial data has been received,
ACK/NACK is generated by writing 0x7Fh (for ACK) or
0xFFh (for NACK) to I2CDATA.
SDA
1−7
8
9
1−7
8
9
1−7
8
9
SCL
S
P
START
Condition(1)
ADDRESS(2)
R/W(2) ACK(3)
DATA(2)
ACK(3)
DATA(2)
ACK(3)
STOP
Condition(4)
NOTES: (1) Generate in software; write 0x7F to I2CDATA.
(2) I2CDATA register.
(3) Generate in software. Can enable bit count = 1 interrupt prior to ACK/NACK for interrupt use.
Generate ACK by writing 0x7F to I2CDATA; generate NACK by writing 0xFF to I2CDATA.
(4) Generate in software; write 0xFF to I2CDATA.
2
Figure 19. Timing Diagram for I C Transmission and Reception
32
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SBAS317E − APRIL 2004 − REVISED MAY 2006
precaution, a lock feature can be activated through HCR0,
which disables erase/write operation to 4kB of Program
Flash Memory or the entire Program Flash Memory in
UAM.
Slave Operation
Slave operation is supported, but address recognition,
R/W determination, and ACK/NACK must be done under
software control. The Disable Clock Stretch (DCS) bit can
be set to disable clock stretching. When the DCS bit is set,
the device will no longer stretch the clock and will not
generate interrupts. This bit can be used to disable clock
stretch interrupts when there is no address match. This bit
is automatically cleared when a start or repeated start
condition occurs.
FLASH MEMORY
The page size for Flash memory is 64 bytes. The
respective page must be erased before it can be written to,
regardless of whether it is mapped to Program memory or
Data memory space. The MSC120x use a memory
addressing scheme that separates Program Memory
(FLASH/ROM) from Data Memory (FLASH/RAM).
Addressing of program and data segments can overlap
since they are accessed by different instructions.
Transmit
Once address recognition, R/W determination, and
ACK/NACK are complete, the serial data to be transferred
can be written to I2CDATA. The data is automatically
shifted out based on the master SCL. After data
transmission, CNTIF is generated and SCL is stretched by
the MSC120x until the I2CDATA register is written with a
0xFFh. The ACK/NACK from the master can then be read.
The MSC120x have three hardware configuration
registers (HCR0, HCR1, and HCR2) that are
programmable only during Flash Memory Programming
mode.
The MSC120x allow the user to partition the Flash Memory
between Program Memory and Data Memory. For
instance, the MSC120xY3 contain 8kB of Flash Memory
on-chip. Through the hardware configuration registers, the
user can define the partition between Program Memory
(PM) and Data Memory (DM), as shown in Table 3,
Table 4, and Figure 20. The MSC120x families offer two
memory configurations.
Receive
Once address recognition, R/W determination, and
ACK/NACK are complete, I2CDATA must be written with
0xFFh to enable data reception. Upon completion of the
data shift, the MSC120x generates the CNT interrupt and
stretches SCL. Received data can then be read from
I2CDATA. After the serial data has been received,
ACK/NACK is generated by writing 0x7Fh (for ACK) or
0xFFh (for NACK) to I2CDATA. The write to I2CDATA
clears the CNT interrupt and clock stretch.
Table 3. Flash Memory Partitioning
HCR0
DFSEL
00
MSC120xY2
DM
MSC120xY3
DM
MEMORY MAP
PM
2kB
2kB
3kB
PM
4kB
6kB
7kB
2kB
2kB
1kB
4kB
2kB
1kB
The MSC120x contain on-chip SFR, Flash Memory,
Configuration Memory, Scratchpad SRAM Memory, and
Boot ROM. The SFR registers are primarily used for
control and status. The standard 8051 features and
additional peripheral features of the MSC120x are
controlled through the SFR. Reading from an undefined
SFR returns zero. Writing to undefined SFR registers is not
recommended and will have indeterminate effects.
01
10
11
(default)
4kB
0kB
8kB
0kB
Table 4. Flash Memory Partitioning Addresses
HCR0
DFSEL
00
MSC120xY2
MSC120xY3
Flash Memory is used for both Program Memory and Data
Memory; however, program execution can only occur from
Program Memory. Program/Data Memory partition size is
selectable. The partition size is set through HCR0 (in the
Configuration Memory), which is programmed serially.
Both Program and Data Flash Memory are erasable and
writable (programmable) in UAM. Erase and write timing
of Flash Memory is controlled in the Flash Memory Timing
Control register (FTCON, SFR 0EFh). As an added
PM
DM
PM
DM
0000−07FF
0000−07FF
0000−0BFF
0400−0BFF
0400−0BFF
0400−07FF
0000−0FFF
0000−17FF
0000−1BFF
0400−13FF
0400−0BFF
0400−07FF
01
10
11
(default)
0000−0FFF
0000
0000−1FFF
0000
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Program
Memory
Data
Memory
Serial Flash
Programming
Mode
User
Application
Mode
FFFFh
FFFFh
Unused
Configuration
Memory
FC00h
1K Internal Boot ROM
F800h
Address
Address(1)
807Fh
8040h
8000h
7Fh
40h
00h
UAM: Read Only
SFPM: Read Only
Unused
Unused
UAM: Read Only
SFPM: Read/Write
1FFFh, 8k (Y3)
13FFh, 5k (Y3)
On−Chip
Flash
On−Chip
Flash
0FFFh, 4k (Y2)
0000h, 0k
0BFFh, 3k (Y2)
03FFh, 1k
NOTE: (1) Can be accessed using CADDR
or the faddr_data_read Boot ROM routine.
Figure 20. Memory Map
It is important to note that the Flash Memory is readable
and writable (depending on the MXWS bit in the MWS
SFR) through the MOVX instruction when configured as
either Program or Data Memory. This flexibility means that
the device can be partitioned for maximum Flash Program
Memory size (no Flash Data Memory) and Flash Program
Memory can be used as Flash Data Memory. However,
this usage may lead to undesirable behavior if the PC
points to an area of Flash Program Memory that is being
used for data storage. Therefore, it is recommended to use
Flash partitioning when Flash Memory is used for data
storage. Flash partitioning prohibits execution of code
from Data Flash Memory. Additionally, the Program
Memory erase/write can be disabled through hardware
configuration bits (HCR0), while still providing access
(read/write/erase) to Data Flash Memory.
CONFIGURATION MEMORY
The MSC120x Configuration Memory consists of 128
bytes of memory. In UAM, all Configuration Memory is
readable using the faddr_data_read Boot ROM routine or
CADDR register, but none of the Configuration Memory is
writable. In SFPM, all Configuration Memory is readable,
but only the lower 64 bytes (8000h−803Fh) are writable;
the upper 64 bytes (8040h−807Fh) are not writable.
Note that reading/writing configuration memory in SFPM
requires
16-bit
addressing;
whereas,
reading
configuration memory in UAM requires only 8-bit
addressing.
Lower 64 Bytes
Note that the three hardware configuration registers
(HCR0, HCR1, and HCR2) reside in the lower 64 bytes of
Configuration Memory and are located in SFPM at
addresses 0803Fh, 0803Eh, and 0803Dh, respectively.
Therefore, care should be taken when writing to
Configuration Memory so that user parameters are not
written into these locations.
The effect of memory mapping on Program and Data
Memory is straightforward. The Program Memory is
decreased in size from the top of Flash Memory. To
maintain compatibility with the MSC121x, the Flash Data
Memory maps to addresses 0400h. Therefore, access to
Data Memory (through MOVX) will access Flash Memory
for the addresses shown in Table 4.
Also note that if the Enable Program Memory Access bit
(HCR0.7) is cleared, Configuration Memory cannot be
changed unless all memory has been cleared with the
Mass Erase command.
Data Memory
The MSC120x has on-chip Flash Data Memory, which is
readable and writable (depending on the Memory Write
Select register) during normal operation (full VDD range).
This memory is mapped into the external Data Memory
space, which requires the use of the MOVX instruction to
program.
Upper 64 Bytes
Information such as device trim values and device serial
number are located in the upper 64 bytes of Configuration
Memory. The locations 08050h through 08053h contain a
unique 4-byte serial number. The location 8054h contains
the temperature sensor correction value (refer to
application note SBAA126, available for download from
www.ti.com). None of these memory locations can be
altered.
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Program Status Word register (PSW; 0D0h) in the SFR
area described below. The 16 bytes immediately above
the R0−R7 registers are bit-addressable, so any of the 128
bits in this area can be directly accessed using
bit-addressable instructions.
REGISTER MAP
Figure 21 illustrates the Register Map. It is entirely
separate from the Program and Data Memory areas
discussed previously. A separate class of instructions is
used to access the registers. There are 256 potential
register locations. In practice, the MSC120x have 256
bytes of Scratchpad RAM and up to 128 SFRs. This is
possible since the upper 128 Scratchpad RAM locations
can only be accessed indirectly. Thus, a direct reference
to one of the upper 128 locations must be an SFR access.
Direct RAM is reached at locations 0 to 7Fh (0 to 127).
7Fh
Direct
RAM
2Fh
2Eh
7F
77
7E
76
6E
66
5E
56
4E
46
3E
36
2E
26
1E
16
0E
06
7D 7C 7B
75 74 73
6D 6C 6B
65 64 63
5D 5C 5B
55 54 53
4D 4C 4B
45 44 43
3D 3C 3B
35 34 33
2D 2C 2B
25 24 23
1D 1C 1B
15 14 13
0D 0C 0B
05 04 03
7A
72
6A
62
5A
52
4A
42
3A
32
2A
22
1A
12
0A
02
79
71
69
61
59
51
49
41
39
31
29
21
19
11
09
01
78
70
68
60
58
50
48
40
38
30
28
20
18
10
08
00
255
255
128
FFh
80h
FFh
2Dh 6F
Direct
Special Function
Registers
Indirect
RAM
2Ch
2Bh
2Ah
29h
28h
27h
67
5F
57
4F
47
3F
128
127
80h
7Fh
SFR Registers
Direct
RAM
0
00h
Scratchpad
RAM
26h 37
Figure 21. Register Map
2F
27
1F
17
0F
07
25h
24h
23h
22h
21h
SFRs are accessed directly between 80h and FFh (128 to
255). The RAM locations between 128 and 255 can be
reached through an indirect reference to those locations.
Scratchpad RAM is available for general-purpose data
storage. Within the 128 bytes of RAM, there are several
special-purpose areas.
20h
1Fh
Bank 3
Bit Addressable Locations
18h
17h
In addition to direct register access, some individual bits
are also accessible. These are individually addressable
bits in both the RAM and SFR area. In the Scratchpad
RAM area, registers 20h to 2Fh are bit-addressable. This
provides 128 (16 × 8) individual bits available to software.
A bit access is distinguished from a full-register access by
the type of instruction. In the SFR area, any register
location ending in a 0h or 8h is bit-addressable. Figure 22
shows details of the on-chip RAM addressing including the
locations of individual RAM bits.
Bank 2
Bank 1
Bank 0
10h
0Fh
08h
07h
00h
MSB
LSB
Working Registers
Figure 22. Scratchpad Register Addressing
As part of the lower 128 bytes of RAM, there are four banks
of Working Registers, as shown in Figure 20. The Working
Registers are general-purpose RAM locations that can be
addressed in a special way. They are designated R0
through R7. Since there are four banks, the currently
selected bank will be used by any instruction using R0−R7.
This design allows software to change context by simply
switching banks. Bank access is controlled via the
Thus, an instruction can designate the value stored in R0
(for example) to address the upper RAM. The 16 bytes
immediately
above
the
these
registers
are
bit-addressable, so any of the 128 bits in this area can be
directly accessed using bit-addressable instructions.
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Stack
Program Memory
Another use of the Scratchpad area is for the
programmer’s stack. This area is selected using the Stack
Pointer (SP, SFR 81h). Whenever a call or interrupt is
invoked, the return address is placed on the Stack. It also
is available to the programmer for variables, etc., since the
Stack can be moved and there is no fixed location within
the RAM designated as Stack. The Stack Pointer defaults
to 07h on reset and the user can then move it as needed.
The SP will point to the last used value. Therefore, the next
value placed on the Stack is put at SP + 1. Each PUSH or
CALL increments the SP by the appropriate value and
each POP or RET decrements it.
After reset, the CPU begins execution from Program
Memory location 0000h. If enabled, the Boot ROM will
appear from address F800h to FFFFh.
Boot ROM
There is a 1kB Boot ROM that controls operation during
serial programming. Additionally, the Boot ROM routines
shown in Table 5 can be accessed during the user mode,
if it is enabled. When enabled, the Boot ROM routines will
be located at memory addresses F800h−FBFFh during
user mode.
Table 5. MSC120x Boot ROM Routines
HEX
ADDRESS
ROUTINE
sfr_rd
C DECLARATIONS
char sfr_rd(void);
DESCRIPTION
(1)
Return SFR value pointed to by CADDR
F802
F805
FBD8
(1)
Write to SFR pointed to by CADDR
sfr_wr
void sfr_wr(char d);
void monitor_isr() interrupt 6;
monitor_isr
Push registers and call cmd_parser
See application note SBAA076, Programming the
MSC1210, available at www.ti.com.
FBDA
cmd_parser
void cmd_parser(void);
FBDC
FBDE
FBE0
FBE2
FBE4
FBE6
FBE8
FBEA
FBEC
FBEE
FBF0
FBF2
FBF4
FBF6
FBF8
FBFA
FBFC
FBFE
put_string
void put_string(char code *string);
char page_erase(int faddr, char fdata, char fdm);
Assembly only; DPTR = address, ACC = data
char write_flash_chk(int faddr, char fdata, char fdm);
void write_flash_byte(int faddr, char fdata);
char faddr_data_read(char faddr);
char data_x_c_read(int faddr, char fdm);
void tx_byte(char);
Output string
page_erase
write_flash
write_flash_chk
write_flash_byte
faddr_data_read
data_x_c_read
tx_byte
Erase flash page
(2)
Flash write
Write flash byte, verify
(2)
Write flash byte
Read byte from Configuration Memory
Read xdata or code byte
Send byte to USART0
tx_hex
void tx_hex(char);
send hex value to USART0
putx
void putx(void);
send “x” to USART0 on R7 = 1
Read byte from USART0
rx_byte
char rx_byte(void);
rx_byte_echo
rx_hex_echo
rx_hex_dbl_echo
rx_hex_word_echo
autobaud
char rx_byte_echo(void);
Read and echo byte on USART0
Read and echo hex on USART0
Read int as hex and echo: USART0
Read int reversed as hex and echo: USART0
char rx_hex_echo(void);
int_rx_hex_dbl_echo(void);
int_rx_hex_word_echo(void);
void autobaud(void);
(3)
Set USART0 baud rate after CR
Output 1 space to USART0
Output CR, LF to USART0
received
putspace1
void putspace1(void);
putcr
void putcr(void);
(1)
CADDR must be set prior to using these routines.
(2)
(3)
MWS register (SFR 8Fh) defines Data Memory or Program Memory write.
SFR registers CKCON and TCON must be initialized: CKCON = 0x10 and TCON = 0x00.
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SBAS317E − APRIL 2004 − REVISED MAY 2006
The recommended baud rate range for SFPM is 2400 to
19200. If communication errors occur, decreasing the
baud rate may improve communication performance.
Serial Flash Programming Mode
Serial Flash Programming mode (SFPM) is used to
download Program and Data Memory into the onboard
Flash Memory on the MSC120x. It is initiated by holding
the P1.0/PROG pin low during the reset cycle, as shown
in Figure 23. After the reset cycle, the host can
communicate with the MSC120x through USART0. Refer
to application note SBAA076 (www.ti.com) for serial
programming commands and protocol.
Also note that in SFPM, the Brownout Detect circuit is
disabled and AV
must be > 2.0V.
DD
INTERRUPTS
The MSC120x use a three-priority interrupt system. As
shown in Table 6, each interrupt source has an
independent priority bit, flag, interrupt vector, and enable
(except that nine interrupts share the Auxiliary Interrupt,
AI, at the highest priority). In addition, interrupts can be
globally enabled or disabled. The interrupt structure is
compatible with the original 8051 family. All of the standard
interrupts are available.
In SFPM, the MSC120x uses the internal oscillator in low
frequency mode (that is, the external clock is disabled).
The internal oscillator frequency is affected by the power
supply voltage and device temperature. Therefore, in
order to avoid losing communication during programming,
it is important to have a stable power supply and
temperature environment during serial communication.
MSC120x
Reset Circuit (or VDD
)
RST
AVDD
DVDD
P1.0/PROG
P3.1 TXD
Host PC
RS232
Serial
Port 0
or
P3.0 RXD
Transceiver
Serial Terminal
NOTE: Serial programming is selected when P1.0/PROG is low at reset.
Figure 23. Serial Flash Programming Mode
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Table 6. Interrupt Summary
INTERRUPT
PRIORITY
CONTROL
ADDR
NUM
INTERRUPT/EVENT
PRIORITY
FLAG
ENABLE
High
0
AV
DD
Low Voltage Detect
33h
6
ALVDIP (AIPOL.1)(1)
EALV (AIE.1)(1)
N/A
2
Count (SPI/I C)
33h
33h
33h
33h
33h
33h
03h
0Bh
13h
1Bh
6
6
6
6
6
6
0
1
2
3
0
0
0
0
0
0
1
2
3
4
CNTIP (AIPOL.2)(1)
I2CIP (AIPOL.3)(1)
MSECIP (AIPOL.4)(1)
ADCIP (AIPOL.5)(1)
SUMIP (AIPOL.6)(1)
SECIP (AIPOL.7)(1)
IE0 (TCON.1)(2)
ECNT (AIE.2)(1)
EI2C (AIE.3)(1)
EMSEC (AIE.4)(1)
EADC (AIE.5)(1)
ESUM (AIE.6)(1)
ESEC (AIE.7)(1)
EX0 (IE.0)(4)
N/A
N/A
2
I C Start/Stop
Milliseconds Timer
ADC
N/A
N/A
Summation Register
Seconds Timer
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
N/A
N/A
PX0 (IP.0)
PT0 (IP.1)
PX1 (IP.2)
PT1 (IP.3)
TF0 (TCON.5)(3)
ET0 (IE.1)(4)
IE1 (TCON.3)(2)
EX1 (IE.2)(4)
TF1 (TCON.7)(3)
ET1 (IE.3)(4)
RI_0 (SCON0.0)
TI_0 (SCON0.1)
Serial Port 0
23h
4
5
ES0 (IE.4)(4)
PS0 (IP.4)
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
Watchdog
43h
4Bh
53h
5Bh
63h
8
6
7
8
9
IE2 (EXIF.4)
IE3 (EXIF.5)
EX2 (EIE.0)(4)
EX3 (EIE.1)(4)
EX4 (EIE.2)(4)
EX5 (EIE.3)(4)
EWDI (EIE.4)(4)
PX2 (EIP.0)
PX3 (EIP.1)
PX4 (EIP.2)
PX5 (EIP.3)
PWDI (EIP.4)
9
10
11
12
IE4 (EXIF.6)
IE5 (EXIF.7)
10
WDTI (EICON.3)
Low
(1)
(2)
(3)
(4)
These interrupts set the AI flag (EICON.4) and are enabled by EAI (EICON.5).
If edge-triggered, cleared automatically by hardware when the service routine is vectored to. If level-triggered, the flag follows the state of the pin.
Cleared automatically by hardware when interrupt vector occurs.
Globally enabled by EA (IE.7).
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Hardware Configuration Register 0 (HCR0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CADDR 3Fh
EPMA
PML
RSL
EBR
EWDR
1
DFSEL1
DFSEL0
NOTE: HCR0 is programmable only in SFPM, but can be read in UAM using the faddr_data_read Boot ROM routine.
EPMA
Enable Program Memory Access (Security Bit).
bit 7
0: After reset in programming modes, Flash Memory can only be accessed in UAM until a mass erase is done.
1: Fully Accessible (default)
PML
Program Memory Lock (PML has priority over RSL).
0: Enable read and write for Program Memory in UAM.
1: Enable Read-Only mode for Program Memory in UAM (default).
bit 6
RSL
bit 5
Reset Sector Lock. The reset sector can be used to provide another method of Flash Memory programming, which
allows Program Memory updates without changing the jumpers for in-circuit code updates or program development.
The code in this boot sector would then provide the monitor and programming routines with the ability to jump into
the main Flash code when programming is finished.
0: Enable Reset Sector Writing
1: Enable Read-Only mode for reset sector (4kB) (default). Same effect as PML for the MSC120xY2.
EBR
Enable Boot ROM. Boot ROM is 1kB of code located in ROM, not to be confused with the 4kB Boot Sector located
bit 4
in Flash Memory.
0: Disable Internal Boot ROM
1: Enable Internal Boot ROM (default)
EWDR
Enable Watchdog Reset.
bit 3
0: Disable Watchdog Reset
1: Enable Watchdog Reset (default)
DFSEL1−0 Data Flash Memory Size (see Table 3).
bits 1−0
00: 4kB Data Flash Memory (MSC120xY3 only)
01: 2kB Data Flash Memory
10: 1kB Data Flash Memory
11: No Data Flash Memory (default)
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Hardware Configuration Register 1 (HCR1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CADDR 3Eh
DBSEL3
DBSEL2
DBSEL1
DBSEL0
1
DDB
1
1
NOTE: HCR1 is programmable only in SFPM, but can be read in UAM using the faddr_data_read Boot ROM routine.
DBSEL3−0 Digital Supply Brownout Level Select. The values listed are nominal. The actual value will vary depending on
device clock frequency and supply voltage. For high clock frequencies, the variation could be on the order of 10%
below the nominal value.
bits 7−4
0000: 4.6V
0001: 4.2V
0010: 3.8V
0011: 3.6V
0100: 3.3V
0101: 3.1V
0110: 2.9V
0111: 2.7V
1000: 2.6V
1001: Reserved
1010: Reserved
1011: Reserved
1100: Reserved
1101: Reserved
1110: Reserved
1111: Reserved
DDB
Disable Digital Brownout Detection.
0: Enable Digital Brownout Detection
1: Disable Digital Brownout Detection (default)
bit 2
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Hardware Configuration Register 2 (HCR2)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CADDR 3Dh
0
0
0
0
0
CLKSEL2
CLKSEL1
CLKSEL0
NOTE: HCR2 is programmable only in SFPM, but can be read in UAM using the faddr_data_read Boot ROM routine.
CLKSEL2−1 Clock Select.
bits 2−0
000: Reserved
001: Reserved
010: Reserved
011: External Clock Mode
100: PLL High-Frequency (HF) Mode
101: PLL Low-Frequency (LF) Mode
110: Internal Oscillator High-Frequency (HF) Mode
111: Internal Oscillator Low-Frequency (LF) Mode
NOTE: Clock status can be verified reading PLLH in UAM.
Configuration Memory Programming
Hardware Configuration Memory can be changed only in Serial Flash Programming mode (SFPM).
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Table 7. Special Function Registers
ADDRESS REGISTER BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RESET VALUE
80h
81h
82h
83h
84h
85h
86h
87h
88h
SP
07h
00h
00h
00h
00h
00h
30h
00h
DPL0
DPH0
DPL1
DPH1
DPS
0
0
0
0
0
0
0
SEL
IDLE
IT0
PCON
TCON
TMOD
SMOD
TF1
0
1
1
GF1
IE1
GF0
IT1
STOP
IE0
TR1
TF0
TR0
−−−−−−−−−−−−−−− Timer 1 −−−−−−−−−−−−−−−
−−−−−−−−−−−−−−− Timer 0 −−−−−−−−−−−−−−−
89h
00h
GATE
C/T
M1
M0
GATE
C/T
M1
M0
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
TL0
00h
00h
00h
00h
01h
00h
TL1
TH0
TH1
CKCON
MWS
P1
0
0
0
0
0
0
T1M
0
T0M
0
MD2
0
MD1
0
MD0
MXWS
P1.7
INT5
P1.6
INT4
P1.5
INT3
P1.4
INT2/SS
P1.3
DIN
P1.2
DOUT
P1.1
P1.0
PROG
90h
FFh
08h
91h
92h
93h
94h
95h
96h
97h
98h
99h
EXIF
IE5
IE4
IE3
IE2
1
0
0
0
CADDR
CDATA
00h
00h
SCON0
SBUF0
SM0_0
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
00h
00h
SPICON
I2CCON
SBIT3
SBIT3
SBIT2
SBIT2
SBIT1
SBIT1
SBIT0
SBIT0
ORDER
STOP
CPHA
START
ESS
DCS
CPOL
CNTSEL
9Ah
9Bh
00h
00h
SPIDATA
I2CDATA
9Ch
9Dh
9Eh
9Fh
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AIPOL
PAI
SECIP
0
SUMIP
0
ADCIP
0
MSECIP
0
I2CIP
PAI3
EI2C
I2C
CNTIP
PAI2
ALVDIP
PAI1
0
00h
00h
00h
00h
00h
PAI0
0
AIE
ESEC
SEC
EA
ESUM
SUM
0
EADC
ADC
0
EMSEC
MSEC
ES0
ECNT
CNT
EALV
ALVD
ET0
AISTAT
IE
0
ET1
EX1
EX0
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Table 7. Special Function Registers (continued)
ADDRESS REGISTER BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RESET VALUE
AAh
ABh
ACh
ADh
AEh
AFh
P1DDRL
P1DDRH
P3
P13H
P17H
P3.7
P13L
P17L
P3.6
P12H
P16H
P3.5
P12L
P16L
P11H
P15H
P11L
P15L
P10H
P14H
P10L
P14L
00h
00h
P3.4
T0
P3.3
INT1
P3.2
INT0
P3.1
TXD0
P3.0
RXD0
B0h
FFh
SCK/SCL/CLKS T1
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
D2h
D3h
D4h
D5h
D6h
P3DDRL
P3DDRH
IDAC
P33H
P37H
P33L
P37L
P32H
P36H
P32L
P36L
P31H
P35H
P31L
P35L
P30H
P34H
P30L
P34L
00h
00h
00h
IP
1
0
0
PS0
PT1
PX1
PT0
PX0
80h
EWU
EWUWDT
DIV2
EWUEX1
DIV1
EWUEX0
DIV0
00h
00h
SYSCLK
0
0
DIVMOD1
DIVMOD0
0
PSW
OCL
OCM
OCH
GCL
GCM
GCH
CY
AC
F0
RS1
RS0
OV
F1
P
00h
00h
00h
00h
5Ah
ECh
5Fh
LSB
MSB
MSB
LSB
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Table 7. Special Function Registers (continued)
ADDRESS REGISTER BIT 7
BIT 6
INP2
1
BIT 5
INP1
EAI
BIT 4
INP0
AI
BIT 3
INN3
WDTI
BIT 2
INN2
0
BIT 1
INN1
0
BIT 0
INN0
0
RESET VALUE
01h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
ECh
EDh
EEh
EFh
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
ADMUX
EICON
INP3
0
40h
(1)
(1)
ADRESL
ADRESM
ADRESH
LSB
00h
(1)
(1)
(1)
MSB
00h
(1)
MSB
00h
ADCON0
ADCON1
ADCON2
ADCON3
ACC
BOD
POL
EVREF
SM1
VREFH
SM0
EBUF
—
PGA2
CAL2
DR2
PGA1
CAL1
DR1
PGA0
CAL0
DR0
30h
OF_UF
DR7
00h
DR6
DR5
DR4
DR3
0
1Bh
0
0
0
0
DR10
ACC.2
SHF2
DR9
DR8
06h
ACC.7
SSCON1
ACC.6
SSCON0
ACC.5
SCNT2
ACC.4
SCNT1
ACC.3
SCNT0
ACC.1
SHF1
ACC.0
SHF0
LSB
00h
SSCON
SUMR0
SUMR1
SUMR2
SUMR3
ODAC
00h
00h
00h
00h
MSB
00h
00h
LVDCON
EIE
ALVDIS
0
1
0
0
0
1
0
1
0
ALVD3
ALVD2
ALVD1
EX3
ALVD0
EX2
8Fh
1
0
0
EWDI
EX5
0
EX4
0
E0h
HWPC0
HWPC1
HWVER
0
0
DEVICE
0
MEMORY
0
0000_00xxb
20h
0
0
FMCON
FTCON
B
0
PGERA
FER2
0
FRCM
FER0
0
BUSY
FWR2
SPM
FPM
02h
A5h
00h
6Fh
00h
FER3
FER1
FWR3
FWR1
FWR0
PDCON
PASEL
PDICLK
PSEN4
PDIDAC
PSEN3
PDI2C
0
PDADC
PSEN0
PDWDT
0
PDST
0
PDSPI
0
PSEN2
PSEN1
(2)
(2)
PLLL
PLL7
CKSTAT2
0
PLL6
PLL5
PLL4
PLL3
PLL2
PLL1
PLL0
xxh
xxh
PLLH
CKSTAT1
FREQ6
0
CKSTAT0
FREQ5
0
PLLLOCK
FREQ4
0
0
0
PLL9
PLL8
ACLK
FREQ3
0
FREQ2
0
FREQ1
0
FREQ0
RSTREQ
PX2
03h
SRST
0
00h
E0h
7Fh
7Fh
03h
9Fh
0Fh
63h
00h
EIP
1
1
1
PWDI
PX5
PX4
PX3
SECINT
MSINT
USEC
MSECL
MSECH
HMSEC
WDTCON
WRT
WRT
0
SECINT6
MSINT6
0
SECINT5
MSINT5
FREQ5
MSECL5
MSECH5
HMSEC5
RWDT
SECINT4
MSINT4
FREQ4
MSECL4
MSECH4
HMSEC4
WDCNT4
SECINT3
MSINT3
FREQ3
MSECL3
MSECH3
HMSEC3
WDCNT3
SECINT2
MSINT2
FREQ2
MSECL2
MSECH2
HMSEC2
WDCNT2
SECINT1
MSINT1
FREQ1
MSECL1
MSECH1
HMSEC1
WDCNT1
SECINT0
MSINT0
FREQ0
MSECL0
MSECH0
HMSEC0
WDCNT0
MSECL7
MSECH7
HMSEC7
EWDT
MSECL6
MSECH6
HMSEC6
DWDT
(1)
For the MSC1200/01, the ADC result is contained in ADRESH, ADRESM, and ADRESL. For the MSC1202, the ADC result is contained in
ADRESM and ADRESL (that is, shifted right one byte) and the MSB is sign-extended (Bipolar mode) or zero-padded (Unipolar mode) in
ADRESH. Therefore, when migrating between the MSC1200/01 and MSC1202, the ADC result calculation must be adjusted accordingly. For
all devices, the ADC interrupt is cleared by reading ADRESL.
(2)
Dependent on active clock mode.
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Table 8. Special Function Register Cross Reference
POWER
AND
CLOCKS
SERIAL
COMM.
TIMER
FLASH
ADC
COUNTERS MEMORY DACS
SFR
ADDRESS FUNCTIONS
CPU
X
INTERRUPTS PORTS
SP
81h
Stack Pointer
DPL0
DPH0
DPL1
DPH1
DPS
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
93h
94h
98h
99h
Data Pointer Low 0
Data Pointer High 0
Data Pointer Low 1
Data Pointer High 1
Data Pointer Select
Power Control
X
X
X
X
X
PCON
TCON
TMOD
TL0
X
Timer/Counter Control
Timer Mode Control
Timer0 LSB
X
X
X
X
X
X
X
X
X
X
TL1
Timer1 LSB
TH0
Timer0 MSB
TH1
Timer1 MSB
CKCON
MWS
P1
Clock Control
X
X
Memory Write Select
Port 1
X
EXIF
External Interrupt Flag
Configuration Address
Configuration Data
Serial Port 0 Control
Serial Data Buffer 0
SPI Control
X
CADDR
CDATA
SCON0
SBUF0
SPICON
I2CCON
SPIDATA
I2CDATA
AIPOL
PAI
X
X
X
X
X
X
X
X
X
X
X
X
9Ah
9Bh
2
I C Control
SPI Data
2
I C Data
A4h
A5h
A6h
A7h
A8h
AEh
AFh
B0h
B3h
B4h
B5h
B8h
C6h
C7h
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
Auxiliary Interrupt Poll
Pending Auxiliary Interrupt
Auxiliary Interrupt Enable
Auxiliary Interrupt Status
Interrupt Enable
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
AIE
AISTAT
IE
P1DDRL
P1DDRH
P3
Port 1 Data Direction Low
Port 1 Data Direction High
Port 3
P3DDRL
P3DDRH
IDAC
Port 3 Data Direction Low
Port 3 Data Direction High
Current DAC
X
X
IP
Interrupt Priority
X
X
EWU
Enable Wake Up
X
X
SYSCLK
PSW
System Clock Divider
X
X
X
Program Status Word
X
OCL
ADC Offset Calibration Low Byte
ADC Offset Calibration Mid Byte
ADC Offset Calibration High Byte
ADC Gain Calibration Low Byte
ADC Gain Calibration Mid Byte
ADC Gain Calibration High Byte
ADC Input Multiplexer
Enable Interrupt Control
X
X
X
X
X
X
X
X
OCM
OCH
GCL
GCM
GCH
ADMUX
EICON
X
X
X
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Table 8. Special Function Register Cross Reference (continued)
POWER
AND
CLOCKS
SERIAL
COMM.
TIMER
FLASH
ADC
COUNTERS MEMORY DACS
SFR
ADDRESS FUNCTIONS
ADC Results Low Byte
CPU
INTERRUPTS PORTS
ADRESL
ADRESM
ADRESH
ADCON0
ADCON1
ADCON2
ADCON3
ACC
D9h
DAh
DBh
DCh
DDh
DEh
DFh
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
EEh
EFh
F0h
F1h
F2h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
X
X
X
X
X
X
X
ADC Results Middle Byte
ADC Results High Byte
ADC Control 0
ADC Control 1
ADC Control 2
ADC Control 3
Accumulator
X
X
X
X
X
X
SSCON
SUMR0
SUMR1
SUMR2
SUMR3
ODAC
Summation/Shifter Control
Summation 0
X
X
X
X
X
X
Summation 1
Summation 2
Summation 3
Offset DAC
LVDCON
EIE
Low Voltage Detect Control
Extended Interrupt Enable
Hardware Product Code 0
Hardware Product Code 1
Hardware Version
Flash Memory Control
Flash Memory Timing Control
Second Accumulator
Power Down Control
PSEN/ALE Select
Phase Lock Loop Low
Phase Lock Loop High
Analog Clock
X
X
HWPC0
HWPC1
HWVER
FMCON
FTCON
B
X
X
X
X
X
X
PDCON
PASEL
PLLL
X
X
X
X
X
X
X
X
X
X
X
PLLH
ACLK
SRST
System Reset
X
EIP
Extended Interrupt Priority
Seconds Interrupt
Milliseconds Interrupt
One Microsecond
One Millisecond Low
One Millisecond High
One Hundred Millisecond
Watchdog Timer
X
X
X
SECINT
MSINT
USEC
X
X
X
X
X
X
X
X
X
X
MSECL
MSECH
HMSEC
WDTCON
X
HCR0
HCR1
HCR2
3Fh
3Eh
3Dh
Hardware Configuration Reg. 0
Hardware Configuration Reg. 1
Hardware Configuration Reg. 2
X
X
X
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Stack Pointer (SP)
7
6
5
4
3
2
1
0
Reset Value
SFR 81h
SP.7
SP.6
SP.5
SP.4
SP.3
SP.2
SP.1
SP.0
07h
SP.7−0
Stack Pointer. The stack pointer identifies the location where the stack will begin. The stack pointer is incremented before
bits 7−0 every PUSH or CALL operation and decremented after each POP or RET/RETI. This register defaults to 07h after reset.
Data Pointer Low 0 (DPL0)
7
6
5
4
3
2
1
0
Reset Value
SFR 82h
DPL0.7
DPL0.6
DPL0.5
DPL0.4
DPL0.3
DPL0.2
DPL0.1
DPL0.0
00h
DPL0.7−0 Data Pointer Low 0. This register is the low byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 are used
bits 7−0 to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86h).
Data Pointer High 0 (DPH0)
7
6
5
4
3
2
1
0
Reset Value
SFR 83h
DPH0.7
DPH0.6
DPH0.5
DPH0.4
DPH0.3
DPH0.2
DPH0.1
DPH0.0
00h
DPH0.7−0 Data Pointer High 0. This register is the high byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 are used
bits 7−0 to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86h).
Data Pointer Low 1 (DPL1)
7
6
5
4
3
2
1
0
Reset Value
SFR 84h
DPL1.7
DPL1.6
DPL1.5
DPL1.4
DPL1.3
DPL1.2
DPL1.1
DPL1.0
00h
DPL1.7−0 Data Pointer Low 1. This register is the low byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0)
bits 7−0 (SFR 86h) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations.
Data Pointer High 1 (DPH1)
7
6
5
4
3
2
1
0
Reset Value
SFR 85h
DPH1.7
DPH1.6
DPH1.5
DPH1.4
DPH1.3
DPH1.2
DPH1.1
DPH1.0
00h
DPH1.7−0 Data Pointer High. This register is the high byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0)
bits 7−0 (SFR 86h) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations.
Data Pointer Select (DPS)
7
6
5
4
3
2
1
0
Reset Value
SFR 86h
0
0
0
0
0
0
0
SEL
00h
SEL
bit 0
Data Pointer Select. This bit selects the active data pointer.
0: Instructions that use the DPTR will use DPL0 and DPH0.
1: Instructions that use the DPTR will use DPL1 and DPH1.
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Power Control (PCON)
7
6
5
4
3
2
1
0
Reset Value
SFR 87h
SMOD
0
1
1
GF1
GF0
STOP
IDLE
30h
SMOD
Serial Port 0 Baud Rate Doubler Enable. The serial baud rate doubling function for Serial Port 0.
0: Serial Port 0 baud rate will be a standard baud rate.
bit 7
1: Serial Port 0 baud rate will be double that defined by baud rate generation equation.
GF1
General-Purpose User Flag 1. This is a general-purpose flag for software control.
bit 3
GF0
General-Purpose User Flag 0. This is a general-purpose flag for software control.
bit 2
STOP
bit 1
Stop Mode Select. Setting this bit halts the internal oscillator and blocks external clocks. This bit always reads as 0.
Exit with RESET. In this mode, internal peripherals are frozen and I/O pins are held in their current state. The ADC is
frozen, but IDAC and VREF remain active.
IDLE
bit 0
Idle Mode Select. Setting this bit freezes the CPU, Timer 0 and 1, and the USART; other peripherals remain active.
This bit will always be read as a 0. Exit with AIE (A6h) and EWU (C6h) interrupts (refer to Figure 6 for clocks affected
during Idle mode).
Timer/Counter Control (TCON)
7
6
5
4
3
2
1
0
Reset Value
SFR 88h
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00h
TF1
Timer 1 Overflow Flag. This bit indicates when Timer 1 overflows its maximum count as defined by the current mode.
bit 7
This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine.
0: No Timer 1 overflow has been detected.
1: Timer 1 has overflowed its maximum count.
TR1
Timer 1 Run Control. This bit enables/disables the operation of Timer 1. Halting this timer preserves the current
bit 6
count in TH1, TL1.
0: Timer is halted.
1: Timer is enabled.
TF0
Timer 0 Overflow Flag. This bit indicates when Timer 0 overflows its maximum count as defined by the current mode.
bit 5
This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine.
0: No Timer 0 overflow has been detected.
1: Timer 0 has overflowed its maximum count.
TR0
Timer 0 Run Control. This bit enables/disables the operation of Timer 0. Halting this timer preserves the current
bit 4
count in TH0, TL0.
0: Timer is halted.
1: Timer is enabled.
IE1
bit 3
Interrupt 1 Edge Detect. This bit is set when an edge/level of the type defined by IT1 is detected. If IT1 = 1, this bit
will remain set until cleared in software or the start of the External Interrupt 1 service routine. If IT1 = 0, this bit will inversely
reflect the state of the INT1 pin.
IT1
Interrupt 1 Type Select. This bit selects whether the INT1 pin will detect edge- or level-triggered interrupts.
bit 2
0: INT1 is level-triggered.
1: INT1 is edge-triggered.
IE0
bit 1
Interrupt 0 Edge Detect. This bit is set when an edge/level of the type defined by IT0 is detected. If IT0 = 1, this bit
will remain set until cleared in software or the start of the External Interrupt 0 service routine. If IT0 = 0, this bit will inversely
reflect the state of the INT0 pin.
IT0
Interrupt 0 Type Select. This bit selects whether the INT0 pin will detect edge- or level-triggered interrupts.
bit 0
0: INT0 is level-triggered.
1: INT0 is edge-triggered.
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Timer Mode Control (TMOD)
7
6
5
4
3
2
1
0
Reset Value
TIMER 1
TIMER 0
SFR 89h
00h
GATE
C/T
M1
M0
GATE
C/T
M1
M0
GATE
Timer 1 Gate Control. This bit enables/disables the ability of Timer 1 to increment.
0: Timer 1 will clock when TR1 = 1, regardless of the state of pin INT1.
1: Timer 1 will clock only when TR1 = 1 and pin INT1 = 1.
bit 7
C/T
Timer 1 Counter/Timer Select.
bit 6
0: Timer is incremented by internal clocks.
1: Timer is incremented by pulses on T1 pin when TR1 (TCON.6, SFR 88h) is 1.
M1, M0
Timer 1 Mode Select. These bits select the operating mode of Timer 1.
bits 5−4
M1
0
M0
0
MODE
Mode 0: 8-bit counter with 5-bit prescale.
Mode 1: 16 bits.
0
1
1
0
Mode 2: 8-bit counter with auto reload.
Mode 3: Timer 1 is halted, but holds its count.
1
1
GATE
Timer 0 Gate Control. This bit enables/disables the ability of Timer 0 to increment.
0: Timer 0 will clock when TR0 = 1, regardless of the state of pin INT0 (software control).
1: Timer 0 will clock only when TR0 = 1 and pin INT0 = 1 (hardware control).
bit 3
C/T
Timer 0 Counter/Timer Select.
bit 2
0: Timer is incremented by internal clocks.
1: Timer is incremented by pulses on pin T0 when TR0 (TCON.4, SFR 88h) is 1.
M1, M0
Timer 0 Mode Select. These bits select the operating mode of Timer 0.
bits 1−0
M1
0
M0
0
MODE
Mode 0: 8-bit counter with 5-bit prescale.
Mode 1: 16 bits.
0
1
1
0
Mode 2: 8-bit counter with auto reload.
Mode 3: Two 8-bit counters.
1
1
Timer 0 LSB (TL0)
7
6
5
4
3
2
1
0
Reset Value
SFR 8Ah
TL0.7
TL0.6
TL0.5
TL0.4
TL0.3
TL0.2
TL0.1
TL0.0
00h
TL0.7−0
Timer 0 LSB. This register contains the least significant byte of Timer 0.
bits 7−0
Timer 1 LSB (TL1)
7
6
5
4
3
2
1
0
Reset Value
SFR 8Bh
TL1.7
TL1.6
TL1.5
TL1.4
TL1.3
TL1.2
TL1.1
TL1.0
00h
TL1.7−0
Timer 1 LSB. This register contains the least significant byte of Timer 1.
bits 7−0
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Timer 0 MSB (TH0)
7
6
5
4
3
2
1
0
Reset Value
SFR 8Ch
TH0.7
TH0.6
TH0.5
TH0.4
TH0.3
TH0.2
TH0.1
TH0.0
00h
TH0.7−0
Timer 0 MSB. This register contains the most significant byte of Timer 0.
bits 7−0
Timer 1 MSB (TH1)
7
6
5
4
3
2
1
0
Reset Value
SFR 8Dh
TH1.7
TH1.6
TH1.5
TH1.4
TH1.3
TH1.2
TH1.1
TH1.0
00h
TH1.7−0
Timer 1 MSB. This register contains the most significant byte of Timer 1.
bits 7−0
Clock Control (CKCON)
7
6
5
4
3
2
1
0
Reset Value
SFR 8Eh
0
0
0
T1M
T0M
MD2
MD1
MD0
01h
T1M
Timer 1 Clock Select. This bit controls the division of the system clock that drives Timer 1. Clearing this bit to 0
bit 4
maintains 8051 compatibility. This bit has no effect on instruction cycle timing.
0: Timer 1 uses a divide-by-12 of the crystal frequency.
1: Timer 1 uses a divide-by-4 of the crystal frequency.
T0M
Timer 0 Clock Select. This bit controls the division of the system clock that drives Timer 0. Clearing this bit to 0
bit 3
maintains 8051 compatibility. This bit has no effect on instruction cycle timing.
0: Timer 0 uses a divide-by-12 of the crystal frequency.
1: Timer 0 uses a divide-by-4 of the crystal frequency.
MD2, MD1, MD0 Stretch MOVX Select. These bits select the time by which external MOVX cycles are to be stretched in the
bits 2−0
standard 8051 core. Since the MSC120x does not allow external memory access, these bits should be set to
000b to allow for the fastest Flash Data Memory access.
Memory Write Select (MWS)
7
6
5
4
3
2
1
0
Reset Value
SFR 8Fh
0
0
0
0
0
0
0
MXWS
00h
MXWS
MOVX Write Select. This allows writing to the internal Flash Program Memory.
bit 0
0: No writes are allowed to the internal Flash Program Memory.
1: Writing is allowed to the internal Flash Program Memory, unless PML or RSL (HCR0, CADDR 3Fh) are set.
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Port 1 (P1)
7
6
5
4
3
2
1
0
Reset Value
P1.7
INT5
P1.6
INT4
P1.5
INT3
P1.4
INT2/SS
P1.3
DIN
P1.2
DOUT
P1.1
P1.0
PROG
SFR 90h
FFh
P1.7−0
bits 7−0
General-Purpose I/O Port 1. This register functions as a general-purpose I/O port. In addition, all the pins have an
alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port 1
latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity. To use the alternate
function, set the appropriate mode in P1DDRL (SFR AEh), P1DDRH (SFR AFh).
INT5
bit 7
External Interrupt 5. A falling edge on this pin will cause an external interrupt 5 if enabled.
External Interrupt 4. A rising edge on this pin will cause an external interrupt 4 if enabled.
External Interrupt 3. A falling edge on this pin will cause an external interrupt 3 if enabled.
INT4
bit 6
INT3
bit 5
INT2/SS
External Interrupt 2. A rising edge on this pin will cause an external interrupt 2 if enabled. This pin can be used as
bit 4
slave select (SS) in SPI slave mode.
2
2
DIN
Serial Data In. This pin receives serial data in SPI and I C modes (in I C mode, this pin should be configured as an
bit 3
input) or standard 8051.
2
2
DOUT
Serial Data Out. This pin transmits serial data in SPI and I C modes (in I C mode, this pin should be configured as
bit 2
an open drain) or standard 8051.
PROG
Program Mode. When this pin is pulled low at power-up, the device enters Serial Programming mode (refer to
bit 0
Figure 2).
External Interrupt Flag (EXIF)
7
6
5
4
3
2
1
0
Reset Value
SFR 91h
IE5
IE4
IE3
IE2
1
0
0
0
08h
IE5
External Interrupt 5 Flag. This bit will be set when a falling edge is detected on INT5. This bit must be cleared
bit 7
manually by software. Setting this bit in software will cause an interrupt if enabled.
IE4
External Interrupt 4 Flag. This bit will be set when a rising edge is detected on INT4. This bit must be cleared
bit 6
manually by software. Setting this bit in software will cause an interrupt if enabled.
IE3
External Interrupt 3 Flag. This bit will be set when a falling edge is detected on INT3. This bit must be cleared
bit 5
manually by software. Setting this bit in software will cause an interrupt if enabled.
IE2
External Interrupt 2 Flag. This bit will be set when a rising edge is detected on INT2. This bit must be cleared
bit 4
manually by software. Setting this bit in software will cause an interrupt if enabled.
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Configuration Address (CADDR) (write-only)
7
6
5
4
3
2
1
0
Reset Value
SFR 93h
00h
CADDR
bits 7−0
Configuration Address. This register supplies the address for reading bytes in the 128 bytes of Flash Configuration
Memory. It is recommended that faddr_data_read be used when accessing Configuration memory.This register is
also used as the address for the sfr_read and sfr_write routines, so it must be set prior to their use.
CAUTION: If this register is written to while executing from Flash Memory, the CDATA register will be incorrect.
Configuration Data (CDATA) (read-only)
7
6
5
4
3
2
1
0
Reset Value
SFR 94h
00h
CDATA
bits 7−0
Configuration Data. This register will contain the data in the 128 bytes of Flash Configuration Memory that
is located at the last written address in the CADDR register. This is a read-only register.
Serial Port 0 Control (SCON0)
7
6
5
4
3
2
1
0
Reset Value
SFR 98h
SM0_0
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
00h
SM0−2
Serial Port 0 Mode. These bits control the mode of serial Port 0. Modes 1, 2, and 3 have 1 start and 1 stop bit in
bits 7−5
addition to the 8 or 9 data bits.
MODE SM0
SM1
SM2 FUNCTION
LENGTH
8 bits
PERIOD
(1)
0
0
1
1
2
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Synchronous
12 p
4 p
CLK
(1)
CLK
Synchronous
8 bits
Asynchronous
10 bits
10 bits
11 bits
Timer 1 Baud Rate Equation
Timer 1 Baud Rate Equation
(2)
Asynchronous−Valid Stop Required
Asynchronous
(1)
(1)
64 p
32 p
(SMOD = 0)
(SMOD = 1)
CLK
CLK
(1)
(1)
2
1
0
1
Asynchronous with Multiprocessor Communication
11 bits
64 p
32 p
(SMOD = 0)
(SMOD = 1)
CLK
CLK
3
3
1
1
1
1
0
1
Asynchronous
11 bits
11 bits
Timer 1 Baud Rate Equation
Timer 1 Baud Rate Equation
(3)
Asynchronous with Multiprocessor Communication
(1)
(2)
(3)
pCLK will be equal to tCLK, except that pCLK will stop for Idle mode.
RI_0 will only be activated when a valid STOP is received.
RI_0 will not be activated if bit 9 = 0.
REN_0
Receive Enable. This bit enables/disables the serial Port 0 received shift register.
bit 4
0: Serial Port 0 reception disabled.
1: Serial Port 0 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0).
TB8_0
9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 0 modes 2 and 3.
bit 3
RB8_0
9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 0 modes
bit 2
2 and 3. In serial port mode 1, when SM2_0 = 0, RB8_0 is the state of the stop bit. RB8_0 is not used in mode 0.
TI_0
bit 1
Transmitter Interrupt Flag. This bit indicates that data in the serial Port 0 buffer has been completely shifted out. In serial
port mode 0, TI_0 is set at the end of the 8th data bit. In all other modes, this bit is set at the end of the last data bit.
This bit must be manually cleared by software.
RI_0
bit 0
Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 0 buffer. In serial
port mode 0, RI_0 is set at the end of the 8th bit. In serial port mode 1, RI_0 is set after the last sample of the incoming
stop bit subject to the state of SM2_0. In modes 2 and 3, RI_0 is set after the last sample of RB8_0. This bit must
be manually cleared by software.
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Serial Data Buffer 0 (SBUF0)
7
6
5
4
3
2
1
0
Reset Value
SFR 99h
00h
SBUF0
bits 7−0
Serial Data Buffer 0. Data for Serial Port 0 is read from or written to this location. The serial transmit and receive
buffers are separate registers, but both are addressed at this location.
SPI Control (SPICON)
7
6
5
4
3
2
1
0
Reset Value
SFR 9Ah
SBIT3
SBIT2
SBIT1
SBIT0
ORDER
CPHA
ESS
CPOL
00h
SBIT3−0
Serial Bit Count. Number of bits transferred (read-only).
bits 7−4
SBIT3:0
0x00
0x01
0x03
0x02
0x06
0x07
0x05
0x04
0x0C
COUNT
0
1
2
3
4
5
6
7
8
ORDER
Set Bit Order for Transmit and Receive.
0: Most significant bits first
bit 3
1: Least significant bBits first
CPHA
Serial Clock Phase Control.
bit 2
0: Valid data starting from half SCK period before the first edge of SCK
1: Valid data starting from the first edge of SCK
ESS
Enable Slave Select.
bit 1
0: SS (P1.4) is configured as a general-purpose I/O (default).
1: SS (P1.4) is configured as SS for SPI mode. DOUT (P1.2) drives when SS is low, and DOUT (P1.2) is
high-impedance when SS is high.
CPOL
Serial Clock Polarity.
0: SCK idle at logic low
1: SCK idle at logic high
bit 0
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SBAS317E − APRIL 2004 − REVISED MAY 2006
2
I C Control (I2CCON)
7
6
5
4
3
2
1
0
Reset Value
SFR 9Ah
SBIT3
SBIT2
SBIT1
SBIT0
STOP
START
DCS
CNTSEL
00h
SBIT3−0
Serial Bit Count. Number of bits transferred (read-only).
bits 7−4
SBIT3:0
0x00
0x01
0x03
0x02
0x06
0x07
0x05
0x04
0x0C
COUNT
0
1
2
3
4
5
6
7
8
STOP
Stop-Bit Status.
bit 3
0: No stop
1: Stop condition received and I2C (bit 3, SFR A7h) set (cleared on write to I2CDATA)
START
Start-Bit Status.
bit 2
0: No stop
1: Start or repeated start condition received and I2C (bit 3, SFR A7h) set (cleared on write to I2CDATA)
DCS
Disable Serial Clock Stretch.
bit 1
0: Enable SCL stretch (cleared by firmware or START condition)
1: Disable SCL stretch
CNTSEL
Counter Select.
bit 0
0: Counter IRQ set for bit counter = 8 (default)
1: Counter IRQ set for bit counter = 1
2
SPI Data (SPIDATA) / I C Data (I2CDATA)
7
6
5
4
3
2
1
0
Reset Value
SFR 9Bh
00h
SPIDATA
SPI Data. Data for SPI is read from or written to this location. The SPI transmit and receive buffers are
bits 7−0
separate registers, but both are addressed at this location. Read to clear the receive interrupt and write to clear the
transmit interrupt.
2
2
I2CDATA
I2C Data. Data for I C is read from or written to this location. The I C transmit and receive buffers are
bits 7−0
separate registers, but both are addressed at this location.
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Auxiliary Interrupt Poll (AIPOL)
7
6
5
4
3
2
1
0
Reset Value
SFR A4h
SECIP
SUMIP
ADCIP
MSECIP
I2CIP
CNTIP
ALVDIP
0
00h
Interrupts are enabled by EICON.4 (SFR D8h). The other interrupts are controlled by the IE and EIE registers.
SECIP
Second System Timer Interrupt Poll (before IRQ masking).
0 = Second system timer interrupt poll inactive
bit 7
1 = Second system timer interrupt poll active
SUMIP
Summation Interrupt Poll (before IRQ masking).
0 = Summation interrupt poll inactive
bit 6
1 = Summation interrupt poll active
ADCIP
ADC Interrupt Poll (before IRQ masking).
0 = ADC interrupt poll inactive
bit 5
1 = ADC interrupt poll active
MSECIP
Millisecond System Timer Interrupt Poll (before IRQ masking).
0 = Millisecond system timer interrupt poll inactive
1 = Millisecond system timer interrupt poll active
bit 4
2
I2CIP
I C Start/Stop Interrupt Poll (before IRQ masking).
2
bit 3
0 = I C start/stop interrupt poll inactive
2
1 = I C start/stop interrupt poll active
CNTIP
Serial Bit Count Interrupt Poll (before IRQ masking).
0 = Serial bit count interrupt poll inactive
bit 2
1 = Serial bit count interrupt poll active
ALVDIP
Analog Low Voltage Detect Interrupt Poll (before IRQ masking).
bit 1
0 = Analog low voltage detect interrupt poll inactive (AV
> ALVD threshold; ALVD threshold set in LVDCON, E7h)
< ALVD threshold; ALVD threshold set in LVDCON, E7h)
DD
1 = Analog low voltage detect interrupt poll active (AV
DD
Pending Auxiliary Interrupt (PAI)
7
6
5
4
3
2
1
0
Reset Value
SFR A5h
0
0
0
0
PAI3
PAI2
PAI1
PAI0
00h
PAI
bits 3−0
Pending Auxiliary Interrupt Register. The results of this register can be used as an index to vector to the
appropriate interrupt routine. All of these interrupts vector through address 0033h.
PAI3
PAI2
PAI1
PAI0
AUXILIARY INTERRUPT STATUS
No Pending Auxiliary IRQ.
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Reserved.
Analog Low Voltage Detect IRQ and Possible Lower Priority Pending.
2
I C IRQ and Possible Lower Priority Pending.
Serial Bit Count Interrupt and Possible Lower Priority Pending.
Millisecond System Timer IRQ and Possible Lower Priority Pending.
ADC IRQ and Possible Lower Priority Pending.
Summation IRQ and Possible Lower Priority Pending.
Second System Timer IRQ.
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Auxiliary Interrupt Enable (AIE)
7
6
5
4
3
2
1
0
Reset Value
SFR A6h
ESEC
ESUM
EADC
EMSEC
EI2C
ECNT
EALV
0
00h
Interrupts are enabled by EICON.4 (SFR D8h). The other interrupts are controlled by the IE and EIE registers.
ESEC
Enable Second System Timer Interrupt (lowest priority auxiliary interrupt).
Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: Second Timer Interrupt mask.
bit 7
ESUM
Enable Summation Interrupt.
bit 6
Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: Summation Interrupt mask.
EADC
Enable ADC Interrupt.
bit 5
Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: ADC Interrupt mask.
EMSEC
Enable Millisecond System Timer Interrupt.
bit 4
Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: Millisecond System Timer Interrupt mask.
2
EI2C
Enable I C Start/Stop Bit.
bit 3
Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
2
Read: I C Start/Stop Bit mask.
ECNT
Enable Serial Bit Count Interrupt.
bit 2
Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: Serial Bit Count Interrupt mask.
EALV
Enable Analog Low Voltage Interrupt.
bit 1
Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: Analog Low Voltage Detect Interrupt mask.
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Auxiliary Interrupt Status (AISTAT)
7
6
5
4
3
2
1
0
Reset Value
SFR A7h
SEC
SUM
ADC
MSEC
I2C
CNT
ALVD
0
00h
SEC
Second System Timer Interrupt Status Flag (lowest priority AI).
0: SEC interrupt cleared or masked.
bit 7
1: SEC Interrupt active (it is cleared by reading SECINT, SFR F9h).
SUM
Summation Register Interrupt Status Flag.
bit 6
0: SUM interrupt cleared or masked.
1: SUM interrupt active (it is cleared by reading the lowest byte of SUMR0, SFR E2h).
ADC
ADC Interrupt Status Flag.
bit 5
0: ADC interrupt cleared or masked.
1: ADC interrupt active (it is cleared by reading the lowest byte of ADRESL, SFR D9h; if active, no new data will be
written to the ADC Results registers).
MSEC
Millisecond System Timer Interrupt Status Flag.
0: MSEC interrupt cleared or masked.
bit 4
1: MSEC interrupt active (it is cleared by reading MSINT, SFR FAh).
2
I2C
I C Start/Stop Interrupt Status Flag.
2
bit 3
0: I C start/stop interrupt cleared or masked.
2
1: I C start/stop interrupt active (it is cleared by writing to I2CDATA, SFR 9Bh).
CNT
CNT Interrupt Status Flag.
bit 2
0: CNT Interrupt cleared or masked.
1: CNT Interrupt active (it is cleared by reading from or writing to SPIDATA/I2CDATA, SFR 9Bh).
ALVD
Analog Low Voltage Detect Interrupt Status Flag.
bit 1
0: ALVD Interrupt cleared or masked.
1: ALVD Interrupt active (cleared in hardware if AV
exceeds ALVD threshold).
DD
NOTE: If an interrupt is masked, the status can be read in AIPOL (SFR A4h).
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Interrupt Enable (IE)
7
6
5
4
3
2
1
0
Reset Value
SFR A8h
EA
0
0
ES0
ET1
EX1
ET0
EX0
00h
EA
Global Interrupt Enable. This bit controls the global masking of all interrupts except those in AIE (SFR A6h).
0: Disable interrupt sources. This bit overrides individual interrupt mask settings for this register.
1: Enable all individual interrupt masks. Individual interrupts in this register will occur if enabled.
bit 7
ES0
Enable Serial Port 0 Interrupt. This bit controls the masking of the serial Port 0 interrupt.
0: Disable all serial Port 0 interrupts.
bit 4
1: Enable interrupt requests generated by the RI_0 (SCON0.0, SFR 98h) or TI_0 (SCON0.1, SFR 98h) flags.
ET1
Enable Timer 1 Interrupt. This bit controls the masking of the Timer 1 interrupt.
0: Disable Timer 1 interrupt.
bit 3
1: Enable interrupt requests generated by the TF1 flag (TCON.7, SFR 88h).
EX1
Enable External Interrupt 1. This bit controls the masking of external interrupt 1.
0: Disable external interrupt 1.
bit 2
1: Enable interrupt requests generated by the INT1 pin.
ET0
Enable Timer 0 Interrupt. This bit controls the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupts.
bit 1
1: Enable interrupt requests generated by the TF0 flag (TCON.5, SFR 88h).
EX0
Enable External Interrupt 0. This bit controls the masking of external interrupt 0.
0: Disable external interrupt 0.
bit 0
1: Enable interrupt requests generated by the INT0 pin.
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Port 1 Data Direction Low (P1DDRL)
7
6
5
4
3
2
1
0
Reset Value
SFR AEh
P13H
P13L
P12H
P12L
P11H
P11L
P10H
P10L
00h
P1.3
Port 1 bit 3 control.
bits 7−6
P13H
P13L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P1.2
Port 1 bit 2 control.
bits 5−4
P12H
P12L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P1.1
Port 1 bit 1 control.
bits 3−2
P11H
P11L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P1.0
Port 1 bit 0 control.
bits 1−0
P10H
P10L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Port 1 Data Direction High (P1DDRH)
7
6
5
4
3
2
1
0
Reset Value
SFR AFh
P17H
P17L
P16H
P16L
P15H
P15L
P14H
P14L
00h
P1.7
Port 1 bit 7 control.
bits 7−6
P17H
P17L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P1.6
Port 1 bit 6 control.
bits 5−4
P16H
P16L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P1.5
Port 1 bit 5 control.
bits 3−2
P15H
P15L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P1.4
Port 1 bit 4 control.
bits 1−0
P14H
P14L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Port 3 (P3)
7
6
5
4
3
2
1
0
Reset Value
P3.7
P3.6
SCK/SCL/CLKS
P3.5
T1
P3.4
T0
P3.3
INT1
P3.2
INT0
P3.1
TXD0
P3.0
RXD0
SFR B0h
FFh
P3.7−0
bits 7−0
General-Purpose I/O Port 3. This register functions as a general-purpose I/O port. In addition, all the pins have an
alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port 3
latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity.
SCK/SCL/CLKS Clock Source Select. Refer to PASEL (SFR F2h).
bit 6
T1
Timer/Counter 1 External Input. A 1 to 0 transition on this pin will increment Timer 1.
Timer/Counter 0 External Input. A 1 to 0 transition on this pin will increment Timer 0.
External Interrupt 1. A falling edge/low level on this pin will cause an external interrupt 1 if enabled.
External Interrupt 0. A falling edge/low level on this pin will cause an external interrupt 0 if enabled.
bit 5
T0
bit 4
INT1
bit 3
INT0
bit 2
TXD0
Serial Port 0 Transmit. This pin transmits the serial Port 0 data in serial port modes 1, 2, 3, and emits the
bit 1
synchronizing clock in serial port mode 0.
RXD0
Serial Port 0 Receive. This pin receives the serial Port 0 data in serial port modes 1, 2, 3, and is a bidirectional data
bit 0
transfer pin in serial port mode 0.
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Port 3 Data Direction Low (P3DDRL)
7
6
5
4
3
2
1
0
Reset Value
SFR B3h
P33H
P33L
P32H
P32L
P31H
P31L
P30H
P30L
00h
P3.3
Port 3 bit 3 control.
bits 7−6
P33H
P33L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P3.2
Port 3 bit 2 control.
bits 5−4
P32H
P32L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P3.1
Port 3 bit 1 control.
bits 3−2
P31H
P31L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P3.0
Port 3 bit 0 control.
bits 1−0
P30H
P30L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Port 3 Data Direction High (P3DDRH)
7
6
5
4
3
2
1
0
Reset Value
SFR B4h
P37H
P37L
P36H
P36L
P35H
P35L
P34H
P34L
00h
P3.7
bits 7−6
Port 3 bit 7 control.
P37H
P37L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
:
NOTE Port 3.7 also controlled by EA and Memory Access Control HCR1.1.
P3.6
Port 3 bit 6 control.
bits 5−4
P36H
P36L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
:
NOTE Port 3.6 also controlled by EA and Memory Access Control HCR1.1.
P3.5
Port 3 bit 5 control.
bits 3−2
P35H
P35L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P3.4
Port 3 bit 4 control.
bits 1−0
P34H
P34L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
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SBAS317E − APRIL 2004 − REVISED MAY 2006
IDAC
7
6
5
4
3
2
1
0
Reset Value
SFR B5h
MSB
LSB
00h
IDAC
bits 7−0
Current DAC.
IDAC
= IDAC • 3.9µA (∼1mA full-scale). Setting (PDCON.PDIDAC) will shut down IDAC and float the IDAC pin.
OUT
Interrupt Priority (IP)
7
6
5
4
3
2
1
0
Reset Value
SFR B8h
1
0
0
PS0
PT1
PX1
PT0
PX0
80h
PS0
Serial Port 0 Interrupt. This bit controls the priority of the serial Port 0 interrupt.
0 = Serial Port 0 priority is determined by the natural priority order.
1 = Serial Port 0 is a high-priority interrupt.
bit 4
PT1
Timer 1 Interrupt. This bit controls the priority of the Timer 1 interrupt.
0 = Timer 1 priority is determined by the natural priority order.
1 = Timer 1 priority is a high-priority interrupt.
bit 3
PX1
External Interrupt 1. This bit controls the priority of external interrupt 1.
0 = External interrupt 1 priority is determined by the natural priority order.
1 = External interrupt 1 is a high-priority interrupt.
bit 2
PT0
Timer 0 Interrupt. This bit controls the priority of the Timer 0 interrupt.
0 = Timer 0 priority is determined by the natural priority order.
1 = Timer 0 priority is a high-priority interrupt.
bit 1
PX0
External Interrupt 0. This bit controls the priority of external interrupt 0.
0 = External interrupt 0 priority is determined by the natural priority order.
1 = External interrupt 0 is a high-priority interrupt.
bit 0
Enable Wake Up (EWU) (Waking Up from Idle Mode)
7
6
5
4
3
2
1
0
Reset Value
SFR C6h
—
—
—
—
—
EWUWDT
EWUEX1
EWUEX0
00h
Auxiliary interrupts will wake up from Idle mode. They are enabled with EAI (EICON.5).
EWUWDT Enable Wake Up Watchdog Timer. Wake using watchdog timer interrupt.
bit 2
0 = Do not wake up on watchdog timer interrupt.
1 = Wake up on watchdog timer interrupt.
EWUEX1
Enable Wake Up External 1. Wake using external interrupt source 1.
0 = Do not wake up on external interrupt source 1.
1 = Wake up on external interrupt source 1.
bit 1
EWUEX0
Enable Wake Up External 0. Wake using external interrupt source 0.
0 = Do not wake up on external interrupt source 0.
1 = Wake up on external interrupt source 0.
bit 0
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SBAS317E − APRIL 2004 − REVISED MAY 2006
System Clock Divider (SYSCLK)
7
6
5
4
3
2
1
0
Reset Value
SFR C7h
0
0
DIVMOD1
DIVMOD0
0
DIV2
DIV1
DIV0
00h
NOTE: Changing the SYSCLK registers affects all internal clocks, including the ADC clock.
DIVMOD1−0 Clock Divide Mode
bits 5−4
Write:
DIVMOD DIVIDE MODE
00
01
10
Normal mode (default, no divide).
Immediate mode: start divide immediately; return to Normal mode on Idle mode wakeup condition, or by direct write to SFR.
Delay mode: same as Immediate mode, except that the mode changes with the millisecond interrupt (MSINT). If MSINT is
enabled, the divide will start on the next MSINT and return to normal mode on the following MSINT. If MSINT is not enabled,
the divide will start on the next MSINT condition (even if masked) but will not leave the divide mode until the MSINT counter
overflows, which follows a wakeup condition. Can exit by directly writing to SFR.
11
Manual mode: start divide immediately; exit mode only by directly writing to SFR. Same as immediate mode, but cannot
return to Normal mode on Idle mode wakeup condition; only by directly writing to SFR.
Read:
DIVMOD
DIVIDE MODE STATUS
No divide
00
01
10
11
Divider is in Immediate mode
Divider is in Delay mode
Manual mode
DIV2−0
Divide Mode
bit 2−0
DIV
000
001
010
011
100
101
110
111
DIVISOR
f
FREQUENCY
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Divide by 2 (default)
Divide by 4
f
f
f
f
f
f
f
f
= f
SYS
= f
SYS
= f
SYS
= f
SYS
= f
SYS
= f
SYS
= f
SYS
= f
SYS
/2
/4
Divide by 8
/8
Divide by 16
/16
Divide by 32
/32
Divide by 1024
Divide by 2048
Divide by 4096
/1024
/2048
/4096
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Program Status Word (PSW)
7
6
5
4
3
2
1
0
Reset Value
SFR D0h
CY
AC
F0
RS1
RS0
OV
F1
P
00h
CY
Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (during addition) or a borrow (during
bit 7
subtraction). Otherwise, it is cleared to ‘0’ by all arithmetic operations.
AC
Auxiliary Carry Flag. This bit is set to ‘1’ if the last arithmetic operation resulted in a carry into (during addition), or
bit 6
a borrow (during subtraction) from the high order nibble. Otherwise, it is cleared to ‘0’ by all arithmetic operations.
F0
User Flag 0. This is a bit-addressable, general-purpose flag for software control.
bit 5
RS1, RS0
Register Bank Select 1−0. These bits select which register bank is addressed during register accesses.
bits 4−3
RS1
RS0
REGISTER BANK
ADDRESS
00h − 07h
08h − 0Fh
10h − 17h
18h − 1Fh
0
0
1
1
0
1
0
1
0
1
2
3
OV
Overflow Flag. This bit is set to ‘1’ if the last arithmetic operation resulted in a carry (addition), borrow (subtraction),
bit 2
or overflow (multiply or divide). Otherwise, it is cleared to ‘0’ by all arithmetic operations.
F1
User Flag 1. This is a bit-addressable, general-purpose flag for software control.
bit 1
P
Parity Flag. This bit is set to ‘1’ if the modulo-2 sum of the 8 bits of the accumulator is 1 (odd parity), and cleared to
bit 0
‘0’ on even parity.
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SBAS317E − APRIL 2004 − REVISED MAY 2006
ADC Offset Calibration Low Byte (OCL)
7
6
5
4
3
2
1
0
Reset Value
SFR D1h
LSB
00h
All MSC120x devices support 24-bit calibration values.
OCL
ADC Offset Calibration Low Byte. This is the low byte of the 24-bit word that contains the ADC offset
bits 7−0
calibration. This value is written by the device after performing a calibration. This register is read/writable, so it can
be used for setting calibration values independent of the hardware-generated calibration values.
ADC Offset Calibration Middle Byte (OCM)
7
6
5
4
3
2
1
0
Reset Value
SFR D2h
00h
All MSC120x devices support 24-bit calibration values.
OCM
bits 7−0
ADC Offset Calibration Middle Byte. This is the middle byte of the 24-bit word that contains the ADC offset
calibration. This value is written by the device after performing a calibration. This register is read/writable, so it can
be used for setting calibration values independent of the hardware-generated calibration values.
ADC Offset Calibration High Byte (OCH)
7
6
5
4
3
2
1
0
Reset Value
SFR D3h
MSB
00h
All MSC120x devices support 24-bit calibration values.
OCH
bits 7−0
ADC Offset Calibration High Byte. This is the high byte of the 24-bit word that contains the ADC offset
calibration. This value is written by the device after performing a calibration. This register is read/writable, so it can
be used for setting calibration values independent of the hardware-generated calibration values.
ADC Gain Calibration Low Byte (GCL)
7
6
5
4
3
2
1
0
Reset Value
SFR D4h
LSB
5Ah
All MSC120x devices support 24-bit calibration values.
GCL
ADC Gain Calibration Low Byte. This is the low byte of the 24-bit word that contains the ADC gain
bits 7−0
calibration. This value is written by the device after performing a calibration. This register is read/writable, so it can
be used for setting calibration values independent of the hardware-generated calibration values.
ADC Gain Calibration Middle Byte (GCM)
7
6
5
4
3
2
1
0
Reset Value
SFR D5h
ECh
All MSC120x devices support 24-bit calibration values.
GCM
bits 7−0
ADC Gain Calibration Middle Byte. This is the middle byte of the 24-bit word that contains the ADC gain
calibration. This value is written by the device after performing a calibration. This register is read/writable, so it can
be used for setting calibration values independent of the hardware-generated calibration values.
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SBAS317E − APRIL 2004 − REVISED MAY 2006
ADC Gain Calibration High Byte (GCH)
7
6
5
4
3
2
1
0
Reset Value
SFR D6h
MSB
5Fh
All MSC120x devices support 24-bit calibration values.
GCH
bits 7−0
ADC Gain Calibration High Byte. This is the high byte of the 24-bit word that contains the ADC gain
calibration. This value is written by the device after performing a calibration. This register is read/writable, so it can
be used for setting calibration values independent of the hardware-generated calibration values.
ADC Input Multiplexer (ADMUX)
7
6
5
4
3
2
1
0
Reset Value
SFR D7h
INP3
INP2
INP1
INP0
INN3
INN2
INN1
INN0
01h
INP3−0
Input Multiplexer Positive Input. This selects the positive signal input.
bits 7−4
INP3
INP2
INP1
INP0
POSITIVE INPUT
AIN0 (default)
AIN1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN2
AIN3
AIN4
AIN5
AIN6 (MSC1200 only; for the MSC1201/02, this pin is internally tied to REFIN−)
AIN7 (MSC1200 only; for the MSC1201/02, this pin is internally tied to REFIN−)
AINCOM
Temperature Sensor (requires ADMUX = FFh)
INN3−0
Input Multiplexer Negative Input. This selects the negative signal input.
bits 3−0
INN3
INN2
INN1
INN0
NEGATIVE INPUT
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN0
AIN1 (default)
AIN2
AIN3
AIN4
AIN5
AIN6 (MSC1200 Only)
AIN7 (MSC1200 Only)
AINCOM
Temperature Sensor (requires ADMUX = FFh)
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Enable Interrupt Control (EICON)
7
6
5
4
3
2
1
0
Reset Value
SFR D8h
0
1
EAI
AI
WDTI
0
0
0
40h
EAI
Enable Auxiliary Interrupt. The Auxiliary Interrupt accesses nine different interrupts which are masked and
bit 5
identified by SFR registers PAI (SFR A5h), AIE (SFR A6h), and AISTAT (SFR A7h).
0 = Auxiliary Interrupt disabled (default).
1 = Auxiliary Interrupt enabled.
AI
bit 4
Auxiliary Interrupt Flag. AI must be cleared by software before exiting the interrupt service routine, after the source
of the interrupt is cleared. Otherwise, the interrupt occurs again. Setting AI in software generates an Auxiliary
Interrupt, if enabled.
0 = No Auxiliary Interrupt detected (default).
1 = Auxiliary Interrupt detected.
WDTI
bit 3
Watchdog Timer Interrupt Flag. WDTI must be cleared by software before exiting the interrupt service routine.
Otherwise, the interrupt occurs again. Setting WDTI in software generates a watchdog time interrupt, if enabled. The
Watchdog timer can generate an interrupt or reset. The interrupt is available only if the reset action is disabled in
HCR0.
0 = No Watchdog Timer Interrupt Detected (default).
1 = Watchdog Timer Interrupt Detected.
ADC Results Low Byte (ADRESL)
7
6
5
4
3
2
1
0
Reset Value
SFR D9h
LSB
00h
ADRESL
bits 7−0
ADC Results Low Byte. This is the low byte of the ADC results.
Reading from this register clears the ADC interrupt; however, AI in EICON (SFR D8) must also be cleared.
ADC Results Middle Byte (ADRESM)
7
6
5
4
3
2
1
0
Reset Value
SFR DAh
00h
ADRESM
ADC Results Middle Byte. This is the middle byte of the ADC results for the MSC1200/01 and the most significant
byte for the MSC1202.
bits 7−0
ADC Results High Byte (ADRESH)
7
6
5
4
3
2
1
0
Reset Value
SFR DBh
MSB
00h
ADRESH
bits 7−0
ADC Results High Byte. This is the high byte and most significant byte of the ADC results for the MSC1200/01.
This is a sign-extended (Bipolar mode) or zero-padded (Unipolar mode) byte for the MSC1202 (that is, all 0s for
positive ADC or unipolar results and all 1s for negative ADC results).
69
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SBAS317E − APRIL 2004 − REVISED MAY 2006
ADC Control 0 (ADCON0)
7
6
5
4
3
2
1
0
Reset Value
SFR DCh
—
BOD
EVREF
VREFH
EBUF
PGA2
PGA1
PGA0
30h
BOD
bit 6
Burnout Detect. When enabled, this connects a positive current source to the positive channel and a negative
current source to the negative channel. If the channel is open circuit, then the ADC results will be full-scale (buffer
must be enabled).
0 = Burnout Current Sources Off (default).
1 = Burnout Current Sources On.
EVREF
Enable Internal Voltage Reference. If an external voltage is used, the internal voltage reference should be disabled.
0 = Internal Voltage Reference Off for external reference.
bit 5
1 = Internal Voltage Reference On (default). Note that in this mode, REFIN− must be connected to AGND.
VREFH
Voltage Reference High Select. The internal voltage reference can be selected to be 2.5V or 1.25V.
0 = REFOUT/REF IN+ is 1.25V.
bit 4
1 = REFOUT/REF IN+ is 2.5V (default).
EBUF
Enable Buffer. Enables the input buffer to provide higher input impedance but limits the input voltage range and
bit 3
dissipates more power.
0 = Buffer disabled (default).
1 = Buffer enabled. Input signal limited to AV
− 1.5V.
DD
PGA2−0
Programmable Gain Amplifier. Sets the gain for the PGA from 1 to 128.
bits 2−0
PGA2
PGA1
PGA0
GAIN
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1 (default)
2
4
8
16
32
64
128
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SBAS317E − APRIL 2004 − REVISED MAY 2006
ADC Control 1 (ADCON1)
7
6
5
4
3
2
1
0
Reset Value
SFR DDh
OF_UF
POL
SM1
SM0
—
CAL2
CAL1
CAL0
00h
OF_UF
Overflow/Underflow. If this bit is set, the data in the Summation register is invalid; either an overflow or underflow
bit 6
occurred. This bit is cleared by writing a ‘0’ to it.
POL
Polarity. Polarity of the ADC result and Summation register.
bit 6
0 = Bipolar.
1 = Unipolar.
DIGITAL OUTPUT
(ADRESH:ADRESM:ADRESL)
MSC1200
(1)
MSC1202
MSC1201
7FFFFFh
000000h
800000h
FFFFFFh
000000h
000000h
POL
ANALOG INPUT
+FSR
007FFFh
000000h
FF8000h
00FFFFh
000000h
000000h
ZERO
0
−FSR
+FSR
ZERO
1
−FSR
(1)
The MSC1202 ADC result is sign-extended into ADRESH.
SM1−0
Settling Mode. Selects the type of filter or auto-select which defines the digital filter settling characteristics.
bits 5−4
SM1
SM0
SETTLING MODE
0
0
1
1
0
1
0
1
Auto
Fast Settling Filter
2
Sinc Filter
3
Sinc Filter
CAL2−0
Calibration Mode Control Bits. Writing to this register initiates calibration.
bits 2−0
CAL2
CAL1
CAL0
CALIBRATION MODE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No Calibration (default)
Self-Calibration, Offset and Gain
Self-Calibration, Offset only
Self-Calibration, Gain only
System Calibration, Offset only (requires external signal)
System Calibration, Gain only (requires external signal)
Reserved
Reserved
:
NOTE Read value—000b.
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SBAS317E − APRIL 2004 − REVISED MAY 2006
ADC Control 2 (ADCON2)
7
6
5
4
3
2
1
0
Reset Value
SFR DEh
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
1Bh
DR7−0
bits 7−0
Decimation Ratio LSB (refer to ADCON3, SFR DFh).
ADC Control 3 (ADCON3)
7
6
5
4
3
2
1
0
Reset Value
SFR DFh
—
—
—
—
—
DR10
DR9
DR8
06h
DR10−8
Decimation Ratio Most Significant 3 Bits.
fMOD
fCLK
bits 2−0
The ADC output data rate is:
where fMOD
+
.
Decimation Ratio
(
)
ACLK)1 @ 64
Accumulator (A or ACC)
7
6
5
4
3
2
1
0
Reset Value
SFR E0h
ACC.7
ACC.6
ACC.5
ACC.4
ACC.3
ACC.2
ACC.1
ACC.0
00h
ACC.7−0
Accumulator. This register serves as the accumulator for arithmetic and logic operations.
bits 7−0
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Summation/Shifter Control (SSCON)
7
6
5
4
3
2
1
0
Reset Value
SFR E1h
SSCON1
SSCON0
SCNT2
SCNT1
SCNT0
SHF2
SHF1
SHF0
00h
The Summation register is powered down when the ADC is powered down. If all zeroes are written to this register, the 32-bit
SUMR3−0 registers will be cleared. The Summation registers will do sign-extend if Bipolar Mode is selected in ADCON1.
SSCON1−0 Summation/Shift Count.
bits 7−6
SSCON1 SSCON0
SCNT2
SCNT1
SCNT0
SHF2
SHF1
SHF0
DESCRIPTION
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
0
Clear Summation Register
0
1
0
0
0
0
CPU Summation on Write to SUMR0 (sum count/shift ignored)
CPU Subtraction on Write to SUMR0 (sum count/shift ignored)
CPU Shift only
1
0
0
0
0
0
x
x
x
Note (1)
x
Note (1)
x
Note (1)
x
Note (1)
Note (1)
Note (1)
Note (1)
Note (1)
Note (1)
ADC Summation only
Note (1)
Note (1)
Note (1)
ADC Summation completes, then shift completes
(1)
Refer to register bit definition.
SCNT2−0
Summation Count. When the summation is complete an interrupt will be generated unless masked. Reading the
bits 5−3
SUMR0 register clears the interrupt.
SCNT2
SCNT1
SCNT0
SUMMATION COUNT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
4
8
16
32
64
128
256
SHF2−0
Shift Count.
bits 2−0
SHF2
SHF1
SHF0
SHIFT
DIVIDE
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
4
8
16
32
64
128
256
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Summation 0 (SUMR0)
7
6
5
4
3
2
1
0
Reset Value
SFR E2h
LSB
00h
SUMR0
bits 7−0
Summation 0. This is the least significant byte of the 32-bit summation register, or bits 0 to 7.
Write: Will cause values in SUMR3−0 to be added to the summation register.
Read: Will clear the Summation Interrupt.
Summation 1 (SUMR1)
7
6
5
4
3
2
1
0
Reset Value
SFR E3h
00h
SUMR1
Summation 1. This is the most significant byte of the lowest 16 bits of the summation register, or bits 8−15.
bits 7−0
Summation 2 (SUMR2)
7
6
5
4
3
2
1
0
Reset Value
SFR E4h
00h
SUMR2
Summation 2. This is the most significant byte of the lowest 24 bits of the summation register, or bits 16−23.
bits 7−0
Summation 3 (SUMR3)
7
6
5
4
3
2
1
0
Reset Value
SFR E5h
MSB
00h
SUMR3
bits 7−0
Summation 3. This is the most significant byte of the 32-bit summation register, or bits 24−31.
Offset DAC (ODAC)
7
6
5
4
3
2
1
0
Reset Value
SFR E6h
00h
ODAC
bits 7−0
Offset DAC. This register will shift the input by up to half of the ADC full-scale input range. The Offset DAC
value is summed into the ADC prior to conversion. Writing 00h or 80h to ODAC turns off the Offset DAC. The offset
DAC should be cleared prior to calibration, since the offset DAC analog output is applied directly to the ADC input.
bit 7
Offset DAC Sign Bit.
0 = Positive
1 = Negative
*VREF
2 @ PGA
ODAC [6 : 0]
127
bit7
@ ǒ
Ǔ@ *1
(
)
bit 6−0
Offset +
NOTE: ODAC cannot be used to offset the analog inputs so that the buffer can be used for signals within 50mV of AGND.
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Low Voltage Detect Control (LVDCON)
7
6
5
4
3
2
1
0
Reset Value
SFR E7h
ALVDIS
0
0
0
ALVD3
ALVD2
ALVD1
ALVD0
8Fh
ALVDIS
Analog Low Voltage Detect Disable.
bit 7
0 = Enable Detection of Low Analog Supply Voltage (ALVD flag and interrupt are set when AV
< ALVD threshold)
DD
1 = Disable Detection of Low Analog Supply Voltage
ALVD3−0
Analog Low Voltage Detect. Sets ALVD threshold.
0000: 4.6V
bits 7−4
0001: 4.2V
0010: 3.8V
0011: 3.6V
0100: 3.3V
0101: 3.1V
0110: 2.9V
0111: 2.7V
1000: Reserved
1001: Reserved
1010: Reserved
1011: Reserved
1100: Reserved
1101: Reserved
1110: Reserved
1111: Reserved
Extended Interrupt Enable (EIE)
7
6
5
4
3
2
1
0
Reset Value
SFR E8h
1
1
1
EWDI
EX5
EX4
EX3
EX2
E0h
EWDI
Enable Watchdog Interrupt. This bit enables/disables the watchdog interrupt. The Watchdog timer is enabled by
bit 4
the WDTCON (SFR FFh) and PDCON (SFR F1h) registers.
0 = Disable the Watchdog Interrupt
1 = Enable Interrupt Request Generated by the Watchdog Timer
EX5
External Interrupt 5 Enable. This bit enables/disables external interrupt 5.
0 = Disable External Interrupt 5
bit 3
1 = Enable External Interrupt 5
EX4
External Interrupt 4 Enable. This bit enables/disables external interrupt 4.
0 = Disable External Interrupt 4
bit 2
1 = Enable External Interrupt 4
EX3
External Interrupt 3 Enable. This bit enables/disables external interrupt 3.
0 = Disable External Interrupt 3
bit 1
1 = Enable External Interrupt 3
EX2
External Interrupt 2 Enable. This bit enables/disables external interrupt 2.
0 = Disable External Interrupt 2
bit 0
1 = Enable External Interrupt 2
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Hardware Product Code 0 (HWPC0) (read-only)
7
6
5
4
3
2
1
0
Reset Value
SFR E9h
0
0
0
0
0
0
DEVICE
MEMORY
0000_00xxb
HWPC0.7−0 Hardware Product Code LSB. Read-only.
bits 7−0
FLASH
MEMORY
DEVICE
MEMORY
MODEL
0
0
1
1
0
1
0
1
MSC1200Y2, MSC1201Y2
MSC1200Y3, MSC1201Y3
MSC1202Y2
4kB
8kB
4kB
8kB
MSC1202Y3
Hardware Product Code 1 (HWPC1) (read-only)
7
6
5
4
3
2
1
0
Reset Value
SFR EAh
0
0
1
0
0
0
0
0
20h
HWPC1.7−0 Hardware Product Code MSB. Read-only.
bits 7−0
Hardware Version (HWVER)
7
6
5
4
3
2
1
0
Reset Value
SFR EBh
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Flash Memory Control (FMCON)
7
6
5
4
3
2
1
0
Reset Value
SFR EEh
0
PGERA
0
FRCM
0
BUSY
SPM
FPM
02h
PGERA
Page Erase. Available in both user and program modes.
bit 6
0 = Disable Page Erase Mode
1 = Enable Page Erase Mode (automatically set by page_erase Boot ROM routine)
FRCM
Frequency Control Mode.
bit 4
0 = Bypass (default)
1 = Use Delay Line. Recommended for saving power.
BUSY
Write/Erase BUSY Signal.
0 = Idle or Available
1 = Busy
bit 2
SPM
Serial Programming Mode. Read-only.
bit 1
0 = Indicates the device is not in serial programming mode.
1 = Indicates the device is in serial programming mode (if FPM also = 1).
FPM
Flash Programming Mode. Read-only.
bit 0
0 = Indicates the device is operating in UAM.
1 = Indicates the device is operating in programming mode.
Flash Memory Timing Control (FTCON)
7
6
5
4
3
2
1
0
Reset Value
SFR EFh
FER3
FER2
FER1
FER0
FWR3
FWR2
FWR1
FWR0
A5h
Refer to Flash Memory Characteristics.
FER3−0
bits 7−4
Set Erase. Flash Erase Time = (1 + FER) • (MSEC + 1) • tCLK. This can be broken into multiple, shorter erase times.
For more Information, see Application Report SBAA137, Incremental Flash Memory Page Erase, available for
download from www.ti.com.
Industrial temperature range: 11ms
Commercial temperature range: 5ms
FWR3−0
bits 3−0
Set Write. Set Flash Write Time = (1 + FWR) • (USEC + 1) • 5 • tCLK. Total writing time will be longer. For more
Information, see Application Report SBAA087, In-Application Flash Programming, available for download from
www.ti.com.
Range: 30µs to 40µs.
B Register (B)
7
6
5
4
3
2
1
0
Reset Value
SFR F0h
00h
B.7−0
B Register. This register serves as a second accumulator for certain arithmetic operations.
bits 7−0
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Power-Down Control (PDCON)
7
6
5
4
3
2
1
0
Reset Value
SFR F1h
PDICLK
PDIDAC
PDI2C
0
PDADC
PDWDT
PDST
PDSPI
6Fh
Turning peripheral modules off puts the MSC120x in the lowest power mode.
PDICLK
Internal Clock Control.
bit 7
0 = Internal Oscillator and PLL On (Internal Oscillator or PLL mode)
1 = Internal Oscillator and PLL Power Down (External Clock mode). Bit is not active on IOM or PLL mode.
PDIDAC
IDAC Control.
bit 6
0 = IDAC On
1 = IDAC Power Down (default)
PDI2C
I2C Control.
2
bit 5
0 = I C On (only when PDSPI = 1)
2
1 = I C Power Down (default)
PDADC
ADC Control.
bit 3
0 = ADC On
1 = ADC, VREF, and Summation registers are powered down (default).
PDWDT
Watchdog Timer Control.
bit 2
0 = Watchdog Timer On
1 = Watchdog Timer Power Down (default)
PDST
System Timer Control.
bit 1
0 = System Timer On
1 = System Timer Power Down (default)
PDSPI
SPI System Control.
bit 0
0 = SPI System On
1 = SPI System Power Down (default)
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SBAS317E − APRIL 2004 − REVISED MAY 2006
PSEN/ALE Select (PASEL)
7
6
5
4
3
2
1
0
Reset Value
SFR F2h
PSEN4
PSEN3
PSEN2
PSEN1
PSEN0
0
0
0
00h
PSEN2−0
PSEN Mode Select. Defines the output on P3.6 in UAM or SFPM.
00000: General-purpose I/O (default)
bits 7−3
00001: SYSCLK
00011: Internal PSEN (refer to Figure 5 for timing)
00101: Internal ALE (refer to Figure 5 for timing)
00111: f
(buffered XIN oscillator clock)
OSC
01001: Memory WR (MOVX write)
(1)
01011: T0 Out (overflow)
(1)
01101: T1 Out (overflow)
(2)
01111: f
MOD
(2)
10001: SYSCLK/2 (toggles on rising edge)
(2)
10011: Internal PSEN/2
(2)
10101: Internal ALE/2
(2)
10111: f
OSC
(2)
11001: Memory WR/2 (MOVX write)
(2)
11011: T0 Out/2 (overflow)
(2)
11101: T1 Out/2 (overflow)
(2)
11111: f
/2
MOD
(1)
(2)
One period of these signals equal to t
Duty cycle is 50%.
.
CLK
Phase Lock Loop Low (PLLL)
7
6
5
4
3
2
1
0
Reset Value
SFR F4h
PLL7
PLL6
PLL5
PLL4
PLL3
PLL2
PLL1
PLL0
xxh
PLL7−0
bits 7−0
PLL Counter Value Least Significant Bit.
PLL Frequency = External Crystal Frequency • (PLL9:0 + 1).
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Phase Lock Loop High (PLLH)
7
6
5
4
3
2
1
0
Reset Value
SFR F5h
CLKSTAT2
CLKSTAT1
CLKSTAT0
PLLLOCK
0
0
PLL9
PLL8
xxh
CLKSTAT2−0 Active Clock Status (read-only). Derived from HCR2 setting; refer to Table 3.
bits 7−5
000: Reserved
001: Reserved
010: Reserved
011: External Clock Mode
100: PLL High-Frequency (HF) Mode (must read PLLLOCK to determine active clock status)
101: PLL Low-Frequency (LF) Mode (must read PLLLOCK to determine active clock status)
110: Internal Oscillator High-Frequency (HF) Mode
111: Internal Oscillator Low-Frequency (LF) Mode
PLLLOCK PLL Lock Status and Status Enable.
bit 4
For Write (PLL Lock Status Enable):
0 = No Effect
1 = Enable PLL Lock Detection (must wait 20ms before PLLLOCK read status is valid).
For Read (PLL Lock Status):
0 = PLL Not Locked (PLL may be inactive; refer to Table 3 for active clock mode)
1 = PLL Locked (PLL is active clock).
PLL9−8
PLL Counter Value Most Significant 2 Bits (refer to PLLL, SFR F4h).
bits 1−0
Analog Clock (ACLK)
7
6
5
4
3
2
1
0
Reset Value
SFR F6h
0
FREQ6
FREQ5
FREQ4
FREQ3
FREQ2
FREQ1
FREQ0
03h
FREQ6−0 Clock Frequency − 1. This value + 1 divides the system clock to create the ADC clock.
bits 6−0
.
fCLK
ACLK ) 1
fACLK
fOSC
fACLK
fMOD
+
+
, where fCLK +
SYSCLK divider
64
fMOD
ADC Data Rate + fDATA
+
Decimation Ratio
System Reset (SRST)
7
6
5
4
3
2
1
0
Reset Value
SFR F7h
0
0
0
0
0
0
0
RSTREQ
00h
RSTREQ
Reset Request. Setting this bit to ‘1’ and then clearing to ‘0’ will generate a system reset.
bit 0
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SBAS317E − APRIL 2004 − REVISED MAY 2006
Extended Interrupt Priority (EIP)
7
6
5
4
3
2
1
0
Reset Value
SFR F8h
1
1
1
PWDI
PX5
PX4
PX3
PX2
E0h
PWDI
Watchdog Interrupt Priority. This bit controls the priority of the watchdog interrupt.
0 = The watchdog interrupt is low priority.
bit 4
1 = The watchdog interrupt is high priority.
PX5
External Interrupt 5 Priority. This bit controls the priority of external interrupt 5.
0 = External interrupt 5 is low priority.
bit 3
1 = External interrupt 5 is high priority.
PX4
External Interrupt 4 Priority. This bit controls the priority of external interrupt 4.
0 = External interrupt 4 is low priority.
bit 2
1 = External interrupt 4 is high priority.
PX3
External Interrupt 3 Priority. This bit controls the priority of external interrupt 3.
0 = External interrupt 3 is low priority.
bit 1
1 = External interrupt 3 is high priority.
PX2
External Interrupt 2 Priority. This bit controls the priority of external interrupt 2.
0 = External interrupt 2 is low priority.
bit 0
1 = External interrupt 2 is high priority.
Seconds Timer Interrupt (SECINT)
7
6
5
4
3
2
1
0
Reset Value
SFR F9h
WRT
SECINT6
SECINT5
SECINT4
SECINT3
SECINT2
SECINT1
SECINT0
7Fh
This system clock is divided by the value of the 16-bit register MSECH:MSECL. Then, that 1ms timer tick is divided by the
register HMSEC which provides the 100ms signal used by this seconds timer. Therefore, this seconds timer can generate
an interrupt which occurs from 100ms to 12.8 seconds. Reading this register will clear the Seconds Interrupt. This Interrupt
can be monitored in the AIE register.
WRT
Write Control. Determines whether to write the value immediately or wait until the current count is finished.
Read = 0.
bit 7
0 = Delay Write Operation. The SEC value is loaded when the current count expires.
1 = Write Immediately. The counter is loaded once the CPU completes the write operation.
SECINT6−0 Seconds Count. Normal operation would use 100ms as the clock interval.
bits 6−0 Seconds Interrupt = (1 + SEC) • (HMSEC + 1) • (MSEC + 1) • tCLK
.
81
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ꢝ
ꢡ
ꢡ
ꢡ
ꢏ
ꢏ
ꢏ
ꢜ
ꢜ
ꢜ
ꢢ
ꢢ
ꢢ
ꢚ
ꢚ
ꢚ
ꢚ
ꢜ
ꢢ
www.ti.com
SBAS317E − APRIL 2004 − REVISED MAY 2006
Milliseconds TImer Interrupt (MSINT)
7
6
5
4
3
2
1
0
Reset Value
SFR FAh
WRT
MSINT6
MSINT5
MSINT4
MSINT3
MSINT2
MSINT1
MSINT0
7Fh
The clock used for this timer is the 1ms clock, which results from dividing the system clock by the values in registers
MSECH:MSECL. Reading this register is necessary for clearing the interrupt; however, AI in EICON (SFR D8h) must also
be cleared.
WRT
Write Control. Determines whether to write the value immediately or wait until the current count is finished.
Read = 0.
bit 7
0 = Delay Write Operation. The MSINT value is loaded when the current count expires.
1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation.
MSINT6−0 Milliseconds Count. Normal operation would use 1ms as the clock interval.
bits 6−0 MS Interrupt Interval = (1 + MSINT) • (MSEC + 1) • tCLK
One Microsecond Timer (USEC)
7
6
5
4
3
2
1
0
Reset Value
SFR FBh
0
0
FREQ5
FREQ4
FREQ3
FREQ2
FREQ1
FREQ0
03h
FREQ5−0 Clock Frequency − 1. This value + 1 divides the system clock to create a 1µs Clock.
bits 5−0 USEC = CLK/(FREQ + 1). This clock is used to set Flash write time. See FTCON (SFR EFh).
One Millisecond TImer Low Byte (MSECL)
7
6
5
4
3
2
1
0
Reset Value
SFR FCh
MSECL7
MSECL6
MSECL5
MSECL4
MSECL3
MSECL2
MSECL1
MSECL0
9Fh
MSECL7−0 One Millisecond Timer Low Byte. This value in combination with the next register is used to create a 1ms clock.
bits 7−0 1ms = (MSECH • 256 + MSECL + 1) • tCLK. This clock is used to set Flash erase time. See FTCON (SFR EFh).
One Millisecond Timer High Byte (MSECH)
7
6
5
4
3
2
1
0
Reset Value
SFR FDh
MSECH7
MSECH6
MSECH5
MSECH4
MSECH3
MSECH2
MSECH1
MSECH0
0Fh
MSECH7−0 One Millisecond Timer High Byte. This value in combination with the previous register is used to create a 1ms clock.
bits 7−0 1ms = (MSECH • 256 + MSECL + 1) • tCLK
.
One Hundred Millisecond Timer (HMSEC)
7
6
5
4
3
2
1
0
Reset Value
SFR FEh
HMSEC7
HMSEC6
HMSEC5
HMSEC4
HMSEC3
HMSEC2
HMSEC1
HMSEC0
63h
WRT
Write Control. Determines whether to write the value immediately or wait until the current count is finished.
Read = 0.
HMSEC7−0 One Hundred Millisecond Timer. This clock divides the 1ms clock to create a 100ms clock.
bits 7−0
100ms = (MSECH • 256 + MSECL + 1) • (HMSEC + 1) • t
.
CLK
82
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ꢡꢏ
ꢡꢏ
ꢜ
ꢜ
ꢜ
ꢢ
ꢢ
ꢢ
ꢚ
ꢚ
ꢚ
ꢚ
ꢜ
ꢢ
www.ti.com
SBAS317E − APRIL 2004 − REVISED MAY 2006
Watchdog Timer (WDTCON)
7
6
5
4
3
2
1
0
Reset Value
SFR FFh
EWDT
DWDT
RWDT
WDCNT4
WDCNT3
WDCNT2
WDCNT1
WDCNT0
00h
EWDT
Enable Watchdog (R/W).
bit 7
Write 1/Write 0 sequence sets the Watchdog Enable Counting bit.
DWDT
Disable Watchdog (R/W).
bit 6
Write 1/Write 0 sequence clears the Watchdog Enable Counting bit.
RWDT
Reset Watchdog (R/W).
bit 5
Write 1/Write 0 sequence restarts the Watchdog Counter.
WDCNT4−0 Watchdog Count (R/W).
bits 4−0
Watchdog expires in (WDCNT + 1) • HMSEC to (WDCNT + 2) • HMSEC, if the sequence is not asserted. There is
an uncertainty of 1 count.
NOTE: If HCR0.3 (EWDR) is set and the watchdog timer expires, a system reset is generated. If HCR0.3 (EWDR) is
cleared and the watchdog timer expires, an interrupt is generated (see Table 6).
83
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
MSC1200Y2PFBR
MSC1200Y2PFBRG4
MSC1200Y2PFBT
OBSOLETE
OBSOLETE
ACTIVE
TQFP
TQFP
TQFP
PFB
48
48
48
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
MSC1200Y2
PFB
PFB
250
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSC1200Y2
MSC1200Y2
MSC1200Y3
MSC1200Y2PFBTG4
ACTIVE
TQFP
PFB
48
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
MSC1200Y3PFBR
MSC1200Y3PFBRG4
MSC1200Y3PFBT
OBSOLETE
OBSOLETE
ACTIVE
TQFP
TQFP
TQFP
PFB
PFB
PFB
48
48
48
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
250
250
250
250
250
250
2500
2500
250
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSC1200Y3
MSC1200Y3
MSC1200Y3PFBTG4
MSC1201Y3RHHT
MSC1201Y3RHHTG4
MSC1202Y2RHHT
MSC1202Y2RHHTG4
MSC1202Y3RHHR
MSC1202Y3RHHRG4
MSC1202Y3RHHT
MSC1202Y3RHHTG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TQFP
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
PFB
RHH
RHH
RHH
RHH
RHH
RHH
RHH
RHH
48
36
36
36
36
36
36
36
36
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Green (RoHS
& no Sb/Br)
MSC
1201Y3
Green (RoHS
& no Sb/Br)
MSC
1201Y3
Green (RoHS
& no Sb/Br)
MSC
1202Y2
Green (RoHS
& no Sb/Br)
MSC
1202Y2
Green (RoHS
& no Sb/Br)
MSC
1202Y3
Green (RoHS
& no Sb/Br)
MSC
1202Y3
Green (RoHS
& no Sb/Br)
MSC
1202Y3
Green (RoHS
& no Sb/Br)
MSC
1202Y3
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSC1200Y2PFBT
MSC1200Y3PFBT
MSC1201Y3RHHT
MSC1202Y2RHHT
MSC1202Y3RHHR
MSC1202Y3RHHT
TQFP
TQFP
VQFN
VQFN
VQFN
VQFN
PFB
PFB
RHH
RHH
RHH
RHH
48
48
36
36
36
36
250
250
250
250
2500
250
177.8
177.8
180.0
180.0
330.0
180.0
16.4
16.4
16.4
16.4
16.4
16.4
9.6
9.6
6.3
6.3
6.3
6.3
9.6
9.6
6.3
6.3
6.3
6.3
1.5
1.5
1.1
1.1
1.1
1.1
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
Q2
Q2
Q2
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSC1200Y2PFBT
MSC1200Y3PFBT
MSC1201Y3RHHT
MSC1202Y2RHHT
MSC1202Y3RHHR
MSC1202Y3RHHT
TQFP
TQFP
VQFN
VQFN
VQFN
VQFN
PFB
PFB
RHH
RHH
RHH
RHH
48
48
36
36
36
36
250
250
250
250
2500
250
210.0
210.0
210.0
210.0
367.0
210.0
185.0
185.0
185.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
38.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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