MSP430AFE223IPWR [TI]
MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器型号: | MSP430AFE223IPWR |
厂家: | TEXAS INSTRUMENTS |
描述: | MIXED SIGNAL MICROCONTROLLER |
文件: | 总47页 (文件大小:904K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
www.ti.com
SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
MIXED SIGNAL MICROCONTROLLER
1
FEATURES
•
Low Supply Voltage Range: 1.8 V to 3.6 V
•
Up to Three 24-Bit Sigma-Delta
Analog-to-Digital (A/D) Converters With
Differential PGA Inputs
•
Ultra-Low Power Consumption
–
–
–
Active Mode: 220 µA at 1 MHz, 2.2 V
Standby Mode: 0.5 µA
•
•
16-Bit Timer_A With Three Capture/Compare
Registers
Off Mode (RAM Retention): 0.1 µA
Serial Communication Interface (USART),
Asynchronous UART or Synchronous SPI
Selectable by Software
•
•
Five Power-Saving Modes
Ultra-Fast Wake-Up From Standby Mode in
Less Than 1 µs
•
•
•
16-Bit Hardware Multiplier
Brownout Detector
•
•
16-Bit RISC Architecture, up to 12-MHz System
Clock
Supply Voltage Supervisor/Monitor with
Programmable Level Detection
Basic Clock Module Configurations
–
Internal Frequencies up to 12 MHz With
Two Calibrated Frequencies
•
Serial Onboard Programming, No External
Programming Voltage Needed Programmable
Code Protection by Security Fuse
–
Internal Very-Low-Power Low-Frequency
(LF) Oscillator
•
•
•
On-Chip Emulation Module
–
–
–
High-Frequency (HF) Crystal up to 16 MHz
Resonator
Family Members are Summarized in Table 1.
For Complete Module Descriptions, See the
MSP430x2xx Family User's Guide, Literature
Number SLAU144
External Digital Clock Source
DESCRIPTION
The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.
The MSP430AFE2x3 devices are ultra-low-power mixed signal microcontrollers integrating three independent
24-bit sigma-delta A/D converters, one 16-bit timer, one 16-bit hardware multiplier, USART communication
interface, watchdog timer, and 11 I/O pins.
The MSP430AFE2x2 devices are identical to the MSP430AFE2x3, except that there are only two 24-bit
sigma-delta A/D converters integrated.
The MSP430AFE2x1 devices are identical to the MSP430AFE2x3, except that there is only one 24-bit
sigma-delta A/D converter integrated.
Available family members are summarized in Table 1.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
www.ti.com
Table 1. Family Members(1)
USART
(UART/
SPI)
Flash
(KB)
SRAM
(Byte)
SD24_A
Converters
16-Bit
MPY
Package
Type(3)
Device
EEM
Timer_A(2)
Clocks
I/O
HF, DCO,
VLO
MSP430AFE253IPW
MSP430AFE233IPW
MSP430AFE223IPW
MSP430AFE252IPW
MSP430AFE232IPW
MSP430AFE222IPW
MSP430AFE251IPW
MSP430AFE231IPW
MSP430AFE221IPW
16
8
512
512
256
512
512
256
512
512
256
1
1
1
1
1
1
1
1
1
3
3
3
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
3
3
3
3
3
3
3
3
3
1
1
1
1
1
1
1
1
1
11
11
11
11
11
11
11
11
11
24-TSSOP
24-TSSOP
24-TSSOP
24-TSSOP
24-TSSOP
24-TSSOP
24-TSSOP
24-TSSOP
24-TSSOP
HF, DCO,
VLO
HF, DCO,
VLO
4
HF, DCO,
VLO
16
8
HF, DCO,
VLO
HF, DCO,
VLO
4
HF, DCO,
VLO
16
8
HF, DCO,
VLO
HF, DCO,
VLO
4
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(3) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Development Tool Support
All MSP430™ microcontrollers include an Embedded Emulation Module (EEM) that allows advanced debugging
and programming through easy-to-use development tools. Recommended hardware options include:
•
Debugging and Programming Interface
–
–
MSP-FET430UIF (USB)
MSP-FET430PIF (Parallel Port)
•
•
Debugging and Programming Interface with Target Board
MSP-TS430PW24
Production Programmer
–
–
MSP-GANG430
2
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
www.ti.com
SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
Functional Block Diagram
AVCC AVSS
P2.x
DVCC DVSS
P1.x
XT2IN XT2OUT
3
8
ACLK
Hardware
Multiplier
(16x16)
Port P2
Port P1
Basic
Clock
System+
16KB
8KB
4KB
512B
512B
256B
3 I/O
8 I/O
Interrupt
capability
Pull-up/
down
Interrupt
capability
Pull-up/
down
SMCLK
MPY,
MPYS,
MAC,
Flash
RAM
MCLK
MACS
resistors
resistors
12MHz
CPU
MAB
MDB
incl. 16
Registers
Emulation
2BP
Timer_A3
SD24_A
(w/o BUF)
USART0
Watchdog
WDT+
JTAG
Interface
BOR
UART
or SPI
Function
3 CC
Registers
3 Converter
2 Converter
1 Converter
SVS/SVM
15/16-bit
Spy-Bi
Wire
RST/NMI
Pin Designation, MSP430AFE2x3IPW
A0.0+
1
2
24
23
22
21
20
19
18
17
16
15
14
13
P2.0/STE0/TA0/TDI/TCLK
P1.7/UCLK0/TA1/TDO/TDI
P1.6/SOMI0/TA2/TCK
P1.5/SIMO0/SVSOUT/TMS
P1.4/URXD0/SD2DO
P1.3/UTXD0/SD1DO
P1.2/TA0/SD0DO
P1.1/TA1/SDCLK
DVCC
A0.0-
A1.0+
3
A1.0-
4
AVCC
5
AVSS
6
MSP430AFE2x3
VREF
A2.0+
7
8
A2.0-
9
TEST/SBWTCK
10
11
12
P2.7/XT2OUT
RST/NMI/SBWTDIO
P1.0/SVSIN/TACLK/SMCLK/TA2
P2.6/XT2IN
DVSS
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
www.ti.com
Pin Designation, MSP430AFE2x2IPW
A0.0+
1
2
24
23
22
21
20
19
18
17
16
15
14
13
P2.0/STE0/TA0/TDI/TCLK
A0.0-
P1.7/UCLK0/TA1/TDO/TDI
P1.6/SOMI0/TA2/TCK
P1.5/SIMO0/SVSOUT/TMS
P1.4/URXD0
A1.0+
3
A1.0-
4
AVCC
5
AVSS
6
P1.3/UTXD0/SD1DO
P1.2/TA0/SD0DO
P1.1/TA1/SDCLK
DVCC
MSP430AFE2x2
VREF
7
NC
NC
8
9
TEST/SBWTCK
10
11
12
P2.7/XT2OUT
RST/NMI/SBWTDIO
P1.0/SVSIN/TACLK/SMCLK/TA2
P2.6/XT2IN
DVSS
A. Connect NC pins to analog ground (AVSS)
Pin Designation, MSP430AFE2x1IPW
A0.0+
1
2
24
23
22
21
20
19
18
17
16
15
14
13
P2.0/STE0/TA0/TDI/TCLK
P1.7/UCLK0/TA1/TDO/TDI
P1.6/SOMI0/TA2/TCK
P1.5/SIMO0/SVSOUT/TMS
P1.4/URXD0
A0.0-
NC
3
NC
4
AVCC
5
AVSS
6
P1.3/UTXD0
MSP430AFE2x1
VREF
7
P1.2/TA0/SD0DO
P1.1/TA1/SDCLK
DVCC
NC
NC
8
9
TEST/SBWTCK
10
11
12
P2.7/XT2OUT
RST/NMI/SBWTDIO
P1.0/SVSIN/TACLK/SMCLK/TA2
P2.6/XT2IN
DVSS
B. Connect NC pins to analog ground (AVSS)
4
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
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SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
Table 2. Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
1
A0.0+
A0.0-
A1.0+
A1.0-
AVCC
AVSS
I
I
I
I
SD24_A positive analog input A0.0(1)
SD24_A negative analog input A0.0(1)
SD24_A positive analog input A1.0 (not available on MSP430AFE2x1)(1)
SD24_A negative analog input A1.0 (not available on MSP430AFE2x1)(1)
Analog supply voltage, positive terminal. Must not power up prior to DVCC.
Analog supply voltage, negative terminal
2
3
4
5
6
Input for an external reference voltage/
output for internal reference voltage (can be used as mid-voltage)
VREF
A2.0+
A2.0-
7
8
9
I/O
SD24_A positive analog input A2.0 (not available on MSP430AFE2x2 and
MSP430AFE2x1)(1)
I
I
SD24_A negative analog input A2.0 (not available on MSP430AFE2x2 and
MSP430AFE2x1)(1)
Selects test mode for JTAG pins on P1.5 to P1.7 and P2.0.
The device protection fuse is connected to TEST.
Spy-Bi-Wire test clock input for device programming and test.
TEST/SBWTCK
10
11
I
I
Reset or nonmaskable interrupt input
Spy-Bi-Wire test data input/output for device programming and test.
RST/NMI/SBWTDIO
General-purpose digital I/O pin
Analog input to supply voltage supervisor
Timer_A3, clock signal TACLK input
SMCLK signal output
P1.0/SVSIN/TACLK/SMCLK/TA2
12
I/O
Timer_A3, compare: Out2 Output
DVSS
13
14
Digital supply voltage, negative terminal
Input terminal of crystal oscillator
General-purpose digital I/O pin
P2.6/XT2IN
I/O
I/O
Output terminal of crystal oscillator
General-purpose digital I/O pin
P2.7/XT2OUT
DVCC
15
16
Digital supply voltage, positive terminal.
General-purpose digital I/O pin
P1.1/TA1/SDCLK
P1.2/TA0/SD0DO
P1.3/UTXD0/SD1DO
17
18
19
I/O
I/O
I/O
Timer_A3, capture: CCI1A and CCI1B inputs, compare: Out1 output
SD24_A bit stream clock output
General-purpose digital I/O pin
Timer_A3, capture: CCI0A and CCI0B inputs, compare: Out0 output
SD24_A bit stream data output for channel 0
General-purpose digital I/O pin
Transmit data out - USART0/UART mode
SD24_A bit stream data output for channel 1 (not available on MSP430AFE2x1)
General-purpose digital I/O pin
Receive data in - USART0/UART mode
SD24_A bit stream data output for channel 2 (not available on MSP430AFE2x2 and
MSP430AFE2x1)
P1.4/URXD0/SD2DO
20
21
22
I/O
I/O
I/O
General-purpose digital I/O
Slave in/master out of USART0/SPI mode
SVS: output of SVS comparator
JTAG test mode select. TMS is used as an input port for device programming and
test.
P1.5/SIMO0/SVSOUT/TMS
P1.6/SOMI0/TA2/TCK
General-purpose digital I/O pin
Slave out/master in of USART0/SPI mode
Timer_A3, compare: Out2 output
JTAG test clock. TCK is the clock input port for device programming and test.
General-purpose digital I/O pin
External clock input - USART0/UART or SPI mode, clock output - USART0/SPI
mode.
P1.7/UCLK0/TA1/TDO/TDI
23
I/O
Timer_A3, compare: Out1 output
JTAG test data output port. TDO/TDI data output or programming data input
terminal.
(1) It is recommended to short unused analog input pairs and connect them to analog ground.
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
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Table 2. Terminal Functions (continued)
TERMINAL
NAME
I/O
DESCRIPTION
NO.
General-purpose digital I/O pin
Slave transmit enable - USART0/SPI mode.
Timer_A3, compare: Out0 output
P2.0/STE0/TA0/TDI/TCLK
24
I/O
JTAG test data input or test clock input for device programming and test.
6
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
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SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
SHORT-FORM DESCRIPTION
Program Counter
Stack Pointer
PC/R0
CPU
The MSP430™ CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
R4
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
The CPU is integrated with 16 registers that provide
reduced
instruction
execution
time.
The
R5
register-to-register operation execution time is one
cycle of the CPU clock.
R6
R7
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator respectively. The remaining
registers are general-purpose registers.
R8
R9
Peripherals are connected to the CPU using data,
address, and control buses and can be handled with
all instructions.
R10
R11
Instruction Set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 3 shows examples of the three types of
instruction formats; Table 4 shows the address
modes.
R12
R13
R14
R15
Table 3. Instruction Word Formats
INSTRUCTION FORMAT
Dual operands, source-destination
EXAMPLE
ADD R4,R5
CALL R8
JNE
OPERATION
R4 + R5 → R5
Single operands, destination only
PC → (TOS), R8 → PC
Relative jump, unconditional/conditional
Jump-on-equal bit = 0
Table 4. Address Mode Descriptions
ADDRESS MODE
Register
S(1)
✓
D(2)
✓
SYNTAX
MOV Rs,Rd
EXAMPLE
OPERATION
R10 → R11
MOV R10,R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV &MEM,&TCDAT
MOV @Rn,Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
M(R10) → M(Tab+R6)
Symbolic (PC relative)
Absolute
✓
✓
✓
✓
Indirect
✓
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
M(R10) → R11
R10 + 2 → R10
Indirect autoincrement
Immediate
✓
✓
MOV @Rn+,Rm
MOV #X,TONI
#45 → M(TONI)
(1) S = source
(2) D = destination
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
www.ti.com
Operating Modes
The MSP430 microcontrollers have one active mode and five software-selectable low-power modes of operation.
An interrupt event can wake up the device from any of the five low-power modes, service the request, and
restore back to the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
•
Active mode ( AM)
All clocks are active.
Low-power mode 0 (LPM0)
–
•
–
–
CPU is disabled.
ACLK and SMCLK remain active. MCLK is disabled.
•
•
Low-power mode 1 (LPM1)
–
–
CPU is disabled ACLK and SMCLK remain active. MCLK is disabled.
DCO dc-generator is disabled if DCO not used in active mode.
Low-power mode 2 (LPM2)
–
–
–
–
CPU is disabled.
MCLK and SMCLK are disabled.
DCO dc-generator remains enabled.
ACLK remains active.
•
•
Low-power mode 3 (LPM3)
–
–
–
–
CPU is disabled.
MCLK and SMCLK are disabled.
DCO dc-generator is disabled.
ACLK remains active.
Low-power mode 4 (LPM4)
–
–
–
–
–
CPU is disabled.
ACLK is disabled.
MCLK and SMCLK are disabled.
DCO dc-generator is disabled.
Crystal oscillator is stopped.
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
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SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed), the
CPU goes into LPM4 immediately after power up.
Table 5. Interrupt Vector Addresses
SYSTEM
INTERRUPT
INTERRUPT SOURCE
INTERRUPT FLAG
WORD ADDRESS
PRIORITY
Power up
External reset
Watchdog
PORIFG
RSTIFG
WDTIFG
Reset
0FFFEh
15, highest
Flash key violation
KEYV
(2)
PC out-of-range(1)
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG
(Non)maskable,
(Non)maskable,
(Non)maskable
0FFFCh
14
(2) (3)
0FFFAh
0FFF8h
13
12
SD24CCTLx SD24OVIFG,
SD24CCTLx SD24IFG(2) (4)
SD24_A
Maskable
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
0FFECh
11
10
9
Watchdog Timer
USART0 Receive
USART0 Transmit
WDTIFG
URXIFG0
UTXIFG0
Maskable
Maskable
Maskable
8
7
Timer_A3
Timer_A3
TA0CCR0 CCIFG(4)
Maskable
Maskable
Maskable
6
TA0CCR1 CCIFG,
TA0CCR2 CCIFG,
TA0CTL TAIFG
P1IFG.0 to P1IFG.7(2) (4)
0FFEAh
5
(2) (4)
I/O Port P1 (eight flags)
0FFE8h
0FFE6h
0FFE4h
0FFE2h
0FFE0h
4
3
2
1
I/O Port P2 (three flags)
P2IFG.0 to P2IFG.2(2) (4)
Maskable
0, lowest
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address range.
(2) Multiple source flags
(3) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
(4) Interrupt flags are located in the module.
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
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Special Function Registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw
Bit can be read and written.
rw-0, 1
rw-(0), (1)
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device.
Table 6. Interrupt Enable 1
Address
00h
7
6
5
4
3
2
1
0
UTXIE0
rw-0
URXIE0
rw-0
ACCVIE
rw-0
NMIIE
rw-0
OFIE
rw-0
WDTIE
rw-0
WDTIE
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval
timer mode.
OFIE
Oscillator fault interrupt enable
NMIIE
(Non)maskable interrupt enable
ACCVIE
URXIE0
UTXIE0
Flash access violation interrupt enable
USART0: UART and SPI receive interrupt enable
USART0: UART and SPI transmit interrupt enable
Table 7. Interrupt Enable 2
Address
7
6
5
4
3
2
1
0
01h
Table 8. Interrupt Flag Register 1
Address
02h
7
6
5
4
3
2
1
0
UTXIFG0
rw-1
URXIFG0
rw-0
NMIIFG
rw-0
RSTIFG
rw-(0)
PORIFG
rw-(1)
OFIFG
rw-1
WDTIFG
rw-(0)
WDTIFG
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG
Flag set on oscillator fault
RSTIFG
PORIFG
NMIIFG
URXIFG0
UTXIFG0
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up.
Power-on reset interrupt flag. Set on VCC power up.
Set via RST/NMI-pin
USART0: UART and SPI receive interrupt flag
USART0: UART and SPI transmit interrupt flag
Table 9. Interrupt Flag Register 2
Address
03h
7
6
5
4
3
2
1
0
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SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
Table 10. Module Enable Register 1
Address
04h
7
6
5
4
3
2
1
0
UTXE0
URXE0
USPIE0
rw-0
rw-0
URXE0
USART0: UART mode receive enable
USART0: UART mode transmit enable
UTXE0
USPIE0
USART0: SPI mode transmit and receive enable
Table 11. Module Enable Register 2
Address
05h
7
6
5
4
3
2
1
0
Memory Organization
Table 12. Memory Organization
MSP430AFE22x
MSP430AFE23x
MSP430AFE25x
Memory
Size
4 KB
8 KB
16 KB
Main: interrupt vector
Main: code memory
Flash 0xFFFF to 0xFFE0
0xFFFF to 0xFFE0
0xFFFF to 0xE000
0xFFFF to 0xFFE0
0xFFFF to 0xC000
Flash
0xFFFF to 0xF000
Size
256 Byte
256 Byte
0x10FFh to 0x1000
256 Byte
0x10FFh to 0x1000
Information memory
Flash 0x10FFh to 0x1000
256 Byte
Size
512 Byte
0x03FF to 0x0200
512 Byte
0x03FF to 0x0200
RAM
0x02FF to 0x0200
16-bit
8-bit
8-bit SFR
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
Peripherals
Flash Memory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
•
Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
•
•
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
•
Segment A contains calibration data. After reset segment A is protected against programming and erasing. It
can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is
required.
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for an internal digitally controlled
oscillator (DCO), a high-frequency crystal oscillator, and an internal very-low-power low-frequency oscillator
(VLO). The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic
clock module provides the following clock signals:
•
•
•
Auxiliary clock (ACLK), sourced from the VLO
Main clock (MCLK), the system clock used by the CPU
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules
Table 13. DCO Calibration Data
(Provided From Factory in Flash Information Memory Segment A)
DCO FREQUENCY
CALIBRATION REGISTER
CALBC1_8MHZ
SIZE
byte
byte
byte
byte
ADDRESS
010FDh
010FCh
010FBh
010FAh
8 MHz
CALDCO_8MHZ
CALBC1_12MHZ
12 MHz
CALDCO_12MHZ
Brownout, Supply Voltage Supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off. The supply voltage supervisor (SVS) circuitry detects if supply voltage drops below a user-selectable
level and supports both supply voltage supervision (the device is automatically reset) and supply voltage
monitoring (SVM) (the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have
ramped to VCC(min) at that time. The user must ensure that the default DCO settings are not changed until VCC
reaches VCC(min) . If desired, the SVS circuit can be used to determine when VCC reaches VCC(min)
.
Digital I/O
There are two I/O ports implemented: 8-bit port P1 and 3-bit port P2.
•
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt condition is possible.
Edge-selectable interrupt input capability for all eight bits of port P1 and three bits of port P2.
Read/write access to port-control registers is supported by all instructions.
Each I/O has an individually programmable pullup/pulldown resistor.
Because there are only three I/O pins implemented from port P2, bits [5:1] of all port P2 registers read as 0, and
write data is ignored.
Watchdog Timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be disabled or configured as an interval timer and can generate interrupts at
selected time intervals.
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Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 14. Timer_A3 Signal Connections
OUTPUT PIN
NUMBER
INPUT PIN NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE OUTPUT
SIGNAL
MODULE BLOCK
24-PIN PW
24-PIN PW
12 - P1.0
TACLK
ACLK
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
NA
SMCLK
TACLK
TA0
12 - P1.0
18 - P1.2
18 - P1.2
18 - P1.2
24 - P2.0
TA0
CCR0
CCR1
CCR2
TA0
TA1
TA2
DVSS
DVCC
TA1
VCC
17 - P1.1
17 - P1.1
CCI1A
CCI1B
GND
17 - P1.1
23 - P1.7
TA1
DVSS
DVCC
DVSS
ACLK (internal)
DVSS
DVCC
VCC
CCI2A
CCI2B
GND
12 - P1.0
22 - P1.6
VCC
USART0
The MSP430AFE2xx devices have one hardware universal synchronous/asynchronous receive transmit
(USART0) peripheral module that is used for serial data communication. The USART0 module supports
synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit
and receive channels. The maximum operational frequency for the USART0 module is 8 MHz.
Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16x16, 16x8,
8x16, and 8x8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as
signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
SD24_A
The SD24_A module integrates up to three independent 24-bit sigma-delta A/D converters. Each channel is
designed with fully differential analog input pair and programmable gain amplifier input stage. In addition to
external analog inputs, an internal VCC sense and temperature sensor are also available.
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Peripheral File Map
Table 15. Peripherals With Word Access
Timer_A3
Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_A register
TACCR2
TACCR1
TACCR0
TAR
0x0176
0x0174
0x0172
0x0170
0x0166
0x0164
0x0162
0x0160
0x012E
0x013E
0x013C
0x013A
0x0138
0x0136
0x0134
0x0132
0x0130
0x012C
0x012A
0x0128
0x0120
0x0100
0x0102
0x0104
0x0106
0x0110
0x0112
0x0114
0x01AE
Capture/compare control 2
Capture/compare control 1
Capture/compare control 0
Timer_A control
TACCTL2
TACCTL1
TACCTL0
TACTL
Timer_A interrupt vector
Sum extend
TAIV
Hardware Multiplier
SUMEXT
RESHI
Result high word
Result low word
RESLO
Second operand
OP2
Multiply signed + accumulate/operand 1
Multiply + accumulate/operand 1
Multiply signed/operand 1
Multiply unsigned/operand 1
Flash control 3
MACS
MAC
MPYS
MPY
Flash Memory
FCTL3
Flash control 2
FCTL2
Flash control 1
FCTL1
Watchdog Timer+
Watchdog/timer control
General Control
WDTCTL
SD24CTL
SD24CCTL0
SD24CCTL1
SD24CCTL2
SD24MEM0
SD24MEM1
SD24MEM2
SD24IV
SD24_A
(also see Table 16)
Channel 0 Control
Channel 1Control
Channel 2 Control
Channel 0 conversion memory
Channel 1 conversion memory
Channel 2 conversion memory
SD24 Interrupt vector word register
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Table 16. Peripherals With Byte Access
SD24_A
(also see Table 15)
Channel 0 Input Control
Channel 1 Input Control
Channel 2 Input Control
Channel 0 Preload
SD24INCTL0
SD24INCTL1
SD24INCTL2
SD24PRE0
SD24PRE1
SD24PRE2
SD24CONF1
U0TXBUF
U0RXBUF
U0BR1
U0BR0
U0MCTL
U0RCTL
U0TCTL
U0CTL
0x00B0
0x00B1
0x00B2
0x00B8
0x00B9
0x00BA
0x00BF
0x0077
0x0076
0x0075
0x0074
0x0073
0x0072
0x0071
0x0070
0x0053
0x0058
0x0057
0x0056
0x0055
0x0042
0x002F
0x002E
0x002D
0x002C
0x002B
0x002A
0x0029
0x0028
0x0041
0x0027
0x0026
0x0025
0x0024
0x0023
0x0022
0x0021
0x0020
0x0005
0x0004
0x0003
0x0002
0x0001
0x0000
Channel 1 Preload
Channel 2 Preload
Reserved (Internal SD24_A Configuration 1)
Transmit buffer
USART0
Receive buffer
Baud rate
Baud rate
Modulation control
Receive control
Transmit control
USART control
Basic Clock System+
Basic clock system control 3
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
SVS control register (reset by brownout signal)
Port P2 selection 2
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
SVSCTL
P2SEL2
P2REN
P2SEL
Brownout, SVS
Port P2
Port P2 resistor enable
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
P2IE
P2IES
P2IFG
P2DIR
Port P2 output
P2OUT
P2IN
Port P2 input
Port P1
Port P1 selection 2 register
Port P1 resistor enable
Port P1 selection
P1SEL2
P1REN
P1SEL
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
P1IE
P1IES
P1IFG
P1DIR
Port P1 output
P1OUT
P1IN
Port P1 input
Special Function
SFR module enable 2
SFR module enable 1
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
ME2
ME1
IFG2
IFG1
IE2
IE1
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Absolute Maximum Ratings(1)
Voltage applied at VCC to VSS
Voltage applied to any pin(2)
-0.3 V to 4.1 V
-0.3 V to VCC + 0.3 V
±2 mA
Diode current at any device terminal
Unprogrammed device
Programmed device
-55°C to 150°C
-40°C to 85°C
(3)
Storage temperature, Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
(3) Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak
reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
Recommended Operating Conditions(1) (2)
MIN NOM
MAX UNIT
During program
execution(3)
1.8
3.6
3.6
V
V
(1)
VCC
Supply voltage
AVCC = DVCC = VCC
AVSS = DVSS = VSS
During program/erase
flash memory
2.2
VSS
TA
Supply voltage
0
V
Operating free-air temperature
-40
dc
dc
dc
85
4.15
9
°C
VCC = 1.8 V, Duty cycle = 50% ±10%
(maximum MCLK frequency)(1)(2) VCC = 2.7 V, Duty cycle = 50% ±10%
Processor frequency
fSYSTEM
MHz
(see Figure 1)
V
CC ≥ 3.3 V, Duty cycle = 50% ±10%
12
(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(3) The operating voltage range for SD24_A is 2.5 V to 3.6 V
Legend :
12 MHz
Supply voltage range
during flash memory
programming
9
MHz
Supply voltage range
during program execution
6.5 MHz
4.15 MHz
1.8 V
2.2 V
2.7 V
3.3 V 3.6 V
Supply Voltage − V
A. Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
B. If high frequency crystal used is above 12 MHz and selected to source CPU clock then MCLK divider should be
programmed appropriately to run CPU below 8 MHz.
Figure 1. Operating Area
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Active Mode Supply Current (into DVCC + AVCC) Excluding External Current(1)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX UNIT
fDCO = fMCLK = fSMCLK = DCO default
frequency (approximately 1 MHz),
fACLK = fVLO = 12 kHz,
Program executes in flash,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
2.2 V
220
Active mode (AM)
current at 1 MHz
IAM, 1MHz
µA
3 V
350
4.0
fDCO = fMCLK = fSMCLK = 12 MHz,
fACLK = fVLO = 12 kHz,
Program executes in flash,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
Active mode (AM)
current at 12 MHz
IAM, 12MHz
3.3 V
4.5
mA
(1) All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
Typical Characteristics – Active-Mode Supply Current (Into DVCC + AVCC)
4
3.5
3
5
4.5
4
fDCO = 12 MHz
VCC = 3 V,
TA = 85°C
3.5
3
VCC = 3 V,
TA = 25°C
fDCO = 8 MHz
2.5
2
VCC = 2.2 V,
TA = 85°C
2.5
2
1.5
1
1.5
1
VCC = 2.2 V,
TA = 25°C
fDCO = 1 MHz
0.5
0
0.5
0
1.5 1.75
2
2.25 2.5 2.75
3
3.25 3.5 3.75
4
0
2
4
6
8
fDCO - DCO Frequency - MHz
10
12
VCC - Supply Voltage - V
Figure 2. Active-Mode Current vs VCC, TA = 25°C
Figure 3. Active-Mode Current vs DCO Frequency
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MAX UNIT
(1)
Low-Power-Mode Supply Currents (Into VCC) Excluding External Current
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
fMCLK = 0 MHz,
fSMCLK = fDCO = DCO default frequency
(approximately 1 MHz),
fACLK = fVLO = 12 kHz,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
Low-power mode 0
(LPM0) current(2)
ILPM0
25°C
2.2 V
65
µA
µA
fMCLK = fSMCLK = 0 MHz,
fDCO = DCO default frequency
(approximately 1 MHz),
fACLK = fVLO = 12 kHz,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
Low-power mode 2
(LPM2) current(3)
ILPM2
25°C
25°C
2.2 V
22
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = fVLO = 12 kHz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
Low-power mode 3
(LPM3) current(3)
ILPM3,VLO
2.2 V
2.2 V
0.5
1.0
µA
µA
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = fVLO = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
25°C
85°C
0.1
1.1
0.7
2.5
Low-power mode 4
(LPM4) current(4)
ILPM4
(1) All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
(2) Current for brownout and WDT clocked by SMCLK included.
(3) Current for brownout and WDT clocked by ACLK included.
(4) Current for brownout included.
Typical Characteristics – LPM4 Current
6.0
5.0
4.0
3.0
2.0
1.0
0.0
VCC = 3.6 V
VCC = 3 V
VCC = 2.2 V
VCC = 1.8 V
-40
-20
0
20
TA - Temperature - °C
Figure 4. ILPM4 -- LPM4 Current vs Temperature
40
60
80
100
120
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Schmitt-Trigger Inputs (Ports Px and RST/NMI)
PARAMETER
TEST CONDITIONS
VCC
MIN
0.45 VCC
1.35
TYP
MAX UNIT
0.75 VCC
VIT+
Positive-going input threshold voltage
V
V
3 V
2.25
0.55 VCC
1.65
0.25 VCC
0.75
VIT-
Negative-going input threshold voltage
3 V
3 V
Vhys
RPull
CI
Input voltage hysteresis (VIT+ - VIT-
)
0.3
1.0
V
Pullup/pulldown resistor
(not RST/NMI pin)
For pullup: VIN = VSS;
For pulldown: VIN = VCC
3 V
20
35
5
50
kΩ
pF
Input capacitance
VIN = VSS or VCC
Leakage Current (Ports Px)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
±50 nA
(1)(2)
Ilkg(Px.y)
High-impedance leakage current
3 V
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
Outputs (Ports Px)
PARAMETER
TEST CONDITIONS
IOH(max) = -6 mA(1)
IOL(max) = 6 mA(1)
VCC
3 V
3 V
MIN
TYP
MAX UNIT
VOH
VOL
High-level output voltage
Low-level output voltage
V
CC – 0.2
V
V
VSS + 0.2
(1) The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency (Ports Px)
PARAMETER
TEST CONDITIONS
Px.y, CL = 20 pF, RL = 1 kΩ(1)(2)
Px.y, CL = 20 pF(2)
VCC
3 V
3 V
MIN
TYP
12
MAX UNIT
MHz
fPx.y
Port output frequency (with load)
Clock output frequency
fPort_CLK
16
MHz
(1) A resistive divider with two 0.5-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the
divider.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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Typical Characteristics – Outputs
One output loaded at a time.
TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
25.0
20.0
15.0
10.0
5.0
50.0
40.0
30.0
20.0
10.0
0.0
V
= 2.2 V
T
= 25°C
V = 3 V
CC
CC
A
P1.0
P1.0
T
= 25°C
= 85°C
A
T
= 85°C
A
T
A
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OL
− Low-Level Output V oltage − V
V
OL
− Low-Level Output V oltage − V
Figure 5.
Figure 6.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0.0
−5.0
0.0
−10.0
−20.0
−30.0
−40.0
−50.0
V
= 2.2 V
V
= 3 V
CC
CC
P1.0
P1.0
−10.0
−15.0
−20.0
−25.0
T
= 85°C
A
T
A
= 85°C
T = 25°C
A
T
A
= 25°C
1.5
0.0
0.5
1.0
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OH
− High-Level Output V oltage − V
V
OH
− High-Level Output V oltage − V
Figure 7.
Figure 8.
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POR/Brownout Reset (BOR)(1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
0.7 ×
V(B_IT-)
VCC(start)
See Figure 9
dVCC/dt ≤ 3 V/s
V
V(B_IT-)
See Figure 9 through Figure 11
See Figure 9
dVCC/dt ≤ 3 V/s
dVCC/dt ≤ 3 V/s
1.42
120
V
Vhys(B_IT-)
td(BOR)
mV
µs
See Figure 9
2000
Pulse length needed at RST/NMI pin
to accepted reset internally
t(reset)
3 V
2
µs
(1) The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-)
Vhys(B_IT- ) is ≤ 1.8 V.
+
(2) During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-). The default DCO settings
must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency.
V
CC
V
hys(B_IT−)
V
(B_IT−)
V
CC(start)
1
0
t
d(BOR)
Figure 9. POR/Brownout Reset (BOR) vs Supply Voltage
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Typical Characteristics – POR/Brownout Reset (BOR)
V
t
CC
pw
2
3 V
V
= 3 V
Typical Conditions
CC
1.5
1
V
CC(drop)
0.5
0
0.001
1
1000
1 ns
1 ns
− Pulse Width − µs
t
− Pulse Width − µs
t
pw
pw
Figure 10. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
V
t
CC
pw
2
1.5
1
3 V
V
= 3 V
CC
Typical Conditions
V
CC(drop)
0.5
t
t
r
f =
0
0.001
1
1000
t
t
r
f
t
− Pulse Width − µs
t
− Pulse Width − µs
pw
pw
Figure 11. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
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SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
Supply Voltage Supervisor (SVS) / Supply Voltage Monitor (SVM)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
100
2000
100
12
MAX UNIT
dVCC/dt > 30 V/ms (see Figure 12)
t(SVSR)
µs
dVCC/dt ≤ 30 V/ms
td(SVSon)
tsettle
SVS on, switch from VLD = 0 to VLD ≉ 0, VCC =3 V
VLD ≉ 0(2)
µs
µs
V(SVSstart)
VLD ≉ 0, VCC/dt ≤ 3 V/s (see Figure 12)
1.55
120
15
1.7
V
VLD = 1
mV
mV
VCC/dt ≤ 3 V/s (see Figure 12)
VLD = 2 to 14
Vhys(SVS_IT-)
VCC/dt ≤ 3 V/s (see Figure 12), external voltage applied on
SVSIN
VLD = 15
10
mV
VLD = 1
VLD = 2
VLD = 3
VLD = 4
VLD = 5
VLD = 6
VLD = 7
VLD = 8
VLD = 9
VLD = 10
VLD = 11
VLD = 12
VLD = 13
VLD = 14
1.8
2.24
2.69
1.9
2.1
2.05
2.6
2.2
2.3
2.4
2.5
2.65
2.8
VCC/dt ≤ 3V/s (see Figure 12)
V(SVS_IT-)
V
2.9
3.13
3.05
3.2
3.35
3.24
1.1
3.5 3.76(3)
3.7(3)
VCC/dt ≤ 3 V/s (see Figure 12), external voltage applied on
SVSIN
VLD = 15
1.2
12
1.3
17
(1)
ICC(SVS)
VLD ≠ 0, VCC = 3 V
µA
(1) The current consumption of the SVS module is not included in the ICC current consumption data.
(2) tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≉ 0 to a different VLD value
somewhere between 2 and 15. The overdrive is assumed to be > 50 mV.
(3) The recommended operating voltage range is limited to 3.6 V.
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SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
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Typical Characteristics – SVS
Software sets VLD > 0:
SVS is active
AV
CC
V
hys(SVS_IT- )
V
(SVS_IT- )
V
(SVSstart)
V
hys(B_IT- )
V
(B_IT- )
V
CC(start)
Brown-
out
Region
Brownout
Region
Brownout
1
0
t
t
SVS out
1
d(BOR)
d(BOR)
SVS CircuitisActiveFromVLD>toV
< V(
CC
B_IT- )
0
t
t
d(SVSon)
d(SVSR)
Set POR
1
undefined
0
Figure 12. SVS Reset (SVSR) vs Supply Voltage
V
CC
t
pw
3 V
2
Rectangular Drop
V
CC(min)
1.5
1
Triangular Drop
1 ns
1ns
V
t
CC
pw
0.5
0
3 V
1
10
101000
t
pw
– Pulse Width – µs
V
CC(min)
t = t
f
r
t
f
t
r
t – Pulse Width – µs
Figure 13. VCC(min) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
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SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
Main DCO Characteristics
•
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
•
•
DCO control bits DCOx have a step size as defined by parameter SDCO.
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
32 × f
× f
DCO(RSEL,DCO)
DCO(RSEL,DCO+1)
f
=
average
MOD × f
+ (32 – MOD) × f
DCO(RSEL,DCO)
DCO(RSEL,DCO+1)
DCO Frequency
PARAMETER
TEST CONDITIONS
VCC
MIN
1.8
TYP
MAX UNIT
RSELx < 14
RSELx = 14
RSELx = 15
3.6
VCC
Supply voltage range
2.2
3.6
3.6
V
3.0
fDCO(0,0)
fDCO(0,3)
fDCO(1,3)
fDCO(2,3)
fDCO(3,3)
fDCO(4,3)
fDCO(5,3)
fDCO(6,3)
fDCO(7,3)
fDCO(8,3)
fDCO(9,3)
fDCO(10,3)
fDCO(11,3)
fDCO(12,3)
fDCO(13,3)
fDCO(14,3)
fDCO(15,3)
fDCO(15,7)
DCO frequency (0, 0)
DCO frequency (0, 3)
DCO frequency (1, 3)
DCO frequency (2, 3)
DCO frequency (3, 3)
DCO frequency (4, 3)
DCO frequency (5, 3)
DCO frequency (6, 3)
DCO frequency (7, 3)
DCO frequency (8, 3)
DCO frequency (9, 3)
DCO frequency (10, 3)
DCO frequency (11, 3)
DCO frequency (12, 3)
DCO frequency (13, 3)
DCO frequency (14, 3)
DCO frequency (15, 3)
DCO frequency (15, 7)
RSELx = 0, DCOx = 0, MODx = 0
RSELx = 0, DCOx = 3, MODx = 0
RSELx = 1, DCOx = 3, MODx = 0
RSELx = 2, DCOx = 3, MODx = 0
RSELx = 3, DCOx = 3, MODx = 0
RSELx = 4, DCOx = 3, MODx = 0
RSELx = 5, DCOx = 3, MODx = 0
RSELx = 6, DCOx = 3, MODx = 0
RSELx = 7, DCOx = 3, MODx = 0
RSELx = 8, DCOx = 3, MODx = 0
RSELx = 9, DCOx = 3, MODx = 0
RSELx = 10, DCOx = 3, MODx = 0
RSELx = 11, DCOx = 3, MODx = 0
RSELx = 12, DCOx = 3, MODx = 0
RSELx = 13, DCOx = 3, MODx = 0
RSELx = 14, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 7, MODx = 0
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
0.06
0.10
0.12
0.15
0.21
0.30
0.41
0.58
0.80
1.15
1.60
2.30
3.40
4.25
5.80
7.80
0.14 MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
M Hz
MHz
8.6 11.25
15.30
13.9 MHz
MHz
21.00
MHz
Frequency step between
range RSEL and RSEL+1
SRSEL
SDCO
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
3.3 V
1.35
ratio
Frequency step between tap
DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
Measured at SMCLK output
3.3 V
3.3 V
1.08
50
ratio
%
Duty cycle
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Calibrated DCO Frequencies – Tolerance
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX UNIT
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3.3V
8-MHz tolerance over
temperature(1)
0°C to 85°C
3.3 V
7.76
8
8.24 MHz
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3.3V
8-MHz tolerance over VCC
8-MHz tolerance overall
30°C
2.7 V to 3.6 V
2.7 V to 3.6 V
3.3 V
7.76
7.52
8
8
8.24 MHz
8.48 MHz
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3.3V
-40°C to 85°C
0°C to 85°C
30°C
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3.3V
12-MHz tolerance over
temperature(1)
11.64
11.64
11.28
12 12.36 MHz
12 12.36 MHz
12 12.72 MHz
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3.3V
12-MHz tolerance over VCC
12-MHz tolerance overall
3.3 V to 3.6 V
3.3 V to 3.6 V
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3.3V
-40°C to 85°C
(1) This is the frequency change from the measured frequency at 30°C over temperature.
Wake-Up From Lower-Power Modes (LPM3/4)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
1.5
MAX UNIT
DCO clock wake-up time from
LPM3/4(1)
fDCO = DCO default frequency
(approximately 1 MHz)
tDCO,LPM3/4
tCPU,LPM3/4
3 V
µs
CPU wake-up time from
LPM3/4(2)
1 / fMCLK
tDCO,LPM3/4
+
µs
(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
(2) Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics – DCO Clock Wake-Up Time From LPM3/4
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
DCO Frequency − MHz
Figure 14. Clock Wake-Up Time From LPM3 vs DCO Frequency
10.00
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SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
PARAMETER
TA
VCC
3 V
MIN
TYP
12
MAX UNIT
22 kHz
%/°C
fVLO
VLO frequency
-40°C to 85°C
-40°C to 85°C
25°C
4
dfVLO/dT
dfVLO/dVCC
VLO frequency temperature drift(1)
VLO frequency supply voltage drift(2)
3 V
0.5
4
1.8 V to 3.6 V
%/V
(1) Calculated using the box method: [MAX(-40...85°C) - MIN(-40...85°C)]/MIN(-40...85°C)/[85°C - (-40°C)]
(2) Calculated using the box method: [MAX(1.8...3.6 V) - MIN(1.8...3.6 V)]/MIN(1.8...3.6 V)/(3.6 V - 1.8 V)
Crystal Oscillator (XT2)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
XT2 oscillator crystal frequency,
HF mode 0
fXT2,HF0
fXT2,HF1
XT2OFF = 0, XT2Sx = 0
1.8 V to 3.6 V
0.4
1
MHz
MHz
XT2 oscillator crystal frequency,
HF mode 1
XT2OFF = 0, XT2Sx = 1
XT2OFF = 0, XT2Sx = 2
1.8 V to 3.6 V
1
4
1.8 V to 2.2 V
2.2 V to 3.0 V
3.0 V to 3.6 V
1.8 V to 2.2 V
2.2 V to 3.0 V
3.0 V to 3.6 V
2
2
10
XT2 oscillator crystal frequency,
HF mode 2
fXT2,HF2
12 MHz
2
16
0.4
0.4
0.4
10
XT2 oscillator logic-level
square-wave input frequency,
HF mode
fXT2,HF,logic
XT2OFF = 0, XT2Sx = 3
12 MHz
16
XT2OFF = 0, XT2Sx = 0
fXT2,HF = 1 MHz,
CL,eff = 15 pF
2700
800
Oscillation allowance for HF
crystals (see Figure 15 and
Figure 16)
XT2OFF = 0, XT2Sx = 1
fXT2,HF = 4 MHz,
OAHF
Ω
CL,eff = 15 pF
XT2OFF = 0, XT2Sx = 2
fXT2,HF = 16 MHz,
CL,eff = 15 pF
300
1
Integrated effective load
capacitance, HF mode(2)
CL,eff
XT2OFF = 0(3)
pF
XT2OFF = 0, Measured at
P1.0/SVSIN/TACLK/SMCLK/TA2,
fXT2,HF = 10 MHz
40
50
60
Duty cycle
3 V
3 V
%
XT2OFF = 0, Measured at
P1.0/SVSIN/TACLK/SMCLK/TA2,
fXT2,HF = 16 MHz
XT2OFF = 0, XT2Sx = 3(5)
40
30
50
60
(4)
fFault,HF
Oscillator fault frequency
300 kHz
(1) To improve EMI on the XT2 oscillator the following guidelines should be observed:
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
(d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should
always match the specification of the used crystal.
(3) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(4) Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
(5) Measured with logic-level input frequency, but also applies to operation with crystals.
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Typical Characteristics – XT2 Oscillator
100000.00
10000.00
1000.00
100.00
1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
0.0
LFXT1Sx = 2
LFXT1Sx = 2
LFXT1Sx = 1
LFXT1Sx = 1
LFXT1Sx = 0
1.00
LFXT1Sx = 0
8.0 12.0
Crystal Frequency − MHz
Figure 16. XT2 Oscillator Supply Current vs Crystal
10.00
0.10
10.00
100.00
0.0
4.0
16.0
20.0
Crystal Frequency − MHz
Figure 15. Oscillation Allowance vs Crystal Frequency,
CL,eff = 15 pF, TA = 25°C
Frequency, CL,eff = 15 pF, TA = 25°C
SD24_A, Power Supply and Recommended Operating Conditions
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
AVCC = DVCC
AVSS = DVSS = 0 V
AVCC Analog supply voltage
2.5
3.6
V
GAIN: 1, 2
GAIN: 4, 8, 16
GAIN: 32
800
900
1200
800
900
1
1100
SD24LP = 0, fSD24 = 1 MHz,
SD24OSR = 256
Analog supply current: 1 active
SD24_A channel including
internal reference
ISD24
3 V
3 V
µA
GAIN: 1
SD24LP = 1, fSD24 = 0.5 MHz,
SD24OSR = 256
GAIN: 32
SD24LP = 0 (low-power mode disabled)
SD24LP = 1 (low-power mode enabled)
0.03
0.03
1.1
Analog front-end input clock
frequency
fSD24
MHz
0.5
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SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
SD24_A, Input Range(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
-VREF
2GAIN
/
+VREF
2GAIN
/
Bipolar mode, SD24UNI = 0
Differential full scale input
voltage range
VID,FSR
mV
mV
+VREF
2GAIN
/
Unipolar mode, SD24UNI = 1
0
SD24GAINx = 1
±500
±250
±125
±62
±31
±15
200
75
SD24GAINx = 2
SD24GAINx = 4
SD24GAINx = 8
SD24GAINx = 16
SD24GAINx = 32
SD24GAINx = 1
SD24GAINx = 32
SD24GAINx = 1
SD24GAINx = 32
Differential input voltage
VID
range for specified
SD24REFON = 1
performance(2)
Input impedance (one input
pin to AVSS)
ZI
fSD24 = 1 MHz
fSD24 = 1 MHz
3 V
3 V
kΩ
kΩ
300
100
400
150
Differential input impedance
(IN+ to IN-)
ZID
VI
Absolute input voltage range
AVSS - 1
AVCC
AVCC
V
V
Common-mode input voltage
range
VIC
AVSS - 1
(1) All parameters pertain to each SD24_A channel.
(2) The full-scale range is defined by VFSR+ = +(VREF/2)/GAIN and VFSR- = -(VREF/2)/GAIN. If VREF is sourced externally, the analog input
range should not exceed 80% of VFSR+ or VFSR-; that is, VID = 0.8 VFSR- to 0.8 VFSR+. If VREF is sourced internally, the given VID ranges
apply.
SD24_A, Performance (fSD24 = 1 MHz, SD24OSRx = 256, SD24REFON = 1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
1
MAX
UNIT
SD24GAINx = 1
SD24GAINx = 2
SD24GAINx = 4
SD24GAINx = 8
1.96
3.86
7.62
15.04
28.35
G
Nominal gain
3 V
SD24GAINx = 16
SD24GAINx = 32
SD24GAINx = 1
SD24GAINx = 32
SD24GAINx = 1
SD24GAINx = 32
±0.2
±1.5
±20
EOS
Offset error
3 V
3 V
%FSR
±4
Offset error temperature
coefficient
ppm
FSR/°C
ΔEOS/ΔT
±20
±100
SD24GAINx = 1, Common-mode input signal:
VID = 500 mV, fIN = 50 Hz, 100 Hz
>90
>75
Common-mode rejection
ratio
CMRR
3 V
dB
SD24GAINx = 32, Common-mode input signal:
VID = 16 mV, fIN = 50 Hz, 100 Hz
AC power supply
rejection ratio
SD24GAINx = 1, VCC = 3 V ± 100 mV,
fVCC = 50 Hz
AC PSRR
XT
3 V
3 V
>80
dB
dB
SD24GAINx = 1, VID = 500 mV,
fIN = 50 Hz, 100 Hz
Crosstalk
<-100
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MSP430AFE2x2
MSP430AFE2x1
SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
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SD24_A, Temperature Sensor and Built-In VCC Sense
PARAMETER
TEST CONDITIONS
VCC
MIN
1.18
-100
420
TYP
MAX UNIT
TCSensor
Sensor temperature coefficient
Sensor offset voltage
1.32
1.46 mV/°C
VOffset,sensor
100
515
442
mV
Temperature sensor voltage at TA = 85°C
Temperature sensor voltage at TA = 30°C
475
402
VSensor
Sensor output voltage(1)(2)
3 V
mV
350
fSD24 = 1 MHz, SD24OSRx = 256,
SD24REFON = 1
VCC/1
1
VCC,Sense
VCC divider at input 5
V
Source resistance of VCC
divider at input 5
RSource,VCC
20
kΩ
(1) The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor (273 + T [°C]) + VOffset,sensor [mV]
(2) Results based on characterization and/or production test, not TCSensor or VOffset,sensor. Measured with fSD24 = 1 MHz, SD24OSRx = 256,
SD24REFON = 1.
SD24_A, Built-In Voltage Reference
PARAMETER
TEST CONDITIONS
VCC
3 V
3 V
3 V
MIN
TYP
1.2
MAX
1.26
320
UNIT
V
VREF
IREF
Internal reference voltage
Reference supply current
Temperature coefficient
VREF load capacitance
VREF(I) maximum load current
SD24REFON = 1, SD24VMIDON = 0
SD24REFON = 1, SD24VMIDON = 0
SD24REFON = 1, SD24VMIDON = 0(1)
SD24REFON = 1, SD24VMIDON = 0(2)
SD24REFON = 1, SD24VMIDON = 0
1.14
200
18
µA
TC
50 ppm/°C
CREF
ILOAD
100
nF
3 V
3 V
±200
nA
SD24REFON = 0→1, SD24VMIDON = 0,
CREF = 100nF
tON
Turn-on time
5
ms
DC power supply rejection
ΔVREF/ΔVCC
SD24REFON = 1, SD24VMIDON = 0,
VCC = 2.5 V to 3.6 V
DC PSR
100
µV/V
(1) Calculated using the box method: (MAX(-40...85°C) - MIN(-40...85°C)) / MIN(-40...85°C) / (85°C - (-40°C))
(2) There is no capacitance required on VREF. However, a capacitance of at least 100 nF is recommended to reduce any reference voltage
noise.
SD24_A, Reference Output Buffer
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Reference buffer output
voltage
VREF,BUF
SD24REFON = 1, SD24VMIDON = 1
3 V
1.2
V
Reference supply + reference
output buffer quiescent
current
IREF,BUF
SD24REFON = 1, SD24VMIDON = 1
3 V
430
650
µA
Required load capacitance
on VREF
CREF(O)
SD24REFON = 1, SD24VMIDON = 1
SD24REFON = 1, SD24VMIDON = 1
|ILOAD| = 0 to 1 mA
470
-15
nF
mA
mV
µs
Maximum load current on
VREF
ILOAD,Max
3 V
3 V
3 V
±1
Maximum voltage variation vs
load current
+15
SD24REFON = 0→1, SD24VMIDON = 0→1,
CREF = 470 nF
tON
Turn-on time
100
30
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MSP430AFE2x2
MSP430AFE2x1
www.ti.com
SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
SD24_A, External Reference Input
PARAMETER
TEST CONDITIONS
SD24REFON = 0
SD24REFON = 0
VCC
3 V
3 V
MIN
TYP
MAX UNIT
VREF(I) Input voltage range
IREF(I) Input current
1.0
1.25
1.5
50
V
nA
USART0
PARAMETER
fUSART USART clock frequency
t(τ)
USART0: deglitch time(1)
TEST CONDITIONS
MIN
TYP
MAX UNIT
8
MHz
ns
VCC = 3 V, SYNC = 0, UART mode
150
280
500
(1) The signal applied to the USART0 receive signal/terminal (URXD0) should meet the timing requirements of t(τ) to ensure that the URXS
flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating conditions to
set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the
URXD0 line.
Timer_A3
PARAMETER
TEST CONDITIONS
SMCLK, Duty cycle = 50% ± 10%
TA0, TA1
VCC
MIN
TYP
MAX UNIT
fTA
Timer_A3 clock frequency
Timer_A3, capture timing
fSYSTEM
MHz
ns
tTA,cap
3 V
20
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX UNIT
VCC(PGM/ERASE)
fFTG
Program and erase supply voltage
Flash timing generator frequency
Supply current from VCC during program
Supply current from VCC during erase
Cumulative program time(1)
2.2
3.6
V
257
476 kHz
IPGM
2.2 V/3.6 V
2.2 V/3.6 V
2.2 V/3.6 V
2.2 V/3.6 V
1
1
5
7
mA
mA
IERASE
tCPT
10
ms
tCMErase
Cumulative mass erase time
20
104
100
ms
Program/erase endurance
105
cycles
years
tFTG
tFTG
tRetention
tWord
Data retention duration
TJ = 25°C
(2)
Word or byte program time
30
25
(2)
tBlock, 0
Block program time for first byte or word
Block program time for each additional byte or
word
(2)
tBlock, 1-63
18
tFTG
(2)
(2)
(2)
tBlock, End
tMass Erase
tSeg Erase
Block program end-sequence wait time
Mass erase time
6
10593
4819
tFTG
tFTG
tFTG
Segment erase time
(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
(2) These values are hardwired into the flash controller's state machine (tFTG = 1 / fFTG).
Copyright © 2010–2011, Texas Instruments Incorporated
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MSP430AFE2x2
MSP430AFE2x1
SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
www.ti.com
RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
CPU halted
MIN
MAX UNIT
(1)
V(RAMh)
RAM retention supply voltage
1.6
V
(1) This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
3 V
3 V
MIN
0
TYP
MAX UNIT
fSBW
Spy-Bi-Wire input frequency
Spy-Bi-Wire low clock pulse length
20 MHz
tSBW,Low
0.025
15
µs
µs
µs
Spy-Bi-Wire enable time
tSBW,En
3 V
1
(TEST high to acceptance of first clock edge(1)
)
tSBW,Ret
fTCK
Spy-Bi-Wire return to normal operation time
TCK input frequency(2)
3 V
3 V
3 V
15
0
100
10 MHz
90 kΩ
RInternal
Internal pulldown resistance on TEST
25
60
(1) Tools accessing the Spy-Bi-Wire interface must wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.5
6
MAX UNIT
VCC(FB)
VFB
Supply voltage during fuse-blow condition
Voltage level on TEST for fuse blow
Supply current into TEST during fuse blow
Time to blow fuse
TA = 25°C
V
7
100
1
V
IFB
mA
ms
tFB
(1) Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, or emulation feature is possible, and JTAG is switched to
bypass mode.
32
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
www.ti.com
SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
APPLICATION INFORMATION
Port P1 Pin Schematic: P1.0 Input/Output With Schmitt Trigger
Pad Logic
To SVS Mux
VLD = 15
P1REN.0
0
1
DVSS
DVCC
1
0
1
P1DIR.0
P1SEL2.0
Direction
0: Input
1: Output
0
1
From Timer_A3
SMCLK
1
0
P1OUT.0
P1.0/SVSIN/TACLK/SMCLK/TA2
Bus
Keeper
EN
P1SEL.0
P1IN.0
EN
To Timer_A3
P1IRQ.0
D
P1IE.0
EN
Set
Q
P1IFG.0
P1SEL.0
P1IES.0
Interrupt
Edge Select
Table 17. Port P1 (P1.0) Pin Functions
CONTROL BITS / SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
P1SEL2.x
P1.0 (I/O)
I: 0, O: 1
0
X
1
1
1
X
X
0
1
0
SVSIN (VLD = 15)
Timer_A3.TACLK
SMCLK
X
0
1
1
P1.0/SVSIN/TACLK/SMCLK/TA2
0
Timer_A3.TA2
(1) X = don't care
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
www.ti.com
Port P1 Pin Schematic: P1.1 and P1.2 Input/Output With Schmitt Trigger
Pad Logic
P1REN.x
0
1
DVSS
DVCC
1
0
1
P1DIR.x
P1SEL2.x
Direction
0: Input
1: Output
From Timer_A3
From SD24_A
0
1
1
0
P1OUT.x
P1.1/TA1/SDCLK
P1.2/TA0/SD0DO
Bus
Keeper
EN
P1SEL.x
P1IN.x
EN
To Timer_A3
P1IRQ.x
D
P1IE.x
EN
Set
Q
P1IFG.x
P1SEL.x
P1IES.x
Interrupt
Edge Select
Table 18. Port P1 (P1.1 and P1.2) Pin Functions
CONTROL BITS / SIGNAL(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
P1SEL2.x
P1.1 (I/O)
I: 0, O: 1
0
1
1
1
0
1
1
1
X
0
0
1
X
0
0
1
Timer_A3.CCI1A and CCI1B
Timer_A3.TA1
SDCLK
0
P1.1/TA1/SDCLK
1
1
1
P1.2 (I/O)
I: 0, O: 1
Timer_A3.CCI0A and CCI0B
Timer_A3.TA0
SD0DO
0
1
1
P1.2/TA0/SD0DO
2
(1) X = don't care
34
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
www.ti.com
SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
Port P1 Pin Schematic: P1.3 Input/Output With Schmitt Trigger
Pad Logic
P1REN.3
0
1
DVSS
DVCC
P1DIR.3
1
0
1
1
0
Direction
0: Input
1: Output
USART0
direction
P1OUT.3
0
1
SD24_A data
1
0
P1.3/UTXD0/SD1DO
USART0
data out
P1SEL.3
P1SEL2.3
Bus
Keeper
EN
P1IN.3
EN
Not used
P1IRQ.3
D
P1IE.3
EN
Set
Q
P1IFG.3
P1SEL.3
P1IES.3
Interrupt
Edge Select
Table 19. Port P1 (P1.3) Pin Functions
CONTROL BITS / SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
P1SEL2.x
P1.3 (I/O)
I: 0, O: 1
0
1
1
X
0
1
P1.3/UTXD0/SD1DO
3
UTXD0
SD1DO
X
1
(1) X = don't care
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
www.ti.com
Port P1 Pin Schematic: P1.4 Input/Output With Schmitt Trigger
Pad Logic
P1REN.4
0
1
DVSS
DVCC
P1DIR.4
1
0
1
1
0
Direction
0: Input
1: Output
USART0
direction
P1OUT.4
P1SEL2.4
0
1
SD24_A data
P1SEL.4
P1.4/URXD0/SD2DO
Bus
Keeper
EN
P1IN.4
EN
USART0
data in
D
P1IE.4
EN
Set
P1IRQ.4
Q
P1IFG.4
P1SEL.4
Interrupt
Edge Select
P1IES.4
Table 20. Port P1 (P1.4) Pin Functions
CONTROL BITS / SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
P1SEL2.x
P1.4 (I/O)
URXD0
I: 0, O: 1
0
1
1
X
0
1
P1.4/URXD0/SD2DO
4
X
1
SD2DO
(1) X = don't care
36
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
www.ti.com
SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
Port P1 Pin Schematic: P1.5 to P1.7 Input/Output With Schmitt Trigger
Pad Logic
P1REN.x
0
1
DVSS
DVCC
P1DIR.x
Direction
0: Input
1: Output
1
0
1
1
0
USART0
direction
P1OUT.x
0
1
Module X out
1
0
USART0
data out
P1.5/SIMO0/SVSOUT/TMS
P1.6/SOMI0/TA2/TCK
P1.7/UCLK0/TA1/TDO/TDI
P1SEL.x
P1SEL2.x
Bus
Keeper
EN
P1IN.x
EN
USART0
data in
D
P1IE.x
EN
Set
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
Interrupt
Edge Select
To JTAG
From JTAG
From JTAG
From JTAG (TDO)
Table 21. Port P1 (P1.5 to P1.7) Pin Functions
CONTROL BITS / SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
JTAG
P1DIR.x
P1SEL.x
P1SEL2.x
Mode(2)
5
P1.5 (I/O)
I: 0; O: 1
0
1
1
X
0
1
1
X
0
1
1
X
X
0
1
X
X
0
1
X
X
0
1
X
0
0
0
1
0
0
0
1
0
0
0
1
SIMO0
X
P1.5/SIMO0/SVSOUT/TMS
SVSOUT
TMS
1
X
6
7
P1.6 (I/O)
SOMI0
I: 0; O: 1
X
P1.6/SOMI0/TA2/TCK
Timer_A3.TA2
TCK
1
X
P1.7 (I/O)
UCLK0
I: 0; O: 1
X
1
P1.7/UCLK0/TA1/TDO/TDI
Timer_A3.TA1
TDO/TDI
X
(1) X = don't care
(2) JTAG Mode is not a register bit but signal generated internally when 4-wire JTAG option is selected in IDE
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
www.ti.com
Port P2 Pin Schematic: P2.0 Input/Output With Schmitt Trigger
P2REN.0
Pad Logic
0
1
DVSS
DVCC
P2DIR.0
Direction
0: Input
1: Output
1
0
1
1
0
USART0
direction
P2OUT.0
0
1
Timer_A3 out
1
0
USART0
data out
P2.0/STE0/TA0/TDI/TCLK
P2SEL.0
P2SEL2.0
Bus
Keeper
EN
P2IN.0
EN
USART0
data in
D
P2IE.0
EN
Set
P2IRQ.0
Q
P2IFG.0
P2SEL.0
P2IES.0
Interrupt
Edge Select
To JTAG
From JTAG
Table 22. Port P2 (P2.0) Pin Functions
CONTROL BITS / SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
JTAG
P2DIR.x
P2SEL.x
P2SEL2.x
Mode(2)
0
P2.0 (I/O)
STE0
I: 0; O: 1
0
1
1
X
X
0
1
X
0
0
0
1
X
1
P2.0/STE0/TA0/TDI/TCLK
Timer_A3.TA0
TDI/TCLK
X
(1) X = don't care
(2) JTAG Mode is not a register bit but signal generated internally when 4-wire JTAG option is selected in IDE
38
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
www.ti.com
SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger
BCSCTL3.XT2Sx = 11
XT2 off
P2.7/XT2OUT
0
XT2CLK
1
P2SEL.7
Pad Logic
P2REN.6
0
DVSS
1
1
DVCC
P2DIR.6
0
1
Direction
0: Input
1: Output
P2OUT.6
0
1
Module X OUT
P2.6/XT2IN
Bus
Keeper
EN
P2SEL.6
P2IN.6
EN
Module X IN
P2IRQ.6
D
P2IE.6
EN
Set
Q
P2IFG.6
P2SEL.6
P2IES.6
Interrupt
Edge Select
Table 23. Port P2 (P2.6) Pin Functions
CONTROL BITS / SIGNALS
Pin Name (P2.x)
x
FUNCTION
P2DIR.6
P2SEL.6
P2.6 (I/O)
I: 0; O: 1
0
0
1
P2.6/XT2IN
6
XT2IN (default)
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
www.ti.com
Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger
BCSCTL3.XT2Sx = 11
P2.6/XT2IN
XT2 off
0
XT2CLK
From P2.6/XT2IN
1
P2SEL.6
Pad Logic
P2REN.7
0
1
DVSS
DVCC
1
P2DIR.7
0
1
Direction
0: Input
1: Output
P2OUT.7
0
1
Module X OUT
P2.7/XT2OUT
Bus
Keeper
EN
P2SEL.7
P2IN.7
EN
Module X IN
P2IRQ.7
D
P2IE.7
EN
Set
Q
P2IFG.7
P2SEL.7
P2IES.7
Interrupt
Edge Select
Table 24. Port P2 (P2.7) Pin Functions
CONTROL BITS / SIGNALS
PIN NAME (P2.x)
x
FUNCTION
P2DIR.7
I: 0, O: 1
0
P2SEL.7
P2.7 (I/O)
0
1
P2.7/XT2OUT
7
XT2OUT (default)
40
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
www.ti.com
SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
JTAG Fuse Check Mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the
fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF , of 1 mA at 3 V or 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care
must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense
currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is
being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.
After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR, the fuse
check mode has the potential to be activated.
The fuse check current flow only when the fuse check mode is active and the TMS pin is in a low state (see
Figure 17). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
I
TF
I
TEST
Figure 17. Fuse Check Mode Current
NOTE
The CODE and RAM data protection is ensured if the JTAG fuse is blown.
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
www.ti.com
REVISION HISTORY
REVISION
COMMENTS
SLAS701
Product Preview release
Production Data release
SLAS701A
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PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
MSP430AFE221IPW
MSP430AFE221IPWR
MSP430AFE222IPW
MSP430AFE222IPWR
MSP430AFE223IPW
MSP430AFE223IPWR
MSP430AFE231IPW
MSP430AFE231IPWR
MSP430AFE232IPW
MSP430AFE232IPWR
MSP430AFE233IPW
MSP430AFE233IPWR
MSP430AFE251IPW
MSP430AFE251IPWR
MSP430AFE252IPW
MSP430AFE252IPWR
MSP430AFE253IPW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
60
2000
60
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
2000
60
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
2000
60
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
2000
60
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
2000
60
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
2000
60
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
2000
60
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
2000
60
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2011
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
MSP430AFE253IPWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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Addendum-Page 2
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