MSP430F1610IPMR [TI]
MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器
| 型号： | MSP430F1610IPMR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MIXED SIGNAL MICROCONTROLLER |
| 文件： | 总70页 (文件大小：1168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
D
D
Low Supply-Voltage Range, 1.8 V . . . 3.6 V
D
D
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
Ultralow-Power Consumption:
− Active Mode: 330 µA at 1 MHz, 2.2 V
− Standby Mode: 1.1 µA
− Off Mode (RAM Retention): 0.2 µA
Family Members Include:
− MSP430F155:
16KB+256B Flash Memory
512B RAM
− MSP430F156:
D
D
D
Five Power-Saving Modes
Wake-Up From Standby Mode in less
than 6 µs
16-Bit RISC Architecture, 125-ns
Instruction Cycle Time
24KB+256B Flash Memory
1KB RAM
D
Three-Channel Internal DMA
− MSP430F157:
32KB+256B Flash Memory,
1KB RAM
− MSP430F167:
32KB+256B Flash Memory,
1KB RAM
− MSP430F168:
48KB+256B Flash Memory,
2KB RAM
− MSP430F169:
60KB+256B Flash Memory,
2KB RAM
− MSP430F1610:
32KB+256B Flash Memory
5KB RAM
− MSP430F1611:
48KB+256B Flash Memory
10KB RAM
− MSP430F1612:
55KB+256B Flash Memory
5KB RAM
D
12-Bit A/D Converter With Internal
Reference, Sample-and-Hold and Autoscan
Feature
D
D
D
Dual 12-Bit D/A Converters With
Synchronization
16-Bit Timer_A With Three
Capture/Compare Registers
16-Bit Timer_B With Three or Seven
Capture/Compare-With-Shadow Registers
D
On-Chip Comparator
D
Serial Communication Interface (USART0),
Functions as Asynchronous UART or
2
TM
Synchronous SPI or I C Interface
D
D
Serial Communication Interface (USART1),
Functions as Asynchronous UART or
Synchronous SPI Interface
Supply Voltage Supervisor/Monitor With
Programmable Level Detection
D
Brownout Detector
Bootstrap Loader
D
D
Available in 64-Pin Quad Flat Pack (QFP)
and 64-pin QFN (see Available Options)
D
2
For Complete Module Descriptions, See the
MSP430x1xx Family User’s Guide,
Literature Number SLAU049
I C is a registered trademark of Philips Incorporated.
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs.
The MSP430x15x/16x/161x series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit
A/D converter, dual 12-bit D/A converter, one or two universal serial synchronous/asynchronous
2
communication interfaces (USART), I C, DMA, and 48 I/O pins. In addition, the MSP430x161x series offers
extended RAM addressing for memory-intensive applications and large C-stack requirements.
Typical applications include sensor systems, industrial control applications, hand-held meters, etc.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002 − 2005, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
PLASTIC 64-PIN QFP (PM)
PLASTIC 64-PIN QFN (RTD)
†
MSP430F155IPM
MSP430F156IPM
MSP430F157IPM
MSP430F167IPM
MSP430F168IPM
MSP430F169IPM
MSP430F1610IPM
MSP430F1611IPM
MSP430F1612IPM
MSP430F155IRTD
MSP430F156IRTD†
MSP430F157IRTD†
MSP430F167IRTD†
MSP430F168IRTD†
MSP430F169IRTD†
MSP430F1610IRTD
MSP430F1611IRTD
MSP430F1612IRTD
−40°C to 85°C
†
Product Preview
pin designation, MSP430F155, MSP430F156, and MSP430F157
PM, RTD PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DVCC
P6.3/A3
1
48 P5.4/MCLK
47 P5.3
2
P6.4/A4
3
46 P5.2
P6.5/A5
4
45 P5.1
5
44
43
42
41
40
39
38
37
36
35
34
33
P6.6/A6/DAC0
P6.7/A7/DAC1/SVSIN
VREF+
P5.0
P4.7/TBCLK
P4.6
6
7
8
XIN
XOUT
P4.5
P4.4
9
10
11
12
13
14
15
16
VeREF+
P4.3
VREF−/VeREF−
P1.0/TACLK
P1.1/TA0
P4.2/TB2
P4.1/TB1
P4.0/TB0
P3.7
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P3.6
P3.5/URXD0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
pin designation, MSP430F167, MSP430F168, MSP430F169
PM, RTD PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DVCC
P6.3/A3
1
48 P5.4/MCLK
47 P5.3/UCLK1
46 P5.2/SOMI1
45 P5.1/SIMO1
2
P6.4/A4
P6.5/A5
3
4
5
44
P6.6/A6/DAC0
P6.7/A7/DAC1/SVSIN
VREF+
P5.0/STE1
P4.7/TBCLK
P4.6/TB6
6
43
42
41
40
39
38
37
36
35
34
33
7
8
XIN
XOUT
P4.5/TB5
P4.4/TB4
9
10
11
12
13
14
15
16
VeREF+
P4.3/TB3
P4.2/TB2
VREF−/VeREF−
P1.0/TACLK
P1.1/TA0
P4.1/TB1
P4.0/TB0
P1.2/TA1
P3.7/URXD1
P3.6/UTXD1
P3.5/URXD0
P1.3/TA2
P1.4/SMCLK
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
pin designation, MSP430F1610, MSP430F1611, MSP430F1612
PM, RTD PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DVCC
P6.3/A3
1
48 P5.4/MCLK
47 P5.3/UCLK1
46 P5.2/SOMI1
45 P5.1/SIMO1
2
P6.4/A4
P6.5/A5
3
4
5
44
43
42
41
40
39
38
37
36
35
34
33
P6.6/A6/DAC0
P6.7/A7/DAC1/SVSIN
VREF+
P5.0/STE1
P4.7/TBCLK
P4.6/TB6
6
7
8
XIN
XOUT
P4.5/TB5
P4.4/TB4
9
10
11
12
13
14
15
16
VeREF+
P4.3/TB3
P4.2/TB2
VREF−/VeREF−
P1.0/TACLK
P1.1/TA0
P4.1/TB1
P4.0/TB0
P1.2/TA1
P3.7/URXD1
P3.6/UTXD1
P3.5/URXD0
P1.3/TA2
P1.4/SMCLK
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
functional block diagrams
MSP430x15x
P1
XIN XOUT
DV
RST/NMI
P2
P3
P4
P5
P6
DV
AV
AV
SS
CC
SS
CC
8
8
8
8
8
8
R
OSC
Oscillator
ACLK
32KB Flash
24KB Flash
1KB RAM
1KB RAM
ADC12
12-Bit
DAC12
12-Bit
I/O Port 1/2 I/O Port 3/4 I/O Port 5/6
16 I/Os,
with
16 I/Os
16 I/Os
XT2IN
System
Clock
SMCLK
8 Channels 2 Channels
16KB Flash 512B RAM <10µs Conv. Voltage out
Interrupt
Capability
XT2OUT
MCLK
MAB,
4 Bit
Test
MAB, 16-Bit
JTAG
CPU
MCB
Incl. 16 Reg.
Bus
Conv
MDB, 16-Bit
MDB, 8 Bit
4
TMS
TCK
DMA
Controller
Watchdog
Timer
Timer_B3
Timer_A3
3 CC Reg
POR
SVS
Brownout
Comparator
A
USART0
3 CC Reg
Shadow
Reg
UART Mode
SPI Mode
TDI/TCLK
TDO/TDI
3 Channels
15/16-Bit
2
I C Mode
MSP430x16x
P1
XIN XOUT
DV
CC
RST/NMI
P2
P3
P4
P5
P6
DV
AV
AV
SS
SS
CC
8
8
8
8
8
8
R
OSC
Oscillator
ACLK
60KB Flash
48KB Flash
32KB Flash
2KB RAM
2KB RAM
1KB RAM
ADC12
12-Bit
8 Channels 2 Channels
<10µs Conv. Voltage out
DAC12
12-Bit
I/O Port 1/2 I/O Port 3/4 I/O Port 5/6
16 I/Os,
with
16 I/Os
16 I/Os
XT2IN
System
Clock
SMCLK
Interrupt
Capability
XT2OUT
MCLK
MAB,
4 Bit
Test
MAB, 16-Bit
JTAG
CPU
MCB
Incl. 16 Reg.
Bus
Conv
MDB, 16-Bit
MDB, 8 Bit
4
TMS
TCK
Hardware
Multiplier
DMA
Controller
Watchdog
Timer
Timer_B7
Timer_A3
3 CC Reg
POR
SVS
Brownout
Comparator
A
USART0
USART1
7 CC Reg
Shadow
Reg
UART Mode UART Mode
MPY, MPYS
MAC,MACS
TDI/TCLK
TDO/TDI
3 Channels
15/16-Bit
SPI Mode
SPI Mode
2
I C Mode
5
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
functional block diagrams (continued)
MSP430x161x
P1
XIN XOUT
DV
RST/NMI
P2
P3
P4
P5
P6
DV
AV
AV
SS
CC
SS
CC
8
8
8
8
8
8
R
OSC
Oscillator
ACLK
55KB Flash
5KB RAM
ADC12
12-Bit
8 Channels 2 Channels
<10µs Conv. Voltage out
DAC12
12-Bit
I/O Port 1/2 I/O Port 3/4 I/O Port 5/6
16 I/Os,
with
16 I/Os
16 I/Os
XT2IN
System
Clock
SMCLK
48KB Flash 10KB RAM
Interrupt
Capability
XT2OUT
32KB Flash
5KB RAM
MCLK
MAB,
4 Bit
Test
MAB, 16-Bit
JTAG
CPU
MCB
Incl. 16 Reg.
Bus
Conv
MDB, 16-Bit
MDB, 8 Bit
4
TMS
TCK
Hardware
Multiplier
DMA
Controller
Watchdog
Timer
Timer_B7
Timer_A3
3 CC Reg
POR
SVS
Brownout
Comparator
A
USART0
USART1
7 CC Reg
Shadow
Reg
UART Mode UART Mode
MPY, MPYS
MAC,MACS
TDI/TCLK
TDO/TDI
3 Channels
15/16-Bit
SPI Mode
SPI Mode
2
I C Mode
6
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SLAS368D− OCTOBER 2002− REVISED MARCH 2005
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
64
62
1
AV
AV
Analog supply voltage, positive terminal. Supplies only the analog portion of ADC12 and DAC12.
Analog supply voltage, negative terminal. Supplies only the analog portion of ADC12 and DAC12.
Digital supply voltage, positive terminal. Supplies all digital parts.
CC
SS
DV
DV
CC
63
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Digital supply voltage, negative terminal. Supplies all digital parts.
SS
P1.0/TACLK
P1.1/TA0
I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input
I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit
I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
I/O General-purpose digital I/O pin/SMCLK signal output
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P1.5/TA0
I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output
P1.6/TA1
I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output
P1.7/TA2
I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output
P2.0/ACLK
P2.1/TAINCLK
P2.2/CAOUT/TA0
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/Rosc
I/O General-purpose digital I/O pin/ACLK output
I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK
I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output/BSL receive
I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input
I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input
I/O General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency
I/O General-purpose digital I/O pin/conversion clock – 12-bit ADC/DMA channel 0 external trigger
P2.6/ADC12CLK/
DMAE0
P2.7/TA0
27
28
29
30
31
I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output
P3.0/STE0
I/O General-purpose digital I/O pin/slave transmit enable – USART0/SPI mode
2
2
P3.1/SIMO0/SDA
P3.2/SOMI0
P3.3/UCLK0/SCL
I/O General-purpose digital I/O pin/slave in/master out of USART0/SPI mode, I C data − USART0/I C mode
I/O General-purpose digital I/O pin/slave out/master in of USART0/SPI mode
I/O General-purpose digital I/O pin/external clock input − USART0/UART or SPI mode, clock output –
2
2
USART0/SPI mode, I C clock − USART0/I C mode
P3.4/UTXD0
P3.5/URXD0
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
I/O General-purpose digital I/O pin/transmit data out – USART0/UART mode
I/O General-purpose digital I/O pin/receive data in – USART0/UART mode
I/O General-purpose digital I/O pin/transmit data out – USART1/UART mode
I/O General-purpose digital I/O pin/receive data in – USART1/UART mode
I/O General-purpose digital I/O pin/Timer_B, capture: CCI0A/B input, compare: Out0 output
I/O General-purpose digital I/O pin/Timer_B, capture: CCI1A/B input, compare: Out1 output
I/O General-purpose digital I/O pin/Timer_B, capture: CCI2A/B input, compare: Out2 output
I/O General-purpose digital I/O pin/Timer_B, capture: CCI3A/B input, compare: Out3 output
I/O General-purpose digital I/O pin/Timer_B, capture: CCI4A/B input, compare: Out4 output
I/O General-purpose digital I/O pin/Timer_B, capture: CCI5A/B input, compare: Out5 output
I/O General-purpose digital I/O pin/Timer_B, capture: CCI6A input, compare: Out6 output
I/O General-purpose digital I/O pin/Timer_B, clock signal TBCLK input
†
P3.6/UTXD1
P3.7/URXD1†
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3†
P4.4/TB4†
P4.5/TB5†
P4.6/TB6†
P4.7/TBCLK
P5.0/STE1†
P5.1/SIMO1†
P5.2/SOMI1†
P5.3/UCLK1†
I/O General-purpose digital I/O pin/slave transmit enable – USART1/SPI mode
I/O General-purpose digital I/O pin/slave in/master out of USART1/SPI mode
I/O General-purpose digital I/O pin/slave out/master in of USART1/SPI mode
I/O General-purpose digital I/O pin/external clock input – USART1/UART or SPI mode, clock output –
USART1/SPI mode
†
16x, 161x devices only
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SLAS368D− OCTOBER 2002− REVISED MARCH 2005
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
P5.4/MCLK
P5.5/SMCLK
P5.6/ACLK
NO.
48
I/O General-purpose digital I/O pin/main system clock MCLK output
I/O General-purpose digital I/O pin/submain system clock SMCLK output
I/O General-purpose digital I/O pin/auxiliary clock ACLK output
49
50
P5.7/TBOUTH/
SVSOUT
51
I/O General-purpose digital I/O pin/switch all PWM digital output ports to high impedance − Timer_B TB0 to
TB6/SVS comparator output
P6.0/A0
59
60
61
2
I/O General-purpose digital I/O pin/analog input a0 – 12-bit ADC
I/O General-purpose digital I/O pin/analog input a1 – 12-bit ADC
I/O General-purpose digital I/O pin/analog input a2 – 12-bit ADC
I/O General-purpose digital I/O pin/analog input a3 – 12-bit ADC
I/O General-purpose digital I/O pin/analog input a4 – 12-bit ADC
I/O General-purpose digital I/O pin/analog input a5 – 12-bit ADC
I/O General-purpose digital I/O pin/analog input a6 – 12-bit ADC/DAC12.0 output
I/O General-purpose digital I/O pin/analog input a7 – 12-bit ADC/DAC12.1 output/SVS input
P6.1/A1
P6.2/A2
P6.3/A3
P6.4/A4
3
P6.5/A5
4
P6.6/A6/DAC0
5
P6.7/A7/DAC1/
SVSIN
6
RST/NMI
TCK
58
57
55
54
56
10
7
I
I
I
Reset input, nonmaskable interrupt input port, or bootstrap loader start (in Flash devices).
Test clock. TCK is the clock input port for device programming test and bootstrap loader start
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TDI/TCLK
TDO/TDI
TMS
I/O Test data output port. TDO/TDI data output or programming data input terminal
I
I
Test mode select. TMS is used as an input port for device programming and test.
Input for an external reference voltage
Ve
REF+
REF+
V
V
O
I
Output of positive terminal of the reference voltage in the ADC12
/Ve
REF−
11
Negative terminal for the reference voltage for both sources, the internal reference voltage, or an external
applied reference voltage
REF−
XIN
8
9
I
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
Output terminal of crystal oscillator XT1
XOUT
O
I
XT2IN
XT2OUT
QFN Pad
53
52
NA
Input port for crystal oscillator XT2. Only standard crystals can be connected.
Output terminal of crystal oscillator XT2
O
NA QFN package pad connection to DV recommended (RTD package only)
SS
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SLAS368D− OCTOBER 2002− REVISED MARCH 2005
short-form description
CPU
Program Counter
Stack Pointer
PC/R0
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
R4
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
R5
R6
R7
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
R8
R9
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
R10
R11
instruction set
R12
R13
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
R14
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
e.g. ADD R4,R5
R4 + R5 −−−> R5
e.g. CALL
e.g. JNE
R8
PC −−>(TOS), R8−−> PC
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
Register
S
D
SYNTAX
MOV Rs,Rd
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
OPERATION
D D
R10 −−> R11
Indexed
D D
MOV X(Rn),Y(Rm)
MOV EDE,TONI
M(2+R5)−−> M(6+R6)
M(EDE) −−> M(TONI)
M(MEM) −−> M(TCDAT)
M(R10) −−> M(Tab+R6)
Symbolic (PC relative) D D
Absolute
Indirect
D D MOV &MEM,&TCDAT
D
D
D
MOV @Rn,Y(Rm)
MOV @Rn+,Rm
MOV #X,TONI
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
Indirect
autoincrement
M(R10) −−> R11
R10 + 2−−> R10
Immediate
#45 −−> M(TONI)
NOTE: S = source
D = destination
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SLAS368D− OCTOBER 2002− REVISED MARCH 2005
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D
D
Active mode AM;
All clocks are active
Low-power mode 0 (LPM0);
−
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
D
D
Low-power mode 1 (LPM1);
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCO’s dc-generator is disabled if DCO not used in active mode
Low-power mode 2 (LPM2);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D
D
Low-power mode 3 (LPM3);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
Low-power mode 4 (LPM4);
−
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
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SLAS368D− OCTOBER 2002− REVISED MARCH 2005
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External Reset
Watchdog
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh
15, highest
Flash memory
NMI
Oscillator Fault
Flash memory access violation
NMIIFG (see Notes 1 & 3)
OFIFG (see Notes 1 & 3)
ACCVIFG (see Notes 1 & 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
0FFFAh
14
13
Timer_B7 (see Note 5)
Timer_B7 (see Note 5)
TBCCR0 CCIFG
(see Note 2)
Maskable
TBCCR1 to TBCCR6
CCIFGs, TBIFG
Maskable
0FFF8h
12
(see Notes 1 & 2)
Comparator_A
Watchdog timer
USART0 receive
USART0 transmit
CAIFG
WDTIFG
URXIFG0
Maskable
Maskable
Maskable
Maskable
0FFF6h
0FFF4h
0FFF2h
0FFF0h
11
10
9
UTXIFG0
I2CIFG (see Note 4)
8
2
I C transmit/receive/others
ADC12
ADC12IFG
(see Notes 1 & 2)
Maskable
Maskable
0FFEEh
0FFECh
7
6
Timer_A3
TACCR0 CCIFG
(see Note 2)
TACCR1 and TACCR2
CCIFGs, TAIFG
(see Notes 1 & 2)
Timer_A3
Maskable
Maskable
0FFEAh
0FFE8h
5
4
P1IFG.0 to P1IFG.7
(see Notes 1 & 2)
I/O port P1 (eight flags)
USART1 receive
USART1 transmit
URXIFG1
UTXIFG1
Maskable
Maskable
0FFE6h
0FFE4h
3
2
P2IFG.0 to P2IFG.7
(see Notes 1 & 2)
I/O port P2 (eight flags)
Maskable
Maskable
0FFE2h
0FFE0h
1
DAC12
DMA
DAC12_0IFG,
DAC12_1IFG
0, lowest
DMA0IFG, DMA1IFG,
DMA2IFG (see Notes 1 & 2)
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
2
4. I C interrupt flags located in the module
5. Timer_B7 in MSP430x16x/161x family has 7 CCRs; Timer_B3 in MSP430x15x family has 3 CCRs; in Timer_B3 there are only
interrupt flags TBCCR0, 1 and 2 CCIFGs and the interrupt-enable bits TBCCR0, 1 and 2 CCIEs.
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SLAS368D− OCTOBER 2002− REVISED MARCH 2005
special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
interrupt enable 1 and 2
7
6
5
4
3
2
1
0
Address
0h
UTXIE0
URXIE0
ACCVIE
NMIIE
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
WDTIE:
Watchdog timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as general-purpose timer.
OFIE:
Oscillator-fault-interrupt enable
NMIIE:
Nonmaskable-interrupt enable
ACCVIE:
URXIE0:
UTXIE0:
Flash memory access violation interrupt enable
USART0: UART and SPI receive-interrupt enable
USART0: UART and SPI transmit-interrupt enable
7
6
5
4
3
2
1
0
Address
01h
UTXIE1
URXIE1
rw-0
rw-0
URXIE1†:
USART1: UART and SPI receive-interrupt enable
USART1: UART and SPI transmit-interrupt enable
UTXIE1†:
†
URXIE1 and UTXIE1 are not present in MSP430x15x devices.
interrupt flag register 1 and 2
7
6
URXIFG0
rw-0
5
4
3
2
1
0
Address
02h
UTXIFG0
NMIIFG
OFIFG
WDTIFG
rw-1
rw-0
rw-1
rw-(0)
WDTIFG:
Set on watchdog-timer overflow (in watchdog mode) or security key violation
Reset on V power-on, or a reset condition at the RST/NMI pin in reset mode
CC
OFIFG:
Flag set on oscillator fault
Set via RST/NMI pin
NMIIFG:
URXIFG0: USART0: UART and SPI receive flag
UTXIFG0: USART0: UART and SPI transmit flag
7
6
5
4
3
2
1
0
Address
03h
UTXIFG1
URXIFG1
rw-1
rw-0
URXIFG1‡: USART1: UART and SPI receive flag
UTXIFG1‡: USART1: UART and SPI transmit flag
URXIFG1 and UTXIFG1 are not present in MSP430x15x devices.
‡
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ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢆ
ꢉ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢊ
ꢆ
ꢉ
ꢀ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢊ
ꢇ
ꢆ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
module enable registers 1 and 2
7
6
5
4
3
2
1
0
Address
04h
UTXE0
URXE0
USPIE0
rw-0
rw-0
URXE0:
USART0: UART mode receive enable
USART0: UART mode transmit enable
UTXE0:
USPIE0:
USART0: SPI mode transmit and receive enable
7
6
5
4
3
2
1
0
Address
05h
UTXE1
URXE1
USPIE1
rw-0
rw-0
URXE1†:
USART1: UART mode receive enable
USART1: UART mode transmit enable
UTXE1†:
USPIE1†:
USART1: SPI mode transmit and receive enable
†
URXE1, UTXE1, and USPIE1 are not present in MSP430x15x devices.
Legend: rw:
rw-0:
Bit Can Be Read and Written
Bit Can Be Read and Written. It Is Reset by PUC.
SFR Bit Not Present in Device
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SLAS368D− OCTOBER 2002− REVISED MARCH 2005
memory organization (MSP430F15x)
MSP430F155
MSP430F156
MSP430F157
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
16KB
0FFFFh − 0FFE0h
0FFFFh − 0C000h
24KB
0FFFFh − 0FFE0h
0FFFFh − 0A000h
32KB
0FFFFh − 0FFE0h
0FFFFh − 08000h
Information memory
Boot memory
RAM
Size
Flash
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Size
ROM
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
Size
512B
1KB
1KB
03FFh − 0200h
05FFh − 0200h
05FFh − 0200h
Peripherals
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
memory organization (MSP430F16x)
MSP430F167
32KB
0FFFFh − 0FFE0h
0FFFFh − 08000h
MSP430F168
MSP430F169
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
48KB
0FFFFh − 0FFE0h
0FFFFh − 04000h
60KB
0FFFFh − 0FFE0h
0FFFFh − 01100h
Information memory
Boot memory
RAM
Size
Flash
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Size
ROM
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
Size
1KB
2KB
2KB
05FFh − 0200h
09FFh − 0200h
09FFh − 0200h
Peripherals
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
memory organization (MSP430F161x)
MSP430F1610
32KB
0FFFFh − 0FFE0h
0FFFFh − 08000h
MSP430F1611
MSP430F1612
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
48KB
0FFFFh − 0FFE0h
0FFFFh − 04000h
55KB
0FFFFh − 0FFE0h
0FFFFh − 02500h
RAM (Total)
Size
Size
Size
5KB
10KB
038FFh − 01100h
5KB
024FFh − 01100h
024FFh − 01100h
Extended
3KB
8KB
3KB
024FFh − 01900h
038FFh − 01900h
024FFh − 01900h
Mirrored
2KB
2KB
2KB
018FFh − 01100h
018FFh − 01100h
018FFh − 01100h
Information memory
Boot memory
Size
Flash
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Size
1KB
1KB
1KB
ROM
0FFFh − 0C00h
0FFFh − 0C00h
0FFFh − 0C00h
RAM
Size
2KB
2KB
2KB
(mirrored at
018FFh - 01100h)
09FFh − 0200h
09FFh − 0200h
09FFh − 0200h
Peripherals
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
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SLAS368D− OCTOBER 2002− REVISED MARCH 2005
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
BSL Function
Data Transmit
Data Receive
PM, RTD Package Pins
13 - P1.1
22 - P2.2
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D
Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D
D
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A and B can be erased individually, or as a group with segments 0−n.
Segments A and B are also called information memory.
D
New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
MSP430F161x
48KB
MSP430F15x and MSP430F16x
16KB
24KB
32KB
48KB
60KB
32KB
55KB
Segment 0
0FFFFh
0FFFFh
0FFFFh
0FFFFh
0FFFFh
0FFFFh
0FFFFh
0FFFFh
w/ Interrupt Vectors
0FE00h
0FDFFh 0FDFFh
0FE00h
0FE00h
0FDFFh 0FDFFh 0FDFFh
0FE00h
0FE00h
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
Segment 1
Segment 2
0FC00h
0FBFFh 0FBFFh
0FC00h
0FC00h
0FBFFh 0FBFFh 0FBFFh
0FC00h
0FC00h
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
Main
Memory
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0C400h
0C3FFh 0A3FFh
0A400h
08400h
083FFh
04400h
043FFh
01400h
013FFh
08400h
083FFh
04400h
043FFh
02800h
027FFh
Segment n-1
0C200h
0C1FFh 0A1FFh
0A200h
08200h
081FFh
04200h
041FFh
01200h
011FFh
08200h
081FFh
04200h
041FFh
02600h
025FFh
Segment n†
0C000h
010FFh
0A000h
08000h
04000h
01100h
08000h
024FFh
04000h
038FFh
02500h
024FFh
RAM
(’F161x
only)
01100h
010FFh
01100h
010FFh
01100h
010FFh
010FFh
010FFh
010FFh
010FFh
Segment A
Segment B
Info
Memory
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01000h
01000h
01000h
01000h
01000h
01000h
01000h
01000h
†
MSP430F169 and MSP430F1612 flash segment n = 256 bytes.
15
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ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature number
SLAU049.
DMA controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to
or from a peripheral.
oscillator and system clock
The clock system in the MSP430x15x and MSP430x16x(x) family of devices is supported by the basic clock
module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator
(DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements
of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source
and stabilizes in less than 6 µs. The basic clock module provides the following clock signals:
D
D
D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, V may not
CC
have ramped to V
at that time. The user must insure the default DCO settings are not changed until V
CC(min)
CC
reaches V
. If desired, the SVS circuit can be used to determine when V reaches V
.
CC(min)
CC
CC(min)
digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6:
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
hardware multiplier (MSP430x16x/161x Only)
The multiplication operation is supported by a dedicated peripheral module. The module performs 16 16,
16 8, 8 16, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
16
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ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
USART0
The MSP430x15x and the MSP430x16x(x) have one hardware universal synchronous/asynchronous receive
transmit (USART0) peripheral module that is used for serial data communication. The USART supports
synchronous SPI (3 or 4 pin), asynchronous UART and I2C communication protocols using double-buffered
transmit and receive channels.
2
2
The I C support is compliant with the Philips I C specification version 2.1 and supports standard mode (up to
100 kbps) and fast mode (up to 400 kbps). In addition, 7-bit and 10-bit device addressing modes are supported,
2
as well as master and slave modes. The USART0 also supports 16-bit-wide I C data transfers and has two
dedicated DMA channels to maximize bus throughput. Extensive interrupt capability is also given in the I C
2
mode.
USART1 (MSP430x16x/161x Only)
The MSP430x16x(x) devices have a second hardware universal synchronous/asynchronous receive transmit
(USART1) peripheral module that is used for serial data communication. The USART supports synchronous
SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive
channels. With the exception of I2C support, operation of USART1 is identical to USART0.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number Device Input Signal Module Input Name
Module Block
Module Output Signal
Output Pin Number
12 - P1.0
TACLK
ACLK
TACLK
ACLK
Timer
NA
SMCLK
TAINCLK
TA0
SMCLK
INCLK
CCI0A
CCI0B
GND
21 - P2.1
13 - P1.1
22 - P2.2
13 - P1.1
17 - P1.5
27 - P2.7
TA0
CCR0
CCR1
CCR2
TA0
TA1
TA2
DV
DV
SS
CC
V
CC
14 - P1.2
15 - P1.3
TA1
CAOUT (internal)
CCI1A
CCI1B
GND
14 - P1.2
18 - P1.6
DV
DV
23 - P2.3
SS
CC
V
CC
ADC12 (internal)
15 - P1.3
TA2
ACLK (internal)
CCI2A
CCI2B
GND
19 - P1.7
DV
DV
24 - P2.4
SS
CC
V
CC
timer_B3 (MSP430x15x Only)
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
17
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ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
timer_B7 (MSP430x16x/161x Only)
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
†
Timer_B3/B7 Signal Connections
Input Pin Number Device Input Signal Module Input Name
Module Block
Module Output Signal
Output Pin Number
43 - P4.7
TBCLK
ACLK
SMCLK
TBCLK
TB0
TBCLK
ACLK
Timer
NA
SMCLK
INCLK
CCI0A
CCI0B
GND
43 - P4.7
36 - P4.0
36 - P4.0
36 - P4.0
TB0
ADC12 (internal)
CCR0
CCR1
CCR2
CCR3
CCR4
CCR5
CCR6
TB0
TB1
TB2
TB3
TB4
TB5
TB6
DV
SS
CC
DV
V
CC
37 - P4.1
37 - P4.1
TB1
TB1
CCI1A
CCI1B
GND
37 - P4.1
ADC12 (internal)
DV
DV
SS
CC
V
CC
38 - P4.2
38 - P4.2
TB2
TB2
CCI2A
CCI2B
GND
38 - P4.2
39 - P4.3
40 - P4.4
41 - P4.5
42 - P4.6
DV
DV
SS
CC
V
CC
39 - P4.3
39 - P4.3
TB3
TB3
CCI3A
CCI3B
GND
DV
DV
SS
CC
V
CC
40 - P4.4
40 - P4.4
TB4
TB4
CCI4A
CCI4B
GND
DV
DV
SS
CC
V
CC
41 - P4.5
41 - P4.5
TB5
TB5
CCI5A
CCI5B
GND
DV
DV
SS
CC
V
CC
42 - P4.6
TB6
ACLK (internal)
CCI6A
CCI6B
GND
DV
SS
CC
DV
V
CC
†
Timer_B3 implements three capture/compare blocks (CCR0, CCR1 and CCR2 only).
18
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ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
comparator_A
The primary function of the comparator_A module is to support precision slope analog−to−digital conversions,
battery−voltage supervision, and monitoring of external analog signals.
ADC12
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without
any CPU intervention.
DAC12
The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode,
and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may
be grouped together for synchronous operation.
19
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
peripheral file map
PERIPHERAL FILE MAP
DMA
DMA channel 2 transfer size
DMA channel 2 destination address
DMA channel 2 source address
DMA channel 2 control
DMA channel 1 transfer size
DMA channel 1 destination address
DMA channel 1 source address
DMA channel 1 control
DMA channel 0 transfer size
DMA channel 0 destination address
DMA channel 0 source address
DMA channel 0 control
DMA module control 1
DMA module control 0
DAC12_1 data
DMA2SZ
01F6h
01F4h
01F2h
01F0h
01EEh
01ECh
01EAh
01E8h
01E6h
01E4h
01E2h
01E0h
0124h
0122h
01CAh
01C2h
01C8h
01C0h
01A8h
01A6h
01A4h
01A2h
01A0h
DMA2DA
DMA2SA
DMA2CTL
DMA1SZ
DMA1DA
DMA1SA
DMA1CTL
DMA0SZ
DMA0DA
DMA0SA
DMA0CTL
DMACTL1
DMACTL0
DAC12_1DAT
DAC12_1CTL
DAC12_0DAT
DAC12_0CTL
ADC12IV
DAC12
ADC12
DAC12_1 control
DAC12_0 data
DAC12_0 control
Interrupt-vector-word register
Inerrupt-enable register
Inerrupt-flag register
ADC12IE
ADC12IFG
ADC12CTL1
ADC12CTL0
Control register 1
Control register 0
Conversion memory 15
Conversion memory 14
Conversion memory 13
Conversion memory 12
Conversion memory 11
Conversion memory 10
Conversion memory 9
Conversion memory 8
Conversion memory 7
Conversion memory 6
Conversion memory 5
Conversion memory 4
Conversion memory 3
Conversion memory 2
Conversion memory 1
Conversion memory 0
ADC12MEM15 015Eh
ADC12MEM14 015Ch
ADC12MEM13 015Ah
ADC12MEM12 0158h
ADC12MEM11 0156h
ADC12MEM10 0154h
ADC12MEM9
ADC12MEM8
ADC12MEM7
ADC12MEM6
ADC12MEM5
ADC12MEM4
ADC12MEM3
ADC12MEM2
ADC12MEM1
ADC12MEM0
0152h
0150h
014Eh
014Ch
014Ah
0148h
0146h
0144h
0142h
0140h
20
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ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
peripheral file map (continued)
PERIPHERAL FILE MAP (CONTINUED)
ADC memory-control register15
ADC memory-control register14
ADC memory-control register13
ADC memory-control register12
ADC memory-control register11
ADC memory-control register10
ADC memory-control register9
ADC memory-control register8
ADC memory-control register7
ADC memory-control register6
ADC memory-control register5
ADC memory-control register4
ADC memory-control register3
ADC memory-control register2
ADC memory-control register1
ADC memory-control register0
Capture/compare register 6
Capture/compare register 5
Capture/compare register 4
Capture/compare register 3
Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_B register
ADC12
(continued)
ADC12MCTL15 08Fh
ADC12MCTL14 08Eh
ADC12MCTL13 08Dh
ADC12MCTL12 08Ch
ADC12MCTL11 08Bh
ADC12MCTL10 08Ah
ADC12MCTL9
ADC12MCTL8
ADC12MCTL7
ADC12MCTL6
ADC12MCTL5
ADC12MCTL4
ADC12MCTL3
ADC12MCTL2
ADC12MCTL1
ADC12MCTL0
TBCCR6
089h
088h
087h
086h
085h
084h
083h
082h
081h
080h
Timer_B7/
Timer_B3
(see Note 1)
019Eh
019Ch
019Ah
0198h
0196h
0194h
0192h
0190h
018Eh
018Ch
018Ah
0188h
0186h
0184h
0182h
0180h
011Eh
017Eh
017Ch
017Ah
0178h
0176h
0174h
0172h
0170h
016Eh
016Ch
016Ah
0168h
TBCCR5
TBCCR4
TBCCR3
TBCCR2
TBCCR1
TBCCR0
TBR
Capture/compare control 6
Capture/compare control 5
Capture/compare control 4
Capture/compare control 3
Capture/compare control 2
Capture/compare control 1
Capture/compare control 0
Timer_B control
TBCCTL6
TBCCTL5
TBCCTL4
TBCCTL3
TBCCTL2
TBCCTL1
TBCCTL0
TBCTL
Timer_B interrupt vector
Reserved
TBIV
Timer_A3
Reserved
Reserved
Reserved
Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_A register
TACCR2
TACCR1
TACCR0
TAR
Reserved
Reserved
Reserved
Reserved
NOTE 1: Timer_B7 in MSP430x16x/161x family has 7 CCRs, Timer_B3 in MSP430x15x family has 3 CCRs.
21
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
peripheral file map (continued)
PERIPHERAL FILE MAP (CONTINUED)
Capture/compare control 2
Timer_A3
(continued)
TACCTL2
TACCTL1
TACCTL0
TACTL
0166h
0164h
0162h
0160h
012Eh
013Eh
013Ch
013Ah
0138h
0136h
0134h
0132h
0130h
012Ch
012Ah
0128h
0120h
07Fh
07Eh
07Dh
07Ch
07Bh
07Ah
079h
Capture/compare control 1
Capture/compare control 0
Timer_A control
Timer_A interrupt vector
Sum extend
TAIV
Hardware
Multiplier
(MSP430x16x and
MSP430x161x
only)
SUMEXT
RESHI
Result high word
Result low word
Second operand
Multiply signed +accumulate/operand1
Multiply+accumulate/operand1
Multiply signed/operand1
Multiply unsigned/operand1
Flash control 3
RESLO
OP2
MACS
MAC
MPYS
MPY
Flash
FCTL3
Flash control 2
FCTL2
Flash control 1
FCTL1
Watchdog
Watchdog Timer control
Transmit buffer
WDTCTL
U1TXBUF
U1RXBUF
U1BR1
U1BR0
U1MCTL
U1RCTL
U1TCTL
U1CTL
U0TXBUF
U0RXBUF
U0BR1
U0BR0
U0MCTL
U0RCTL
U0TCTL
U0CTL
I2CIV
USART1
(MSP430x16x and
MSP430x161x
only)
Receive buffer
Baud rate
Baud rate
Modulation control
Receive control
Transmit control
USART control
078h
USART0
(UART or
SPI mode)
Transmit buffer
077h
Receive buffer
076h
Baud rate
075h
Baud rate
074h
Modulation control
Receive control
Transmit control
USART control
073h
072h
071h
070h
USART0
I2C interrupt vector
I2C slave address
I2C own address
I2C data
011Ch
011Ah
0118h
076h
2
(I C mode)
I2CSA
I2COA
I2CDR
I2C SCLL
I2CSCLL
I2CSCLH
I2CPSC
I2CDCTL
I2CTCTL
U0CTL
I2CNDAT
I2CIFG
I2CIE
075h
I2C SCLH
074h
I2C PSC
073h
I2C data control
I2C transfer control
USART control
072h
071h
070h
I2C data count
052h
I2C interrupt flag
I2C interrupt enable
051h
050h
22
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ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
peripheral file map (continued)
PERIPHERAL FILE MAP (CONTINUED)
Comparator_A port disable
Comparator_A control2
Comparator_A
CAPD
05Bh
05Ah
059h
058h
057h
056h
055h
037h
036h
035h
034h
033h
032h
031h
030h
01Fh
01Eh
01Dh
01Ch
01Bh
01Ah
019h
018h
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
026h
025h
024h
023h
022h
021h
020h
005h
004h
003h
002h
001h
000h
CACTL2
CACTL1
BCSCTL2
BCSCTL1
DCOCTL
Comparator_A control1
Basic Clock
Basic clock system control2
Basic clock system control1
DCO clock frequency control
BrownOUT, SVS
Port P6
SVS control register (reset by brownout signal) SVSCTL
Port P6 selection
Port P6 direction
Port P6 output
P6SEL
P6DIR
P6OUT
P6IN
Port P6 input
Port P5
Port P4
Port P3
Port P2
Port P5 selection
Port P5 direction
Port P5 output
P5SEL
P5DIR
P5OUT
P5IN
Port P5 input
Port P4 selection
Port P4 direction
Port P4 output
P4SEL
P4DIR
P4OUT
P4IN
Port P4 input
Port P3 selection
Port P3 direction
Port P3 output
P3SEL
P3DIR
P3OUT
P3IN
Port P3 input
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt-edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
Port P2 input
Port P1
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt-edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
Port P1 input
Special Functions
SFR module enable 2
SFR module enable 1
SFR interrupt flag2
SFR interrupt flag1
SFR interrupt enable2
SFR interrupt enable1
ME2
ME1
IFG2
IFG1
IE2
IE1
23
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Voltage applied at V to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
CC
SS
Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.3 V
CC
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature, T : (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
stg
(programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to V . The JTAG fuse-blow voltage, V , is allowed to exceed the absolute maximum rating. The voltage is applied
SS
FB
to the TDI/TCLK pin when blowing the JTAG fuse.
recommended operating conditions
MIN
NOM
MAX UNITS
Supply voltage during program execution,
MSP430F15x/16x/
161x
1.8
3.6
3.6
V
V
V
CC
(AV = DV = V
)
CC
CC
CC
Supply voltage during flash memory programming, V
MSP430F15x/16x/
161x
CC
2.7
(AV = DV = V )
CC
CC
CC
Supply voltage during program execution, SVS enabled (see
Note 1), V (AV = DV = V
MSP430F15x/16x/
161x
2
0
3.6
0
V
V
)
CC
CC
CC
CC
Supply voltage, V (AV = DV = V
SS
)
SS
SS
SS
MSP430F15x/16x/
161x
Operating free-air temperature range, T
−40
85
°C
A
LF selected, XTS=0
Watch crystal
32.768
kHz
kHz
kHz
LFXT1 crystal frequency, f
(see Notes 2 and 3)
(LFXT1)
XT1 selected, XTS=1 Ceramic resonator
XT1 selected, XTS=1 Crystal
Ceramic resonator
450
1000
450
8000
8000
8000
8000
4.15
8
XT2 crystal frequency, f
kHz
(XT2)
Crystal
1000
DC
V
CC
V
CC
= 1.8 V
= 3.6 V
Processor frequency (signal MCLK), f
MHz
(System)
DC
NOTES: 1. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply
voltage. POR is going inactive when the V is raised above the minimum supply voltage plus the hysteresis of the SVS circuitry.
CC
2. In LF mode, the LFXT1 oscillator requires a watch crystal. A 5.1MΩ resistor from XOUT to V is recommended when V
<
SS
CC
2.5 V. In XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 4.15MHz at V ≥ 2.2 V. In XT1 mode,
CC
the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 8MHz at V ≥ 2.8 V.
CC
3. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
f (MHz)
8.0 MHz
Supply voltage range,
Supply voltage range,
’F15x/16x/161x, during
’F15x/16x/161x,
program execution
during flash memory programming
4.15 MHz
1.8 V
2.7 V 3 V
3.6 V
Supply Voltage − V
Figure 1. Frequency vs Supply Voltage, MSP430F15x/16x/161x
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
MSP430F15x/16x supply current into AV + DV excluding external current (AV = DV = V
)
CC
CC
CC
CC
CC
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
Active mode, (see Note 1)
V
CC
V
CC
V
CC
V
CC
= 2.2 V
= 3 V
330
400
600
7
f
f
= f
= 1 MHz,
(MCLK)
(SMCLK)
T
= −40°C to 85°C
= −40°C to 85°C
µA
A
= 32,768 Hz
(ACLK)
500
2.5
9
XTS=0, SELM=(0,1)
I
(AM)
Active mode, (see Note 1)
= 2.2 V
= 3 V
f
f
= f
= 4,096 Hz,
(MCLK)
(SMCLK)
T
A
µA
= 4,096 Hz
(ACLK)
20
XTS=0, SELM=3
Low-power mode, (LPM0)
V
V
= 2.2 V
= 3 V
50
75
60
90
CC
CC
f
f
= 0 MHz, f
= 32,768 Hz
= 1 MHz,
(MCLK)
(SMCLK)
I
I
T
= −40°C to 85°C
= −40°C to 85°C
µA
µA
(ACLK)
(LPM0)
A
XTS=0, SELM=(0,1)
(see Note 1)
Low-power mode, (LPM2),
V
V
= 2.2 V
= 3 V
11
17
14
22
CC
f
f
= f
= 0 MHz,
T
A
(MCLK)
(ACLK)
(SMCLK)
(LPM2)
= 32.768 Hz, SCG0 = 0
CC
T
= −40°C
= 25°C
= 85°C
= −40°C
= 25°C
= 85°C
= −40°C
= 25°C
= 85°C
1.1
1.1
2.2
2.2
2.0
3.0
0.1
0.2
1.3
1.6
1.6
3.0
2.8
2.6
4.3
0.5
0.5
2.5
A
T
A
V
= 2.2 V
CC
Low-power mode, (LPM3)
T
A
f
f
= f
= 0 MHz,
(MCLK)
(SMCLK)
I
µA
µA
(LPM3)
= 32,768 Hz, SCG0 = 1
T
A
(ACLK)
(see Note 2)
T
A
V
V
= 3 V
=
CC
T
A
T
A
Low-power mode, (LPM4)
CC
T
A
f
f
= 0 MHz, f
= 0 Hz, SCG0 = 1
= 0 MHz,
I
(MCLK)
(ACLK)
(SMCLK)
(LPM4)
2.2V / 3 V
T
A
NOTES: 1. Timer_B is clocked by f
= 1 MHz. All inputs are tied to 0 V or to V . Outputs do not source or sink any current.
CC
(DCOCLK)
2. WDT is clocked by f
= 32,768 Hz. All inputs are tied to 0 V or to V . Outputs do not source or sink any current. The current
(ACLK)
CC
consumption in LPM2 and LPM3 are measured with ACLK selected.
Current consumption of active mode versus system frequency, F-version
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
Current consumption of active mode versus supply voltage, F-version
I
= I
+ 210 µA/V × (V – 3 V)
(AM) [3 V] CC
(AM)
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
MSP430F161x supply current into AV + DV excluding external current (AV = DV = V )
CC
CC
CC
CC
CC
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
Active mode, (see Note 1)
V
CC
V
CC
V
CC
V
CC
= 2.2 V
= 3 V
330
500
2.5
9
400
f
f
= f
= 1 MHz,
(MCLK)
(SMCLK)
T
= −40°C to 85°C
= −40°C to 85°C
µA
A
= 32,768 Hz
(ACLK)
600
7
XTS=0, SELM=(0,1)
I
(AM)
Active mode, (see Note 1)
= 2.2 V
= 3 V
f
f
= f
= 4,096 Hz,
(MCLK)
(SMCLK)
T
A
µA
= 4,096 Hz
(ACLK)
20
XTS=0, SELM=3
Low-power mode, (LPM0)
V
V
= 2.2 V
= 3 V
50
75
60
95
CC
CC
f
f
= 0 MHz, f
= 32,768 Hz
= 1 MHz,
(MCLK)
(SMCLK)
I
I
T
= −40°C to 85°C
= −40°C to 85°C
µA
µA
(ACLK)
(LPM0)
A
XTS=0, SELM=(0,1)
(see Note 1)
Low-power mode, (LPM2),
V
V
= 2.2 V
= 3 V
11
17
14
22
CC
f
f
= f
= 0 MHz,
T
A
(MCLK)
(ACLK)
(SMCLK)
(LPM2)
= 32.768 Hz, SCG0 = 0
CC
T
= −40°C
= 25°C
= 85°C
= −40°C
= 25°C
= 85°C
= −40°C
= 25°C
= 85°C
1.3
1.3
3.0
2.6
2.6
4.4
0.2
0.2
2.0
1.6
1.6
6.0
3.0
3.0
8.0
0.5
0.5
5.0
A
T
A
V
= 2.2 V
CC
Low-power mode, (LPM3)
T
A
f
f
= f
= 0 MHz,
(MCLK)
(SMCLK)
I
µA
µA
(LPM3)
= 32,768 Hz, SCG0 = 1
T
A
(ACLK)
(see Note 2)
T
A
V
V
= 3 V
=
CC
T
A
T
A
Low-power mode, (LPM4)
CC
T
A
f
f
= 0 MHz, f
= 0 Hz, SCG0 = 1
= 0 MHz,
I
(MCLK)
(ACLK)
(SMCLK)
(LPM4)
2.2V / 3 V
T
A
NOTES: 1. Timer_B is clocked by f
= 1 MHz. All inputs are tied to 0 V or to V . Outputs do not source or sink any current.
CC
(DCOCLK)
2. WDT is clocked by f
= 32,768 Hz. All inputs are tied to 0 V or to V . Outputs do not source or sink any current. The current
(ACLK)
CC
consumption in LPM2 and LPM3 are measured with ACLK selected.
Current consumption of active mode versus system frequency, F-version
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
Current consumption of active mode versus supply voltage, F-version
I
= I
+ 210 µA/V × (V – 3 V)
(AM) [3 V] CC
(AM)
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SCHMITT-trigger inputs − Ports P1, P2, P3, P4, P5, P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER
TEST CONDITIONS
MIN
1.1
1.5
0.4
0.9
0.3
0.5
TYP
MAX
1.5
1.98
0.9
1.3
1.1
1
UNIT
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.2 V
= 3 V
V
IT+
V
IT−
V
hys
Positive-going input threshold voltage
V
= 2.2 V
= 3 V
Negative-going input threshold voltage
V
V
= 2.2 V
= 3 V
Input voltage hysteresis (V − V
)
IT−
IT+
inputs Px.x, TAx, TBx
PARAMETER
TEST CONDITIONS
V
MIN
62
TYP
MAX
UNIT
CC
2.2 V
3 V
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag, (see Note 1)
t
t
External interrupt timing
ns
(int)
50
TA0, TA1, TA2
2.2 V
62
Timer_A, Timer_B capture
timing
ns
(cap)
TB0, TB1, TB2, TB3, TB4, TB5, TB6
(see Note 2)
3 V
50
Timer_A, Timer_B clock
frequency externally applied
to pin
f
f
2.2 V
3 V
8
(TAext)
TACLK, TBCLK, INCLK: t = t
MHz
MHz
(H)
(L)
10
(TBext)
f
f
2.2 V
3 V
8
(TAint)
Timer_A, Timer_B clock
frequency
SMCLK or ACLK signal selected
10
(TBint)
NOTES: 1. The external signal sets the interrupt flag every time the minimum t
parameters are met. It may be set even with trigger signals
(int)
shorter than t
.
(int)
2. Seven capture/compare registers in ’x16x/161x and three capture/compare registers in ’x15x.
leakage current − Ports P1, P2, P3, P4, P5 and P6 (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Leakage
current
I
Port Px
V
(Px.y)
(see Note 2)
V = 2.2 V/3 V
CC
±50
nA
lkg(Px.y)
NOTES: 1. The leakage current is measured with V or V applied to the corresponding pin(s), unless otherwise noted.
SS
CC
2. The port pin must be selected as input.
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1, P2, P3, P4, P5, and P6
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
I
I
I
I
I
I
I
= −1.5 mA,
= −6 mA,
= −1.5 mA,
= −6 mA,
= 1.5 mA,
= 6 mA,
V
V
V
V
V
V
V
V
= 2.2 V,
= 2.2 V,
= 3 V,
See Note 1
See Note 2
See Note 1
See Note 2
See Note 1
See Note 2
See Note 1
See Note 2
V
−0.25
V
V
V
V
OH(max)
OH(max)
OH(max)
OH(max)
OL(max)
OL(max)
OL(max)
OL(max)
OH(max)
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
V
−0.6
CC
V
High-level output voltage
V
OH
V
CC
−0.25
= 3 V,
V
−0.6
CC
= 2.2 V,
= 2.2 V,
= 3 V,
V
SS
V
SS
V
SS
V
SS
V
+0.25
SS
V
+0.6
SS
V
OL
Low-level output voltage
V
= 1.5 mA,
= 6 mA,
V
SS
+0.25
= 3 V,
V
+0.6
SS
NOTES: 1. The maximum total current, I
specified voltage drop.
and I
for all outputs combined, should not exceed ±12 mA to satisfy the maximum
OL(max),
2. The maximum total current, I
specified voltage drop.
and I
for all outputs combined, should not exceed ±48 mA to satisfy the maximum
OH(max)
OL(max),
output frequency
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
C = 20 pF,
I = ±1.5 mA
L
L
f
(1 ≤ x ≤ 6, 0 ≤ y ≤ 7)
V
V
= 2.2 V / 3 V
= 2.2 V / 3 V
DC
f
f
MHz
(Px.y)
CC
System
f
f
f
P2.0/ACLK, P5.6/ACLK
P5.4/MCLK,
P1.4/SMCLK, P5.5/SMCLK
(ACLK)
System
C = 20 pF
L
MHz
(MCLK)
(SMCLK)
CC
f
f
f
f
= f
= f
= f
= f
= f
40%
30%
60%
70%
(ACLK)
(ACLK)
(ACLK)
(MCLK)
(LFXT1)
(LFXT1)
(LFXT1)
(XT1)
P1.0/TACLK
C = 20 pF
(LF)
L
V
CC
= 2.2 V / 3 V
50%
50%
= f
40%
60%
(XT1)
(DCOCLK)
P1.1/TA0/MCLK,
t
Duty cycle of output frequency
C = 20 pF,
(Xdc)
50%−
15 ns
50%+
15 ns
L
f
f
f
= f
(MCLK)
V
CC
= 2.2 V / 3 V
= f
40%
60%
(SMCLK)
(SMCLK)
(XT2)
P1.4/TBCLK/SMCLK,
C = 20 pF,
50%−
15 ns
50%+
15 ns
L
= f
50%
(DCOCLK)
V
CC
= 2.2 V / 3 V
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1, P2, P3, P4, P5, and P6 (continued)
TYPICAL LOW-LEVEL OUTPUT CURRENT
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
25
20
15
10
5
40
30
20
10
0
V
P3.5
= 2.2 V
T
= 25°C
V
P3.5
= 3 V
CC
A
CC
T
= 25°C
A
T
= 85°C
A
T
= 85°C
A
0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OL
− Low-Level Output Voltage − V
V
OL
− Low-Level Output Voltage − V
Figure 2
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
0
−5
V
P3.5
= 2.2 V
CC
V
P3.5
= 3 V
CC
−5
−15
−25
−35
−45
−10
−15
−20
−25
T
A
= 85°C
T
A
= 85°C
T
A
= 25°C
T
A
= 25°C
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OH
− High-Level Output Voltage − V
V
OH
− High-Level Output Voltage − V
Figure 5
Figure 4
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
DCO
= 2.2 V/3 V,
CC
t
Delay time
6
µs
(LPM3)
f
≥ f
DCO43
RAM
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VRAMh
CPU HALTED (see Note 1)
1.6
V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
Comparator_A (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
25
MAX UNIT
V
V
= 2.2 V
= 3 V
40
µA
60
CC
I
I
CAON=1, CARSEL=0, CAREF=0
(DD)
45
CC
CAON=1, CARSEL=0,
CAREF=1/2/3, no load at
P2.3/CA0/TA1 and P2.4/CA1/TA2
V
= 2.2 V
= 3 V
30
45
50
µA
71
CC
CC
(Refladder/Refdiode)
V
Common-mode input
voltage
V
CAON =1
V
= 2.2 V/3 V
= 2.2 V/3 V
0
V −1
CC
V
(IC)
CC
CC
PCA0=1, CARSEL=1, CAREF=1,
no load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
Voltage @ 0.25 V
node
node
V
V
0.23
0.24
0.48
0.25
0.5
CC
(Ref025)
V
CC
PCA0=1, CARSEL=1, CAREF=2,
no load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
Voltage @ 0.5V
CC
V
V
V
CC
= 2.2 V/3 V
0.47
(Ref050)
V
CC
PCA0=1, CARSEL=1, CAREF=3,
no load at P2.3/CA0/TA1 and
P2.4/CA1/TA2 T = 85°C
V
V
= 2.2 V
= 3 V
390
400
480
490
540
550
CC
(see Figure 6 and Figure 7)
mV
(RefVT)
CC
A
V
V
Offset voltage
See Note 2
CAON=1
V
V
V
V
V
V
V
V
= 2.2 V/3 V
= 2.2 V/3 V
= 2.2 V
= 3 V
−30
0
30
1.4
mV
mV
(offset)
CC
CC
CC
CC
CC
CC
CC
CC
Input hysteresis
0.7
210
150
1.9
hys
130
80
300
240
3.4
T
A
= 25°C, Overdrive 10 mV,
ns
µs
ns
µs
Without filter: CAF=0
t
(response LH)
= 2.2 V
= 3 V
1.4
0.9
130
80
T
A
= 25°C, Overdrive 10 mV,
With filter: CAF=1
1.5
2.6
= 2.2 V
= 3 V
210
150
300
240
T
A
= 25°C, Overdrive 10 mV,
Without filter: CAF=0
t
(response HL)
V
V
= 2.2 V
= 3 V
1.4
0.9
1.9
1.5
3.4
2.6
CC
T
A
= 25°C, Overdrive 10 mV,
With filter: CAF=1
CC
NOTES: 1. The leakage current for the Comparator_A terminals is identical to I
specification.
lkg(Px.x)
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
650
600
550
500
450
400
650
600
550
500
450
400
V
= 2.2 V
V
CC
= 3 V
CC
Typical
Typical
−45
−25
−5
15
35
55
75
95
−45
−25
−5
15
35
55
75
95
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 7. V
vs Temperature, V = 2.2 V
Figure 6. V
vs Temperature, V = 3 V
CC
(RefVT)
CC
(RefVT)
0 V
V
CC
0
1
CAF
CAON
To Internal
Modules
Low Pass Filter
0
1
0
1
+
_
V+
V−
CAOUT
Set CAIFG
Flag
τ ≈ 2.0 µs
Figure 8. Block Diagram of Comparator_A Module
V
CAOUT
Overdrive
V−
400 mV
V+
t
(response)
Figure 9. Overdrive Definition
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
POR/brownout reset (BOR) (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µs
t
2000
d(BOR)
V
dV /dt ≤ 3 V/s (see Figure 10)
CC
0.7 × V
(B_IT−)
V
CC(Start)
V
V
dV /dt ≤ 3 V/s (see Figure 10 through Figure 12)
1.71
180
V
(B_IT−)
CC
Brownout
dV /dt ≤ 3 V/s (see Figure 10)
CC
70
2
130
mV
hys(B_IT−)
Pulse length needed at RST/NMI pin to accepted reset internally,
t
µs
(reset)
V
CC
= 2.2 V/3 V
NOTES: 1. The current consumption of the brownout module is already included in the I current consumption data. The voltage level V
CC
(B_IT−)
+ V
is ≤ 1.8 V.
hys(B_IT−)
2. During power up, the CPU begins code execution following a period of t
default DCO settings must not be changed until V ≥ V , where V is the minimum supply voltage for the desired
CC(min)
after V = V
+ V . The
hys(B_IT−)
BOR(delay)
CC
(B_IT−)
CC
CC(min)
operating frequency. See the MSP430x1xx Family User’s Guide (SLAU049) for more information on the brownout/SVS circuit.
typical characteristics
V
CC
V
hys(B_IT−)
V
(B_IT−)
V
CC(Start)
BOR
1
0
t
d(BOR)
Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
typical characteristics (continued)
V
t
CC
pw
2
3 V
Vcc = 3 V
typical conditions
1.5
1
0.5
0
V
CC(min)
0.001
1
1000
1 ns
1 ns
− Pulse Width − µs
t
− Pulse Width − µs
t
pw
pw
Figure 11. V
Level With a Square Voltage Drop to Generate a POR/Brownout Signal
CC(min)
V
t
CC
pw
2
3 V
Vcc = 3 V
typical conditions
1.5
1
V
CC(min)
0.5
0
t = t
f
r
0.001
1
1000
t
t
r
f
t
− Pulse Width − µs
t
− Pulse Width − µs
pw
pw
Figure 12. V
Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
CC(min)
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
SVS (supply voltage supervisor/monitor)
PARAMETER
TEST CONDITIONS
dV /dt > 30 V/ms (see Figure 13)
MIN
NOM
MAX
150
2000
150
12
UNIT
µs
5
CC
t
(SVSR)
dV /dt ≤ 30 V/ms
CC
µs
t
t
SVSON, switch from VLD = 0 to VLD ≠ 0, V = 3 V
20
µs
d(SVSon)
CC
‡
VLD ≠ 0
µs
settle
V
VLD ≠ 0, V /dt ≤ 3 V/s (see Figure 13)
1.55
120
1.7
V
(SVSstart)
CC
VLD = 1
70
155
mV
V
V
/dt ≤ 3 V/s (see Figure 13)
V
V
(SVS_IT−)
x 0.008
CC
(SVS_IT−)
x 0.004
VLD = 2 .. 14
V
hys(SVS_IT−)
/dt ≤ 3 V/s (see Figure 13), External voltage applied
CC
VLD = 15
4.4
10.4
mV
on A7
VLD = 1
VLD = 2
VLD = 3
VLD = 4
VLD = 5
VLD = 6
VLD = 7
VLD = 8
VLD = 9
VLD = 10
VLD = 11
VLD = 12
VLD = 13
VLD = 14
1.8
1.9
2.1
2.05
2.25
2.37
2.48
2.6
1.94
2.05
2.14
2.24
2.33
2.46
2.58
2.69
2.83
2.94
3.11
3.24
3.43
2.2
2.3
2.4
2.5
2.71
2.86
3
2.65
2.8
V
CC
/dt ≤ 3 V/s (see Figure 13 and Figure 14)
V
V
(SVS_IT−)
2.9
3.13
3.29
3.42
3.05
3.2
†
3.35
3.5
3.61
†
3.76
†
†
3.7
3.99
V
/dt ≤ 3 V/s (see Figure 13 and Figure 14), External
CC
VLD = 15
1.1
1.2
10
1.3
15
voltage applied on A7
I
CC(SVS)
VLD ≠ 0, V = 2.2 V/3 V
µA
CC
(see Note 1)
†
‡
The recommended operating voltage range is limited to 3.6 V.
is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
t
settle
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 1: The current consumption of the SVS module is not included in the I current consumption data.
CC
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
typical characteristics
Software sets VLD >0:
SVS is active
AV
CC
V
(SVS_IT−)
hys(SVS_IT−)
V
V
(SVSstart)
V
hys(B_IT−)
V
(B_IT−)
V
CC(start)
Brown-
out
Region
Brownout
Region
Brownout
1
0
t
t
SVS out
1
d(BOR)
d(BOR)
SVS Circuit is Active From VLD > to V < V(
CC
B_IT−)
0
t
t
d(SVSon)
d(SVSR)
Set POR
1
undefined
0
Figure 13. SVS Reset (SVSR) vs Supply Voltage
V
CC
t
pw
3 V
2
Rectangular Drop
V
CC(min)
1.5
1
Triangular Drop
1 ns
1 ns
V
t
CC
pw
0.5
0
3 V
1
10
100
1000
t
− Pulse Width − µs
pw
V
CC(min)
t = t
f
r
t
t
r
f
t − Pulse Width − µs
Figure 14. V
: Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal (VLD = 1)
CC(min)
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
DCO (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
0.08
NOM
0.12
MAX
0.15
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 2.2 V
= 3 V
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
f
R
R
R
R
R
R
R
= 0, DCO = 3, MOD = 0, DCOR = 0, T = 25°C
MHz
(DCO03)
(DCO13)
(DCO23)
(DCO33)
(DCO43)
(DCO53)
(DCO63)
sel
sel
sel
sel
sel
sel
sel
A
0.08
0.14
0.14
0.22
0.22
0.37
0.37
0.61
0.61
1
0.13
0.19
0.18
0.30
0.28
0.49
0.47
0.77
0.75
1.2
0.16
0.23
0.22
0.36
0.34
0.59
0.56
0.93
0.90
1.5
= 2.2 V
= 3 V
f
f
f
f
f
f
= 1, DCO = 3, MOD = 0, DCOR = 0, T = 25°C
MHz
MHz
MHz
MHz
MHz
MHz
A
= 2.2 V
= 3 V
= 2, DCO = 3, MOD = 0, DCOR = 0, T = 25°C
A
= 2.2 V
= 3 V
= 3, DCO = 3, MOD = 0, DCOR = 0, T = 25°C
A
= 2.2 V
= 3 V
= 4, DCO = 3, MOD = 0, DCOR = 0, T = 25°C
A
= 2.2 V
= 3 V
= 5, DCO = 3, MOD = 0, DCOR = 0, T = 25°C
A
1
1.3
1.5
= 2.2 V
= 3 V
1.6
1.9
2.2
= 6, DCO = 3, MOD = 0, DCOR = 0, T = 25°C
A
1.69
2.4
2.0
2.29
3.4
= 2.2 V
= 3 V
2.9
f
f
R
R
= 7, DCO = 3, MOD = 0, DCOR = 0, T = 25°C
MHz
MHz
(DCO73)
sel
sel
A
2.7
3.2
3.65
f
f
f
DCO40
× 2.5
DCO40
DCO40
= 4, DCO = 7, MOD = 0, DCOR = 0, T = 25°C
V
CC
= 2.2 V/3 V
(DCO47)
A
× 1.7
× 2.1
V
V
= 2.2 V
= 3 V
4
4.4
4.5
4.9
4.9
5.4
CC
f
R
= 7, DCO = 7, MOD = 0, DCOR = 0, T = 25°C
MHz
(DCO77)
sel
A
CC
S
S
S
S
= f
/ f
V
= 2.2 V/3 V
= 2.2 V/3 V
1.35
1.07
−0.31
−0.33
1.65
1.12
−0.36
−0.38
2
Rsel
R
Rsel+1 Rsel
CC
CC
= f / f
(DCO+1) (DCO)
V
1.16
−0.40
−0.43
DCO
DCO
V
= 2.2 V
= 3 V
CC
CC
Temperature drift, R = 4, DCO = 3, MOD = 0
(see Note 2)
sel
D
D
%/°C
%/V
t
V
Drift with V variation, R = 4, DCO = 3, MOD = 0
(see Note 2)
CC
sel
V
CC
= 2.2 V/3 V
0
5
10
V
NOTES: 1. The DCO frequency may not exceed the maximum system frequency defined by parameter processor frequency, f
2. This parameter is not production tested.
.
(System)
1
DCOCLK
f
Max
DCO_7
f
Min
Max
f
DCO_0
Min
0
1
2
3
4
5
6
7
DCO
V
CC
− V
2.2
3
Figure 15. DCO Characteristics
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
main DCO characteristics
D
Individual devices have a minimum and maximum operation frequency. The specified parameters for
DCOx0) to f DCOx7) are valid for all devices.
f
(
(
D
D
D
All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7.
DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter SDCO
.
Modulation control bits MOD0 to MOD4 select how often f DCO+1) is used within the period of 32 DCOCLK
(
cycles. The frequency f(DCO) is used for the remaining cycles. The frequency is an average equal to:
32 f(DCO) f(DCO)1)
faverage
+
MOD f(DCO))(32*MOD) f(DCO)1)
DCO when using R
(see Note 1)
OSC
PARAMETER
TEST CONDITIONS
V
MIN
NOM
1.8±15%
1.95±15%
±0.1
MAX
UNIT
MHz
MHz
%/°C
%/V
CC
2.2 V
R
= 4, DCO = 3, MOD = 0, DCOR = 1,
sel
f
, DCO output frequency
DCO
T = 25°C
A
3 V
D , Temperature drift
R
R
= 4, DCO = 3, MOD = 0, DCOR = 1
= 4, DCO = 3, MOD = 0, DCOR = 1
2.2 V/3 V
2.2 V/3 V
t
sel
sel
D , Drift with V variation
10
v
CC
NOTES: 1. R
= 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and T = ±50ppm/°C.
K
OSC
crystal oscillator, LFXT1 oscillator (see Note 1)
PARAMETER
TEST CONDITIONS
XTS=0; LF oscillator selected, V = 2.2 V/3 V
MIN
NOM
12
2
MAX
UNIT
CC
C
C
Integrated input capacitance
pF
XIN
XTS=1; XT1 oscillator selected, V = 2.2 V/3 V
CC
XTS=0; LF oscillator selected, V = 2.2 V/3 V
12
2
CC
Integrated output capacitance
Input levels at XIN
pF
V
XOUT
XTS=1; XT1 oscillator selected, V = 2.2 V/3 V
CC
XTS = 0 or 1
V
V
V
0.2 × V
CC
IL
SS
V
= 2.2 V/3 V
XT1 or LF modes
XTS = 0, LF mode
XTS = 1, XT1 mode
CC
(see Note 2)
0.9 × V
0.8 × V
V
V
CC
CC
IH
CC
CC
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
crystal oscillator, XT2 oscillator (see Note 1)
PARAMETER
TEST CONDITIONS
= 2.2 V/3 V
MIN
NOM
MAX
UNIT
pF
pF
V
C
C
Integrated input capacitance
Integrated output capacitance
V
V
2
2
XIN
XOUT
IL
CC
= 2.2 V/3 V
CC
V
V
V
SS
0.2 × V
CC
Input levels at XIN
V
CC
= 2.2 V/3 V (see Note 2)
0.8 × V
V
CC
V
IH
CC
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
USART0, USART1 (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
200
150
NOM
430
MAX
800
UNIT
V
V
= 2.2 V
= 3 V
CC
t
τ
( )
USART0/USART1: deglitch time
ns
280
500
CC
NOTE 1: The signal applied to the USART0/USART1 receive signal/terminal (URXD0/1) should meet the timing requirements of t to ensure
(τ
)
that the URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t . The operating
(τ
)
conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative
transitions on the URXD0/1 line.
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, power supply and input range conditions (see Note 1)
PARAMETER
TEST CONDITIONS
AV and DV are connected together
MIN NOM
MAX
UNIT
CC
CC
AV
Analog supply voltage
AV and DV are connected together
2.2
3.6
V
CC
SS
SS
V
(AVSS)
= V
= 0 V
(DVSS)
All P6.0/A0 to P6.7/A7 terminals. Analog inputs
selected in ADC12MCTLx register and P6Sel.x=1
Analog input voltage
range (see Note 2)
V
0
V
AVCC
V
(P6.x/Ax)
0 ≤ x ≤ 7; V
≤ V
≤ V
(AVSS)
P6.x/Ax (AVCC)
Operating supply current
f
= 5.0 MHz
2.2 V
3 V
0.65
0.8
1.3
1.6
ADC12CLK
into AV terminal
ADC12ON = 1, REFON = 0
SHT0=0, SHT1=0, ADC12DIV=0
I
mA
mA
CC
ADC12
(see Note 3)
f
= 5.0 MHz
ADC12CLK
ADC12ON = 0,
REFON = 1, REF2_5V = 1
3 V
0.5
0.8
Operating supply current
I
into AV terminal
REF+
CC
f
= 5.0 MHz
2.2 V
3 V
0.5
0.5
0.8
0.8
ADC12CLK
(see Note 4)
ADC12ON = 0,
REFON = 1, REF2_5V = 0
mA
Only one terminal can be selected
at one time, P6.x/Ax
†
C
R
Input capacitance
2.2 V
3 V
40
pF
I
I
†
Input MUX ON resistance 0V ≤ V ≤ V
2000
Ω
Ax
AVCC
†
Not production tested, limits verified by design
NOTES: 1. The leakage current is defined in the leakage current table with P6.x/Ax parameter.
2. The analog input voltage range must be within the selected reference voltage range V to V for valid conversion results.
R+
R−
3. The internal reference supply current is not included in current consumption parameter I
.
ADC12
4. The internal reference current is supplied via terminal AV . Consumption is independent of the ADC12ON control bit, unless a
CC
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
12-bit ADC, external reference (see Note 1)
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
Positive external
reference voltage input
V
V
> V
> V
/V
(see Note 2)
(see Note 3)
(see Note 4)
1.4
V
V
eREF+
eREF+
REF− eREF−
AVCC
Negative external
reference voltage input
V
V
V
eREF+
/V
REF− eREF−
0
1.2
V
V
REF− / eREF−
(V
−
Differential external
reference voltage input
eREF+
V
eREF+
> V
/V
1.4
V
AVCC
REF− eREF−
V
V
)
REF−/ eREF−
I
I
Static input current
Static input current
0V ≤V
≤ V
2.2 V/3 V
2.2 V/3 V
±1
±1
µA
µA
VeREF+
eREF+
AVCC
0V ≤ V
≤ V
AVCC
VREF−/VeREF−
eREF−
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, C , is also
i
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, built-in reference
PARAMETER
TEST CONDITIONS
REF2_5V = 1 for 2.5 V
max ≤ I ≤ I
MIN NOM
MAX
UNIT
3 V
2.4
2.5
1.5
2.6
I
min
VREF+
VREF+ VREF+
Positive built-in reference
voltage output
V
REF+
V
REF2_5V = 0 for 1.5 V
max ≤ I ≤ I
2.2 V/3 V
1.44
1.56
I
min
VREF+
VREF+ VREF+
REF2_5V = 0, I
max ≤ I
≤ I min
2.2
2.8
VREF+
VREF+ VREF+
AV minimum voltage,
Positive built-in reference
active
CC
REF2_5V = 1, −0.5mA ≤ I
≤ I
min
AV
V
VREF+ VREF+
CC(min)
REF2_5V = 1, −1mA ≤ I
≤ I
min
2.9
VREF+ VREF+
2.2 V
3 V
0.01
0.01
−0.5
−1
Load current out of V
terminal
REF+
I
mA
VREF+
I
= 500 µA +/− 100 µA
2.2 V
3 V
±2
±2
VREF+
Analog input voltage ~0.75 V;
REF2_5V = 0
LSB
Load-current regulation
terminal
†
I
L(VREF)+
V
REF+
I
= 500 µA ± 100 µA
VREF+
Analog input voltage ~1.25 V;
REF2_5V = 1
3 V
3 V
±2
LSB
I
=100 µA → 900 µA,
=5 µF, ax ~0.5 x V
VREF+
Load current regulation
terminal
‡
C
I
20
ns
VREF+
REF+
DL(VREF) +
V
REF+
Error of conversion result ≤ 1 LSB
Capacitance at pin V
(see Note 1)
REFON =1,
REF+
C
2.2 V/3 V
2.2 V/3 V
5
10
µF
VREF+
0 mA ≤ I
≤ I
max
VREF+
VREF+
Temperature coefficient of
built-in reference
I
is a constant in the range of
VREF+
†
T
REF+
±100 ppm/°C
0 mA ≤ I
≤ 1 mA
VREF+
Settle time of internal
reference voltage (see
Figure 16 and Note 2)
I
V
= 0.5 mA, C
= 10 µF,
= 2.2 V
VREF+
VREF+
†
17
ms
t
REFON
= 1.5 V, V
REF+
AVCC
†
‡
Not production tested, limits characterized
Not production tested, limits verified by design
NOTES: 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses
two capacitors between pins V
and AV and V
/V
and AV : 10 µF tantalum and 100 nF ceramic.
REF+
SS
REF− eREF−
SS
2. The condition is that the error in a conversion started after t
capacitive load.
is less than ±0.5 LSB. The settling time depends on the external
REFON
C
VREF+
100 µF
t
≈ .66 x C
[ms] with C
in µF
REFON
VREF+
VREF+
10 µF
1 µF
0
10 ms
1 ms
100 ms
t
REFON
Figure 16. Typical Settling Time of Internal Reference t
vs External Capacitor on V
+
REF
REFON
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢓ
ꢀ
ꢋ
ꢌ
ꢍ
ꢎ
ꢁ
ꢋ
ꢏ
ꢐ
ꢑ
ꢒ
ꢀ
ꢋ
ꢔ
ꢕꢓ
ꢕꢐ
ꢖ
ꢔ
ꢕꢒ
ꢒꢍ
ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
DV
DV
From
Power
Supply
CC
+
−
SS
10 µF 100 nF
AV
CC
SS
+
−
MSP430F15x
MSP430F16x
MSP430F161x
AV
10 µF 100 nF
Apply External Reference [V
or Use Internal Reference [V
]
eREF+
V
REF+
or V
eREF+
]
REF+
+
−
10 µF 100 nF
Apply
External
Reference
V
REF
−/V
eREF−
+
−
10 µF 100 nF
Figure 17. Supply Voltage and Reference Voltage Design V
V
External Supply
REF−/ eREF−
DV
From
Power
Supply
CC
SS
+
−
DV
10 µF 100 nF
AV
CC
SS
+
−
MSP430F15x
MSP430F16x
AV
10 µF 100 nF
MSP430F161x
Apply External Reference [V
or Use Internal Reference [V
]
eREF+
V
REF+
or V
]
eREF+
REF+
+
−
10 µF 100 nF
Reference Is Internally
Switched to AV
V
/V
REF− eREF−
SS
Figure 18. Supply Voltage and Reference Voltage Design V
V
= AV , Internally Connected
REF−/ eREF− SS
40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, timing parameters
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
For specified performance of ADC12
linearity parameters
2.2V/
3 V
f
f
0.45
5
6.3
MHz
ADC12CLK
Internal ADC12
oscillator
ADC12DIV=0,
2.2 V/
3 V
3.7
5
6.3
MHz
µs
ADC12OSC
f
=f
ADC12CLK ADC12OSC
C
≥ 5 µF, Internal oscillator,
2.2 V/
3 V
VREF+
2.06
3.51
f
= 3.7 MHz to 6.3 MHz
ADC12OSC
t
Conversion time
CONVERT
External f
from ACLK, MCLK or SMCLK:
13×ADC12DIV×
ADC12CLK
µs
ADC12SSEL ≠ 0
1/f
ADC12CLK
Turn on settling time of
the ADC
‡
t
t
(see Note 1)
100
ns
ADC12ON
R
= 400 Ω, R = 1000 Ω,
I
3 V
1220
1400
S
‡
Sampling time
ns
C = 30 pF
Sample
I
2.2 V
τ = [R + R ] x C (see Note 2)
S
I
I;
†
‡
Not production tested, limits characterized
Not production tested, limits verified by design
NOTES: 1. The condition is that the error in a conversion started after t
settled.
is less than ±0.5 LSB. The reference and input signal are already
ADC12ON
2. Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
n+1
t
= ln(2 ) x (R + R ) x C + 800 ns where n = ADC resolution = 12, R = external source resistance.
Sample
S
I
I
S
12-bit ADC, linearity parameters
PARAMETER
TEST CONDITIONS
/V ) min ≤ 1.6 V
REF− eREF−
MIN NOM MAX
UNIT
1.4 V ≤ (V
− V
− V
±2
eREF+
E
E
Integral linearity error
2.2 V/3 V
2.2 V/3 V
LSB
I
1.6 V < (V
/V
) min ≤ [V
]
±1.7
eREF+
REF− eREF−
AVCC
Differential linearity
error
(V
C
− V
/V
)
≤ (V
− V /V
),
),
eREF+
VREF+
REF− eREF− min
eREF+
REF− eREF−
±1
LSB
LSB
D
= 10 µF (tantalum) and 100 nF (ceramic)
− V /V ≤ (V − V /V
REF− eREF−
(V
eREF+
)
REF− eREF− min
eREF+
E
O
Internal impedance of source R < 100 Ω,
2.2 V/3 V
±2
±4
Offset error
Gain error
S
C
= 10 µF (tantalum) and 100 nF (ceramic)
VREF+
(V
C
− V
/V
)
≤ (V
− V /V
),
),
eREF+
VREF+
REF− eREF− min
eREF+
REF− eREF−
E
E
2.2 V/3 V
2.2 V/3 V
±1.1
±2
±2
±5
LSB
LSB
G
= 10 µF (tantalum) and 100 nF (ceramic)
− V /V ≤ (V − V /V
REF− eREF−
(V
C
)
Total unadjusted
error
eREF+
REF− eREF− min
eREF+
T
= 10 µF (tantalum) and 100 nF (ceramic)
VREF+
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, temperature sensor and built-in V
MID
PARAMETER
TEST CONDITIONS
MIN
NOM
40
MAX
120
UNIT
2.2 V
3 V
Operating supply current into
REFON = 0, INCH = 0Ah,
I
µA
SENSOR
AV terminal (see Note 1)
ADC12ON=NA, T = 25_C
CC
A
60
986
986
3.55
3.55
160
2.2 V
3 V
ADC12ON = 1, INCH = 0Ah,
†
V
(see Note 2)
mV
SENSOR
T
A
= 0°C
2.2 V
3 V
3.55±3%
3.55±3%
†
TC
ADC12ON = 1, INCH = 0Ah
mV/°C
SENSOR
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1
LSB
2.2 V
3 V
30
30
Sample time required if channel
10 is selected (see Note 3)
†
t
µs
SENSOR(sample)
VMID
2.2 V
3 V
NA
NA
Current into divider at channel 11
(see Note 4)
I
ADC12ON = 1, INCH = 0Bh,
ADC12ON = 1, INCH = 0Bh,
µA
2.2 V
3 V
1.1
1.1±0.04
V
AV divider at channel 11
V
MID
CC
V
MID
is ~0.5 x V
AVCC
1.5 1.50±0.04
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1
LSB
2.2 V
3 V
1400
1220
Sample time required if channel
11 is selected (see Note 5)
t
ns
VMID(sample)
†
Not production tested, limits characterized
NOTES: 1. The sensor current I is consumed if (ADC12ON = 1 and REFON=1), or (ADC12ON=1 AND INCH=0Ah and sample signal
SENSOR
is high). When REFON = 1, I
is already included in I
.
SENSOR
REF+
2. The temperature sensor offset can be as much as ±20_C. A single-point calibration is recommended in order to minimize the offset
error of the built-in temperature sensor.
3. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t
SENSOR(on)
4. No additional current is needed. The V
is used during sampling.
MID
5. The on-time t
is included in the sampling time t ; no additional on time is needed.
VMID(sample)
VMID(on)
12-bit DAC, supply specifications
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
AV
DV
,
CC =
CC
AV
Analog supply voltage
2.20
3.60
V
CC
AV = DV =0 V
SS
SS
DAC12AMPx=2, DAC12IR=0,
DAC12_xDAT=0800h
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V
50
50
110
110
DAC12AMPx=2, DAC12IR=1,
Supply Current:
DAC12_xDAT=0800h
V
eREF+
=V
= AV
,
REF+
CC
CC
CC
Single DAC Channel
(see Notes 1 and 2)
I
µA
DD
DAC12AMPx=5, DAC12IR=1,
DAC12_xDAT=0800h, V
200
700
440
=V
REF+
= AV
= AV
eREF+
DAC12AMPx=7, DAC12IR=1,
1500
DAC12_xDAT=0800h, V
=V
REF+
eREF+
DAC12_xDAT = 800h, V
= 1.5 V
REF
REF
Power supply
∆AV = 100mV
CC
rejection ratio
PSRR
70
dB
DAC12_xDAT = 800h, V
= 1.5 V or 2.5 V
(see Notes 3 and 4)
3V
∆AV = 100mV
CC
NOTES: 1. No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
2. Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input
specifications.
3. PSRR = 20*log{∆AV /∆V
}.
CC
DAC12_xOUT
4.
V
REF
is applied externally. The internal reference is not used.
42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (see Figure 19)
PARAMETER
TEST CONDITIONS
(12-bit Monotonic)
= 1.5 V
V
MIN
TYP
MAX
UNIT
CC
Resolution
12
bits
V
ref
2.2V
3V
DAC12AMPx = 7, DAC12IR = 1
= 2.5 V
Integral nonlinearity
(see Note 1)
INL
±2.0
±8.0
LSB
LSB
V
ref
DAC12AMPx = 7, DAC12IR = 1
= 1.5 V
V
ref
2.2V
3V
DAC12AMPx = 7, DAC12IR = 1
= 2.5 V
Differential nonlinearity
(see Note 1)
DNL
±0.4
±1.0
±21
V
ref
DAC12AMPx = 7, DAC12IR = 1
= 1.5 V
V
ref
2.2V
3V
Offset voltage w/o
calibration
DAC12AMPx = 7, DAC12IR = 1
= 2.5 V
V
ref
(see Notes 1, 2)
E
O
DAC12AMPx = 7, DAC12IR = 1
= 1.5 V
mV
V
ref
2.2V
3V
Offset voltage with
calibration
DAC12AMPx = 7, DAC12IR = 1
= 2.5 V
±2.5
V
ref
(see Notes 1, 2)
DAC12AMPx = 7, DAC12IR = 1
Offset error
d
/d
/d
E(O)
T
temperature coefficient
(see Note 1)
2.2V/3V
30
10
uV/C
V
V
= 1.5 V
= 2.5 V
2.2V
3V
REF
E
Gain error (see Note 1)
±3.50 % FSR
G
REF
Gain temperature
ppm of
FSR/°C
d
E(G)
2.2V/3V
T
coefficient (see Note 1)
DAC12AMPx=2
2.2V/3V
2.2V/3V
2.2V/3V
100
Time for offset calibration
(see Note 3)
DAC12AMPx=3,5
DAC12AMPx=4,6,7
32
6
t
ms
Offset_Cal
NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and
“b” of the first order equation: y = a + b*x. V = E + (1 + E ) * (V /4095) * DAC12_xDAT, DAC12IR = 1.
DAC12_xOUT
O
G
eREF+
2. The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx
={0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may
effect accuracy and is not recommended.
DAC V
OUT
DAC Output
V
R+
R
=
Load
Ideal transfer
function
AV
CC
2
Offset Error
Positive
Gain Error
C
= 100pF
Load
Negative
DAC Code
Figure 19. Linearity Test Load Conditions and Gain/Offset Definition
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (continued)
TYPICAL INL ERROR
vs
DIGITAL INPUT DATA
4
V
CC
= 2.2 V, V
= 1.5V
REF
DAC12AMPx = 7
DAC12IR = 1
3
2
1
0
−1
−2
−3
−4
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT − Digital Code
TYPICAL DNL ERROR
vs
DIGITAL INPUT DATA
2.0
1.5
V
= 2.2 V, V
= 1.5V
CC
REF
DAC12AMPx = 7
DAC12IR = 1
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT − Digital Code
44
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, output specifications
PARAMETER
TEST CONDITIONS
No Load, Ve = AV
V
CC
MIN
TYP
MAX
UNIT
,
CC
REF+
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
2.2V/3V
2.2V/3V
2.2V/3V
0
0.005
V
No Load, Ve
= AV
,
REF+
CC
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
AV −0.05
AV
Output voltage
CC
CC
range
V
O
(see Note 1,
Figure 22)
R
= 3 kΩ, Ve
= AV
,
Load
REF+
CC
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
0
0.1
V
R
= 3 kΩ, Ve
= AV
,
Load
REF+
CC
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
2.2V/3V
2.2V/3V
AV −0.13
AV
V
CC
CC
Max DAC12
C
100
pF
L(DAC12)
load capacitance
2.2V
3V
−0.5
−1.0
+0.5
+1.0
mA
mA
Max DAC12
load current
I
L(DAC12)
R
= 3 kΩ
Load
V
= 0 V
O/P(DAC12)
2.2V/3V
150
250
DAC12AMPx = 7
DAC12_xDAT = 0h
R
V
= 3 kΩ
Output
Load
= AV
R
Ω
Resistance
(see Figure 22)
O/P(DAC12)
CC
O/P(DAC12)
2.2V/3V
2.2V/3V
150
1
250
4
DAC12AMPx = 7
DAC12_xDAT = 0FFFh
= 3 kΩ
R
Load
0.3 V < V
< AV − 0.3 V
CC
O/P(DAC12)
DAC12AMPx = 7
NOTES: 1. Data is valid after the offset calibration of the output amplifier.
R
O/P(DAC12_x)
Max
R
Load
I
Load
AV
CC
DAC12
2
C
= 100pF
O/P(DAC12_x)
Min
Load
0.3
AV
−0.3V
V
CC
OUT
AV
CC
Figure 22. DAC12_x Output Resistance Tests
45
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
12-bit DAC, reference input specifications
PARAMETER
Reference input
TEST CONDITIONS
DAC12IR=0, (see Notes 1 and 2)
DAC12IR=1, (see Notes 3 and 4)
DAC12_0 IR=DAC12_1 IR =0
DAC12_0 IR=1, DAC12_1 IR = 0
DAC12_0 IR=0, DAC12_1 IR = 1
V
MIN
TYP
MAX
UNIT
CC
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
AV /3 AV +0.2
CC
CC
Ve
V
REF+
voltage range
AVcc AVcc+0.2
20
40
MΩ
48
24
56
28
kΩ
kΩ
Ri
Ri
,
Reference input
resistance
(VREF+)
DAC12_0 IR=DAC12_1 IR =1
DAC12_0 SREFx = DAC12_1 SREFx
(see Note 5)
(VeREF+)
2.2V/3V
20
NOTES: 1. For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AV ).
CC
2. The maximum voltage applied at reference input voltage terminal Ve
= [AV − V
] / [3*(1 + E )].
E(O) G
REF+
CC
3. For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AV ).
CC
4. The maximum voltage applied at reference input voltage terminal Ve
= [AV − V
] / (1 + E ).
E(O) G
REF+
CC
5. When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
12-bit DAC, dynamic specifications; V = V , DAC12IR = 1 (see Figure 23 and Figure 24)
ref
CC
PARAMETER
TEST CONDITIONS
DAC12AMPx=0 → {2, 3, 4}
DAC12AMPx=0 → {5, 6}
DAC12AMPx=0 → 7
DAC12AMPx=2
V
MIN
TYP
60
15
6
MAX
120
30
UNIT
CC
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
DAC12_xDAT = 800h,
Error < ±0.5 LSB
DAC12 on-
time
t
t
t
µs
V(O)
ON
(see Note 1,Figure 23)
12
100
40
15
5
200
80
Settling
DAC12_xDAT =
DAC12AMPx=3,5
DAC12AMPx=4,6,7
DAC12AMPx=2
µs
µs
S(FS)
time,full-scale 80h→ F7Fh→ 80h
30
DAC12_xDAT =
Settling time,
DAC12AMPx=3,5
DAC12AMPx=4,6,7
DAC12AMPx=2
2
3F8h→ 408h→ 3F8h
code to code
S(C-C)
BF8h→ C08h→ BF8h
1
0.05
0.35
1.5
0.12
0.7
2.7
10
10
10
DAC12_xDAT =
DAC12AMPx=3,5
DAC12AMPx=4,6,7
DAC12AMPx=2
SR
Slew Rate
V/µs
nV-s
80h→ F7Fh→ 80h
DAC12_xDAT =
DAC12AMPx=3,5
DAC12AMPx=4,6,7
Glitch energy: full-scale
80h→ F7Fh→ 80h
NOTES: 1. R
and C connected to AV (not AV /2) in Figure 23.
Load SS CC
Load
2. Slew rate applies to output voltage steps >= 200mV.
Conversion 1
Conversion 2
Conversion 3
V
+/− 1/2 LSB
DAC Output
OUT
Glitch
Energy
R
= 3 kΩ
Load
I
Load
AV
CC
2
+/− 1/2 LSB
C
= 100pF
Load
R
O/P(DAC12.x)
t
t
settleHL
settleLH
Figure 23. Settling Time and Glitch Energy Testing
46
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
Conversion 1
Conversion 2
Conversion 3
V
OUT
90%
90%
10%
10%
t
t
SRHL
SRLH
Figure 24. Slew Rate Testing
12-bit DAC, dynamic specifications continued (T = 25°C unless otherwise noted)
A
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
2.2V/3V
2.2V/3V
2.2V/3V
40
3-dB bandwidth,
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
180
550
BW
kHz
V
DC
=1.5V, V =0.1V
AC PP
−3dB
(see Figure 25)
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
DAC12_0DAT = 800h, No Load,
DAC12_1DAT = 80h<−>F7Fh, R
= 3kΩ
2.2V/3V
2.2V/3V
−80
−80
Load
f
= 10kHz @ 50/50 duty cycle
DAC12_1OUT
dB
Channel to channel crosstalk
(see Note 1 and Figure 26)
DAC12_0DAT = 80h<−>F7Fh, R
= 3kΩ,
Load
DAC12_1DAT = 800h, No Load
f
= 10kHz @ 50/50 duty cycle
DAC12_0OUT
NOTES: 1. R
= 3 kΩ, C
= 100 pF
LOAD
LOAD
R
= 3 kΩ
Load
I
Load
Ve
REF+
AV
CC
DAC12_x
2
DACx
AC
DC
C
= 100pF
Load
Figure 25. Test Conditions for 3-dB Bandwidth Specification
R
Load
I
Load
AV
DAC12_xDAT 080h
7F7h
080h
7F7h
080h
CC
DAC12_0
2
DAC0
V
OUT
C
= 100pF
Load
V
V
V
DAC12_yOUT
DAC12_xOUT
REF+
R
Load
I
Load
AV
CC
DAC12_1
2
f
DAC1
Toggle
C
= 100pF
Load
Figure 26. Crosstalk Test Conditions
47
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
Flash Memory
TEST
CONDITIONS
PARAMETER
V
CC
MIN NOM
MAX
UNIT
V
CC(PGM/
ERASE)
Program and Erase supply voltage
Flash Timing Generator frequency
2.7
3.6
V
f
I
I
t
t
257
476
5
kHz
mA
FTG
Supply current from DV during program
2.7 V/ 3.6 V
2.7 V/ 3.6 V
2.7 V/ 3.6 V
2.7 V/ 3.6 V
3
PGM
CC
Supply current from DV during erase
3
7
mA
ERASE
CPT
CC
Cumulative program time
Cumulative mass erase time
Program/Erase endurance
Data retention duration
see Note 1
see Note 2
4
ms
200
ms
CMErase
4
5
10
100
10
cycles
years
t
T = 25°C
J
Retention
t
t
t
t
t
t
Word or byte program time
35
30
Word
st
Block program time for 1 byte or word
Block, 0
Block program time for each additional byte or word
Block program end-sequence wait time
Mass erase time
21
Block, 1-63
Block, End
Mass Erase
Seg Erase
see Note 3
t
FTG
6
5297
4819
Segment erase time
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/f
,max = 5297x1/476kHz). To
FTG
achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller’s state machine (t
= 1/f ).
FTG
FTG
JTAG Interface
TEST
CONDITIONS
PARAMETER
V
CC
MIN NOM
MAX
UNIT
2.2 V
3 V
0
0
5
10
90
MHz
MHz
kΩ
f
TCK input frequency
see Note 1
TCK
R
Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2
may be restricted to meet the timing requirements of the module selected.
2.2 V/ 3 V
25
60
Internal
NOTES: 1. f
TCK
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG Fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
V
CC
MIN NOM
MAX
UNIT
V
V
Supply voltage during fuse-blow condition
Voltage level on TDI/TCLK for fuse-blow: F versions
Supply current into TDI/TCLK during fuse blow
Time to blow fuse
T
A
= 25°C
2.5
6
V
V
CC(FB)
7
100
1
FB
I
FB
t
FB
mA
ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
48
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
APPLICATION INFORMATION
input/output schematic
port P1, P1.0 to P1.7, input/output with Schmitt-trigger
P1SEL.x
0
P1DIR.x
Direction Control
1
0
1
From Module
Pad Logic
P1.0/TACLK ...
P1.7/TA2
P1OUT.x
Module X OUT
P1IN.x
EN
D
Module X IN
P1IRQ.x
P1IE.x
Interrupt
Edge
Select
EN
Q
Set
P1IFG.x
Interrupt
Flag
P1IES.x
P1SEL.x
Dir. CONTROL
FROM MODULE
PnSel.x
PnDIR.x
PnOUT.x MODULE X OUT PnIN.x
MODULE X IN
PnIE.x PnIFG.x PnIES.x
†
P1Sel.0
P1Sel.1
P1Sel.2
P1Sel.3
P1Sel.4
P1Sel.5
P1Sel.6
P1Sel.7
P1DIR.0
P1DIR.1
P1DIR.2
P1DIR.3
P1DIR.4
P1DIR.5
P1DIR.6
P1DIR.7
P1DIR.0
P1DIR.1
P1DIR.2
P1DIR.3
P1DIR.4
P1DIR.5
P1DIR.6
P1DIR.7
P1OUT.0
P1OUT.1
P1OUT.2
P1OUT.3
P1OUT.4
P1OUT.5
P1OUT.6
P1OUT.7
DV
P1IN.0
P1IN.1
P1IN.2
P1IN.3
P1IN.4
P1IN.5
P1IN.6
P1IN.7
TACLK
P1IE.0 P1IFG.0 P1IES.0
P1IE.1 P1IFG.1 P1IES.1
P1IE.2 P1IFG.2 P1IES.2
P1IE.3 P1IFG.3 P1IES.3
P1IE.4 P1IFG.4 P1IES.4
P1IE.5 P1IFG.5 P1IES.5
P1IE.6 P1IFG.6 P1IES.6
P1IE.7 P1IFG.7 P1IES.7
SS
†
†
†
†
Out0 signal
Out1 signal
Out2 signal
SMCLK
CCI0A
†
CCI1A
†
CCI2A
unused
unused
unused
unused
†
†
†
Out0 signal
Out1 signal
Out2 signal
†
Signal from or to Timer_A
49
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.0 to P2.2, P2.6, and P2.7 input/output with Schmitt-trigger
P2SEL.x
0
0: Input
P2DIR.x
Direction Control
From Module
1: Output
1
0
1
P2OUT.x
Module X OUT
P2.0/ACLK
P2.1/TAINCLK
P2.2/CAOUT/TA0
P2.6/ADC12CLK/DMAE0
P2.7/TA0
Pad Logic
P2IN.x
EN
D
Bus Keeper
Module X IN
P2IRQ.x
P2IE.x
P2IFG.x
CAPD.X
EN
Interrupt
Edge
Select
Q
Set
Interrupt
Flag
P2IES.x
P2SEL.x
x: Bit Identifier 0 to 2, 6, and 7 for Port P2
Dir. CONTROL
PnSel.x
PnDIR.x
PnOUT.x MODULE X OUT PnIN.x
MODULE X IN
PnIE.x PnIFG.x PnIES.x
FROM MODULE
P2Sel.0
P2Sel.1
P2Sel.2
P2Sel.6
P2Sel.7
P2DIR.0
P2DIR.1
P2DIR.2
P2DIR.6
P2DIR.7
P2DIR.0
P2OUT.0
P2OUT.1
P2OUT.2
P2OUT.6
P2OUT.7
ACLK
DV
P2IN.0
P2IN.1
P2IN.2
P2IN.6
P2IN.7
unused
P2IE.0 P2IFG.0 P2IES.0
P2IE.1 P2IFG.1 P2IES.1
P2IE.2 P2IFG.2 P2IES.2
P2IE.6 P2IFG.6 P2IES.6
P2IE.7 P2IFG.7 P2IES.7
‡
P2DIR.1
INCLK
SS
†
‡
P2DIR.2
CAOUT
CCI0B
¶
#
P2DIR.6
ADC12CLK
DMAE0
§
P2DIR.7
Out0 signal
unused
†
‡
§
¶
#
Signal from Comparator_A
Signal to Timer_A
Signal from Timer_A
ADC12CLK signal is output of the 12-bit ADC module
Signal to DMA, channel 0, 1 and 2
50
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.3 to P2.4, input/output with Schmitt-trigger
P2SEL.3
0: Input
0
1: Output
P2DIR.3
Direction Control
1
From Module
Pad Logic
P2.3/CA0/TA1
0
P2OUT.3
Module X OUT
1
P2IN.3
EN
Bus Keeper
Module X IN
P2IRQ.3
D
P2IE.3
Interrupt
Edge
Select
EN
Set
CAPD.3
Q
P2IFG.3
Comparator_A
CAF
CAEX
P2CA
Interrupt
Flag
P2IES.3
P2SEL.3
CAREF
+
CCI1B
To Timer_A3
−
P2SEL.4
P2IES.4
Reference Block
CAREF
Interrupt
Flag
Edge
Select
Interrupt
P2IFG.4
Set
Q
EN
CAPD.4
P2IRQ.4
Module X IN
P2IE.4
D
Bus Keeper
EN
P2IN.4
1
Module X OUT
P2OUT.4
0
1
P2.4/CA1/TA2
Pad Logic
From Module
Direction Control
P2DIR.4
1: Output
0: Input
0
P2SEL.4
DIRECTION
CONTROL
PnSel.x
PnDIR.x
PnOUT.x MODULE X OUT PnIN.x
MODULE X IN
PnIE.x PnIFG.x PnIES.x
FROM MODULE
†
P2Sel.3
P2Sel.4
P2DIR.3
P2DIR.4
P2DIR.3
P2DIR.4
P2OUT.3
P2OUT.4
Out1 signal
Out2 signal
P2IN.3
P2IN.4
unused
unused
P2IE.3 P2IFG.3 P2IES.3
P2IE.4 P2IFG.4 P2IES.4
†
†
Signal from Timer_A
51
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.5, input/output with Schmitt-trigger and R
function for the basic clock module
osc
0: Input
1: Output
P2SEL.5
Pad Logic
0
1
0
1
P2DIR.5
Direction Control
From Module
P2.5/Rosc
P2OUT.5
Module X OUT
Bus Keeper
P2IN.5
EN
D
Internal to
Basic Clock
Module
Module X IN
P2IRQ.5
1
0
V
CC
Edge
Select
Interrupt
P2IE.5
EN
Q
Set
P2IFG.5
Interrupt
Flag
to
DC Generator
P2IES.5
P2SEL.5
DCOR
CAPD.5
DCOR: Control Bit From Basic Clock Module
If it Is Set, P2.5 Is Disconnected From P2.5 Pad
DIRECTION
PnSel.x
PnDIR.x
CONTROL
FROM MODULE
PnOUT.x MODULE X OUT PnIN.x
P2OUT.5 DV P2IN.5
MODULE X IN
PnIE.x PnIFG.x PnIES.x
P2Sel.5
P2DIR.5
P2DIR.5
unused
P2IE.5 P2IFG.5 P2IES.5
SS
52
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.0 and P3.4 to P3.7, input/output with Schmitt-trigger
P3SEL.x
0: Input
0
1
0
1
1: Output
P3DIR.x
Direction Control
From Module
Pad Logic
P3.0/STE0
P3OUT.x
Module X OUT
P3.4/UTXD0
P3.5/URXD0
‡
P3.6/UTXD1
¶
P3.7/URXD1
P3IN.x
EN
D
Module X IN
x: Bit Identifier, 0 and 4 to 7 for Port P3
DIRECTION
CONTROL
FROM MODULE
PnSel.x
PnDIR.x
PnOUT.x
MODULE X OUT
DV
PnIN.x
MODULE X IN
P3Sel.0
P3Sel.4
P3Sel.5
P3Sel.6
P3Sel.7
P3DIR.0
P3DIR.4
P3DIR.5
P3DIR.6
P3DIR.7
DV
DV
DV
DV
DV
P3OUT.0
P3OUT.4
P3OUT.5
P3OUT.6
P3OUT.7
P3IN.0
P3IN.4
P3IN.5
P3IN.6
P3IN.7
STE0
SS
CC
SS
CC
SS
SS
†
UTXD0
DV
Unused
§
URXD0
SS
‡
UTXD1
DV
Unused
¶
URXD1
SS
†
‡
‡
¶
Output from USART0 module
Output from USART1 module
Input to USART0 module
Input to USART1 module
53
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.1, input/output with Schmitt-trigger
P3SEL.1
P3DIR.1
0: Input
1: Output
0
1
0
1
SYNC
MM
DCM_SIMO
STC
STE
Pad Logic
P3.1/SIMO0/SDA
P3OUT1
(SI)MO0 or SDAo/p
From USART0
P3IN.1
EN
D
SI(MO)0 or SDAi/p
To USAET0
54
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.2, input/output with Schmitt-trigger
P3SEL.2
P3DIR.2
0: Input
1: Output
0
1
0
1
SYNC
MM
DCM_SOMI
Pad Logic
STC
STE
P3.2/SOMI0
P3OUT.2
SO(MI)0
From USART0
P3IN.2
EN
D
(SO)MI0
To USART0
port P3, P3.3, input/output with Schmitt-trigger
0: Input
1: Output
P3SEL.3
P3DIR.3
0
1
0
1
SYNC
MM
DCM_UCLK
STC
STE
Pad Logic
P3.3/UCLK0/SCL
P3OUT.3
UCLK.0
From USART0
P3IN.3
EN
D
UCLK0
To USART0
NOTE: UART mode:
The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always
an input.
SPI, slave mode:
The clock applied to UCLK0 is used to shift data in and out.
SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode).
2
I C, slave mode:
The clock applied to SCL is used to shift data in and out. The frequency of the clock source of the module must be
w 10 times the frequency of the SCL clock.
2
2
I C, master mode:
To shift data in and out, the clock is supplied via the SCL terminal to all I C slaves. The frequency of the clock source
of the module must be w 10 times the frequency of the SCL clock.
55
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
APPLICATION INFORMATION
input/output schematic (continued)
port P4, P4.0 to P4.6, input/output with Schmitt-trigger
Module IN of pin
P5.7/TBOUTH/SVSOUT
P4DIR.7
P4SEL.7
P4SEL.x
0: Input
1: Output
0
P4DIR.x
Direction Control
From Module
1
P4.0/TB0 ...
P4.6/TB6
0
1
P4OUT.x
Module X OUT
Bus
Keeper
P4IN.x
EN
D
Module X IN
x: Bit Identifier, 0 to 6 for Port P4
DIRECTION
PnSel.x
PnDIR.x
CONTROL
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
FROM MODULE
†
‡
P4Sel.0
P4Sel.1
P4DIR.0
P4DIR.1
P4DIR.0
P4DIR.1
P4OUT.0
P4OUT.1
Out0 signal
P4IN.0
P4IN.1
CCI0A / CCI0B
†
‡
Out1 signal
CCI1A / CCI1B
†
‡
P4Sel.2
P4Sel.3
P4Sel.4
P4Sel.5
P4Sel.6
P4DIR.2
P4DIR.3
P4DIR.4
P4DIR.5
P4DIR.6
P4DIR.2
P4DIR.3
P4DIR.4
P4DIR.5
P4DIR.6
P4OUT.2
P4OUT.3
P4OUT.4
P4OUT.5
P4OUT.6
Out2 signal
P4IN.2
P4IN.3
P4IN.4
P4IN.5
P4IN.6
CCI2A / CCI2B
†
‡
Out3 signal
CCI3A / CCI3B
†
‡
Out4 signal
CCI4A / CCI4B
†
‡
Out5 signal
CCI5A / CCI5B
†
Out6 signal
CCI6A
†
‡
Signal from Timer_B
Signal to Timer_B
56
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
APPLICATION INFORMATION
input/output schematic (continued)
port P4, P4.7, input/output with Schmitt-trigger
P4SEL.7
P4DIR.7
0: Input
1: Output
0
1
0
1
Pad Logic
P4.7/TBCLK
P4OUT.7
DV
SS
P4IN.7
EN
D
Timer_B,
TBCLK
port P5, P5.0 and P5.4 to P5.7, input/output with Schmitt-trigger
P5SEL.x
0: Input
0
1
0
1
1: Output
P5DIR.x
Direction Control
From Module
Pad Logic
P5.0/STE1
P5OUT.x
Module X OUT
P5.4/MCLK
P5.5/SMCLK
P5.6/ACLK
P5.7/TBOUTH/SVSOUT
P5IN.x
EN
D
Module X IN
x: Bit Identifier, 0 and 4 to 7 for Port P5
PnSel.x
P5Sel.0
P5Sel.4
P5Sel.5
P5Sel.6
P5Sel.7
PnDIR.x
P5DIR.0
P5DIR.4
P5DIR.5
P5DIR.6
P5DIR.7
Dir. CONTROL FROM MODULE
PnOUT.x
MODULE X OUT
DV
PnIN.x
P5IN.0
P5IN.4
P5IN.5
P5IN.6
P5IN.7
MODULE X IN
STE.1
DV
DV
DV
DV
DV
P5OUT.0
P5OUT.4
P5OUT.5
P5OUT.6
P5OUT.7
SS
CC
CC
CC
SS
SS
MCLK
SMCLK
ACLK
unused
unused
unused
SVSOUT
TBOUTHiZ
NOTE: TBOUTHiZ signal is used by port module P4, pins P4.0 to P4.6. The function of TBOUTHiZ is mainly useful when used with Timer_B7.
57
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
APPLICATION INFORMATION
input/output schematic (continued)
port P5, P5.1, input/output with Schmitt-trigger
P5SEL.1
P5DIR.1
0: Input
1: Output
0
1
0
1
SYNC
MM
DCM_SIMO
Pad Logic
STC
STE
P5.1/SIMO1
P5OUT.1
(SI)MO1
From USART1
P5IN.1
EN
D
SI(MO)1
To USART1
port P5, P5.2, input/output with Schmitt-trigger
P5SEL.2
P5DIR.2
0: Input
1: Output
0
1
0
1
SYNC
MM
DCM_SOMI
STC
STE
Pad Logic
P5.2/SOMI1
P5OUT.2
SO(MI)1
From USART1
P5IN.2
EN
D
(SO)MI1
To USART1
58
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
APPLICATION INFORMATION
input/output schematic (continued)
port P5, P5.3, input/output with Schmitt-trigger
P5SEL.3
P5DIR.3
0: Input
1: Output
0
1
0
1
SYNC
MM
DCM_SIMO
Pad Logic
STC
STE
P5.3/UCLK1
P5OUT.3
UCLK1
From USART1
P5IN.3
EN
D
UCLK1
To USART1
NOTE: UART mode:
The UART clock can only be an input. If UART mode and UART function are selected, the P5.3/UCLK1 direction
is always input.
SPI, slave mode:
The clock applied to UCLK1 is used to shift data in and out.
SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P5.3/UCLK1 (in slave mode).
59
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
APPLICATION INFORMATION
input/output schematic (continued)
port P6, P6.0 to P6.5, input/output with Schmitt-trigger
P6SEL.x
0
0: Input
P6DIR.x
Direction Control
From Module
1: Output
1
0
1
Pad Logic
P6OUT.x
Module X OUT
P6.0/A0
P6.1/A1
P6.2/A2
P6.3/A3
P6.4/A4
P6.5/A5
Bus Keeper
P6IN.x
EN
D
Module X IN
From ADC
To ADC
x: Bit Identifier, 0 to 5 for Port P6
NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if
the analog signal is in the range of transitions 0→1 or 1←0. The value of the throughput current depends on the driving capability of the
gate. For MSP430, it is approximately 100 µA.
Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used by the ADC12.
DIR. CONTROL
FROM MODULE
PnSel.x
PnDIR.x
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
P6Sel.0
P6Sel.1
P6Sel.2
P6Sel.3
P6Sel.4
P6Sel.5
P6DIR.0
P6DIR.1
P6DIR.2
P6DIR.3
P6DIR.4
P6DIR.5
P6DIR.0
P6OUT.0
P6OUT.1
P6OUT.2
P6OUT.3
P6OUT.4
P6OUT.5
DV
DV
DV
DV
DV
DV
P6IN.0
P6IN.1
P6IN.2
P6IN.3
P6IN.4
P6IN.5
unused
unused
unused
unused
unused
unused
SS
SS
SS
SS
SS
SS
P6DIR.1
P6DIR.2
P6DIR.3
P6DIR.4
P6DIR.5
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
60
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
APPLICATION INFORMATION
input/output schematic (continued)
port P6, P6.6, input/output with Schmitt-trigger
0: Port Active, T-Switch Off
1: T-Switch On, Port Disabled
†
INCH = 6
†
a6
’1’, if DAC12.0AMP > 0
Pad Logic
0: Input
P6SEL.6
0
1: Output
P6DIR.6
1
P6DIR.6
0
P6OUT.6
1
DVSS
Bus
Keeper
P6.6/A6/DAC0
P6IN.6
EN
D
0, if DAC12.0CALON = 0 and DAC12.0AMP > 1
1
+
0
−
1, if DAC12.0AMP >1
1, if DAC12.0AMP = 1
†
Signal from or to ADC12
61
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
APPLICATION INFORMATION
input/output schematic (continued)
port P6, P6.7, input/output with Schmitt-trigger
†
To SVS Mux (15)
0: Port Active, T-Switch Off
1: T-Switch On, Port Disabled
‡
INCH = 7
‡
a7
§
’1’, if VLD = 15
’1’, if DAC12.0AMP > 0
Pad Logic
P6SEL.6
0: Input
0
1: Output
P6DIR.7
1
P6DIR.7
0
P6OUT.7
1
DVSS
Bus
Keeper
P6.7/A7/
DAC1/SVSIN
P6IN.7
EN
D
0, if DAC12.0CALON = 0 and DAC12.0AMP > 1
1
+
0
−
1, if DAC12.0AMP > 1
1, if DAC12.0AMP = 1
†
‡
§
Signal to SVS Block, Selected if VLD = 15
Signal From or To ADC12
VLD Control Bits are Located in SVS
62
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢊ ꢆ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢊ ꢇꢆ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢏ ꢐꢑꢒ ꢀ ꢋꢓꢔꢕ ꢓꢕ ꢐꢖ ꢔꢕ ꢒꢒ ꢍꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
APPLICATION INFORMATION
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger
TDO
Controlled by JTAG
Controlled by JTAG
JTAG
TDO/TDI
Controlled
by JTAG
DV
DV
CC
CC
TDI
Fuse
Burn & Test
Fuse
Test
and
TDI/TCLK
DV
CC
Emulation
Module
TMS
TCK
TMS
TCK
DV
CC
During Programming Activity and
During Blowing of the Fuse, Pin
TDO/TDI Is Used to Apply the Test
Input Data for JTAG Circuitry
63
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢆꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢊ ꢇ ꢆ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢏꢐ ꢑ ꢒ ꢀꢋ ꢓ ꢔꢕꢓ ꢕꢐ ꢖꢔ ꢕꢒ ꢒꢍ ꢔ
SLAS368D− OCTOBER 2002− REVISED MARCH 2005
APPLICATION INFORMATION
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, I , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/TCLK pin to ground if the fuse is not burned.
TF
Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see
Figure 27). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
I
TF
I
TDI/TCLK
Figure 27. Fuse Check Mode Current, MSP430x15x/16x/161x
64
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jul-2005
PACKAGING INFORMATION
Orderable Device
MSP430F155IPM
MSP430F155IPMR
MSP430F156IPM
MSP430F156IPMR
MSP430F157IPM
MSP430F157IPMR
MSP430F1610IPM
MSP430F1610IPMR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
LQFP
PM
64
64
64
64
64
64
64
64
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
PM
PM
PM
PM
PM
PM
PM
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
MSP430F1610IRTD
MSP430F1610IRTDR
ACTIVE
ACTIVE
QFN
QFN
RTD
RTD
64
64
TBD
Call TI
Call TI
2500 Green (RoHS &
no Sb/Br)
Level-2-260C-1 YEAR
MSP430F1610IRTDT
MSP430F1611IPM
MSP430F1611IPMR
ACTIVE
ACTIVE
ACTIVE
QFN
LQFP
LQFP
RTD
PM
64
64
64
250 Green (RoHS &
no Sb/Br)
Level-2-260C-1 YEAR
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
PM
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
MSP430F1611IRTD
MSP430F1611IRTDR
ACTIVE
ACTIVE
QFN
QFN
RTD
RTD
64
64
TBD
Call TI
Call TI
2500 Green (RoHS &
no Sb/Br)
Level-2-260C-1 YEAR
MSP430F1611IRTDT
MSP430F1612IPM
MSP430F1612IPMR
ACTIVE
ACTIVE
ACTIVE
QFN
LQFP
LQFP
RTD
PM
64
64
64
250 Green (RoHS &
no Sb/Br)
Level-2-260C-1 YEAR
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
PM
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
MSP430F1612IRTD
MSP430F1612IRTDR
ACTIVE
ACTIVE
QFN
QFN
RTD
RTD
64
64
TBD
Call TI
Call TI
2500 Green (RoHS &
no Sb/Br)
Level-2-260C-1 YEAR
MSP430F1612IRTDT
MSP430F167IPM
MSP430F167IPMR
MSP430F168IPM
MSP430F168IPMR
MSP430F169IPM
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
QFN
LQFP
LQFP
LQFP
LQFP
LQFP
RTD
PM
PM
PM
PM
PM
64
64
64
64
64
64
250 Green (RoHS &
no Sb/Br)
Level-2-260C-1 YEAR
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jul-2005
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
MSP430F169IPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
0°–7°
11,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040152/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
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www.ti.com/automotive
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dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
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