MSP430F2101IDWR [TI]
MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器
| 型号： | MSP430F2101IDWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MIXED SIGNAL MICROCONTROLLER |
| 文件： | 总53页 (文件大小：1140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
D
D
Low Supply Voltage Range 1.8 V to 3.6 V
D
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by
Security Fuse
Ultralow-Power Consumption
− Active Mode: 250 µA at 1 MHz, 2.2 V
− Standby Mode: 0.7 µA
− Off Mode (RAM Retention): 0.1 µA
Ultrafast Wake-Up From Standby Mode in
less than 1 µs
16-Bit RISC Architecture, 62.5 ns
Instruction Cycle Time
D
D
D
Bootstrap Loader
D
D
D
On Chip Emulation Module
Family Members Include:
MSP430F2101: 1KB + 256B Flash Memory
128B RAM
MSP430F2111: 2KB + 256B Flash Memory
128B RAM
MSP430F2121: 4KB + 256B Flash Memory
256B RAM
Basic Clock Module Configurations:
− Internal Frequencies up to 16MHz with
4 calibrated Frequencies to 1%
− 32-kHz Crystal
− High-Frequency Crystal up to 16MHz
− Resonator
MSP430F2131: 8KB + 256B Flash Memory
256B RAM
D
D
Available in a 20-Pin Plastic Small-Outline
Wide Body (SOWB) Package, 20-Pin Plastic
Small-Outline Thin (TSSOP) Package,
20-Pin TVSOP and 24-Pin QFN
For Complete Module Descriptions, Refer
to the MSP430x2xx Family User’s Guide
− External Digital Clock Source
D
D
16-Bit Timer_A With Three
Capture/Compare Registers
On-Chip Comparator for Analog Signal
Compare Function or Slope A/D
Conversion
D
Brownout Detector
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1µs.
The MSP430x21x1 series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer, versatile
analog comparator and sixteen I/O pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data for display or for transmission to a host system. Stand alone RF sensor front end is another
area of application. The analog comparator provides slope A/D conversion capability.
AVAILABLE OPTIONS
PACKAGED DEVICES
PLASTIC
20-PIN SOWB
(DW)
PLASTIC
20-PIN TSSOP
(PW)
PLASTIC
20-PIN TVSOP
(DGV)
PLASTIC
24-PIN QFN
(RGE)
T
A
MSP430F2101IDW
MSP430F2111IDW
MSP430F2121IDW
MSP430F2131IDW
MSP430F2101IPW
MSP430F2111IPW
MSP430F2121IPW
MSP430F2131IPW
MSP430F2101IDGV
MSP430F2111IDGV
MSP430F2121IDGV
MSP430F2131IDGV
MSP430F2101IRGE
MSP430F2111IRGE
MSP430F2121IRGE
MSP430F2131IRGE
−40°C to 85°C
−40°C to 105°C
MSP430F2101TDW
MSP430F2111TDW
MSP430F2121TDW
MSP430F2131TDW
MSP430F2101TPW
MSP430F2111TPW
MSP430F2121TPW
MSP430F2131TPW
MSP430F2101TDGV
MSP430F2111TDGV
MSP430F2121TDGV
MSP430F2131TDGV
MSP430F2101TRGE
MSP430F2111TRGE
MSP430F2121TRGE
MSP430F2131TRGE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004 − 2006 Texas Instruments Incorporated
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1
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
device pinout
RGE PACKAGE
(TOP VIEW)
DW, PW, or DGV PACKAGE
(TOP VIEW)
TEST
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI/TCLK
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
P2.5/CA5
V
SS
XOUT/P2.7/CA7
XIN/P2.6/CA6
P1.2/TA1
RST/NMI
P1.1/TA0
24 23 22 21 20 19
NC
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
1
2
3
4
5
6
18
17
16
15
14
13
P2.0/ACLK/CA2
P2.1/INCLK/CA3
P2.2/CAOUT/TA0/CA4
P1.0/TACLK
V
SS
P2.4/TA2/CA1
P2.3/TA1/CA0
XOUT/P2.7/CA7
XIN/P2.6/CA6
RST/NMI
P1.2/TA1
P1.1/TA0
P2.0/ACLK/CA2
P1.0/TACLK
7 8 9 10 11 12
Note: NC pins not internally connected
Power Pad connection to V
recommended
SS
functional block diagram
P2.x &
XIN/XOUT
8
VCC
VSS
P1.x & JTAG
8
XIN
XOUT
Port P1
Port P2
ACLK
Flash
RAM
Comparator
_A+
Basic Clock
System+
8 I/O
Interrupt
capability,
pull−up/down pull−up/down
resistors
8 I/O
Interrupt
capability,
8kB
4kB
2kB
1kB
256B
256B
128B
128B
SMCLK
8 Channel
Input Mux
MCLK
resistors
MAB
16MHz
CPU
incl. 16
Registers
MDB
Emulation
(2BP)
Watchdog
WDT+
Timer_A3
JTAG
Interface
Brownout
Protection
3 CC
15/16−Bit
Registers
RST/NMI
NOTE: See port schematics section for detailed I/O information.
2
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
Terminal Functions
TERMINAL
DW, PW, or DGV
RGE
NO.
13
DESCRIPTION
NAME
I/O
NO.
P1.0/TACLK
13
I/O General-purpose digital I/O pin
Timer_A, clock signal TACLK input
P1.1/TA0
14
15
16
17
18
19
20
8
14
15
16
17
18
20
21
6
I/O General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit
P1.2/TA1
I/O General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2
I/O General-purpose digital I/O pin
Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK/TCK
P1.5/TA0/TMS
P1.6/TA1/TDI/TCLK
I/O General-purpose digital I/O pin / SMCLK signal output
Test Clock input for device programming and test
I/O General-purpose digital I/O pin / Timer_A, compare: Out0 output
Test Mode Select input for device programming and test
I/O General-purpose digital I/O pin / Timer_A, compare: Out1 output
Test Data Input or Test Clock Input for programming and test
†
P1.7/TA2/TDO/TDI
P2.0/ACLK/CA2
P2.1/INCLK/CA3
I/O General-purpose digital I/O pin / Timer_A, compare: Out2 output
Test Data Output or Test Data Input for programming and test
I/O General-purpose digital I/O pin / ACLK output
Comparator_A+, CA2 input
9
7
I/O General-purpose digital I/O pin / Timer_A, clock signal at INCLK
Comparator_A+, CA3 input
P2.2/CAOUT/
TA0/CA4
10
8
I/O General-purpose digital I/O pin
Timer_A, capture: CCI0B input/BSL receive
Comparator_A+, output / CA4 input
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/CA5
11
12
3
10
11
24
4
I/O General-purpose digital I/O pin / Timer_A, compare: Out1 output
Comparator_A+, CA0 input
I/O General-purpose digital I/O pin / Timer_A, compare: Out2 output
Comparator_A+, CA1 input
I/O General-purpose digital I/O pin
Comparator_A+, CA5 input
XIN/P2.6/CA6
6
I/O Input terminal of crystal oscillator
General-purpose digital I/O pin
Comparator_A+, CA6 input
XOUT/P2.7/CA7
5
3
I/O Output terminal of crystal oscillator
general-purpose digital I/O pin
Comparator_A+, CA7 input
RST/NMI
TEST
7
1
5
I
I
Reset or nonmaskable interrupt input
22
Selects test mode for JTAG pins on Port1. The device protection fuse
is connected to TEST.
V
V
2
4
23
Supply voltage
CC
2
Ground reference
SS
QFN Pad
NA
Package Pad
NA QFN package pad connection to V recommended.
SS
†
TDO or TDI is selected via JTAG instruction.
NOTE: If XOUT/P2.7/CA7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver
connection to this pad after reset.
3
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
short-form description
CPU
Program Counter
Stack Pointer
PC/R0
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
R4
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
R5
R6
R7
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
R8
R9
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
R10
R11
instruction set
R12
R13
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
R14
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
e.g. ADD R4,R5
R4 + R5 −−−> R5
e.g. CALL
e.g. JNE
R8
PC −−>(TOS), R8−−> PC
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
Register
S
D
SYNTAX
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
OPERATION
F
F
F
F
F
F
F
F
F
MOV Rs,Rd
R10 −−> R11
Indexed
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV &MEM,&TCDAT
MOV @Rn,Y(Rm)
M(2+R5)−−> M(6+R6)
M(EDE) −−> M(TONI)
M(MEM) −−> M(TCDAT)
M(R10) −−> M(Tab+R6)
Symbolic (PC relative)
Absolute
Indirect
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
Indirect
autoincrement
M(R10) −−> R11
R10 + 2−−> R10
F
F
MOV @Rn+,Rm
Immediate
MOV #X,TONI
#45 −−> M(TONI)
NOTE: S = source
D = destination
4
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D
D
Active mode AM;
All clocks are active
Low-power mode 0 (LPM0);
−
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
D
D
Low-power mode 1 (LPM1);
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCO’s dc-generator is disabled if DCO not used in active mode
Low-power mode 2 (LPM2);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D
D
Low-power mode 3 (LPM3);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
Low-power mode 4 (LPM4);
−
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
5
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh−0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g. flash is not programmed) the CPU will
go into LPM4 immediately after power−up.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog
PORIFG
RSTIFG
WDTIFG
KEYV
Reset
0FFFEh
31, highest
Flash key violation
PC out-of-range (see Note 1)
(see Note 2)
NMIIFG
OFIFG
ACCVIFG
NMI
Oscillator fault
Flash memory access violation
(non)-maskable,
(non)-maskable,
(non)-maskable
0FFFCh
30
(see Notes 2 & 4)
0FFFAh
0FFF8h
0FFF6h
0FFF4h
0FFF2h
29
28
27
26
25
Comparator_A+
Watchdog Timer+
Timer_A2
CAIFG
WDTIFG
maskable
maskable
maskable
TACCR0 CCIFG (see Note 3)
TACCR1 CCIFG,
TAIFG (see Notes 2 & 3)
Timer_A2
maskable
0FFF0h
24
0FFEEh
0FFECh
0FFEAh
0FFE8h
23
22
21
20
I/O Port P2
(eight flags)
P2IFG.0 to P2IFG.7
(see Notes 2 & 3)
maskable
maskable
0FFE6h
0FFE4h
19
18
I/O Port P1
(eight flags)
P1IFG.0 to P1IFG.7
(see Notes 2 & 3)
0FFE2h
0FFE0h
17
16
(see Note 5)
(see Note 6)
0FFDEh
15
0FFDCh ... 0FFC0h
14 ... 0, lowest
NOTES: 1. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh).
2. Multiple source flags
3. Interrupt flags are located in the module
4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
5. This location is used as bootstrap loader security key (BSLSKEY).
A value of 0AA55h at this location disables the BSL completely.
A value of 0h disables the erasure of the flash if an invalid password is supplied.
6. The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
6
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
interrupt enable 1 and 2
7
6
5
4
3
2
1
0
Address
0h
OFIE
WDTIE
ACCVIE
NMIIE
rw-0
rw-0
rw-0
rw-0
WDTIE:
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer
is configured in interval timer mode.
OFIE:
Oscillator fault enable
NMIIE:
ACCVIE:
(Non)maskable interrupt enable
Flash access violation interrupt enable
7
6
5
4
3
2
1
0
Address
01h
interrupt flag register 1 and 2
7
6
5
4
3
2
1
0
Address
02h
NMIIFG
RSTIFG
PORIFG
OFIFG
WDTIFG
rw-0
rw-(0)
rw-1
rw-(0)
rw-(1)
WDTIFG:
Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on V power-up or a reset condition at RST/NMI pin in reset mode.
Flag set on oscillator fault
CC
OFIFG:
RSTIFG:
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on V
power−up
CC
PORIFG:
NMIIFG:
Power−On Reset interrupt flag. Set on V
Set via RST/NMI-pin
power−up.
CC
7
6
5
4
3
2
1
0
Address
03h
Legend
rw:
Bit can be read and written.
rw-0,1:
rw-(0,1):
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device
7
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
memory organization
MSP430F2101
MSP430F2111
MSP430F2121
MSP430F2131
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
1KB Flash
0FFFFh−0FFE0h
0FFFFh−0FC00h
2KB Flash
0FFFFh−0FFE0h
0FFFFh−0F800h
4KB Flash
0FFFFh−0FFE0h
0FFFFh−0F000h
8KB Flash
0FFFFh−0FFE0h
0FFFFh−0E000h
Information memory
Boot memory
RAM
Size
Flash
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Size
ROM
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
Size
128 Byte
128 Byte
256 Byte
256 Byte
027Fh − 0200h
027Fh − 0200h
02FFh − 0200h
02FFh − 0200h
Peripherals
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. A bootstrap loader
security key is provided at address 0FFDEh to disable the BSL completely or to disable the erasure of the flash
if an invalid password is supplied. For complete description of the features of the BSL and its implementation,
see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089.
BSLKEY
00000h
Description
Erasure of flash disabled if an invalid password is supplied
BSL disabled
0AA55h
any other value
BSL enabled
BSL Function
Data Transmit
Data Receive
DW, PW & DGV Package Pins
14 - P1.1
RGE Package Pins
14 - P1.1
8 - P2.2
10 - P2.2
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D
Flash memory has n segments of main memory and four segments of information memory (A to D) of 64
bytes each. Each segment in main memory is 512 bytes in size.
D
D
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually, or as a group with segments 0−n.
Segments A to D are also called information memory.
D
Segment A contains calibration data. After reset segment A is protected against programming or erasing.
It can be unlocked but care should be taken not to erase this segment if the calibration data is required.
8
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x2xx Family User’s Guide.
oscillator and system clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock
module is designed to meet the requirements of both low system cost and low-power consumption. The internal
DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic clock module provides the
following clock signals:
D
D
D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
DCO Calibration Data (provided from factory in flash info memory segment A)
DCO Frequency
Calibration Register
CALBC1_1MHZ
CALDCO_1MHZ
CALBC1_8MHZ
CALDCO_8MHZ
CALBC1_12MHZ
CALDCO_12MHZ
CALBC1_16MHZ
CALDCO_16MHZ
Size
byte
byte
byte
byte
byte
byte
byte
byte
Address
010FFh
010FEh
010FDh
010FCh
010FBh
010FAh
010F9h
010F8h
1 MHz
8 MHz
12 MHz
16 MHz
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off.
digital I/O
There are two 8-bit I/O ports implemented—ports P1 and P2:
D
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of port P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Each I/O has an individually programmable pull−up/pull−down resistor.
WDT+ watchdog timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
9
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
comparator_A+
The primary function of the Comparator_A+ module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input
Pin Number
Device
Input Signal
Module
Input Name
Module
Block
Module
Output Signal
Output
Pin Number
DW, PW, DGV
RGE
DW, PW, DGV
RGE
13 - P1.0
13 - P1.0
TACLK
ACLK
SMCLK
INCLK
TA0
TACLK
ACLK
Timer
CCR0
CCR1
CCR2
NA
TA0
TA1
TA2
SMCLK
INCLK
CCI0A
CCI0B
GND
9 - P2.1
14 - P1.1
10 - P2.2
7 - P2.1
14 - P1.1
8 - P2.2
14 - P1.1
18 - P1.5
14 - P1.1
18 - P1.5
TA0
V
SS
V
V
CC
CC
15 - P1.2
16 - P1.3
15 - P1.2
16 - P1.3
TA1
CCI1A
CCI1B
GND
11 - P2.3
15 - P1.2
19 - P1.6
10 - P2.3
15 - P1.2
20 - P1.6
CAOUT (internal)
V
SS
V
CC
V
CC
TA2
CCI2A
CCI2B
GND
12 - P2.4
16 - P1.3
20 - P1.7
11 - P2.4
16 - P1.3
21 - P1.7
ACLK (internal)
V
SS
V
CC
V
CC
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
peripheral file map
PERIPHERALS WITH WORD ACCESS
Timer_A
Capture/compare register
Capture/compare register
Capture/compare register
Timer_A register
Capture/compare control
Capture/compare control
Capture/compare control
Timer_A control
TACCR2
TACCR1
TACCR0
TAR
TACCTL2
TACCTL1
TACCTL0
TACTL
0176h
0174h
0172h
0170h
0166h
0164h
0162h
0160h
012Eh
Timer_A interrupt vector
TAIV
Flash Memory
Flash control 3
Flash control 2
Flash control 1
FCTL3
FCTL2
FCTL1
012Ch
012Ah
0128h
Watchdog TImer+
Comparator_A+
Watchdog/timer control
WDTCTL
0120h
PERIPHERALS WITH BYTE ACCESS
Comparator_A+ port disable
Comparator_A+ control 2
Comparator_A+ control 1
CAPD
CACTL2
CACTL1
05Bh
05Ah
059h
Basic Clock
Port P2
Basic clock system control 3
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
053h
058h
057h
056h
Port P2 resistor enable
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
P2REN
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
02Fh
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P2 output
Port P2 input
Port P1
Port P1 resistor enable
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
P1REN
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
027h
026h
025h
024h
023h
022h
021h
020h
Port P1 output
Port P1 input
Special Function
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
IFG2
IFG1
IE2
003h
002h
001h
000h
IE1
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
absolute maximum ratings (see Note 1)
Voltage applied at V
to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
CC
SS
Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V +0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA
CC
Storage temperature, T (unprogrammed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
stg
Storage temperature, T (programmed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
stg
NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. All voltages referenced to V . The JTAG fuse-blow voltage, V , is allowed to exceed the absolute maximum rating. The voltage
SS
FB
is applied to the TEST pin when blowing the JTAG fuse.
3. Higher temperature may be applied during board soldering process according to the current JEDEC J−STD−020 specification with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
recommended operating conditions
MIN NOM
MAX UNIT
Supply voltage during program execution, V
CC
1.8
2.2
0
3.6
3.6
V
V
Supply voltage during program/erase flash memory, V
CC
Supply voltage, V
SS
V
I Version
T Version
−40
−40
0
85
105
6
°C
°C
Operating free-air temperature range, T
A
V
= 1.8 V, Duty Cycle = 50% 10%
CC
CC
V
= 2.7 V, Duty Cycle = 50% 10%
Processor frequency f
SYSTEM
0
0
12
16
(see Note 3)
MHz
(Maximum MCLK frequency)
(see Notes 1, 2 and Figure 1)
V
= 3.3 V, Duty Cycle = 50% 10%
CC
(see Note 4)
NOTES: 1. The MSP430 CPU is clocked directly with MCLK.
Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.
2. Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this
datasheet.
3. This includes using the provided DCO calibration value for 12 MHz for V
4. This includes using the provided DCO calibration value for 16 MHz for V
= 2.7 V to 3.6 V over the operating temperature range.
= 3.3 V to 3.6 V over the operating temperature range.
CC
CC
Legend:
16 MHz
12 MHz
Supply voltage range,
during flash memory
programming
Supply voltage range,
during program execution
6 MHz
1.8 V
2.2 V
2.7 V
3.3 V 3.6 V
Supply Voltage −V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V
of 2.2 V.
CC
Figure 1. Operating Area
12
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
active mode supply current (into V ) excluding external current (see Notes 1 and 2)
CC
PARAMETER
TEST CONDITIONS
T
A
VCC
MIN
TYP
MAX UNIT
f
= f
= f
= 1MHz,
DCO MCLK SMCLK
f = 32,768Hz,
ACLK
2.2 V
250
300
µA
Program executes in flash,
Active mode (AM)
current (1MHz)
I
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
AM,1MHz
AM,1MHz
3 V
2.2 V
3 V
350
200
410
f
= f
= f
= 1MHz,
DCO MCLK SMCLK
f = 32,768Hz,
ACLK
Program executes in RAM,
Active mode (AM)
current (1MHz)
I
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
µA
300
2
f
f
f
= f =
= 32,768Hz/8 = 4,096Hz,
= 0Hz,
MCLK SMCLK
ACLK
DCO
-40−85°C
105°C
2.2 V
2.2 V
3 V
5
6
Active mode (AM) Program executes in flash,
I
I
µA
9
AM,4kHz
current (4kHz)
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCG0 = 1, SCG1 = 0,
OSCOFF = 0
-40−85°C
105°C
3
3 V
9
f
= f ≈ 100kHz,
= 0Hz,
= f
MCLK SMCLK DCO(0,0)
2.2 V
3 V
60
72
85
µA
95
f
ACLK
Program executes in flash,
RSELx = 0, DCOx = 0,
Active mode (AM)
current (100kHz)
AM,100kHz
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 1
NOTES: 1. All inputs are tied to 0 V or V . Outputs do not source or sink any current.
CC
2. The currents are characterized with a Micro Crystal CC4V−T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9pF.
13
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
typical characteristics − active mode supply current (into V
)
CC
7.0
5.0
f
f
= 16 MHz
DCO
6.0
5.0
4.0
3.0
2.0
1.0
0.0
4.0
3.0
2.0
1.0
0.0
T
= 85 °C
= 25 °C
A
= 12 MHz
= 8 MHz
DCO
f
T
A
V
= 3 V
DCO
CC
T
= 85 °C
= 25 °C
A
T
A
V
CC
= 2.2 V
f
= 1 MHz
DCO
1.5
2.0
2.5
3.0
3.5
4.0
0.0
4.0
8.0
12.0
16.0
V
CC
− Supply Voltage − V
f
DCO
− DCO Frequency − MHz
Figure 2. Active mode current vs V , T = 25°C
Figure 3. Active mode current vs DCO frequency
CC
A
14
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
low power mode supply currents (into V ) excluding external current (see Notes 1 and 2)
CC
PARAMETER
TEST CONDITIONS
T
A
VCC
MIN
TYP
MAX UNIT
f
f
f
= 0MHz,
MCLK
= f
= 1MHz,
= 32,768Hz,
2.2 V
65
80
SMCLK DCO
Low-power mode
ACLK
I
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
µA
0 (LPM0) current,
see Note 3
LPM0,1MHz
3 V
85
37
100
f
f
f
= 0MHz,
MCLK
2.2 V
3 V
48
µA
52
= f
SMCLK DCO(0, 0)
≈ 100kHz,
Low-power mode
0 (LPM0) current,
see Note 3
= 0Hz,
ACLK
I
LPM0,100kHz
RSELx = 0, DCOx = 0,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 1
41
22
f
= f
MCLK SMCLK
= 0MHz, f = 1MHz,
DCO
-40−85°C
105°C
29
2.2 V
3 V
f
= 32,768Hz,
ACLK
Low-power mode
2 (LPM2) current,
see Note 4
31
µA
32
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
I
LPM2
-40−85°C
25
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
105°C
-40°C
25°C
34
0.7
0.7
1.6
3
1.2
1.0
µA
2.3
2.2 V
3 V
85°C
Low-power mode
3 (LPM3) current,
see Note 4
f
= f = 0MHz,
= f
= 32,768Hz,
DCO MCLK SMCLK
105°C
-40°C
25°C
6
f
ACLK
I
LPM3,LFXT1
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
0.9
0.9
1.6
3
1.2
1.2
µA
2.8
85°C
105°C
-40°C
25°C
7
0.5
0.5
0.1
0.1
0.8
2
f
= f = 0MHz,
= 0Hz,
= f
DCO MCLK SMCLK
Low-power mode
4 (LPM4) current,
see Note 5
f
ACLK
I
LPM4
2.2 V/3 V
µA
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
85°C
1.9
105°C
4
NOTES: 1. All inputs are tied to 0 V or V . Outputs do not source or sink any current.
CC
2. The currents are characterized with a Micro Crystal CC4V−T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9pF.
3. Current for brownout and WDT clocked by SMCLK included.
4. Current for brownout and WDT clocked by ACLK included.
5. Current for brownout included.
15
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs − Ports P1 and P2
PARAMETER
TEST CONDITIONS
VCC
MIN
0.45
1.00
1.35
0.25
0.55
0.75
0.2
TYP
MAX UNIT
0.75
1.65
2.25
0.55
1.20
1.65
1.0
V
CC
V
Positive-going input threshold
voltage
2.2 V
3 V
V
IT+
V
CC
V
Negative-going input threshold
voltage
2.2 V
3 V
V
V
IT−
2.2 V
3 V
Input voltage hysteresis (V
IT+
−
V
hys
V
)
0.3
1.0
IT−
For pull−up: V = V
For pull−down: V = V
IN
;
IN SS
R
C
Pull−up/pull−down resistor
Input Capacitance
20
35
50
kW
Pull
I
CC
V
IN
= V
SS
or V
CC
5
pF
inputs − Ports P1 and P2
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Port P1, P2: P1.x to P2.x, External
trigger puls width to set interrupt
flag, (see Note 1)
t
External interrupt timing
2.2 V/3 V
20
ns
(int)
NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t
(int)
is met. It may be set even with trigger signals
shorter than t
.
(int)
leakage current − Ports P1 and P2
PARAMETER
TEST CONDITIONS
see Notes 1 and 2
or V applied to the corresponding pin(s), unless otherwise noted.
VCC
MIN
TYP
MAX UNIT
50 nA
I
High-impedance leakage current
2.2 V/3 V
lkg(Px.x)
NOTES: 1. The leakage current is measured with V
SS
CC
2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pull−up/pull−down resistor
is disabled.
16
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs − Ports P1 and P2
PARAMETER
TEST CONDITIONS
= −1.5 mA (see Note 1)
= −6 mA (see Note 2)
= −1.5 mA (see Note 1)
= −6 mA (see Note 2)
= 1.5 mA (see Note 1)
= 6 mA (see Note 2)
= 1.5 mA (see Note 1)
= 6 mA (see Note 2)
VCC
2.2 V
2.2 V
3 V
MIN
−0.25
TYP
MAX
UNIT
I
I
I
I
I
I
I
I
V
V
CC
V
CC
V
CC
V
CC
(OHmax)
(OHmax)
(OHmax)
(OHmax)
(OLmax)
(OLmax)
(OLmax)
(OLmax)
CC
V
−0.6
High-level output
voltage
CC
−0.25
V
V
OH
OL
V
CC
3 V
V
−0.6
CC
2.2 V
2.2 V
3 V
V
V
+0.25
SS
SS
SS
SS
SS
V
V
V
V +0.6
SS
Low-level output
voltage
V
V
V
+0.25
+0.6
SS
3 V
V
SS
NOTES: 1. The maximum total current, I
voltage drop specified.
and I
, for all outputs combined, should not exceed 12 mA to hold the maximum
OHmax
OLmax
OLmax
2. The maximum total current, I
voltage drop specified.
and I
, for all outputs combined, should not exceed 48 mA to hold the maximum
OHmax
output frequency − Ports P1 and P2
PARAMETER
TEST CONDITIONS
VCC
2.2 V
3 V
MIN
TYP
MAX UNIT
10 MHz
12 MHz
12 MHz
16 MHz
Port output frequency
(with load)
P1.4/SMCLK, C = 20 pF, R = 1 kOhm
L
L
f
f
Px.y
(see Note 1 and 2)
2.2 V
3 V
P2.0/ACLK, P1.4/SMCLK, C = 20 pF
L
(see Note 2)
Clock output frequency
Port_CLK
NOTES: 1. A resistive divider with 2 times 0.5 kW between V
and V
is used as load. The output is connected to the center tap of the divider.
at the specified toggle frequency.
CC
SS
2. The output voltage reaches at least 10% and 90% V
CC
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics − outputs
TYPICAL LOW-LEVEL OUTPUT CURRENT
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
25.0
20.0
15.0
10.0
5.0
50.0
40.0
30.0
20.0
10.0
0.0
V
CC
P2.4
= 2.2 V
T
= 25°C
V
CC
P2.4
= 3 V
A
T
= 25°C
= 85°C
A
T
= 85°C
A
T
A
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OL
− Low-Level Output Voltage − V
V
OL
− Low-Level Output Voltage − V
Figure 4
Figure 5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
0.0
−5.0
0.0
−10.0
−20.0
−30.0
−40.0
−50.0
V
= 2.2 V
CC
P2.4
V
= 3 V
CC
P2.4
−10.0
−15.0
−20.0
−25.0
T
= 85°C
A
T
A
= 85°C
T
A
= 25°C
T
= 25°C
A
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OH
− High-Level Output Voltage − V
V
OH
− High-Level Output Voltage − V
Figure 6
Figure 7
NOTE: One output loaded at a time.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
POR/brownout reset (BOR) (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
T
A
VCC
MIN
TYP
MAX UNIT
V
V
(see Figure 8)
dV /dt ≤ 3 V/s
0.7 × V
V
CC(start)
CC
dV /dt ≤ 3 V/s
(B_IT−)
(see Figure 8 through Figure 10)
(see Figure 8)
1.71
180
V
(B_IT−)
CC
-40−85°C
105°C
70
70
130
130
mV
mV
µs
V
dV /dt ≤ 3 V/s
CC
hys(B_IT−)
d(BOR)
(reset)
210
t
t
(see Figure 8)
2000
Pulse length needed at RST/NMI
pin to accepted reset internally
2.2 V/3 V
2
µs
NOTES: 1. The current consumption of the brownout module is already included in the I
current consumption data. The voltage level V
(B_IT−)
CC
+ V
is ≤ 1.8V.
2. During power up, the CPU begins code execution following a period of t
hys(B_IT−)
after V
CC
= V
(B_IT−)
+ V . The default
hys(B_IT−)
d(BOR)
CC(min)
DCO settings must not be changed until V
operating frequency.
≥ V
, where V
is the minimum supply voltage for the desired
CC
CC(min)
V
CC
V
hys(B_IT−)
V
(B_IT−)
V
CC(start)
1
0
t
d(BOR)
Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics − POR/brownout reset (BOR)
V
t
CC
pw
2
3 V
V
= 3 V
CC
Typical Conditions
1.5
1
V
CC(drop)
0.5
0
0.001
1
1000
1 ns
1 ns
− Pulse Width − µs
t
− Pulse Width − µs
t
pw
pw
Figure 9. V
Level With a Square Voltage Drop to Generate a POR/Brownout Signal
CC(drop)
V
t
CC
pw
2
3 V
V
= 3 V
CC
Typical Conditions
1.5
1
V
CC(drop)
0.5
0
t = t
f
r
0.001
1
1000
t
t
r
f
t
− Pulse Width − µs
t
− Pulse Width − µs
pw
pw
Figure 10. V
Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
CC(drop)
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
main DCO characteristics
D
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
D
DCO control bits DCOx have a step size as defined by parameter S
.
DCO
D
Modulation control bits MODx select how often f
is used within the period of 32 DCOCLK
DCO(RSEL,DCO+1)
cycles. The frequency f
to:
is used for the remaining cycles. The frequency is an average equal
DCO(RSEL,DCO)
32 fDCO(RSEL,DCO) fDCO(RSEL,DCO)1)
faverage
+
MOD fDCO(RSEL,DCO))(32*MOD) fDCO(RSEL,DCO)1)
DCO frequency
PARAMETER
TEST CONDITIONS
RSELx < 14
VCC
MIN
1.8
TYP
MAX UNIT
3.6
3.6
3.6
V
V
V
RSELx = 14
2.2
3.0
Vcc
Supply voltage range
RSELx = 15
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
DCO frequency (0, 0)
DCO frequency (0, 3)
DCO frequency (1, 3)
DCO frequency (2, 3)
DCO frequency (3, 3)
DCO frequency (4, 3)
DCO frequency (5, 3)
DCO frequency (6, 3)
DCO frequency (7, 3)
DCO frequency (8, 3)
DCO frequency (9, 3)
DCO frequency (10, 3)
DCO frequency (11, 3)
DCO frequency (12, 3)
DCO frequency (13, 3)
DCO frequency (14, 3)
DCO frequency (15, 3)
DCO frequency (15, 7)
Frequency step between
RSELx = 0, DCOx = 0, MODx = 0
RSELx = 0, DCOx = 3, MODx = 0
RSELx = 1, DCOx = 3, MODx = 0
RSELx = 2, DCOx = 3, MODx = 0
RSELx = 3, DCOx = 3, MODx = 0
RSELx = 4, DCOx = 3, MODx = 0
RSELx = 5, DCOx = 3, MODx = 0
RSELx = 6, DCOx = 3, MODx = 0
RSELx = 7, DCOx = 3, MODx = 0
RSELx = 8, DCOx = 3, MODx = 0
RSELx = 9, DCOx = 3, MODx = 0
RSELx = 10, DCOx = 3, MODx = 0
RSELx = 11, DCOx = 3, MODx = 0
RSELx = 12, DCOx = 3, MODx = 0
RSELx = 13, DCOx = 3, MODx = 0
RSELx = 14, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 7, MODx = 0
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
3 V
0.06
0.07
0.10
0.14
0.20
0.28
0.39
0.54
0.80
1.10
1.60
2.50
3.00
4.30
6.00
8.60
12.0
16.0
0.14 MHz
0.17 MHz
0.20 MHz
0.28 MHz
0.40 MHz
0.54 MHz
0.77 MHz
1.06 MHz
1.50 MHz
2.10 MHz
3.00 MHz
4.30 MHz
5.50 MHz
7.30 MHz
9.60 MHz
13.9 MHz
18.5 MHz
26.0 MHz
DCO(0,0)
DCO(0,3)
DCO(1,3)
DCO(2,3)
DCO(3,3)
DCO(4,3)
DCO(5,3)
DCO(6,3)
DCO(7,3)
DCO(8,3)
DCO(9,3)
DCO(10,3)
DCO(11,3)
DCO(12,3)
DCO(13,3)
DCO(14,3)
DCO(15,3)
DCO(15,7)
3 V
S
=
RSEL
S
2.2 V/3 V
1.55
ratio
1.12
RSEL
DCO
range RSEL and RSEL+1
f
/f
DCO(RSEL+1,DCO) DCO(RSEL,DCO)
Frequency step between
tap DCO and DCO+1
S
=
DCO
S
2.2 V/3 V
2.2 V/3 V
1.05
40
1.08
50
f
/f
DCO(RSEL,DCO+1) DCO(RSEL,DCO)
Duty Cycle
Measured at P1.4/SMCLK
60
%
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies − tolerance at calibration
PARAMETER
TEST CONDITIONS
T
VCC
MIN
−1
TYP
0.2
MAX UNIT
+1
A
Frequency tolerance at calibration
25°C
3 V
%
BCSCTL1= CALBC1_1MHZ
DCOCTL = CALDCO_1MHZ
Gating time: 5ms
f
1MHz calibration value
8MHz calibration value
12MHz calibration value
16MHz calibration value
25°C
3 V
3 V
3 V
3 V
0.990
7.920
11.88
15.84
1
8
1.010 MHz
8.080 MHz
CAL(1MHz)
BCSCTL1= CALBC1_8MHZ
DCOCTL = CALDCO_8MHZ
Gating time: 5ms
f
25°C
25°C
25°C
CAL(8MHz)
BCSCTL1= CALBC1_12MHZ
DCOCTL = CALDCO_12MHZ
Gating time: 5ms
f
12 12.12 MHz
16 16.16 MHz
CAL(12MHz)
BCSCTL1= CALBC1_16MHZ
DCOCTL = CALDCO_16MHZ
Gating time: 2ms
f
CAL(16MHz)
calibrated DCO frequencies − tolerance over temperature 0°C − +85°C
PARAMETER
TEST CONDITIONS
T
VCC
3.0 V
3.0 V
3.0 V
3.0 V
2.2 V
3.0 V
3.6 V
2.2 V
3.0 V
3.6 V
2.2 V
3.0 V
3.6 V
MIN
TYP
MAX UNIT
A
1 MHz tolerance over temperature
8 MHz tolerance over temperature
12 MHz tolerance over temperature
16 MHz tolerance over temperature
0−85°C
0−85°C
0−85°C
0−85°C
−2.5
0.5
1.0
1.0
2.0
1
+2.5
+2.5
+2.5
+3.0
%
%
%
%
−2.5
−2.5
−3.0
0.970
0.975
0.970
7.760
7.800
7.600
11.70
11.70
11.70
1.030 MHz
1.025 MHz
1.030 MHz
8.400 MHz
8.200 MHz
8.240 MHz
BCSCTL1= CALBC1_1MHZ
DCOCTL = CALDCO_1MHZ
Gating time: 5ms
1
f
1MHz calibration value
8MHz calibration value
0−85°C
0−85°C
CAL(1MHz)
1
8
BCSCTL1= CALBC1_8MHZ
DCOCTL = CALDCO_8MHZ
Gating time: 5ms
8
f
CAL(8MHz)
8
12 12.30 MHz
12 12.30 MHz
12 12.30 MHz
BCSCTL1= CALBC1_12MHZ
DCOCTL = CALDCO_12MHZ
Gating time: 5ms
f
12MHz calibration value
16MHz calibration value
0−85°C
0−85°C
CAL(12MHz)
BCSCTL1= CALBC1_16MHZ
DCOCTL = CALDCO_16MHZ
Gating time: 2ms
3.0 V
3.6 V
15.52
15.00
16 16.48 MHz
16 16.48 MHz
f
CAL(16MHz)
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies − tolerance over supply voltage V
CC
PARAMETER
TEST CONDITIONS
T
VCC
MIN
−3
TYP
MAX UNIT
A
1 MHz tolerance over V
8 MHz tolerance over V
25°C
1.8 V − 3.6 V
1.8 V − 3.6 V
2.2 V − 3.6 V
3.0 V − 3.6 V
2
+3
+3
+3
+3
%
%
%
%
CC
25°C
25°C
25°C
−3
−3
−3
2
2
2
CC
12 MHz tolerance over V
CC
CC
16 MHz tolerance over V
BCSCTL1= CALBC1_1MHZ
DCOCTL = CALDCO_1MHZ
Gating time: 5ms
f
1MHz calibration value
8MHz calibration value
12MHz calibration value
16MHz calibration value
25°C
25°C
25°C
25°C
1.8 V − 3.6 V
1.8 V − 3.6 V
2.2 V − 3.6 V
3.0 V − 3.6 V
0.970
7.760
11.64
15.00
1
8
1.030 MHz
8.240 MHz
CAL(1MHz)
BCSCTL1= CALBC1_8MHZ
DCOCTL = CALDCO_8MHZ
Gating time: 5ms
f
CAL(8MHz)
BCSCTL1= CALBC1_12MHZ
DCOCTL = CALDCO_12MHZ
Gating time: 5ms
f
12 12.36 MHz
16 16.48 MHz
CAL(12MHz)
BCSCTL1= CALBC1_16MHZ
DCOCTL = CALDCO_16MHZ
Gating time: 2ms
f
CAL(16MHz)
calibrated DCO frequencies − overall tolerance
PARAMETER
TEST CONDITIONS
T
A
VCC
MIN
TYP
MAX UNIT
I: -40−85°C
T: -40−105°C
1 MHz tolerance overall
1.8 V − 3.6 V
−5
2
2
2
3
+5
+5
+5
+6
%
%
%
%
I: -40−85°C
T: -40−105°C
8 MHz tolerance overall
12 MHz tolerance overall
16 MHz tolerance overall
1.8 V − 3.6 V
2.2 V − 3.6 V
3.0 V − 3.6 V
−5
−5
−6
I: -40−85°C
T: -40−105°C
I: -40−85°C
T: -40−105°C
BCSCTL1= CALBC1_1MHZ
DCOCTL = CALDCO_1MHZ
Gating time: 5ms
I: -40−85°C
T: -40−105°C
f
1MHz calibration value
8MHz calibration value
12MHz calibration value
16MHz calibration value
1.8 V − 3.6 V
1.8 V − 3.6 V
2.2 V − 3.6 V
3.0 V − 3.6 V
0.950
7.600
11.40
15.00
1
8
1.050 MHz
8.400 MHz
CAL(1MHz)
BCSCTL1= CALBC1_8MHZ
DCOCTL = CALDCO_8MHZ
Gating time: 5ms
I: -40−85°C
T: -40−105°C
f
CAL(8MHz)
BCSCTL1= CALBC1_12MHZ
DCOCTL = CALDCO_12MHZ
Gating time: 5ms
I: -40−85°C
T: -40−105°C
f
12 12.60 MHz
16 17.00 MHz
CAL(12MHz)
BCSCTL1= CALBC1_16MHZ
DCOCTL = CALDCO_16MHZ
Gating time: 2ms
I: -40−85°C
T: -40−105°C
f
CAL(16MHz)
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢈ
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics − calibrated 1MHz DCO frequency
1.03
1.02
V
V
= 1.8 V
= 2.2 V
CC
1.01
1.00
0.99
0.98
0.97
CC
V
CC
= 3.0 V
V
CC
= 3.6 V
−50.0 −25.0
0.0
25.0
50.0
75.0 100.0
T
A
− Temperature − °C
Figure 11. Calibrated 1 MHz Frequency vs. Temperature
1.03
1.02
1.01
1.00
0.99
0.98
0.97
T
= 105 °C
= 85 °C
A
T
A
T
= 25 °C
A
T
= −40 °C
A
1.5
2.0
2.5
3.0
3.5
4.0
V
CC
− Supply Voltage − V
Figure 12. Calibrated 1 MHz Frequency vs. V
CC
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
wake-up from lower power modes (LPM3/4)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
BCSCTL1= CALBC1_1MHZ;
DCOCTL = CALDCO_1MHZ
2.2 V/3 V
2
BCSCTL1= CALBC1_8MHZ;
DCOCTL = CALDCO_8MHZ
2.2 V/3 V
2.2 V/3 V
3 V
1.5
DCO clock wake−up time from
LPM3/4
(see Note 1)
t
t
µs
DCO,LPM3/4
BCSCTL1= CALBC1_12MHZ;
DCOCTL = CALDCO_12MHZ
1
BCSCTL1= CALBC1_16MHZ;
DCOCTL = CALDCO_16MHZ
1
CPU wake−up time from LPM3/4
(see Note 2)
1/f
+
MCLK
CPU,LPM3/4
t
Clock,LPM3/4
NOTES: 1. The DCO clock wake−up time is measured from the edge of an external wake−up signal (e.g. port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK).
2. Parameter applicable only if DCOCLK is used for MCLK.
typical characteristics − DCO clock wake−up time from LPM3/4
10.00
RSELx = 0...11
1.00
0.10
RSELx = 12...15
0.10
1.00
DCO Frequency − MHz
10.00
Figure 13. DCO wake−up time from LPM3 vs DCO frequency
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, low frequency modes (see Note 4)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
LFXT1 oscillator crystal
frequency, LF mode 0, 1
f
XTS = 0, LFXT1Sx = 0 or 1
1.8 V − 3.6 V
32,768
Hz
LFXT1,LF
LFXT1 oscillator logic level
square wave input frequency,
LF mode
f
XTS = 0, LFXT1Sx = 3
XTS = 0, LFXT1Sx = 0;
1.8 V − 3.6 V
10,000 32,768 50,000
Hz
kW
kW
LFXT1,LF,logic
f
C
= 32,768 kHz,
500
200
LFXT1,LF
= 6 pF
L,eff
XTS = 0, LFXT1Sx = 0;
= 32,768 kHz,
Oscillation Allowance for LF
crystals
OA
LF
f
LFXT1,LF
= 12 pF
C
L,eff
XTS = 0, XCAPx = 0
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
XTS = 0, XCAPx = 3
XTS = 0, Measured at
1
5.5
8.5
11
pF
pF
pF
pF
Integrated effective Load
Capacitance, LF mode
(see Note 1)
C
L,eff
Duty Cycle
LF mode
P1.4/ACLK, f
Hz
= 32,768
2.2 V/3 V
2.2 V/3 V
30
10
50
70
%
LFXT1,LF
Oscillator fault frequency, LF
mode (see Note 3)
XTS = 0, LFXT1Sx = 3
(see Notes 2)
f
10,000
Hz
Fault,LF
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Measured with logic level input frequency but also applies to operation with crystals.
3. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
− Keep as short of a trace as possible between the device and the crystal.
− Design a good ground plane around the oscillator pins.
− Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
− Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
− Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
− If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
− Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
26
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, high frequency modes (see Note 5)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
LFXT1 oscillator crystal frequency,
HF mode 0
f
f
XTS = 1, LFXT1Sx = 0
1.8 V − 3.6 V
0.4
1
4
MHz
MHz
LFXT1,HF0
LFXT1 oscillator crystal frequency,
HF mode 1
XTS = 1, LFXT1Sx = 1
XTS = 1, LFXT1Sx = 2
1.8 V − 3.6 V
1
LFXT1,HF1
1.8 V − 3.6 V
2.2 V − 3.6 V
3.0 V − 3.6 V
1.8 V − 3.6 V
2.2 V − 3.6 V
3.0 V − 3.6 V
2
2
10 MHz
12 MHz
16 MHz
10 MHz
12 MHz
16 MHz
LFXT1 oscillator crystal frequency,
HF mode 2
f
LFXT1,HF2
2
0.4
0.4
0.4
LFXT1 oscillator logic level square
wave input frequency,
HF mode
f
XTS = 1, LFXT1Sx = 3
XTS = 0, LFXT1Sx = 0,
LFXT1,HF,logic
f
C
= 1 MHz,
2700
800
300
1
W
W
LFXT1,HF
= 15 pF
L,eff
XTS = 0, LFXT1Sx = 1
= 4 MHz,
Oscillation Allowance for HF
crystals
(refer to Figure 14 and Figure 15)
f
C
OA
HF
LFXT1,HF
= 15 pF
L,eff
XTS = 0, LFXT1Sx = 2
= 16 MHz,
f
C
W
LFXT1,HF
= 15 pF
L,eff
Integrated effective Load
Capacitance, HF mode
(see Note 1)
C
XTS = 1 (see Note 2)
pF
L,eff
XTS = 1, Measured at P1.4/ACLK,
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
40
40
30
50
50
60
60
%
%
f
= 10 MHz
LFXT1,HF
XTS = 1, Measured at P1.4/ACLK,
= 16 MHz
Duty Cycle
HF mode
f
LFXT1,HF
Oscillator fault frequency, HF mode XTS = 1, LFXT1Sx = 3
(see Note 4) (see Notes 3)
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin).
f
300 kHz
Fault,HF
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
3. Measured with logic level input frequency but also applies to operation with crystals.
4. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
5. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
− Keep as short of a trace as possible between the device and the crystal.
− Design a good ground plane around the oscillator pins.
− Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
− Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
− Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
− If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
− Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
27
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics − LFXT1 oscillator in HF mode (XTS = 1)
100000.00
10000.00
1000.00
LFXT1Sx = 3
100.00
LFXT1Sx = 2
10.00
LFXT1Sx = 1
1.00
10.00
0.10
100.00
Crystal Frequency − MHz
Figure 14. Oscillation Allowance vs Crystal Frequency, C
= 15 pF, T = 25°C
A
L,eff
800.0
LFXT1Sx = 3
700.0
600.0
500.0
400.0
300.0
200.0
100.0
0.0
LFXT1Sx = 2
LFXT1Sx = 1
0.0
4.0
8.0
12.0
16.0
20.0
Crystal Frequency − MHz
Figure 15. XT Oscillator Supply Current vs Crystal Frequency, C
= 15 pF, T = 25°C
A
L,eff
28
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Timer_A
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK;
External: TACLK, INCLK;
Duty Cycle = 50% 10%
2.2 V
10
f
t
Timer_A clock frequency
Timer_A, capture timing
MHz
16
TA
3 V
TA0, TA1, TA2
2.2 V/3 V
20
ns
TA,cap
Comparator_A+ (see Note 1)
PARAMETER
TEST CONDITIONS
VCC
2.2 V
3 V
MIN
TYP
25
MAX UNIT
40
µA
60
I
I
CAON=1, CARSEL=0, CAREF=0
(DD)
45
CAON=1, CARSEL=0,
CAREF=1/2/3, no load at
P2.3/CA0/TA1 and P2.4/CA1/TA2
2.2 V
3 V
30
45
50
µA
71
(Refladder/RefDiode)
Common-mode input
voltage
V
CAON=1
2.2 V/3 V
2.2 V/3 V
0
V
CC
−1
V
(IC)
PCA0=1, CARSEL=1, CAREF=1,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
Voltage @ 0.25 V
node
CC
V
0.23
0.24
0.48
0.25
0.5
(Ref025)
V
CC
PCA0=1, CARSEL=1, CAREF=2,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
Voltage @ 0.5V
node
CC
V
2.2 V/3 V
0.47
(Ref050)
(RefVT)
V
CC
PCA0=1, CARSEL=1, CAREF=3,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2, T = 85°C
2.2 V
3 V
390
400
480
490
540
550
V
(see Figure 19 and Figure 20)
mV
A
V
V
Offset voltage
See Note 2
2.2 V/3 V
2.2 V/3 V
−30
0
30
mV
mV
(offset)
Input hysteresis
CAON=1
0.7
1.4
hys
T
= 25°C, Overdrive 10 mV,
A
2.2 V
3 V
80
70
165
300
240
2.8
2.2
Without filter: CAF=0
(see Note 3, Figure 16 and
Figure 17)
ns
120
1.9
1.5
Response time
(low−high and high−low)
t
(response)
T
= 25°C, Overdrive 10 mV,
A
2.2 V
1.4
0.9
With filter: CAF=1
(see Note 3, Figure 16 and
Figure 17)
µs
3 V
NOTES: 1. The leakage current for the Comparator_A+ terminals is identical to I
specification.
lkg(Px.x)
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements.
The two successive measurements are then summed together.
3. Response time measured at P2.2/CAOUT.
29
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
0 V
V
CC
0
1
CAF
CAON
To Internal
Modules
Low Pass Filter
0
1
0
1
+
_
V+
V−
CAOUT
Set CAIFG
Flag
τ ≈ 2.0 µs
Figure 16. Block Diagram of Comparator_A+ Module
V
CAOUT
Overdrive
V−
400 mV
V+
t
(response)
Figure 17. Overdrive Definition
CASHORT
CA1
CA0
1
+
−
I
= 10µA
OUT
V
IN
Comparator_A+
CASHORT = 1
Figure 18. Comparator_A+ Short Resistance Test Condition
30
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics − Comparator_A+
650
600
550
500
450
400
650
600
550
500
450
400
V
= 2.2 V
V
CC
= 3 V
CC
Typical
Typical
−45
−25
−5
15
35
55
75
95
−45
−25
−5
15
35
55
75
95
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 20. V
vs Temperature, V
= 2.2 V
Figure 19. V
vs Temperature, V
= 3 V
(RefVT)
CC
(RefVT)
CC
100.00
10.00
1.00
V
CC
= 1.8V
V
= 2.2V
CC
V
CC
= 3.0V
V
CC
= 3.6V
0.6
0.0
0.2
/V
0.4
0.8
1.0
V
− Normalized Input Voltage − V/V
IN CC
Figure 21. Short Resistance vs V /V
IN CC
31
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Flash Memory
PARAMETER
TEST CONDITIONS
VCC
MIN
2.2
TYP
MAX UNIT
V
CC(PGM/
ERASE)
Program and Erase supply voltage
Flash Timing Generator frequency
3.6
V
f
I
I
t
t
257
476
5
kHz
mA
FTG
Supply current from V
Supply current from V
during program
during erase
2.2 V/3.6 V
2.2 V/3.6 V
2.2 V/3.6 V
2.2 V/3.6 V
3
3
PGM
CC
7
mA
ERASE
CPT
CC
Cumulative program time (see Note 1)
Cumulative mass erase time
Program/Erase endurance
Data retention duration
10
ms
20
ms
CMErase
4
10
5
10
cycles
years
t
T = 25°C
J
100
Retention
t
t
t
t
t
t
Word or byte program time
30
25
Word
st
Block program time for 1 byte or word
Block, 0
Block program time for each additional byte or word
Block program end-sequence wait time
Mass erase time
18
Block, 1-63
Block, End
Mass Erase
Seg Erase
see Note 2
t
FTG
6
10593
4819
Segment erase time
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. These values are hardwired into the Flash Controller’s state machine (t
FTG
= 1/f ).
FTG
RAM
PARAMETER
TEST CONDITIONS
CPU halted
MIN
TYP
MAX UNIT
V
RAM retention supply voltage (see Note 1)
1.6
V
(RAMh)
NOTE 1: This parameter defines the minimum supply voltage V
happen during this supply voltage condition.
when the data in RAM remains unchanged. No program execution should
CC
JTAG Interface
PARAMETER
TEST CONDITIONS
VCC
2.2 V
MIN
0
TYP
MAX UNIT
MHz
10 MHz
90 kΩ
5
f
TCK input frequency
see Note 1
TCK
3 V
0
R
Internal pull-down resistance on TEST
2.2 V/3 V
25
60
Internal
NOTES: 1. f
may be restricted to meet the timing requirements of the module selected.
TCK
JTAG Fuse (see Note 1)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.5
6
TYP
MAX UNIT
V
V
Supply voltage during fuse-blow condition
Voltage level on TEST for fuse-blow
Supply current into TEST during fuse blow
Time to blow fuse
T
= 25°C
= 25°C
= 25°C
= 25°C
V
CC(FB)
A
T
7
100
1
V
FB
A
I
t
T
mA
ms
FB
A
T
FB
A
NOTES: 1. Once the fuse is blown, no further access to the JTAG/Test and emulation feature is possible and is switched to bypass mode.
32
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
APPLICATION INFORMATION
Port P1 pin schematic: P1.0 to P1.3, input/output with Schmitt-trigger
Pad Logic
P1REN.x
DVSS
DVCC
0
1
1
P1DIR.x
0
1
Direction
0: Input
1: Output
0
1
P1OUT.x
Module X OUT
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1SEL.x
P1IN.x
EN
D
Module X IN
P1IRQ.x
P1IE.x
EN
Q
Set
P1IFG.x
Interrupt
Edge
Select
P1SEL.x
P1IES.x
Port P1 (P1.0 to P1.3) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
P1DIR.x
P1SEL.x
P1.0/TACLK
0
P1.0† (I/O)
TACLK
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
0
DV
1
SS
P1.1/TA0
P1.2/TA1
P1.3/TA2
1
2
3
P1.1† (I/O)
I: 0; O: 1
Timer_A3.CCI0A
Timer_A3.TA0
P1.2† (I/O)
0
1
I: 0; O: 1
Timer_A3.CCI0A
Timer_A3.TA0
P1.3† (I/O)
0
1
I: 0; O: 1
Timer_A3.CCI0A
Timer_A3.TA0
0
1
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
33
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
Port P1 pin schematic: P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features
Pad Logic
P1REN.1
DVSS
DVCC
0
1
1
P1DIR.1
0
1
Direction
0: Input
1: Output
0
1
P1OUT.1
Module X OUT
P1.4/SMCLK/TCK
P1.5/TA0/TMS
P1.6/TA1/TDI
Bus
Keeper
P1SEL.1
P1IN.1
P1.7/TA2/TDO/TDI
EN
EN
D
Module X IN
P1IRQ.1
P1IE.1
EN
Q
Set
P1IFG.1
Interrupt
Edge
Select
P1SEL.1
P1IES.1
To JTAG
From JTAG
TDO From JTAG
P1.7/TA2/TDO/TDI only
TEST pad
TEST
JTAG
Fuse
DVSS
34
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
Port P1 (P1.4 to P1.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
P1DIR.x
P1SEL.x
TEST
P1.4/SMCLK/TCK
4
P1.4† (I/O)
I: 0; O: 1
0
1
X
0
1
X
0
1
X
0
1
X
0
0
1
0
0
1
0
0
1
0
0
1
SMCLK
1
TCK
X
P1.5/TA0/TMS
5
6
7
P1.5† (I/O)
I: 0; O: 1
Timer_A3.TA0
TMS
1
X
P1.6/TA1/TDI/TCLK
P1.7/TA2/TDO/TDI
P1.6† (I/O)
I: 0; O: 1
Timer_A3.TA1
TDI/TCLK (see Note 3)
P1.7† (I/O)
1
X
I: 0; O: 1
Timer_A3.TA2
TDO/TDI (see Note 3)
1
X
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Function controlled by JTAG.
35
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
Port P2 pin schematic: P2.0 to P2.5, input/output with Schmitt-trigger
Pad Logic
To Comparator_A+
From Comparator_A+
CAPD.x
P2REN.x
DVSS
DVCC
0
1
1
P2DIR.x
0
1
Direction
0: Input
1: Output
0
1
P2OUT.x
Module X OUT
P2.0/ACLK/CA2
P2.1/INCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/TA1/CA0
P2.4/TA2/CA1
P2.5/CA5
Bus
Keeper
P2SEL.x
P2IN.x
EN
EN
D
Module X IN
P2IRQ.x
P2IE.x
EN
Q
Set
P2IFG.x
Interrupt
Edge
Select
P2SEL.x
P2IES.x
Control signal “From Comparator_A+”
SIGNAL “FROM COMPARATOR_A+” = 1
PIN NAME
FUNCTION
P2CA4
1
P2CA0
P2CA3
P2CA2
P2CA1
P2.0/ACLK/CA2
P2.1/INCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/TA1/CA0
CA2
CA3
CA4
CA0
CA1
CA5
1
N/A
N/A
1
0
0
1
1
0
1
N/A
N/A
0
1
0
0
OR
N/A
0
N/A
0
N/A
1
P2.4/TA2/CA1
1
0
P2.5/CA5
N/A
N/A
1
0
1
NOTES: 1. N/A: Not available or not applicable.
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
Port P2 (P2.0 to P2.5) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
X
FUNCTION
P2DIR.x
P2SEL.x
CAPD.x
P2.0/ACLK/CA2
0
P2.0† (I/O)
I: 0; O: 1
0
1
X
0
1
1
X
0
1
1
X
0
1
X
0
1
X
0
X
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
1
0
1
ACLK
1
CA2 (see Note 3)
P2.1† (I/O)
X
P2.1/INCLK/CA3
1
2
I: 0; O: 1
Timer_A3.INCLK
0
DV
1
SS
CA3 (see Note 3)
P2.2† (I/O)
X
P2.2/CAOUT/TA0/CA4
I: 0; O: 1
Timer_A3.CCI0B
CAOUT
0
1
CA4 (see Note 3)
P2.3† (I/O)
X
P2.3/TA1/CA0
P2.4/TA2/CA1
P2.5/CA5
3
4
5
I: 0; O: 1
Timer_A3.TA1
CA0 (see Note 3)
P2.4† (I/O)
1
X
I: 0; O: 1
Timer_A3.TA2
CA1 (see Note 3)
P2.5† (I/O)
1
X
I: 0; O: 1
X
CA5 (see Note 3)
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the CAPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CAx input pin to the comparator multiplexer with the P2CAx bits automatically disables the input buffer
for that pin, regardless of the state of the associated CAPD.x bit.
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢈ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
Port P2 pin schematic: P2.6, input/output with Schmitt-trigger and crystal oscillator input
Pad Logic
To Comparator_A+
From Comparator_A+
CAPD.x
LFXT1 Oscillator
BCSCTL3.LFXT1Sx = 11
P2.7/XOUT/CA7
LFXT1 off
0
LFXT1CLK
1
P2SEL.7
P2REN.6
DVSS
DVCC
0
1
1
P2DIR.6
0
1
Direction
0: Input
1: Output
0
1
P2OUT.6
Module X OUT
P2.6/XIN/CA6
Bus
Keeper
P2SEL.6
P2IN.6
EN
EN
D
Module X IN
P2IRQ.6
P2IE.6
EN
Set
Q
P2IFG.6
Interrupt
Edge
Select
P2SEL.6
P2IES.6
Control signal “From Comparator_A+”
SIGNAL “FROM COMPARATOR_A+” = 1
PIN NAME
FUNCTION
P2CA3
P2CA2
P2CA1
P2.6/XIN/CA6
CA6
1
1
0
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢈ ꢆꢈ
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
Port P2 pin schematic: P2.7, input/output with Schmitt-trigger and crystal oscillator output
Pad Logic
To Comparator_A+
From Comparator_A+
CAPD.x
LFXT1 Oscillator
BCSCTL3.LFXT1Sx = 11
LFXT1 off
0
LFXT1CLK
From
P2.6/XIN
P2.6/XIN/CA6
1
Pad Logic
P2SEL.6
P2REN.7
DVSS
DVCC
0
1
1
P2DIR.7
0
1
Direction
0: Input
1: Output
0
1
P2OUT.7
Module X OUT
P2.7/XOUT/CA7
Bus
Keeper
P2SEL.7
P2IN.7
EN
EN
D
Module X IN
P2IRQ.7
P2IE.7
EN
Set
Q
P2IFG.7
Interrupt
Edge
Select
P2SEL.7
P2IES.7
Control signal “From Comparator_A+”
SIGNAL “FROM COMPARATOR_A+” = 1
PIN NAME
FUNCTION
P2CA3
P2CA2
P2CA1
P2.7/XOUT/CA7
CA7
1
1
1
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢈ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
Port P2 (P2.6) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
X
FUNCTION
P2DIR.x
P2SEL.x
CAPD.x
P2.6/XIN/CA6
6
P2.6 (I/O)
XIN†
I: 0; O: 1
0
1
0
0
1
X
X
CA6 (see Note 3)
X
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the CAPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CAx input pin to the comparator multiplexer with the P2CAx bits automatically disables the input buffer
for that pin, regardless of the state of the associated CAPDx bit.
Port P2 (P2.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
X
FUNCTION
P2DIR.x
P2SEL.x
CAPD.x
P2.7/XOUT/CA7
6
P2.7 (I/O)
I: 0; O: 1
0
1
0
0
1
XOUT† (see Note 4)
CA7 (see Note 3)
X
X
X
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the CAPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CAx input pin to the comparator multiplexer with the P2CAx bits automatically disables the input buffer
for that pin, regardless of the state of the associated CAPD.x bit.
4. If the pin XOUT/P2.7/CA7 is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection
to this pin after reset.
40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢈ ꢆꢈ
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
JTAG fuse check mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of
the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, I , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care
TF
must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense
currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS
is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.
After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse
check mode has the potential to be activated.
The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see
Figure 22). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
I
TF
I
TEST
Figure 22. Fuse Check Mode Current, MSP430F21x1
NOTE:
The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader
access key is used. Also, see the bootstrap loader section for more information.
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢆꢈ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
Data Sheet Revision History
Literature
Number
Summary
SLAS439
SLAS439A
SLAS439B
Preliminary PRODUCT PREVIEW datasheet release.
MSP430x21x1 production datasheet release.
Corrected instruction cycle time to 62.5ns, pg 1
Updated Figure 1. Operating Area, pg 12
Updated Figures 2 & 3, pg 13
R
unit corrected from ”W” to ”kW”, pg 15
Pull
Max load current specification and Note 3 removed from ”outputs” table, pg 16
MIN and MAX percentages for ”calibrated DCO frequencies − tolerance over supply voltage VCC” corrected from 2.5% to
3% to match the specified frequency ranges., pg 22
SLAS439C
MSP430x21x1T production datasheet release.
105°C characterization results added.
NOTE: The referring page and figure numbers are referred to the respective document revision.
42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
MSP430F2101IDGV
MSP430F2101IDGVR
MSP430F2101IDW
MSP430F2101IDWR
MSP430F2101IPW
MSP430F2101IPWR
MSP430F2101IRGER
MSP430F2101IRGET
MSP430F2101TDGV
MSP430F2101TDGVR
MSP430F2101TDW
MSP430F2101TDWR
MSP430F2101TPW
MSP430F2101TPWR
MSP430F2101TRGER
MSP430F2101TRGET
MSP430F2111IDGV
MSP430F2111IDGVR
MSP430F2111IDW
MSP430F2111IDWR
MSP430F2111IPW
MSP430F2111IPWR
MSP430F2111IRGER
MSP430F2111IRGET
MSP430F2111TDGV
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TVSOP
DGV
20
20
20
20
20
20
24
24
20
20
20
20
20
20
24
24
20
20
20
20
20
20
24
24
20
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TVSOP
SOIC
DGV
DW
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
QFN
PW
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGE
RGE
DGV
DGV
DW
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TVSOP
TVSOP
SOIC
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
QFN
PW
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGE
RGE
DGV
DGV
DW
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TVSOP
TVSOP
SOIC
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
QFN
PW
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGE
RGE
DGV
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TVSOP
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
Orderable Device
MSP430F2111TDGVR
MSP430F2111TDW
MSP430F2111TDWR
MSP430F2111TPW
MSP430F2111TPWR
MSP430F2111TRGER
MSP430F2111TRGET
MSP430F2121IDGV
MSP430F2121IDGVR
MSP430F2121IDW
MSP430F2121IDWR
MSP430F2121IPW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TVSOP
DGV
20
20
20
20
20
24
24
20
20
20
20
20
20
24
24
20
20
20
20
20
20
24
24
20
20
20
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
SOIC
DW
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
QFN
PW
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGE
RGE
DGV
DGV
DW
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TVSOP
TVSOP
SOIC
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
QFN
PW
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSP430F2121IPWR
MSP430F2121IRGER
MSP430F2121IRGET
MSP430F2121TDGV
MSP430F2121TDGVR
MSP430F2121TDW
MSP430F2121TDWR
MSP430F2121TPW
MSP430F2121TPWR
MSP430F2121TRGER
MSP430F2121TRGET
MSP430F2131IDGV
MSP430F2131IDGVR
MSP430F2131IDW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGE
RGE
DGV
DGV
DW
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TVSOP
TVSOP
SOIC
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
QFN
PW
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGE
RGE
DGV
DGV
DW
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TVSOP
TVSOP
SOIC
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
Orderable Device
MSP430F2131IDWR
MSP430F2131IPW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
DW
20
20
20
24
24
20
20
20
20
20
20
24
24
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
QFN
PW
PW
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSP430F2131IPWR
MSP430F2131IRGER
MSP430F2131IRGET
MSP430F2131TDGV
MSP430F2131TDGVR
MSP430F2131TDW
MSP430F2131TDWR
MSP430F2131TPW
MSP430F2131TPWR
MSP430F2131TRGER
MSP430F2131TRGET
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGE
RGE
DGV
DGV
DW
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TVSOP
TVSOP
SOIC
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
QFN
PW
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGE
RGE
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 4
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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