MSP430F2617TPNR [TI]
MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器
| 型号： | MSP430F2617TPNR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MIXED SIGNAL MICROCONTROLLER |
| 文件： | 总98页 (文件大小：1650K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
D
D
Low Supply-Voltage Range, 1.8 V to 3.6 V
D
Supply Voltage Supervisor/Monitor With
Programmable Level Detection
Ultralow-Power Consumption:
-- Active Mode: 365 μA at 1 MHz, 2.2 V
-- Standby Mode (VLO): 0.5 μA
D
D
D
Brownout Detector
Bootstrap Loader
-- Off Mode (RAM Retention): 0.1 μA
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
D
D
Wake-Up From Standby Mode in Less
Than 1 μs
16-Bit RISC Architecture,
62.5-nsInstruction Cycle Time
D
Family Members Include:
-- MSP430F2416:
D
D
Three-Channel Internal DMA
92KB+256B Flash Memory, 4KB RAM
-- MSP430F2417:
92KB+256B Flash Memory, 8KB RAM
-- MSP430F2418:
116KB+256B Flash Memory, 8KB RAM
-- MSP430F2419:
120KB+256B Flash Memory, 4KB RAM
-- MSP430F2616:
12-Bit Analog-to-Digital (A/D) Converter
With Internal Reference, Sample-and-Hold,
and Autoscan Feature
D
D
D
Dual 12-Bit Digital-to-Analog (D/A)
Converters With Synchronization
16-Bit Timer_A With Three
Capture/Compare Registers
16-Bit Timer_B With Seven
Capture/Compare-With-Shadow Registers
92KB+256B Flash Memory, 4KB RAM
-- MSP430F2617:
92KB+256B Flash Memory, 8KB RAM
-- MSP430F2618:
116KB+256B Flash Memory, 8KB RAM
-- MSP430F2619:
D
D
On-Chip Comparator
Four Universal Serial Communication
Interfaces (USCIs)
-- USCI_A0 and USCI_A1
-- Enhanced UART Supporting
Auto-Baudrate Detection
-- IrDA Encoder and Decoder
-- Synchronous SPI
120KB+256B Flash Memory, 4KB RAM
D
D
Available in 80-Pin Quad Flat Pack (QFP)
and 64-Pin QFP (See Available Options)
For Complete Module Descriptions, See the
MSP430x2xx Family User’s Guide,
Literature Number SLAU144
-- USCI_B0 and USCI_B1
-- I 2Ct
†
The MSP430F241x devices are identical to the MSP430F261x
devices, with the exception that the DAC12 modules and the DMA
controller are not implemented.
-- Synchronous SPI
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The calibrated digitally controlled oscillator (DCO) allows wake-up from low-power modes to active
mode in less than 1 μs.
The MSP430F261x/241x series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit
A/D converter, a comparator, dual 12-bit D/A converters, four universal serial communication interface (USCI)
modules, DMA, and up to 64 I/O pins. The MSP430F241x devices are identical to the MSP430F261x devices,
with the exception that the DAC12 and the DMA modules are not implemented.
Typical applications include sensor systems, industrial control applications, hand-held meters, etc.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
I C is a registered trademark of Philips Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
PLASTIC 80-PIN LQFP (PN)
PLASTIC 64-PIN LQFP (PM)
MSP430F2416TPN
MSP430F2417TPN
MSP430F2418TPN
MSP430F2419TPN
MSP430F2616TPN
MSP430F2617TPN
MSP430F2618TPN
MSP430F2619TPN
MSP430F2416TPM
MSP430F2417TPM
MSP430F2418TPM
MSP430F2419TPM
MSP430F2616TPM
MSP430F2617TPM
MSP430F2618TPM
MSP430F2619TPM
-- 4 0 °C to 105°C
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
pin designation, MSP430F241x, 80-pin package
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DVCC1
P6.3/A3
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P7.6
2
P7.5
P6.4/A4
3
P7.4
P6.5/A5
4
P7.3
P6.6/A6
5
P7.2
P6.7/A7/SVSIN
VREF+
6
P7.1
7
P7.0
XIN
8
DVSS2
XOUT
9
DVCC2
80-pin
PN PACKAGE
(TOP VIEW)
VeREF+
10
11
12
13
14
15
16
17
18
19
20
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
VREF-/VeREF-
P1.0/TACLK/CAOUT
P1.1/TA0
P5.5/SMCLK
P5.4/MCLK
P1.2/TA1
P5.3/UCB1CLK/UCA1STE
P5.2/UCB1SOMI/UCB1SCL
P5.1/UCB1SIMO/UCB1SDA
P5.0/UCB1STE/UCA1CLK
P4.7/TBCLK
P1.3/TA2
P1.4/SMCLK
P1.5/TA0
P1.6/TA1
P1.7/TA2
P4.6/TB6
P2.0/ACLK/CA2
P4.5/TB5
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
pin designation, MSP430F241x, 64-pin package
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DVCC1
P6.3/A3
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P5.4/MCLK
2
P5.3/UCB1CLK/UCA1STE
P5.2/UCB1SOMI/UCB1SCL
P5.1/UCB1SIMO/UCB1SDA
P5.0/UCB1STE/UCA1CLK
P4.7/TBCLK
P6.4/A4
3
P6.5/A5
4
P6.6/A6
5
P6.7/A7/SVSIN
VREF+
6
7
P4.6/TB6
64-pin
PM PACKAGE
(TOP VIEW)
XIN
8
P4.5/TB5
XOUT
9
P4.4/TB4
VeREF+
10
11
12
13
14
15
16
P4.3/TB3
VREF-/VeREF-
P1.0/TACLK/CAOUT
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P4.2/TB2
P4.1/TB1
P4.0/TB0
P3.7/UCA1RXD/UCA1SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.5/UCA0RXD/UCA0SOMI
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
pin designation, MSP430F261x, 80-pin package
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DVCC1
P6.3/A3
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P7.6
2
P7.5
P6.4/A4
3
P7.4
P6.5/A5/DAC1
P6.6/A6/DAC0
P6.7/A7/DAC1/SVSIN
VREF+
4
P7.3
5
P7.2
6
P7.1
7
P7.0
XIN
8
DVSS2
XOUT
9
DVCC2
80-pin
PN PACKAGE
(TOP VIEW)
VeREF+/DAC0
10
11
12
13
14
15
16
17
18
19
20
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
V
REF-/VeREF-
P1.0/TACLK/CAOUT
P1.1/TA0
P5.5/SMCLK
P5.4/MCLK
P1.2/TA1
P5.3/UCB1CLK/UCA1STE
P5.2/UCB1SOMI/UCB1SCL
P5.1/UCB1SIMO/UCB1SDA
P5.0/UCB1STE/UCA1CLK
P4.7/TBCLK
P1.3/TA2
P1.4/SMCLK
P1.5/TA0
P1.6/TA1
P1.7/TA2
P4.6/TB6
P2.0/ACLK/CA2
P4.5/TB5
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
pin designation, MSP430F261x, 64-pin package
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DVCC1
P6.3/A3
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P5.4/MCLK
2
P5.3/UCB1CLK/UCA1STE
P5.2/UCB1SOMI/UCB1SCL
P5.1/UCB1SIMO/UCB1SDA
P5.0/UCB1STE/UCA1CLK
P4.7/TBCLK
P6.4/A4
3
P6.5/A5/DAC1
P6.6/A6/DAC0
P6.7/A7/DAC1/SVSIN
VREF+
4
5
6
7
P4.6/TB6
64-pin
PM PACKAGE
(TOP VIEW)
XIN
8
P4.5/TB5
XOUT
9
P4.4/TB4
VeREF+/DAC0
10
11
12
13
14
15
16
P4.3/TB3
V
REF-/VeREF-
P4.2/TB2
P1.0/TACLK/CAOUT
P1.1/TA0
P4.1/TB1
P4.0/TB0
P1.2/TA1
P3.7/UCA1RXD/UCA1SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.5/UCA0RXD/UCA0SOMI
P1.3/TA2
P1.4/SMCLK
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
functional block diagram, MSP430F241x, 80-pin package
XIN/
XOUT/
P3.x/P4.x
P5.x/P6.x
4x8
DVCC1/2 DVSS1/2
AVCC
AVSS
P1.x/P2.x
2x8
P7.x/P8.x
2x8/
1x16
XT2IN XT2OUT
2
2
ACLK
Oscillators
Basic Clock
System+
Ports
P1/P2
Ports
P3/P4
P5/P6
Ports
P7/P8
Flash
RAM
USCI A0
UART/
LIN,
ADC12
12-Bit
SMCLK
120kB
116kB
92kB
4kB
8kB
8kB
4kB
IrDA, SPI
2x8 I/O
Interrupt
capability
2x8/1x16
I/O
8
4x8 I/O
MCLK
USCI B0
SPI, I2C
Channels
92kB
16MHz
MAB
CPU
1MB
incl. 16
Registers
MDB
Hardware
Multiplier
Timer_B7
USCI A1
UART/
LIN,
Brownout
Protection
Emulation
Watchdog
WDT+
Timer_A3
Comp_A+
7 CC
Registers,
Shadow
Reg
MPY,
MPYS,
MAC,
IrDA, SPI
3 CC
Registers
8
JTAG
Interface
SVS,
SVM
15-Bit
Channels
USCI B1
SPI, I2C
MACS
RST/NMI
functional block diagram, MSP430F241x, 64-pin package
P3.x/P4.x
P5.x/P6.x
XIN/ XOUT/
XT2IN XT2OUT
DVCC
Flash
DVSS
AVCC
AVSS
P1.x/P2.x
2x8
4x8
2
2
ACLK
Oscillators
Basic Clock
System+
RAM
Ports
P1/P2
Ports
P3/P4
P5/P6
USCI A0
ADC12
12-Bit
UART/
LIN,
SMCLK
120kB
116kB
92kB
4kB
8kB
8kB
4kB
IrDA, SPI
2x8 I/O
Interrupt
capability
8
4x8 I/O
MCLK
USCI B0
SPI, I2C
Channels
92kB
16MHz
CPU
MAB
1MB
incl. 16
Registers
MDB
Hardware
Multiplier
Timer_B7
USCI A1
UART/
LIN,
Brownout
Protection
Emulation
Watchdog
WDT+
Timer_A3
Comp_A+
7 CC
Registers,
Shadow
Reg
MPY,
MPYS,
MAC,
IrDA, SPI
3 CC
Registers
8
JTAG
Interface
SVS,
SVM
15-Bit
Channels
USCI B1
SPI, I2C
MACS
RST/NMI
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
functional block diagram, MSP430F261x, 80-pin package
XIN/
XOUT/
P3.x/P4.x
P5.x/P6.x
DVCC1/2 DVSS1/2
AVCC
AVSS
P1.x/P2.x
2x8
P7.x/P8.x
2x8/
1x16
XT2IN XT2OUT
2
2
4x8
ACLK
Flash
RAM
DAC12
12-Bit
Oscillators
Basic Clock
System+
Ports
P1/P2
Ports
P3/P4
P5/P6
Ports
P7/P8
USCI A0
UART/
LIN,
ADC12
12-Bit
SMCLK
120kB
116kB
92kB
92kB
56kB
4kB
8kB
8kB
4kB
4kB
2
IrDA, SPI
2x8 I/O
Interrupt
capability
2x8/1x16
I/O
8
Channels
Voltage
Out
4x8 I/O
MCLK
USCI B0
SPI, I2C
Channels
16MHz
MAB
CPU
1MB
incl. 16
Registers
MDB
Hardware
Multiplier
Timer_B7
USCI A1
UART/
LIN,
Brownout
Protection
DMA
Controller
Emulation
Watchdog
WDT+
Timer_A3
Comp_A+
7 CC
Registers,
Shadow
Reg
MPY,
MPYS,
MAC,
IrDA, SPI
3 CC
Registers
8
JTAG
Interface
SVS,
SVM
3
15-Bit
Channels
USCI B1
SPI, I2C
Channels
MACS
RST/NMI
functional block diagram, MSP430F261x, 64-pin package
XIN/
XOUT/
P3.x/P4.x
P5.x/P6.x
DVCC
DVSS
AVCC
AVSS
P1.x/P2.x
XT2IN XT2OUT
2
2
2x8
4x8
ACLK
Flash
RAM
DAC12
12-Bit
Oscillators
Basic Clock
System+
Ports
P1/P2
Ports
P3/P4
P5/P6
USCI A0
UART/
LIN,
ADC12
12-Bit
SMCLK
120kB
116kB
92kB
92kB
56kB
4kB
8kB
8kB
4kB
4kB
2
IrDA, SPI
2x8 I/O
Interrupt
capability
8
Channels
Voltage
Out
4x8 I/O
MCLK
USCI B0
SPI, I2C
Channels
16MHz
MAB
CPU
1MB
incl. 16
Registers
MDB
Hardware
Multiplier
Timer_B7
USCI A1
UART/
LIN,
Brownout
Protection
DMA
Controller
Emulation
Watchdog
WDT+
Timer_A3
Comp_A+
7 CC
Registers,
Shadow
Reg
MPY,
MPYS,
MAC,
IrDA, SPI
3 CC
Registers
8
JTAG
Interface
SVS,
SVM
3
15-Bit
Channels
USCI B1
SPI, I2C
Channels
MACS
RST/NMI
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
NAME
64
80
PIN
64
62
1
PIN
AV
AV
80
78
1
Analog supply voltage, positive terminal. Supplies only the analog portion of ADC12 and DAC12.
Analog supply voltage, negative terminal. Supplies only the analog portion of ADC12 and DAC12.
Digital supply voltage, positive terminal. Supplies all digital parts.
CC
SS
DV
DV
DV
DV
CC1
63
79
52
53
Digital supply voltage, negative terminal. Supplies all digital parts.
SS1
CC2
SS2
Digital supply voltage, positive terminal. Supplies all digital parts.
Digital supply voltage, negative terminal. Supplies all digital parts.
P1.0/TACLK/
CAOUT
12
12
I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input/Comparator_A output
P1.1/TA0
13
14
15
16
17
18
19
20
13
14
15
16
17
18
19
20
I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit
I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
I/O General-purpose digital I/O pin/SMCLK signal output
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P1.5/TA0
I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output
P1.6/TA1
I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output
P1.7/TA2
I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output
P2.0/ACLK/CA2
I/O General-purpose digital I/O pin/ACLK output/Comparator_A input
P2.1/TAINCLK/
CA3
21
22
21
22
I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK
P2.2/CAOUT/
TA0/CA4
General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output/BSL
I/O
receive/Comparator_A input
P2.3/CA0/TA1
P2.4/CA1/TA2
23
24
23
24
I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input
I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input
General-purpose digital I/O pin/input for external resistor defining the DCO nominal
frequency/Comparator_A input
P2.5/Rosc/CA5
25
25
I/O
P2.6/ADC12CLK/
DMAE0†/CA6
General-purpose digital I/O pin/conversion clock
trigger/Comparator_A input
– 12-bit ADC/DMA channel 0 external
26
27
28
26
27
28
I/O
P2.7/TA0/CA7
I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output/Comparator_A input
I/O General-purpose digital I/O pin/USCI B0 slave transmit enable/USCI A0 clock input/output
P3.0/UCB0STE/
UCA0CLK
P3.1/UCB0SIMO/
UCB0SDA
2
2
29
30
31
32
33
34
35
29
30
31
32
33
34
35
I/O General-purpose digital I/O pin/USCI B0 slave in/master out in SPI mode, SDA I C data in I C mode
P3.2/UCB0SOMI/
UCB0SCL
2
2
I/O General-purpose digital I/O pin/USCI B0 slave out/master in in SPI mode, SCL I C clock in I C mode
P3.3/UCB0CLK/
UCA0STE
I/O General-purpose digital I/O/USCI B0 clock input/output, USCI A0 slave transmit enable
P3.4/UCA0TXD/
UCA0SIMO
General-purpose digital I/O pin/USCIA transmit data output in UART mode, slave data in/master out
I/O
in SPI mode
P3.5/UCA0RXD/
UCA0SOMI
General-purpose digital I/O pin/USCI A0 receive data input in UART mode, slave data out/master
I/O
in in SPI mode
P3.6/UCA1TXD/
UCA1SIMO
General-purpose digital I/O pin/USCI A1 transmit data output in UART mode, slave data in/master
I/O
out in SPI mode
P3.7/UCA1RXD/
UCA1SOMI
General-purpose digital I/O pin/USCIA1 receive data input in UART mode, slave data out/master
I/O
in in SPI mode
†
MSP430F261x devices only
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Terminal Functions (Continued)
TERMINAL
NO.
I/O
DESCRIPTION
NAME
P4.0/TB0
64
80
PIN
36
37
38
39
40
41
42
43
PIN
36
37
38
39
40
41
42
43
I/O General-purpose digital I/O pin/Timer_B, capture: CCI0A/B input, compare: Out0 output
I/O General-purpose digital I/O pin/Timer_B, capture: CCI1A/B input, compare: Out1 output
I/O General-purpose digital I/O pin/Timer_B, capture: CCI2A/B input, compare: Out2 output
I/O General-purpose digital I/O pin/Timer_B, capture: CCI3A/B input, compare: Out3 output
I/O General-purpose digital I/O pin/Timer_B, capture: CCI4A/B input, compare: Out4 output
I/O General-purpose digital I/O pin/Timer_B, capture: CCI5A/B input, compare: Out5 output
I/O General-purpose digital I/O pin/Timer_B, capture: CCI6A input, compare: Out6 output
I/O General-purpose digital I/O pin/Timer_B, clock signal TBCLK input
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
P4.5/TB5
P4.6/TB6
P4.7/TBCLK
P5.0/UCB1STE/
UCA1CLK
44
45
46
47
44
45
46
47
I/O General-purpose digital I/O pin/USCI B1 slave transmit enable/USCI A1 clock input/output
P5.1/UCB1SIMO/
UCB1SDA
2
2
I/O General-purpose digital I/O pin/USCI B1slave in/master out in SPI mode, SDA I C data in I C mode
P5.2/UCB1SOMI/
UCB1SCL
2
2
I/O General-purpose digital I/O pin/USCI B1slave out/master in in SPI mode, SCL I C clock in I C mode
P5.3/UCB1CLK/
UCA1STE
I/O General-purpose digital I/O/USCI B1 clock input/output, USCI A1 slave transmit enable
P5.4/MCLK
P5.5/SMCLK
P5.6/ACLK
48
49
50
48
49
50
I/O General-purpose digital I/O pin/main system clock MCLK output
I/O General-purpose digital I/O pin/submain system clock SMCLK output
I/O General-purpose digital I/O pin/auxiliary clock ACLK output
P5.7/TBOUTH/
SVSOUT
General-purpose digital I/O pin/switch all PWM digital output ports to high impedance -- Timer_B
TB0 to TB6/SVS comparator output
51
51
I/O
P6.0/A0
P6.1/A1
P6.2/A2
P6.3/A3
P6.4/A4
59
60
61
2
75
76
77
2
I/O General-purpose digital I/O pin/analog input A0 – 12-bit ADC
I/O General-purpose digital I/O pin/analog input A1 – 12-bit ADC
I/O General-purpose digital I/O pin/analog input A2 – 12-bit ADC
I/O General-purpose digital I/O pin/analog input A3 – 12-bit ADC
I/O General-purpose digital I/O pin/analog input A4 – 12-bit ADC
I/O General-purpose digital I/O pin/analog input A5 – 12-bit ADC/DAC12.1 output
I/O General-purpose digital I/O pin/analog input A6 – 12-bit ADC/DAC12.0 output
3
3
†
P6.5/A5/DAC1
4
4
†
P6.6/A6/DAC0
5
5
†
P6.7/A7/DAC1 /
6
6
I/O General-purpose digital I/O pin/analog input a7 – 12-bit ADC/DAC12.1 output/SVS input
SVSIN
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
P8.0
P8.1
P8.2
P8.3
54
55
56
57
58
59
60
61
62
63
64
65
I/O General-purpose digital I/O pin
I/O General-purpose digital I/O pin
I/O General-purpose digital I/O pin
I/O General-purpose digital I/O pin
I/O General-purpose digital I/O pin
I/O General-purpose digital I/O pin
I/O General-purpose digital I/O pin
I/O General-purpose digital I/O pin
I/O General-purpose digital I/O pin
I/O General-purpose digital I/O pin
I/O General-purpose digital I/O pin
I/O General-purpose digital I/O pin
†
MSP430F261x devices only
10
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Terminal Functions (Continued)
TERMINAL
NO.
I/O
DESCRIPTION
NAME
64
80
PIN
PIN
P8.4
P8.5
66
67
68
I/O General-purpose digital I/O pin
I/O General-purpose digital I/O pin
P8.6/XT2OUT
O
General-purpose digital I/O pin/Output terminal of crystal oscillator XT2
General-purpose digital I/O pin/Input port for crystal oscillator XT2. Only standard crystals can be
connected.
P8.7/XT2IN
69
I
XT2OUT
XT2IN
52
53
58
57
55
54
56
10
7
O
I
Output terminal of crystal oscillator XT2
Input port for crystal oscillator XT2
RST/NMI
TCK
74
73
71
70
72
10
7
I
Reset input, nonmaskable interrupt input port, or bootstrap loader start (in flash devices).
Test clock (JTAG). TCK is the clock input port fordevice programming test and bootstrap loaderstart.
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
I
TDI/TCLK
TDO/TDI
TMS
I
I/O Test data output port. TDO/TDI data output or programming data input terminal.
I
I
Test mode select. TMS is used as an input port for device programming and test.
Input for an external reference voltage/DAC12.0 output
†
Ve
/DAC0
REF+
V
O
Output of positive terminal of the reference voltage in the ADC12
REF+
Negative terminal for the reference voltage for both sources, the internal reference voltage, or an
external applied reference voltage
V
/Ve
11
11
I
REF--
REF--
XIN
8
9
8
9
I
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
Output port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT
O
†
MSP430F261x devices only
11
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
short-form description
CPU
Program Counter
Stack Pointer
PC/R0
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
R4
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
R5
R6
R7
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator, respectively. The
remaining registers are general-purpose
registers.
R8
R9
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
R10
R11
instruction set
R12
R13
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
R14
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
e.g., ADD R4,R5
R4 + R5 ------> R5
e.g., CALL
e.g., JNE
R8
PC ---->(TOS), R8----> PC
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
Register
S
D
SYNTAX
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
OPERATION
D D
D D
MOV Rs,Rd
R10 ----> R11
Indexed
MOV X(Rn),Y(Rm)
MOV EDE,TONI
M(2+R5)----> M(6+R6)
M(EDE) ----> M(TONI)
M(MEM) ----> M(TCDAT)
M(R10) ----> M(Tab+R6)
Symbolic (PC relative) D D
Absolute
D D MOV &MEM,&TCDAT
Indirect
D
D
D
MOV @Rn,Y(Rm)
MOV @Rn+,Rm
MOV #X,TONI
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
Indirect
autoincrement
M(R10) ----> R11
R10 + 2----> R10
Immediate
#45 ----> M(TONI)
NOTE: S = source
D = destination
12
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D
Active mode (AM)
-- All clocks are active.
Low-power mode 0 (LPM0)
D
-- CPU is disabled.
ACLK and SMCLK remain active. MCLK is disabled.
D
D
Low-power mode 1 (LPM1)
-- CPU is disabled.
ACLK and SMCLK remain active. MCLK is disabled.
DCO’s dc-generator is disabled if DCO not used in active mode.
Low-power mode 2 (LPM2)
-- CPU is disabled.
MCLK and SMCLK are disabled.
DCO’s dc-generator remains enabled.
ACLK remains active.
D
D
Low-power mode 3 (LPM3)
-- CPU is disabled.
MCLK and SMCLK are disabled.
DCO’s dc-generator is disabled.
ACLK remains active.
Low-power mode 4 (LPM4)
-- CPU is disabled.
ACLK is disabled.
MCLK and SMCLK are disabled.
DCO’s dc-generator is disabled.
Crystal oscillator is stopped.
13
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
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interrupt vector addresses
The interruptvectors and the power-up starting address are located in theaddress range0x0FFFFto 0x0FFC0.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. If the reset
vector (0x0FFFE) contains 0xFFFF (e.g., flash is not programmed), the CPU enters LPM4 after power-up.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-up
External Reset
PORIFG
WDTIFG
Watchdog
Flash Key Violation
PC out of range (see Note 1)
RSTIFG
KEYV (see Note 2)
Reset
0x0FFFE
0x0FFFC
31, highest
30
NMI
Oscillator Fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG (see Notes 2 and 6)
(Non)maskable
(Non)maskable
(Non)maskable
TBCCR0 CCIFG
(see Note 3)
Timer_B7
Timer_B7
Maskable
Maskable
0x0FFFA
0x0FFF8
29
28
TBCCR1 to TBCCR6 CCIFGs, TBIFG
(see Notes 2 and 3)
Comparator_A+
Watchdog timer+
Timer_A3
CAIFG
WDTIFG
Maskable
Maskable
Maskable
0x0FFF6
0x0FFF4
0x0FFF2
27
26
25
TACCR0 CCIFG (see Note 3)
TACCR1 CCIFG
TACCR2 CCIFG
TAIFG (see Notes 2 and 3)
Timer_A3
Maskable
Maskable
0x0FFF0
24
USCI_A0/USCI_B0 receive
USCI_B0 I2C status
UCA0RXIFG, UCB0RXIFG
(see Notes 2 and 4)
0x0FFEE
0x0FFEC
23
22
USCI_A0/USCI_B0 transmit
USCI_B0 I2C receive/transmit
UCA0TXIFG, UCB0TXIFG
(see Note 2 and 4)
Maskable
Maskable
ADC12
ADC12IFG (see Notes 2 and 3)
0x0FFEA
0x0FFE8
0x0FFE6
0x0FFE4
21
20
19
18
I/O port P2 (eight flags)
I/O port P1 (eight flags)
P2IFG.0 to P2IFG.7 (see Notes 2 and 3)
P1IFG.0 to P1IFG.7 (see Notes 2 and 3)
Maskable
Maskable
USCI_A0/USCI_B1 receive
USCI_B1 I2C status
UCA1RXIFG, UCB1RXIFG
(see Notes 2 and 4)
Maskable
Maskable
Maskable
Maskable
0x0FFE2
0x0FFE0
0x0FFDE
0x0FFDC
17
16
15
14
USCI_A1/USCI_B1 transmit
USCI_B1 I2C receive/transmit
UCA1TXIFG, UCB1TXIFG
(see Notes 2 and 5)
DMA0IFG, DMA1IFG, DMA2IFG
(see Notes 2 and 3)
DMA
DAC12
DAC12_0IFG, DAC12_1IFG
(see Notes 2 and 3)
0x0FFDA to
0x0FFC0
13 to 0,
lowest
Reserved (see Notes 7 and 8)
Reserved
NOTES: 1. A reset is executed if the CPU tries to fetch instructions from within the module register memory address range (0x00000 to 0x001FF)
or from within unused address ranges.
2. Multiple source flags.
3. Interrupt flags are located in the module.
4. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
5. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
6. (Non)maskable: The individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot.
7. The address 0x0FFBE is used as bootstrap loader security key (BSLSKEY).
A 0x0AA55 at this location disables the BSL completely.
A zero disables the erasure of the flash if an invalid password is supplied.
8. The interrupt vectors at addresses 0x0FFDA to 0x0FFC0 are not used in this device and can be used for regular program code if
necessary.
14
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
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special function registers
Most interrupt enable bits are collected in the lowest address space. Special-function register bits not allocated
to a functional purpose are not physically present in the device. This arrangement provides simple software
access.
interrupt enable 1 and 2
Address
00h
7
6
5
4
3
2
1
0
ACCVIE
rw--0
NMIIE
rw--0
OFIE
rw--0
WDTIE
rw--0
Interrupt Enable Register 1
WDTIE
Watchdog timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as general-purpose timer.
OFIE
Oscillator-fault-interrupt enable
NMIIE
ACCVIE
Nonmaskable-interrupt enable
Flash memory access violation interrupt enable
Address
01h
7
6
5
4
3
2
1
0
UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE
rw--0 rw--0 rw--0 rw--0
Interrupt Enable Register 2
UCA0RXIE
UCA0TXIE
UCB0RXIE
UCB0TXIE
USCI_A0 receive-interrupt enable
USCI_A0 transmit-interrupt enable
USCI_B0 receive-interrupt enable
USCI_B0 transmit-interrupt enable
15
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
interrupt flag register 1 and 2
Address
02h
7
6
5
4
3
2
1
0
NMIIFG
rw--0
RSTIFG
rw--(0)
PORIFG
rw--(1)
OFIFG
rw--1
WDTIFG
rw--(0)
Interrupt Flag Register 1
Set on watchdog timer overflow or security key violation
WDTIFG
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode
OFIFG
Flag set on oscillator fault7
PORIFG
RSTIFG
Power--on interrupt flag. Set on VCC power up.
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset
on VCC power up.
NMIIFG
Set via RST/NMI pin
Address
03h
7
6
5
4
3
2
1
0
UCB0TX
IFG
UCB0RX
IFG
UCA0TX
IFG
UCA0RX
IFG
rw--1
rw--0
rw--1
rw--0
Interrupt Flag Register 2
UCA0RXIFG USCI_A0 receive-interrupt flag
UCA0TXIFG USCI_A0 transmit-interrupt flag
UCB0RXIFG USCI_B0 receive-interrupt flag
UCB0TXIFG
USCI_B0 transmit-interrupt flag
Legend
rw:
Bit can be read and written .
rw-0,1:
rw-(0,1)
Bit can be read and written . It is Reset or Set by PUC .
Bit can be read and written . It is Reset or Set by POR .
SFR bit is not present in device .
16
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
memory organization
MSP430F2416
MSP430F2616
MSP430F2417
MSP430F2617
Memory
Size
92KB
92KB
Main: interrupt vector
Main: code memory
Flash
Flash
0x0FFFF -- 0x0FFC0
0x18FFF -- 0x02100
0x0FFFF -- 0x0FFC0
0x19FFF -- 0x03100
RAM (total)
Extended
Mirrored
Size
Size
Size
4kB
8kB
0x020FF -- 0x01100
2kB
0x020FF -- 0x01900
2kB
0x030FF -- 0x01100
6kB
0x030FF -- 0x01900
2kB
0x018FF -- 0x01100
0x018FF -- 0x01100
Information memory
Boot memory
Size
Flash
256 Byte
0x010FF -- 0x01000
256 Byte
0x010FF -- 0x01000
Size
1KB
1KB
ROM
0x00FFF -- 0x00C00
0x00FFF -- 0x00C00
RAM (mirrored at
Size
2KB
2KB
0x18FF to 0x01100)
0x009FF -- 0x00200
0x009FF -- 0x00200
Peripherals
16-bit
8-bit
8-bit SFR
0x001FF -- 0x00100
0x000FF -- 0x00010
0x0000F -- 0x00000
0x001FF -- 0x00100
0x000FF -- 0x00010
0x0000F -- 0x00000
MSP430F2618
MSP430F2418
MSP430F2619
MSP430F2419
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
116KB
0x0FFFF -- 0x0FFC0
0x1FFFF -- 0x03100
120KB
0x0FFFF -- 0x0FFC0
0x1FFFF -- 0x02100
RAM (total)
Extended
Mirrored
Size
Size
Size
8kB
4kB
0x030FF -- 0x01100
6kB
0x030FF -- 0x01900
2kB
0x020FF -- 0x01100
2kB
0x020FF -- 0x01900
2kB
0x018FF -- 0x01100
0x018FF -- 0x01100
Information memory
Boot memory
Size
Flash
256 Byte
0x010FF -- 0x01000
256 Byte
0x010FF -- 0x01000
Size
1KB
1KB
ROM
0x00FFF -- 0x00C00
0x00FFF -- 0x00C00
RAM (mirrored at
Size
2KB
2KB
0x18FF to 0x01100)
0x009FF -- 0x00200
0x009FF -- 0x00200
Peripherals
16-bit
8-bit
8-bit SFR
0x001FF -- 0x00100
0x000FF -- 0x00010
0x0000F -- 0x00000
0x001FF -- 0x00100
0x000FF -- 0x00010
0x0000F -- 0x00000
bootstrap loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access
to the MSP430 memory via the BSL is protected by a user-defined password. For complete description of the
features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap
Loader, literature number SLAA089.
BSL Function
Data Transmit
Data Receive
PM, RTD Package Pins
13 - P1.1
22 - P2.2
17
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MIXED SIGNAL MICROCONTROLLER
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flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D
Flash memory has n segments of main memory and four segments of information memory (A to D) of 64
bytes each. Each segment in main memory is 512 bytes in size.
D
D
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
D
D
Segment A contains calibration data. After reset, segment A is protected against programming or erasing.
It can be unlocked, but care should be taken not to erase this segment if the calibration data is required.
Flash content integrity check with marginal read modes
peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User’s Guide, literature number
SLAU144.
DMA controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to
or from a peripheral.
oscillator and system clock
The clock system in the MSP430x241x and MSP43x261x family of devices is supported by the basic clock
module that includes support for a 32768-Hz watch crystal oscillator, an internal very low power, low frequency
oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock
module is designed to meet the requirements of both low system cost and low-power consumption. The internal
DCO provides a fast turn-on clock source and stabilizes in less than 1 μs. The basic clock module provides the
following clock signals:
D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high frequency crystal, or a very
low-power LF oscillator
D
D
Main clock (MCLK), the system clock used by the CPU
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules
The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.
18
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calibration data stored in information memory segment A
Calibration data is stored for the DCO and for the ADC12. It is organized in a tag-length-value (TLV) structure.
TAGS USED BY THE ADC CALIBRATION TAGS
NAME
ADDRESS
0x10F6
0x10DA
--
VALUE
0x01
DESCRIPTION
TAG_DCO_30
TAG_ADC12_1
TAG_EMPTY
DCO frequency calibration at VCC = 3 V and T = 25°C at calibration
A
0x10
ADC12_1 calibration tag
0xFE
Identifier for empty memory areas
LABELS USED BY THE ADC CALIBRATION TAGS
CONDITION AT CALIBRATION / DESCRIPTION
LABEL
SIZE
word
word
word
word
word
word
word
word
byte
byte
byte
byte
byte
byte
byte
byte
ADDRESS OFFSET
0x000E
0x000C
0x000A
0x0008
CAL_ADC_25T85 INCHx = 0x1010; REF2_5 = 1, T = 85°C
A
CAL_ADC_25T30 INCHx = 0x1010; REF2_5 = 1, T = 30°C
A
CAL_ADC_25VREF_FACTOR REF2_5 = 1, T = 30°C
A
CAL_ADC_15T85 INCHx = 0x1010; REF2_5 = 0, T = 85°C
A
CAL_ADC_15T30 INCHx = 0x1010; REF2_5 = 0, T = 30°C
0x0006
A
CAL_ADC_15VREF_FACTOR REF2_5 = 0, T = 30°C
0x0004
A
CAL_ADC_OFFSET External V
CAL_ADC_GAIN_FACTOR External V
CAL_BC1_1MHz --
= 1.5 V, f
= 1.5 V, f
= 5 MHz
= 5 MHz
0x0002
REF
REF
ADC12CLK
ADC12CLK
0x0000
0x0007
CAL_DCO_1MHz --
0x0006
CAL_BC1_8MHz --
0x0005
CAL_DCO_8MHz --
0x0004
CAL_BC1_12MHz --
0x0003
CAL_DCO_12MHz --
0x0002
CAL_BC1_16MHz --
0x0001
CAL_DCO_16MHz --
0x0000
brownout, supply voltage supervisor (SVS)
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The SVS circuitry detects if the supply voltage drops below a user selectable level and supports
both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the
device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must ensure that the default DCO settings are not changed until
VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min)
.
19
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MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
digital I/O
There are up to eight 8-bit I/O ports implemented—ports P1 through P8:
D
D
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Each I/O has an individually programmable pullup/pulldown resistor.
Ports P7/P8 can be accessed word wise.
watchdog timer+ (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
hardware multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16×16,
16×8, 8×16, and 8×8 bit operations. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
universal serial communication interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 pin or 4 pin) or I2C, and asynchronous combination protocols such as
UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.
The USCI A module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, and IrDA.
The USCI B module provides support for SPI (3 pin or 4 pin) and I2C.
20
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_A3 SIGNAL CONNECTIONS
INPUT PIN
NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE
BLOCK
MODULE OUTPUT
SIGNAL
OUTPUT PIN NUMBER
12 - P1.0
TACLK
ACLK
TACLK
ACLK
Timer
CCR0
CCR1
NA
SMCLK
TAINCLK
TA0
SMCLK
INCLK
CCI0A
CCI0B
GND
21 - P2.1
13 - P1.1
22 - P2.2
13 - P1.1
17 - P1.5
27 - P2.7
TA0
TA0
DV
DV
SS
CC
V
CC
14 - P1.2
TA1
CAOUT (internal)
CCI1A
CCI1B
GND
14 - P1.2
18 - P1.6
DV
23 - P2.3
SS
CC
TA1
TA2
DV
V
ADC12 (internal)
DAC12_0 (internal)
DAC12_1 (internal)
15 - P1.3
CC
15 - P1.3
TA2
ACLK (internal)
CCI2A
CCI2B
GND
19 - P1.7
CCR2
DV
24 - P2.4
SS
CC
DV
V
CC
21
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
timer_B7
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
†
TIMER_B3/B7 SIGNAL CONNECTIONS
INPUT PIN
NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE
BLOCK
MODULE OUTPUT
SIGNAL
OUTPUT PIN NUMBER
43 - P4.7
TBCLK
ACLK
SMCLK
TBCLK
TB0
TBCLK
ACLK
Timer
CCR0
CCR1
CCR2
CCR3
CCR4
CCR5
CCR6
NA
SMCLK
INCLK
CCI0A
CCI0B
GND
43 - P4.7
36 - P4.0
36 - P4.0
36 - P4.0
TB0
ADC12 (internal)
TB0
TB1
TB2
TB3
TB4
TB5
TB6
DV
DV
SS
CC
V
CC
37 - P4.1
37 - P4.1
TB1
TB1
CCI1A
CCI1B
GND
37 - P4.1
ADC12 (internal)
DV
DV
SS
CC
V
CC
38 - P4.2
38 - P4.2
TB2
TB2
CCI2A
CCI2B
GND
38 - P4.2
DAC_0(internal)
DAC_1(internal)
DV
DV
SS
CC
V
CC
39 - P4.3
39 - P4.3
TB3
TB3
CCI3A
CCI3B
GND
39 - P4.3
40 - P4.4
41 - P4.5
42 - P4.6
DV
DV
SS
CC
V
CC
40 - P4.4
40 - P4.4
TB4
TB4
CCI4A
CCI4B
GND
DV
SS
CC
DV
V
CC
41 - P4.5
41 - P4.5
TB5
TB5
CCI5A
CCI5B
GND
DV
DV
SS
CC
V
CC
42 - P4.6
TB6
ACLK (internal)
CCI6A
CCI6B
GND
DV
DV
SS
CC
V
CC
22
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
comparator_A+
The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
ADC12
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without
any CPU intervention.
DAC12
The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8-bit or 12-bit mode
and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may
be grouped together for synchronous operation.
23
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
peripheral file map
PERIPHERAL FILE MAP
†
DMA
DMA channel 2 transfer size
DMA2SZ
0x01F2
0x01EE
0x01EA
0x01E8
0x01E6
0x01E2
0x01DE
0x01DC
0x01DA
0x01D6
0x01D2
0x01D0
0x0126
0x0124
0x0122
0x01CA
0x01C2
0x01C8
0x01C0
0x01A8
0x01A6
0x01A4
0x01A2
0x01A0
DMA channel 2 destination address
DMA channel 2 source address
DMA channel 2 control
DMA channel 1 transfer size
DMA channel 1 destination address
DMA channel 1 source address
DMA channel 1 control
DMA channel 0 transfer size
DMA channel 0 destination address
DMA channel 0 source address
DMA channel 0 control
DMA module interrupt vector word
DMA module control 1
DMA module control 0
DAC12_1 data
DMA2DA
DMA2SA
DMA2CTL
DMA1SZ
DMA1DA
DMA1SA
DMA1CTL
DMA0SZ
DMA0DA
DMA0SA
DMA0CTL
DMAIV
DMACTL1
DMACTL0
DAC12_1DAT
DAC12_1CTL
DAC12_0DAT
DAC12_0CTL
ADC12IV
†
DAC12
ADC12
DAC12_1 control
DAC12_0 data
DAC12_0 control
Interrupt-vector-word register
Inerrupt-enable register
Inerrupt-flag register
ADC12IE
ADC12IFG
ADC12CTL1
ADC12CTL0
Control register 1
Control register 0
Conversion memory 15
Conversion memory 14
Conversion memory 13
Conversion memory 12
Conversion memory 11
Conversion memory 10
Conversion memory 9
Conversion memory 8
Conversion memory 7
Conversion memory 6
Conversion memory 5
Conversion memory 4
Conversion memory 3
Conversion memory 2
Conversion memory 1
Conversion memory 0
ADC12MEM15 0x015E
ADC12MEM14 0x015C
ADC12MEM13 0x015A
ADC12MEM12 0x0158
ADC12MEM11 0x0156
ADC12MEM10 0x0154
ADC12MEM9
ADC12MEM8
ADC12MEM7
ADC12MEM6
ADC12MEM5
ADC12MEM4
ADC12MEM3
ADC12MEM2
ADC12MEM1
ADC12MEM0
0x0152
0x0150
0x014E
0x014C
0x014A
0x0148
0x0146
0x0144
0x0142
0x0140
†
MSP430F261x devices only
24
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
PERIPHERAL FILE MAP (CONTINUED)
ADC12
(continued)
ADC memory-control register15
ADC memory-control register14
ADC memory-control register13
ADC memory-control register12
ADC memory-control register11
ADC memory-control register10
ADC memory-control register9
ADC memory-control register8
ADC memory-control register7
ADC memory-control register6
ADC memory-control register5
ADC memory-control register4
ADC memory-control register3
ADC memory-control register2
ADC memory-control register1
ADC memory-control register0
Capture/compare register 6
Capture/compare register 5
Capture/compare register 4
Capture/compare register 3
Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_B register
ADC12MCTL15 0x008F
ADC12MCTL14 0x008E
ADC12MCTL13 0x008D
ADC12MCTL12 0x008C
ADC12MCTL11 0x008B
ADC12MCTL10 0x008A
ADC12MCTL9
ADC12MCTL8
ADC12MCTL7
ADC12MCTL6
ADC12MCTL5
ADC12MCTL4
ADC12MCTL3
ADC12MCTL2
ADC12MCTL1
ADC12MCTL0
TBCCR6
0x0089
0x0088
0x0087
0x0086
0x0085
0x0084
0x0083
0x0082
0x0081
0x0080
0x019E
0x019C
0x019A
0x0198
0x0196
0x0194
0x0192
0x0190
0x018E
0x018C
0x018A
0x0188
0x0186
0x0184
0x0182
0x0180
0x011E
0x0176
0x0174
0x0172
0x0170
0x016E
0x016C
0x016A
0x0168
0x0166
0x0164
0x0162
0x0160
0x012E
Timer_B7
TBCCR5
TBCCR4
TBCCR3
TBCCR2
TBCCR1
TBCCR0
TBR
Capture/compare control 6
Capture/compare control 5
Capture/compare control 4
Capture/compare control 3
Capture/compare control 2
Capture/compare control 1
Capture/compare control 0
Timer_B control
TBCCTL6
TBCCTL5
TBCCTL4
TBCCTL3
TBCCTL2
TBCCTL1
TBCCTL0
TBCTL
Timer_B interrupt vector
Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_A register
TBIV
Timer_A3
TACCR2
TACCR1
TACCR0
TAR
Reserved
Reserved
Reserved
Reserved
Capture/compare control 2
Capture/compare control 1
Capture/compare control 0
Timer_A control
TACCTL2
TACCTL1
TACCTL0
TACTL
Timer_A interrupt vector
TAIV
25
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
PERIPHERAL FILE MAP (CONTINUED)
Hardware
Multiplier
Sum extend
SUMEXT
0x013E
0x013C
0x013A
0x0138
0x0136
0x0134
0x0132
0x0130
0x01BE
0x012C
0x012A
0x0128
0x0120
0x005D
0x0067
0x0066
0x0065
0x0064
0x0063
0x0062
0x0061
0x0060
0x005F
0x005E
0x006F
0x006E
0x006D
0x006C
0x006B
0x006A
0x0069
0x0068
0x011A
0x0118
0x00CD
0x00D7
0x00D6
0x00D5
0x00D4
0x00D3
0x00D2
0x00D1
0x00D0
0x00CF
0x00CE
Result high word
RESHI
Result low word
RESLO
Second operand
OP2
Multiply signed +accumulate/operand1
Multiply+accumulate/operand1
Multiply signed/operand1
Multiply unsigned/operand1
Flash control 4
MACS
MAC
MPYS
MPY
Flash
FCTL4
Flash control 3
FCTL3
Flash control 2
FCTL2
Flash control 1
FCTL1
Watchdog
Watchdog Timer control
USCI A0 auto baud rate control
USCI A0 transmit buffer
USCI A0 receive buffer
USCI A0 status
WDTCTL
USCI A0/B0
UCA0ABCTL
UCA0TXBUF
UCA0RXBUF
UCA0STAT
UCA0MCTL
UCA0BR1
UCA0BR0
UCA0CTL1
UCA0CTL0
UCA0IRRCTL
UCA0IRTCLT
UCB0TXBUF
UCB0RXBUF
UCB0STAT
UCB0CIE
UCB0BR1
UCB0BR0
UCB0CTL1
UCB0CTL0
UCB0SA
USCI A0 modulation control
USCI A0 baud rate control 1
USCI A0 baud rate control 0
USCI A0 control 1
USCI A0 control 0
USCI A0 IrDA receive control
USCI A0 IrDA transmit control
USCI B0 transmit buffer
USCI B0 receive buffer
USCI B0 status
USCI B0 I2C Interrupt enable
USCI B0 baud rate control 1
USCI B0 baud rate control 0
USCI B0 control 1
USCI B0 control 0
USCI B0 I2C slave address
USCI B0 I2C own address
USCI A1 auto baud rate control
USCI A1 transmit buffer
USCI A1 receive buffer
USCI A1 status
UCB0OA
USCI A1/B1
UCA1ABCTL
UCA1TXBUF
UCA1RXBUF
UCA1STAT
UCA1MCTL
UCA1BR1
UCA1BR0
UCA1CTL1
UCA1CTL0
UCA1IRRCTL
UCA1IRTCLT
USCI A1 modulation control
USCI A1 baud rate control 1
USCI A1 baud rate control 0
USCI A1 control 1
USCI A1 control 0
USCI A1 IrDA receive control
USCI A1 IrDA transmit control
26
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
PERIPHERAL FILE MAP (CONTINUED)
USCI B1 transmit buffer
USCI A1/B1
(continued)
UCB1TXBUF
UCB1RXBUF
UCB1STAT
UCB1CIE
UCB1BR1
UCB1BR0
UCB1CTL1
UCB1CTL0
UCB1SA
UCB1OA
UC1IE
0x00DF
0x00DE
0x00DD
0x00DC
0x00DB
0x00DA
0x00D9
0x00D8
0x017E
0x017C
0x0006
0x0007
0x005B
0x005A
0x0059
0x0053
0x0058
0x0057
0x0056
0x0055
0x0014
0x003E
0x003C
0x003A
0x0038
0x0015
0x003F
0x003D
0x003B
0x0039
0x0014
0x003E
0x003C
0x003A
0x0038
0x0013
0x0037
0x0036
0x0035
0x0034
0x0012
0x0033
0x0032
0x0031
0x0030
USCI B1 receive buffer
USCI B1 status
USCI B1 I2C Interrupt enable
USCI B1 baud rate control 1
USCI B1 baud rate control 0
USCI B1 control 1
USCI B1 control 0
USCI B1 I2C slave address
USCI B1 I2C own address
USCI A1/B1 interrupt enable
USCI A1/B1 interrupt flag
Comparator_A port disable
Comparator_A control2
Comparator_A control1
Basic clock system control3
Basic clock system control2
Basic clock system control1
DCO clock frequency control
UC1IFG
Comparator_A+
Basic Clock
CAPD
CACTL2
CACTL1
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
Brownout, SVS
SVS control register (reset by brownout signal) SVSCTL
†
Port PA
Port PA resistor enable
Port PA selection
Port PA direction
Port PA output
PAREN
PASEL
PADIR
PAOUT
PAIN
Port PA input
†
Port P8
Port P8 resistor enable
Port P8 selection
Port P8 direction
Port P8 output
P8REN
P8SEL
P8DIR
P8OUT
P8IN
Port P8 input
†
Port P7
Port P7 resistor enable
Port P7 selection
Port P7 direction
Port P7 output
P7REN
P7SEL
P7DIR
P7OUT
P7IN
Port P7 input
Port P6
Port P6 resistor enable
Port P6 selection
Port P6 direction
Port P6 output
P6REN
P6SEL
P6DIR
P6OUT
P6IN
Port P6 input
Port P5
Port P5 resistor enable
Port P5 selection
Port P5 direction
Port P5 output
P5REN
P5SEL
P5DIR
P5OUT
P5IN
Port P5 input
†
80-pin devices only
27
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
PERIPHERAL FILE MAP (CONTINUED)
Port P4
Port P3
Port P2
Port P4 selection
P4SEL
P4REN
P4DIR
P4OUT
P4IN
0x001F
0x0011
0x001E
0x001D
0x001C
0x0010
0x001B
0x001A
0x0019
0x0018
0x002F
0x002E
0x002D
0x002C
0x002B
0x002A
0x0029
0x0028
0x0027
0x0026
0x0025
0x0024
0x0023
0x0022
0x0021
0x0020
0x0003
0x0002
0x0001
0x0000
Port P4 resistor enable
Port P4 direction
Port P4 output
Port P4 input
Port P3 resistor enable
Port P3 selection
P3REN
P3SEL
P3DIR
P3OUT
P3IN
Port P3 direction
Port P3 output
Port P3 input
Port P2 resistor enable
Port P2 selection
P2REN
P2SEL
P2IE
Port P2 interrupt enable
Port P2 interrupt-edge select
Port P2 interrupt flag
Port P2 direction
P2IES
P2IFG
P2DIR
P2OUT
P2IN
Port P2 output
Port P2 input
Port P1
Port P1 resistor enable
Port P1 selection
P1REN
P1SEL
P1IE
Port P1 interrupt enable
Port P1 interrupt-edge select
Port P1 interrupt flag
Port P1 direction
P1IES
P1IFG
P1DIR
P1OUT
P1IN
Port P1 output
Port P1 input
Special Functions
SFR interrupt flag2
SFR interrupt flag1
SFR interrupt enable2
SFR interrupt enable1
IFG2
IFG1
IE2
IE1
28
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
absolute maximum ratings (see Note 1)
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4.1 V
Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to VCC + 0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature: Unprogrammed device (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . --55°C to 150°C
Programmed device (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --40°C to 105°C
NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. All voltages referenced to V . The JTAG fuse-blow voltage, V , is allowed to exceed the absolute maximum rating. The voltage
SS
FB
is applied to the TDI/TCLK pin when blowing the JTAG fuse.
3. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification, with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
recommended operating conditions
PARAMETER
MIN
1.8
MAX UNIT
Supply voltage during program execution, V
AV = DV = V (see Note 1)
3.6
3.6
0.0
85
V
V
V
CC
CC
CC
CC
Supply voltage during flash memory programming, V
AV = DV = V (see Note 1)
2.2
CC
CC
CC
CC
SS
Supply voltage, V
AV = DV = V
0.0
SS
SS
SS
I version
-- 4 0
-- 4 0
Operating free-air temperature, T
°C
A
T version
105
V
= 1.8 V,
CC
dc
dc
dc
4.15
12
Duty cycle = 50% ± 10%
V = 2.7 V,
CC
Processor frequency f
(see Notes 2 and 3 and Figure 1)
(maximum MCLK frequency)
SYSYTEM
MHz
Duty cycle = 50% ± 10%
V
≥ 3.3 V,
CC
16
Duty cycle = 50% ± 10%
NOTES: 1. It is recommended to power AV and DV from the same source. A maximum difference of 0.3 V between AV and DV can
CC
CC
CC
CC
be tolerated during power-up.
2. The MSP430 CPU is clocked directly with MCLK.
Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.
3. Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend:
16 MHz
Supply voltage range
during flash memory
programming
12 MHz
Supply voltage range
during program execution
7.5 MHz
4.15 MHz
1.8 V
2.2 V
2.7 V
3.3 V 3.6 V
Supply Voltage --V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V of 2.2 V.
CC
Figure 1. Operating Area
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
active mode supply current into VCC excluding external current (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
T
A
VCC
MIN
TYP
MAX UNIT
f
f
= f
MCLK
= f = 1 MHz,
DCO
SMCLK
-- 4 0 _C to 85_C
105_C
365
395
= 32,768 Hz,
ACLK
2.2 V
Program executes from flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
375
515
525
330
340
460
470
420
μA
560
Active mode (AM)
current (1 MHz)
I
I
AM, 1MHz
-- 4 0 _C to 85_C
105_C
3 V
2.2 V
3 V
595
370
f
f
= f
= f
= 1 MHz,
SMCLK
DCO
MCLK
-- 4 0 _C to 85_C
105_C
= 32,768 Hz,
ACLK
Program executes in RAM,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
390
μA
495
Active mode (AM)
current (1 MHz)
AM, 1MHz
-- 4 0 _C to 85_C
105_C
520
9
f
f
f
= f
=
SMCLK
MCLK
ACLK
-- 4 0 _C to 85_C
105_C
2.1
15
3
= 32,768 Hz/8 = 4,096 Hz,
= 0 Hz,
2.2 V
3 V
DCO
31
μA
11
Active mode (AM) Program executes in flash,
I
I
AM, 4kHz
current (4 kHz)
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCG0 = 1, SCG1 = 0,
OSCOFF = 0
-- 4 0 _C to 85_C
105_C
19
32
86
f
f
= f
= 0 Hz,
= f
≈ 100 kHz,
DCO(0, 0)
MCLK
ACLK
SMCLK
-- 4 0 _C to 85_C
105_C
67
80
84
99
2.2 V
3 V
99
μA
Program executes in flash,
RSELx = 0, DCOx = 0,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 1
Active mode (AM)
current (100 kHz)
AM,100kHz
-- 4 0 _C to 85_C
105_C
107
128
NOTES: 1. All inputs are tied to 0 V or V . Outputs do not source or sink any current.
CC
2. The currents are characterized with a micro crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
typical characteristics -- active mode supply current (into DVCC + AVCC
)
7.0
10.0
T
= 85 °C
= 25 °C
A
f
= 16 MHz
= 12 MHz
DCO
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
T
A
f
DCO
V
= 3 V
CC
T
= 85 °C
= 25 °C
A
f
= 8 MHz
DCO
T
A
V
= 2.2 V
CC
f
= 1 MHz
DCO
1.5
2.0
2.5
3.0
3.5
4.0
0.0
4.0
8.0
12.0
16.0
V
-- Supply Voltage -- V
f
-- DCO Frequency -- MHz
CC
DCO
Figure 2. Active Mode Current vs VCC, TA = 25°C
Figure 3. Active Mode Current vs DCO Frequency
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
low-power mode supply current into VCC excluding external current (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
T
A
VCC
MIN
TYP
MAX UNIT
f
f
f
= 0 MHz,
MCLK
-- 4 0 _C to 85_C
105_C
68
83
= f
= 1 MHz,
SMCLK
DCO
2.2 V
= 32,768 Hz,
Low-power mode 0
(LPM0) current,
see Note 3
83
87
98
μA
105
ACLK
I
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
LPM0, 1MHz
-- 4 0 _C to 85_C
105_C
3 V
100
125
49
f
f
f
= 0MHz,
MCLK
-- 4 0 _C to 85_C
105_C
37
50
40
57
23
35
25
2.2 V
3 V
= f
≈ 100 kHz,
SMCLK
DCO(0, 0)
Low-power mode 0
(LPM0) current,
see Note 3
62
μA
55
= 0 Hz,
I
ACLK
LPM0,
RSELx = 0, DCOx = 0,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 1
f
f
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
100kHz
-- 4 0 _C to 85_C
105_C
73
33
= f
= 0 MHz, f
= 1 MHz,
DCO
MCLK
ACLK
SMCLK
-- 4 0 _C to 85_C
105_C
2.2 V
3 V
= 32,768 Hz,
Low-power mode 2
(LPM2) current,
see Note 4
46
μA
36
I
LPM2
-- 4 0 _C to 85_C
105_C
-- 4 0 °C
25°C
40
0.8
1
55
1.2
1.3
7
2.2 V
3 V
85°C
4.6
14
f
f
= f
= f
= 0 MHz,
SMCLK
DCO
MCLK
Low-power mode 3
(LPM3) current,
see Note 4
105°C
-- 4 0 °C
25°C
24
μA
1.3
= 32,768 Hz,
ACLK
I
LPM3,LFXT1
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
0.9
1.1
5.5
17
1.5
8
85°C
105°C
-- 4 0 °C
25°C
30
1.0
1.0
6.5
0.4
0.5
4.3
14
2.2 V
3 V
85°C
f
f
= f
= f
= 0 MHz,
SMCLK
DCO
MCLK
105°C
-- 4 0 °C
25°C
24
μA
1.2
Low-power mode 3
(LPM3) current,
see Note 4
from internal LF oscillator (VLO),
ACLK
I
LPM3,VLO
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
0.6
0.6
5
1.2
7.5
85°C
105°C
16.5
29.5
NOTES: 1. All inputs are tied to 0 V or V . Outputs do not source or sink any current.
CC
2. The currents are characterized with a micro crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
3. Current for Brownout and WDT+ is included. The WDT+ is clocked by SMCLK.
4. Current for Brownout and WDT+ is included. The WDT+ is clocked by ACLK.
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
low-power mode supply current into VCC excluding external current (see Notes 1 and 2) (continued)
PARAMETER
TEST CONDITIONS
T
VCC
MIN
TYP
0.1
0.1
4
MAX UNIT
A
-- 4 0 °C
25°C
0.5
0.5
Low-power mode 4
(LPM4) current,
see Note 3
f
f
= f
MCLK
= f = 0 MHz,
SMCLK
DCO
= 0 Hz,
ACLK
I
I
2.2 V
μA
LPM4
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
85°C
6
105°C
13
23
0.5
0.5
-- 4 0 °C
25°C
0.2
0.2
4.7
14
Low-power mode 4
(LPM4) current,
see Note 3
f
f
= f
= f
= 0 MHz,
SMCLK
DCO
MCLK
= 0 Hz,
ACLK
3 V
μA
LPM4
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
85°C
7
105°C
24
NOTES: 1. All inputs are tied to 0 V or V . Outputs do not source or sink any current.
CC
2. The currents are characterized with a micro crystal CC4V--T1A SMD crystal with a load capacitance of 9 pf. The internal and external
load capacitance is chosen to closely match the required 9 pf.
3. Current for Brownout included.
typical characteristics -- LPM4 current
16.0
15.0
14.0
13.0
12.0
11.0
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
Vcc = 3.6V
Vcc = 3.0V
Vcc = 2.2V
Vcc = 1.8V
--40.0 --20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0
T
A
-- Temperature -- °C
Figure 4. ILPM4 -- LPM4 Current vs Temperature
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Schmitt-trigger inputs -- ports P1 through P8, RST/NMI, JTAG, XIN, and XT2IN (see Note 4)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
0.45 V
0.75 V
CC
CC
2.2 V
3 V
1.0
1.65
V
Positive-going input threshold voltage
V
IT+
1.35
2.25
0.25 V
0.55 V
CC
CC
2.2 V
3 V
0.55
1.2
V
V
Negative-going input threshold voltage
V
V
IT--
0.75
0.2
1.65
1.0
2.2 V
3 V
Input voltage hysteresis (V
-- V
)
IT--
hys
IT+
0.3
1.0
Pullup: V = V
,
SS
IN
R
C
Pullup/pulldown resistor
Input capacitance
20
35
5
50
kΩ
Pull
Pulldown: V = V
IN
CC
V
= V or V
CC
pF
I
IN
SS
NOTE 4: XIN and XT2IN in bypass mode only.
inputs -- ports P1 and P2
PARAMETER
TEST CONDITIONS
VCC
MIN
20
MAX
UNIT
Port P1, P2: P1.x to P2.x, external trigger pulse width to
set the interrupt flag (see Note)
t
External interrupt timing
2.2 V/3 V
ns
int
NOTE: The external signal sets the interrupt flag every time the minimum t
parameters are met. It may be set even with trigger signals shorter
(int)
than t
.
(int)
leakage current -- ports P1 through P8 (see Note 1 and 2)
PARAMETER
TEST CONDITIONS
see Notes 1 and 2
VCC
MIN
MAX
UNIT
I
High-impedance leakage current
2.2 V/3 V
±50
nA
lkg (Px.x)
NOTES: 1. The leakage current is measured with V or V applied to the corresponding pin(s), unless otherwise noted.
SS
CC
2. The leakage of digital port pins is measured individually. The port pin is selected for input and the pull--up/pull--down resistor is
disabled..
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
standard inputs -- RST/NMI
PARAMETER
Low-level input voltage
High-level input voltage
TEST CONDITIONS
VCC
MIN
MAX
+0.6
UNIT
V
V
V
2.2 V/3 V
2.2 V/3 V
V
V
SS
IL
SS
CC
0.8×V
V
V
IH
CC
outputs -- ports P1 through P8
PARAMETER
TEST CONDITIONS
= --1.5 mA (see Note 2)
= --6 mA (see Note 2)
= --1.5 mA (see Note 2)
= --6 mA (see Note 2)
= 1.5 mA (see Note 2)
= 6 mA (see Note 2)
= 1.5 mA (see Note 2)
= 6 mA (see Note 2)
VCC
MIN
MAX
UNIT
I
I
I
I
I
I
I
I
V
--0.25
V
V
V
V
OH(max)
OH(max)
OH(max)
OH(max)
OL(max)
OL(max)
OL(max)
OL(max)
CC
CC
CC
CC
CC
2.2 V
V
-- 0 . 6
CC
V
V
High-level output voltage
Low-level output voltage
V
OH
V
--0.25
CC
3 V
2.2 V
3 V
V
-- 0 . 6
CC
V
V
V
V
V
+0.25
SS
SS
SS
SS
SS
V
+0.6
SS
V
OL
V
+0.25
SS
V
+0.6
SS
NOTES: 1. The maximum total current, I
voltage drop specified.
and I
for all outputs combined, should not exceed ±12 mA to satisfy the maximum
OH(max)
OL(max),
2. The maximum total current, I
voltage drop specified.
and I
for all outputs combined, should not exceed ±48 mA to satisfy the maximum
OH(max)
OL(max),
output frequency -- ports P1 through P8
PARAMETER
TEST CONDITIONS
VCC
2.2 V
3.0 V
2.2 V
3.3 V
MIN
TYP
MAX
10
UNIT
DC
Port output frequency
with load
P1.4/SMCLK, C = 20 pF, R = 1 kΩ
L
L
f
f
MHz
Px.y
(see Notes 1 and 2)
DC
12
DC
12
P2.0/ACLK/CA2, P1.4/SMCLK, C = 20 pF
L
Clock output frequency
MHz
%
Port_CLK
(see Note 2)
DC
16
P5.6/ACLK, C = 20 pF, LF mode
L
30
50
50
70
P5.6/ACLK, C = 20 pF, XT1 mode
L
40
40
60
P5.4/MCLK, C = 20 pF, XT1 mode
L
60
Duty cycle of output
frequency
t
(Xdc)
P5.4/MCLK, C = 20 pF, DCO
50% -- 15 ns
40
50% 50% + 15 ns
60
L
P1.4/SMCLK, C = 20 pF, XT2 mode
%
L
P1.4/SMCLK, C = 20 pF, DCO
50% -- 15 ns
50% + 15 ns
L
NOTES: 1. A resistive divider with 2 times 0.5 kΩ between V and V is used as load. The output is connected to the center tap of the divider.
CC
SS
2. The output voltage reaches at least 10% and 90% V at the specified toggle frequency.
CC
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- outputs
TYPICAL LOW-LEVEL OUTPUT CURRENT
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
of one pin
of one pin
25.0
20.0
15.0
10.0
5.0
50.0
40.0
30.0
20.0
10.0
0.0
V
P4.5
= 2.2 V
CC
V
P4.5
= 3 V
CC
T
= 25°C
A
T
= 25°C
= 85°C
A
T
= 85°C
A
T
A
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
-- Low-Level Output Voltage -- V
V
-- Low-Level Output Voltage -- V
OL
OL
Figure 6
Figure 5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
of one pin
HIGH-LEVEL OUTPUT VOLTAGE
of one pin
0.0
-- 5 . 0
0.0
--10.0
--20.0
--30.0
--40.0
--50.0
V
P4.5
= 2.2 V
CC
V
P4.5
= 3 V
CC
--10.0
--15.0
--20.0
--25.0
T
A
= 85°C
T
A
= 85°C
T
A
= 25°C
T
A
= 25°C
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
-- High-Level Output Voltage -- V
OH
V
-- High-Level Output Voltage -- V
OH
Figure 7
Figure 8
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
POR/brownout reset (BOR) (see Notes 1 and 2)
PARAMETER
operating voltage
negative going V reset threshold voltage
TEST CONDITIONS
dV /dt ± 3 V/s
VCC
MIN
TYP
MAX
UNIT
V
V
V
V
0.7 ¢ V
CC(start)
(B_IT--)
CC
(B_IT--)
dV /dt ± 3 V/s
CC
1.71
V
CC
V
reset threshold hysteresis
dV /dt ± 3 V/s
CC
70
2
130
210
mV
μs
hys(B_IT--)
d(BOR)
reset
CC
t
t
BOR reset release delay time
2000
Pulse length at RST/NMI pin to accept a reset
2.2 V / 3 V
μs
NOTES: 1. The current consumption of the brownout module is included in the I current consumption data. The voltage level
CC
V
+ V
is ≤ 1.8 V.
(B_IT--)
hys(B_IT--)
2. During power up, the CPU begins code execution following a period of t
after V = V
+ V . The default DCO
hys(B_IT--)
d(BOR)
CC
(B_IT--)
settings must not be changed until V
frequency.
≥ V
, where V
is the minimum supply voltage for the desired operating
CC
CC(MIN)
CC(min)
VCC
Vhys(B_IT-)
V(B_IT-)
VCC(Start)
1
0
td(BOR)
Figure 9. POR/Brownout Reset (BOR) vs Supply Voltage
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- POR/brownout reset (BOR)
V
t
CC
pw
2
3 V
V
= 3 V
CC
Typical Conditions
1.5
1
V
CC(drop)
0.5
0
0.001
1
1000
1 ns
1 ns
-- Pulse Width -- μs
t
pw
-- Pulse Width -- μs
t
pw
Figure 10. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
V
t
CC
pw
2
1.5
1
3 V
V
= 3 V
CC
Typical Conditions
V
CC(drop)
0.5
t = t
f
r
0
0.001
1
1000
t
f
t
r
t
pw
-- Pulse Width -- μs
t
pw
-- Pulse Width -- μs
Figure 11. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
SVS (supply voltage supervisor/monitor)
PARAMETER
TEST CONDITIONS
dV /dt > 30 V/ms (see Figure 12)
MIN
TYP
MAX UNIT
5
150
μs
CC
t
(SVSR)
dV /dt ≤ 30 V/ms
CC
2000
t
t
SVSON, switch from VLD = 0 to VLD ≠ 0, V = 3 V
20
150
12
μs
μs
V
d(SVSon)
settle
CC
‡
VLD ≠ 0
V
VLD ≠ 0, V /dt ≤ 3 V/s (see Figure 12)
1.55
120
1.7
210
×
(SVSstart)
CC
VLD = 1
70
mV
V
V
/dt ≤ 3 V/s (see Figure 12)
V
×
V
CC
(SVS_IT--)
(SVS_IT--)
VLD = 2 to 14
V
0.004
0.016
V
hys(SVS_IT-- )
/dt ≤ 3 V/s (see Figure 12), External voltage applied
CC
VLD = 15
4.4
20
mV
on A7
VLD = 1
VLD = 2
VLD = 3
VLD = 4
VLD = 5
VLD = 6
VLD = 7
VLD = 8
VLD = 9
VLD = 10
VLD = 11
VLD = 12
VLD = 13
VLD = 14
1.8
1.94
2.05
2.14
2.24
2.33
2.46
2.58
2.69
2.83
2.94
3.11
3.24
3.43
1.9
2.1
2.05
2.25
2.37
2.48
2.6
2.2
2.3
2.4
2.5
2.71
2.86
3
2.65
2.8
V
/dt ≤ 3 V/s (see Figure 12 and Figure 13)
CC
V
V
(SVS_IT--)
2.9
3.13
3.29
3.42
3.05
3.2
†
3.35
3.5
3.61
†
3.76
†
†
3.7
3.99
V
/dt ≤ 3 V/s (see Figure 12 and Figure 13),
CC
VLD = 15
1.1
1.2
10
1.3
15
External voltage applied on A7
I
CC(SVS)
VLD ≠ 0, V = 2.2 V/3 V
μA
CC
(see Note 1)
†
‡
The recommended operating voltage range is limited to 3.6 V.
is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
t
settle
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 1: The current consumption of the SVS module is not included in the I current consumption data.
CC
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
typical characteristics
Software sets VLD >0:
SVS is active
AV
CC
V
hys(SVS_IT--)
V
(SVS_IT--)
V
(SVSstart)
V
hys(B_IT--)
V
(B_IT--)
V
CC(start)
Brown-
out
Brownout
Region
Region
Brownout
1
0
t
t
SVS out
1
d(BOR)
d(BOR)
SVS Circuit is Active From VLD > to V < V(
CC
B_IT--)
0
t
t
d(SVSon)
d(SVSR)
Set POR
1
undefined
0
Figure 12. SVS Reset (SVSR) vs Supply Voltage
V
CC
t
pw
3 V
2
Rectangular Drop
V
CC(min)
1.5
1
Triangular Drop
1 ns
1 ns
V
t
CC
pw
0.5
0
3 V
1
10
100
1000
t
pw
-- Pulse Width -- μs
V
CC(min)
t = t
f
r
t
f
t
r
t -- Pulse Width -- μs
Figure 13. VCC(min): Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal (VLD = 1)
40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
main DCO characteristics
D
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
D
D
DCO control bits DCOx have a step size as defined by parameter SDCO.
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal
to:
32 × fDCO(RSEL,DCO) × fDCO(RSEL,DCO+1)
MOD × fDCO(RSEL,DCO)+(32−MOD) × fDCO(RSEL,DCO+1)
faverage
=
DCO frequency
PARAMETER
TEST CONDITIONS
RSELx < 14
VCC
MIN
1.8
TYP
MAX UNIT
3.6
RSELx = 14
2.2
3.6
3.6
Vcc
Supply voltage range
V
RSELx = 15
3.0
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
DCO frequency (0, 0)
DCO frequency (0, 3)
DCO frequency (1, 3)
DCO frequency (2, 3)
DCO frequency (3, 3)
DCO frequency (4, 3)
DCO frequency (5, 3)
DCO frequency (6, 3)
DCO frequency (7, 3)
DCO frequency (8, 3)
DCO frequency (9, 3)
DCO frequency (10, 3)
DCO frequency (11, 3)
DCO frequency (12, 3)
DCO frequency (13, 3)
DCO frequency (14, 3)
DCO frequency (15, 3)
DCO frequency (15, 7)
Frequency step between
RSELx = 0, DCOx = 0, MODx = 0
RSELx = 0, DCOx = 3, MODx = 0
RSELx = 1, DCOx = 3, MODx = 0
RSELx = 2, DCOx = 3, MODx = 0
RSELx = 3, DCOx = 3, MODx = 0
RSELx = 4, DCOx = 3, MODx = 0
RSELx = 5, DCOx = 3, MODx = 0
RSELx = 6, DCOx = 3, MODx = 0
RSELx = 7, DCOx = 3, MODx = 0
RSELx = 8, DCOx = 3, MODx = 0
RSELx = 9, DCOx = 3, MODx = 0
RSELx = 10, DCOx = 3, MODx = 0
RSELx = 11, DCOx = 3, MODx = 0
RSELx = 12, DCOx = 3, MODx = 0
RSELx = 13, DCOx = 3, MODx = 0
RSELx = 14, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 7, MODx = 0
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
3 V
0.06
0.07
0.10
0.14
0.20
0.28
0.39
0.54
0.80
1.10
1.60
2.50
3.00
4.30
6.00
8.60
12.0
16.0
0.14 MHz
0.17 MHz
0.20 MHz
0.28 MHz
0.40 MHz
0.54 MHz
0.77 MHz
1.06 MHz
1.50 MHz
2.10 MHz
3.00 MHz
4.30 MHz
5.50 MHz
7.30 MHz
9.60 MHz
13.9 MHz
18.5 MHz
26.0 MHz
DCO(0,0)
DCO(0,3)
DCO(1,3)
DCO(2,3)
DCO(3,3)
DCO(4,3)
DCO(5,3)
DCO(6,3)
DCO(7,3)
DCO(8,3)
DCO(9,3)
DCO(10,3)
DCO(11,3)
DCO(12,3)
DCO(13,3)
DCO(14,3)
DCO(15,3)
DCO(15,7)
3 V
S
S
S
S
= f /f
DCO(RSEL+1,DCO) DCO(RSEL,DCO)
2.2 V/3 V
1.55 ratio
1.12 ratio
RSEL
DCO
RSEL
DCO
range RSEL and RSEL+1
Frequency step between
tap DCO and DCO+1
= f
/f
2.2 V/3 V
2.2 V/3 V
1.05
40
1.08
50
DCO(RSEL,DCO+1) DCO(RSEL,DCO)
Duty cycle
Measured at P1.4/SMCLK
60
%
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies -- tolerance at calibration
PARAMETER
TEST CONDITIONS
T
VCC
MIN
TYP
MAX UNIT
+1
A
Frequency tolerance at calibration
25°C
3 V
-- 1
±0.2
%
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
Gating time: 5 ms
f
f
f
f
1-MHz calibration value
8-MHz calibration value
12-MHz calibration value
16-MHz calibration value
25°C
3 V
3 V
3 V
3 V
0.990
7.920
11.88
15.84
1
8
1.010 MHz
8.080 MHz
CAL(1MHz)
CAL(8MHz)
CAL(12MHz)
CAL(16MHz)
BCSCTL1 = CALBC1_8MHz,
DCOCTL = CALDCO_8MHz,
Gating time: 5ms
25°C
25°C
25°C
BCSCTL1 = CALBC1_12MHz,
DCOCTL = CALDCO_12MHz,
Gating time: 5ms
12 12.12 MHz
16 16.16 MHz
BCSCTL1 = CALBC1_16MHz,
DCOCTL = CALDCO_16MHz,
Gating time: 2 ms
calibrated DCO frequencies -- tolerance over temperature 0°C to 85°C
PARAMETER
TEST CONDITIONS
T
VCC
3 V
MIN
-- 2 . 5
TYP
MAX UNIT
A
1-MHz tolerance over temperature
8-MHz tolerance over temperature
12-MHz tolerance over temperature
16-MHz tolerance over temperature
0°C to 85°C
0°C to 85°C
0°C to 85°C
0°C to 85°C
±0.5
±1.0
±1.0
±2.0
1
+2.5
+2.5
%
%
%
%
3 V
-- 2 . 5
3 V
-- 2 . 5
+2.5
3 V
-- 3 . 0
+3.0
2.2 V
3 V
0.970
0.975
0.970
7.760
7.800
7.600
11.64
11.64
11.64
1.030
1.025
1.030
8.400
8.200
8.240
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
Gating time: 5ms
1
f
f
1-MHz calibration value
8-MHz calibration value
0°C to 85°C
0°C to 85°C
MHz
MHz
CAL(1MHz)
CAL(8MHz)
3.6 V
2.2 V
3 V
1
8
BCSCTL1 = CALBC1_8MHz,
DCOCTL = CALDCO_8MHz,
Gating time: 5 ms
8
3.6 V
2.2 V
3 V
8
12 12.36
12 12.36
12 12.36
BCSCTL1 = CALBC1_12MHz,
DCOCTL = CALDCO_12MHz,
Gating time: 5 ms
f
f
12-MHz calibration value
16-MHz calibration value
0°C to 85°C
0°C to 85°C
MHz
MHz
CAL(12MHz)
CAL(16MHz)
3.6 V
BCSCTL1 = CALBC1_16MHz,
DCOCTL = CALDCO_16MHz,
Gating time: 2 ms
3 V
15.52
15.00
16 16.48
16 16.48
3.6 V
42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies -- tolerance over supply voltage VCC
PARAMETER
TEST CONDITIONS
T
VCC
MIN
-- 3
TYP
±2
MAX UNIT
A
1-MHz tolerance over V
25°C
25°C
25°C
25°C
1.8 V to 3.6 V
1.8 V to 3.6 V
2.2 V to 3.6 V
3.0 V to 3.6 V
+3
+3
+3
+3
%
%
%
%
CC
CC
8-MHz tolerance over V
-- 3
±2
12-MHz tolerance over V
16-MHz tolerance over V
-- 3
±2
CC
CC
-- 6
±2
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
Gating time: 5 ms
f
f
f
f
1-MHz calibration value
8-MHz calibration value
12-MHz calibration value
16-MHz calibration value
25°C
25°C
25°C
25°C
1.8 V to 3.6 V 0.970
1.8 V to 3.6 V 7.760
1
8
1.030 MHz
8.240 MHz
CAL(1MHz)
CAL(8MHz)
CAL(12MHz)
CAL(16MHz)
BCSCTL1 = CALBC1_8MHz,
DCOCTL = CALDCO_8MHz,
Gating time: 5 ms
BCSCTL1 = CALBC1_12MHz,
DCOCTL = CALDCO_12MHz,
Gating time: 5 ms
2.2 V to 3.6 V
11.64
12 12.36 MHz
16 16.48 MHz
BCSCTL1 = CALBC1_16MHz,
DCOCTL = CALDCO_16MHz,
Gating time: 2 ms
3.0 V to 3.6 V 15.00
calibrated DCO frequencies -- overall tolerance
PARAMETER
1-MHz tolerance overall
8-MHz tolerance overall
12-MHz tolerance overall
16-MHz tolerance overall
TEST CONDITIONS
T
VCC
MIN
-- 5
TYP
MAX UNIT
A
-- 4 0 °C to 105°C 1.8 V to 3.6 V
-- 4 0 °C to 105°C 1.8 V to 3.6 V
-- 4 0 °C to 105°C 2.2 V to 3.6 V
±2
±2
±2
±3
+5
+5
+5
+6
%
%
%
%
-- 5
-- 5
-- 4 0 °C to 105°C
3 V to 3.6 V
-- 6
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
Gating time: 5ms
f
f
f
f
1-MHz calibration value
8-MHz calibration value
-- 4 0 °C to 105°C 1.8 V to 3.6 V 0.950
-- 4 0 °C to 105°C 1.8 V to 3.6 V 7.600
1
8
1.050 MHz
8.400 MHz
CAL(1MHz)
CAL(8MHz)
CAL(12MHz)
CAL(16MHz)
BCSCTL1 = CALBC1_8MHz,
DCOCTL = CALDCO_8MHz,
Gating time: 5ms
BCSCTL1 = CALBC1_12MHz,
12-MHz calibration value DCOCTL = CALDCO_12MHz, -- 4 0 °C to 105°C 2.2 V to 3.6 V
11.40
15.00
12 12.60 MHz
16 17.00 MHz
Gating time: 5ms
BCSCTL1 = CALBC1_16MHz,
16-MHz calibration value DCOCTL = CALDCO_16MHz, -- 4 0 °C to 105°C
3 V to 3.6 V
Gating time: 2 ms
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- calibrated 1-MHz DCO frequency
1.02
1.01
T
A
= 105 °C
1.00
0.99
0.98
T
= 85 °C
= 25 °C
A
T
A
T
A
= --40 °C
1.5
2.0
2.5
3.0
3.5
4.0
V
-- Supply Voltage -- V
CC
Figure 14. Calibrated 1-MHz Frequency vs VCC
typical characteristics -- calibrated 8-MHz DCO frequency
8.20
8.15
8.10
8.05
8.00
7.95
7.90
7.85
7.80
T
= 105 °C
A
T
= 85 °C
A
T
A
= 25 °C
T
A
= --40 °C
1.5
2.0
2.5
3.0
3.5
4.0
V
-- Supply Voltage -- V
CC
Figure 15. Calibrated 8-MHz Frequency vs VCC
44
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- calibrated 12-MHz DCO frequency
12.2
12.1
T
A
= --40 °C
T
= 25 °C
= 85 °C
12.0
11.9
11.8
11.7
A
T
A
T
A
= 105 °C
1.5
2.0
2.5
3.0
3.5
4.0
V
-- Supply Voltage -- V
CC
Figure 16. Calibrated 12-MHz Frequency vs VCC
typical characteristics -- calibrated 16-MHz DCO frequency
16.1
16.0
15.9
15.8
15.7
15.6
T
= --40 °C
A
T
= 25 °C
A
T
A
= 85 °C
T
A
= 105 °C
1.5
2.0
2.5
3.0
3.5
4.0
V
-- Supply Voltage -- V
CC
Figure 17. Calibrated 16-MHz Frequency vs VCC
45
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
wake-up from low-power modes (LPM3/LPM4)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
BCSCTL1= CALBC1_1MHz,
DCOCTL = CALDCO_1MHz
2.2 V/3 V
2
BCSCTL1= CALBC1_8MHz,
DCOCTL = CALDCO_8MHz
2.2 V/3 V
2.2 V/3 V
3 V
1.5
DCO clock wake-up time from LPM3/4
(see Note 1)
t
t
μs
DCO,LPM3/4
CPU,LPM3/4
BCSCTL1= CALBC1_12MHz,
DCOCTL = CALDCO_12MHz
1
BCSCTL1= CALBC1_16MHz,
DCOCTL = CALDCO_16MHz
1
CPU wake-up time from LPM3/4
(see Note 2)
1/f
+
MCLK
t
Clock,LPM3/4
NOTES: 1. The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK).
2. Parameter applicable only if DCOCLK is used for MCLK.
typical characteristics -- DCO clock wake-up time from LPM3/4
10.00
RSELx = 0...11
1.00
RSELx = 12...15
0.10
0.10
1.00
DCO Frequency -- MHz
10.00
Figure 18. Clock Wake-Up Time From LPM3 vs DCO Frequency
46
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
DCO with external resistor ROSC (see Note 1)
PARAMETER
TEST CONDITIONS
VCC
2.2 V
TYP UNIT
1.8
MHz
1.95
f
DCO output frequency with R
Temperature drift
DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0, T = 25°C
DCO,ROSC
OSC
A
3 V
D
D
DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0
DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
2.2 V/3 V
±0.1 %/°C
t
Drift with V
10 %/V
V
CC
NOTE 1:
R = 100 kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and T = ±50ppm/°C.
OSC K
typical characteristics -- DCO with external resistor ROSC
10.00
10.00
1.00
0.10
0.01
1.00
0.10
RSELx = 4
RSELx = 4
0.01
10.00
100.00
1000.00
10000.00
10.00
100.00
1000.00
10000.00
R
OSC
-- External Resistor -- kOhm
R
OSC
-- External Resistor -- kOhm
Figure 19. DCO Frequency vs ROSC
,
Figure 20. DCO Frequency vs ROSC
,
V
CC = 2.2 V, TA = 25°C
V
CC = 3.0 V, TA = 25°C
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
R
= 100k
OSC
R
= 100k
OSC
R
R
= 270k
= 1M
3.5
R
R
= 270k
= 1M
OSC
OSC
OSC
OSC
--50.0 --25.0
0.0
25.0
50.0
75.0 100.0
1.5
2.0
2.5
3.0
4.0
T
A
-- Temperature -- °C
V
CC
-- Supply Voltage -- V
Figure 21. DCO Frequency vs Temperature,
CC = 3.0 V
Figure 22. DCO Frequency vs VCC,
V
TA = 25°C
47
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, low frequency modes (see Note 4)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
LFXT1 oscillator crystal
frequency, LF mode 0/1
f
f
XTS = 0, LFXT1Sx = 0 or 1
1.8 V to 3.6 V
32,768
Hz
LFXT1,LF
LFXT1 oscillator logic
level square wave input
frequency, LF mode
XTS = 0, LFXT1Sx = 3, XCAPx = 0
XTS = 0, LFXT1Sx = 0,
1.8 V to 3.6 V
10,000 32,768
50,000
Hz
LFXT1,LF,logic
f
C
= 32,768 kHz,
= 6 pF
500
200
LFXT1,LF
Oscillation allowance for
LF crystals
L,eff
OA
kΩ
LF
XTS = 0, LFXT1Sx = 0;
= 32,768 kHz, C
f
= 12 pF
L,eff
LFXT1,LF
XTS = 0, XCAPx = 0
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
XTS = 0, XCAPx = 3
1
5.5
8.5
11
Integrated effective load
capacitance, LF mode
(see Note 1)
C
L,eff
pF
XTS = 0, Measured at P1.4/ACLK,
= 32,768 Hz
Duty cycle
LF mode
2.2 V/3 V
2.2 V/3 V
30
10
50
70
%
f
LFXT1,LF
Oscillator fault
frequency, LF mode
(see Note 3)
XTS = 0, LFXT1Sx = 3, XCAPx = 0
(see Note 2)
f
10,000
Hz
Fault,LF
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
2. Measured with logic level input frequency but also applies to operation with crystals.
3. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep as short of a trace as possible between the device and the crystal.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
-- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
-- If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
-- Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
5. Applies only if using an external logic-level clock source. Not applicable when using a crystal or resonator.
48
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
internal very low power, low frequency oscillator (VLO)
PARAMETER
TEST CONDITIONS
T
A
VCC
MIN
TYP
MAX UNIT
-- 4 0 °C to 85°C
105°C
4
12
20
f
VLO frequency
2.2 V/3 V
kHz
22
VLO
VLO frequency
temperature drift
df
df
/dT
/dV
See Note NO TAG1
See Note 2
2.2 V/3 V
0.5
4
%/°C
VLO
VLO
VLO frequency supply
voltage drift
25°C
1.8V -- 3.6V
%/V
CC
NOTES: 1. Calculated using the box method:
I version: (MAX(--40_C to 85_C) -- MIN(--40_C to 85_C))/MIN(--40_C to 85_C)/(85_C -- (--40_C))
T version: (MAX(--40_C to 105_C) -- MIN(--40_C to 105_C))/MIN(--40_C to 105_C)/(105_C -- (--40_C))
2. Calculated using the box method: (MAX(1.8 V to 3.6V) -- MIN(1.8V to 3.6V))/MIN(1.8 V to 3.6V)/(3.6 V -- 1.8 V)
49
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, high frequency modes (see Note 5)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
LFXT1 oscillator crystal frequency,
HF mode 0
f
f
XTS = 1, LFXT1Sx = 0, XCAPx = 0 1.8 V to 3.6 V
0.4
1
4
MHz
MHz
LFXT1,HF0
LFXT1,HF1
LFXT1 oscillator crystal frequency,
HF mode 1
XTS = 1, LFXT1Sx = 1, XCAPx = 0 1.8 V to 3.6 V
1.8 V to 3.6 V
1
2
2
10
12
16
10
12
16
LFXT1 oscillator crystal frequency,
HF mode 2
2.2 V to 3.6 V
3 V to 3.6 V
1.8 V to 3.6 V
2.2 V to 3.6 V
3 V to 3.6 V
f
f
XTS = 1, LFXT1Sx = 2, XCAPx = 0
MHz
MHz
LFXT1,HF2
2
0.4
0.4
0.4
LFXT1 oscillator logic level
square-wave input frequency,
HF mode
XTS = 1, LFXT1Sx = 3, XCAPx = 0
XTS = 1, XCAPx = 0,
LFXT1,HF,logic
LFXT1Sx = 0, f
= 1 MHz,
= 4 MHz,
= 16 MHz,
2700
800
300
1
LFXT1,HF
C
L,eff
= 15 pF
XTS = 1, XCAPx = 0,
LFXT1Sx = 1, f
Oscillation allowance for HF
crystals
OA
Ω
LFXT1,HF
HF
C
L,eff
= 15 pF
(see Figure 23 and Figure 24)
XTS = 1, XCAPx = 0,
LFXT1Sx = 2, f
LFXT1,HF
C
L,eff
= 15 pF
Integrated effective load
capacitance, HF mode
(see Note 1)
C
XTS = 1, XCAPx = 0 (see Note 2)
pF
%
L,eff
XTS = 1, XCAPx = 0,
Measured at P1.4/ACLK,
2.2 V/3 V
40
50
60
60
f
= 10 MHz
LFXT1,HF
Duty cycle
HF mode
XTS = 1, XCAPx = 0,
Measured at P1.4/ACLK,
2.2 V/3 V
2.2 V/3 V
40
30
50
f
= 16 MHz
LFXT1,HF
Oscillator fault frequency, HF mode XTS = 1, LFXT1Sx = 3, XCAPx = 0
(see Note 4) (see Note 3)
f
300 kHz
Fault,HF
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
3. Measured with logic level input frequency but also applies to operation with crystals.
4. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
5. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep the trace between the device and the crystal as short as possible.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
-- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
-- If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
-- Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
50
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- LFXT1 oscillator in HF mode (XTS = 1)
100000.00
10000.00
1000.00
LFXT1Sx = 3
100.00
LFXT1Sx = 2
10.00
LFXT1Sx = 1
1.00
10.00
0.10
100.00
Crystal Frequency -- MHz
Figure 23. Oscillation Allowance vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C
1500.0
1400.0
1300.0
LFXT1Sx = 3
1200.0
1100.0
1000.0
900.0
800.0
700.0
600.0
500.0
400.0
300.0
LFXT1Sx = 2
200.0
100.0
LFXT1Sx = 1
0.0
0.0
4.0
8.0
12.0
16.0
20.0
Crystal Frequency -- MHz
Figure 24. XT Oscillator Supply Current vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C
51
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, XT2 (see Note 5)
PARAMETER
TEST CONDITIONS
XT2Sx = 0
VCC
MIN
TYP
MAX UNIT
XT2 oscillator crystal frequency,
mode 0
f
f
1.8 V to 3.6 V
0.4
1
4
MHz
MHz
XT2
XT2
XT2 oscillator crystal frequency,
mode 1
XT2Sx = 1
XT2Sx = 2
1.8 V to 3.6 V
1
1.8 V to 3.6 V
2.2 V to 3.6 V
3 V to 3.6 V
2
2
10
12
16
10
12
16
XT2 oscillator crystal frequency,
mode 2
f
f
MHz
MHz
XT2
XT2
2
1.8 V to 3.6 V
2.2 V to 3.6 V
3 V to 3.6 V
0.4
0.4
0.4
XT2 oscillator logic level
square-wave input frequency
XT2Sx = 3
XT2Sx = 0, f
= 1 MHz,
= 4 MHz,
XT2
XT2
2700
800
C
L,eff
= 15 pF
XT2Sx = 1, f
Oscillation allowance
(see Figure 23 and Figure 24)
OA
Ω
C
L,eff
= 15 pF
XT2Sx = 2, f
= 16 MHz,
XT1,HF
300
C
= 15 pF
L,eff
Integrated effective load
capacitance, HF mode
(see Note 1)
C
See Note 2
1
pF
%
L,eff
Measured at P1.4/SMCLK,
= 10 MHz
40
40
30
50
50
60
60
f
XT2
Duty cycle
2.2 V/3 V
2.2 V/3 V
Measured at P1.4/SMCLK,
= 16 MHz
f
XT2
Oscillator fault frequency, HF mode
(see Note 4)
f
XT2Sx = 3, (see Note 3)
300 kHz
Fault
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
3. Measured with logic level input frequency but also applies to operation with crystals.
4. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
5. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep the trace between the device and the crystal as short as possible.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
-- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
-- If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
-- Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
52
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- XT2 oscillator
100000.00
10000.00
1000.00
XT2Sx = 3
100.00
XT2Sx = 2
XT2Sx = 1
1.00
10.00
0.10
10.00
100.00
Crystal Frequency -- MHz
Figure 25. Oscillation Allowance vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C
1600.0
1500.0
1400.0
XT2Sx = 3
1300.0
1200.0
1100.0
1000.0
900.0
800.0
700.0
600.0
500.0
400.0
300.0
XT2Sx = 2
200.0
100.0
XT2Sx = 1
0.0
0.0
4.0
8.0
12.0
16.0
20.0
Crystal Frequency -- MHz
Figure 26. XT2 Oscillator Supply Current vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C
53
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Timer_A
PARAMETER
TEST CONDITIONS
Internal: SMCLK, ACLK,
External: TACLK, INCLK,
VCC
MIN
MAX UNIT
2.2 V
10
f
t
Timer_A clock frequency
Timer_A, capture timing
MHz
16
TA
3.3 V
Duty cycle = 50% ±10%
TA0, TA1, TA2
2.2 V/3 V
20
ns
TA,cap
Timer_B
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK, ACLK,
External: TBCLK,
Duty cycle = 50% ±10%
2.2 V
10
f
Timer_B clock frequency
Timer_B, capture timing
MHz
16
TB
3.3 V
t
TB0, TB1, TB2
2.2 V/3 V
20
ns
TB,cap
54
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART mode)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
External: UCLK
f
USCI input clock frequency
f
MHz
USCI
SYSTEM
Duty cycle = 50% ± 10%
BITCLK clock frequency
(equals baud rate in MBaud)
f
t
2.2 V /3 V
1
MHz
BITCLK
2.2 V
3 V
50
50
150
100
600
600
ns
ns
UART receive deglitch time
(see Note 1)
τ
NOTE 1: Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI master mode) (see Figure 27 and Figure 28)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
SMCLK, ACLK
Duty cycle = 50% ± 10%
f
t
t
t
USCI input clock frequency
f
MHz
ns
USCI
SYSTEM
2.2 V
3 V
110
75
0
SOMI input data setup time
SOMI input data hold time
SU,MI
2.2 V
3 V
ns
HD,MI
0
2.2 V
3 V
30
20
UCLK edge to SIMO valid;
SIMO output data valid time
1
ns
VALID,MO
C
L
= 20 pF
NOTE 2: fUCxCLK
=
with tLO∕HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
2tLO∕HI
For the slave parameters t
and t
, see the SPI parameters of the attached slave.
VALID,SO(Slave)
SU,SI(Slave)
USCI (SPI slave mode) (see Figure 29 and Figure 30)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
STE lead time,
STE low to clock
t
t
t
t
2.2 V/3 V
50
ns
STE,LEAD
STE,LAG
STE,ACC
STE,DIS
STE lag time,
Last clock to STE high
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
10
ns
ns
ns
STE access time,
STE low to SOMI data out
50
50
STE disable time,
STE high to SOMI high impedance
2.2 V
3 V
20
15
10
10
t
t
t
SIMO input data setup time
SIMO input data hold time
ns
SU,SI
2.2 V
3 V
ns
HD,SI
2.2 V
3 V
75
50
110
UCLK edge to SOMI valid;
= 20 pF
SOMI output data valid time
1
ns
75
VALID,SO
C
L
NOTE 3: fUCxCLK
=
with tLO∕HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI))
2tLO∕HI
For the master parameters t
and t
, see the SPI parameters of the attached master.
VALID,MO(Master)
SU,MI(Master)
55
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
1/f
UCxCLK
CKPL=0
CKPL=1
UCLK
t
t
t
LO/HI
LO/HI
SU,MI
t
HD,MI
SOMI
SIMO
t
VALID,MO
Figure 27. SPI Master Mode, CKPH = 0
1/f
UCxCLK
CKPL=0
CKPL=1
UCLK
t
t
LO/HI
LO/HI
t
HD,MI
t
SU,MI
SOMI
SIMO
t
VALID,MO
Figure 28. SPI Master Mode, CKPH = 1
56
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
t
t
STE,LAG
STE,LEAD
STE
1/f
UCxCLK
CKPL=0
CKPL=1
UCLK
t
t
t
LO/HI
LO/HI
SU,SI
t
HD,SI
SIMO
SOMI
t
t
t
STE,DIS
STE,ACC
VALID,SO
Figure 29. SPI Slave Mode, CKPH = 0
t
t
STE,LAG
STE,LEAD
STE
1/f
UCxCLK
CKPL=0
CKPL=1
UCLK
t
t
LO/HI
LO/HI
t
HD,SI
t
SU,SI
SIMO
SOMI
t
t
t
STE,DIS
STE,ACC
VALID,SO
Figure 30. SPI Slave Mode, CKPH = 1
57
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (I2C mode) (see Figure 31)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
MHz
Internal: SMCLK, ACLK
External: UCLK
f
USCI input clock frequency
f
SYSTEM
USCI
Duty cycle = 50% ± 10%
f
t
SCL clock frequency
2.2 V/3 V
2.2 V/3 V
0
4.0
0.6
4.7
0.6
0
400 kHz
SCL
f
f
f
f
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
SCL
SCL
SCL
SCL
Hold time (repeated) Start
μs
HD,STA
t
Setup time for a repeated Start
2.2 V/3 V
μs
SU,STA
t
t
t
Data hold time
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V
ns
HD,DAT
SU,DAT
SU,STO
Data setup time
Setup time for Stop
250
4.0
50
ns
μs
150
100
600
t
Pulse width of spikes suppressed by input filter
ns
SP
3 V
50
600
t
t
t
SU,STA HD,STA
HD,STA
SDA
SCL
1/f
t
SP
SCL
t
t
SU,STO
SU,DAT
t
HD,DAT
Figure 31. I2C Mode Timing
58
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Comparator_A+ (see Note 1)
PARAMETER
TEST CONDITIONS
VCC
2.2 V
3 V
MIN
TYP
25
MAX UNIT
40
μA
60
I
I
CAON = 1, CARSEL = 0, CAREF = 0
(DD)
45
CAON = 1, CARSEL = 0,
CAREF = 1/2/3, no load at P2.3/CA0/TA1
and P2.4/CA1/TA2
2.2 V
30
45
50
μA
71
(Refladder/Refdiode)
3 V
V
V
Common-mode input voltage
CAON =1
2.2 V/3 V
0
V
-- 1
CC
V
(IC)
PCA0 = 1, CARSEL = 1, CAREF = 1,
no load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
Voltage @ 0.25 V
node
2.2 V/3 V
2.2 V/3 V
0.23
0.24
0.48
0.25
0.5
(Ref025)
CC
V
CC
PCA0 = 1, CARSEL = 1, CAREF = 2,
no load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
Voltage @ 0.5V
node
CC
V
V
0.47
(Ref050)
(RefVT)
V
CC
PCA0 = 1, CARSEL = 1, CAREF = 3,
no load at P2.3/CA0/TA1 and
P2.4/CA1/TA2, T = 85°C
2.2 V
3 V
390
400
480
490
540
550
See Figure 35 and Figure 36
mV
A
V
V
Offset voltage
See Note 2
CAON=1
2.2 V/3 V
2.2 V/3 V
2.2 V
-- 3 0
0
30
1.4
300
240
2.8
2.2
mV
mV
(offset)
hys
Input hysteresis
0.7
165
120
1.9
80
70
1.4
0.9
T
A
= 25°C, Overdrive 10 mV,
ns
Without filter: CAF = 0
3 V
Response time, low-to-high and
high-to-low (see Note 3)
t
(response)
2.2 V
T
A
= 25°C, Overdrive 10 mV,
μs
With filter: CAF = 1
3 V
1.5
NOTES: 1. The leakage current for the Comparator_A+ terminals is identical to I
specification.
lkg(Px.x)
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements.
The two successive measurements are then summed together.
3. The response time is measured at P2.2/CAOUT/TA0/CA4 with an input voltage step, with Comparator_A+ already enabled
(CAON = 1). If CAON is set at the same time, a settling time of up to 300 ns is added to the response time.
59
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
0 V
V
CC
0
1
CAF
CAON
To Internal
Modules
Low Pass Filter
0
1
0
1
+
_
V+
V--
CAOUT
Set CAIFG
Flag
τ ≈ 2.0 μs
Figure 32. Block Diagram of Comparator_A Module
V
CAOUT
Overdrive
V--
400 mV
V+
t
(response)
Figure 33. Overdrive Definition
CASHORT
CA1
CA0
1
+
--
I
= 10μA
OUT
V
IN
Comparator_A+
CASHORT = 1
Figure 34. Comparator_A+ Short Resistance Test Condition
60
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- Comparator A+
650
600
550
500
450
400
650
600
550
500
450
400
V
= 2.2 V
V
= 3 V
CC
CC
Typical
Typical
-- 4 5
-- 2 5
-- 5
1 5
3 5
5 5
7 5
9 5
-- 4 5
-- 2 5
-- 5
1 5
3 5
5 5
7 5
9 5
T
A
-- Free-Air Temperature -- °C
T
A
-- Free-Air Temperature -- °C
Figure 36. V(RefVT) vs Temperature, VCC = 2.2 V
Figure 35. V(RefVT) vs Temperature, VCC = 3 V
100.00
V
= 1.8V
CC
V
= 2.2V
= 3.0V
CC
V
CC
10.00
V
= 3.6V
0.6
CC
1.00
0.0
0.2
/V
0.4
0.8
1.0
V
-- Normalized Input Voltage -- V/V
IN CC
Figure 37. Short Resistance vs VIN/VCC
61
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
12-bit ADC power supply and input range conditions (see Note 1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
AV and DV are connected together,
CC
CC
AV
Analog supply voltage
AV and DV are connected together,
2.2
3.6
V
CC
SS
SS
V
= V
= 0 V
(AVSS)
(DVSS)
All P6.0/A0 to P6.7/A7 terminals.
Analog inputs selected in ADC12MCTLx register
and P6Sel.x = 1, 0 ≤ x ≤ 7,
Analog input voltage
(see Note 2)
V
0
V
AVCC
V
(P6.x/Ax)
V
≤ V
≤ V
(AVSS)
P6.x/Ax (AVCC)
Operating supply current
2.2 V
3 V
0.65
0.8
0.8
1.0
f
= 5 MHz, ADC12ON = 1, REFON = 0,
ADC12CLK
into AV terminal
I
mA
CC
ADC12
SHT0 = 0, SHT1 = 0, ADC12DIV = 0
(see Note 3)
f
= 5 MHz, ADC12ON = 0,
ADC12CLK
3 V
0.5
0.7
Operating supply current
REFON = 1, REF2_5V = 1
I
mA
into AV terminal
(see Note 4)
REF+
†
CC
2.2 V
3 V
0.5
0.5
0.7
0.7
f
= 5 MHz, ADC12ON = 0,
ADC12CLK
REFON = 1, REF2_5V = 0
Only one terminal can be selected at one time,
P6.x/Ax
C
Input capacitance
2.2 V
40
pF
I
†
R
I
Input MUX ON resistance 0 V ≤ V ≤ V
3 V
2000
Ω
Ax
AVCC
†
Lmits verified by design
NOTES: 1. The leakage current is defined in the leakage current table with P6.x/Ax parameter.
2. The analog input voltage range must be within the selected reference voltage range V to V for valid conversion results.
R+
R--
3. The internal reference supply current is not included in current consumption parameter I
.
ADC12
4. The internal reference current is supplied via terminal AV . Consumption is independent of the ADC12ON control bit, unless a
CC
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
12-bit ADC external reference (see Note 1)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
Positive external
reference voltage input
V
V
> V
> V
/V
(see Note 2)
(see Note 3)
(see Note 4)
1.4
V
V
eREF+
eREF+
REF-- eREF--
AVCC
Negative external
reference voltage input
V
V
V
eREF+
/V
REF-- eREF--
0
1.2
V
V
REF-- / eREF--
Differential external
reference voltage input
(V
-- V
V
)
V
eREF+
> V
/V
1.4
V
AVCC
eREF+
REF--/ eREF--
REF-- eREF--
I
I
Static input current
Static input current
0V ≤V
≤ V
AVCC
2.2 V/3 V
2.2 V/3 V
±1
±1
μA
μA
VeREF+
eREF+
0V ≤ V
≤ V
AVCC
VREF--/VeREF--
eREF--
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, C , is also
i
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
62
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
12-bit ADC built-in reference
PARAMETER
TEST CONDITIONS
REF2_5V = 1 (2.5 V)
VCC
TA
MIN
2.4
TYP
2.5
2.5
1.5
1.5
MAX
2.6
UNIT
-- 4 0 °C to 85°C
105°C
3 V
Positive built-in
reference voltage
output
I
max ≤ I ≤ I
min
VREF+
VREF+ VREF+
2.37
1.44
1.42
2.64
1.56
1.57
V
V
REF+
-- 4 0 °C to 85°C
105°C
REF2_5V = 0 (1.5 V)
max ≤ I ≤ I
2.2 V/3 V
2.2 V/3 V
I
min
min
VREF+
VREF+ VREF+
REF2_5V = 0,
max ≤ I
2.2
2.8
2.9
I
≤ I
VREF+ VREF+
VREF+
AV minimum
CC
REF2_5V = 1,
voltage, positive
built-in reference
active
AV
V
CC(min)
--0.5mA ≤ I
≤ I
min
VREF+ VREF+
REF2_5V = 1,
-- 1 m A ≤ I
≤ I
min
VREF+ VREF+
2.2 V
3 V
0.01
0.01
-- 0 . 5
-- 1
Load current out of
I
I
mA
VREF+
V
terminal
REF+
I
= 500 μA +/-- 100 μA
2.2 V
3 V
±2
±2
VREF+
Analog input voltage ~0.75 V,
REF2_5V = 0
Load-current
regulation, V
terminal
†
LSB
REF+
L(VREF)+
I
= 500 μA ± 100 μA
VREF+
Analog input voltage ~1.25 V,
REF2_5V = 1
3 V
±2
Load current
regulation V
I
C
= 100 μA → 900 μA,
= 5 μF, at ~0.5 V ,
REF+
VREF+
‡
I
3 V
20
ns
REF+
VREF+
DL(VREF) +
terminal
Capacitance at pin REFON =1,
(see Note 1) 0 mA ≤ I
Error of conversion result ≤ 1 LSB
C
2.2 V/3 V
2.2 V/3 V
5
10
μF
VREF+
V
≤ I
max
VREF+
REF+
VREF+
Temperature
coefficient of
I
is a constant in the range
VREF+
†
T
REF+
±100 ppm/°C
of 0 mA ≤ I
≤ 1 mA
VREF+
built-in reference
Settle time of
internal reference
voltage (see
Figure 38 and Note
2)
I
V
= 0.5 mA, C
= 10 μF,
= 2.2 V
VREF+
VREF+
†
17
ms
t
REFON
= 1.5 V, V
REF+
AVCC
†
‡
Limits characterized
Limits verified by design
NOTES: 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests use
two capacitors between pins V
and AV and V
/V
and AV : 10 μF tantalum and 100 nF ceramic.
REF+
SS
REF-- eREF--
SS
2. The condition is that the error in a conversion started after t
capacitive load.
is less than ±0.5 LSB. The settling time depends on the external
REFON
63
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- ADC12
C
VREF+
100 μF
t
≈ .66 x C
[ms] with C
in μF
REFON
VREF+
VREF+
10 μF
1 μF
0
10 ms
1 ms
100 ms
t
REFON
Figure 38. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF
+
64
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
DV
From
Power
Supply
CC
SS
+
--
DV
10 μF 100 nF
AV
CC
SS
+
--
MSP430F261x
MSP430F241x
AV
10 μF 100 nF
Apply External Reference [V
or Use Internal Reference [V
]
eREF+
V
or V
eREF+
REF+
]
REF+
+
--
10 μF 100 nF
Apply
V
-- / V
eREF--
REF
External
Reference
+
--
10 μF 100 nF
Figure 39. Supply Voltage and Reference Voltage Design VREF--/VeREF-- External Supply
DV
DV
From
Power
Supply
CC
+
--
SS
10 μF 100 nF
AV
CC
SS
+
--
MSP430F261x
MSP430F241x
AV
V
10 μF 100 nF
Apply External Reference [V
or Use Internal Reference [V
]
eREF+
or V
]
REF+
eREF+
REF+
+
--
10 μF 100 nF
Reference Is Internally
Switched to AV
V
/V
REF-- eREF--
SS
Figure 40. Supply Voltage and Reference Voltage Design VREF--/VeREF-- = AVSS, Internally Connected
65
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
12-bit ADC timing parameters
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
For specified performance of ADC12
linearity parameters
f
f
2.2V/3 V
0.45
5
6.3
MHz
ADC12CLK
ADC12OSC
ADC12DIV = 0,
Internal ADC12 oscillator
Conversion time
2.2 V/ 3 V
2.2 V/ 3 V
3.7
5
6.3
MHz
f
= f
ADC12CLK
ADC12OSC
C
VREF+
≥ 5 μF, Internal oscillator,
2.06
3.51
f
= 3.7 MHz to 6.3 MHz
ADC12OSC
t
μs
CONVERT
External f
from ACLK, MCLK
13 × ADC12DIV
ADC12CLK
or SMCLK, ADC12SSEL ≠ 0
× 1/f
ADC12CLK
Turn-on settling time of
the ADC
‡
t
t
See Note 1
100
ns
ns
ADC12ON
3 V
1220
1400
R
S
= 400 Ω, R = 1000 Ω, C = 30 pF,
I I
‡
Sampling time
Sample
τ = [R + R ] x C (see Note 2)
2.2 V
S
I
I;
†
‡
Limits characterized
Limits verified by design
NOTES: 1. The condition is that the error in a conversion started after t
settled.
is less than ±0.5 LSB. The reference and input signal are already
ADC12ON
2. Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
n+1
t
= ln(2 ) x (R + R ) x C + 800 ns where n = ADC resolution = 12, R = external source resistance.
Sample
S
I
I
S
12-bit ADC linearity parameters
PARAMETER
TEST CONDITIONS
VCC
MIN TYP
MAX
±2
UNIT
1.4 V ≤ (V
-- V
/V
) min ≤ 1.6 V
eREF+
REF-- eREF--
E
E
Integral linearity error
2.2 V/3 V
LSB
I
1.6 V < (V
-- V
/V
) min ≤ V
±1.7
eREF+
REF-- eREF--
AVCC
(V
C
-- V
/V
)
≤ (V
-- V
/V
),
eREF+
VREF+
REF-- eREF-- min
eREF+
REF-- eREF--
Differential linearity error
2.2 V/3 V
2.2 V/3 V
±1
LSB
LSB
D
= 10 μF (tantalum) and 100 nF (ceramic)
-- V /V ≤ (V -- V /V
REF-- eREF--
(V
eREF+
)
),
REF-- eREF-- min
eREF+
E
Internal impedance of source R < 100 Ω,
±2
±4
Offset error
O
S
C
VREF+
= 10 μF (tantalum) and 100 nF (ceramic)
(V
C
-- V
/V
)
≤ (V
-- V /V
REF-- eREF--
),
),
eREF+
VREF+
REF-- eREF-- min
eREF+
E
E
2.2 V/3 V
2.2 V/3 V
±1.1
±2
±2
±5
LSB
LSB
Gain error
G
T
= 10 μF (tantalum) and 100 nF (ceramic)
-- V /V ≤ (V -- V /V
REF-- eREF--
= 10 μF (tantalum) and 100 nF (ceramic)
(V
)
eREF+
VREF+
REF-- eREF-- min
eREF+
Total unadjusted error
C
66
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC temperature sensor and built-in VMID
PARAMETER
TEST CONDITIONS
VCC
2.2 V
3 V
MIN
TYP
40
MAX UNIT
120
Operating supply current into
REFON = 0, INCH = 0Ah,
I
μA
SENSOR
AV terminal (see Note 1)
ADC12ON = 1, T = 25_C
CC
A
60
160
2.2 V
3 V
986
986
3.55
3.55
ADC12ON = 1, INCH = 0Ah,
†
V
See Note 2
mV
SENSOR
T
A
= 0°C
2.2 V
3 V
†
TC
ADC12ON = 1, INCH = 0Ah
mV/°C
SENSOR
2.2 V
3 V
30
30
Sample time required if channel
10 is selected (see Note 3)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
†
t
μs
SENSOR(sample)
VMID
2.2 V
3 V
NA
Current into divider at channel 11
(see Note 4)
I
ADC12ON = 1, INCH = 0Bh
ADC12ON = 1, INCH = 0Bh,
μA
NA
2.2 V
3 V
1.1
1.1±0.04
V
AV divider at channel 11
V
MID
CC
V
is ~0.5 x V
MID
AVCC
1.5 1.50±0.04
2.2 V
3 V
1400
1220
Sample time required if channel
11 is selected (see Note 5)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
t
ns
VMID(sample)
†
Limits characterized
NOTES: 1. The sensor current I
is consumed if (ADC12ON = 1 and REFON = 1) or if (ADC12ON = 1, INCH = 0Ah and sample signal
SENSOR
is high). When REFON = 1, I
is already included in I
.
SENSOR
REF+
2. The temperature sensor offset can be as much as ±20_C. A single-point calibration is recommended in order to minimize the offset
error of the built-in temperature sensor.
3. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t
.
SENSOR(on)
4. No additional current is needed. The V
is used during sampling.
MID
5. The on time t
is included in the sampling time t
; no additional on time is needed.
VMID(on)
VMID(sample)
67
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
12-bit DAC supply specifications
PARAMETER
TEST CONDITIONS
VCC
T
A
MIN TYP MAX UNIT
AV = DV
,
CC
CC
AV
Analog supply voltage
2.20
3.60
V
CC
AV = DV = 0 V
SS
SS
-- 4 0 °C to 85°C
105°C
50
69
110
150
DAC12AMPx = 2, DAC12IR = 0,
DAC12_xDAT = 0x0800
2.2V/3V
2.2V/3V
DAC12AMPx = 2, DAC12IR = 1,
DAC12_xDAT = x00800
50
130
440
,
V
eREF+
= V
= AV
REF+ CC
Supply current, single
DAC channel
I
μA
DAC12AMPx = 5, DAC12IR = 1,
DAC12_xDAT = 0x0800,
DD
(see Notes 1 and 2)
2.2V/3V
2.2V/3V
200
V
eREF+
= V
= AV
REF+ CC
DAC12AMPx = 7, DAC12IR = 1,
DAC12_xDAT = 0x0800,
700 1500
V
eREF+
= V
= AV
REF+ CC
DAC12_xDAT = 800h, V
= 1.5 V,
REF
REF
2.2V
3V
Power-supply rejection
ratio
∆AV = 100mV
CC
PSRR
70
dB
DAC12_xDAT = 800h, V
= 1.5 V or 2.5 V,
(see Notes 3 and 4)
∆AV = 100mV
CC
NOTES: 1. No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
2. Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input
specifications.
3. PSRR = 20 × log{∆AV /∆V
}
CC
DAC12_xOUT
4.
V
is applied externally. The internal reference is not used.
REF
68
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC linearity specifications (see Figure 41)
PARAMETER
TEST CONDITIONS
12-bit monotonic
= 1.5 V
VCC
MIN
TYP
MAX
UNIT
Resolution
12
bits
V
REF
2.2 V
3 V
DAC12AMPx = 7, DAC12IR = 1
= 2.5 V
INL
Integral nonlinearity (see Note 1)
±2.0
±8.0
LSB
LSB
V
REF
DAC12AMPx = 7, DAC12IR = 1
= 1.5 V
V
REF
2.2 V
3 V
DAC12AMPx = 7, DAC12IR = 1
= 2.5 V
Differential nonlinearity
(see Note 1)
DNL
±0.4
±1.0
±21
V
REF
DAC12AMPx = 7, DAC12IR = 1
= 1.5 V
V
REF
2.2 V
3 V
DAC12AMPx = 7, DAC12IR = 1
= 2.5 V
Offset voltage without calibration
(see Notes 1 and 2)
V
REF
DAC12AMPx = 7, DAC12IR = 1
= 1.5 V
E
O
mV
V
REF
2.2 V
3 V
DAC12AMPx = 7, DAC12IR = 1
= 2.5 V
Offset voltage with calibration
(see Notes 1 and 2)
±2.5
V
REF
DAC12AMPx = 7, DAC12IR = 1
Offset error temperature
coefficient (see Note 1)
d
/d
/d
2.2 V/3 V
30
10
μV/C
E(O)
T
T
V
V
= 1.5 V
= 2.5 V
2.2 V
3 V
REF
REF
E
Gain error (see Note 1)
±3.50 % FSR
G
Gain temperature
coefficient (see Note 1)
ppm of
FSR/°C
d
2.2 V/3 V
E(G)
DAC12AMPx = 2
100
Time for offset calibration
(see Note 3)
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
32
6
t
2.2 V/3 V
ms
Offset_Cal
NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and
“b” of the first order equation: y = a + b × x. V = E + (1 + E ) × (V /4095) × DAC12_xDAT, DAC12IR = 1.
DAC12_xOUT
O
G
eREF+
2. The offset calibration works on the output operational amplifier. Offset calibration is triggered setting bit DAC12CALON.
3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with
DAC12AMPx = {0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during
calibration may affect accuracy and is not recommended.
DAC V
OUT
DAC Output
V
R+
R
=
Load
Ideal transfer
function
AV
CC
2
Offset Error
Positive
Gain Error
DAC Code
C
= 100pF
Load
Negative
Figure 41. Linearity Test Load Conditions and Gain/Offset Definition
69
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
typical characteristics -- 12-bit DAC, linearity specifications
TYPICAL INL ERROR
vs
DIGITAL INPUT DATA
4
V
= 2.2 V, V
= 1.5V
REF
CC
DAC12AMPx = 7
DAC12IR = 1
3
2
1
0
-- 1
-- 2
-- 3
-- 4
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT -- Digital Code
TYPICAL DNL ERROR
vs
DIGITAL INPUT DATA
2.0
1.5
V
= 2.2 V, V
= 1.5V
REF
CC
DAC12AMPx = 7
DAC12IR = 1
1.0
0.5
0.0
-- 0 . 5
-- 1 . 0
-- 1 . 5
-- 2 . 0
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT -- Digital Code
70
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC output specifications
PARAMETER
TEST CONDITIONS
No Load, Ve = AV
VCC
MIN
TYP
MAX UNIT
,
CC
REF+
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
0
0.005
No Load, Ve
= AV
,
CC
REF+
DAC12_xDAT = 0FFFh,
DAC12IR = 1, DAC12AMPx = 7
AV --0.05
AV
CC
CC
Output voltage range
(see Note 1 and Figure 44)
V
2.2 V/3 V
V
O
R
Load
= 3 kΩ, Ve = AV
,
CC
REF+
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
0
0.1
R = 3 kΩ, Ve
Load
= AV
,
CC
REF+
DAC12_xDAT = 0FFFh, DAC12IR =
1, DAC12AMPx = 7
AV --0.13
AV
CC
CC
Max DAC12 load
capacitance
C
2.2 V/3 V
100
pF
L(DAC12)
2.2V
3V
-- 0 . 5
-- 1 . 0
+0.5
+1.0
I
Max DAC12 load current
mA
L(DAC12)
R
= 3 kΩ, V
= 0 V,
O/P(DAC12)
Load
150
150
250
DAC12AMPx = 7, DAC12_xDAT = 0h
R
Load
= 3 kΩ, V = AV
,
CC
O/P(DAC12)
DAC12AMPx = 7,
DAC12_xDAT = 0FFFh
250
Output resistance
(see Figure 44)
R
2.2 V/3 V
Ω
O/P(DAC12)
R = 3 kΩ,
Load
0.3 V < V
< AV -- 0 . 3 V,
1
4
O/P(DAC12)
CC
DAC12AMPx = 7
NOTE 1: Data is valid after the offset calibration of the output amplifier.
R
O/P(DAC12_x)
Max
R
Load
I
Load
AV
CC
DAC12
2
C
= 100pF
O/P(DAC12_x)
Min
Load
0.3
AV
--0.3V
V
CC
OUT
AV
CC
Figure 44. DAC12_x Output Resistance Tests
71
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC reference input specifications
PARAMETER
TEST CONDITIONS
DAC12IR = 0, (see Notes 1 and 2)
DAC12IR = 1, (see Notes 3 and 4)
DAC12_0 IR = DAC12_1 IR = 0
DAC12_0 IR = 1, DAC12_1 IR = 0
DAC12_0 IR = 0, DAC12_1 IR = 1
VCC
MIN
TYP
MAX UNIT
AV /3 AV +0.2
CC
CC
Reference input voltage
range
Ve
2.2 V/3 V
V
REF+
AVcc AVcc+0.2
20
40
MΩ
48
24
56
28
Ri
,
Reference input
resistance
(VREF+)
2.2 V/3 V
Ri
(VeREF+)
kΩ
DAC12_0 IR = DAC12_1 IR = 1
DAC12_0 SREFx = DAC12_1 SREFx
(see Note 5)
20
NOTES: 1. For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AV ).
CC
2. The maximum voltage applied at reference input voltage terminal Ve
= [AV -- V
] / [3*(1 + E )].
E(O) G
REF+
CC
3. For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AV ).
CC
4. The maximum voltage applied at reference input voltage terminal Ve
= [AV -- V
] / (1 + E ).
E(O) G
REF+
CC
5. When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
12-bit DAC dynamic specifications, Vref = VCC, DAC12IR = 1 (see Figure 45 and Figure 46)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
60
15
6
MAX
120
30
UNIT
DAC12AMPx = 0 → {2, 3, 4}
DAC12_xDAT = 800h,
Error < ±0.5 LSB
V(O)
DAC12AMPx = 0 → {5, 6}
DAC12AMPx = 0 → 7
DAC12AMPx = 2
t
DAC12 on-time
2.2 V/3 V
μs
ON
(see Note 1 and
Figure 45)
12
100
40
15
5
200
80
Settling time,
full scale
DAC12_xDAT =
80h→ F7Fh→ 80h
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
DAC12AMPx = 2
t
t
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
μs
μs
S(FS)
30
DAC12_xDAT =
Settling time,
code to code
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
DAC12AMPx = 2
2
3F8h→ 408h→ 3F8h
BF8h→ C08h→ BF8h
S(C-C)
1
0.05
0.35
1.5
0.12
0.7
2.7
600
150
30
DAC12_xDAT =
80h→ F7Fh→ 80h
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
DAC12AMPx = 2
SR
Slew rate
V/μs
nV-s
Glitch energy,
full scale
DAC12_xDAT =
80h→ F7Fh→ 80h
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
NOTES: 1.
R
Load
and C
are connected to AV (not AV /2) in Figure 45.
Load SS CC
2. Slew rate applies to output voltage steps ≥ 200 mV.
Conversion 1
Conversion 2
Conversion 3
+/-- 1/2 LSB
V
+/-- 1/2 LSB
DAC Output
OUT
Glitch
Energy
R
= 3 kΩ
Load
I
Load
AV
CC
2
C
= 100pF
Load
R
O/P(DAC12.x)
t
t
settleHL
settleLH
Figure 45. Settling Time and Glitch Energy Testing
72
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Conversion 1
Conversion 2
Conversion 3
V
OUT
90%
90%
10%
10%
t
t
SRHL
SRLH
Figure 46. Slew Rate Testing
12-bit DAC, dynamic specifications (continued) (TA = 25°C, unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
40
3-dB bandwidth,
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
180
550
BW
2.2 V/3 V
kHz
V
= 1.5V, V = 0.1 V
--3dB
DC
AC PP
(see Figure 47)
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
DAC12_0DAT = 800h, No load,
DAC12_1DAT = 80h<-->F7Fh, R
= 3 kΩ,
-- 8 0
-- 8 0
Load
f
= 10 kHz, Duty cycle = 50%
DAC12_1OUT
Channel-to-channel crosstalk
(see Note 1 and Figure 48)
2.2 V/3 V
dB
DAC12_0DAT = 80h<-->F7Fh, R
DAC12_1DAT = 800h, No load,
= 3 kΩ,
Load
f
= 10 kHz, Duty cycle = 50%
DAC12_0OUT
NOTE 1:
R
LOAD
= 3 kΩ, C
= 100 pF
LOAD
R
= 3 kΩ
Load
I
Load
Ve
REF+
AV
CC
DAC12_x
2
DACx
AC
DC
C
= 100pF
Load
Figure 47. Test Conditions for 3-dB Bandwidth Specification
R
Load
I
Load
AV
DAC12_xDAT 080h
7F7h
080h
7F7h
080h
CC
DAC12_0
DAC12_1
2
DAC0
V
OUT
C
= 100pF
Load
V
V
V
DAC12_yOUT
DAC12_xOUT
REF+
R
Load
I
Load
AV
CC
e
2
f
DAC1
Toggle
C
= 100pF
Load
Figure 48. Crosstalk Test Conditions
73
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
flash memory
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX
UNIT
V
Program and erase supply voltage
Flash Timing Generator frequency
2.2
3.6
476
5
V
kHz
mA
CC(PGM/ERASE)
f
I
I
t
t
257
FTG
Supply current from DV during program
2.2 V/ 3.6 V
2.2 V/ 3.6 V
2.2 V/ 3.6 V
2.2 V/ 3.6 V
3
3
PGM
CC
Supply current from DV during erase
CC
7
mA
ERASE
Cumulative program time
See Note 1
See Note 2
4
ms
CPT
Cumulative mass erase time
Program/Erase endurance
Data retention duration
200
ms
CMErase
4
5
10
10
cycles
years
t
T = 25°C
J
100
Retention
t
t
t
t
t
t
Word or byte program time
Block program time for first byte or word
See Note 3
See Note 3
35
30
t
t
t
t
t
t
Word
FTG
FTG
FTG
FTG
FTG
FTG
Block, 0
Block program time for each additional byte or word See Note 3
21
Block, 1-63
Block, End
Mass Erase
Seg Erase
Block program end-sequence wait time
Mass erase time (see Note 4)
Segment erase time
See Note 3
See Note 3
See Note 3
6
10593
4819
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1 ms ( = 5297x1/f ,max = 5297 × 1/476 kHz). To
FTG
achieve the required cumulative mass erase time, the Flash Controller’s mass erase operation can be repeated until this time is met.
A worst case minimum of 19 cycles is required.
3. These values are hardwired into the Flash Controller’s state machine (t
= 1/f
).
FTG
FTG
4. To erase the complete code area, the mass erase must be performed once with a dummy address in the range of the lower 64-kB
flash addresses and once with the dummy address in the upper 64-kB flash addresses.
RAM
PARAMETER
TEST CONDITIONS
CPU halted
MIN
MAX
UNIT
VRAMh
See Note 1
1.6
V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
74
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
JTAG interface
TEST
CONDITIONS
PARAMETER
V
MIN
TYP
MAX
UNIT
CC
2.2 V
3 V
0
0
5
10
90
f
TCK input frequency
Internal pullup resistance on TMS, TCK, TDI/TCLK
See Note 1
See Note 2
MHz
TCK
R
2.2 V/ 3 V
25
60
kΩ
Internal
NOTES: 1.
f
may be restricted to meet the timing requirements of the module selected.
TCK
2. TMS, TDI/TCLK, and TCK pullup resistors are implemented in all versions.
JTAG fuse (see Note 1)
PARAMETER
Supply voltage during fuse-blow condition
Voltage level on TDI/TCLK for fuse blow (F versions)
Supply current into TDI/TCLK during fuse blow
Time to blow fuse
TEST CONDITIONS
MIN
2.5
6
MAX
UNIT
V
V
V
T
A
= 25°C
CC(FB)
FB
7
100
1
V
I
t
mA
ms
FB
FB
NOTE 1: Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
75
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
APPLICATION INFORMATION
Port P1 pin schematic: P1.0 to P1.7, input/output with Schmitt trigger
Pad Logic
P1REN.x
0
1
DVSS
DVCC
1
P1DIR.x
0
1
Direction
0: Input
1: Output
P1OUT.x
0
1
Module X OUT
P1.0/TACLK/CAOUT
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P1.5/TA0
P1SEL.x
P1IN.x
EN
P1.6/TA1
P1.7/TA2
Module X IN
P1IRQ.x
D
P1IE.x
EN
Set
Q
P1IFG.x
P1SEL.x
P1IES.x
Interrupt
Edge Select
76
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P1 (P1.0 to P1.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
P1DIR.x
P1SEL.x
P1.0/TACLK
0
P1.0 (I/O)
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
1
0
1
1
0
1
1
Timer_A3.TACLK
CAOUT
0
1
P1.1/TA0
P1.2/TA1
P1.3/TA2
1
2
3
P1.1 (I/O)
I: 0; O: 1
Timer_A3.CCI0A
Timer_A3.TA0
P1.2 (I/O)
0
1
I: 0; O: 1
Timer_A3.CCI0A
Timer_A3.TA0
P1.3 (I/O)
0
1
I: 0; O: 1
Timer_A3.CCI0A
Timer_A3.TA0
P1.4 (I/O)
0
1
P1.4/SMCLK
P1.5/TA0
4
5
I: 0; O: 1
SMCLK
1
P1.5 (I/O)
I: 0; O: 1
Timer_A3.CCI0A
Timer_A3.TA0
P1.6 (I/O)
0
1
P1.6/TA1
P1.7/TA2
6
7
I: 0; O: 1
Timer_A3.CCI0A
Timer_A3.TA1
P1.7 (I/O)
0
1
I: 0; O: 1
Timer_A3.CCI0A
Timer_A3.TA2
0
1
77
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P2 pin schematic: P2.0 to P2.4, P2.6, and P2.7, input/output with Schmitt trigger
Pad Logic
To
Comparator_A
From
Comparator_A
CAPD.x
P2REN.x
0
1
DVSS
DVCC
1
0
1
P2DIR.x
Direction
0: Input
1: Output
0
1
P2OUT.x
Module X OUT
P2.0/ACLK/CA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
Bus
Keeper
EN
P2SEL.x
P2IN.x
P2.4/CA1/TA2
P2.6/ADC12CLK/
DMAE0/CA6
EN
P2.7/TA0/CA7
D
Module X IN
P2IRQ.x
P2IE.x
EN
Set
Q
P2IFG.x
P2SEL.x
P2IES.x
Interrupt
Edge Select
78
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P2.0, P2.3, P2.4, P2.6 and P2.7 pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
X
FUNCTION
CAPD.x
P2DIR.x
P2SEL.x
P2.0/ACLK/CA2
0
P2.0 (I/O)
ACLK
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
I: 0; O: 1
0
1
X
0
1
1
X
0
1
1
X
0
1
X
0
X
1
0
1
1
X
0
1
X
1
CA2
X
P2.1/TAINCLK/CA3
1
2
P2.1 (I/O)
Timer_A3.INCLK
I: 0; O: 1
0
DV
1
SS
CA3
X
P2.2/CAOUT/TA0/
CA4
P2.2 (I/O)
CAOUT
TA0
I: 0; O: 1
1
0
CA4
X
P2.3/CA0/TA1
P2.4/CA1/TA2
3
4
6
P2.3 (I/O)
Timer_A3.TA1
CA0
I: 0; O: 1
1
X
P2.4 (I/O)
Timer_A3.TA2
CA1
I: 0; O: 1
1
X
P2.6/ADC12CLK/
DMAE0/CA6
P2.6 (I/O)
ADC12CLK
DMAE0
CA6
I: 0; O: 1
1
0
X
P2.7/TA0/CA7
7
P2.7 (I/O)
Timer_A3.TA0
CA7
I: 0; O: 1
1
X
NOTE: X: Don’t care
79
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P2 pin schematic: P2.5, input/output with Schmitt trigger
Pad Logic
To Comparator
From Comparator
CAPD.5
To DCO
in DCO
DCOR
P2REN.5
0
1
DVSS
DVCC
1
P2DIR.5
0
1
Direction
0: Input
1: Output
P2OUT.5
0
1
Module X OUT
P2.5/ROSC/CA5
Bus
Keeper
EN
P2SEL.x
P2IN.5
EN
Module X IN
P2IRQ.5
D
P2IE.5
EN
Set
Q
P2IFG.5
P2SEL.5
P2IES.5
Interrupt
Edge Select
Port P2.5 pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
P2.5/R /CA5
X
FUNCTION
CAPD
DCOR
P2DIR.5
P2SEL.5
5
P2.5 (I/O)
(see Note 2)
0
0
1
0
0
I: 0; O: 1
0
X
1
OSC
R
0
X
1
OSC
DV
0
SS
CA5
1 or selected
X
X
NOTES: 1. X: Don’t care
2. If Rosc is used it is connected to an external resistor.
80
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P3 pin schematic: P3.0 to P3.7, input/output with Schmitt trigger
Pad Logic
P3REN.x
0
1
DVSS
DVCC
1
P3DIR.x
0
1
Direction
0: Input
1: Output
Module
direction
P3OUT.x
0
1
Module X OUT
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.7/UCA1RXD/UCA1SOMI
P3SEL.x
P3IN.x
EN
D
Module X IN
Port P3.0 to P3.7 pin functions
CONTROL BITS / SIGNALS
PIN NAME (P3.X)
X
FUNCTION
P3DIR.x
P3SEL.x
P3.0/UCB0STE/
UCA0CLK
0
P3.0 (I/O)
I: 0; O: 1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
UCB0STE/UCA0CLK (see Note 2 and 4)
P3.1 (I/O)
X
P3.1/UCB0SIMO/
UCB0SDA
1
2
3
4
5
6
7
I: 0; O: 1
UCB0SIMO/UCB0SDA (see Note 2 and 3)
P3.2 (I/O)
X
P3.2/UCB0SOMI/
UCB0SCL
I: 0; O: 1
UCB0SOMI/UCB0SCL (see Note 2 and 3)
P3.3 (I/O)
X
P3.3/UCB0CLK/
UCA0STE
I: 0; O: 1
UCB0CLK/UCA0STE (see Note 2)
P3.4 (I/O)
X
P3.4/UCA0TXD/
UCA0SIMO
I: 0; O: 1
UCA0TXD/UCA0SIMO (see Note 2)
P3.5 (I/O)
X
P3.5/UCA0RXD/
UCA0SOMI
I: 0; O: 1
UCA0RXD/UCA0SOMI (see Note 2)
P3.6 (I/O)
X
I: 0; O: 1
X
P3.6/UCA1TXD/
UCA1SIMO
UCA1TXD/UCA1SIMO (see Note 2)
P3.7 (I/O)
P3.7/UCA1RXD/
UCA1SOMI
I: 0; O: 1
X
UCA1RXD/UCA1SOMI (see Note 2)
NOTES: 1. X: Don’t care
2. The pin direction is controlled by the USCI module.
3. In case the I2C functionality is selected the output drives only the logical 0 to V level.
SS
4. UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output USCI A0/B0 will
be forced to 3-wire SPI mode if 4-wire SPI mode is selected.
81
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P4 pin schematic: P4.0 to P4.7, input/output with Schmitt trigger
Pad Logic
P4REN.x
0
1
DVSS
DVCC
1
P4DIR.x
0
1
Direction
0: Input
1: Output
P4OUT.x
0
1
Module X OUT
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
P4.5/TB5
P4.6/TB6
P4.7/TBCLK
P4SEL.x
P4IN.x
EN
D
Module X IN
Port P4.0 to P4.7 pin functions
CONTROL BITS / SIGNALS
PIN NAME (P4.X)
X
FUNCTION
P4DIR.x
P4SEL.x
P4.0/TB0
0
P4.0 (I/O)
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
Timer_B7.CCI0A and Timer_B7.CCI0B
Timer_B7.TB0
0
1
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
P4.5/TB5
P4.6/TB6
P4.7/TBCLK
1
2
3
4
5
6
7
P4.1 (I/O)
I: 0; O: 1
Timer_B7.CCI1A and Timer_B7.CCI1B
Timer_B7.TB1
0
1
P4.2 (I/O)
I: 0; O: 1
Timer_B7.CCI2A and Timer_B7.CCI2B
Timer_B7.TB2
0
1
P4.3 (I/O)
I: 0; O: 1
Timer_B7.CCI3A and Timer_B7.CCI3B
Timer_B7.TB3
0
1
P4.4 (I/O)
I: 0; O: 1
Timer_B7.CCI4A and Timer_B7.CCI4B
Timer_B7.TB4
0
1
P4.5 (I/O)
I: 0; O: 1
Timer_B7.CCI5A and Timer_B7.CCI5B
Timer_B7.TB5
0
1
P4.6 (I/O)
I: 0; O: 1
Timer_B7.CCI6A and Timer_B7.CCI6B
Timer_B7.TB6
0
1
I: 0; O: 1
1
P4.7 (I/O)
Timer_B7.TBCLK
82
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P5 pin schematic: P5.0 to P5.7, input/output with Schmitt trigger
Pad Logic
P5REN.x
0
1
DVSS
DVCC
1
P5DIR.x
0
1
Direction
0: Input
1: Output
Module
Direction
P5OUT.x
0
1
Module X OUT
P5.0/UCB1STE/UCA1CLK
P5.1/UCB1SIMO/UCB1SDA
P5.2/UCB1SOMI/UCB1SCL
P5.3/UCB1CLK/UCA1STE
P5.4/MCLK
P5SEL.x
P5IN.x
P5.5/SMCLK
P5.6/ACLK
P5.7/TBOUTH/SVSOUT
EN
D
Module X IN
Port P5.0 to P5.7 pin functions
CONTROL BITS / SIGNALS
PIN NAME (P5.X)
X
FUNCTION
P5DIR.x
P5SEL.x
P5.0/UCB1STE/
UCA1CLK
0
P5.0 (I/O)
I: 0; O: 1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
UCB1STE/UCA1CLK (see Note 2 and 4)
X
P5.1/UCB1SIMO/
UCB1SDA
1
2
3
4
5
6
7
P5.1 (I/O)
I: 0; O: 1
UCB1SIMO/UCB1SDA (see Note 2 and 3)
X
P5.2/UCB1SOMI/
UCB1SCL
P5.2 (I/O)
I: 0; O: 1
UCB1SOMI/UCB1SCL (see Note 2 and 3)
X
P5.3/UCB1CLK/
UCA1STE
P5.3 (I/O)
I: 0; O: 1
UCB1CLK/UCA1STE (see Note 2)
X
P5.4/MCLK
P5.5/SMCLK
P5.6/ACLK
P5.0 (I/O)
MCLK
I: 0; O: 1
1
P5.1 (I/O)
SMCLK
I: 0; O: 1
1
P5.2 (I/O)
ACLK
I: 0; O: 1
1
P5.7/TBOUTH/
SVSOUT
P5.7 (I/O)
TBOUTH
SVSOUT
I: 0; O: 1
0
1
NOTES: 1. X: Don’t care
2. The pin direction is controlled by the USCI module.
3. In case the I2C functionality is selected the output drives only the logical 0 to V level.
SS
4. UCA1CLK function takes precedence over UCB1STE function. If the pin is required as UCA1CLK input or output USCI A1/B1 will
be forced to 3-wire SPI mode if 4-wire SPI mode is selected.
83
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P6 pin schematic: P6.0 to P6.4, input/output with Schmitt trigger
Pad Logic
ADC12 Ax
P6REN.x
0
1
DVSS
1
DVCC
P6DIR.x
0
1
Direction
0: Input
1: Output
P6OUT.x
0
1
Module X OUT
P6.0/A0
P6.1/A1
P6.2/A2
P6.3/A3
P6.4/A4
Bus
Keeper
EN
P6SEL.x
P6IN.x
EN
D
Module X IN
Port P6.0 to P6.4 pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
X
FUNCTION
P6DIR.x
P6SEL.x
P6.0/A0
0
P6.0 (I/O)
I: 0; O: 1
0
X
0
A0 (see Note 2)
P6.1 (I/O)
X
P6.1/A1
P6.2/A2
P6.3/A3
P6.4/A4
1
2
3
4
I: 0; O: 1
A1 (see Note 2)
P6.2 (I/O)
X
X
0
I: 0; O: 1
A2 (see Note 2)
P6.3 (I/O)
X
I: 0; O: 1
X
X
0
A3 (see Note 2)
P6.4 (I/O)
X
0
I: 0; O: 1
X
A4 (see Note 2)
X
NOTES: 1. X: Don’t care
2. The ADC12 channel Ax is connected to AVss internally if not selected.
84
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P6 pin schematic: P6.5 and P6.6, input/output with Schmitt trigger
Pad Logic
DAC12_0OUT
DAC12AMP > 0
ADC12 Ax
ADC12 Ax
P6REN.x
0
1
DVSS
DVCC
1
P6DIR.x
0
1
Direction
0: Input
1: Output
P6OUT.x
0
1
Module X OUT
P6.5/A5/DAC1
P6.6/A6/DAC0
Bus
Keeper
EN
P6SEL.x
P6IN.x
EN
D
Module X IN
Port P6.5 to P6.6 pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
X
FUNCTION
CAPD.x or
DAC12AMP > 0
P6DIR.x
P6SEL.x
P6.5/A5/DAC1†
5
P6.5 (I/O)
DV
I: 0; O: 1
0
1
0
0
1
1
0
0
1
1
1
SS
A5 (see Note 2)
X
X
X
0
DAC1 (DA12OPS= 1, see Note 3)
P6.6 (I/O)
X
P6.6/A6/DAC0†
6
I: 0; O: 1
DV
1
X
X
1
SS
A6 (see Note 2)
X
X
DAC0 (DA12OPS= 0, see Note 3)
†
MSP430F261x devices only
NOTES: 1. X: Don’t care
2. The ADC12 channel Ax is connected to AVss internally if not selected.
3. The DAC outputs are floating if not selected.
85
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P6 pin schematic: P6.7, input/output with Schmitt trigger
Pad Logic
to SVS Mux
VLD = 15
DAC12_0OUT
DAC12AMP > 0
ADC12 A7
from ADC12
P6REN.7
0
1
DVSS
1
DVCC
P6DIR.7
0
1
Direction
0: Input
1: Output
P6OUT.7
0
1
Module X OUT
P6.7/A7/DAC1/SVSIN
Bus
Keeper
EN
P6SEL.7
P6IN.7
EN
D
Module X IN
Port P6.7 pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
X
FUNCTION
P6DIR.x
P6SEL.x
P6.7/A7/DAC1†/
SVSIN†
7
P6.7 (I/O)
I: 0; O: 1
0
1
DV
1
X
X
X
SS
A7 (see Note 2)
X
X
X
DAC1 (DA12OPS= 0, see Note 3)
SVSIN (VLD = 15)
NOTES: 1. X: Don’t care
2. The ADC12 channel Ax is connected to AVss internally if not selected.
3. The DAC outputs are floating if not selected.
MSP430F261x devices only
†
86
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P7 pin schematic: P7.0 to P7.7, input/output with Schmitt trigger†
Pad Logic
P7REN.x
0
1
DVSS
DVCC
1
P7DIR.x
0
0
1
Direction
0: Input
1: Output
P7OUT.x
VSS
0
1
P7.x
P7SEL.x
P7IN.x
EN
D
Module X IN
Port P7.0 to P7.7 pin functions†
CONTROL BITS / SIGNALS
PIN NAME (P7.X)
P7.0
X
FUNCTION
P7DIR.x
P7SEL.x
0
P7.0 (I/O)
Input
I: 0; O: 1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
P7.1
1
2
3
4
5
6
7
P7.1 (I/O)
Input
I: 0; O: 1
X
P7.2
P7.2 (I/O)
Input
I: 0; O: 1
X
P7.3
P7.3 (I/O)
Input
I: 0; O: 1
X
P7.4
P7.4 (I/O)
Input
I: 0; O: 1
X
P7.5
P7.5 (I/O)
Input
I: 0; O: 1
X
I: 0; O: 1
X
P7.6
P7.6 (I/O)
Input
P7.7
P7.7 (I/O)
Input
I: 0; O: 1
X
†
80-pin devices only
87
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P8 pin schematic: P8.0 to P8.5, input/output with Schmitt trigger†
Pad Logic
P8REN.x
0
1
DVSS
1
DVCC
P8DIR.x
0
0
1
Direction
0: Input
1: Output
P8OUT.x
VSS
0
1
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8SEL.x
P8IN.x
EN
D
Module X IN
Port P8.0 to P8.5 pin functions†
CONTROL BITS / SIGNALS
PIN NAME (P8.X)
P8.0
X
FUNCTION
P8DIR.x
P8SEL.x
0
P8.0 (I/O)
Input
I: 0; O: 1
0
1
0
1
0
1
0
1
0
1
0
1
X
P8.1
1
2
3
4
5
P8.1 (I/O)
Input
I: 0; O: 1
X
P8.2
P8.2 (I/O)
Input
I: 0; O: 1
X
P8.3
P8.3 (I/O)
Input
I: 0; O: 1
X
I: 0; O: 1
X
P8.4
P8.4 (I/O)
Input
P8.5
P8.5 (I/O)
Input
I: 0; O: 1
X
†
80-pin devices only
88
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P8 pin schematic: P8.6, input/output with Schmitt trigger†
BCSCTL3.XT2Sx = 11
0
XT2CLK
From
P8.7/XIN
P8.7/XIN
1
XT2 off
Pad Logic
P8SEL.7
P8REN.6
0
1
DVSS
DVCC
1
P8DIR.6
0
1
Direction
0: Input
1: Output
P8OUT.6
0
1
Module X OUT
P8.6/XOUT
Bus
Keeper
EN
P8SEL.6
P8IN.6
EN
D
Module X IN
Port P8.6 pin functions†
CONTROL BITS / SIGNALS
PIN NAME (P8.X)
X
FUNCTION
P8DIR.x
P8SEL.x
P8.6/XOUT
6
P8.6 (I/O)
I: 0; O: 1
0
1
1
XOUT (default)
0
1
DV
SS
†
80-pin devices only
89
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P8 pin schematic: P8.7, input/output with Schmitt trigger†
BCSCTL3.XT2Sx = 11
XT2 off
P8.6/XOUT
0
XT2CLK
1
P8SEL.6
P8REN.7
Pad Logic
0
1
DVSS
DVCC
0
1
P8DIR.7
0
1
Direction
0: Input
1: Output
P8OUT.7
0
1
Module X OUT
P8.7/XIN
Bus
Keeper
EN
P8SEL.7
P8IN.7
EN
D
Module X IN
Port P8.7 pin functions†
CONTROL BITS / SIGNALS
PIN NAME (P8.X)
X
FUNCTION
P8DIR.x
P8SEL.x
P8.7/XIN
7
P8.7 (I/O)
I: 0; O: 1
0
1
1
XIN (default)
0
1
V
SS
†
80-pin devices only
90
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
APPLICATION INFORMATION
JTAG pins: TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger
TDO
Controlled by JTAG
Controlled by JTAG
JTAG
TDO/TDI
Controlled
by JTAG
DV
DV
CC
CC
TDI
Fuse
Burn & Test
Fuse
Test
and
TDI/TCLK
DV
CC
Emulation
Module
TMS
TCK
TMS
TCK
DV
CC
During Programming Activity and
During Blowing of the Fuse, Pin
TDO/TDI Is Used to Apply the Test
Input Data for JTAG Circuitry
91
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
APPLICATION INFORMATION
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF, of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/TCLK pin to ground if the fuse is not burned.
Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see
Figure 49). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
I
TF
I
TDI/TCLK
Figure 49. Fuse Check Mode Current
92
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Data Sheet Revision History
LITERATURE
NUMBER
SUMMARY
SLAS541
Product Preview release.
Production Data release.
Corrected the format and the content shown on the first page.
Corrected pin number of P3.6 and P3.7 in 64-pin package in the terminal function list.
Corrected the port schematics.
SLAS541A
Corrected “calibration data” section (page 20). Typos and formatting corrected.
Added figure “typical characteristics -- LPM4 current” (page 33).
93
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
2-Nov-2007
PACKAGING INFORMATION
Orderable Device
MSP430F2416TPM
MSP430F2416TPMR
MSP430F2416TPN
MSP430F2416TPNR
MSP430F2417TPM
MSP430F2417TPMR
MSP430F2417TPN
MSP430F2417TPNR
MSP430F2418TPM
MSP430F2418TPMR
MSP430F2418TPN
MSP430F2418TPNR
MSP430F2419TPM
MSP430F2419TPMR
MSP430F2419TPN
MSP430F2419TPNR
MSP430F2616TPM
MSP430F2616TPMR
MSP430F2616TPN
MSP430F2616TPNR
MSP430F2617TPM
MSP430F2617TPMR
MSP430F2617TPN
MSP430F2617TPNR
MSP430F2618TPM
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
LQFP
PM
64
64
80
80
64
64
80
80
64
64
80
80
64
64
80
80
64
64
80
80
64
64
80
80
64
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
PM
PN
PN
PM
PM
PN
PN
PM
PM
PN
PN
PM
PM
PN
PN
PM
PM
PN
PN
PM
PM
PN
PN
PM
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
119 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
119 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
119 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
119 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
119 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
119 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Nov-2007
Orderable Device
MSP430F2618TPMR
MSP430F2618TPN
MSP430F2618TPNR
MSP430F2619TPM
MSP430F2619TPMR
MSP430F2619TPN
MSP430F2619TPNR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
LQFP
PM
64
80
80
64
64
80
80
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
PN
PN
PM
PM
PN
PN
119 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
119 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
0°–7°
11,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040152/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
60
M
0,08
41
61
40
0,13 NOM
80
21
1
20
Gage Plane
9,50 TYP
0,25
12,20
SQ
11,80
0,05 MIN
0°–7°
14,20
SQ
13,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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dsp.ti.com
www.ti.com/audio
Automotive
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Digital Control
Military
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
RFID
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lpw
Telephony
Low Power
Wireless
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
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