MSP430F423IPMR [TI]
MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器
| 型号： | MSP430F423IPMR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MIXED SIGNAL MICROCONTROLLER |
| 文件： | 总45页 (文件大小：912K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
D
D
Low Supply-Voltage Range, 1.8 V to 3.6 V
D
D
Supply Voltage Supervisor/Monitor With
Programmable Level Detection
Ultralow-Power Consumption:
− Active Mode: 400 μA at 1 MHz, 3.0 V
− Standby Mode: 1.6 μA
− Off Mode (RAM Retention): 0.1 μA
Five Power-Saving Modes
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
D
D
D
D
Bootstrap Loader in Flash Devices
Wake-Up From Standby Mode in Less
Than 6 μs
Frequency-Locked Loop, FLL+
Family Members Include:
− MSP430F423:
8KB + 256B Flash Memory,
256B RAM
− MSP430F425:
16KB + 256B Flash Memory,
512B RAM
− MSP430F427:
D
D
16-Bit RISC Architecture, 125-ns
Instruction Cycle Time
D
D
Three Independent 16-bit Sigma-Delta A/D
Converters With Differential PGA Inputs
16-Bit Timer_A With Three
Capture/Compare Registers
32KB + 256B Flash Memory,
1KB RAM
D
D
Integrated LCD Driver for 128 Segments
D
D
Available in 64-Pin Quad Flat Pack (QFP)
Serial Communication Interface (USART),
Asynchronous UART or Synchronous SPI
Selectable by Software
For Complete Module Descriptions, Refer
to the MSP430x4xx Family User’s Guide,
Literature Number SLAU056
D
Brownout Detector
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6 μs.
The MSP430F42x series are microcontroller configurations with three independent 16-bit sigma-delta A/D
converters, each with an integrated differential programmable gain amplifier input stage. Also included is a
built-in 16-bit timer, 128 LCD segment drive capability, hardware multiplier, and 14 I/O pins.
Typical applications include high resolution applications such as handheld metering equipment, weigh scales,
and energy meters.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2004−2007 Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
PLASTIC 64-PIN QFP
(PM)
MSP430F423IPM
MSP430F425IPM
MSP430F427IPM
−40°C to 85°C
pin designation{
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
P1.5/TACLK/ACLK/S28
DVCC
A0.0+
A0.0−
A1.0+
A1.0−
A2.0+
A2.0−
XIN
P1.6/SIMO0/S27
P1.7/SOMI0/S26
P2.0/TA2/S25
P2.1/UCLK0/S24
R33
R23
R13
R03
COM3
COM2
COM1
COM0
S23
S22
S21
2
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
3
4
5
6
7
8
MSP430F42x
XOUT
9
V
REF
10
11
12
13
14
15
16
P2.2/STE0
S0
S1
S2
S3
S4
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
†
Open connection recommended for all unused analog inputs.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
functional block diagram
DV
DV
AV
AV
SS
CC
SS
CC
XIN XOUT
P1
P2
8
6
ACLK
SMCLK
Oscillators
FLL+
Flash
RAM
Timer_A3
3 CC Reg
Port 1
Port 2
USART0
32KB
16KB
8KB
1KB
512B
256B
8 I/O
Interrupt
Capability
6 I/O
Interrupt
Capability
UART or
SPI
Function
MCLK
MAB
8 MHz
CPU
incl. 16
Registers
MDB
Emulation
Module
SD16
Hardware
Multiplier
POR/
SVS/
Brownout
Watchdog
WDT+
Basic
Timer 1
LCD
128
Segments
1,2,3,4 MUX
Three 16-bit
Sigma-Delta
A/D
MPY, MPYS
MAC,MACS
15/16-Bit
1 Interrupt
Vector
JTAG
Interface
Converters
f
LCD
RST/NMI
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
MSP430F42x Terminal Functions
TERMINAL
PN
I/O
DESCRIPTION
NAME
NO.
1
DV
Digital supply voltage, positive terminal.
CC
A0.0+
A0.0−
A1.0+
A1.0−
A2.0+
A2.0−
XIN
2
I
I
Internal connection to SD16 Channel 0, input 0 +. (see Note 1)
Internal connection to SD16 Channel 0, input 0 −. (see Note 1)
Internal connection to SD16 Channel 1, input 0 +. (see Note 1)
Internal connection to SD16 Channel 1, input 0 −. (see Note 1)
Internal connection to SD16 Channel 2, input 0 +. (see Note 1)
Internal connection to SD16 Channel 2, input 0 −. (see Note 1)
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
Output terminal of crystal oscillator XT1
3
4
I
5
I
6
I
7
I
8
I
XOUT
9
O
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O Input for an external reference voltage / internal reference voltage output (can be used as mid-voltage)
I/O General-purpose digital I/O / slave transmit enable—USART0/SPI mode
REF
P2.2/STE0
S0
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
LCD segment output 0
S1
LCD segment output 1
S2
LCD segment output 2
S3
LCD segment output 3
S4
LCD segment output 4
S5
LCD segment output 5
S6
LCD segment output 6
S7
LCD segment output 7
S8
LCD segment output 8
S9
LCD segment output 9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
COM0
COM1
COM2
COM3
R03
LCD segment output 10
LCD segment output 11
LCD segment output 12
LCD segment output 13
LCD segment output 14
LCD segment output 15
LCD segment output 16
LCD segment output 17
LCD segment output 18
LCD segment output 19
LCD segment output 20
LCD segment output 21
LCD segment output 22
LCD segment output 23
Common output, COM0−3 are used for LCD backplanes.
Common output, COM0−3 are used for LCD backplanes.
Common output, COM0−3 are used for LCD backplanes.
Common output, COM0−3 are used for LCD backplanes.
Input port of fourth positive (lowest) analog LCD level (V5)
NOTE 1: Open connection recommended for all unused analog inputs.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
MSP430F42x Terminal Functions (Continued)
TERMINAL
PN
I/O
DESCRIPTION
NAME
NO.
41
R13
R23
R33
I
I
Input port of third most positive analog LCD level (V4 or V3)
Input port of second most positive analog LCD level (V2)
Output port of most positive analog LCD level (V1)
42
43
O
General-purpose digital I/O / external clock input-USART0/UART or SPI mode, clock output—USART0/SPI
mode / LCD segment output 24 (See Note 1)
P2.1/UCLK0/S24
P2.0/TA2/S25
44
45
46
47
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O / Timer_A Capture: CCI2A input, Compare: Out2 output / LCD segment output
25 (See Note 1)
General-purpose digital I/O / slave out/master in of USART0/SPI mode / LCD segment output 26
(See Note 1)
P1.7/SOMI0/S26
P1.6/SIMO0/S27
General-purpose digital I/O / slave in/master out of USART0/SPI mode / LCD segment output 27
(See Note 1)
P1.5/TACLK/
ACLK/S28
General-purpose digital I/O / Timer_A and SD16 clock signal TACLK input / ACLK output (divided by 1,
2, 4, or 8) / LCD segment output 28 (See Note 1)
48
49
50
P1.4/S29
I/O General-purpose digital I/O / LCD segment output 29 (See Note 1)
P1.3/SVSOUT/
S30
I/O General-purpose digital I/O / SVS: output of SVS comparator / LCD segment output 30 (See Note 1)
General-purpose digital I/O / Timer_A, Capture: CCI1A, CCI1B input, Compare: Out1 output / LCD segment
output 31 (See Note 1)
P1.2/TA1/S31
51
52
I/O
General-purpose digital I/O / Timer_A, Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
P1.1/TA0/MCLK
I/O
P1.0/TA0
TDO/TDI
TDI/TCLK
TMS
53
54
55
56
57
58
59
60
61
I/O General-purpose digital I/O / Timer_A, Capture: CCI0A input, Compare: Out0 output / BSL transmit
I/O Test data output port. TDO/TDI data output or programming data input terminal.
I
I
I
I
Test data input or test clock input. The device protection fuse is connected to TDI.
Test mode select. TMS is used as an input port for device programming and test.
Test clock. TCK is the clock input port for device programming and test.
Reset input or nonmaskable interrupt input port
TCK
RST/NMI
P2.5/URXD0
P2.4/UTXD0
P2.3/SVSIN
I/O General-purpose digital I/O / receive data in—USART0/UART mode
I/O General-purpose digital I/O / transmit data out—USART0/UART mode
I/O General-purpose digital I/O / Analog input to brownout, supply voltage supervisor
Analog supply voltage, negative terminal. Supplies SD16, SVS, brownout, oscillator, and LCD resistive
divider circuitry.
AV
62
63
64
SS
DV
Digital supply voltage, negative terminal
SS
CC
Analog supply voltage, positive terminal. Supplies SD16, SVS, brownout, oscillator, and LCD resistive
AV
divider circuitry; must not power up prior to DV
.
CC
NOTE 1: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
short-form description
CPU
Program Counter
Stack Pointer
PC/R0
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
R4
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
R5
R6
R7
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
R8
R9
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
R10
R11
instruction set
R12
R13
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
R14
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
e.g. ADD R4,R5
R4 + R5 −−−> R5
e.g. CALL
e.g. JNE
R8
PC −−>(TOS), R8−−> PC
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
Register
S
D
SYNTAX
MOV Rs,Rd
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
OPERATION
D D
D D
R10 −−> R11
Indexed
MOV X(Rn),Y(Rm)
MOV EDE,TONI
M(2+R5)−−> M(6+R6)
M(EDE) −−> M(TONI)
M(MEM) −−> M(TCDAT)
M(R10) −−> M(Tab+R6)
Symbolic (PC relative) D D
Absolute
Indirect
D D MOV &MEM,&TCDAT
D
D
D
MOV @Rn,Y(Rm)
MOV @Rn+,Rm
MOV #X,TONI
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
Indirect
autoincrement
M(R10) −−> R11
R10 + 2−−> R10
Immediate
#45 −−> M(TONI)
NOTE: S = source
D = destination
6
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MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
operating modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D
Active mode (AM)
All clocks are active
Low-power mode 0 (LPM0)
−
D
−
CPU is disabled
ACLK and SMCLK remain active, MCLK is available to modules
FLL+ loop control remains active
D
D
Low-power mode 1 (LPM1)
−
CPU is disabled
ACLK and SMCLK remain active, MCLK is available to modules
FLL+ loop control is disabled
Low-power mode 2 (LPM2)
−
CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D
D
Low-power mode 3 (LPM3)
−
CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
Low-power mode 4 (LPM4)
−
CPU is disabled
ACLK is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
7
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MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh−0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External Reset
WDTIFG
KEYV
Reset
0FFFEh
15, highest
Watchdog
(see Note 1)
Flash memory
PC Out-of-Range (see Note 4)
NMI
Oscillator Fault
Flash memory access violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
0FFFAh
0FFF8h
14
13
12
SD16CCTLx SD16OVIFG,
SD16CCTLx SD16IFG
(see Notes 1 and 2)
SD16
Maskable
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
0FFECh
11
10
9
Watchdog Timer
USART0 Receive
USART0 Transmit
WDTIFG
URXIFG0
UTXIFG0
Maskable
Maskable
Maskable
8
7
Timer_A3
Timer_A3
TACCR0 CCIFG (see Note 2)
Maskable
Maskable
6
TACCR1 and TACCR2
CCIFGs, and TACTL TAIFG
(see Notes 1 and 2)
0FFEAh
5
P1IFG.0 to P1IFG.7
(see Notes 1 and 2)
I/O port P1 (eight flags)
Maskable
0FFE8h
4
0FFE6h
0FFE4h
3
2
P2IFG.0 to P2IFG.7
(see Notes 1 and 2)
I/O port P2 (eight flags)
Maskable
Maskable
0FFE2h
0FFE0h
1
Basic Timer1
BTIFG
0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.
4. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh) or from
within unused address ranges (from 0600h to 0BFFh).
8
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MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1 and 2
7
6
5
4
3
2
1
0
Address
0h
UTXIE0
URXIE0
ACCVIE
NMIIE
OFIE
WDTIE
rw–0
rw–0
rw–0
rw–0
rw–0
rw–0
WDTIE:
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
OFIE:
Oscillator-fault-interrupt enable
NMIIE:
Nonmaskable-interrupt enable
ACCVIE:
URXIE0:
UTXIE0:
Flash access violation interrupt enable
USART0: UART and SPI receive-interrupt enable
USART0: UART and SPI transmit-interrupt enable
7
6
5
4
3
2
1
0
Address
1h
BTIE
rw-0
BTIE:
Basic Timer1 interrupt enable
interrupt flag register 1 and 2
7
6
URXIFG0
rw–0
5
4
3
2
1
0
Address
02h
UTXIFG0
NMIIFG
OFIFG
WDTIFG
rw–(0)
rw–1
rw–0
rw–1
WDTIFG:
Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on V
power up or a reset condition at the RST/NMI pin in reset mode.
CC
OFIFG:
Flag set on oscillator fault
Set via RST/NMI pin
NMIIFG:
URXIFG0: USART0: UART and SPI receive flag
UTXIFG0: USART0: UART and SPI transmit flag
7
6
5
4
3
2
1
0
Address
3h
BTIFG
rw-0
BTIFG:
Basic Timer1 interrupt flag
9
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MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
module enable registers 1 and 2
7
6
5
4
3
2
1
0
Address
04h
UTXE0
URXE0
USPIE0
rw–0
rw–0
URXE0:
USART0: UART mode receive enable
USART0: UART mode transmit enable
UTXE0:
USPIE0:
USART0: SPI mode transmit and receive enable
7
6
5
4
3
2
1
0
Address
05h
Legend: rw−0,1:
rw−(0,1):
Bit Can Be Read and Written. It Is Reset or Set by PUC.
Bit Can Be Read and Written. It Is Reset or Set by POR.
SFR Bit Not Present in Device.
memory organization
MSP430F423
MSP430F425
16KB
MSP430F427
Memory
Size
8KB
32KB
Interrupt vector
Code memory
Flash
Flash
0FFFFh − 0FFE0h
0FFFFh − 0E000h
0FFFFh − 0FFE0h
0FFFFh − 0C000h
0FFFFh − 0FFE0h
0FFFFh − 08000h
Information memory
Boot memory
RAM
Size
Size
Size
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
1kB
1kB
1kB
0FFFh − 0C00h
0FFFh − 0C00h
0FFFh − 0C00h
256 Byte
512 Byte
1KB
02FFh − 0200h
03FFh − 0200h
05FFh − 0200h
Peripherals
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
BSL Function
Data Transmit
Data Receive
PM Package Pins
53 - P1.0
52 - P1.1
10
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MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D
Flash memory has n segments of main memory and two segments of information memory (A and B) of
128 bytes each. Each segment in main memory is 512 bytes in size.
D
D
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A and B can be erased individually, or as a group with segments 0−n.
Segments A and B are also called information memory.
D
New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
8KB
16KB
32KB
0FFFFh 0FFFFh
0FFFFh
Segment 0
With Interrupt Vectors
0FE00h 0FE00h
0FDFFh 0FDFFh
0FE00h
0FDFFh
Segment 1
Segment 2
0FC00h 0FC00h
0FBFFh 0FBFFh
0FC00h
0FBFFh
0FA00h 0FA00h
0F9FFh 0F9FFh
0FA00h
0F9FFh
Main Memory
0C400h 08400h
0C3FFh 083FFh
0E400h
0E3FFh
Segment n−1
Segment n
Segment A
Segment B
0C200h 08200h
0C1FFh 081FFh
0E200h
0E1FFh
0C000h 08000h
010FFh 010FFh
0E000h
010FFh
01080h 01080h
0107Fh 0107Fh
01080h
0107Fh
Information Memory
01000h 01000h
01000h
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, TI literature
number SLAU056.
oscillator and system clock
The clock system in the MSP430F42x family of devices is supported by the FLL+ module that includes support
for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a high frequency
crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low
power consumption. The FLL+ features digital frequency locked loop (FLL) hardware that, in conjunction with
a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.
The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The FLL+ module
provides the following clock signals:
D
D
D
D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, V may not
CC
have ramped to V
at that time. The user must insure the default FLL+ settings are not changed until V
CC(min)
CC
reaches V
. If desired, the SVS circuit can be used to determine when V reaches V
.
CC(min)
CC
CC(min)
digital I/O
There are two 8-bit I/O ports implemented—ports P1 and P2 (only six P2 I/O signals are available on external
pins):
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of port P1 and six bits of P2.
Read/write access to port-control registers is supported by all instructions.
NOTE:
Six bits of port P2 (P2.0 to P2.5) are available on external pins, but all control and data bits for port
P2 are implemented.
Basic Timer1
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and
clock for the LCD module.
LCD drive
The LCD driver generates the segment and common signals required to drive an LCD display. The LCD
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
WDT+ watchdog timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number Device Input Signal Module Input Name
Module Block
Module Output Signal
Output Pin Number
48 - P1.5
TACLK
ACLK
SMCLK
TACLK
TA0
TACLK
ACLK
Timer
NA
SMCLK
INCLK
CCI0A
CCI0B
GND
48 - P1.5
53 - P1.0
52 - P1.1
53 - P1.0
51 - P1.2
45 - P2.0
TA0
CCR0
CCR1
CCR2
TA0
TA1
TA2
DV
DV
SS
CC
V
CC
51 - P1.2
51 - P1.2
TA1
TA1
CCI1A
CCI1B
GND
DV
SS
CC
DV
V
CC
45 - P2.0
TA2
ACLK (internal)
CCI2A
CCI2B
GND
DV
DV
SS
CC
V
CC
USART0
The MSP430F42x devices have one hardware universal synchronous/asynchronous receive transmit
(USART0) peripheral module that is used for serial data communication. The USART supports synchronous
SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive
channels.
hardware multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16 16,
16 8, 8 16, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
SD16
The SD16 module integrates three independent 16-bit sigma-delta A/D converters, internal temperature sensor
and built-in voltage reference. Each channel is designed with a fully differential analog input pair and
programmable gain amplifier input stage.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog
Timer_A3
Watchdog Timer control
Timer_A interrupt vector
Timer_A control
WDTCTL
TAIV
0120h
012Eh
0160h
0162h
0164h
0166h
0170h
0172h
0174h
0176h
013Eh
013Ch
013Ah
0138h
0136h
0134h
0132h
0130h
012Ch
012Ah
0128h
0100h
0102h
0104h
0106h
0108h
010Ah
010Ch
010Eh
0110h
0112h
0114h
0116h
0118h
011Ah
011Ch
011Eh
TACTL
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Timer_A register
TACCTL0
TACCTL1
TACCTL2
TAR
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
Sum extend
TACCR0
TACCR1
TACCR2
SUMEXT
RESHI
Hardware Multiplier
Result high word
Result low word
RESLO
OP2
Second operand
Multiply signed + accumulate/operand1
Multiply + accumulate/operand1
Multiply signed/operand1
Multiply unsigned/operand1
Flash control 3
MACS
MAC
MPYS
MPY
Flash
FCTL3
Flash control 2
FCTL2
Flash control 1
FCTL1
SD16
General Control
SD16CTL
SD16CCTL0
SD16CCTL1
SD16CCTL2
(see also: Peripherals
with Byte Access)
Channel 0 Control
Channel 1 Control
Channel 2 Control
Reserved
Reserved
Reserved
Reserved
Interrupt vector word register
Channel 0 conversion memory
Channel 1 conversion memory
Channel 2 conversion memory
Reserved
SD16IV
SD16MEM0
SD16MEM1
SD16MEM2
Reserved
Reserved
Reserved
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
Channel 0 Input Control
SD16
SD16INCTL0
SD16INCTL1
SD16INCTL2
0B0h
0B1h
0B2h
0B3h
0B4h
0B5h
0B6h
0B7h
0B8h
0B9h
0BAh
0BBh
0BCh
0BDh
0BEh
0BFh
0A4h
:
(see also: Peripherals
with Word Access)
Channel 1 Input Control
Channel 2 Input Control
Reserved
Reserved
Reserved
Reserved
Reserved
Channel 0 preload
Channel 1 preload
Channel 2 preload
Reserved
SD16PRE0
SD16PRE1
SD16PRE2
Reserved
Reserved
Reserved
Reserved
LCD
LCD memory 20
:
LCDM20
:
LCD memory 16
LCD memory 15
:
LCDM16
LCDM15
:
0A0h
09Fh
:
LCD memory 1
LCD control and mode
Transmit buffer
Receive buffer
Baud rate
LCDM1
LCDCTL
U0TXBUF
U0RXBUF
U0BR1
U0BR0
U0MCTL
U0RCTL
U0TCTL
U0CTL
091h
090h
077h
076h
075h
074h
073h
072h
071h
070h
056h
054h
053h
052h
051h
050h
047h
046h
040h
USART0
Baud rate
Modulation control
Receive control
Transmit control
USART control
SVS control register
FLL+ Control1
FLL+ Control0
System clock frequency control
System clock frequency integrator
System clock frequency integrator
BT counter2
Brownout, SVS
FLL+ Clock
SVSCTL
FLL_CTL1
FLL_CTL0
SCFQCTL
SCFI1
SCFI0
Basic Timer1
BTCNT2
BTCNT1
BTCTL
BT counter1
BT control
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P2
Port P2 selection
P2SEL
P2IE
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
026h
025h
024h
023h
022h
021h
020h
005h
004h
003h
002h
001h
000h
Port P2 interrupt enable
Port P2 interrupt-edge select
Port P2 interrupt flag
Port P2 direction
P2IES
P2IFG
P2DIR
P2OUT
P2IN
Port P2 output
Port P2 input
Port P1
Port P1 selection
P1SEL
P1IE
Port P1 interrupt enable
Port P1 interrupt-edge select
Port P1 interrupt flag
Port P1 direction
P1IES
P1IFG
P1DIR
P1OUT
P1IN
Port P1 output
Port P1 input
Special Functions
SFR module enable 2
SFR module enable 1
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable2
SFR interrupt enable1
ME2
ME1
IFG2
IFG1
IE2
IE1
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
absolute maximum ratings†
Voltage applied at V to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to + 4.1 V
CC
SS
Voltage applied to any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.3 V
CC
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA
Storage temperature (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Storage temperature (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages referenced to V . The JTAG fuse-blow voltage, V , is allowed to exceed the absolute maximum rating. The voltage is
SS
FB
applied to the TDI/TCLK pin when blowing the JTAG fuse.
recommended operating conditions
PARAMETER
MIN
NOM
MAX UNITS
Supply voltage during program execution; SD16 disabled.
MSP430F42x
MSP430F42x
MSP430F42x
1.8
3.6
3.6
3.6
V
V
V
V
CC
(AV = DV = V ) (see Note 1)
CC CC CC
Supply voltage during program execution; SD16 disabled, SVS enabled, and
PORON = 1. V (AV = DV = V ) (see Note 1 and Note 2)
2.0
2.7
CC
CC
CC
CC
Supply voltage during program execution; SD16 enabled or
during programming of flash memory. V (AV = DV = V )
CC
CC
CC
CC
Supply voltage, V (AV = DV = V )
SS
0
0
V
SS
SS
SS
Operating free-air temperature range, T
MSP430F42x
Watch crystal
Ceramic resonator
Crystal
−40
85
°C
A
LF selected, XTS_FLL=0
XT1 selected, XTS_FLL=1
XT1 selected, XTS_FLL=1
32768
Hz
450
1000
DC
8000
8000
4.15
8
kHz
kHz
LFXT1 crystal frequency, f
(see Note 3)
(LFXT1)
V
V
= 1.8 V
= 3.6 V
CC
Processor frequency (signal MCLK), f
MHz
(System)
DC
CC
NOTES: 1. It is recommended to power AV and DV from the same source. A maximum difference of 0.3 V between AV and DV can
CC
CC
CC
CC
be tolerated during power up and operation.
2. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing supply voltage.
POR is going inactive when the supply voltage is raised above minimum supply voltage plus the hysteresis of the SVS circuitry.
3. The LFXT1 oscillator in LF-mode requires a watch crystal.
f (MHz)
8 MHz
Supply Voltage Range with SD16
Enabled or During Programming
of the Flash Memory
Supply Voltage Range
During Program
Execution
6 MHz
4.15 MHz
1.8 V
2.7 V 3 V
3.6 V
V
CC
− Supply Voltage − V
Figure 1. Frequency vs Supply Voltage
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AV + DV excluding external current (see Note 1)
CC
CC
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
Active mode,
f
f
= f
= f = 1 MHz,
(DCO)
(MCLK)
(SMCLK)
I
T = −40°C to 85°C
A
V
CC
= 3 V
400
500
μA
(AM)
= 32,768 Hz, XTS_FLL = 0
(ACLK)
(program executes in flash)
Low-power mode, (LPM0/LPM1)
f
f
= f
= f
= 1 MHz,
(MCLK)
(SMCLK)
(DCO)
I
I
T = −40°C to 85°C
V
V
= 3 V
= 3 V
130
150
μA
μA
(LPM0)
A
CC
= 32,768 Hz, XTS_FLL = 0
(ACLK)
FN_8=FN_4=FN_3=FN_2=0 (see Note 2)
Low-power mode, (LPM2) (see Note 2)
T = −40°C to 85°C
A
10
1.5
1.6
1.7
2.0
0.1
0.1
0.8
22
2.0
2.1
2.2
2.6
0.5
0.5
2.5
(LPM2)
CC
T = −40°C
A
T = 25°C
A
I
Low-power mode, (LPM3) (see Note 2)
Low-power mode, (LPM4) (see Note 2)
V
= 3 V
= 3 V
μA
μA
(LPM3)
CC
CC
T = 60°C
A
T = 85°C
A
T = −40°C
A
T = 25°C
A
I
V
(LPM4)
T = 85°C
A
NOTES: 1. All inputs are tied to 0 V or V . Outputs do not source or sink any current.
CC
The current consumption in LPM2, LPM3, and LPM4 are measured with active Basic Timer1 and LCD (ACLK selected).
The current consumption of the SD16 and the SVS module are specified in their respective sections.
LPMx currents measured with WDT disabled.
The currents are characterized with a KDS Daishinku DT−38 (6 pF) crystal.
2. Current for brownout included.
current consumption of active mode versus system frequency
I
= I
× f
(AM)
(AM) [1 MHz] (System) [MHz]
current consumption of active mode versus supply voltage
I
= I + 170 μA/V × (V – 3 V)
(AM) [3 V] CC
(AM)
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Schmitt-trigger inputs − Ports P1 and P2; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER
Positive-going input threshold voltage
Negative-going input threshold voltage
TEST CONDITIONS
MIN
1.5
TYP
TYP
MAX
1.98
1.3
1
UNIT
V
V
V
V
CC
V
CC
V
CC
= 3 V
= 3 V
= 3 V
V
V
V
IT+
IT−
hys
0.9
Input voltage hysteresis (V − V
)
IT−
0.45
IT+
inputs Px.x, TAx
PARAMETER
TEST CONDITIONS
V
CC
MIN
1.5
50
MAX
UNIT
cycle
ns
3 V
3 V
Port P1, P2: P1.x to P2.x, External trigger signal
for the interrupt flag, (see Note 1)
t
External interrupt timing
(int)
t
f
f
Timer_A, capture timing
TAx
3 V
3 V
3 V
50
ns
(cap)
Timer_A clock frequency
externally applied to pin
TACLK, INCLK t = t
(L)
10
10
MHz
(TAext)
(H)
Timer_A clock frequency
SMCLK or ACLK signal selected
MHz
(TAint)
NOTES: 1. The external signal sets the interrupt flag every time the minimum t
cycle and time parameters are met. It may be set even with
(int)
trigger signals shorter than t . Both the cycle and timing specifications must be met to ensure the flag is set. t
is measured in
(int)
(int)
MCLK cycles.
leakage current (see Note 1)
PARAMETER
TEST CONDITIONS
(see Note 2)
MIN NOM
MAX
UNIT
I
I
Port P1 Port 1: V
Port P2 Port 2: V
50
50
lkg(P1.x)
(P1.x)
Leakage
current
V
CC
= 3 V
nA
(see Note 2)
lkg(P2.x)
(P2.x)
NOTES: 1. The leakage current is measured with V or V applied to the corresponding pin(s), unless otherwise noted.
SS
CC
2. The port pin must be selected as an input.
outputs − Ports P1 and P2
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
I
I
I
= −1.5 mA,
= −6 mA,
= 1.5 mA,
= 6 mA,
V
CC
V
CC
V
CC
V
CC
= 3 V,
= 3 V,
= 3 V,
= 3 V,
See Note 1
See Note 2
See Note 1
See Note 2
V
−0.25
V
OH(max)
OH(max)
OL(max)
OL(max)
CC
CC
CC
V
V
High-level output voltage
V
OH
V
−0.6
V
CC
V
SS
V
SS
V
+0.25
SS
Low-level output voltage
V
OL
V
+0.6
SS
NOTES: 1. The maximum total current, I
and I
for all outputs combined, should not exceed 12 mA to satisfy the
OH(max)
OL(max),
maximum specified voltage drop.
2. The maximum total current, I
and I
for all outputs combined, should not exceed 48 mA to satisfy the
OH(max)
OL(max),
maximum specified voltage drop.
output frequency
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
C = 20 pF,
I = 1.5mA
L
L
f
(1 ≤ x ≤ 2, 0 ≤ y ≤ 7)
V
CC
= 3 V
DC
12
MHz
Px.y
f
f
f
ACLK,
MCLK,
SMCLK
P1.1/TA0/MCLK
P1.5/TACLK/ACLK/S28
C = 20 pF
L
V
CC
= 3 V
12
MHz
f
f
f
= f
= f
= f
= f
= f
40%
30%
60%
70%
ACLK
ACLK
ACLK
LFXT1
LFXT1
LFXT1
XT1
P1.5/TACLK/ACLK/
S28, C = 20 pF
LF
L
V
CC
= 3 V
50%
50%
t
Duty cycle of output frequency
Xdc
P1.1/TA0/MCLK,
C = 20 pF,
50%−
15 ns
50%+
15 ns
f
= f
DCOCLK
L
MCLK
V
CC
= 3 V
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1 and P2 (continued)
TYPICAL LOW-LEVEL OUTPUT CURRENT
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
30
25
20
15
10
5
50
40
30
20
10
0
V
P2.1
= 2.2 V
V
P2.1
= 3 V
CC
CC
T
A
= 25°C
T
A
= 25°C
T
A
= 85°C
T
A
= 85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OL
− Low-Level Output Voltage − V
V
OL
− Low-Level Output Voltage − V
Figure 2
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
0
−5
0
−10
−20
−30
−40
−50
V
P2.1
= 2.2 V
CC
V
P2.1
= 3 V
CC
−10
−15
−20
−25
−30
T
A
= 85°C
T
A
= 85°C
T
A
= 25°C
T
= 25°C
A
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OH
− High-Level Output Voltage − V
V
OH
− High-Level Output Voltage − V
Figure 4
Figure 5
NOTE:
One output loaded at a time
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER
TEST CONDITIONS
f = 1 MHz
MIN
TYP
TYP
MAX
UNIT
6
6
6
f = 2 MHz
f = 3 MHz
t
Delay time
V
CC
= 3 V
μs
d(LPM3)
RAM (see Note 1)
PARAMETER
TEST CONDITIONS
CPU halted (see Note 1)
MIN
MAX
UNIT
VRAMh
1.6
V
NOTE 1: This parameter defines the minimum supply voltage when the data in the program memory RAM remain unchanged. No program
execution should take place during this supply voltage condition.
LCD
PARAMETER
TEST CONDITIONS
Voltage at R33
MIN
TYP
MAX
UNIT
V
V
V
V
I
2.5
V
+0.2
(33)
(23)
(13)
CC
Voltage at R23
(V −V ) × 2/3 + V
03
33
03
Analog voltage
Input leakage
V
= 3 V
V
CC
Voltage at R13
(V −V ) × 1/3 + V
(33) (03)
(03)
V
Voltage at R33/R03
2.5
V
+0.2
20
(33) − (03)
CC
R03 = V
No load at all
segment and
common lines,
(R03)
(R13)
(R23)
SS
I
I
R13 = V /3
20
20
nA
V
CC
R23 = 2 × V /3
V
CC
= 3 V
CC
V
(Sxx0)
V
(Sxx1)
V
(Sxx2)
V
(Sxx3)
V
V
V
− 0.1
(03)
(03)
(13)
(23)
(33)
V
V
V
− 0.1
− 0.1
+ 0.1
(13)
Segment line
voltage
I
= −3 μA,
V
CC
= 3 V
(Sxx)
V(
V(
23)
33)
USART0 (see Note 1)
PARAMETER
TEST CONDITIONS
= 3 V, SYNC = 0, UART mode
CC
MIN
NOM MAX
280 500
UNIT
t
τ
( )
USART0: deglitch time
V
150
ns
NOTE 1: The signal applied to the USART0 receive signal/terminal (URXD0) should meet the timing requirements of t to ensure that the URXS
(τ
)
flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t . The operating conditions to
(τ
)
set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the
URXD0 line.
POR brownout, reset (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
μs
t
2000
d(BOR)
V
V
V
dV /dt ≤ 3 V/s (see Figure 6)
0.7 × V
(B_IT−)
V
CC(start)
(B_IT−)
CC
dV /dt ≤ 3 V/s (see Figure 6, Figure 7, and Figure 8)
CC
1.71
180
V
Brownout
dV /dt ≤ 3 V/s (see Figure 6)
CC
70
2
130
mV
hys(B_IT−)
Pulse length needed at RST/NMI pin to accepted reset internally,
t
μs
(reset)
V
CC
= 3 V
NOTES: 1. The current consumption of the brownout module is already included in the I current consumption data. The voltage level
CC
V
+ V
is ≤ 1.8 V.
(B_IT−)
hys(B_IT−)
2. During power up, the CPU begins code execution following a period of t
after V = V
+ V
.
d(BOR)
CC
(B_IT−)
hys(B_IT−)
The default FLL+ settings must not be changed until V ≥ V
, where V
is the minimum supply voltage for the desired
CC
CC(min)
CC(min)
operating frequency. See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout/SVS circuit.
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
V
CC
V
hys(B_IT−)
V
(B_IT−)
V
CC(start)
1
0
t
d(BOR)
Figure 6. POR/Brownout Reset (BOR) vs Supply Voltage
V
CC
t
2
pw
3 V
V
= 3 V
cc
Typical Conditions
1.5
1
V
CC(drop)
0.5
0
0.001
1
1000
1 ns
1 ns
− Pulse Width − μs
t
− Pulse Width − μs
t
pw
pw
Figure 7. V
Level With a Square Voltage Drop to Generate a POR/Brownout Signal
CC(drop)
V
CC
t
pw
2
3 V
V
= 3 V
cc
Typical Conditions
1.5
1
V
CC(drop)
0.5
t = t
f
r
0
0.001
1
1000
t
t
t
r
f
− Pulse Width − μs
t
− Pulse Width − μs
pw
pw
Figure 8. V
Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
CC(drop)
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SVS (supply voltage supervisor/monitor) (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
150
2000
150
12
UNIT
dV /dt > 30 V/ms (see Figure 9)
5
CC
t
μs
(SVSR)4
dV /dt ≤ 30 V/ms
CC
t
t
SVSon, switch from VLD=0 to VLD ≠ 0, V = 3 V
20
μs
μs
V
d(SVSon)
CC
‡
VLD ≠ 0
settle
V
VLD ≠ 0, V /dt ≤ 3 V/s (see Figure 9)
1.55
120
1.7
(SVSstart)
CC
VLD = 1
70
155
mV
V
V
/dt ≤ 3 V/s (see Figure 9)
V
V
(SVS_IT−)
x 0.008
CC
(SVS_IT−)
x 0.004
VLD = 2 .. 14
V
hys(SVS_IT−)
/dt ≤ 3 V/s (see Figure 9), external voltage applied
CC
VLD = 15
4.4
10.4
mV
on P2.3
VLD = 1
VLD = 2
VLD = 3
VLD = 4
VLD = 5
VLD = 6
VLD = 7
VLD = 8
VLD = 9
VLD = 10
VLD = 11
VLD = 12
VLD = 13
VLD = 14
1.8
1.9
2.1
2.05
2.25
2.37
2.48
2.6
1.94
2.05
2.14
2.24
2.33
2.46
2.58
2.69
2.83
2.94
3.11
3.24
3.43
2.2
2.3
2.4
2.5
2.71
2.86
3
2.65
2.8
V
CC
/dt ≤ 3 V/s (see Figure 9)
V
V
(SVS_IT−)
2.9
3.13
3.29
3.42
3.05
3.2
†
3.35
3.5
3.61
†
3.76
†
†
3.7
3.99
V
/dt ≤ 3 V/s (see Figure 9), external voltage applied
CC
VLD = 15
1.1
1.2
10
1.3
15
on P2.3
I
CC(SVS)
VLD ≠ 0, V = 2.2 V/3 V
μA
CC
(see Note 1)
†
‡
The recommended operating voltage range is limited to 3.6 V.
is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
t
settle
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 1: The current consumption of the SVS module is not included in the I current consumption data.
CC
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Software Sets VLD>0:
SVS is Active
V
CC
(SVS_IT−)
V
hys(SVS_IT−)
V
V
(SVSstart)
V
hys(B_IT−)
V
(B_IT−)
V
CC(start)
Brownout
Region
Brownout
Region
Brownout
1
0
t
t
d(BOR)
SVS out
1
d(BOR)
SVS Circuit is Active From VLD > to V < V
CC
(B_IT−)
0
t
d(SVSon)
Set POR
1
t
d(SVSR)
Undefined
0
Figure 9. SVS Reset (SVSR) vs Supply Voltage
V
CC
t
pw
3 V
2
Rectangular Drop
1.5
1
V
CC(drop)
Triangular Drop
1 ns
1 ns
0.5
0
V
CC
t
pw
3 V
1
10
100
1000
t
− Pulse Width − μs
pw
V
CC(drop)
t = t
f
r
t
t
r
f
t − Pulse Width − μs
Figure 10. V
With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
CC(drop)
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
DCO
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
N
f
=01Eh, FN_8=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0,
= 32.768 kHz
(DCO)
Crystal
f
3 V
1
MHz
(DCOCLK)
f
f
f
f
f
f
f
f
f
f
FN_8=FN_4=FN_3=FN_2=0 ; DCOPLUS = 1
FN_8=FN_4=FN_3=FN_2=0; DCOPLUS = 1
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1
FN_8=0, FN_4= 1, FN_3= FN_2=x; DCOPLUS = 1
FN_8=0, FN_4=1, FN_3= FN_2=x; DCOPLUS = 1
FN_8=1, FN_4=FN_3=FN_2=x; DCOPLUS = 1
FN_8=1,FN_4=FN_3=FN_2=x; DCOPLUS = 1
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
0.3
2.7
0.8
6.5
1.3
10.3
2.1
16
0.7
6.1
1.3
11.3
2.5
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
(DCO=2)
(DCO=27)
(DCO=2)
(DCO=27)
(DCO=2)
(DCO=27)
(DCO=2)
(DCO=27)
(DCO=2)
(DCO=27)
1.5
12.1
2.2
20
3.5
17.9
3.4
28.5
5.2
26.6
6.3
41
4.2
30
9.2
46
70
1 < TAP ≤ 20
1.06
1.07
1.11
1.17
Step size between adjacent DCO taps:
S
n
S = f
/ f
, (see Figure 12 for taps 21 to 27)
n
DCO(Tap n+1) DCO(Tap n)
TAP = 27
Temperature drift, N
D = 2; DCOPLUS = 0
= 01Eh, FN_8=FN_4=FN_3=FN_2=0
(DCO)
D
D
3 V
–0.2
0
–0.3
5
–0.4
15
%/_C
t
Drift with V variation, N
= 01Eh, FN_8=FN_4=FN_3=FN_2=0
CC
(DCO)
%/V
V
D = 2; DCOPLUS = 0
f
f
(DCO)
(DCO)
f
f
5
(DCO3V)
(DCO20 C)
1.0
1.0
0
1.8
2.4
3.0
3.6
V
−40
−20
0
20
40
60
85
− V
T − °C
A
CC
Figure 11. DCO Frequency vs Supply Voltage V and vs Ambient Temperature
CC
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
1.17
Max
1.11
1.07
1.06
Min
1
20
27
DCO Tap
Figure 12. DCO Tap Step Size
Legend
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
9
5
2 to 2 in SCFI1 {N
}
{DCO}
Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_3=x
FN_4=x
FN_8=1
Figure 13. Five Overlapping DCO Ranges Controlled by FN_x Bits
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
OSCCAPx = 0h
OSCCAPx = 1h
OSCCAPx = 2h
OSCCAPx = 3h
OSCCAPx = 0h
OSCCAPx = 1h
OSCCAPx = 2h
OSCCAPx = 3h
V
CC
MIN
TYP
0
MAX
UNIT
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
10
14
18
0
Integrated input capacitance
(see Note 4)
C
pF
XIN
10
14
18
Integrated output capacitance
(see Note 4)
C
V
pF
V
XOUT
V
SS
0.2×V
CC
IL
Input levels at XIN
see Note 3
3 V
V
IH
0.8×V
V
CC
CC
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2pF. The effective load capacitor for the crystal is
(C x C ) / (C + C ). It is independent of XTS_FLL.
XIN
XOUT
XIN
XOUT
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines must be
observed:
• Keep as short a trace as possible between the ’F42x and the crystal.
• Design a good ground plane around oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to XIN an XOUT pins.
• Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
• Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation.
This signal is no longer required for the serial programming adapter.
3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.
4. External capacitance is recommended for precision real-time clock applications; OSCCAPx = 0h.
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16, power supply and recommended operating conditions
PARAMETER
TEST CONDITIONS
V
CC
MIN
2.7
TYP
MAX
UNIT
Analog supply
voltage
AV = DV
CC
CC
AV
3.6
V
CC
AV = DV = 0V
SS SS
GAIN: 1, 2
3 V
3 V
3 V
650
950
1100
1550
SD16LP = 0,
= 1 MHz,
SD16OSR = 256
Analog supply
current: 1 active
SD16 channel
including internal
reference
GAIN: 4, 8, 16
GAIN: 32
730
f
SD16
1050
ISD16
μA
SD16LP = 1,
GAIN: 1
3 V
3 V
3 V
3 V
620
700
1
930
f
= 0.5 MHz,
SD16
GAIN: 32
1060
SD16OSR = 256
Analog front-end
input clock
frequency
SD16LP = 0 (Low power mode disabled)
SD16LP = 1 (Low power mode enabled)
f
MHz
SD16
0.5
SD16, analog input range (see Note 1)
PARAMETER
TEST CONDITIONS
SD16GAINx = 1, SD16REFON = 1
V
CC
MIN
TYP
500
250
125
62
MAX
UNIT
SD16GAINx = 2, SD16REFON = 1
SD16GAINx = 4, SD16REFON = 1
SD16GAINx = 8, SD16REFON = 1
SD16GAINx = 16, SD16REFON = 1
SD16GAINx = 32, SD16REFON = 1
Differential input
voltage range for
specified
performance
(see Note 2)
V
ID
mV
31
15
Input impedance
(one input pin
f
f
f
f
= 1MHz, SD16GAINx = 1
= 1MHz, SD16GAINx = 32
= 1MHz, SD16GAINx = 1
= 1MHz, SD16GAINx = 32
3 V
3 V
3 V
3 V
200
75
SD16
SD16
SD16
SD16
Z
kΩ
kΩ
I
to AV
)
SS
Differential
input impedance
(IN+ to IN−)
300
400
150
Z
ID
100
AV
Absolute input
voltage range
-
SS
V
V
AV
AV
V
V
I
CC
1.0V
Common-mode
input voltage range
AV
SS
-
IC
CC
1.0V
NOTES: 1. All parameters pertain to each SD16 channel.
2. The analog input range depends on the reference voltage applied to V
. If V
is sourced externally, the full-scale range
REF
REF
is defined by V
= +(V
/2)/GAIN and V
= −(V /2)/GAIN. The analog input range should not exceed 80% of
REF
FSR+
REF
FSR−
V
FSR+
or V
.
FSR−
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16, analog performance (f
= 1MHz, SD16OSRx = 256, SD16REFON = 1)
SD16
PARAMETER
TEST CONDITIONS
V
MIN
83.5
81.5
76
TYP
85
MAX
UNIT
CC
SD16GAINx = 1,Signal Amplitude = 500mV
SD16GAINx = 2,Signal Amplitude = 250mV
SD16GAINx = 4,Signal Amplitude = 125mV
SD16GAINx = 8,Signal Amplitude = 62mV
SD16GAINx = 16,Signal Amplitude = 31mV
SD16GAINx = 32,Signal Amplitude = 15mV
SD16GAINx = 1
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
84
79.5
76.5
73
Signal-to-noise +
distortion ratio
f
= 50Hz,
IN
SINAD
dB
100Hz
73
69
62
69
0.97
1.90
3.76
7.36
1.00
1.96
3.86
7.62
1.02
2.02
3.96
7.84
SD16GAINx = 2
SD16GAINx = 4
G
Nominal gain
SD16GAINx = 8
SD16GAINx = 16
14.56 15.04 15.52
SD16GAINx = 32
27.20 28.35 29.76
SD16GAINx = 1
0.2
1.5
E
OS
Offset error
%FSR
SD16GAINx = 32
Offset error
temperature
coefficient
SD16GAINx = 1
3 V
3 V
4
20
ppm
FSR/_C
dE /dT
OS
SD16GAINx = 32
20
100
SD16GAINx = 1, Common-mode input signal:
3 V
3 V
>90
>75
V
ID
= 500 mV, f = 50 Hz, 100 Hz
IN
Common-mode
rejection ratio
CMRR
dB
SD16GAINx = 32, Common-mode input signal:
= 16 mV, f = 50 Hz, 100 Hz
V
ID
IN
AC power supply
rejection ratio
AC PSRR
SD16GAINx = 1, V = 3 V 100 mV, f
= 50 Hz
3 V
3 V
>80
dB
dB
CC
VCC
X
T
Crosstalk
<−100
SD16, built-in temperature sensor
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
Sensor temperature
coefficient
TC
1.18
1.32
1.46 mV/K
Sensor
Sensor offset
voltage
V
−100
100
mV
mV
Offset,sensor
Temperature sensor voltage at T = 85°C
3 V
3 V
3 V
435
355
320
475
395
360
515
435
400
A
Sensor output
voltage (see Note 2)
Temperature sensor voltage at T = 25°C
V
Sensor
A
Temperature sensor voltage at T = 0°C
A
NOTES: 1. The following formula can be used to calculate the temperature sensor output voltage:
= TC ( 273 + T [°C] ) + V [mV]
V
Sensor,typ
Sensor
Offset,sensor
2. Results based on characterization and/or production test, not TC
or V
.
Sensor
Offset,sensor
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16, built-in voltage reference
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
Internal reference
voltage
V
I
SD16REFON = 1, SD16VMIDON = 0
3 V
3 V
3 V
1.14
1.20
1.26
V
REF
Reference supply
current
SD16REFON = 1, SD16VMIDON = 0
SD16REFON = 1, SD16VMIDON = 0
SD16REFON = 1, SD16VMIDON = 0 (see Note 1)
SD16REFON = 0
175
20
260
μA
REF
Temperature
coefficient
TC
50 ppm/K
nF
V
REF
load
C
100
REF
capacitance
V
REF
maximum load
I
t
3 V
3 V
200
nA
ms
LOAD
current
Turn-on time
SD16REFON = 0 → 1, SD16VMIDON = 0, C
= 100 nF
5
ON
REF
DC power supply
rejection,
DC PSR
SD16REFON = 1, SD16VMIDON = 0, V = 2.5 V to 3.6 V
200
μV/V
CC
ΔV
/ΔV
REF
CC
NOTES: 1. There is no capacitance required on V . However, a capacitance of at least 100nF is recommended to reduce any reference
REF
voltage noise.
SD16, built-in reference output buffer
PARAMETER
TEST CONDITIONS
V
MIN
TYP
1.2
MAX
UNIT
CC
Reference buffer
V
SD16REFON = 1, SD16VMIDON = 1
3 V
V
REF,BUF
output voltage
Reference Supply +
Reference output
buffer quiescent
current
I
SD16REFON = 1, SD16VMIDON = 1
3 V
385
600
μA
REF,BUF
Required load
capacitance on
C
SD16REFON = 1, SD16VMIDON = 1
SD16REFON = 1, SD16VMIDON = 1
470
nF
REF(O)
V
REF
Maximum load
current on V
I
3 V
1
mA
LOAD,Max
REF
Maximum voltage
variation vs. load
current
|I
| = 0 to 1mA
3 V
3 V
−15
+15
mV
LOAD
t
Turn-on time
SD16REFON = 0 → 1, SD16VMIDON = 1, C
= 470 nF
100
μs
ON
REF
SD16, external reference input
PARAMETER
TEST CONDITIONS
SD16REFON = 0
V
MIN
1.0
TYP
1.25
MAX
1.5
UNIT
V
CC
V
REF(I)
Input voltage range
Input current
3 V
I
SD16REFON = 0
3 V
50
nA
REF(I)
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Flash Memory
TEST
CONDITIONS
PARAMETER
V
CC
MIN NOM
MAX
UNIT
V
CC(PGM/
ERASE)
Program and Erase supply voltage
Flash Timing Generator frequency
2.7
3.6
V
f
I
I
t
t
257
476
5
kHz
mA
FTG
Supply current from DV during program
2.7 V/ 3.6 V
2.7 V/ 3.6 V
2.7 V/ 3.6 V
2.7 V/ 3.6 V
3
PGM
CC
Supply current from DV during erase
3
7
mA
ERASE
CPT
CC
Cumulative program time
Cumulative mass erase time
Program/Erase endurance
Data retention duration
see Note 1
see Note 2
10
ms
200
ms
CMErase
4
5
10
100
10
cycles
years
t
T = 25°C
J
Retention
t
t
t
t
t
t
Word or byte program time
35
30
Word
st
Block program time for 1 byte or word
Block, 0
Block program time for each additional byte or word
Block program end-sequence wait time
Mass erase time
21
Block, 1-63
Block, End
Mass Erase
Seg Erase
see Note 3
t
FTG
6
5297
4819
Segment erase time
NOTES: 1. The cumulative programming time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all
programming methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/f ,max = 5297x1/476kHz). To
FTG
achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller’s state machine (t
= 1/f ).
FTG
FTG
JTAG Interface
TEST
CONDITIONS
PARAMETER
V
CC
MIN NOM
MAX
UNIT
2.2 V
3 V
0
0
5
10
90
MHz
MHz
kΩ
f
TCK input frequency
see Note 1
TCK
R
Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2
may be restricted to meet the timing requirements of the module selected.
2.2 V/ 3 V
25
60
Internal
NOTES: 1. f
TCK
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG Fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
V
CC
MIN NOM
MAX
UNIT
V
V
Supply voltage during fuse-blow condition
Voltage level on TDI/TCLK for fuse-blow
Supply current into TDI/TCLK during fuse-blow
Time to blow fuse
T = 25°C
A
2.5
6
V
V
CC(FB)
7
100
1
FB
I
FB
t
FB
mA
ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
APPLICATION INFORMATION
input/output schematic
Port P1, P1.0 to P1.1, input/output with Schmitt-trigger
Pad Logic
CAPD.x
P1SEL.x
0: Input
1: Output
0
P1DIR.x
Direction Control
1
0
1
From Module
P1OUT.x
Module X OUT
Bus
P1.0/TA0
P1.1/TA0/MCLK
keeper
P1IN.x
EN
D
Module X IN
P1IRQ.x
P1IE.x
EN
Interrupt
Edge
Select
Q
P1IFG.x
Set
P1IES.x P1SEL.x
NOTE: 0 ≤ x ≤ 1.
Port Function is Active if CAPD.x = 0
Direction
Module X
PnIN.x
OUT
CAPD.x
PnOUT.x
P1OUT.0
P1OUT.1
PnIE.x
PnIES.x
Control
Module X IN
PnSEL.x
P1SEL.0
P1SEL.1
Timer_A3
PnDIR.x
PnIFG.x
From Module
†
†
P1DIR.0
P1DIR.1
P1DIR.0
P1IN.0
P1IN.1
Out0 Sig.
MCLK
CCI0A
DVSS
DVSS
P1IE.0
P1IE.1
P1IFG.0
P1IFG.1
P1IES.0
P1IES.1
†
P1DIR.1
CCI0B
†
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
APPLICATION INFORMATION
input/output schematic (continued)
Port P1, P1.2 to P1.7, input/output with Schmitt-trigger
Pad Logic
Port/LCD
Segment xx
DVSS
P1SEL.x
0: Input
1: Output
0
P1DIR.x
Direction Control
1
0
1
From Module
P1OUT.x
Module X OUT
Bus
keeper
P1.2/TA1/S31
P1.3/SVSOUT/S30
P1.4/S29
P1.5/TACLK/ACLK/S28
P1.6/SIMO0/S27
P1.7/SOMI0/S26
P1IN.x
EN
D
Module X IN
P1IRQ.x
P1IE.x
EN
Interrupt
Edge
Select
Q
P1IFG.x
Set
P1IES.x P1SEL.x
NOTE: 2 ≤ x ≤ 7.
Port Function is Active if Port/LCD = 0
Direction
Module X
OUT
Segment
PnOUT.x
PnIE.x
PnIES.x
Control
PnIN.x
Module X IN
Port/LCD
PnSEL.x
PnDIR.x
PnIFG.x
From Module
†
†
S31
S30
S29
S28
S27
S26
P1SEL.2
P1SEL.3
P1SEL.4
P1DIR.2
P1DIR.3
P1DIR.4
P1DIR.2
P1DIR.3
P1DIR.4
P1OUT.2
P1OUT.3
P1OUT.4
Out1 Sig.
P1IN.2
P1IN.3
P1IN.4
CCI1A
P1IE.2
P1IE.3
P1IE.4
P1IE.5
P1IE.6
P1IE.7
P1IFG.2
P1IFG.3
P1IFG.4
P1IFG.5
P1IFG.6
P1IFG.7
P1IES.2
P1IES.3
P1IES.4
P1IES.5
P1IES.6
P1IES.7
0: LCDM
< 0E0h
1: LCDM
≥ 0E0h
unused
unused
SVSOUT
DVSS
†
TACLK
P1SEL.5
P1SEL.6
P1DIR.5
P1DIR.6
P1DIR.5
P1OUT.5
P1OUT.6
ACLK
P1IN.5
P1IN.6
0: LCDM
< 0C0h
1: LCDM
≥ 0C0h
‡
‡
DCM_SIMO
SIMO0(o)
SIMO0(i)
‡
SOMI0(o)
‡
P1SEL.7
P1DIR.7
DCM_SOMI
P1OUT.7
P1IN.7
SOMI0(i)
†
‡
Timer_A3
USART0
Direction Control for SIMO0
DCM_SIMO
Direction Control for SOMI0
DCM_SOMI
SYNC
MM
SYNC
MM
STC
STE
STC
STE
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.0 to P2.1, input/output with Schmitt-trigger
0: Port active
1: Segment xx function active
Pad Logic
Port/LCD
Segment xx
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
1
0
1
P2OUT.x
Module X OUT
Bus
Keeper
P2.0/TA2/S25
P2.1/UCLK0/S24
P2IN.x
EN
D
Module X IN
P2IRQ.x
P2IE.x
P2IFG.x
EN
Set
Interrupt
Edge
Select
Q
P2IES.x
P2SEL.x
NOTE: 0 ≤ x ≤ 1.
Port Function is Active if Port/LCD = 0
Dir. Control
from module
Module X
OUT
Segment
PnSel.x
PnDIR.x
PnOUT.x
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
Port/LCD
†
†
0: LCDM
< 0E0h
1: LCDM
≥ 0E0h
S25
S24
P2Sel.0
P2Sel.1
P2DIR.0
P2DIR.1
P2DIR.0
P2OUT.0
Out2sig.
P2IN.0
P2IN.1
CCI2A
P2IES.0
P2IES.1
P2IE.0
P2IE.1
P2IFG.0
P2IFG.1
‡
‡
DCM_UCLK P2OUT.1
UCLK0(o)
UCLK0(i)
†
‡
Timer_A3
USART0
Direction Control for UCLK0
DCM_UCLK
SYNC
MM
STC
STE
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.2 to P2.5, input/output with Schmitt-trigger
To BrownOut/SVS for P2.3/SVSIN
Pad Logic
DVSS
DVSS
CAPD.x
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
1
0
1
From Module
P2OUT.x
Module X OUT
Bus
keeper
P2.2/STE0
P2.3/SVSIN
P2.4/UTXD0
P2.5/URXD0
P2IN.x
EN
D
Module X IN
P2IRQ.x
P2IE.x
EN
Interrupt
Edge
Select
Q
P2IFG.x
Set
P2IES.x P2SEL.x
NOTE: 2 ≤ x ≤ 5
Port function is active if CAPD.x = 0
Direction
Module X
PnIN.x
OUT
PnOUT.x
PnIE.x
PnIES.x
Control
Module X IN
CAPD.x
PnSEL.x
PnDIR.x
PnIFG.x
From Module
†
DVSS
DVSS
DVSS
UTXD0
DVSS
P2SEL.2
P2SEL.3
P2SEL.4
P2DIR.2
P2DIR.3
P2DIR.4
DVSS
P2OUT.2
P2OUT.3
P2OUT.4
P2OUT.5
P2IN.2
P2IN.3
P2IN.4
P2IN.5
STE0
P2IE.2
P2IE.3
P2IE.4
P2IE.5
P2IFG.2
P2IFG.3
P2IFG.4
P2IFG.5
P2IES.2
P2IES.3
P2IES.4
P2IES.5
SVSCTL VLD
= 1111b
P2DIR.3
unused
unused
†
DVSS
DVSS
DVCC
DVSS
†
URXD0
P2SEL.5
P2DIR.5
†
USART0
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
APPLICATION INFORMATION
input/output schematic (continued)
Port P2, unbonded GPIOs P2.6 and P2.7
P2SEL.x
P2DIR.x
0: Input
1: Output
0
1
Direction Control
From Module
0
1
P2OUT.x
Module X OUT
P2IN.x
Node Is Reset With PUC
Bus Keeper
EN
Module X IN
D
P2IRQ.x
P2IE.x
PUC
Interrupt
Edge
Select
EN
Set
Q
P2IFG.x
Interrupt
Flag
P2IES.x
P2SEL.x
NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins
DIRECTION
P2Sel.x P2DIR.x
CONTROL
P2OUT.x MODULE X OUT P2IN.x
MODULE X IN
P2IE.x
P2IFG.x
P2IES.x
FROM MODULE
P2Sel.6 P2DIR.6
P2Sel.7 P2DIR.7
P2DIR.6
P2DIR.7
P2OUT.6
P2OUT.7
DV
DV
P2IN.6
P2IN.7
unused
unused
P2IE.6
P2IE.7
P2IFG.6
P2IFG.7
P2IES.6
P2IES.7
SS
SS
NOTE: Unbonded GPIOs 6 and 7 of port P2 can be used as interrupt flags. Only software can affect the interrupt flags. They work as software
interrupts.
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
APPLICATION INFORMATION
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
TDO
Controlled by JTAG
Controlled by JTAG
TDO/TDI
JTAG
Controlled
DV
CC
by JTAG
TDI
Burn and Test
Fuse
TDI/TCLK
Test
and
DV
CC
TMS
TCK
Emulation
Module
TMS
CC
DV
TCK
RST/NMI
Tau ~ 50 ns
Brownout
D
U
S
G
G
D
U
S
TCK
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
APPLICATION INFORMATION
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, I , of 1.8 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be
TF
taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 14). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
The JTAG pins are terminated internally, and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
I
TF
I
TDI/TCLK
Figure 14. Fuse Check Mode Current, MSP430F42x
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
Data Sheet Revision History
Literature
Number
Summary
SLAS421
Production datasheet release
Updated functional block diagram (page 3)
Clarified test conditions in recommended operating conditions table (page 17)
Changed “Supply voltage during program execution; SD16 disabled, SVS enabled, and PORON = 1” MIN value from 2.2 V
to 2.0 V (page 17)
Clarified test conditions for I
Clarified test conditions in USART0 table (page 21)
in supply current into AV + DV table (page 18)
(LPM0)
CC CC
SLAS421A
Changed PSRR to AC PSRR in SD16 analog performance table (page 29)
Added DC PSR in SD16, built-in voltage reference table (page 30)
Added t parameter to SD16, built-in voltage reference and SD16, built-in reference output buffer tables (page 30)
ON
Changed t
maximum value from 4 ms to 10 ms in Flash memory table (page 31)
CPT
NOTE: Page and figure numbers refer to the respective document revision.
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
15-Dec-2009
PACKAGING INFORMATION
Orderable Device
MSP430F423IPM
MSP430F423IPMR
MSP430F425IPM
MSP430F425IPMR
MSP430F427IPM
MSP430F427IPMR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
LQFP
PM
64
64
64
64
64
64
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
LQFP
LQFP
LQFP
LQFP
LQFP
PM
PM
PM
PM
PM
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Apr-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430F425IPMR
MSP430F427IPMR
LQFP
LQFP
PM
PM
64
64
1000
1000
330.0
330.0
24.4
24.4
12.3
12.3
12.3
12.3
2.5
2.5
16.0
16.0
24.0
24.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Apr-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430F425IPMR
MSP430F427IPMR
LQFP
LQFP
PM
PM
64
64
1000
1000
333.2
333.2
345.9
345.9
41.3
41.3
Pack Materials-Page 2
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
0°–7°
11,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040152/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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