MSP430F448IPZR [TI]
MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器
| 型号： | MSP430F448IPZR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MIXED SIGNAL MICROCONTROLLER |
| 文件： | 总73页 (文件大小：1180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
D
D
Low Supply-Voltage Range, 1.8 V to 3.6 V
D
D
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
Ultralow-Power Consumption:
− Active Mode: 280 μA at 1 MHz, 2.2 V
− Standby Mode: 1.1 μA
− Off Mode (RAM Retention): 0.1 μA
Integrated LCD Driver for up to
160 Segments
D
D
D
D
Five Power Saving Modes
D
Bootstrap Loader
Wake-Up From Standby Mode in Less
Than 6 μs
D
Family Members Include:
− MSP430F435, MSP430F4351 :
§
16-Bit RISC Architecture,
125-ns Instruction Cycle Time
16KB+256B Flash Memory,
512B RAM
12-Bit A/D Converter With Internal
Reference, Sample-and-Hold and
Autoscan Feature
§
− MSP430F436, MSP430F4361 :
24KB+256B Flash Memory,
1KB RAM
†
‡
D
D
16-Bit Timer_B With Three or Seven
§
− MSP430F437, MSP430F4371 :
Capture/Compare-With-Shadow Registers
32KB+256B Flash Memory,
1KB RAM
− MSP430F447:
16-Bit Timer_A With Three
Capture/Compare Registers
32KB+256B Flash Memory,
1KB RAM
− MSP430F448:
48KB+256B Flash Memory,
2KB RAM
− MSP430F449:
D
On-Chip Comparator
D
Serial Communication Interface (USART),
Select Asynchronous UART or
Synchronous SPI by Software:
− Two USARTs (USART0, USART1) —
MSP430x44x Devices
60KB+256B Flash Memory,
2KB RAM
− One USART (USART0) —
MSP430x43x(1) Devices
D
For Complete Module Descriptions, See
The MSP430x4xx Family User’s Guide,
Literature Number SLAU056
D
D
Brownout Detector
Supply Voltage Supervisor/Monitor With
Programmable Level Detection
†
‡
§
’F435, ’F436, and ’F437 devices
’F447, ’F448, and ’F449 devices
The MSP430F43x1 devices are identical to the MSP430F43x
devices with the exception that the ADC12 module is not
implemented.
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6 μs.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002−2007, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
description (continued)
The MSP430x43x(1) and the MSP430x44x series are microcontroller configurations with two built-in 16-bit
timers, a fast 12-bit A/D converter (not implemented on the MSP430F43x1 devices), one or two universal serial
synchronous/asynchronous communication interfaces (USART), 48 I/O pins, and a liquid crystal driver (LCD)
with up to 160 segments.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and
process and transmit the data to a host system, or process this data and display it on a LCD panel. The timers
make the configurations ideal for industrial control applications such as ripple counters, digital motor control,
EE-meters, hand-held meters, etc. The hardware multiplier enhances the performance and offers a broad code
and hardware-compatible family solution.
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
PLASTIC 80-PIN QFP
(PN)
PLASTIC 100-PIN QFP
(PZ)
MSP430F435IPN
MSP430F436IPN
MSP430F437IPN
MSP430F435IPZ
MSP430F436IPZ
MSP430F437IPZ
MSP430F4351IPN
MSP430F4361IPN
MSP430F4371IPN
MSP430F4351IPZ
MSP430F4361IPZ
MSP430F4371IPZ
−40°C to 85°C
MSP430F447IPZ
MSP430F448IPZ
MSP430F449IPZ
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
pin designation, MSP430x4351IPN, MSP430x4361IPN, MSP430x4371IPN
PN PACKAGE
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DVCC1
P6.3
P6.4
P6.5
P6.6
P1.7/CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
P2.4/UTXD0
P2.5/URXD0
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P3.0/STE0/S31
P3.1/SIMO0/S30
P3.2/SOMI0/S29
1
60
2
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
3
4
5
P6.7/SVSIN
Reserved
XIN
6
7
8
XOUT
DVSS
DVSS
9
MSP430F4351IPN
MSP430F4361IPN
MSP430F4371IPN
10
11
12
13
14
15
16
17
18
19
20
P5.1/S0
P5.0/S1
P4.7/S2
P4.6/S3
P4.5/S4
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
pin designation, MSP430x4351IPZ, MSP430x4361IPZ, MSP430x4371IPZ
PZ PACKAGE
(TOP VIEW)
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DVCC1
P6.3
P6.4
P6.5
P6.6
P6.7/SVSIN
Reserved
XIN
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4
P3.5
P3.6
P3.7
P4.0
2
3
4
5
6
7
8
9
XOUT
DVSS
DVSS
P5.1/S0
P5.0/S1
S2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MSP430F4351IPZ
MSP430F4361IPZ
MSP430F4371IPZ
P4.1
DVSS2
DVCC2
S3
S4
S5
S6
S7
S8
S9
S10
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
S11
S12
S13
P4.2/S39
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
pin designation, MSP430x435IPN, MSP430x436IPN, MSP430x437IPN
PN PACKAGE
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P1.7/CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
P2.4/UTXD0
P2.5/URXD0
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P3.0/STE0/S31
P3.1/SIMO0/S30
P3.2/SOMI0/S29
1
60
2
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
3
4
5
P6.7/A7/SVSIN
VREF+
6
7
XIN
XOUT
VeREF+
VREF−/VeREF−
P5.1/S0
8
9
MSP430F435IPN
MSP430F436IPN
MSP430F437IPN
10
11
12
13
14
15
16
17
18
19
20
P5.0/S1
P4.7/S2
P4.6/S3
P4.5/S4
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x437IPZ
PZ PACKAGE
(TOP VIEW)
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7/ADC12CLK
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4
P3.5
P3.6
P3.7
P4.0
2
3
4
5
P6.6/A6
6
P6.7/A7/SVSIN
7
VREF+
XIN
XOUT
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VeREF+
VREF−/VeREF−
MSP430F435IPZ
MSP430F436IPZ
MSP430F437IPZ
P5.1/S0
P5.0/S1
S2
P4.1
DVSS2
DVCC2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/S39
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
pin designation, MSP430x447IPZ, MSP430x448IPZ, MSP430x449IPZ
PZ PACKAGE
(TOP VIEW)
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7/ADC12CLK
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
P4.0/UTXD1
P4.1/URXD1
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
2
3
4
5
P6.6/A6
6
P6.7/A7/SVSIN
7
VREF+
XIN
XOUT
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VeREF+
VREF−/VeREF−
MSP430F447IPZ
MSP430F448IPZ
MSP430F449IPZ
P5.1/S0
P5.0/S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
P4.2/STE1/S39
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
MSP430x43x1 functional block diagram
DV
DV
AV
AV
SS
CC1/2
SS1/2
CC
P4
P5
P6
XIN XOUT
P1
P2
P3
8
8
8
8
8
8
ACLK
XT2IN
Oscillator
FLL+
USART0
Flash
Port 1
Port 2
RAM
XT2OUT
Port 3
8 I/O
Port 4
8 I/O
Port 5
8 I/O
Port 6
6 I/O
SMCLK
UART Mode
SPI Mode
32KB
24KB
16KB
8 I/O
Interrupt
Capability
8 I/O
Interrupt
Capability
1KB
512B
MCLK
8 MHz
CPU
MAB
MDB
incl. 16
Registers
Emulation
Module
Watchdog
Timer
WDT
Timer_B3
Basic
Timer 1
LCD
128/160
Segments
1,2,3,4 MUX
POR/
SVS/
Brownout
Timer_A3
3 CC Reg
Comparator_
A
3 CC Reg
Shadow
Reg
1 Interrupt
Vector
15/16-Bit
JTAG
Interface
f
LCD
RST/NMI
MSP430x43x functional block diagram
DV
DV
AV
AV
SS
CC1/2
SS1/2
CC
P4
8
P5
8
P6
8
XIN XOUT
P1
P2
8
P3
8
8
ACLK
XT2IN
Oscillator
FLL+
USART0
Flash
Port 1
Port 2
RAM
XT2OUT
Port 3
8 I/O
Port 4
8 I/O
Port 5
8 I/O
Port 6
6 I/O
SMCLK
UART Mode
SPI Mode
32KB
24KB
16KB
8 I/O
Interrupt
Capability
8 I/O
Interrupt
Capability
1KB
512B
MCLK
8 MHz
CPU
MAB
MDB
incl. 16
Registers
Emulation
Module
ADC12
Watchdog
Timer
WDT
Timer_B3
Basic
Timer 1
LCD
128/160
Segments
1,2,3,4 MUX
POR/
SVS/
Brownout
Timer_A3
3 CC Reg
Comparator_
A
12-Bit
8 Channels
<10μs Conv.
3 CC Reg
Shadow
Reg
1 Interrupt
Vector
15/16-Bit
JTAG
Interface
f
LCD
RST/NMI
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
MSP430x44x functional block diagram
DV
DV
AV
AV
SS
CC1/2
SS1/2
CC
P4
P5
P6
XIN XOUT
P1
P2
P3
8
8
8
8
8
8
ACLK
XT2IN
Oscillator
FLL+
USART0
USART1
Flash
Port 1
Port 2
RAM
XT2OUT
Port 3
8 I/O
Port 4
8 I/O
Port 5
8 I/O
Port 6
6 I/O
SMCLK
60KB
48KB
32KB
8 I/O
Interrupt
Capability
8 I/O
Interrupt
Capability
2KB
1KB
UART Mode
SPI Mode
MCLK
8 MHz
CPU
MAB
MDB
incl. 16
Registers
Emulation
Module
Hardware
Multiplier
ADC12
Watchdog
Timer
WDT
Timer_B7
Basic
Timer 1
LCD
160
Segments
POR/
SVS/
Brownout
Timer_A3
3 CC Reg
Comparator_
A
12-Bit
8 Channels
<10μs Conv.
7 CC Reg
Shadow
Reg
MPY, MPYS
MAC,MACS
1 Interrupt
Vector
1,2,3,4 MUX
15/16-Bit
JTAG
Interface
f
LCD
RST/NMI
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
MSP430x43x1 Terminal Functions
TERMINAL
I/O
PN
NAME
PZ
NAME
DESCRIPTION
I/O
NO.
1
NO.
1
DV
DV
Digital supply voltage, positive terminal.
CC1
CC1
P6.3
P6.4
P6.5
P6.6
2
I/O P6.3
I/O P6.4
I/O P6.5
I/O P6.6
2
I/O General-purpose digital I/O
I/O General-purpose digital I/O
I/O General-purpose digital I/O
I/O General-purpose digital I/O
3
3
4
4
5
5
P6.7/SVSIN
6
I/O P6.7/SVSIN
6
I/O General-purpose digital I/O / input to brownout, supply voltage
supervisor
Reserved
XIN
7
8
Reserved
7
8
Reserved, do not connect externally
Input port for crystal oscillator XT1. Standard or watch crystals can be
connected.
I
XIN
I
XOUT
9
O
I
XOUT
9
O
I
Output terminal of crystal oscillator XT1
DV
DV
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DV
DV
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Connect to DV
Connect to DV
SS
SS
SS
SS
SS
SS
I
I
P5.1/S0
P5.0/S1
P4.7/S2
P4.6/S3
P4.5/S4
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
P4.0/S9
S10
I/O P5.1/S0
I/O P5.0/S1
I/O S2
I/O General-purpose digital I/O / LCD segment output 0
I/O General-purpose digital I/O / LCD segment output 1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
General-purpose digital I/O / LCD segment output 2
General-purpose digital I/O / LCD segment output 3
General-purpose digital I/O / LCD segment output 4
General-purpose digital I/O / LCD segment output 5
General-purpose digital I/O / LCD segment output 6
General-purpose digital I/O / LCD segment output 7
General-purpose digital I/O / LCD segment output 8
General-purpose digital I/O / LCD segment output 9
LCD segment output 10
I/O S3
I/O S4
I/O S5
I/O S6
I/O S7
I/O S8
I/O S9
O
O
O
O
O
O
O
O
S10
S11
S12
S13
S14
S15
S16
S17
S11
LCD segment output 11
S12
LCD segment output 12
S13
LCD segment output 13
S14
LCD segment output 14
S15
LCD segment output 15
S16
LCD segment output 16
S17
LCD segment output 17
P2.7/S18
I/O S18
General-purpose digital I/O / LCD segment output 18
General-purpose digital I/O / Comparator_A output / LCD segment
output 19
P2.6/CAOUT/S19
31
I/O S19
31
O
S20
32
33
34
35
36
37
38
39
O
O
O
O
S20
S21
S22
S23
32
33
34
35
36
37
38
39
O
O
O
O
O
O
O
O
LCD segment output 20
S21
LCD segment output 21
S22
LCD segment output 22
S23
LCD segment output 23
P3.7/S24
P3.6/S25
P3.5/S26
P3.4/S27
I/O S24
I/O S25
I/O S26
I/O S27
General-purpose digital I/O / LCD segment output 24
General-purpose digital I/O / LCD segment output 25
General-purpose digital I/O / LCD segment output 26
General-purpose digital I/O / LCD segment output 27
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
MSP430x43x1 Terminal Functions (Continued)
TERMINAL
PN
NAME
PZ
NAME
DESCRIPTION
I/O
I/O
O
NO.
NO.
General-purpose digital I/O / ext. clock i/p—USART0/UART or SPI
mode, clock o/p—USART0/SPI mode / LCD segment output 28
P3.3/UCLK0/S28
P3.2/SOMI0/S29
P3.1/SIMO0/S30
P3.0/STE0/S31
40
I/O S28
I/O S29
I/O S30
I/O S31
40
General-purpose digital I/O / slave out/master in of USART0/SPI mode
/ LCD segment output 29
41
42
43
41
42
43
O
General-purpose digital I/O / slave out/master out of USART0/SPI
mode / LCD segment output 30
O
General-purpose digital I/O / slave transmit enable-USART0/SPI
mode / LCD segment output 31
O
S32
S33
44
45
46
47
48
49
50
51
52
O
LCD segment output 32
O
LCD segment output 33
P4.7/S34
I/O
I/O
I/O
I/O
I/O
I/O
O
General-purpose digital I/O / LCD segment output 34
General-purpose digital I/O / LCD segment output 35
General-purpose digital I/O / LCD segment output 36
General-purpose digital I/O / LCD segment output 37
General-purpose digital I/O / LCD segment output 38
General-purpose digital I/O / LCD segment output 39
COM0−3 are used for LCD backplanes.
P4.6/S35
P4.5/S36
P4.4/S37
P4.3/S38
P4.2/S39
COM0
COM0
44
45
O
General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
P5.2/COM1
I/O P5.2/COM1
I/O P5.3/COM2
I/O P5.4/COM3
53
54
I/O
I/O
General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
P5.3/COM2
46
General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
P5.4/COM3
R03
47
48
49
55
56
57
I/O
I
I
R03
Input port of fourth positive (lowest) analog LCD level (V5)
General-purpose digital I/O / input port of third most positive analog
LCD level (V4 or V3)
P5.5/R13
I/O P5.5/R13
I/O P5.6/R23
I/O P5.7/R33
I/O
General-purpose digital I/O / input port of second most positive analog
LCD level (V2)
P5.6/R23
P5.7/R33
50
51
58
59
I/O
I/O
General-purpose digital I/O / output port of most positive analog LCD
level (V1)
DV
DV
52
53
DV
DV
60
61
62
63
64
65
66
67
Digital supply voltage, positive terminal.
Digital supply voltage, negative terminal.
General-purpose digital I/O
CC2
CC2
SS2
SS2
P4.1
P4.0
P3.7
P3.6
P3.5
P3.4
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O / external clock input—USART0/UART or
SPI mode, clock output—USART0/SPI mode
P3.3/UCLK0
68
I/O
P3.2/SOMI0
P3.1/SIMO0
P3.0/STE0
69
70
71
72
73
74
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O / slave out/master in of USART0/SPI mode
General-purpose digital I/O / slave in/master out of USART0/SPI mode
General-purpose digital I/O / slave transmit enable USART0/SPI mode
General-purpose digital I/O
P2.7
P2.6/CAOUT
I/O P2.5/URXD0
General-purpose digital I/O / Comparator_A output
P2.5/URXD0
54
General-purpose digital I/O / receive data in—USART0/UART mode
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
MSP430x43x1 Terminal Functions (Continued)
TERMINAL
PN
NAME
PZ
NAME
DESCRIPTION
I/O
I/O
I/O
I/O
NO.
NO.
P2.4/UTXD0
55
I/O P2.4/UTXD0
75
General-purpose digital I/O / transmit data out—USART0/UART mode
General-purpose digital I/O / Timer_B3 CCR2.
Capture: CCI2A/CCI2B input, compare: Out2 output
P2.3/TB2
56
57
58
59
I/O P2.3/TB2
76
77
78
79
General-purpose digital I/O / Timer_B3 CCR1.
Capture: CCI1A/CCI1B input, compare: Out1 output
P2.2/TB1
P2.1/TB0
P2.0/TA2
I/O P2.2/TB1
I/O P2.1/TB0
I/O P2.0/TA2
I/O
I/O
I/O
General-purpose digital I/O / Timer_B3 CCR0.
Capture: CCI0A/CCI0B input, compare: Out0 output
General-purpose digital I/O / Timer_A
Capture: CCI2A input, compare: Out2 output
P1.7/CA1
P1.6/CA0
60
61
I/O P1.7/CA1
I/O P1.6/CA0
80
81
I/O
I/O
General-purpose digital I/O / Comparator_A input
General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK
P1.5/TACLK/
ACLK
General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8)
62
63
64
65
66
I/O
82
83
84
85
86
I/O
I/O
I/O
I/O
I/O
P1.4/TBCLK/
SMCLK
P1.4/TBCLK/
SMCLK
General-purpose digital I/O / input clock TBCLK—Timer_B3 / submain
system clock SMCLK output
I/O
P1.3/TBOUTH/
SVSOUT
P1.3/TBOUTH/
SVSOUT
General-purpose digital I/O / switch all PWM digital output ports to high
impedance—Timer_B3 TB0 to TB2 / SVS: output of SVS comparator
I/O
General-purpose digital I/O / Timer_A, Capture: CCI1A input,
compare: Out1 output
P1.2/TA1
I/O P1.2/TA1
General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK
output. Note: TA0 is only an input on this pin / BSL receive
P1.1/TA0/MCLK
I/O P1.1/TA0/MCLK
I/O P1.0/TA0
General-purpose digital I/O / Timer_A. Capture: CCI0A input,
compare: Out0 output / BSL transmit
P1.0/TA0
XT2OUT
XT2IN
67
68
69
87
88
89
I/O
O
I
O
I
XT2OUT
XT2IN
Output terminal of crystal oscillator XT2
Input port for crystal oscillator XT2. Only standard crystals can be
connected.
Test data output port. TDO/TDI data output or programming data input
terminal
TDO/TDI
70
71
I/O TDO/TDI
90
91
I/O
I
Test data input or test clock input. The device protection fuse is
connected to TDI/TCLK.
TDI/TCLK
I
TDI/TCLK
Test mode select. TMS is used as an input port for device programming
and test.
TMS
72
73
74
I
I
I
TMS
92
93
94
I
I
I
TCK
TCK
Test clock. TCK is the clock input port for device programming and test.
General-purpose digital I/O / reset input or nonmaskable interrupt input
port
RST/NMI
RST/NMI
P6.0
P6.1
P6.2
75
76
77
I/O P6.0
I/O P6.1
I/O P6.2
95
96
97
I/O
I/O
I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
Analog supply voltage, negative terminal. Supplies SVS, brownout,
oscillator, comparator_A, port 1, and LCD resistive divider circuitry.
AV
78
79
AV
98
99
SS
SS
DV
DV
Digital supply voltage, negative terminal.
SS1
SS1
Analog supply voltage, positive terminal. Supplies SVS, brownout,
oscillator, comparator_A, port 1, and LCD resistive divider circuitry;
AV
80
AV
100
CC
CC
must not power up prior to DV
/DV
.
CC1
CC2
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
MSP430x43x Terminal Functions
TERMINAL
I/O
PN
NAME
PZ
NAME
DESCRIPTION
I/O
NO.
1
NO.
1
DV
DV
Digital supply voltage, positive terminal.
CC1
CC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
2
I/O P6.3/A3
I/O P6.4/A4
I/O P6.5/A5
I/O P6.6/A6
2
I/O General-purpose digital I/O / analog input a3—12-bit ADC
I/O General-purpose digital I/O / analog input a4—12-bit ADC
I/O General-purpose digital I/O / analog input a5—12-bit ADC
I/O General-purpose digital I/O / analog input a6—12-bit ADC
3
3
4
4
5
5
P6.7/A7/SVSIN
6
I/O P6.7/A7/SVSIN
6
I/O General-purpose digital I/O / analog input a7—12-bit ADC, analog /
input to brownout, supply voltage supervisor
V
7
8
O
I
V
7
8
O
Output of positive terminal of the reference voltage in the ADC
REF+
REF+
Input port for crystal oscillator XT1. Standard or watch crystals can be
connected.
XIN
XIN
I
XOUT
9
O
I
XOUT
9
O
I
Output terminal of crystal oscillator XT1
Ve
REF+
10
Ve
REF+
10
Input for an external reference voltage to the ADC
Negative terminal for the ADC’s reference voltage for both sources, the
internal reference voltage, or an external applied reference voltage.
V
REF−
/Ve
11
I
V /Ve
REF− REF−
11
I
REF−
P5.1/S0
P5.0/S1
P4.7/S2
P4.6/S3
P4.5/S4
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
P4.0/S9
S10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
I/O P5.1/S0
I/O P5.0/S1
I/O S2
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
I/O General-purpose digital I/O / LCD segment output 0
I/O General-purpose digital I/O / LCD segment output 1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
General-purpose digital I/O / LCD segment output 2
General-purpose digital I/O / LCD segment output 3
General-purpose digital I/O / LCD segment output 4
General-purpose digital I/O / LCD segment output 5
General-purpose digital I/O / LCD segment output 6
General-purpose digital I/O / LCD segment output 7
General-purpose digital I/O / LCD segment output 8
General-purpose digital I/O / LCD segment output 9
LCD segment output 10
I/O S3
I/O S4
I/O S5
I/O S6
I/O S7
I/O S8
I/O S9
O
O
O
O
O
O
O
O
S10
S11
S12
S13
S14
S15
S16
S17
S11
LCD segment output 11
S12
LCD segment output 12
S13
LCD segment output 13
S14
LCD segment output 14
S15
LCD segment output 15
S16
LCD segment output 16
S17
LCD segment output 17
P2.7/ADC12CLK/
S18
I/O S18
General-purpose digital I/O / conversion clock—12-bit ADC / LCD
segment output 18
General-purpose digital I/O / Comparator_A output / LCD segment
output 19
P2.6/CAOUT/S19
31
I/O S19
31
O
S20
32
33
34
35
36
37
38
39
O
O
O
O
S20
S21
S22
S23
32
33
34
35
36
37
38
39
O
O
O
O
O
O
O
O
LCD segment output 20
S21
LCD segment output 21
S22
LCD segment output 22
S23
LCD segment output 23
P3.7/S24
P3.6/S25
P3.5/S26
P3.4/S27
I/O S24
I/O S25
I/O S26
I/O S27
General-purpose digital I/O / LCD segment output 24
General-purpose digital I/O / LCD segment output 25
General-purpose digital I/O / LCD segment output 26
General-purpose digital I/O / LCD segment output 27
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
MSP430x43x Terminal Functions (Continued)
TERMINAL
PN
NAME
PZ
NAME
DESCRIPTION
I/O
I/O
O
NO.
NO.
General-purpose digital I/O / ext. clock i/p—USART0/UART or SPI
mode, clock o/p—USART0/SPI mode / LCD segment output 28
P3.3/UCLK0/S28
P3.2/SOMI0/S29
P3.1/SIMO0/S30
P3.0/STE0/S31
40
I/O S28
I/O S29
I/O S30
I/O S31
40
General-purpose digital I/O / slave out/master in of USART0/SPI mode
/ LCD segment output 29
41
42
43
41
42
43
O
General-purpose digital I/O / slave out/master out of USART0/SPI
mode / LCD segment output 30
O
General-purpose digital I/O / slave transmit enable-USART0/SPI
mode / LCD segment output 31
O
S32
S33
44
45
46
47
48
49
50
51
52
O
LCD segment output 32
O
LCD segment output 33
P4.7/S34
I/O
I/O
I/O
I/O
I/O
I/O
O
General-purpose digital I/O / LCD segment output 34
General-purpose digital I/O / LCD segment output 35
General-purpose digital I/O / LCD segment output 36
General-purpose digital I/O / LCD segment output 37
General-purpose digital I/O / LCD segment output 38
General-purpose digital I/O / LCD segment output 39
COM0−3 are used for LCD backplanes.
P4.6/S35
P4.5/S36
P4.4/S37
P4.3/S38
P4.2/S39
COM0
COM0
44
45
O
General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
P5.2/COM1
I/O P5.2/COM1
I/O P5.3/COM2
I/O P5.4/COM3
53
54
I/O
I/O
General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
P5.3/COM2
46
General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
P5.4/COM3
R03
47
48
49
55
56
57
I/O
I
I
R03
Input port of fourth positive (lowest) analog LCD level (V5)
General-purpose digital I/O / input port of third most positive analog
LCD level (V4 or V3)
P5.5/R13
I/O P5.5/R13
I/O P5.6/R23
I/O P5.7/R33
I/O
General-purpose digital I/O / input port of second most positive analog
LCD level (V2)
P5.6/R23
P5.7/R33
50
51
58
59
I/O
I/O
General-purpose digital I/O / output port of most positive analog LCD
level (V1)
DV
DV
52
53
DV
DV
60
61
62
63
64
65
66
67
Digital supply voltage, positive terminal.
Digital supply voltage, negative terminal.
General-purpose digital I/O
CC2
CC2
SS2
SS2
P4.1
P4.0
P3.7
P3.6
P3.5
P3.4
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O / external clock input—USART0/UART or
SPI mode, clock output—USART0/SPI mode
P3.3/UCLK0
68
I/O
P3.2/SOMI0
P3.1/SIMO0
69
70
71
72
73
74
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O / slave out/master in of USART0/SPI mode
General-purpose digital I/O / slave in/master out of USART0/SPI mode
General-purpose digital I/O / slave transmit enable USART0/SPI mode
General-purpose digital I/O / conversion clock—12-bit ADC
General-purpose digital I/O / Comparator_A output
P3.0/STE0
P2.7/ADC12CLK
P2.6/CAOUT
P2.5/URXD0
54
I/O P2.5/URXD0
General-purpose digital I/O / receive data in—USART0/UART mode
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
MSP430x43x Terminal Functions (Continued)
TERMINAL
PN
NAME
PZ
NAME
DESCRIPTION
I/O
I/O
I/O
I/O
NO.
NO.
P2.4/UTXD0
55
I/O P2.4/UTXD0
75
General-purpose digital I/O / transmit data out—USART0/UART mode
General-purpose digital I/O / Timer_B3 CCR2.
Capture: CCI2A/CCI2B input, compare: Out2 output
P2.3/TB2
56
57
58
59
I/O P2.3/TB2
76
77
78
79
General-purpose digital I/O / Timer_B3 CCR1.
Capture: CCI1A/CCI1B input, compare: Out1 output
P2.2/TB1
P2.1/TB0
P2.0/TA2
I/O P2.2/TB1
I/O P2.1/TB0
I/O P2.0/TA2
I/O
I/O
I/O
General-purpose digital I/O / Timer_B3 CCR0.
Capture: CCI0A/CCI0B input, compare: Out0 output
General-purpose digital I/O / Timer_A
Capture: CCI2A input, compare: Out2 output
P1.7/CA1
P1.6/CA0
60
61
I/O P1.7/CA1
I/O P1.6/CA0
80
81
I/O
I/O
General-purpose digital I/O / Comparator_A input
General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK
P1.5/TACLK/
ACLK
General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8)
62
63
64
65
66
I/O
82
83
84
85
86
I/O
I/O
I/O
I/O
I/O
P1.4/TBCLK/
SMCLK
P1.4/TBCLK/
SMCLK
General-purpose digital I/O / input clock TBCLK—Timer_B3 / submain
system clock SMCLK output
I/O
P1.3/TBOUTH/
SVSOUT
P1.3/TBOUTH/
SVSOUT
General-purpose digital I/O / switch all PWM digital output ports to high
impedance—Timer_B3 TB0 to TB2 / SVS: output of SVS comparator
I/O
General-purpose digital I/O / Timer_A, Capture: CCI1A input,
compare: Out1 output
P1.2/TA1
I/O P1.2/TA1
General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK
output. Note: TA0 is only an input on this pin / BSL receive
P1.1/TA0/MCLK
I/O P1.1/TA0/MCLK
I/O P1.0/TA0
General-purpose digital I/O / Timer_A. Capture: CCI0A input,
compare: Out0 output / BSL transmit
P1.0/TA0
XT2OUT
XT2IN
67
68
69
87
88
89
I/O
O
I
O
I
XT2OUT
XT2IN
Output terminal of crystal oscillator XT2
Input port for crystal oscillator XT2. Only standard crystals can be
connected.
Test data output port. TDO/TDI data output or programming data input
terminal
TDO/TDI
70
71
I/O TDO/TDI
90
91
I/O
I
Test data input or test clock input. The device protection fuse is
connected to TDI/TCLK.
TDI/TCLK
I
TDI/TCLK
Test mode select. TMS is used as an input port for device programming
and test.
TMS
72
73
74
I
I
I
TMS
92
93
94
I
I
I
TCK
TCK
Test clock. TCK is the clock input port for device programming and test.
General-purpose digital I/O / reset input or nonmaskable interrupt input
port
RST/NMI
RST/NMI
P6.0/A0
P6.1/A1
P6.2/A2
75
76
77
I/O P6.0/A0
I/O P6.1/A1
I/O P6.2/A2
95
96
97
I/O
I/O
I/O
General-purpose digital I/O / analog input a0 − 12-bit ADC
General-purpose digital I/O / analog input a1 − 12-bit ADC
General-purpose digital I/O / analog input a2 − 12-bit ADC
Analog supply voltage, negative terminal. Supplies SVS, brownout,
oscillator, comparator_A, ADC12, port 1, and LCD resistive divider
circuitry.
AV
78
79
80
AV
98
99
SS
SS
DV
DV
Digital supply voltage, negative terminal.
SS1
CC
SS1
CC
Analog supply voltage, positive terminal. Supplies SVS, brownout,
oscillator, comparator_A, ADC12, port 1, and LCD resistive divider
AV
AV
100
circuitry; must not power up prior to DV
/DV
.
CC1
CC2
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
MSP430x44x Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
1
DV
Digital supply voltage, positive terminal.
CC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
2
I/O General-purpose digital I/O / analog input a3—12-bit ADC
I/O General-purpose digital I/O / analog input a4—12-bit ADC
I/O General-purpose digital I/O / analog input a5—12-bit ADC
I/O General-purpose digital I/O / analog input a6—12-bit ADC
3
4
5
General-purpose digital I/O / analog input a7—12-bit ADC / analog input to brownout, supply voltage
supervisor
P6.7/A7/SVSIN
6
I/O
V
7
8
O
I
Output of positive terminal of the reference voltage in the ADC
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
Output terminal of crystal oscillator XT1
REF+
XIN
XOUT
9
O
I
Ve
10
Input for an external reference voltage to the ADC
REF+
Negative terminal for the ADC’s reference voltage for both sources, the internal reference voltage, or an
external applied reference voltage
V
REF−
/Ve
11
I
REF−
P5.1/S0
P5.0/S1
S2
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O General-purpose digital I/O / LCD segment output 0
I/O General-purpose digital I/O / LCD segment output 1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
LCD segment output 2
LCD segment output 3
LCD segment output 4
LCD segment output 5
LCD segment output 6
LCD segment output 7
LCD segment output 8
LCD segment output 9
LCD segment output 10
LCD segment output 11
LCD segment output 12
LCD segment output 13
LCD segment output 14
LCD segment output 15
LCD segment output 16
LCD segment output 17
LCD segment output 18
LCD segment output 19
LCD segment output 20
LCD segment output 21
LCD segment output 22
LCD segment output 23
LCD segment output 24
LCD segment output 25
LCD segment output 26
LCD segment output 27
LCD segment output 28
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
16
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MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
MSP430x44x Terminal Functions (Continued)
TERMINAL
PN
I/O
DESCRIPTION
NAME
NO.
41
42
43
44
45
46
47
S29
S30
S31
S32
S33
O
O
O
O
O
LCD segment output 29
LCD segment output 30
LCD segment output 31
LCD segment output 32
LCD segment output 33
P4.7/S34
P4.6/S35
I/O General-purpose digital I/O / LCD segment output 34
I/O General-purpose digital I/O / LCD segment output 35
General-purpose digital I/O / external clock input—USART1/UART or SPI mode, clock
output—USART1/SPI MODE / LCD segment output 36
P4.5/UCLK1/S36
48
I/O
P4.4/SOMI1/S37
P4.3/SIMO1/S38
P4.2/STE1/S39
COM0
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
I/O General-purpose digital I/O / slave out/master in of USART1/SPI mode / LCD segment output 37
I/O General-purpose digital I/O / slave in/master out of USART1/SPI mode / LCD segment output 38
I/O General-purpose digital I/O / slave transmit enable—USART1/SPI mode / LCD segment output 39
O
COM0−3 are used for LCD backplanes.
P5.2/COM1
P5.3/COM2
P5.4/COM3
R03
I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
I
Input port of fourth positive (lowest) analog LCD level (V5)
P5.5/R13
I/O General-purpose digital I/O / Input port of third most positive analog LCD level (V4 or V3)
I/O General-purpose digital I/O / Input port of second most positive analog LCD level (V2)
I/O General-purpose digital I/O / Output port of most positive analog LCD level (V1)
Digital supply voltage, positive terminal.
P5.6/R23
P5.7/R33
DV
DV
CC2
SS2
Digital supply voltage, negative terminal.
P4.1/URXD1
P4.0/UTXD1
P3.7/TB6
I/O General-purpose digital I/O / receive data in—USART1/UART mode
I/O General-purpose digital I/O / transmit data out—USART1/UART mode
I/O General-purpose digital I/O / Timer_B7 CCR6 / Capture: CCI6A/CCI6B input, compare: Out6 output
I/O General-purpose digital I/O / Timer_B7 CCR5 / Capture: CCI5A/CCI5B input, compare: Out5 output
I/O General-purpose digital I/O / Timer_B7 CCR4 / Capture: CCI4A/CCI4B input, compare: Out4 output
I/O General-purpose digital I/O / Timer_B7 CCR3 / Capture: CCI3A/CCI3B input, compare: Out3 output
P3.6/TB5
P3.5/TB4
P3.4/TB3
General-purpose digital I/O / external clock input—USART0/UART or SPI mode, clock
output—USART0/SPI mode
P3.3/UCLK0
68
I/O
P3.2/SOMI0
P3.1/SIMO0
P3.0/STE0
P2.7/ADC12CLK
P2.6/CAOUT
P2.5/URXD0
P2.4/UTXD0
P2.3/TB2
69
70
71
72
73
74
75
76
77
78
79
80
I/O General-purpose digital I/O / slave out/master in of USART0/SPI mode
I/O General-purpose digital I/O / slave in/master out of USART0/SPI mode
I/O General-purpose digital I/O / slave transmit enable—USART0/SPI mode
I/O General-purpose digital I/O / conversion clock—12-bit ADC
I/O General-purpose digital I/O / Comparator_A output
I/O General-purpose digital I/O / receive data in—USART0/UART mode
I/O General-purpose digital I/O / transmit data out—USART0/UART mode
I/O General-purpose digital I/O / Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output
I/O General-purpose digital I/O / Timer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output
I/O General-purpose digital I/O / Timer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output
I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output
I/O General-purpose digital I/O / Comparator_A input
P2.2/TB1
P2.1/TB0
P2.0/TA2
P1.7/CA1
17
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SLAS344F − JANUARY 2002 − REVISED MAY 2007
MSP430x44x Terminal Functions (Continued)
TERMINAL
PN
I/O
DESCRIPTION
NAME
NO.
P1.6/CA0
81
I/O General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK
82
83
I/O General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by 1, 2, 4, or 8)
P1.4/TBCLK/
SMCLK
I/O General-purpose digital I/O / input clock TBCLK—Timer_B7 / submain system clock SMCLK output
P1.3/TBOUTH/
SVSOUT
General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B7 TB0 to TB6
/ SVS: output of SVS comparator
84
85
86
I/O
P1.2/TA1
I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 output
General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
P1.1/TA0/MCLK
I/O
P1.0/TA0
XT2OUT
XT2IN
87
88
89
90
91
92
93
94
95
96
97
I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL transmit
O
I
Output terminal of crystal oscillator XT2
Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI
TDI/TCLK
TMS
I/O Test data output port. TDO/TDI data output or programming data input terminal
I
I
I
I
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
Test mode select. TMS is used as an input port for device programming and test.
Test clock. TCK is the clock input port for device programming and test.
Reset input or nonmaskable interrupt input port
TCK
RST/NMI
P6.0/A0
P6.1/A1
P6.2/A2
I/O General-purpose digital I/O, analog input a0—12-bit ADC
I/O General-purpose digital I/O, analog input a1—12-bit ADC
I/O General-purpose digital I/O, analog input a2—12-bit ADC
Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_A, ADC12,
port 1, and LCD resistive divider circuitry.
AV
98
99
SS
DV
Digital supply voltage, negative terminal.
SS1
CC
Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_A, ADC12, port 1,
AV
100
and LCD resistive divider circuitry; must not power up prior to DV
/DV
.
CC1
CC2
18
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MSP430x43x1, MSP430x43x, MSP430x44x
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SLAS344F − JANUARY 2002 − REVISED MAY 2007
short-form description
CPU
Program Counter
Stack Pointer
PC/R0
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
R4
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
R5
R6
R7
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
R8
R9
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
R10
R11
instruction set
R12
R13
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
R14
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
e.g. ADD R4,R5
R4 + R5 −−−> R5
e.g. CALL
e.g. JNE
R8
PC −−>(TOS), R8−−> PC
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
Register
S
D
SYNTAX
MOV Rs,Rd
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
OPERATION
D D
R10 −−> R11
Indexed
D D
MOV X(Rn),Y(Rm)
MOV EDE,TONI
M(2+R5)−−> M(6+R6)
M(EDE) −−> M(TONI)
M(MEM) −−> M(TCDAT)
M(R10) −−> M(Tab+R6)
Symbolic (PC relative) D D
Absolute
Indirect
D D MOV &MEM,&TCDAT
D
D
D
MOV @Rn,Y(Rm)
MOV @Rn+,Rm
MOV #X,TONI
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
Indirect
autoincrement
M(R10) −−> R11
R10 + 2−−> R10
Immediate
#45 −−> M(TONI)
NOTE: S = source
D = destination
19
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MSP430x43x1, MSP430x43x, MSP430x44x
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operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D
D
Active mode (AM)
All clocks are active
Low-power mode 0 (LPM0)
−
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
FLL+ loop control remains active
D
D
Low-power mode 1 (LPM1)
−
CPU is disabled
FLL+ loop control is disabled
ACLK and SMCLK remain active. MCLK is disabled
Low-power mode 2 (LPM2)
−
CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D
D
Low-power mode 3 (LPM3)
−
CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
Low-power mode 4 (LPM4)
−
CPU is disabled
ACLK is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
20
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MSP430x43x1, MSP430x43x, MSP430x44x
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interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh−0FFE0h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 3. Interrupt Sources, Flags, and Vectors of 4xx Configurations
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
PRIORITY
Power-Up
External Reset
Watchdog
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh
15, highest
Flash Memory
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
14
†
Timer_B7
TBCCR0 CCIFG (see Note 2)
Maskable
0FFFAh
0FFF8h
13
12
TBCCR1 to TBCCR6 CCIFGs
TBIFG (see Notes 1 and 2)
†
Timer_B7
Maskable
Comparator_A
Watchdog Timer
USART0 Receive
USART0 Transmit
ADC12 (see Note 4)
Timer_A3
CAIFG
WDTIFG
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
0FFECh
11
10
9
URXIFG0
UTXIFG0
8
ADC12IFG (see Notes 1 and 2)
TACCR0 CCIFG (see Note 2)
7
6
TACCR1 and TACCR2 CCIFGs,
TAIFG (see Notes 1 and 2)
Timer_A3
Maskable
Maskable
0FFEAh
0FFE8h
5
4
P1IFG.0 to P1IFG.7
(see Notes 1 and 2)
I/O Port P1 (Eight Flags)
‡
USART1 Receive
URXIFG1
UTXIFG1
Maskable
Maskable
0FFE6h
0FFE4h
3
2
‡
USART1 Transmit
P2IFG.0 to P2IFG.7
(see Notes 1 and 2)
I/O Port P2 (Eight Flags)
Basic Timer1
Maskable
Maskable
0FFE2h
0FFE0h
1
BTIFG
0, lowest
†
‡
’43x(1) uses Timer_B3 with TBCCR0, 1 and 2 CCIFG flags, and TBIFG. ’44x uses Timer_B7 with TBCCR0 CCIFG, TBCCR1 to TBCCR6
CCIFGs, and TBIFG
USART1 is implemented in ’44x only.
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable
it.
4. ADC12 is not implemented in MSP430x43x1 devices.
21
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special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
interrupt enable 1 and 2
7
6
5
4
3
2
1
0
Address
0h
UTXIE0
URXIE0
ACCVIE
NMIIE
OFIE
WDTIE
rw–0
rw–0
rw–0
rw–0
rw–0
rw–0
WDTIE:
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
OFIE:
Oscillator-fault-interrupt enable
NMIIE:
Nonmaskable-interrupt enable
ACCVIE:
URXIE0:
UTXIE0:
Flash access violation interrupt enable
USART0: UART and SPI receive-interrupt enable
USART0: UART and SPI transmit-interrupt enable
7
6
5
4
3
2
1
0
Address
01h
BTIE
rw–0
UTXIE1
URXIE1
rw–0
rw–0
URXIE1:
UTXIE1:
BTIE:
USART1: UART and SPI receive-interrupt enable (MSP430F44x devices only)
USART1: UART and SPI transmit-interrupt enable (MSP430F44x devices only)
Basic timer interrupt enable
interrupt flag register 1 and 2
7
6
URXIFG0
rw–0
5
4
3
2
1
0
Address
02h
UTXIFG0
NMIIFG
OFIFG
WDTIFG
rw–1
rw–0
rw–1
rw–(0)
WDTIFG:
Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on V
power up or a reset condition at the RST/NMI pin in reset mode.
CC
OFIFG:
Flag set on oscillator fault
Set via RST/NMI pin
NMIIFG:
URXIFG0: USART0: UART and SPI receive flag
UTXIFG0: USART0: UART and SPI transmit flag
7
6
5
4
3
2
1
0
Address
03h
UTXIFG1
URXIFG1
BTIFG
rw
rw–1
rw–0
URXIFG1: USART1: UART and SPI receive flag (MSP430F44x devices only)
UTXIFG1: USART1: UART and SPI transmit flag (MSP430F44x devices only)
BTIFG:
Basic timer flag
22
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module enable registers 1 and 2
7
6
5
4
3
2
1
0
Address
04h
UTXE0
URXE0
USPIE0
rw–0
rw–0
URXE0:
USART0: UART mode receive enable
USART0: UART mode transmit enable
UTXE0:
USPIE0:
USART0: SPI mode transmit and receive enable
7
6
5
4
3
2
1
0
Address
05h
UTXE1
URXE1
USPIE1
rw–0
rw–0
URXE1:
USART1: UART mode receive enable (MSP430F44x devices only)
USART1: UART mode transmit enable (MSP430F44x devices only)
UTXE1:
USPIE1:
USART1: SPI mode transmit and receive enable (MSP430F44x devices only)
Legend: rw:
Bit Can Be Read and Written
rw–0,1:
rw–(0,1):
Bit Can Be Read and Written. It Is Reset or Set by PUC.
Bit Can Be Read and Written. It Is Reset or Set by POR.
SFR Bit Not Present in Device
memory organization
MSP430F437
MSP430F447
MSP430F435
MSP430F436
MSP430F448
MSP430F449
Memory
Size
16KB
24KB
32KB
48KB
60KB
Main: interrupt vector
Main: code memory
Flash 0FFFFh − 0FFE0h 0FFFFh − 0FFE0h 0FFFFh − 0FFE0h 0FFFFh − 0FFE0h 0FFFFh − 0FFE0h
Flash 0FFFFh − 0C000h 0FFFFh − 0A000h 0FFFFh − 08000h 0FFFFh − 04000h 0FFFFh − 01100h
Information memory
Boot memory
RAM
Size
256 Byte
256 Byte
256 Byte
256 Byte
256 Byte
Flash 010FFh − 01000h 010FFh − 01000h 010FFh − 01000h 010FFh − 01000h 010FFh − 01000h
Size
ROM
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
Size
512 Byte
1KB
1KB
2KB
2KB
03FFh − 0200h
05FFh − 0200h
05FFh − 0200h
09FFh − 0200h
09FFh − 0200h
Peripherals
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
BSL Function
Data Transmit
Data Receive
PN Package Pins
67 - P1.0
PZ Package Pins
87 - P1.0
66 - P1.1
86 - P1.1
23
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MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
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flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D
Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D
D
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A and B can be erased individually, or as a group with segments 0−n.
Segments A and B are also called information memory.
D
New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
16KB
24KB
32KB
48KB
60KB
Segment 0
w/ Interrupt Vectors
0FFFFh
0FFFFh
0FFFFh
0FFFFh
0FFFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
Segment 1
Segment 2
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
Main
Memory
0C400h
0C3FFh
0A400h
0A3FFh
08400h
083FFh
04400h
043FFh
01400h
013FFh
Segment n-1
Segment n
0C200h
0C1FFh
0A200h
0A1FFh
08200h
081FFh
04200h
041FFh
01200h
011FFh
0C000h
010FFh
0A000h
010FFh
08000h
010FFh
04000h
010FFh
01100h
010FFh
Segment A
Segment B
Information
Memory
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01000h
01000h
01000h
01000h
01000h
24
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peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide, literature
number SLAU056.
digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6:
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
oscillator and system clock
The clock system in the MSP430x43x(1) and MSP43x44x family of devices is supported by the FLL+ module
that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and
a high frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low
system cost and low-power consumption. The FLL+ features a digital frequency locked loop (FLL) hardware
which in conjunction with a digital modulator stabilizes the DCO frequency to a programmable multiple of the
watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs.
The FLL+ module provides the following clock signals:
D
D
D
D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, V may not
CC
have ramped to V
at that time. The user must insure the default FLL+ settings are not changed until V
CC(min)
CC
reaches V
. If desired, the SVS circuit can be used to determine when V reaches V
.
CC(min)
CC
CC(min)
hardware multiplier (MSP430x44x Only)
The multiplication operation is supported by a dedicated peripheral module. The module performs 16 16,
16 8, 8 16, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
USART0
The MSP430x43x(1) and the MSP430x44x have one hardware universal synchronous/asynchronous receive
transmit (USART0) peripheral module that is used for serial data communication. The USART supports
synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered
transmit and receive channels.
USART1 (MSP430x44x Only)
The MSP430x44x has a second hardware universal synchronous/asynchronous receive transmit (USART1)
peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4
pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.
Operation of USART1 is identical to USART0.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number
Output Pin Number
Device Input
Signal
Module Input
Name
Module
Block
Module Output
Signal
PN
PZ
PN
PZ
62 - P1.5
82 - P1.5
TACLK
ACLK
SMCLK
TACLK
TA0
TACLK
ACLK
Timer
CCR0
CCR1
CCR2
NA
TA0
TA1
TA2
SMCLK
INCLK
CCI0A
CCI0B
GND
62 - P1.5
67 - P1.0
66 - P1.1
82 - P1.5
87 - P1.0
86 - P1.1
67 - P1.0
14 - P1.2
87 - P1.0
85 - P1.2
79 - P2.0
TA0
DV
DV
SS
CC
V
CC
65 - P1.2
59 - P2.0
85 - P1.2
79 - P2.0
TA1
CAOUT (internal)
CCI1A
CCI1B
GND
ADC12 (internal)
DV
DV
SS
CC
V
CC
TA2
ACLK (internal)
CCI2A
CCI2B
GND
15 - P1.3
DV
DV
SS
CC
V
CC
timer_B3 (MSP430x43x(1) Only)
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
timer_B7 (MSP430x44x Only)
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
†
Timer_B3/B7 Signal Connections
Input Pin Number
Output Pin Number
Device Input
Signal
Module Input
Name
Module
Block
Module Output
Signal
PN
PZ
PN
PZ
63 - P1.4
83 - P1.4
TBCLK
ACLK
SMCLK
TBCLK
TB0
TBCLK
ACLK
Timer
CCR0
CCR1
CCR2
CCR3
CCR4
CCR5
CCR6
NA
SMCLK
INCLK
CCI0A
CCI0B
GND
63 - P1.4
58 - P2.1
58 - P2.1
83 - P1.4
78 - P2.1
78 - P2.1
58 - P2.1
78 - P2.1
77 - P2.2
TB0
ADC12 (internal)
TB0
TB1
TB2
TB3
TB4
TB5
TB6
DV
DV
SS
CC
V
CC
57 - P2.2
57 - P2.2
77 - P2.2
77 - P2.2
TB1
TB1
CCI1A
CCI1B
GND
57 - P2.2
ADC12 (internal)
DV
DV
SS
CC
V
CC
56 - P2.3
56 - P2.3
76 - P2.3
76 - P2.3
TB2
TB2
CCI2A
CCI2B
GND
56 - P2.3
76 - P2.3
67 - P3.4
66 - P3.5
65 - P3.6
64 - P3.7
DV
DV
SS
CC
V
CC
67 - P3.4
67 - P3.4
TB3
TB3
CCI3A
CCI3B
GND
DV
DV
SS
CC
V
CC
66 - P3.5
66 - P3.5
TB4
TB4
CCI4A
CCI4B
GND
DV
DV
SS
CC
V
CC
65 - P3.6
65 - P3.6
TB5
TB5
CCI5A
CCI5B
GND
DV
DV
SS
CC
V
CC
64 - P3.7
TB6
ACLK (internal)
CCI6A
CCI6B
GND
DV
DV
SS
CC
V
CC
†
Timer_B3 implements three capture/compare blocks (CCR0, CCR1 and CCR2 only).
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
comparator_A
The primary function of the comparator_A module is to support precision slope analog−to−digital conversions,
battery−voltage supervision, and monitoring of external analog signals.
ADC12 (Not implemented in the MSP430x43x1)
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without
any CPU intervention.
Basic Timer1
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and
clock for the LCD module.
LCD drive
The LCD driver generates the segment and common signals required to drive an LCD display. The LCD
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog timer control
Watchdog
WDTCTL
TBCCR6
TBCCR5
TBCCR4
TBCCR3
TBCCR2
TBCCR1
TBCCR0
TBR
0120h
019Eh
019Ch
019Ah
0198h
0196h
0194h
0192h
0190h
018Eh
018Ch
018Ah
0188h
0186h
0184h
0182h
0180h
011Eh
017Eh
017Ch
017Ah
0178h
0176h
0174h
0172h
0170h
016Eh
016Ch
016Ah
0168h
0166h
0164h
0162h
0160h
012Eh
013Eh
013Ch
013Ah
0138h
0136h
0134h
0132h
0130h
Timer_B7/
Timer_B3
(see Note 1)
Capture/compare register 6
Capture/compare register 5
Capture/compare register 4
Capture/compare register 3
Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_B register
Capture/compare control 6
Capture/compare control 5
Capture/compare control 4
Capture/compare control 3
Capture/compare control 2
Capture/compare control 1
Capture/compare control 0
Timer_B control
TBCCTL6
TBCCTL5
TBCCTL4
TBCCTL3
TBCCTL2
TBCCTL1
TBCCTL0
TBCTL
Timer_B interrupt vector
Reserved
TBIV
Timer_A3
Reserved
Reserved
Reserved
Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_A register
TACCR2
TACCR1
TACCR0
TAR
Reserved
Reserved
Reserved
Reserved
Capture/compare control 2
Capture/compare control 1
Capture/compare control 0
Timer_A control
TACCTL2
TACCTL1
TACCTL0
TACTL
TAIV
Timer_A interrupt vector
Sum extend
Hardware
Multiplier
(MSP430x44x only)
SUMEXT
RESHI
RESLO
OP2
Result high word
Result low word
Second operand
Multiply signed + accumulate/operand1
Multiply + accumulate/operand1
Multiply signed/operand1
Multiply unsigned/operand1
MACS
MAC
MPYS
MPY
NOTE 1: Timer_B7 in the MSP430x44x family has seven CCRs; Timer_B3 in the MSP430x43x(1) family has three CCRs.
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
peripheral file map (continued)
PERIPHERALS WITH WORD ACCESS (CONTINUED)
Flash control 3 FCTL3
Flash
012Ch
012Ah
0128h
Flash control 2
FCTL2
FCTL1
Flash control 1
ADC12
Conversion memory 15
Conversion memory 14
Conversion memory 13
Conversion memory 12
Conversion memory 11
Conversion memory 10
Conversion memory 9
ADC12MEM15 015Eh
ADC12MEM14 015Ch
ADC12MEM13 015Ah
ADC12MEM12 0158h
ADC12MEM11 0156h
ADC12MEM10 0154h
ADC12MEM9
ADC12MEM8
ADC12MEM7
ADC12MEM6
ADC12MEM5
ADC12MEM4
ADC12MEM3
ADC12MEM2
ADC12MEM1
ADC12MEM0
ADC12IV
0152h
0150h
014Eh
014Ch
014Ah
0148h
0146h
0144h
0142h
0140h
01A8h
01A6h
01A4h
01A2h
01A0h
Conversion memory 8
Conversion memory 7
Conversion memory 6
Conversion memory 5
Conversion memory 4
Conversion memory 3
Conversion memory 2
Conversion memory 1
Conversion memory 0
Interrupt-vector-word register
Inerrupt-enable register
Inerrupt-flag register
ADC12IE
ADC12IFG
Control register 1
ADC12CTL1
ADC12CTL0
Control register 0
ADC memory-control register15
ADC memory-control register14
ADC memory-control register13
ADC memory-control register12
ADC memory-control register11
ADC memory-control register10
ADC memory-control register9
ADC memory-control register8
ADC memory-control register7
ADC memory-control register6
ADC memory-control register5
ADC memory-control register4
ADC memory-control register3
ADC memory-control register2
ADC memory-control register1
ADC memory-control register0
ADC12MCTL15 08Fh
ADC12MCTL14 08Eh
ADC12MCTL13 08Dh
ADC12MCTL12 08Ch
ADC12MCTL11 08Bh
ADC12MCTL10 08Ah
ADC12MCTL9
ADC12MCTL8
ADC12MCTL7
ADC12MCTL6
ADC12MCTL5
ADC12MCTL4
ADC12MCTL3
ADC12MCTL2
ADC12MCTL1
ADC12MCTL0
089h
088h
087h
086h
085h
084h
083h
082h
081h
080h
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
LCD memory 20
LCD
LCDM20
:
0A4h
:
:
LCD memory 16
LCD memory 15
:
LCDM16
LCDM15
:
0A0h
09Fh
:
LCD memory 1
LCD control and mode
Transmit buffer
Receive buffer
Baud rate
LCDM1
LCDCTL
U1TXBUF
U1RXBUF
U1BR1
U1BR0
U1MCTL
U1RCTL
U1TCTL
U1CTL
091h
090h
07Fh
07Eh
07Dh
07Ch
07Bh
07Ah
079h
078h
077h
076h
075h
074h
073h
072h
071h
070h
05Bh
05Ah
059h
056h
054h
053h
052h
051h
050h
047h
046h
040h
037h
036h
035h
034h
033h
032h
031h
030h
USART1
(Only in ‘x44x)
Baud rate
Modulation control
Receive control
Transmit control
USART control
Transmit buffer
Receive buffer
Baud rate
USART0
U0TXBUF
U0RXBUF
U0BR1
U0BR0
U0MCTL
U0RCTL
U0TCTL
U0CTL
Baud rate
Modulation control
Receive control
Transmit control
USART control
Comparator_A port disable
Comparator_A control2
Comparator_A control1
Comparator_A
CAPD
CACTL2
CACTL1
BrownOUT, SVS
FLL+ Clock
SVS control register (Reset by brownout signal) SVSCTL
FLL+ Control1
FLL_CTL1
FLL_CTL0
SCFQCTL
SCFI1
FLL+ Control0
System clock frequency control
System clock frequency integrator
System clock frequency integrator
BT counter2
SCFI0
Basic Timer1
Port P6
BTCNT2
BTCNT1
BTCTL
P6SEL
P6DIR
BT counter1
BT control
Port P6 selection
Port P6 direction
Port P6 output
P6OUT
P6IN
Port P6 input
Port P5
Port P5 selection
Port P5 direction
Port P5 output
P5SEL
P5DIR
P5OUT
P5IN
Port P5 input
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P4
Port P3
Port P2
Port P4 selection
Port P4 direction
P4SEL
P4DIR
P4OUT
P4IN
01Fh
01Eh
01Dh
01Ch
01Bh
01Ah
019h
018h
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
026h
025h
024h
023h
022h
021h
020h
005h
004h
003h
002h
001h
000h
Port P4 output
Port P4 input
Port P3 selection
Port P3 direction
P3SEL
P3DIR
P3OUT
P3IN
Port P3 output
Port P3 input
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt-edge select
Port P2 interrupt flag
Port P2 direction
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
Port P2 output
Port P2 input
Port P1
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt-edge select
Port P1 interrupt flag
Port P1 direction
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
Port P1 output
Port P1 input
Special functions
SFR module enable2
SFR module enable1
SFR interrupt flag2
SFR interrupt flag1
SFR interrupt enable2
SFR interrupt enable1
ME2
ME1
IFG2
IFG1
IE2
IE1
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Voltage applied at V to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
CC
SS
Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.3 V
CC
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature, T : (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
stg
(programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to V . The JTAG fuse-blow voltage, V , is allowed to exceed the absolute maximum rating. The voltage is applied
SS
FB
to the TDI/TCLK pin when blowing the JTAG fuse.
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
recommended operating conditions
MIN
NOM
MAX UNITS
Supply voltage during program execution
MSP430F43x(1),
MSP430F44x
1.8
3.6
V
V
CC
(AV = DV
= DV = V ) (see Note 1)
CC2 CC
CC
CC1
Supply voltage during program execution, SVS enabled, PORON=1
(see Note 1 and Note 2)
MSP430F43x(1),
MSP430F44x
2
3.6
V
V
CC
(AV = DV
= DV
= V
)
CC
CC1
CC2
CC
Supply voltage during flash memory programming
(AV = DV = DV = V ) (see Note 1)
MSP430F43x(1),
MSP430F44x
2.7
0
3.6
0
V
V
V
CC
CC
CC1
CC2
CC
Supply voltage, V (AV = DV
= DV
= V
)
SS
SS
SS1
SS2
SS
MSP430x43x(1),
MSP430x44x
Operating free-air temperature range, T
−40
85
°C
A
LF selected,
XTS_FLL=0
Watch crystal
Ceramic resonator
Crystal
32.768
kHz
kHz
kHz
XT1 selected,
XTS_FLL=1
LFXT1 crystal frequency, f
(see Note 3)
(LFXT1)
450
8000
8000
XT1 selected,
XTS_FLL=1
1000
Ceramic resonator
Crystal
450
1000
DC
8000
8000
4.15
8
XT2 crystal frequency, f
kHz
(XT2)
V
CC
V
CC
= 1.8 V
= 3.6 V
Processor frequency (signal MCLK), f
MHz
(System)
DC
NOTES: 1. It is recommended to power AV and DV from the same source. A maximum difference of 0.3 V between AV and DV can
CC
CC
CC
CC
be tolerated during power up and operation.
2. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply
voltage. POR is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the SVS
circuitry.
3. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
f
(MHz)
System
8 MHz
Supply voltage range,
’F43x(1)/’F44x, during
program execution
Supply voltage range, ’F43x(1)/’F44x,
during flash memory programming
4.15 MHz
1.8
2.7
3
3.6
Supply Voltage − V
Figure 1. Frequency vs Supply Voltage, MSP430F43x(1) or MSP430F44x
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AV + DV excluding external current
CC
CC
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
Active mode, (see Note 1)
V
V
= 2.2 V
= 3 V
280
350
CC
f
f
= f
= 1 MHz,
(MCLK)
(SMCLK)
I
I
I
T = −40°C to 85°C
A
μA
(AM)
= 32,768 Hz
(ACLK)
420
560
CC
XTS_FLL=0, SELM=(0,1)
V
V
= 2.2 V
= 3 V
32
55
45
70
CC
Low-power mode, (LPM0)
(see Note 1 and Note 4)
T = −40°C to 85°C
μA
μA
(LPM0)
(LPM2)
A
CC
Low-power mode, (LPM2),
V
= 2.2 V
= 3 V
11
17
14
22
CC
CC
f(MCLK) = f (SMCLK) = 0 MHz,
f(ACLK) = 32,768 Hz, SCG0 = 0 (see Note 2 and
Note 4)
T = −40°C to 85°C
A
V
T = −40°C
1
1.1
2
1.5
1.5
3
A
T = 25°C
A
V
CC
V
CC
V
CC
V
CC
= 2.2 V
μA
μA
μA
μA
Low-power mode, (LPM3)
T = 60°C
A
f
f
= f
= 0 MHz,
(MCLK)
(SMCLK)
T = 85°C
A
3.5
1.8
1.6
2.5
4.2
0.1
0.1
0.7
1.7
0.1
0.1
0.8
1.9
6
= 32,768 Hz, SCG0 = 1
(ACLK)
I
(LPM3)
(see Note 3 and Note 4)
T = −40°C
A
2.2
1.9
3.5
7.5
0.5
0.5
1.1
3
T = 25°C
A
= 3 V
T = 60°C
A
T = 85°C
A
T = −40°C
A
T = 25°C
A
= 2.2 V
T = 60°C
A
Low-power mode, (LPM4)
T = 85°C
A
f
f
= 0 MHz, f
= 0 Hz, SCG0 = 1
= 0 MHz,
(MCLK)
(SMCLK)
I
(LPM4)
T = −40°C
A
0.5
0.5
1.2
3.5
(ACLK)
(see Note 2 and Note 4)
T = 25°C
A
= 3 V
T = 60°C
A
T = 85°C
A
NOTES: 1. Timer_B is clocked by f
= f = 1 MHz. All inputs are tied to 0 V or to V . Outputs do not source or sink any current.
(DCO) CC
(DCOCLK)
2. All inputs are tied to 0 V or to V . Outputs do not source or sink any current.
CC
3. All inputs are tied to 0 V or to V . Outputs do not source or sink any current. The current consumption in LPM3 is measured with
CC
active Basic Timer1 and LCD (ACLK selected). The current consumption of the Comparator_A and the SVS module are specified
in the respective sections. The LPM3 currents are characterized with a KDS Daishinku DT−38 (6 pF) crystal and OSCCAPx=1h.
4. Current consumption for brownout included.
Current consumption of active mode versus system frequency
I
= I
[1 MHz] × f
[MHz]
(AM)
(AM)
(System)
Current consumption of active mode versus supply voltage
= I + 175 μA/V × (V – 3 V)
I
(AM)
(AM) [3 V]
CC
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SCHMITT-trigger inputs − ports P1, P2, P3, P4, P5, and P6
PARAMETER
TEST CONDITIONS
MIN
1.1
1.5
0.4
0.9
0.3
0.5
TYP
MAX
1.5
1.9
0.9
1.3
1.1
1
UNIT
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.2 V
= 3 V
V
IT+
V
IT−
V
hys
Positive-going input threshold voltage
V
= 2.2 V
= 3 V
Negative-going input threshold voltage
V
V
= 2.2 V
= 3 V
Input voltage hysteresis (V − V
)
IT−
IT+
standard inputs − RST/NMI; JTAG: TCK, TMS, TDI/TCLK
PARAMETER
TEST CONDITIONS
= 2.2 V / 3 V
MIN
TYP
MAX
UNIT
V
V
V
Low-level input voltage
High-level input voltage
V
V
+0.6
IL
SS
CC
SS
V
CC
0.8×V
V
CC
V
IH
inputs Px.x, TAx, TBx
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
2.2 V/3 V
2.2 V
1.5
62
50
62
cycle
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag, (see Note 1)
t
External interrupt timing
(int)
ns
3 V
TA0, TA1, TA2
2.2 V
Timer_A, Timer_B capture
timing
t
ns
(cap)
TB0, TB1, TB2, TB3, TB4, TB5, TB6
(see Note 2)
3 V
50
Timer_A, Timer_B clock
frequency externally applied
to pin
f
f
2.2 V
3 V
8
(TAext)
TACLK, TBCLK, INCLK: t = t
MHz
MHz
(H)
(L)
10
(TBext)
f
f
2.2 V
3 V
8
(TAint)
Timer_A, Timer_B clock
frequency
SMCLK or ACLK signal selected
10
(TBint)
NOTES: 1. The external signal sets the interrupt flag every time the minimum t
cycle and time parameters are met. It may be set even with
(int)
trigger signals shorter than t . Both the cycle and timing specifications must be met to ensure the flag is set. t
is measured in
(int)
(int)
MCLK cycles.
2. Seven capture/compare registers in ’x44x and three capture/compare registers in ’x43x(1).
leakage current (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
I
I
I
I
I
Port P1 Port 1: V
Port P2 Port 2: V
Port P3 Port 3: V
Port P4 Port 4: V
Port P5 Port 5: V
Port P6 Port 6: V
±50
±50
±50
±50
±50
±50
lkg(P1.x)
lkg(P2.x)
lkg(P3.x)
lkg(P4.x)
lkg(P5.x)
lkg(P6.x)
(P1.x)
(P2.x)
(P3.x)
(P4.x)
(P5.x)
(P6.x)
Leakage
current
V
CC
= 2.2 V/3 V
nA
NOTES: 1. The leakage current is measured with V or V applied to the corresponding pin(s), unless otherwise noted.
SS
CC
2. The port pin must be selected as input and there must be no optional pullup or pulldown resistor.
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − ports P1, P2, P3, P4, P5, and P6
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
I
I
I
I
I
I
I
= −1.5 mA,
= −6 mA,
= −1.5 mA,
= −6 mA,
= 1.5 mA,
= 6 mA,
V
V
V
V
V
V
V
V
= 2.2 V,
= 2.2 V,
= 3 V,
See Note 1
See Note 2
See Note 1
See Note 2
See Note 1
See Note 2
See Note 1
See Note 2
V
−0.25
V
V
V
V
OH(max)
OH(max)
OH(max)
OH(max)
OL(max)
OL(max)
OL(max)
OL(max)
OH(max)
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
V
−0.6
CC
V
High-level output voltage
V
OH
V
CC
−0.25
= 3 V,
V
−0.6
CC
= 2.2 V,
= 2.2 V,
= 3 V,
V
SS
V
SS
V
SS
V
SS
V
+0.25
SS
V
+0.6
SS
V
OL
Low-level output voltage
V
= 1.5 mA,
= 6 mA,
V
SS
+0.25
= 3 V,
V
+0.6
SS
NOTES: 1. The maximum total current, I
specified voltage drop.
and I
for all outputs combined, should not exceed ±12 mA to satisfy the maximum
OL(max),
2. The maximum total current, I
specified voltage drop.
and I
for all outputs combined, should not exceed ±48 mA to satisfy the maximum
OH(max)
OL(max),
output frequency
PARAMETER
TEST CONDITIONS
MIN
DC
DC
TYP
MAX
5
UNIT
V
CC
CC
= 2.2 V
= 3 V
C = 20 pF,
I = ±1.5 mA
L
L
f
(1 ≤ x ≤ 6, 0 ≤ y ≤ 7)
MHz
(Px.y)
V
7.5
f
f
f
(ACLK)
P1.1/TA0/MCLK, P1.5/TACLK/
ACLK P1.4/TBCLK/SMCLK
C = 20 pF
L
f
MHz
(MCLK)
(SMCLK)
(System)
f
f
f
f
= f
= f
= f
= f
= f
40%
30%
60%
70%
(ACLK)
(ACLK)
(ACLK)
(MCLK)
(LFXT1)
(LFXT1)
(LFXT1)
(XT1)
P1.5/TACLK/ACLK,
C = 20 pF
(LF)
L
V
CC
= 2.2 V / 3 V
50%
50%
= f
40%
60%
(XT1)
(DCOCLK)
P1.1/TA0/MCLK,
t
Duty cycle of output frequency
C = 20 pF,
(Xdc)
50%−
15 ns
50%+
15 ns
L
f
f
f
= f
(MCLK)
V
CC
= 2.2 V / 3 V
= f
40%
60%
(SMCLK)
(SMCLK)
(XT2)
P1.4/TBCLK/SMCLK,
C = 20 pF,
50%−
15 ns
50%+
15 ns
L
= f
50%
(DCOCLK)
V
CC
= 2.2 V / 3 V
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1, P2, P3, P4, P5, and P6 (continued)
TYPICAL LOW-LEVEL OUTPUT CURRENT
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
16
14
12
10
8
25
20
15
10
5
V
P2.7
= 2.2 V
T
= 25°C
V
P2.7
= 3 V
CC
A
CC
T
= 25°C
A
T
= 85°C
A
T
= 85°C
A
6
4
2
0
0.0
0
0.0
0.5
1.0
1.5
2.0
2.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OL
− Low-Level Output Voltage − V
V
OL
− Low-Level Output Voltage − V
Figure 2
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
0
−2
0
−5
V
P2.7
= 2.2 V
CC
V
P2.7
= 3 V
CC
−4
−10
−15
−20
−25
−30
−6
−8
T
A
= 85°C
−10
−12
−14
T
A
= 85°C
T
A
= 25°C
T
A
= 25°C
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OH
− High-Level Output Voltage − V
V
OH
− High-Level Output Voltage − V
Figure 4
Figure 5
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER
PARAMETER
TEST CONDITIONS
f = 1 MHz
MIN
TYP
MAX
UNIT
6
6
6
f = 2 MHz
f = 3 MHz
t
Delay time
V
CC
= 2.2 V/3 V
μs
d(LPM3)
RAM
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VRAMh
CPU halted (see Note 1)
1.6
V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
LCD
PARAMETER
TEST CONDITIONS
Voltage at P5.7/R33
MIN
TYP
MAX
UNIT
V
V
V
V
I
2.5
V
V
+ 0.2
(33)
(23)
(13)
(33)
CC
Voltage at P5.6/R23
Voltage at P5.5/R13
Voltage at R33 to R03
[V −V ] × 2/3 + V
(33) (03)
(03)
Analog voltage
V
CC
= 3 V
V
[V −V ] × 1/3 + V
(33) (03)
(03)
− V
2.5
+ 0.2
(03)
CC
R03 = V
±20
No load at all
segment and
common lines,
(R03)
(R13)
(R23)
SS
I
I
P5.5/R13 = V /3
±20
±20
Input leakage
nA
V
CC
P5.6/R23 = 2 × V /3
V
CC
= 3 V
CC
V
V
V
V
V
(03)
V
(13)
V
(23)
V
(33)
V
(03)
V
(13)
V
(23)
V
(33)
− 0.1
(Sxx0)
− 0.1
− 0.1
+ 0.1
(Sxx1)
(Sxx2)
(Sxx3)
Segment line
voltage
I
= −3 μA,
V
CC
= 3 V
(Sxx)
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Comparator_A (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
25
MAX
40
UNIT
V
CC
V
CC
V
CC
V
CC
= 2.2 V
= 3 V
I
I
CAON=1, CARSEL=0, CAREF=0
μA
(CC)
45
30
45
60
50
71
= 2.2 V
= 3 V
CAON=1, CARSEL=0, CAREF=1/2/3,
No load at P1.6/CA0 and P1.7/CA1
μA
(Refladder/RefDiode)
Voltage @ 0.25 V
node
node
PCA0=1, CARSEL=1, CAREF=1,
No load at P1.6/CA0 and P1.7/CA1
CC
V
V
V
= 2.2 V / 3 V
= 2.2V / 3 V
0.23
0.47
0.24
0.48
0.25
0.5
(Ref025)
(Ref050)
CC
V
CC
Voltage @ 0.5 V
PCA0=1, CARSEL=1, CAREF=2,
No load at P1.6/CA0 and P1.7/CA1
CC
V
CC
V
CC
PCA0=1, CARSEL=1, CAREF=3,
No load at P1.6/CA0 and P1.7/CA1;
T = 85°C
A
V
V
= 2.2 V
= 3 V
390
400
480
490
540
550
CC
V
V
See Figure 6 and Figure 7
mV
V
(RefVT)
CC
Common-mode input
voltage range
CAON=1
V
CC
= 2.2 V / 3 V
0
V
−1
30
IC
CC
V −V
p
Offset voltage
See Note 2
CAON = 1
VCC = 2.2 V / 3 V
−30
0
mV
mV
S
V
hys
Input hysteresis
V
= 2.2 V / 3 V
= 2.2 V
= 3 V
0.7
210
150
1.9
1.4
300
240
3.4
CC
CC
CC
CC
CC
CC
CC
CC
CC
V
160
80
T = 25°C,
A
ns
μs
ns
μs
Overdrive 10 mV, without filter: CAF = 0
V
t
(response LH)
(response HL)
V
= 2.2 V
= 3 V
1.4
0.9
130
80
T = 25°C
A
Overdrive 10 mV, with filter: CAF = 1
V
1.5
2.6
V
= 2.2 V
= 3 V
210
150
1.9
300
240
3.4
T = 25°C
A
Overdrive 10 mV, without filter: CAF = 0
V
t
V
V
= 2.2 V
= 3 V
1.4
0.9
T = 25°C,
A
Overdrive 10 mV, with filter: CAF = 1
1.5
2.6
NOTES: 1. The leakage current for the Comparator_A terminals is identical to I
specification.
lkg(Px.x)
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
typical characteristics
REFERENCE VOLTAGE
vs
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
650
600
550
500
450
400
650
600
550
500
450
400
V
CC
= 3 V
V
= 2.2 V
CC
Typical
Typical
−45
−25
−5
15
35
55
75
95
−45
−25
−5
15
35
55
75
95
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 6. V
vs Temperature
Figure 7. V
vs Temperature
(RefVT)
(RefVT)
0 V
V
CC
CAF
0
1
CAON
To Internal
Modules
Low-Pass Filter
0
1
0
1
+
_
V+
V−
CAOUT
Set CAIFG
Flag
τ ≈ 2 μs
Figure 8. Block Diagram of Comparator_A Module
V
CAOUT
Overdrive
V−
400 mV
V+
t
(response)
Figure 9. Overdrive Definition
40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
POR/brownout reset (BOR) (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
μs
t
2000
d(BOR)
V
V
V
dV /dt ≤ 3 V/s (see Figure 10)
0.7 × V
(B_IT−)
V
CC(start)
(B_IT−)
CC
Brownout
(see Note 2)
dV /dt ≤ 3 V/s (see Figure 10 through Figure 12)
CC
1.71
180
V
dV /dt ≤ 3 V/s (see Figure 10)
CC
70
2
130
mV
hys(B_IT−)
Pulse length needed at RST/NMI pin to accepted reset internally,
t
μs
(reset)
V
CC
= 2.2 V/3 V
NOTES: 1. The current consumption of the brownout module is already included in the I current consumption data. The voltage level
CC
V
+ V
is ≤ 1.8V.
(B_IT−)
hys(B_IT−)
2. During power up, the CPU begins code execution following a period of t
after V = V
+ V . The default FLL+
hys(B_IT−)
d(BOR)
CC
(B_IT−)
settings must not be changed until V ≥ V
, where V
is the minimum supply voltage for the desired
CC
CC(min)
CC(min)
operating frequency. See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout/SVS circuit.
typical characteristics
V
CC
V
hys(B_IT−)
V
(B_IT−)
V
CC(start)
1
0
t
d(BOR)
Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage
V
t
CC
pw
2
3 V
V
CC
= 3 V
Typical Conditions
1.5
1
V
CC(drop)
0.5
0
0.001
1
1000
1 ns
1 ns
− Pulse Width − μs
t
− Pulse Width − μs
t
pw
pw
Figure 11. V
Level With a Square Voltage Drop to Generate a POR/Brownout Signal
CC(drop)
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
typical characteristics (Continued)
V
t
CC
pw
2
3 V
V
CC
= 3 V
1.5
1
Typical Conditions
V
CC(drop)
0.5
0
t = t
f
r
0.001
1
1000
t
t
r
f
t
− Pulse Width − μs
t
− Pulse Width − μs
pw
pw
Figure 12. V
Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
CC(drop)
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SVS (supply voltage supervisor/monitor)
PARAMETER
TEST CONDITIONS
dV /dt > 30 V/ms (see Figure 13)
MIN
NOM
MAX
150
2000
150
12
UNIT
μs
5
CC
t
(SVSR)
dV /dt ≤ 30 V/ms
CC
μs
t
t
SVSon, switch from VLD=0 to VLD ≠ 0, V = 3 V
20
μs
d(SVSon)
CC
‡
VLD ≠ 0
μs
settle
V
VLD ≠ 0, V /dt ≤ 3 V/s (see Figure 13)
1.55
120
1.7
V
(SVSstart)
CC
VLD = 1
70
155
mV
V
V
/dt ≤ 3 V/s (see Figure 13)
V
V
(SVS_IT−)
× 0.008
CC
(SVS_IT−)
× 0.004
VLD = 2 .. 14
V
hys(SVS_IT−)
/dt ≤ 3 V/s (see Figure 13), external voltage applied
CC
VLD = 15
4.4
10.4
mV
on A7
VLD = 1
VLD = 2
VLD = 3
VLD = 4
VLD = 5
VLD = 6
VLD = 7
VLD = 8
VLD = 9
VLD = 10
VLD = 11
VLD = 12
VLD = 13
VLD = 14
1.8
1.9
2.1
2.05
2.25
2.37
2.48
2.6
1.94
2.05
2.14
2.24
2.33
2.46
2.58
2.69
2.83
2.94
3.11
3.24
3.43
2.2
2.3
2.4
2.5
2.71
2.86
3
2.65
2.8
V
CC
/dt ≤ 3 V/s (see Figure 13)
V
V
(SVS_IT−)
2.9
3.13
3.29
3.42
3.05
3.2
†
3.35
3.61
†
3.5
3.76
†
†
3.7
3.99
V
on A7
/dt ≤ 3 V/s (see Figure 13), external voltage applied
CC
VLD = 15
1.1
1.2
10
1.3
15
I
CC(SVS)
VLD ≠ 0, V = 2.2 V/3 V
μA
CC
(see Note 1)
†
‡
The recommended operating voltage range is limited to 3.6 V.
is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
t
settle
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 1: The current consumption of the SVS module is not included in the I current consumption data.
CC
42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
typical characteristics
Software Sets VLD>0:
SVS is Active
V
CC
V
hys(SVS_IT−)
V
(SVS_IT−)
V
(SVSstart)
V
hys(B_IT−)
V
(B_IT−)
V
CC(start)
Brown-
Out
Region
Brownout
Region
Brownout
1
0
t
t
SVS
d(BOR)
d(BOR)
Out
SVS Circuit is Active From VLD > to V < V(
CC
B_IT−)
1
0
t
t
d(SVSon)
d(SVSR)
Set POR
1
undefined
0
Figure 13. SVS Reset (SVSR) vs Supply Voltage
V
CC
t
pw
3 V
2
1.5
1
Rectangular Drop
V
CC(drop)
Triangular Drop
1 ns
1 ns
V
t
CC
0.5
pw
3 V
0
1
10
100
1000
V
t
− Pulse Width − μs
pw
CC(drop)
t = t
f
r
t
t
r
f
t − Pulse Width − μs
Figure 14. V
With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
CC(drop)
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
DCO
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
MHz
N
f
=01Eh, FN_8=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0,
= 32.768 kHz
(DCO)
Crystal
f
f
f
f
f
f
f
f
f
f
f
V
CC
= 2.2 V/3 V
1
(DCOCLK)
(DCO=2)
(DCO=27)
(DCO=2)
(DCO=27)
(DCO=2)
(DCO=27)
(DCO=2)
(DCO=27)
(DCO=2)
(DCO=27)
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 2.2 V
= 3 V
0.3
0.3
2.5
2.7
0.7
0.8
5.7
6.5
1.2
1.3
9
0.65
0.7
5.6
6.1
1.3
1.5
10.8
12.1
2
1.25
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
FN_8=FN_4=FN_3=FN_2=0; DCOPLUS = 1
MHz
1.3
= 2.2 V
= 3 V
10.5
FN_8=FN_4=FN_3=FN_2=0; DCOPLUS = 1
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1
MHz
11.3
= 2.2 V
= 3 V
2.3
MHz
2.5
= 2.2 V
= 3 V
18
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1
FN_8=0, FN_4= 1, FN_3= FN_2=x; DCOPLUS = 1
FN_8=0, FN_4=1, FN_3= FN_2=x; DCOPLUS = 1
FN_8=1, FN_4=FN_3=FN_2=x; DCOPLUS = 1
MHz
20
= 2.2 V
= 3 V
3
MHz
2.2
15.5
17.9
2.8
3.4
21.5
26.6
4.2
6.3
32
3.5
= 2.2 V
= 3 V
25
MHz
10.3
1.8
2.1
13.5
16
28.5
= 2.2 V
= 3 V
4.2
MHz
5.2
= 2.2 V
= 3 V
33
MHz
41
= 2.2 V
= 3 V
2.8
4.2
21
6.2
MHz
9.2
= 2.2 V
= 3 V
46
FN_8=1,FN_4=FN_3=FN_2=x; DCOPLUS = 1
Step size between adjacent DCO taps:
MHz
30
46
70
1 < TAP ≤ 20
1.06
1.07
–0.2
–0.2
1.11
1.17
–0.4
S
n
S = f
/ f
, (see Figure 16 for taps 21 to 27)
n
DCO(Tap n+1) DCO(Tap n)
TAP = 27
V
CC
V
CC
= 2.2 V
= 3 V
–0.3
–0.3
D
Temperature drift, N
= 01Eh, FN_8=FN_4=FN_3=FN_2=0
t
(DCO)
%/C
D = 2; DCOPLUS = 0
–0.4
Drift with V variation, N
FN_8=FN_4=FN_3=FN_2=0, D= 2; DCOPLUS = 0
= 01Eh,
(DCO)
CC
V
CC
= 2.2 V/3 V
0
5
15
%/V
D
V
f
f
(DCO)
(DCO)
f
f
5
(DCO3V)
(DCO20 C)
1.0
1.0
0
1.8
2.4
3.0
3.6
−40
−20
0
20
40
60
85
V
CC
− V
T − °C
A
Figure 15. DCO Frequency vs Supply Voltage V and vs Ambient Temperature
CC
44
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
1.17
Max
1.11
1.07
1.06
Min
1
20
27
DCO Tap
Figure 16. DCO Tap Step Size
Legend
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
9
5
2 to 2 in SCFI1 {N
}
(DCO)
Tolerance at Tap 2
Overlapping DCO Ranges:
uninterrupted frequency range
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_3=x
FN_4=x
FN_8=1
Figure 17. Five Overlapping DCO Ranges Controlled by FN_x Bits
45
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
OSCCAPx = 0h, V = 2.2 V / 3 V
MIN
TYP
0
MAX
UNIT
CC
OSCCAPx = 1h, V = 2.2 V / 3 V
10
14
18
0
CC
C
C
Integrated input capacitance
pF
XIN
OSCCAPx = 2h, V = 2.2 V / 3 V
CC
OSCCAPx = 3h, V = 2.2 V / 3 V
CC
OSCCAPx = 0h, V = 2.2 V / 3 V
CC
OSCCAPx = 1h, V = 2.2 V / 3 V
10
14
18
CC
Integrated output capacitance
Input levels at XIN
pF
XOUT
OSCCAPx = 2h, V = 2.2 V / 3 V
CC
OSCCAPx = 3h, V = 2.2 V / 3 V
CC
V
V
V
0.2 × V
CC
V
V
IL
SS
V
CC
= 2.2 V/3 V (see Note 3)
0.8 × V
V
CC
IH
CC
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is
(C x C ) / (C + C ). This is independent of XTS_FLL.
XIN
XOUT
XIN
XOUT
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.
− Keep as short of a trace as possible between the ’F43x(1)/44x and the crystal.
− Design a good ground plane around the oscillator pins.
− Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
− Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
− Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
− If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
− Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.
4. External capacitance is recommended for precision real-time clock applications; OSCCAPx = 0h.
crystal oscillator, XT2 oscillator (see Note 1)
PARAMETER
TEST CONDITIONS
= 2.2 V/3 V
MIN
NOM
MAX
UNIT
pF
pF
V
C
C
Integrated input capacitance
Integrated output capacitance
V
V
2
2
XT2IN
XT2OUT
IL
CC
= 2.2 V/3 V
CC
V
V
V
SS
0.2 × V
CC
Input levels at XT2IN
V
CC
= 2.2 V/3 V (see Note 2)
0.8 × V
V
CC
V
IH
CC
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
USART0, USART1 (see Note 1)
PARAMETER
TEST CONDITIONS
= 2.2 V, SYNC = 0, UART mode
= 3 V, SYNC = 0, UART mode
MIN
200
150
NOM MAX
UNIT
V
V
430
280
800
500
CC
t
τ
( )
USART0/1: deglitch time
ns
CC
NOTE 1: The signal applied to the USART0/1 receive signal/terminal (URXD0/1) should meet the timing requirements of t to ensure that the
(τ
)
URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t . The operating
(τ
)
conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative
transitions on the URXD0/1 line.
46
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, power supply and input range conditions (see Note 1)
PARAMETER
TEST CONDITIONS
AV and DV are connected together
V
CC
MIN NOM
MAX
UNIT
CC
CC
AV
Analog supply voltage
AV and DV are connected together
2.2
3.6
V
CC
SS
SS
V
(AVSS)
= V
= 0 V
(DVSS)
All P6.0/A0 to P6.7/A7 terminals. Analog inputs
selected in ADC12MCTLx register and P6Sel.x=1
Analog input voltage
range (see Note 2)
V
0
V
AVCC
V
(P6.x/Ax)
0 ≤ x ≤ 7; V
≤ V
≤ V
(AVSS)
P6.x/Ax (AVCC)
Operating supply current
f
= 5.0 MHz
2.2 V
3 V
0.65
0.8
1.3
1.6
ADC12CLK
into AV terminal
ADC12ON = 1, REFON = 0
SHT0=0, SHT1=0, ADC12DIV=0
I
mA
mA
CC
ADC12
REF+
(see Note 3)
f
= 5.0 MHz
ADC12CLK
ADC12ON = 0,
REFON = 1, REF2_5V = 1
3 V
0.5
0.8
Operating supply current
I
into AV terminal
CC
f
= 5.0 MHz
2.2 V
3 V
0.5
0.5
0.8
0.8
ADC12CLK
(see Note 4)
ADC12ON = 0,
REFON = 1, REF2_5V = 0
mA
Only one terminal can be selected
at one time, P6.x/Ax
C
R
Input capacitance
2.2 V
3 V
40
pF
I
I
Input MUX ON resistance 0V ≤ V ≤ V
2000
Ω
Ax
AVCC
NOTES: 1. The leakage current is defined in the leakage current table with P6.x/Ax parameter.
2. The analog input voltage range must be within the selected reference voltage range V to V for valid conversion results.
R+
R−
3. The internal reference supply current is not included in current consumption parameter I
.
ADC12
4. The internal reference current is supplied via terminal AV . Consumption is independent of the ADC12ON control bit, unless a
CC
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
12-bit ADC, external reference (see Note 1)
PARAMETER
TEST CONDITIONS
V
CC
MIN NOM
MAX
UNIT
Positive external
reference voltage input
V
V
> V
> V
/V
(see Note 2)
(see Note 3)
(see Note 4)
1.4
V
V
eREF+
eREF+
REF− eREF−
AVCC
Negative external
reference voltage input
V
V
V
eREF+
/V
REF− eREF−
0
1.2
V
V
REF− / eREF−
(V
−
Differential external
reference voltage input
eREF+
V
eREF+
> V
/V
1.4
V
AVCC
REF− eREF−
V
V
)
REF−/ eREF−
I
I
Static input current
Static input current
0V ≤V
≤ V
2.2 V/3 V
2.2 V/3 V
±1
±1
μA
μA
VeREF+
eREF+
AVCC
0V ≤ V
≤ V
AVCC
VREF−/VeREF−
eREF−
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, C , is also
i
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
47
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, built-in reference
PARAMETER
TEST CONDITIONS
REF2_5V = 1 for 2.5 V
≤ I max
V
MIN NOM
MAX
UNIT
CC
3 V
2.4
2.5
1.5
2.6
I
VREF+
VREF+
Positive built-in reference
voltage output
V
REF+
V
REF2_5V = 0 for 1.5 V
2.2 V/3 V
1.44
2.2
1.56
I
≤ I max
VREF+
VREF+
REF2_5V = 0, I
REF2_5V = 1, I
REF2_5V = 1, I
≤ 1mA
≤ 0.5mA
≤ 1mA
VREF+
VREF+
VREF+
AV minimum voltage,
CC
V
V
+ 0.15
Positive built-in reference
active
AV
V
REF+
REF+
CC(min)
+ 0.15
2.2 V
3 V
0.01
−0.5
−1
Load current out of V
terminal
REF+
I
mA
VREF+
I
= 500 μA +/− 100 μA
2.2 V
3 V
±2
±2
VREF+
Analog input voltage ~0.75 V;
REF2_5V = 0
LSB
Load-current regulation
terminal
I
L(VREF)+
V
REF+
I
= 500 μA ± 100 μA
VREF+
Analog input voltage ~1.25 V;
REF2_5V = 1
3 V
3 V
±2
LSB
I
=100 μA → 900 μA,
=5 μF, Ax ~0.5 x V
VREF+
Load current regulation
terminal
C
I
20
ns
VREF+
REF+
DL(VREF) +
V
REF+
Error of conversion result ≤ 1 LSB
Capacitance at pin V
(see Note 1)
REFON =1,
REF+
C
2.2 V/3 V
2.2 V/3 V
5
10
μF
VREF+
0 mA ≤ I
≤ I
max
VREF+
VREF+
Temperature coefficient of
built-in reference
I
is a constant in the range of
VREF+
T
REF+
±100 ppm/°C
0 mA ≤ I
≤ 1 mA
VREF+
Settle time of internal
reference voltage (see
Figure 18 and Note 2)
I
V
= 0.5 mA, C
= 1.5 V
= 10μF,
VREF+
VREF+
2.2 V
17
ms
t
REFON
REF+
NOTES: 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses
two capacitors between pins V
and AV and V
/V
and AV : 10 μF tantalum and 100 nF ceramic.
REF+
SS
REF− eREF−
SS
2. The condition is that the error in a conversion started after t
capacitive load.
is less than ±0.5 LSB. The settling time depends on the external
REFON
C
VREF+
100 μF
t
≈ .66 x C
[ms] with C
in μF
REFON
VREF+
VREF+
10 μF
1 μF
0
10 ms
1 ms
100 ms
t
REFON
Figure 18. Typical Settling Time of Internal Reference t
vs External Capacitor on V
+
REF
REFON
48
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
/DV
DV
DV
From
Power
Supply
CC2
CC1
+
−
/DV
SS1
SS2
10 μF 100 nF
AV
CC
SS
+
−
MSP430F43x
MSP430F44x
AV
10 μF 100 nF
Apply External Reference [V
or Use Internal Reference [V
]
eREF+
V
REF+
or V
eREF+
]
REF+
+
−
10 μF 100 nF
Apply
V
REF
−/V
eREF−
External
Reference
+
−
10 μF 100 nF
Figure 19. Supply Voltage and Reference Voltage Design V
V
External Supply
REF−/ eREF−
/DV
DV
From
Power
Supply
CC2
CC1
+
−
/DV
DV
SS1
SS2
10 μF 100 nF
AV
AV
CC
SS
+
−
MSP430F43x
MSP430F44x
10 μF 100 nF
Apply External Reference [V
or Use Internal Reference [V
]
eREF+
V
REF+
or V
eREF+
]
REF+
+
−
10 μF 100 nF
Reference Is Internally
Switched to AV
V
/V
REF− eREF−
SS
Figure 20. Supply Voltage and Reference Voltage Design V
V
= AV , Internally Connected
REF−/ eREF− SS
49
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, timing parameters
PARAMETER
TEST CONDITIONS
V
CC
MIN
NOM
MAX
UNIT
For specified performance of ADC12
linearity parameters
2.2V/
3 V
f
f
0.45
5
6.3
MHz
ADC12CLK
Internal ADC12
oscillator
ADC12DIV=0,
2.2 V/
3 V
3.7
6.3
MHz
μs
ADC12OSC
f
=f
ADC12CLK ADC12OSC
C
≥ 5 μF, Internal oscillator,
2.2 V/
3 V
VREF+
2.06
3.51
f
= 3.7 MHz to 6.3 MHz
ADC12OSC
t
Conversion time
CONVERT
External f
from ACLK, MCLK or SMCLK:
13×ADC12DIV×
ADC12CLK
μs
ADC12SSEL ≠ 0
1/f
ADC12CLK
Turn on settling time of
the ADC
t
t
(see Note 1)
100
ns
ADC12ON
R = 400 Ω, R = 1000 Ω,
3 V
1220
1400
S
I
Sampling time
ns
C = 30 pF
Sample
I
2.2 V
τ = [R + R ] x C (see Note 2)
S
I
I;
NOTES: 1. The condition is that the error in a conversion started after t
settled.
is less than ±0.5 LSB. The reference and input signal are already
ADC12ON
2. Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
n+1
t
= ln(2 ) x (R + R ) x C + 800 ns where n = ADC resolution = 12, R = external source resistance.
Sample
S
I
I
S
12-bit ADC, linearity parameters
PARAMETER
TEST CONDITIONS
/V ) min ≤ 1.6 V
REF− eREF−
V
MIN NOM MAX
UNIT
CC
1.4 V ≤ (V
− V
− V
±2
eREF+
E
E
Integral linearity error
2.2 V/3 V
2.2 V/3 V
LSB
I
1.6 V < (V
/V
) min ≤ [V
]
±1.7
eREF+
REF− eREF−
(AVCC)
Differential linearity
error
(V
C
− V
/V
)
≤ (V
− V /V
),
),
eREF+
VREF+
REF− eREF− min
eREF+
REF− eREF−
±1
LSB
LSB
D
= 10 μF (tantalum) and 100 nF (ceramic)
− V /V ≤ (V − V /V
REF− eREF−
(V
eREF+
)
REF− eREF− min
eREF+
E
O
Internal impedance of source R < 100 Ω,
2.2 V/3 V
±2
±4
Offset error
Gain error
S
C
= 10 μF (tantalum) and 100 nF (ceramic)
VREF+
(V
C
− V
/V
)
≤ (V
− V /V
),
),
eREF+
VREF+
REF− eREF− min
eREF+
REF− eREF−
E
E
2.2 V/3 V
2.2 V/3 V
±1.1
±2
±2
±5
LSB
LSB
G
= 10 μF (tantalum) and 100 nF (ceramic)
− V /V ≤ (V − V /V
REF− eREF−
(V
C
)
Total unadjusted
error
eREF+
REF− eREF− min
eREF+
T
= 10 μF (tantalum) and 100 nF (ceramic)
VREF+
50
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, temperature sensor and built-in V
MID
PARAMETER
TEST CONDITIONS
V
MIN NOM
MAX
120
UNIT
CC
2.2 V
3 V
40
60
Operating supply current into
REFON = 0, INCH = 0Ah,
I
μA
SENSOR
AV terminal (see Note 1)
ADC12ON=NA, T = 25_C
CC
A
160
2.2 V
3 V
986
986±5%
986±5%
3.55±3%
3.55±3%
ADC12ON = 1, INCH = 0Ah,
T = 0°C
V
mV
mV/°C
μs
SENSOR
A
986
2.2 V
3 V
3.55
3.55
30
TC
t
ADC12ON = 1, INCH = 0Ah
SENSOR
2.2 V
3 V
Sample time required if channel
10 is selected (see Note 2)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
SENSOR(sample)
VMID
30
2.2 V
3 V
NA
NA
ADC12ON = 1, INCH = 0Bh,
(see Note 3)
I
Current into divider at channel 11
μA
2.2 V
3 V
1.1
1.1±0.04
ADC12ON = 1, INCH = 0Bh,
V
MID
AV divider at channel 11
V
CC
V
MID
is ~0.5 x V
AVCC
1.5 1.50±0.04
2.2 V
3 V
1400
1220
Sample time required if channel
11 is selected (see Note 4)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
t
ns
VMID(sample)
NOTES: 1. The sensor current I
is consumed if (ADC12ON = 1 and REFON=1), or (ADC12ON=1 AND INCH=0Ah and sample signal
SENSOR
is high). Therefore it includes the constant current through the sensor and the reference.
2. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t
.
SENSOR(on)
3. No additional current is needed. The V
is used during sampling.
MID
4. The on-time t
is included in the sampling time t ; no additional on time is needed.
VMID(sample)
VMID(on)
51
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Flash Memory
TEST
CONDITIONS
PARAMETER
V
CC
MIN NOM
MAX
UNIT
V
CC(PGM/
ERASE)
Program and Erase supply voltage
Flash Timing Generator frequency
2.7
3.6
V
f
I
I
t
t
257
476
5
kHz
mA
FTG
Supply current from DV during program
2.7 V/ 3.6 V
2.7 V/ 3.6 V
2.7 V/ 3.6 V
2.7 V/ 3.6 V
3
PGM
CC
Supply current from DV during erase
3
7
mA
ERASE
CPT
CC
Cumulative program time
Cumulative mass erase time
Program/Erase endurance
Data retention duration
see Note 1
see Note 2
10
ms
200
ms
CMErase
4
5
10
100
10
cycles
years
t
T = 25°C
J
Retention
t
t
t
t
t
t
Word or byte program time
35
30
Word
st
Block program time for 1 byte or word
Block, 0
Block program time for each additional byte or word
Block program end-sequence wait time
Mass erase time
21
Block, 1-63
Block, End
Mass Erase
Seg Erase
see Note 3
t
FTG
6
5297
4819
Segment erase time
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/f
,max = 5297x1/476kHz). To
FTG
achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller’s state machine (t
= 1/f ).
FTG
FTG
JTAG Interface
TEST
CONDITIONS
PARAMETER
V
CC
MIN NOM
MAX
UNIT
2.2 V
3 V
0
0
5
10
90
MHz
MHz
kΩ
f
TCK input frequency
see Note 1
TCK
R
Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2
may be restricted to meet the timing requirements of the module selected.
2.2 V/ 3 V
25
60
Internal
NOTES: 1. f
TCK
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG Fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
V
CC
MIN NOM
MAX
UNIT
V
V
Supply voltage during fuse-blow condition
Voltage level on TDI/TCLK for fuse-blow: F versions
Supply current into TDI/TCLK during fuse blow
Time to blow fuse
T = 25°C
A
2.5
6
V
V
CC(FB)
7
100
1
FB
I
FB
t
FB
mA
ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
52
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
APPLICATION INFORMATION
input/output schematic
Port P1, P1.0 to P1.5, input/output with Schmitt-trigger
Pad Logic
CAPD.x
P1SEL.x
0: Input
1: Output
0
P1DIR.x
Direction Control
1
0
1
From Module
P1.x
P1OUT.x
Module X OUT
Bus
Keeper
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1IN.x
EN
D
Module X IN
P1IRQ.x
P1IE.x
EN
Interrupt
Edge
Select
Q
P1IFG.x
Set
P1IES.x P1SEL.x
Note: 0 < x< 5
Note: Port function is active if CAPD.x = 0
Direction
Control
From Module
Module X
OUT
PnOUT.x
PnIE.x
PnIES.x
PnIN.x
Module X IN
PnSel.x
PnDIR.x
PnIFG.x
†
†
P1Sel.0
P1Sel.1
P1Sel.2
P1OUT.0
P1DIR.0
P1DIR.1
P1DIR.2
P1DIR.0
P1DIR.1
P1DIR.2
P1DIR.3
P1DIR.4
P1DIR.5
Out0 sig.
MCLK
P1IN.0
P1IN.1
P1IN.2
P1IN.3
P1IN.4
P1IN.5
CCI0A
P1IE.0
P1IE.1
P1IE.2
P1IE.3
P1IE.4
P1IE.5
P1IFG.0
P1IFG.1
P1IFG.2
P1IFG.3
P1IFG.4
P1IFG.5
P1IES.0
P1IES.1
P1IES.2
P1IES.3
P1IES.4
P1IES.5
†
CCI0B
P1OUT.1
P1OUT.2
P1OUT.3
P1OUT.4
P1OUT.5
†
†
Out1 sig.
CCI1A
‡
P1Sel.3
P1Sel.4
P1DIR.3
P1DIR.4
SVSOUT
SMCLK
ACLK
TBOUTH
‡
TBCLK
†
P1Sel.5
P1DIR.5
TACLK
†
‡
Timer_A
Timer_B
53
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
APPLICATION INFORMATION
input/output schematic (continued)
Port P1, P1.6, P1.7, input/output with Schmitt-trigger
Pad Logic
Note: Port function is active if CAPD.6 = 0
CAPD.6
P1SEL.6
0: Input
1: Output
0
P1DIR.6
P1.6/
CA0
1
P1DIR.6
0
P1OUT.6
1
DV
SS
Bus
Keeper
P1IN.6
EN
D
unused
P1IE.7
P1IFG.7
P1IRQ.07
EN
Set
Interrupt
Edge
Select
Q
P1IES.x
P1SEL.x
Comparator_A
CAF
P2CA
AVcc
CAREF
CAEX
CA0
CA1
+
CCI1B
to Timer_Ax
−
2
Reference Block
CAREF
Pad Logic
Note: Port function is active if CAPD.7 = 0
CAPD.7
P1SEL.7
P1DIR.7
P1DIR.7
P1OUT.7
0: input
1: output
0
1
P1.7/
CA1
0
1
DV
SS
Bus
keeper
P1IN.7
EN
D
unused
P1IE.7
EN
P1IRQ.07
Interrupt
Edge
Select
Q
P1IFG.7
Set
P1IES.7
P1SEL.7
54
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.0, P2.4 to P2.5, input/output with Schmitt-trigger
Pad Logic
DVSS
DVSS
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
1
0
1
P2OUT.x
Module X OUT
Bus
Keeper
P2.0/TA2
P2.4/UTXD0
P2IN.x
P2.5/URXD0
EN
D
Module X IN
P2IRQ.x
P2IE.x
P2IFG.x
EN
Set
Interrupt
Edge
Select
Q
P2IES.x
P2SEL.x
Note: x {0,4,5}
Dir. Control
from module
Module X
OUT
PnSel.x
PnDIR.x
PnOUT.x
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
†
†
P2Sel.0
P2Sel.4
P2DIR.0
P2DIR.4
P2DIR.5
P2DIR.0
P2OUT.0
P2OUT.4
P2OUT.5
Out2 sig.
P2IN.0
P2IN.4
CCI2A
P2IE.0
P2IE.4
P2IE.5
P2IFG.0
P2IFG.4
P2IES.0
P2IES.4
‡
UTXD0
unused
URXD0
DV
CC
SS
‡
DV
SS
P2Sel.5
P2IN.5
P2IES.5
DV
P2IFG.5
†
‡
Timer_A
USART0
55
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.1 to P2.3, input/output with Schmitt-trigger
Pad Logic
DVSS
DVSS
Module IN of pin
P1.3/TBOUTH/SVSOUT
P1DIR.3
P1SEL.3
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
1
0
1
P2OUT.x
Module X OUT
Bus
Keeper
P2.1/TB0
P2.2/TB1
P2IN.x
P2.3/TB2
EN
D
Module X IN
P2IRQ.x
P2IE.x
P2IFG.x
EN
Set
Interrupt
Edge
Select
Q
P2IES.x
P2SEL.x
Note: 1 < x < 3
Dir. Control
from module
Module X
OUT
PnSel.x
PnDIR.x
PnOUT.x
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
CCI0A
CCI0B
†
†
†
†
P2Sel.1
P2Sel.2
P2DIR.1
P2DIR.2
P2DIR.3
P2DIR.1
P2DIR.2
P2DIR.3
P2OUT.1
P2OUT.2
P2OUT.3
Out0 sig.
Out1 sig.
Out2 sig.
P2IN.1
P2IN.2
P2IN.3
P2IE.1
P2IE.2
P2IE.3
P2IFG.1
P2IFG.2
P2IFG.3
P2IES.1
P2IES.2
P2IES.3
CCI1A
CCI1B
†
†
CCI2A
CCI2B
P2Sel.3
Timer_B
†
56
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.6 to P2.7, input/output with Schmitt-trigger
0: Port active
1: Segment xx function active
Pad Logic
‡
Port/LCD
‡
Segment xx
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
1
0
1
P2OUT.x
Module X OUT
Bus
Keeper
‡
P2.6/CAOUT/S19
‡
P2.7/ADC12CLK/S18
P2IN.x
‡
Segment function
only available with
MSP430x43x(1)IPN
EN
D
Module X IN
P2IRQ.x
P2IE.x
EN
Set
Interrupt
Edge
Select
Q
P2IFG.x
P2IES.x
P2SEL.x
Note: 6 < x < 7
Dir. Control
from module
Module X
OUT
‡
PnSel.x
PnDIR.x
PnOUT.x
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
Port/LCD
‡
‡
†
P2IES.6
P2IES.7
P2Sel.6
P2Sel.7
P2DIR.6
P2DIR.7
P2DIR.6
P2DIR.7
P2OUT.6
CAOUT
P2IN.6
P2IN.7
unused
unused
0: LCDM<40h
0: LCDM<40h
P2IE.6
P2IE.7
P2IFG.6
P2IFG.7
§
P2OUT.7 ADC12CLK
†
‡
§
Comparator_A
Port/LCD signal is 1 only with MSP430xIPN and LCDM ≥40h.
ADC12
57
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.0 to P3.3, input/output with Schmitt-trigger
MSP430x43x(1)IPN (80-Pin) Only
LCDM.5
0: Port active
LCDM.6
1: Segment xx function active
LCDM.7
Pad Logic
x43xIPZ and x44xIPZ have no segment
function on Port P3: Both lines are low.
Segment xx
P3SEL.x
0: Input
1: Output
0
P3DIR.x
Direction Control
1
From Module
0
1
P3OUT.x
Module X OUT
Bus
Keeper
†
P3.0/STEO/S31
†
P3.1/SIMO0/S30
†
P3.2/SOMI0/S29
P3IN.x
†
P3.3/UCLK0/S28
EN
D
Module X IN
Note: 0 ≤ x ≤ 3
Direction
Control
Module X
OUT
PnSel.x
PnDIR.x
PnOUT.x
PnIN.x
Module X IN
From Module
P3Sel.0
P3Sel.1
P3Sel.2
P3Sel.3
P3DIR.0
P3DIR.1
P3DIR.2
P3DIR.3
P3OUT.0
P3IN.0
STE0(in)
DV
SS
DV
SS
DCM_SIMO0 P3OUT.1
DCM_SOMI0 P3OUT.2
DCM_UCLK0 P3OUT.3
SIMO0(out) P3IN.1
SOMIO(out) P3IN.2
UCLK0(out) P3IN.3
SIMO0(in)
SOMI0(in)
UCLK0(in)
†
S24 to S31 shared with port function only at MSP430x43x(1)IPN (80-pin QFP)
Direction Control for SIMO0 and UCLK0
Direction Control for SOMI0
DCM_SOMI0
SYNC
MM
SYNC
DCM_SIMO0
DCM_UCLK0
MM
STC
STE
STC
STE
58
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.4 to P3.7, input/output with Schmitt-trigger
0: Port active
1: Segment xx function active
Pad Logic
†
‡
‡
LCDM.7 or DVSS
†
Segmentxx or DVSS
#
§
TBOUTHiZ or DVSS
P3SEL.x
P3DIR.x
Direction Control
From Module
0: Input
1: Output
0
1
0
1
P3OUT.x
Module XOUT
Bus
Keeper
’x43x(1)IPN ’x43xIPZ
’x44x
80-Pin
100-Pin
P3IN.x
P3.4/S27
P3.5/S26
P3.6/S25
P3.7/S24
P3.4
P3.5
P3.6
P3.7
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
EN
D
Module X IN
Note: 4 < x < 7
Module IN of pin
P1.3/TBOUTH/SVSOUT
P1DIR.3
P1SEL.3
P3DIR.x
P3SEL.x
TBOUTHiZ
Dir. Control
from module
Module X
OUT
PnSel.x
PnDIR.x
PnOUT.x
PnIN.x
Module X IN
§
#
§
#
unused
CCI3A/B
unused
DVSS
OUT3
P3Sel.4
P3DIR.4
P3DIR.5
P3DIR.6
P3DIR.7
P3OUT.4
P3OUT.5
P3OUT.6
P3OUT.7
P3IN.4
P3IN.5
P3IN.6
P3IN.7
P3DIR.4
P3DIR.5
P3DIR.6
P3DIR.7
§
#
§
#
DVSS
OUT4
P3Sel.5
P3Sel.6
CCI4A/B
unused §
§
#
DVSS
OUT5
#
CCI5A/B
§
#
§
#
unused
CCI6A
DVSS
OUT6
P3Sel.7
†
MSP430x43x(1)IPN
MSP430x43xIPZ, MSP430x44xIPZ
MSP430x43x(1)
‡
§
#
MSP430x44x
59
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
APPLICATION INFORMATION
input/output schematic (continued)
port P4, P4.0 to P4.7, input/output with Schmitt-trigger
0: Port active
1: Segment xx function active
Pad Logic
§
Port/LCD
Segment xx
P4SEL.x
0: Input
1: Output
0
P4DIR.x
Direction Control
1
From Module
0
1
P4OUT.x
Module X OUT
Bus
Keeper
x43x(1)IPN x43xIPZ
80-Pin
QFP:
100-Pin
QFP:
x44x
P4IN.x
P4.7/S2
P4.6/S3
P4.5/S4
P4.3/S6
P4.4/S5
P4.2/S7
P4.1/S8
P4.0/S9
P4.7/S34 P4.7/S34
P4.6/S35 P4.6/S35
P4.5/S36 P4.5/UCLK1/S36
P4.3/S37 P4.4/SMO1/S37
P4.4/S38 P4.3/SIMO1/S38
P4.2/S39 P4.2/STE1/S39
EN
D
Module X IN
Note: 0 < x < 7
P4.0
P4.1
P4.1/URXD1
P4.0/UTXD1
Direction
Module X
OUT
Control
From Module
PnSel.x
PnDIR.x
PnOUT.x
PnIN.x Module X IN
†
DV
†
P4DIR.0
SS
P4Sel.0
P4Sel.1
P4DIR.0
P4DIR.1
P4OUT.0
P4OUT.1
P4IN.0
P4IN.1
unused
unused†
‡
DV
UTXD1
CC‡
†
P4DIR.1
DV
DV
SS
SS
‡
SS‡
URXD1
unused†
STE1(in)‡
†
P4DIR.2
DV
DV
P4Sel.2
P4Sel.3
P4DIR.2
P4DIR.3
P4OUT.2
P4OUT.3
P4IN.2
P4IN.3
SS‡
unused†
SIMO1(in)‡
†
†
DV
SS
P4DIR3.
DCM_SIMO1
‡
SIMO1(out)
‡
unused
SOMI1(in)‡
†
DV
SOMI1(out)
†
P4DIR4.
SS
P4Sel.4
P4Sel.5
P4DIR.4
P4DIR.5
P4OUT.4
P4OUT.5
P4IN.4
P4IN.5
‡
DCM_SOMI
1‡
unused†
UCLK1(in)‡
†
P4DIR5.
†
DV
SS
DCM_UCLK1
‡
‡
UCLK1(out)
DV
SS
P4Sel.6
P4Sel.7
P4DIR.6
P4DIR.7
P4DIR.6
P4DIR.7
P4OUT.6
P4OUT.7
P4IN.6
P4IN.7
unused
unused
DV
SS
†
Signal at MSP430x43x(1)
Signal at MSP430x44x
‡
DEVICE
PORT BITS
PORT FUNCTION
LCDM < 020h
LCDM < 0E0h
LCDM < 0C0h
LCD SEG. FUNCTION
LCDM ≥ 020h
x43x(1)IPN 80-pin QFP
x43xIPZ 100-pin QFP
x44xIPZ 100-pin QFP
P4.0 . . .P4.7
P4.2 . . .P4.5
P4.6 . . .P4.7
LCDM ≥ 0E0h
LCDM ≥ 0C0h
60
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
APPLICATION INFORMATION
input/output schematic (continued)
port P4, P4.0 to P4.7, input/output with Schmitt-trigger (continued)
Direction Control for SIMO1 and UCLK1
Direction Control for SOMI1
DCM_SOMI1
SYNC
SYNC
MM
STC
STE
DCM_SIMO1
DCM_UCLK1
MM
STC
STE
port P5, P5.0 to P5.1, input/output with Schmitt-trigger
0: Port active
Segment Pad Logic
1: Segment function active
Port/LCD
Segment
Port Pad Logic
P5SEL.x
0
P5DIR.x
0: Input
Direction Control
From Module
1
1: Output
0
1
P5OUT.x
Module X OUT
Bus
Keeper
P5.0/S1
P5.1/S0
P5IN.x
EN
D
Module X IN
Note:
0 < x < 1
Module X
OUT
Dir. Control
from module
PnSel.x
PnDIR.x
PnOUT.x
PnIN.x
Module X IN
Segment
Port/LCD
P5Sel.0
P5Sel.1
P5DIR.0
P5DIR.1
P5DIR.0
P5OUT.0
P5OUT.1
P5IN.0
P5IN.1
unused
unused
DV
SS
S1
S0
0: LCDM<20h
0: LCDM<20h
DV
SS
P5DIR.1
61
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
APPLICATION INFORMATION
input/output schematic (continued)
port P5, P5.2 to P5.4, input/output with Schmitt-trigger
0: Port active
Pad Logic
1: LCD function active
Port/LCD
LCD signal
P5SEL.x
0: Input
1: Output
0
P5DIR.x
Direction Control
From Module
1
0
1
P5OUT.x
Module X OUT
Bus
Keeper
P5.2/COM1
P5.3/COM2
P5.4/COM3
P5IN.x
EN
D
Module X IN
Note: 2 < x < 4
Dir. Control
from module
Module X
OUT
PnSel.x
P5Sel.2
P5Sel.3
P5Sel.4
PnDIR.x
P5DIR.2
P5DIR.3
P5DIR.4
PnOUT.x
P5OUT.2
P5OUT.3
P5OUT.4
PnIN.x
Module X IN
unused
LCD signal
Port/LCD
P5DIR.2
P5DIR.3
P5DIR.4
P5IN.2
P5IN.3
P5IN.4
DV
SS
COM1
COM2
COM3
P5SEL.2
P5SEL.3
P5SEL.4
DV
SS
unused
DV
SS
unused
62
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
APPLICATION INFORMATION
input/output schematic (continued)
port P5, P5.5 to P5.7, input/output with Schmitt-trigger
0: Port active
Pad Logic
1: LCD function active
Port/LCD
LCD signal
P5SEL.x
0: Input
1: Output
0
P5DIR.x
Direction Control
From Module
1
0
1
P5OUT.x
Module X OUT
Bus
Keeper
P5.5/R13
P5.6/R23
P5.7/R33
P5IN.x
EN
D
Module X IN
Note: 5 < x < 7
Dir. Control
from module
Module X
OUT
PnSel.x
P5Sel.5
P5Sel.6
P5Sel.7
PnDIR.x
P5DIR.5
P5DIR.6
P5DIR.7
PnOUT.x
P5OUT.5
P5OUT.6
P5OUT.7
PnIN.x
Module X IN
unused
LCD signal
Port/LCD
P5DIR.5
P5DIR.6
P5DIR.7
DV
SS
P5IN.5
P5IN.6
P5IN.7
R13
R23
R33
P5SEL.5
unused
DV
SS
P5SEL.6
P5SEL.7
unused
DV
SS
63
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
APPLICATION INFORMATION
input/output schematic (continued)
port P6, P6.0 to P6.6, input/output with Schmitt-trigger
P6SEL.x
0
0: Input
P6DIR.x
Direction Control
From Module
1: Output
1
0
1
Pad Logic
P6.0/A0 ..
P6.6/A6
P6OUT.x
Module X OUT
Bus Keeper
P6IN.x
EN
D
Module X IN
From ADC
To ADC
x: Bit Identifier, 0 to 6 for Port P6
NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if
the analog signal is in the range of transitions 0→1 or 1→0. The value of the throughput current depends on the driving capability of the
gate. For MSP430, it is approximately 100 μA.
Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used by the ADC12.
Dir. Control
PnSel.x
PnDIR.x
PnOUT.x
Module X OUT
PnIN.x
Module X IN
From Module
P6DIR.0
P6DIR.1
P6DIR.2
P6DIR.3
P6DIR.4
P6DIR.5
P6DIR.6
P6Sel.0
P6Sel.1
P6Sel.2
P6Sel.3
P6Sel.4
P6Sel.5
P6Sel.6
P6DIR.0
P6DIR.1
P6DIR.2
P6DIR.3
P6DIR.4
P6DIR.5
P6DIR.6
P6OUT.0
P6OUT.1
P6OUT.2
P6OUT.3
P6OUT.4
P6OUT.5
P6OUT.6
DV
DV
DV
DV
DV
DV
DV
P6IN.0
P6IN.1
P6IN.2
P6IN.3
P6IN.4
P6IN.5
P6IN.6
unused
unused
unused
unused
unused
unused
unused
SS
SS
SS
SS
SS
SS
SS
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
64
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
APPLICATION INFORMATION
input/output schematic (continued)
port P6, P6.7, input/output with Schmitt-trigger
P6SEL.x
VLP(SVS)=15
0
0: Input
P6DIR.x
Direction Control
1: Output
Pad Logic
1
From Module
P6.7/A7/SVSIN
0
P6OUT.x
Module X OUT
1
Bus Keeper
P6IN.x
EN
Module X IN
D
Note: Not implemented in the MSP430x43x1 devices
From ADC
To ADC
To Brownout/SVS Module
x: Bit Identifier, 7 for Port P6
NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if
the analog signal is in the range of transitions 0→1 or 1→0. The value of the throughput current depends on the driving capability of the
gate. For MSP430, it is approximately 100 μA.
Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used by the ADC12.
Dir. Control
From Module
PnSel.x
PnDIR.x
PnOUT.x
Module X OUT
DV
PnIN.x
Module X IN
P6Sel.7
P6DIR.7
P6DIR.7
P6OUT.7
P6IN.7
unused
SS
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
The signal at pin P6.7/A7/SVSIN is also connected to the input multiplexer in the module brownout/supply voltage supervisor.
65
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
APPLICATION INFORMATION
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
TDO
Controlled by JTAG
Controlled by JTAG
TDO/TDI
JTAG
Controlled
DV
CC
by JTAG
TDI
Burn and Test
Fuse
TDI/TCLK
CC
Test
and
DV
TMS
TCK
Emulation
Module
TMS
DV
CC
TCK
RST/NMI
Tau ~ 50 ns
Brownout
D
U
S
G
D
U
S
TCK
G
66
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
APPLICATION INFORMATION
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current (I
) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be
(TF)
taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 21). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition). The JTAG pins are terminated internally and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
I
(TF)
I
TDI/TCLK
Figure 21. Fuse Check Mode Current MSP430x43x(1), MSP430x44x
67
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
Data Sheet Revision History
Literature
Number
Summary
Added MSP430F43x1 devices
Updated functional block diagram (page 6)
Clarified test conditions in recommended operating conditions table (page 27)
Clarified test conditions in electrical characteristics table (page 28)
Added Port 2 through Port 5 to leakage current table (page 29)
Corrected y-axis unit on Figures 6 and 7; changed from V to mV (page 34)
Clarified test conditions in USART0/USART1 table (page 40)
SLAS344E
SLAS344F
Changed t
maximum value from 4 ms to 10 ms in Flash memory table (page 46)
CPT
Added MSP430F43x1 devices in PZ (100 pin) package
NOTE: Page and figure numbers refer to the respective document revision.
68
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
16-May-2007
PACKAGING INFORMATION
Orderable Device
MSP430F4351IPN
MSP430F4351IPNR
Status (1)
PREVIEW
PREVIEW
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
LQFP
PN
80
50 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
LQFP
PN
80
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
MSP430F4351IPZ
MSP430F4351IPZR
MSP430F435IPN
PREVIEW
PREVIEW
ACTIVE
LQFP
LQFP
LQFP
PZ
PZ
PN
100
100
80
50
TBD
TBD
Call TI
Call TI
Call TI
Call TI
1000
119 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
MSP430F435IPNR
MSP430F435IPZ
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
LQFP
LQFP
PN
PZ
PZ
PN
PN
80
100
100
80
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
MSP430F435IPZR
MSP430F4361IPN
MSP430F4361IPNR
ACTIVE
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
PREVIEW
PREVIEW
50 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
80
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
MSP430F4361IPZ
MSP430F4361IPZR
MSP430F436IPN
PREVIEW
PREVIEW
ACTIVE
LQFP
LQFP
LQFP
PZ
PZ
PN
100
100
80
50
TBD
TBD
Call TI
Call TI
Call TI
Call TI
1000
119 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
MSP430F436IPNR
MSP430F436IPZ
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
LQFP
LQFP
PN
PZ
PZ
PN
PN
80
100
100
80
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
MSP430F436IPZR
MSP430F4371IPN
MSP430F4371IPNR
ACTIVE
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
PREVIEW
PREVIEW
50 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
80
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
MSP430F4371IPZ
MSP430F4371IPZR
MSP430F437IPN
PREVIEW
PREVIEW
ACTIVE
LQFP
LQFP
LQFP
PZ
PZ
PN
100
100
80
50
TBD
TBD
Call TI
Call TI
Call TI
Call TI
1000
119 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
MSP430F437IPNR
MSP430F437IPZ
MSP430F437IPZR
MSP430F447IPZ
MSP430F447IPZR
MSP430F448IPZ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
PN
PZ
PZ
PZ
PZ
PZ
80
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
100
100
100
100
100
90 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-May-2007
Orderable Device
MSP430F448IPZR
MSP430F449IPZ
MSP430F449IPZR
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
LQFP
PZ
100
100
100
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
LQFP
LQFP
PZ
PZ
90 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
60
M
0,08
41
61
40
0,13 NOM
80
21
1
20
Gage Plane
9,50 TYP
0,25
12,20
SQ
11,80
0,05 MIN
0°–7°
14,20
SQ
13,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
M
0,08
51
50
76
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
0,25
16,20
SQ
0,05 MIN
0°–7°
15,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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