MSP430F5214 [TI]
具有 128KB 闪存、8KB SRAM、比较器、DMA、UART/SPI/I2C 和 1.8V 双电源 I/O 的 25MHz MCU;
| 型号： | MSP430F5214 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 128KB 闪存、8KB SRAM、比较器、DMA、UART/SPI/I2C 和 1.8V 双电源 I/O 的 25MHz MCU 静态存储器 比较器 闪存 |
| 文件： | 总124页 (文件大小：3977K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
MSP430F522x/MSP430F521x 混合信号微控制器
1 器件概述
1.1 特性
1
• 双电源电压器件
• 统一时钟系统
– 主电源 (AVVC，DVVC)：
– 针对频率稳定的锁相环 (FLL) 控制环路
– 低功耗低频内部时钟源 (VLO)
– 低频修整内部基准源 (REFO)
– 32kHz 手表晶振 (XT1)
– 由外部电源供电：
3.6V 低至 1.8V
– 多达 22 个通用 I/O，最多可支持 4 个外部中
断
– 高达 32MHz 的高频晶振 (XT2)
– 低压接口电源 (DVIO)：
– 由独立的外部电源供电：1.62V 至 1.98V
– 多达 31 个通用 I/O，支持多达 12 个外部中断
– 串行通信
• 具有 5 个捕捉/比较寄存器的 16 位定时器
TA0，Timer_A
• 具有 3 个捕捉/比较寄存器的 16 位定时器
TA1，Timer_A
• 超低功耗
• 具有 3 个捕捉/比较寄存器的 16 位定时器
TA2，Timer_A
• 具有 7 个捕捉/比较影子寄存器的 16 位定时器
TB0，Timer_B
– 激活模式 (AM)：
所有系统时钟激活
在 8MHz，3.0V，闪存程序执行时为 290µA/MHz
（典型值）
在 8MHz，3.0V，RAM 程序执行时为
150µA/MHz（典型值）
• 2 个通用串行通信接口
– USCI_A0 和 USCI_A1 每个都支持：
– 具有自动波特率检测功能的增强型通用异步收
发器 (UART)
– IrDA 编码和解码
– 同步串行外设接口 (SPI)
– USCI_B0 和 USCI_B1 每个都支持：
– I2C
– 待机模式 (LPM3)：
带有晶振的实时时钟 (RTC)，看门狗和电源监视
器可用，完全 RAM 保持，快速唤醒：
2.2V 时为 1.9µA，3.0V 时为 2.1µA（典型值）
低功耗振荡器 (VLO)，通用计数器，看门狗和电
源监视器可用，完全 RAM 保持，快速唤醒：
3.0V 时为 1.4µA（典型值）
– 同步串行外设接口 (SPI)
– 关闭模式 (LPM4)：
• 带内部基准、采样与保持功能的 10 位模数转换器
完全 RAM 保持，电源监视器可用，快速唤醒：
3.0V 时为 1.1µA（典型值）
– 关断模式 (LPM4.5)：
(ADC)
• 比较器
• 硬件乘法器支持 32 位运算
• 串行板上编程，无需外部编程电压
• 3 通道内部直接内存访问 (DMA)
• 具有 RTC 特性的基本计时器
• 器件比较 汇总了可用的系列产品成员
3.0V 时为 0.18µA（典型值）
• 在 3.5µs（典型值）内从待机模式唤醒
• 16 位精简指令集计算机 (RISC) 架构，扩展内存，
高达 25MHz 的系统时钟
• 灵活的电源管理系统
– 内置可编程的低压降稳压器 (LDO)
– 电源电压监控、监视、和临时限电
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLAS718
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
www.ti.com.cn
1.2 应用范围
•
•
模拟和数字传感器系统
数据记录器
•
通用 应用
1.3 说明
TI 的 MSP430™系列超低功耗微控制器种类繁多，各成员器件配备不同的外设集以满足各类应用的 需要。
此架构与多种低功耗模式配合使用，是延长便携式测量应用电池寿命的最优 选择。该器件 具有 一个强大的
16 位 RISC CPU，使用 16 位寄存器以及常数发生器，以便获得最高编码效率。该数控振荡器 (DCO) 可在
3.5µs（典型值）内从低功率模式唤醒至激活模式。
MSP430F522x 系列微控制器配有四个 16 位定时器、一个高性能 10 位 ADC、两个通用串行通信接口
(USCI)、一个硬件乘法器、DMA、比较器和具有报警功能的 RTC 模块。
MSP430F521x 系列包括除 ADC 以外的所有 MSP430F522x 系列的外设。
所有器件均具有一个分离式 I/O 电源系统，无需进行外部电平转换即可与其他具有 1.8V 标称值 I/O 接口的
器件无缝连接。
有关完整的模块说明，请参阅《MSP430F5xx 和 MSP430F6xx 系列用户指南》。有关设计指南，请参阅
《使用 MSP430F522x 和 MSP430F521x 器件进行设计》。
器件信息(1)
封装
器件型号
MSP430F5229IRGC
MSP430F5229IZQE
MSP430F5224IRGZ
MSP430F5219IYFF
封装尺寸(2)
9mm x 9mm
5mm x 5mm
7mm x 7mm
请参见 节 8
VQFN (64)
BGA (80)
VQFN (48)
DSBGA (64)
(1) 要获得最新的产品、封装和订购信息，请参见封装选项附录（节 8），或者访问德州仪器 (TI) 网站
www.ti.com.cn。
(2) 此处显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参见机械数据（节 8）。
2
器件概述
版权 © 2012–2018, Texas Instruments Incorporated
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
www.ti.com.cn
1.4 功能方框图
图 1-1 给出了采用 RGC、ZQE 和 YFF 封装的 MSP430F5229 和 MSP430F5227 器件的功能方框图。
DVCC AVCC
DVSS AVSS
PB
PC
PD
PJ
PA
XIN XOUT
DVIO VCORE
RSTDVCC RST/NMI BSLEN
P3.x P4.x P5.x P6.x
P1.x
P2.x
P7.x PJ.x
P3
P4
P5
P6
1×5 I/Os 1×8 I/Os 1×6 I/Os 1×8 I/Os 1×6 I/Os
P7
P1
P1
P2
1×4 I/Os 1×4 I/Os 1×8 I/Os
XT2IN
SYS
USCI0,1
ACLK
Power
Management
Unified
Clock
System
128KB
64KB
8KB
PB
1×13 I/Os
PC
1×14 I/Os
PD PJ
1×6 I/Os 1×4 I/Os
PA
1×16 I/Os
Watchdog
USCI_Ax:
UART,
IrDA, SPI
XT2OUT
SMCLK
I/O Ports
Interrupt and Wakeup
Port Map
Control
(P4)
I/O Ports
LDO
SVM/SVS
Brownout
MCLK
USCI_Bx:
SPI, I2C
Flash
RAM
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S: 3+1)
ADC10_A
TA0
TA1
TA2
TB0
10 Bit
200 KSPS
JTAG,
SBW
Interface
COMP_B
RTC_A
MPY32
CRC16
REF
Timer_A
5 CC
Registers
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
Timer_B
7 CC
Registers
8 Channels
12 Channels
(10 ext,2 int)
I/O are supplied by DVIO
Copyright © 2016, Texas Instruments Incorporated
图 1-1. 功能方框图 – F5229 和 F5227 – RGC、ZQE、YFF 封装
版权 © 2012–2018, Texas Instruments Incorporated
器件概述
3
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
www.ti.com.cn
图 1-2 给出了采用 RGZ 封装的 MSP430F5224 和 MSP430F5222 器件的功能方框图。
DVCC AVCC
DVSS AVSS
PB
PC
PA
DVIO VCORE
PJ
XIN XOUT
RSTDVCC RST/NMI BSLEN
P3.x P4.x P5.x P6.x
P1.x
P2.x
PJ.x
P3
P4
P5
1×5 I/Os 1×7 I/Os 1×6 I/Os 1×6 I/Os
P6
P1
P1
P2
1×4 I/Os 1×4 I/Os 1×1 I/Os
XT2IN
SYS
USCI0,1
ACLK
Power
Management
Unified
Clock
System
128KB
64KB
8KB
PB
1×12 I/Os
PC
1×12 I/Os
PJ
1×4 I/Os
PA
1×9 I/Os
Watchdog
USCI_Ax:
UART,
IrDA, SPI
XT2OUT
SMCLK
I/O Ports
Interrupt and Wakeup
Port Map
Control
(P4)
I/O Ports
LDO
SVM,SVS
Brownout
MCLK
USCI_Bx:
SPI, I2C
Flash
RAM
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S: 3+1)
ADC10_A
TA0
TA1
TA2
TB0
10 Bit
200 KSPS
JTAG,
SBW
Interface
COMP_B
RTC_A
MPY32
CRC16
REF
Timer_A
5 CC
Registers
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
Timer_B
7 CC
Registers
6 Channels
10 Channels
(8 ext, 2 int)
I/O are supplied by DVIO
Copyright © 2016, Texas Instruments Incorporated
图 1-2. 功能方框图 – F5224 和 F5222 – RGZ 封装
图 1-3 显示了采用 RGC、ZQE 和 YFF 封装的 MSP430F5219 和 MSP430F5217 器件的功能方框图。
DVCC AVCC
DVSS AVSS
PB
PC
PD
PJ
PA
DVIO VCORE
XIN XOUT
RSTDVCC RST/NMI BSLEN
P3.x P4.x P5.x P6.x
P1.x
P2.x
P7.x PJ.x
P3
P4
P5
P6
1×5 I/Os 1×8 I/Os 1×6 I/Os 1×8 I/Os 1×6 I/Os
P7
P1
P1
P2
1×4 I/Os 1×4 I/Os 1×8 I/Os
XT2IN
SYS
USCI0,1
ACLK
SMCLK
Power
Management
Unified
Clock
System
128KB
64KB
8KB
PB
1×13 I/Os
PC
1×14 I/Os
PD PJ
1×6 I/Os 1×4 I/Os
PA
1×16 I/Os
Watchdog
USCI_Ax:
UART,
IrDA, SPI
XT2OUT
I/O Ports
Interrupt and Wakeup
Port Map
Control
(P4)
I/O Ports
LDO
SVM/SVS
Brownout
MCLK
USCI_Bx:
SPI, I2C
Flash
RAM
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S: 3+1)
TA0
TA1
TA2
TB0
JTAG,
SBW
Interface
COMP_B
RTC_A
MPY32
CRC16
REF
Timer_A
5 CC
Registers
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
Timer_B
7 CC
Registers
8 Channels
I/O are supplied by DVIO
Copyright © 2016, Texas Instruments Incorporated
图 1-3. 功能方框图 – F5219 和 F5217 – RGC、ZQE、YFF 封装
图 1-4 给出了采用 RGZ 封装的 MSP430F5214 和 MSP430F5212 器件的功能方框图。
4
器件概述
版权 © 2012–2018, Texas Instruments Incorporated
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
www.ti.com.cn
DVCC AVCC
DVSS AVSS
PB
PC
PA
PJ
XIN XOUT
DVIO VCORE
RSTDVCC RST/NMI BSLEN
P3.x P4.x P5.x P6.x
P1.x
P2.x
PJ.x
P3
P4
P5
1×5 I/Os 1×7 I/Os 1×6 I/Os 1×6 I/Os
P6
P1
P1
P2
1×4 I/Os 1×4 I/Os 1×1 I/Os
XT2IN
SYS
USCI0,1
ACLK
Power
Management
Unified
Clock
System
128KB
64KB
8KB
PB
1×12 I/Os
PC
1×12 I/Os
PJ
1×4 I/Os
PA
1×9 I/Os
Watchdog
USCI_Ax:
UART,
IrDA, SPI
XT2OUT
SMCLK
I/O Ports
Interrupt and Wakeup
Port Map
Control
(P4)
I/O Ports
LDO
SVM, SVS
Brownout
MCLK
USCI_Bx:
SPI, I2C
Flash
RAM
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S: 3+1)
TA0
TA1
TA2
TB0
JTAG,
SBW
Interface
COMP_B
RTC_A
MPY32
CRC16
REF
Timer_A
5 CC
Registers
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
Timer_B
7 CC
Registers
6 Channels
I/O are supplied by DVIO
Copyright © 2016, Texas Instruments Incorporated
图 1-4. 功能方框图 – F5214 和 F5212 – RGZ 封装
版权 © 2012–2018, Texas Instruments Incorporated
器件概述
5
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
www.ti.com.cn
内容
5.18 Output Frequency – General-Purpose I/O DVIO
1
器件概述.................................................... 1
1.1 特性 ................................................... 1
1.2 应用范围 .............................................. 2
1.3 说明 ................................................... 2
1.4 功能方框图............................................ 3
修订历史记录............................................... 8
Device Comparison ..................................... 9
3.1 Related Products ..................................... 9
Terminal Configuration and Functions ............ 10
4.1 Pin Diagrams........................................ 10
4.2 Signal Descriptions.................................. 16
Specifications ........................................... 21
5.1 Absolute Maximum Ratings......................... 21
5.2 ESD Ratings ........................................ 21
5.3 Recommended Operating Conditions............... 21
Domain
(P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to
P4.7, P7.0 to P7.5).................................. 30
5.19 Typical Characteristics – Outputs, Reduced Drive
Strength (PxDS.y = 0)............................... 31
5.20 Typical Characteristics – Outputs, Full Drive
Strength (PxDS.y = 1)............................... 32
5.21 Crystal Oscillator, XT1, Low-Frequency Mode...... 33
2
3
5.22 Crystal Oscillator, XT2 .............................. 34
5.23 Internal Very-Low-Power Low-Frequency Oscillator
(VLO) ................................................ 35
5.24 Internal Reference, Low-Frequency Oscillator
(REFO) .............................................. 35
5.25 DCO Frequency..................................... 36
5.26 PMM, Brownout Reset (BOR)....................... 37
5.27 PMM, Core Voltage ................................. 37
5.28 PMM, SVS High Side ............................... 38
5.29 PMM, SVM High Side............................... 39
5.30 PMM, SVS Low Side................................ 39
4
5
5.4
Active Mode Supply Current Into VCC Excluding
External Current..................................... 24
5.5
Low-Power Mode Supply Currents (Into VCC
)
Excluding External Current.......................... 25
5.6 Thermal Resistance Characteristics ................ 26
5.31 PMM, SVM Low Side ............................... 40
5.32 Wake-up Times From Low-Power Modes and
Reset ................................................ 40
5.7
5.8
5.9
Schmitt-Trigger Inputs – General-Purpose I/O
DVCC Domain
(P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to
PJ.3, RSTDVCC) ................................... 27
Schmitt-Trigger Inputs – General-Purpose I/O DVIO
Domain
(P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to
P4.7, P7.0 to P7.5, RST/NMI, BSLEN) ............. 27
Inputs – Interrupts DVCC Domain Port P1
5.33 Timer_A ............................................. 41
5.34 Timer_B ............................................. 41
5.35 USCI (UART Mode), Recommended Operating
Conditions ........................................... 42
5.36 USCI (UART Mode)................................. 42
5.37 USCI (SPI Master Mode), Recommended Operating
Conditions ........................................... 42
(P1.0 to P1.3) ....................................... 27
5.10 Inputs – Interrupts DVIO Domain Ports P1 and P2
(P1.4 to P1.7, P2.0 to P2.7)......................... 27
5.11 Leakage Current – General-Purpose I/O DVCC
Domain
5.38 USCI (SPI Master Mode)............................ 42
5.39 USCI (SPI Slave Mode)............................. 44
5.40 USCI (I2C Mode) .................................... 46
5.41 10-Bit ADC, Power Supply and Input Range
(P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to
Conditions ........................................... 47
PJ.3)................................................. 28
5.42 10-Bit ADC, Timing Parameters .................... 47
5.43 10-Bit ADC, Linearity Parameters................... 48
5.44 REF, External Reference ........................... 48
5.45 REF, Built-In Reference............................. 49
5.46 Comparator_B....................................... 50
5.47 Flash Memory ....................................... 51
5.48 JTAG and Spy-Bi-Wire Interface.................... 51
5.49 DVIO BSL Entry..................................... 52
Detailed Description ................................... 53
6.1 CPU (Link to user's guide) .......................... 53
6.2 Operating Modes.................................... 54
6.3 Interrupt Vector Addresses.......................... 55
6.4 Memory Organization ............................... 56
6.5 Bootloader (BSL).................................... 58
6.6 JTAG Operation ..................................... 59
6.7 Flash Memory (Link to user's guide)................ 60
6.8 RAM (Link to user's guide).......................... 60
6.9 Peripherals .......................................... 61
6.10 Input/Output Diagrams .............................. 82
5.12 Leakage Current – General-Purpose I/O DVIO Domain
(P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to
P4.7, P7.0 to P7.5).................................. 28
5.13 Outputs – General-Purpose I/O DVCC Domain (Full
Drive Strength)
(P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to
PJ.3)................................................. 28
5.14 Outputs – General-Purpose I/O DVCC Domain
(Reduced Drive Strength)
(P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to
6
PJ.3)................................................. 28
5.15 Outputs – General-Purpose I/O DVIO Domain (Full
Drive Strength)
(P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to
P4.7, P7.0 to P7.5).................................. 29
5.16 Outputs – General-Purpose I/O DVIO Domain
(Reduced Drive Strength)
(P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to
P4.7, P7.0 to P7.5).................................. 29
5.17 Output Frequency – General-Purpose I/O DVCC
Domain
(P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to
PJ.3)................................................. 30
6
内容
版权 © 2012–2018, Texas Instruments Incorporated
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
www.ti.com.cn
6.11 Device Descriptors .................................. 99
7.5 相关链接 ........................................... 110
7.6 社区资源 ........................................... 110
7.7 商标 ................................................ 110
7.8 静电放电警告....................................... 110
7.9 Glossary............................................ 110
机械、封装和可订购信息 .............................. 110
7
器件和文档支持......................................... 105
7.1 开始使用 ........................................... 105
7.2 Device Nomenclature.............................. 105
7.3 工具与软件 ......................................... 107
7.4 文档支持 ........................................... 108
8
版权 © 2012–2018, Texas Instruments Incorporated
内容
7
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
www.ti.com.cn
2 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from June 29, 2016 to September 26, 2018
Page
•
•
Added Section 3.1, Related Products ............................................................................................. 9
Removed D and E dimension lines on the YFF pinout (for the package dimesions with tolerances, see the
Mechanical Data in 节 8) ........................................................................................................... 15
Added typical conditions statements at the beginning of Section 5, Specifications ........................................ 21
Changed the MIN value of the V(DVCC_BOR_hys) parameter from 60 mV to 50 mV in Section 5.26, PMM,
Brownout Reset (BOR) ............................................................................................................. 37
Updated notes (1) and (2) and added note (3) in Section 5.32, Wake-up Times From Low-Power Modes and
Reset.................................................................................................................................. 40
Removed ADC10DIV from the formula for the TYP value in the second row of the tCONVERT parameter in
•
•
•
•
•
Section 5.42, 10-Bit ADC, Timing Parameters (removed because ADC10CLK is after division)......................... 47
Added second row for tEN_CMP with Test Conditions of "CBPWRMD = 10" and MAX value of 100 μs in
Section 5.46, Comparator_B....................................................................................................... 50
Renamed FCTL4.MGR0 and MGR1 in Section 5.47, Flash Memory, to be consistent with header files ............... 51
Throughout document, changed all instances of "bootstrap loader" to "bootloader"....................................... 58
将先前的开发工具支持 部分替换成了节 7.3，工具与软件.................................................................... 107
在节 7.4文档支持 中添加了内容.................................................................................................. 108
•
•
•
•
8
修订历史记录
Copyright © 2012–2018, Texas Instruments Incorporated
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Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217
MSP430F5214 MSP430F5212
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
www.ti.com.cn
3 Device Comparison
Table 3-1 summarizes the available family members.
Table 3-1. Family Members(1)(2)
USCI
CHANNEL A:
UART, IrDA,
SPI
FLASH
(KB)
SRAM
(KB)
ADC10_A Comp_B
I/O
I/O
DEVICE
Timer_A(3) Timer_B(4)
PACKAGE
DVCC(5) DVIO(6)
CHANNEL B:
SPI, I2C
(Ch)
(Ch)
64 RGC
64 YFF
80 ZQE
10 ext,
2 int
MSP430F5229
MSP430F5227
128
64
8
8
5, 3, 3
5, 3, 3
7
7
2
2
2
2
8
8
22
22
31
31
64 RGC
64 YFF
80 ZQE
10 ext,
2 int
MSP430F5224
MSP430F5222
128
64
8
8
5, 3, 3
5, 3, 3
7
7
2
2
2
2
8 ext, 2 int
8 ext, 2 int
6
6
20
20
17
17
48 RGZ
48 RGZ
64 RGC
64 YFF
80 ZQE
MSP430F5219
MSP430F5217
128
64
8
8
5, 3, 3
5, 3, 3
7
7
2
2
2
2
-
-
8
8
22
22
31
31
64 RGC
64 YFF
80 ZQE
MSP430F5214
MSP430F5212
128
64
8
8
5, 3, 3
5, 3, 3
7
7
2
2
2
2
-
-
6
6
20
20
17
17
48 RGZ
48 RGZ
(1) For the most current device, package, and ordering information, see the Package Option Addendum in 节 8, or see the TI website at
www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(5) All of these I/Os reside on a single voltage rail supplied by DVCC.
(6) All of these I/Os reside on a single voltage rail supplied by DVIO.
3.1 Related Products
For information about other devices in this family of products or related products, see the following links.
Products for TI Microcontrollers TI's low-power and high-performance MCUs, with wired and wireless
connectivity options, are optimized for a broad range of applications.
Products for MSP430 Ultra-Low-Power Microcontrollers One platform. One ecosystem. Endless
possibilities. Enabling the connected world with innovations in ultra-low-power
microcontrollers with advanced peripherals for precise sensing and measurement.
Companion Products for MSP430F5229 Review products that are frequently purchased or used with
this product.
Reference Designs for MSP430F5229 Find reference designs that leverage the best in TI technology to
solve your system-level challenges.
Copyright © 2012–2018, Texas Instruments Incorporated
Device Comparison
9
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Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217
MSP430F5214 MSP430F5212
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
www.ti.com.cn
4 Terminal Configuration and Functions
4.1 Pin Diagrams
Figure 4-1 shows the pinout for the MSP430F5229 and MSP430F5227 devices in the 64-pin RGC
package.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P6.0/A0/CB0
P6.1/A1/CB1
P6.2/A2/CB2
P6.3/A3/CB3
P6.4/A4/CB4
P6.5/A5/CB5
P6.6/A6/CB6
P6.7/A7/CB7
P5.0/A8/VeREF+
P5.1/A9/VeREF-
AVCC
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P4.7/PM_NONE
P4.6/PM_NONE
3
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P4.4/PM_UCA1TXD/PM_UCA1SIMO
P4.3/PM_UCB1CLK/PM_UCA1STE
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P4.0/PM_UCB1STE/PM_UCA1CLK
DVIO
4
5
6
7
8
MSP430F5229IRGC
MSP430F5227IRGC
9
10
11
12
13
14
15
16
DVSS
P3.4/UCA0RXD/UCA0SOMI
P3.3/UCA0TXD/UCA0SIMO
P3.2/UCB0CLK/UCA0STE
P3.1/UCB0SOMI/UCB0SCL
P3.0/UCB0SIMO/UCB0SDA
P2.7/UCB0STE/UCA0CLK
P5.4/XIN
P5.5/XOUT
AVSS
DVCC
DVSS
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Supplied by DVIO
NOTE: TI recommends connection of exposed thermal pad to VSS
.
Figure 4-1. 64-Pin RGC Package – F5229, F5227
10
Terminal Configuration and Functions
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Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217
MSP430F5214 MSP430F5212
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
www.ti.com.cn
Figure 4-2 shows the pinout for the MSP430F5224 and MSP430F5222 devices in the 48-pin RGZ
package.
48 47 46 45 44 43 42 41 40 39 38 37
P6.3/A3/CB3
P6.4/A4/CB4
P6.5/A5/CB5
P5.0/A8/VeREF+
P5.1/A9/VeREF-
AVCC
1
2
36
35
34
33
32
31
30
29
28
27
26
25
BSLEN
P4.6/PM_NONE
3
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P4.4/PM_UCA1TXD/PM_UCA1SIMO
P4.3/PM_UCB1CLK/PM_UCA1STE
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P4.0/PM_UCB1STE/PM_UCA1CLK
DVIO
4
5
6
MSP430F5224IRGZ
MSP430F5222IRGZ
P5.4/XIN
7
P5.5/XOUT
AVSS
8
9
DVCC
10
11
12
DVSS
DVSS
P3.4/UCA0RXD/UCA0SOMI
P3.3/UCA0TXD/UCA0SIMO
VCORE
13 14 15 16 17 18 19 20 21 22 23 24
Supplied by DVIO
NOTE: TI recommends connection of exposed thermal pad to VSS
.
Figure 4-2. 48-Pin RGZ Package – F5224, F5222
Copyright © 2012–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
11
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Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217
MSP430F5214 MSP430F5212
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
www.ti.com.cn
Figure 4-3 shows the pinout for the MSP430F5219 and MSP430F5217 devices in the 64-pin RGC
package.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P6.0/CB0
P6.1/CB1
P6.2/CB2
P6.3/CB3
P6.4/CB4
P6.5/CB5
P6.6/CB6
P6.7/CB7
P5.0
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P4.7/PM_NONE
P4.6/PM_NONE
3
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P4.4/PM_UCA1TXD/PM_UCA1SIMO
P4.3/PM_UCB1CLK/PM_UCA1STE
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P4.0/PM_UCB1STE/PM_UCA1CLK
DVIO
4
5
6
7
8
MSP430F5219IRGC
MSP430F5217IRGC
9
P5.1
10
11
12
13
14
15
16
DVSS
AVCC
P3.4/UCA0RXD/UCA0SOMI
P3.3/UCA0TXD/UCA0SIMO
P3.2/UCB0CLK/UCA0STE
P3.1/UCB0SOMI/UCB0SCL
P3.0/UCB0SIMO/UCB0SDA
P2.7/UCB0STE/UCA0CLK
P5.4/XIN
P5.5/XOUT
AVSS
DVCC
DVSS
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Supplied by DVIO
NOTE: TI recommends connection of exposed thermal pad to VSS
.
Figure 4-3. 64-Pin RGC Package – F5219, F5217
12
Terminal Configuration and Functions
Copyright © 2012–2018, Texas Instruments Incorporated
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Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217
MSP430F5214 MSP430F5212
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
www.ti.com.cn
Figure 4-4 shows the pinout for the MSP430F5214 and MSP430F5212 devices in the 48-pin RGZ
package.
48 47 46 45 44 43 42 41 40 39 38 37
P6.3/CB3
P6.4/CB4
P6.5/CB5
P5.0
1
2
36
35
34
33
32
31
30
29
28
27
26
25
BSLEN
P4.6/PM_NONE
3
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P4.4/PM_UCA1TXD/PM_UCA1SIMO
P4.3/PM_UCB1CLK/PM_UCA1STE
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P4.0/PM_UCB1STE/PM_UCA1CLK
DVIO
4
P5.1
5
AVCC
6
MSP430F5214IRGZ
MSP430F5212IRGZ
P5.4/XIN
P5.5/XOUT
AVSS
7
8
9
DVCC
10
11
12
DVSS
DVSS
P3.4/UCA0RXD/UCA0SOMI
P3.3/UCA0TXD/UCA0SIMO
VCORE
13 14 15 16 17 18 19 20 21 22 23 24
Supplied by DVIO
NOTE: TI recommends connection of exposed thermal pad to VSS
.
Figure 4-4. 48-Pin RGZ Package – F5214, F5212
Copyright © 2012–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
13
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Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217
MSP430F5214 MSP430F5212
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
www.ti.com.cn
Figure 4-5 shows the pinout for the MSP430F5229, MSP430F5227, MSP430F5219, and MSP430F5217
devices in the 80-pin ZQE package.
TEST RST/NMI P7.5
P7.4
A7
P7.3
A8
P7.1
A9
P6.0 RSTDVCC PJ.2
A1
A2
A3
A4
A5
A6
P6.2
B1
P6.1
B2
PJ.3
B3
P5.3
B4
P5.2 BSLEN P7.2
P7.0
B5
B6
C6
D6
E6
F6
B7
B8
B9
P6.4
C1
P6.3
C2
PJ.1
C4
PJ.0
C5
P4.7
C7
P4.6
C8
P4.5
C9
P6.6
D1
P6.5
D2
P4.4
D7
P4.3
D8
P4.2
D9
P6.7
D3
D4
E4
F4
D5
E5
F5
DVIO
E9
P4.0
E8
P4.1
E7
P5.0
E1
P5.1
E2
E3
F3
G3
P5.4 AVCC
DVSS
F9
F1
F2
F7
F8
P5.5 AVSS
P1.3
G4
P1.6
G5
P2.1
G6
P3.4
G7
P3.2
G8
P3.3
G9
G1
G2
DVCC P1.0
P1.1
H3
P1.4
H4
P1.7
H5
P2.3
H6
P2.7
H7
P3.0
H8
P3.1
H9
H1
H2
DVSS
J1
VCORE P1.2
P1.5
J4
P2.0
J5
P2.2
J6
P2.4
J7
P2.5
J8
P2.6
J9
J2
J3
Supplied by DVIO
Figure 4-5. 80-Pin ZQE Package – F5229, F5227, F5219, F5217
14
Terminal Configuration and Functions
Copyright © 2012–2018, Texas Instruments Incorporated
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Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217
MSP430F5214 MSP430F5212
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
www.ti.com.cn
Figure 4-6 shows the pinout for the MSP430F5229, MSP430F5227, MSP430F5219, and MSP430F5217
devices in the 64-pin YFF package.
Top View
Ball-Side View
H8
H7
H6
H5
H4
H3
H2
H1
H1
H2
H3
H4
H5
H6
H7
H8
P3.0
P3.3 DVSS DVIO P4.1
P4.4
P4.6
P7.0
P7.0
P4.6
P4.4
P4.1 DVIO DVSS P3.3
P3.0
G8
G7
G6
G5
G4
G3
G2
G1
G1
G2
G3
G4
G5
G6
G7
G8
P2.6
P3.1
P3.2
P3.4
P4.3
P4.7
P7.1
P7.3
P7.3
P7.1
P4.7
P4.3
P3.4
P3.2
P3.1
P2.6
F8
F7
F6
F5
F4
F3
F2
F1
F1
F2
F3
F4
F5
F6
F7
F8
P2.3
P2.5
P2.7
P4.0
P4.5
P7.2
P7.4
P7.5
P7.5
P7.4
P7.2
P4.5
P4.0
P2.7
P2.5
P2.3
E8
E7
E6
E5
E4
E3
E2
E1
E1
E2
E3
E4
E5
E6
E7
E8
P2.0
P2.2
P2.4
P4.2 TEST RST/NMI BSLEN P5.2
P5.2 BSLEN RST/NMI TEST P4.2
P2.4
P2.2
P2.0
D8
D7
D6
D5
D4
D3
D2
D1
D1
D2
D3
D4
D5
D6
D7
D8
P1.5
P1.6
P1.7
P2.1 RSTDVCC PJ.2
PJ.0
P5.3
P5.3
PJ.0
PJ.2 RSTDVCC P2.1 P1.7
P1.6
P1.5
C8
C7
C6
C5
C4
C3
C2
C1
C1
C2
C3
C4
C5
C6
C7
C8
P1.2
P1.1
P1.3
P1.4
P6.6
P6.3
P6.0
PJ.1
PJ.1
P6.0
P6.3
P6.6
P1.4
P1.3
P1.1
P1.2
B8
B7
B6
B5
B4
B3
B2
B1
B1
B2
B3
B4
B5
B6
B7
B8
VCORE P1.0 AVSS AVCC P5.0
P6.5
P6.2
PJ.3
PJ.3
P6.2
P6.5
P5.0 AVCC AVSS P1.0 VCORE
A8
A7
A6
A5
A4
A3
A2
A1
A1
A2
A3
A4
A5
A6
A7
A8
DVSS DVCC P5.5
P5.4
P5.1
P6.7
P6.4
P6.1
P6.1
P6.4
P6.7
P5.1
P5.4
P5.5 DVCC DVSS
Supplied by DVIO
Figure 4-6. 64-Pin YFF Package – F5229, F5227, F5219, F5217
Copyright © 2012–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
15
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Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217
MSP430F5214 MSP430F5212
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
www.ti.com.cn
4.2 Signal Descriptions
Table 4-1 describes the signals for all device variants and package options.
Table 4-1. Terminal Functions
TERMINAL
NO.
I/O(1) SUPPLY
DESCRIPTION
NAME
RGC ZQE YFF RGZ
General-purpose digital I/O
Comparator_B input CB0
P6.0/CB0/A0
1
2
3
4
5
6
7
8
A1
B2
B1
C2
C1
D2
D1
D3
C2
A1
B2
C3
A2
B3
C4
A3
46
47
48
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
Analog input A0 for ADC (not available on all device types)
General-purpose digital I/O
P6.1/CB1/A1
P6.2/CB2/A2
P6.3/CB3/A3
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6
P6.7/CB7/A7
Comparator_B input CB1
Analog input A1 for ADC (not available on all device types)
General-purpose digital I/O
Comparator_B input CB2
Analog input A2 for ADC (not available on all device types)
General-purpose digital I/O
Comparator_B input CB3
Analog input A3 for ADC (not available on all device types)
General-purpose digital I/O
2
Comparator_B input CB4
Analog input A4 for ADC (not available on all device types)
General-purpose digital I/O
3
Comparator_B input CB5
Analog input A5 for ADC (not available on all device types)
General-purpose digital I/O (not available on all device types)
N/A
N/A
Comparator_B input CB6 (not available on all device types)
Analog input A6 for ADC (not available on all device types)
General-purpose digital I/O (not available on all device types)
Comparator_B input CB7 (not available on all device types)
Analog input A7 for ADC (not available on all device types)
General-purpose digital I/O
Analog input A8 for ADC (not available on all device types)
P5.0/A8/VeREF+
P5.1/A9/VeREF-
9
E1
E2
B4
A4
4
5
I/O
I/O
DVCC
DVCC
Input for an external reference voltage to the ADC (not available
on all device types)
General-purpose digital I/O
Analog input A9 for ADC (not available on all device types)
10
Negative terminal for the ADC reference voltage for an external
applied reference voltage (not available on all device types)
AVCC
11
12
F2
F1
B5
A5
6
7
Analog power supply
General-purpose digital I/O
P5.4/XIN
I/O
I/O
DVCC
DVCC
Input terminal for crystal oscillator XT1(2)
General-purpose digital I/O
P5.5/XOUT
AVSS
13
14
G1
G2
A6
B6
8
9
Output terminal of crystal oscillator XT1
Analog ground supply
(1) I = input, O = output, N/A = not available
(2) When in crystal bypass mode, XIN can be configured so that it can support an input digital waveform with swing levels from DVSS to
DVCC or DVSS to DVIO. In this case, it is required that the pin be configured properly for the intended input swing.
16
Terminal Configuration and Functions
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Table 4-1. Terminal Functions (continued)
TERMINAL
NO.
RGC ZQE YFF RGZ
I/O(1) SUPPLY
DESCRIPTION
NAME
DVCC
DVSS
15
16
H1
J1
A7
A8
10
11
Digital power supply
Digital ground supply
Regulated core power supply output (internal use only, no
external current loading)
VCORE(3)
17
J2
B8
12
DVCC
General-purpose digital I/O with port interrupt
TA0 clock signal TA0CLK input
P1.0/TA0CLK/ACLK
18
H2
B7
13
I/O
I/O
I/O
DVCC
DVCC
DVCC
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
General-purpose digital I/O with port interrupt
P1.1/TA0.0
P1.2/TA0.1
19
20
H3
J3
C7
C8
14
15
TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output
General-purpose digital I/O with port interrupt
TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input
General-purpose digital I/O with port interrupt
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
21
22
23
G4
H4
J4
C6
C5
D8
16
17
18
I/O
I/O
I/O
DVCC
DVIO(4)
DVIO(4)
TA0 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O with port interrupt
TA0 CCR3 capture: CCI3A input compare: Out3 output
General-purpose digital I/O with port interrupt
TA0 CCR4 capture: CCI4A input, compare: Out4 output
General-purpose digital I/O with port interrupt
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
24
25
G5
H5
D7
D6
19
20
I/O
I/O
DVIO(4) TA1 clock signal TA1CLK input
Comparator_B output
General-purpose digital I/O with port interrupt
DVIO(4)
DVIO(4)
TA1 CCR0 capture: CCI0A input, compare: Out0 output
General-purpose digital I/O with port interrupt (not available on
all device types)
P2.0/TA1.1
P2.1/TA1.2
26
27
J5
E8
D5
N/A
N/A
I/O
I/O
TA1 CCR1 capture: CCI1A input, compare: Out1 output (not
available on all device types)
General-purpose digital I/O with port interrupt (not available on
all device types)
G6
DVIO(4)
DVIO(4)
TA1 CCR2 capture: CCI2A input, compare: Out2 output (not
available on all device types)
General-purpose digital I/O with port interrupt (not available on
all device types)
P2.2/TA2CLK/SMCLK
28
J6
E7
N/A
I/O
TA2 clock signal TA2CLK input
SMCLK output (not available on all device types)
General-purpose digital I/O with port interrupt (not available on
all device types)
P2.3/TA2.0
P2.4/TA2.1
29
30
H6
J7
F8
E6
N/A
N/A
I/O
I/O
DVIO(4)
DVIO(4)
TA2 CCR0 capture: CCI0A input, compare: Out0 output (not
available on all device types)
General-purpose digital I/O with port interrupt (not available on
all device types)
TA2 CCR1 capture: CCI1A input, compare: Out1 output (not
available on all device types)
(3) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE
.
(4) This pin function is supplied by DVIO. See Section 5.8 for input and output requirements.
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Terminal Configuration and Functions
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Table 4-1. Terminal Functions (continued)
TERMINAL
NO.
RGC ZQE YFF RGZ
I/O(1) SUPPLY
DESCRIPTION
NAME
General-purpose digital I/O with port interrupt (not available on
all device types)
P2.5/TA2.2
31
J8
F7
N/A
I/O
I/O
DVIO(4)
TA2 CCR2 capture: CCI2A input, compare: Out2 output (not
available on all device types)
General-purpose digital I/O with port interrupt (not available on
all device types)
P2.6/RTCCLK/DMAE0
32
J9
G8
N/A
DVIO(4) RTC clock output for calibration (not available on all device
types)
DMA external trigger input (not available on all device types)
General-purpose digital I/O
P2.7/UCB0STE/
UCA0CLK
Slave transmit enable – USCI_B0 SPI mode
DVIO(4)
33
H7
F6
21
I/O
Clock signal input
–
USCI_A0 SPI slave mode
Clock signal output – USCI_A0 SPI master mode
General-purpose digital I/O
P3.0/UCB0SIMO/
UCB0SDA
34
35
H8
H9
H8
G7
22
23
I/O
I/O
DVIO(4) Slave in, master out – USCI_B0 SPI mode
I2C data – USCI_B0 I2C mode
General-purpose digital I/O
P3.1/UCB0SOMI/
UCB0SCL
DVIO(4) Slave out, master in – USCI_B0 SPI mode
I2C clock – USCI_B0 I2C mode
General-purpose digital I/O
P3.2/UCB0CLK/
UCA0STE
Clock signal input
Clock signal output – USCI_B0 SPI master mode
–
USCI_B0 SPI slave mode
36
G8
G6
24
I/O
DVIO(4)
Slave transmit enable – USCI_A0 SPI mode
General-purpose digital I/O
P3.3/UCA0TXD/
UCA0SIMO
37
38
G9
G7
H7
G5
25
26
I/O
I/O
DVIO(4) Transmit data – USCI_A0 UART mode
Slave in, master out – USCI_A0 SPI mode
General-purpose digital I/O
P3.4/UCA0RXD/
UCA0SOMI
DVIO(4) Receive data – USCI_A0 UART mode
Slave out, master in – USCI_A0 SPI mode
Digital ground supply
DVSS
DVIO(5)
39
40
F9
E9
H6
H5
27
28
Digital I/O power supply
General-purpose digital I/O with reconfigurable port mapping
secondary function Default mapping: Slave transmit enable –
USCI_B1 SPI mode
P4.0/PM_UCB1STE/
PM_UCA1CLK
41
E8
F5
29
I/O
DVIO(4)
Default mapping: Clock signal input – USCI_A1 SPI slave mode
Default mapping: Clock signal output – USCI_A1 SPI master
mode
General-purpose digital I/O with reconfigurable port mapping
secondary function
P4.1/PM_UCB1SIMO/
PM_UCB1SDA
42
43
E7
D9
H4
E5
30
31
I/O
I/O
DVIO(4)
Default mapping: Slave in, master out – USCI_B1 SPI mode
Default mapping: I2C data – USCI_B1 I2C mode
General-purpose digital I/O with reconfigurable port mapping
secondary function
P4.2/PM_UCB1SOMI/
PM_UCB1SCL
DVIO(4)
Default mapping: Slave out, master in – USCI_B1 SPI mode
Default mapping: I2C clock – USCI_B1 I2C mode
(5) The voltage on DVIO is not supervised or monitored.
18 Terminal Configuration and Functions
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Table 4-1. Terminal Functions (continued)
TERMINAL
NO.
RGC ZQE YFF RGZ
I/O(1) SUPPLY
DESCRIPTION
NAME
General-purpose digital I/O with reconfigurable port mapping
secondary function
P4.3/PM_UCB1CLK/
PM_UCA1STE
Default mapping: Clock signal input – USCI_B1 SPI slave mode
Default mapping: Clock signal output – USCI_B1 SPI master
mode
44
D8
G4
32
I/O
DVIO(4)
Default mapping: Slave transmit enable – USCI_A1 SPI mode
General-purpose digital I/O with reconfigurable port mapping
secondary function
P4.4/PM_UCA1TXD/
PM_UCA1SIMO
45
46
D7
C9
H3
F4
33
34
I/O
I/O
DVIO(4)
Default mapping: Transmit data – USCI_A1 UART mode
Default mapping: Slave in, master out – USCI_A1 SPI mode
General-purpose digital I/O with reconfigurable port mapping
secondary function
P4.5/PM_UCA1RXD/
PM_UCA1SOMI
DVIO(4)
Default mapping: Receive data – USCI_A1 UART mode
Default mapping: Slave out, master in – USCI_A1 SPI mode
General-purpose digital I/O with reconfigurable port mapping
secondary function
P4.6/PM_NONE
P4.7/PM_NONE
47
48
C8
C7
H2
G3
35
I/O
I/O
DVIO(4)
DVIO(4)
Default mapping: no secondary function
General-purpose digital I/O with reconfigurable port mapping
secondary function (not available on all device types)
N/A
Default mapping: no secondary function (not available on all
device types)
General-purpose digital I/O (not available on all device types)
B8,
B9
P7.0/TB0.0
P7.1/TB0.1
P7.2/TB0.2
P7.3/TB0.3
P7.4/TB0.4
P7.5/TB0.5
49
50
51
52
53
54
H1
G2
F3
G1
F2
F1
N/A
N/A
N/A
N/A
N/A
N/A
I/O
I/O
I/O
I/O
I/O
I/O
DVIO(4)
DVIO(4)
DVIO(4)
DVIO(4)
DVIO(4)
DVIO(4)
TB0 CCR0 capture: CCI0A input, compare: Out0 output (not
available on all device types)
General-purpose digital I/O (not available on all device types)
A9
B7
A8
A7
A6
TB0 CCR1 capture: CCI1A input, compare: Out1 output (not
available on all device types)
General-purpose digital I/O (not available on all device types)
TB0 CCR2 capture: CCI2A input, compare: Out2 output (not
available on all device types)
General-purpose digital I/O (not available on all device types)
TB0 CCR3 capture: CCI3A input, compare: Out3 output (not
available on all device types)
General-purpose digital I/O (not available on all device types)
TB0 CCR4 capture: CCI4A input, compare: Out4 output (not
available on all device types)
General-purpose digital I/O (not available on all device types)
TB0 CCR5 capture: CCI5A input, compare: Out5 output (not
available on all device types)
BSLEN
55
56
B6
A5
E2
E3
36
37
I
I
DVIO(4) BSL enable with internal pulldown
Reset input active low(6)(7)
RST/NMI
DVIO(4)
Nonmaskable interrupt input(6)
General-purpose digital I/O
DVCC
P5.2/XT2IN
57
B5
E1
38
I/O
Input terminal for crystal oscillator XT2(8)
(6) This pin is configurable as reset or NMI and resides on the DVIO supply domain. When driven from external, input swing levels from
DVSS to DVIO are required.
(7) When this pin is configured as reset, the internal pullup resistor is enabled by default.
(8) When in crystal bypass mode, XT2IN can be configured so that it can support an input digital waveform with swing levels from DVSS to
DVCC or DVSS to DVIO. In this case, it is required that the pin be configured properly for the intended input swing.
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Terminal Configuration and Functions
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Table 4-1. Terminal Functions (continued)
TERMINAL
NO.
RGC ZQE YFF RGZ
I/O(1) SUPPLY
DESCRIPTION
NAME
General-purpose digital I/O
P5.3/XT2OUT
58
59
60
61
62
63
B4
A4
C5
C4
A3
B3
D1
E4
D2
C1
D3
B1
39
40
41
42
43
44
I/O
I
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
Output terminal of crystal oscillator XT2
Test mode pin – Selects four wire JTAG operation
TEST/SBWTCK(9)
PJ.0/TDO(10)
Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated
General-purpose digital I/O
I/O
I/O
I/O
I/O
JTAG test data output port
General-purpose digital I/O
PJ.1/TDI/TCLK(10)
PJ.2/TMS(10)
JTAG test data input or test clock input
General-purpose digital I/O
JTAG test mode select
General-purpose digital I/O
PJ.3/TCK(10)
JTAG test clock
Reset input, active-low(11)
RSTDVCC/
64
A2
D4
45
I/O
DVCC
SBWTDIO(10)
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation
activated
(12)
Reserved
QFN Pad
N/A
N/A
N/A
Reserved
Pad N/A
N/A Pad
QFN thermal pad. TI recommends connecting to VSS.
(9) See Section 6.5 and Section 6.6 for use with BSL and JTAG functions.
(10) See Section 6.6 for use with JTAG function.
(11) This nonconfigurable reset resides on the DVCC supply domain and has an internal pullup to DVCC. When driven from external, input
swing levels from DVSS to DVCC are required. This reset must be used for Spy-Bi-Wire communication and is not the same RST/NMI
reset as found on other devices in the MSP430 family. See Section 6.5 and Section 6.6 for details regarding the use of this pin.
(12) C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.
20
Terminal Configuration and Functions
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5 Specifications
All graphs in this section are for typical conditions, unless otherwise noted.
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
4.1
UNIT
V
Voltage applied at VCC to VSS
–0.3
–0.3
–0.3
–0.3
Voltage applied at VIO to VSS
Voltage applied to any pin (excluding VCORE and VIO pins)(2)
2.2
V
VCC + 0.3
VIO + 0.2
±2
V
Voltage applied to VIO pins
V
Diode current at any device pin
mA
°C
(3)
Storage temperature, Tstg
–55
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD) Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3 Recommended Operating Conditions
MIN
1.8
NOM
MAX
3.6
UNIT
PMMCOREVx = 0
PMMCOREVx = 0, 1
PMMCOREVx = 0, 1, 2
PMMCOREVx = 0, 1, 2, 3
2.0
3.6
Supply voltage during program execution and flash
programming (AVCC = DVCC)(1)(2)(3)
VCC
V
2.2
3.6
2.4
3.6
(2)
VIO
Supply voltage applied to DVIO referenced to VSS
Supply voltage (AVSS = DVSS)
1.62
1.98
V
V
VSS
TA
0
Operating free-air temperature
–40
–40
85
85
°C
°C
nF
TJ
Operating junction temperature
Recommended capacitor at VCORE(4)
CVCORE
470
CDVCC
CVCORE
/
Capacitor ratio of DVCC to VCORE
10
(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2) During VCC and VIO power up, it is required that VIO ≥ VCC during the ramp up phase of VIO. During VCC and VIO power down, it is
required that VIO ≥ VCC during the ramp down phase of VIO (see Figure 5-1).
(3) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 5.28 threshold parameters for
the exact values and further details.
(4) A capacitor tolerance of ±20% or better is required.
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Specifications
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Recommended Operating Conditions (continued)
MIN
NOM
MAX
UNIT
PMMCOREVx = 0
(default condition),
0
8
1.8 V ≤ VCC ≤ 3.6 V
PMMCOREVx = 1,
2.0 V ≤ VCC ≤ 3.6 V
Processor frequency (maximum MCLK frequency)(5)
(see Figure 5-3)
0
0
0
12
20
25
fSYSTEM
MHz
PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V
PMMCOREVx = 3,
2.4 V ≤ VCC ≤ 3.6 V
(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
VCC
VIO
VIO,min
VSS
t
VCC ≤ VIO
VIO ≤ VCC
VCC ≤ VIO
while VIO < VIO,min
while VIO < VIO,min
NOTE: The device supports continuous operation with VCC = VSS while VIO is fully within its specification. During this time, the
general-purpose I/Os that reside on the VIO supply domain are configured as inputs and pulled down to VSS through
their internal pulldown resistors. RST/NMI is high impedance. BSLEN is configured as an input and is pulled down to
VSS through its internal pulldown resistor. When VCC reaches above the BOR threshold, the general-purpose I/Os
become high-impedance inputs (no resistor enabled), RST/NMI becomes an input pulled up to VIO through its internal
pullup resistor, and BSLEN remains pulled down to VSS through its internal pulldown resistor.
NOTE: Under certain condtions during the rising transition of VCC, the general-purpose I/Os residing on the VIO supply
domain may actively transition high momentarily before settling to high-impedance inputs. These voltage transitions
are temporary (typically resolving to high-impedance inputs when VCC exceeds approximately 0.9 V) and are bounded
by the VIO supply.
Figure 5-1. VCC and VIO Power Sequencing
22
Specifications
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VCC
V(SVSH_+), min
tWAKE_UP_RESET
tWAKE_UP_RESET
tWAKE_UP_RESET
DVCC
VCC
VIT+
RSTDVCC
VCC ≥ VRSTDVCC
VRSTDVCC = VCC
VIO
tWAKE_UP_RESET
tWAKE_UP_RESET
DVIO
VIO
VIT+
RST
VIO ≥ VRST
VRST = VIO
t
NOTE: The device remains in reset based on the conditions of the RSTDVCC and RST pins and the voltage present on
DVCC voltage supply. If RSTDVCC or RST is held at a logic low or if DVCC is below the SVSH_+ minimum
threshold, the device remains in its reset condition; that is, these conditions form a logical OR with respect to device
reset.
Figure 5-2. Reset Timing
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Specifications
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25
3
20
2, 3
2
12
1, 2
1, 2, 3
1
8
0
0, 1
0, 1, 2
0, 1, 2, 3
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
NOTE: The numbers within the fields denote the supported PMMCOREVx settings.
Figure 5-3. Maximum System Frequency
5.4 Active Mode Supply Current Into VCC Excluding External Current
(2) (3)
over recommended operating free-air temperature (unless otherwise noted)(1)
FREQUENCY (fDCO = fMCLK = fSMCLK
8 MHz 12 MHz 20 MHz
TYP MAX TYP MAX
)
EXECUTION
MEMORY
PARAMETER
VCC
PMMCOREVx
1 MHz
25 MHz
UNIT
TYP
MAX
TYP
MAX
TYP
10.1
5.3
MAX
11.0
6.2
0
1
2
3
0
1
2
3
0.36
0.40
0.44
0.46
0.20
0.22
0.24
0.26
0.47
2.32
2.65
2.90
3.10
1.20
1.35
1.50
1.60
2.60
4.0
4.3
4.6
4.4
IAM, Flash
Flash
3.0 V
mA
7.1
7.6
7.7
4.2
0.29
1.30
2.0
2.2
2.4
2.2
IAM, RAM
RAM
3.0 V
mA
3.7
3.9
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Characterized with program executing typical data processing.
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.
24
Specifications
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5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
–40°C
25°C
60°C
85°C
PARAMETER
VCC
PMMCOREVx
UNIT
µA
TYP
MAX
TYP
MAX
91
TYP
MAX
TYP
MAX
97
2.2 V
3.0 V
2.2 V
3.0 V
0
3
0
3
0
1
2
0
1
2
3
0
1
2
3
0
1
2
3
73
79
77
83
80
88
85
95
ILPM0,1MHz
Low-power mode 0(3)(4)
Low-power mode 2(5)(4)
99
107
17
6.5
7.0
1.60
1.65
1.75
1.8
1.9
2.0
2.0
1.1
1.1
1.2
1.3
0.9
1.1
1.2
1.3
0.15
6.5
7.0
1.90
2.00
2.15
2.1
2.3
2.4
2.5
1.4
1.4
1.5
1.6
1.1
1.2
1.2
1.3
0.18
12
10
11
ILPM2
µA
13
11
12
18
2,8
3.0
3.2
3.0
3.2
3.3
3.4
2.0
2.2
2.3
2.3
2.0
2.1
2.2
2.2
0.26
6.0
6.3
6.6
6.2
6.5
6.8
6.8
6.1
6.4
6.8
6.8
5.1
5.3
5.5
5.5
0.5
2.2 V
Low-power mode 3, crystal
mode(6)(4)
ILPM3,XT1LF
2.9
9.4
µA
µA
3.0 V
3.9
2.7
10.9
9.7
Low-power mode 3,
VLO mode(7)(4)
ILPM3,VLO
3.0 V
3.0
1.5
10.9
8.8
ILPM4
Low-power mode 4(8)(4)
Low-power mode 4.5(9)
3.0 V
3.0 V
µA
µA
1.6
9.8
1.0
ILPM4.5
0.35
Current supplied from
DVIO while
DVCC = AVCC = 0 V,
DVIO = 1.62 V to 1.98 V,
All DVIO I/O floating
including BSLEN and
RST/NMI
IDVIO_START
0 V
1.8
1.8
1.8
1.8
µA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Current for the watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
(4) Current for brownout and high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML)
disabled. High-side monitor (SVMH) disabled. RAM retention enabled.
(5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO setting = 1
MHz operation, DCO bias generator enabled.)
(6) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
(7) Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
(9) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
Copyright © 2012–2018, Texas Instruments Incorporated
Specifications
25
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5.6 Thermal Resistance Characteristics
THERMAL METRIC(1)
VALUE(2)
27.8
29.6
44.3
35.2
13.6
14.8
0.2
UNIT
VQFN 48 (RGZ)
VQFN 64 (RGC)
DSBGA 64 (YFF)
BGA 80 (ZQE)
RθJA
Junction-to-ambient thermal resistance, still air
Junction-to-case (top) thermal resistance
°C/W
VQFN 48 (RGZ)
VQFN 64 (RGC)
DSBGA 64 (YFF)
BGA 80 (ZQE)
RθJC(TOP)
RθJC(BOTTOM)
RθJB
°C/W
°C/W
°C/W
°C/W
°C/W
17.6
0.9
VQFN 48 (RGZ)
VQFN 64 (RGC)
DSBGA 64 (YFF)
BGA 80 (ZQE)
1.4
Junction-to-case (bottom) thermal resistance
Junction-to-board thermal resistance
N/A(3)
N/A
4.7
VQFN 48 (RGZ)
VQFN 64 (RGC)
DSBGA 64 (YFF)
BGA 80 (ZQE)
8.5
6.0
16.7
0.2
VQFN 48 (RGZ)
VQFN 64 (RGC)
DSBGA 64 (YFF)
BGA 80 (ZQE)
0.2
ΨJT
Junction-to-package-top thermal characterization parameter
Junction-to-board thermal characterization parameter
0.6
0.3
VQFN 48 (RGZ)
VQFN 64 (RGC)
DSBGA 64 (YFF)
BGA 80 (ZQE)
4.7
8.4
ΨJB
6.0
9.6
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(3) N/A = not applicable
26
Specifications
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5.7 Schmitt-Trigger Inputs – General-Purpose I/O DVCC Domain(1)
(P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RSTDVCC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.8 V
3 V
MIN
0.80
1.50
0.45
0.75
0.3
TYP
MAX UNIT
1.40
V
VIT+
VIT–
Vhys
Positive-going input threshold voltage
2.10
1.8 V
3 V
1.00
V
Negative-going input threshold voltage
1.65
1.8 V
3 V
0.8
V
Input voltage hysteresis (VIT+ – VIT–
)
0.4
1.0
For pullup: VIN = VSS
For pulldown: VIN = VCC
,
RPull
CI
Pullup or pulldown resistor(2)
Input capacitance
20
35
5
50
kΩ
VIN = VSS or VCC
pF
(1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
(2) RSTDVCC has a fixed pullup resistor that cannot be disabled.
5.8 Schmitt-Trigger Inputs – General-Purpose I/O DVIO Domain
(P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5, RST/NMI, BSLEN)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
1.62 V
MIN
0.8
1.1
0.3
0.5
0.3
TYP
MAX UNIT
1.25
V
VIT+
Positive-going input threshold voltage
VCC = 3.0 V
1.98 V
1.40
1.62 V
0.7
V
VIT–
Negative-going input threshold voltage
VCC = 3.0 V
VCC = 3.0 V
1.98 V
1.0
Vhys
RPull
CI
Input voltage hysteresis (VIT+ – VIT–
Pullup or pulldown resistor(1)
Input capacitance
)
1.62 V to 1.98 V
0.8
V
For pullup: VIN = VSS
,
20
35
5
50
kΩ
pF
For pulldown: VIN = VIO
VIN = VSS or VIO
(1) Also applies to RST pin when pullup or pulldown resistor is enabled.
5.9 Inputs – Interrupts DVCC Domain Port P1
(P1.0 to P1.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
t(int)
External interrupt timing(1)
External trigger pulse duration to set interrupt flag
1.8 V, 3 V
20
ns
(1) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int)
.
5.10 Inputs – Interrupts DVIO Domain Ports P1 and P2
(P1.4 to P1.7, P2.0 to P2.7)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
VIO
MIN
MAX UNIT
External trigger pulse duration to set interrupt flag,
VCC = 1.8 V or 3.0 V
t(int)
External interrupt timing(2)
1.62 V to 1.98 V
20
ns
(1) In all test conditions, VIO ≤ VCC
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int)
.
.
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Specifications
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5.11 Leakage Current – General-Purpose I/O DVCC Domain
(P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
50 nA
(1) (2)
Ilkg(Px.y)
High-impedance leakage current
1.8 V, 3 V
–50
(1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
5.12 Leakage Current – General-Purpose I/O DVIO Domain
(P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
VIO
MIN
MAX UNIT
50 nA
(2) (3)
Ilkg(Px.y)
High-impedance leakage current
1.62 V to 1.98 V
–50
(1) In all test conditions, VIO ≤ VCC
.
(2) The leakage current is measured with VSS or VIO applied to the corresponding pins, unless otherwise noted.
(3) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
5.13 Outputs – General-Purpose I/O DVCC Domain (Full Drive Strength)
(P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA(1)
VCC
MIN
VCC – 0.25
VCC – 0.60
VCC – 0.25
VCC – 0.60
MAX UNIT
VCC
1.8 V
I(OHmax) = –10 mA(2)
I(OHmax) = –5 mA(1)
I(OHmax) = –15 mA(2)
I(OLmax) = 3 mA(1)
I(OLmax) = 10 mA(2)
I(OLmax) = 5 mA(1)
I(OLmax) = 15 mA(2)
VCC
VOH
High-level output voltage
V
VCC
3 V
1.8 V
3 V
VCC
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
VSS VSS + 0.60
VOL
Low-level output voltage
V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
5.14 Outputs – General-Purpose I/O DVCC Domain (Reduced Drive Strength)
(P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA(2)
VCC
MIN
VCC – 0.25
VCC – 0.60
VCC – 0.25
VCC – 0.60
MAX UNIT
VCC
1.8 V
I(OHmax) = –3 mA(3)
I(OHmax) = –2 mA(2)
I(OHmax) = –6 mA(3)
I(OLmax) = 1 mA(2)
I(OLmax) = 3 mA(3)
I(OLmax) = 2 mA(2)
I(OLmax) = 6 mA(3)
VCC
VOH
High-level output voltage
V
VCC
3.0 V
1.8 V
3.0 V
VCC
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
VSS VSS + 0.60
VOL
Low-level output voltage
V
(1) Selecting reduced drive strength may reduce EMI.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
(3) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
28
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5.15 Outputs – General-Purpose I/O DVIO Domain (Full Drive Strength)
(P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA(2)
I(OHmax) = –6 mA(2)
I(OLmax) = 3 mA(2)
I(OLmax) = 6 mA(2)
VIO
MIN
VIO – 0.25
VIO – 0.50
MAX UNIT
VIO
VOH
High-level output voltage
1.62 V to 1.98 V
V
VIO
VSS VSS + 0.25
VSS VSS + 0.50
VOL
Low-level output voltage
1.62 V to 1.98 V
V
(1) In all test conditions, VIO ≤ VCC
.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
5.16 Outputs – General-Purpose I/O DVIO Domain (Reduced Drive Strength)
(P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(2)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA(3)
I(OHmax) = –2 mA(3)
I(OLmax) = 1 mA(3)
I(OLmax) = 2 mA(3)
VIO
MIN
VIO – 0.25
VIO – 0.50
MAX UNIT
VIO
VOH
High-level output voltage
1.62 V to 1.98 V
V
VIO
VSS VSS + 0.25
VSS VSS + 0.50
VOL
Low-level output voltage
1.62 V to 1.98 V
V
(1) Selecting reduced drive strength may reduce EMI.
(2) In all test conditions, VIO ≤ VCC
.
(3) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
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Specifications
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5.17 Output Frequency – General-Purpose I/O DVCC Domain
(P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
VCC = 1.8 V,
PMMCOREVx = 0
16
Port output frequency
(with load)
(1)(2)
fPx.y
MHz
25
VCC = 3 V,
PMMCOREVx = 3
VCC = 1.8 V,
PMMCOREVx = 0
16
ACLK, SMCLK, or MCLK,
CL = 20 pF(2)
fPort_CLK
Clock output frequency
MHz
25
VCC = 3 V,
PMMCOREVx = 3
(1) A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS
.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
5.18 Output Frequency – General-Purpose I/O DVIO Domain
(P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO = 1.62 V to 1.98 V(3)
MIN
MAX UNIT
,
,
,
,
16
PMMCOREVx = 0
VIO = 1.62 V to 1.98 V(3)
PMMCOREVx = 3
Port output frequency
(with load)
(1)(2)
fPx.y
MHz
25
VIO = 1.62 V to 1.98 V(3)
PMMCOREVx = 0
VIO = 1.62 V to 1.98 V(3)
PMMCOREVx = 3
16
ACLK, SMCLK, or MCLK,
CL = 20 pF(2)
fPort_CLK
Clock output frequency
MHz
25
(1) A resistive divider with 2 × R1 between VIO and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS
.
(2) The output voltage reaches at least 10% and 90% VIO at the specified toggle frequency.
(3) In all test conditions, VIO ≤ VCC
.
30
Specifications
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5.19 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
25.0
20.0
15.0
10.0
5.0
TA = 25°C
TA = 85°C
VCC = 3.0 V
Px.y
VCC = 1.8 V
Px.y
TA = 25°C
TA = 85°C
0.0
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOL – Low-Level Output Voltage – V
Figure 5-5. Typical Low-Level Output Current vs Low-Level
Output Voltage
VOL – Low-Level Output Voltage – V
Figure 5-4. Typical Low-Level Output Current vs Low-Level
Output Voltage
0.0
0.0
VCC = 1.8 V
VCC = 3.0 V
Px.y
Px.y
−1.0
−5.0
−2.0
−3.0
−4.0
−10.0
TA = 85°C
−5.0
−15.0
TA = 85°C
−6.0
TA = 25°C
−20.0
TA = 25°C
−7.0
−8.0
−25.0
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH – High-Level Output Voltage – V
Figure 5-7. Typical High-Level Output Current vs High-Level
Output Voltage
VOH – High-Level Output Voltage – V
Figure 5-6. Typical High-Level Output Current vs High-Level
Output Voltage
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5.20 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
60.0
24
20
16
12
8
TA = 25°C
TA = 85°C
VCC = 1.8 V
Px.y
VCC = 3.0 V
Px.y
55.0
50.0
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
TA = 25°C
TA = 85°C
4
0
0.0
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOL – Low-Level Output Voltage – V
Figure 5-9. Typical Low-Level Output Current vs Low-Level
Output Voltage
VOL – Low-Level Output Voltage – V
Figure 5-8. Typical Low-Level Output Current vs Low-Level
Output Voltage
0
0.0
VCC = 1.8 V
Px.y
VCC = 3.0 V
−5.0
Px.y
−10.0
−15.0
−20.0
−25.0
−30.0
−35.0
−40.0
−4
−8
−12
TA = 85°C
−16
−45.0
TA = 85°C
−50.0
−55.0
TA = 25°C
−60.0
TA = 25°C
−20
0.0
0.5
1.0
1.5
2.0
0.0
0.5
VOH – High-Level Output Voltage – V
Figure 5-10. Typical High-Level Output Current vs High-Level
1.0
1.5
2.0
2.5
3.0
3.5
VOH – High-Level Output Voltage – V
Figure 5-11. Typical High-Level Output Current vs High-Level
Output Voltage
Output Voltage
32
Specifications
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5.21 Crystal Oscillator, XT1, Low-Frequency Mode
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C
0.075
Differential XT1 oscillator crystal
fOSC = 32768 Hz, XTS = 0,
ΔIDVCC.LF
current consumption from lowest XT1BYPASS = 0, XT1DRIVEx = 2,
3.0 V
0.170
µA
drive setting, LF mode
TA = 25°C
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C
0.290
XT1 oscillator crystal frequency,
LF mode
fXT1,LF0
XTS = 0, XT1BYPASS = 0
32768
Hz
XT1 oscillator logic-level square- XTS = 0, XT1BYPASS = 1(2)(3)
fXT1,LF,SW
10 32.768
210
50 kHz
wave input frequency, LF mode
XT1BYPASSLV = 0 or 1
XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
Oscillation allowance for
LF crystals(4)
OALF
kΩ
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
300
XTS = 0, XCAPx = 0(6)
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
XTS = 0, XCAPx = 3
1
5.5
Integrated effective load
capacitance, LF mode(5)
CL,eff
pF
8.5
12.0
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
Duty cycle, LF mode
30%
10
70%
Oscillator fault frequency,
LF mode(7)
XTS = 0, XT1BYPASS = 1(8)
XT1BYPASSLV = 0 or 1
,
fFault,LF
10000
Hz
ms
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C, CL,eff = 6 pF
1000
500
tSTART,LF
Start-up time, LF mode
3.0 V
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C, CL,eff = 12 pF
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
•
•
•
•
•
•
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-Trigger Inputs section of this data sheet. When in crystal bypass mode, XIN can be configured so that it can support an
input digital waveform with swing levels from DVSS to DVCC (XT1BYPASSLV = 0) or DVSS to DVIO (XT1BYPASSLV = 1). In this case,
the pin must be configured properly for the intended input swing.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but each application should be evaluated based on the actual crystal selected:
•
•
•
•
For XT1DRIVEx = 0, CL,eff ≤ 6 pF
For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF
For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF
For XT1DRIVEx = 3, CL,eff ≥ 6 pF
(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the
effective load capacitance should always match the specification of the used crystal.
(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.
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MAX UNIT
5.22 Crystal Oscillator, XT2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
fOSC = 4 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C
200
fOSC = 12 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 1,
TA = 25°C
260
325
450
XT2 oscillator crystal current
consumption
IDVCC.XT2
3.0 V
µA
fOSC = 20 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C
fOSC = 32 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 3,
TA = 25°C
XT2 oscillator crystal frequency,
mode 0
fXT2,HF0
fXT2,HF1
fXT2,HF2
fXT2,HF3
XT2DRIVEx = 0, XT2BYPASS = 0(3)
XT2DRIVEx = 1, XT2BYPASS = 0(3)
XT2DRIVEx = 2, XT2BYPASS = 0(3)
XT2DRIVEx = 3, XT2BYPASS = 0(3)
4
8
8
MHz
XT2 oscillator crystal frequency,
mode 1
16 MHz
24 MHz
32 MHz
XT2 oscillator crystal frequency,
mode 2
16
24
XT2 oscillator crystal frequency,
mode 3
XT2 oscillator logic-level square-
wave input frequency, bypass
mode
XT2BYPASS = 1(4)(3)
XT2BYPASSLV = 0 or 1
fXT2,HF,SW
0.7
32 MHz
XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 6 MHz, CL,eff = 15 pF
450
320
200
200
XT2DRIVEx = 1, XT2BYPASS = 0,
fXT2,HF1 = 12 MHz, CL,eff = 15 pF
Oscillation allowance for
HF crystals(5)
OAHF
Ω
XT2DRIVEx = 2, XT2BYPASS = 0,
fXT2,HF2 = 20 MHz, CL,eff = 15 pF
XT2DRIVEx = 3, XT2BYPASS = 0,
fXT2,HF3 = 32 MHz, CL,eff = 15 pF
fOSC = 6 MHz,
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C, CL,eff = 15 pF
0.5
0.3
tSTART,HF
Start-up time
3.0 V
ms
pF
fOSC = 20 MHz,
XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C, CL,eff = 15 pF
Integrated effective load
CL,eff
1
capacitance, HF mode(6) (1)
Duty cycle
Measured at ACLK, fXT2,HF2 = 20 MHz
40%
50%
60%
(1) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(2) To improve EMI on the XT2 oscillator the following guidelines should be observed.
•
•
•
•
•
•
Keep the traces between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(3) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device
operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.
(4) When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined
in the Schmitt-trigger Inputs section of this data sheet. When in crystal bypass mode, XT2IN can be configured so that it can support an
input digital waveform with swing levels from DVSS to DVCC (XT2BYPASSLV = 0) or DVSS to DVIO (XT2BYPASSLV = 1). In this case,
it is required that the pin be configured properly for the intended input swing.
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the
effective load capacitance should always match the specification of the used crystal.
34
Specifications
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Crystal Oscillator, XT2 (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
XT2BYPASS = 1(8)
XT2BYPASSLV = 0 or 1
,
fFault,HF
Oscillator fault frequency(7)
30
300 kHz
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals. In general, an effective load capacitance of up to
18 pF can be supported.
5.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLO frequency
VLO frequency temperature drift
TEST CONDITIONS
VCC
MIN
TYP
9.4
0.5
4
MAX UNIT
14 kHz
%/°C
fVLO
Measured at ACLK
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
6
dfVLO/dT
Measured at ACLK(1)
Measured at ACLK(2)
Measured at ACLK
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
%/V
40%
50%
60%
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
5.24 Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
3
MAX UNIT
µA
IREFO
REFO oscillator current consumption TA = 25°C
1.8 V to 3.6 V
1.8 V to 3.6 V
REFO frequency
Measured at ACLK
32768
Hz
fREFO
Full temperature range
TA = 25°C
Measured at ACLK(1)
1.8 V to 3.6 V –3.5%
3.5%
1.5%
%/°C
%/V
REFO absolute tolerance
REFO frequency temperature drift
3 V
–1.5%
dfREFO/dT
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
0.01
1.0
dfREFO/dVCC
REFO frequency supply voltage drift Measured at ACLK(2)
Duty cycle
Measured at ACLK
40%/60% duty cycle
40%
50%
25
60%
tSTART
REFO start-up time
µs
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
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5.25 DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DCORSELx = 0, DCOx = 0, MODx = 0
DCORSELx = 0, DCOx = 31, MODx = 0
DCORSELx = 1, DCOx = 0, MODx = 0
DCORSELx = 1, DCOx = 31, MODx = 0
DCORSELx = 2, DCOx = 0, MODx = 0
DCORSELx = 2, DCOx = 31, MODx = 0
DCORSELx = 3, DCOx = 0, MODx = 0
DCORSELx = 3, DCOx = 31, MODx = 0
DCORSELx = 4, DCOx = 0, MODx = 0
DCORSELx = 4, DCOx = 31, MODx = 0
DCORSELx = 5, DCOx = 0, MODx = 0
DCORSELx = 5, DCOx = 31, MODx = 0
DCORSELx = 6, DCOx = 0, MODx = 0
DCORSELx = 6, DCOx = 31, MODx = 0
DCORSELx = 7, DCOx = 0, MODx = 0
DCORSELx = 7, DCOx = 31, MODx = 0
MIN
0.07
0.70
0.15
1.47
0.32
3.17
0.64
6.07
1.3
TYP
MAX UNIT
0.20 MHz
1.70 MHz
0.36 MHz
3.45 MHz
0.75 MHz
7.38 MHz
1.51 MHz
14.0 MHz
3.2 MHz
fDCO(0,0)
fDCO(0,31)
fDCO(1,0)
fDCO(1,31)
fDCO(2,0)
fDCO(2,31)
fDCO(3,0)
fDCO(3,31)
fDCO(4,0)
fDCO(4,31)
fDCO(5,0)
fDCO(5,31)
fDCO(6,0)
fDCO(6,31)
fDCO(7,0)
fDCO(7,31)
DCO frequency (0, 0)(1)
DCO frequency (0, 31)(1)
DCO frequency (1, 0)(1)
DCO frequency (1, 31)(1)
DCO frequency (2, 0)(1)
DCO frequency (2, 31)(1)
DCO frequency (3, 0)(1)
DCO frequency (3, 31)(1)
DCO frequency (4, 0)(1)
DCO frequency (4, 31)(1)
DCO frequency (5, 0)(1)
DCO frequency (5, 31)(1)
DCO frequency (6, 0)(1)
DCO frequency (6, 31)(1)
DCO frequency (7, 0)(1)
DCO frequency (7, 31)(1)
12.3
2.5
28.2 MHz
6.0 MHz
23.7
4.6
54.1 MHz
10.7 MHz
88.0 MHz
19.6 MHz
135 MHz
39.0
8.5
60
Frequency step between range
DCORSEL and DCORSEL + 1
SDCORSEL
SDCO
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
1.2
2.3 ratio
Frequency step between tap
DCO and DCO + 1
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
Measured at SMCLK
1.02
40%
1.12 ratio
60%
Duty cycle
50%
0.1
DCO frequency temperature
drift(2)
dfDCO/dT
fDCO = 1 MHz
%/°C
dfDCO/dVCC
DCO frequency voltage drift(3)
fDCO = 1 MHz
1.9
%/V
(1) When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the
range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31 (DCOx
= 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual fDCO
frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the
selected range is at its minimum or maximum tap setting.
(2) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(3) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
100
VCC = 3.0 V
TA = 25°C
10
DCOx = 31
1
DCOx = 0
0.1
0
1
2
3
4
5
6
7
DCORSEL
Figure 5-12. Typical DCO Frequency
36
Specifications
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5.26 PMM, Brownout Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
| dDVCC/dt | < 3 V/s
| dDVCC/dt | < 3 V/s
MIN
TYP
MAX UNIT
VDVCC_BOR_IT–
VDVCC_BOR_IT+
VDVCC_BOR_hys
BORH on voltage, DVCC falling level
BORH off voltage, DVCC rising level
BORH hysteresis
1.45
1.50
250
V
V
0.80
50
1.30
mV
Pulse duration required at RST/NMI pin to accept
a reset
tRESET
2
µs
5.27 PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Core voltage, active mode,
PMMCOREV = 3
VCORE3(AM)
VCORE2(AM)
VCORE1(AM)
VCORE0(AM)
VCORE3(LPM)
VCORE2(LPM)
VCORE1(LPM)
VCORE0(LPM)
2.4 V ≤ DVCC ≤ 3.6 V
1.90
V
Core voltage, active mode,
PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V
2.0 V ≤ DVCC ≤ 3.6 V
1.8 V ≤ DVCC ≤ 3.6 V
2.4 V ≤ DVCC ≤ 3.6 V
2.2 V ≤ DVCC ≤ 3.6 V
2.0 V ≤ DVCC ≤ 3.6 V
1.8 V ≤ DVCC ≤ 3.6 V
1.80
1.60
1.40
1.94
1.84
1.64
1.44
V
V
V
V
V
V
V
Core voltage, active mode,
PMMCOREV = 1
Core voltage, active mode,
PMMCOREV = 0
Core voltage, low-current mode,
PMMCOREV = 3
Core voltage, low-current mode,
PMMCOREV = 2
Core voltage, low-current mode,
PMMCOREV = 1
Core voltage, low-current mode,
PMMCOREV = 0
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5.28 PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SVSHE = 0, DVCC = 3.6 V
MIN
TYP
0
MAX UNIT
nA
I(SVSH)
SVS current consumption
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
SVSHE = 1, SVSHRVL = 0
200
1.5
µA
1.57
1.79
1.98
2.10
1.62
1.88
2.07
2.20
2.32
2.52
2.90
2.90
1.68
1.88
2.08
2.18
1.74
1.94
2.14
2.30
2.40
2.70
3.10
3.10
1.78
SVSHE = 1, SVSHRVL = 1
1.98
V
V(SVSH_IT–)
SVSH on voltage level(1)
SVSHE = 1, SVSHRVL = 2
2.21
SVSHE = 1, SVSHRVL = 3
2.31
1.85
2.07
2.28
SVSHE = 1, SVSMHRRL = 0
SVSHE = 1, SVSMHRRL = 1
SVSHE = 1, SVSMHRRL = 2
SVSHE = 1, SVSMHRRL = 3
SVSHE = 1, SVSMHRRL = 4
SVSHE = 1, SVSMHRRL = 5
SVSHE = 1, SVSMHRRL = 6
SVSHE = 1, SVSMHRRL = 7
2.42
V
V(SVSH_IT+)
SVSH off voltage level(1)
2.55
2.88
3.23
3.23
SVSHE = 1, dVDVCC/dt = 10 mV/µs,
SVSHFP = 1
2.5
20
tpd(SVSH)
SVSH propagation delay
µs
µs
SVSHE = 1, dVDVCC/dt = 1 mV/µs,
SVSHFP = 0
SVSHE = 0 → 1, dVDVCC/dt = 10 mV/µs,
SVSHFP = 1
12.5
100
t(SVSH)
SVSH on or off delay time
DVCC rise time
SVSHE = 0 → 1, dVDVCC/dt = 1 mV/µs,
SVSHFP = 0
dVDVCC/dt
0
1000
V/s
(1) The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and use.
38
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5.29 PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SVMHE = 0, DVCC = 3.6 V
MIN
TYP
0
MAX UNIT
nA
I(SVMH)
SVMH current consumption
SVMHE= 1, DVCC = 3.6 V, SVMHFP = 0
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
SVMHE = 1, SVSMHRRL = 0
SVMHE = 1, SVSMHRRL = 1
SVMHE = 1, SVSMHRRL = 2
SVMHE = 1, SVSMHRRL = 3
SVMHE = 1, SVSMHRRL = 4
SVMHE = 1, SVSMHRRL = 5
SVMHE = 1, SVSMHRRL = 6
SVMHE = 1, SVSMHRRL = 7
SVMHE = 1, SVMHOVPE = 1
200
1.5
µA
1.85
1.62
1.88
2.07
2.20
2.32
2.52
2.90
2.90
1.74
1.94
2.14
2.30
2.40
2.70
3.10
3.10
3.75
2.07
2.28
2.42
V(SVMH)
SVMH on or off voltage level(1)
2.55
2.88
3.23
3.23
V
SVMHE = 1, dVDVCC/dt = 10 mV/µs,
SVMHFP = 1
2.5
20
tpd(SVMH)
SVMH propagation delay
SVMH on or off delay time
µs
µs
SVMHE = 1, dVDVCC/dt = 1 mV/µs,
SVMHFP = 0
SVMHE = 0 → 1, dVDVCC/dt = 10 mV/µs,
SVMHFP = 1
12.5
100
t(SVMH)
SVMHE = 0 → 1, dVDVCC/dt = 1 mV/µs,
SVMHFP = 0
(1) The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and use.
5.30 PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SVSLE = 0, PMMCOREV = 2
MIN
TYP
0
MAX UNIT
nA
µA
µs
I(SVSL)
SVSL current consumption
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
200
1.5
2.5
20
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
SVSLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
SVSLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
tpd(SVSL)
SVSL propagation delay
SVSL on or off delay time
12.5
100
t(SVSL)
µs
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39
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5.31 PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SVMLE = 0, PMMCOREV = 2
MIN
TYP
0
MAX UNIT
nA
µA
µs
I(SVML)
SVML current consumption
SVMLE= 1, PMMCOREV = 2, SVMLFP = 0
200
1.5
2.5
20
SVMLE= 1, PMMCOREV = 2, SVMLFP = 1
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
SVMLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
SVMLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
tpd(SVML) SVML propagation delay
12.5
100
t(SVML)
SVML on or off delay time
µs
5.32 Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
f
MCLK ≥ 4.0 MHz
3.5
7.5
Wake-up time from LPM2,
LPM3, or LPM4 to active
mode(1)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1
tWAKE-UP-FAST
µs
9
1.0 MHz < fMCLK
4.0 MHz
<
4.5
Wake-up time from LPM2,
LPM3, or LPM4 to active
mode(2)(3)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 0
tWAKE-UP-SLOW
150
175
µs
Wake-up time from LPM4.5
to active mode(4)
tWAKE-UP-LPM5
tWAKE-UP-RESET
2
2
3
3
ms
ms
Wake-up time from RST or
BOR event to active mode(4)
(1) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in full performance
mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in
the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx Family User's Guide.
(2) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in normal mode (low
current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in the
Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx Family User's Guide.
(3) The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by the
performance mode settings as for LPM2, LPM3, and LPM4.
(4) This value represents the time from the wake-up event to the reset vector execution.
40
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5.33 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
VIO
MIN
TYP
MAX UNIT
Internal: SMCLK or ACLK,
External: TACLK,
Duty cycle = 50% ±10%
1.8 V
1.62 V to 1.8 V
25
fTA
Timer_A input clock frequency
MHz
3.0 V
1.8 V
3.0 V
1.62 V to 1.98 V
1.62 V to 1.8 V
1.62 V to 1.98 V
25
All capture inputs,
Minimum pulse duration
required for capture
20
20
tTA,cap Timer_A capture timing(1)
ns
(1) The external signal sets the interrupt flag every time the minimum parameters are met. It may be set even with trigger signals shorter
than tTA,cap
.
5.34 Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
VIO
MIN
TYP
MAX UNIT
Internal: SMCLK or ACLK,
External: TBCLK,
Duty cycle = 50% ±10%
1.8 V
1.62 V to 1.8 V
25
fTB
Timer_B input clock frequency
MHz
3.0 V
1.8 V
3.0 V
1.62 V to 1.98 V
1.62 V to 1.8 V
1.62 V to 1.98 V
25
All capture inputs,
Minimum pulse duration
required for capture
20
20
tTB,cap Timer_B capture timing(1)
ns
(1) The external signal sets the interrupt flag every time the minimum parameters are met. It may be set even with trigger signals shorter
than tTB,cap
.
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Specifications
41
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5.35 USCI (UART Mode), Recommended Operating Conditions
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
Internal: SMCLK or ACLK,
External: UCLK,
fUSCI
USCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ±10%
BITCLK clock frequency
(equals baud rate in MBaud)
fBITCLK
1
MHz
5.36 USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
VIO
MIN
MAX UNIT
1.62 V to
1.80 V
1.8 V
50
50
600
ns
tτ
UART receive deglitch time(1)
1.62 V to
1.98 V
3.0 V
600
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
5.37 USCI (SPI Master Mode), Recommended Operating Conditions
PARAMETER
TEST CONDITIONS
Internal: SMCLK or ACLK,
Duty cycle = 50% ±10%
MIN
MAX UNIT
fUSCI
USCI input clock frequency
fSYSTEM MHz
5.38 USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 5-13 and Figure 5-14)
PARAMETER
TEST CONDITIONS
VCC
VIO
MIN
MAX UNIT
SMCLK or ACLK,
fUSCI
USCI input clock frequency
fSYSTEM
MHz
Duty cycle = 50% ±10%
PMMCOREV = 0
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
1.62 V to 1.80 V
1.62 V to 1.98 V
1.62 V to 1.98 V
1.62 V to 1.98 V
1.62 V to 1.80 V
1.62 V to 1.98 V
1.62 V to 1.98 V
1.62 V to 1.98 V
1.62 V to 1.80 V
55
55
35
35
0
tSU,MI
SOMI input data setup time
SOMI input data hold time
ns
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
0
tHD,MI
ns
ns
ns
0
0
UCLK edge to SIMO valid,
CL = 20 pF,
PMMCOREV = 0
20
20
16
16
3.0 V
2.4 V
3.0 V
1.62 V to 1.98 V
1.62 V to 1.98 V
1.62 V to 1.98 V
tVALID,MO
SIMO output data valid time(2)
SIMO output data hold time(3)
UCLK edge to SIMO valid,
CL = 20 pF,
PMMCOREV = 3
1.8 V
3.0 V
2.4 V
3.0 V
1.62 V to 1.80 V
1.62 V to 1.98 V
1.62 V to 1.98 V
1.62 V to 1.98 V
–10
–10
–10
–10
CL = 20 pF,
PMMCOREV = 0
tHD,MO
CL = 20 pF,
PMMCOREV = 3
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)
)
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-13 and Figure 5-14.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-
13 and Figure 5-14.
42
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1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
SIMO
tHD,MO
tVALID,MO
Figure 5-13. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLO/HI
tLO/HI
tHD,MI
tSU,MI
SOMI
SIMO
tHD,MO
tVALID,MO
Figure 5-14. SPI Master Mode, CKPH = 1
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Specifications
43
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5.39 USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 5-15 and Figure 5-16)
PARAMETER
TEST CONDITIONS
VCC
VIO
MIN
12
12
10
10
6
MAX UNIT
1.8 V 1.62 V to 1.80 V
3.0 V 1.62 V to 1.98 V
2.4 V 1.62 V to 1.98 V
3.0 V 1.62 V to 1.98 V
1.8 V 1.62 V to 1.80 V
3.0 V 1.62 V to 1.98 V
2.4 V 1.62 V to 1.98 V
3.0 V 1.62 V to 1.98 V
1.8 V 1.62 V to 1.80 V
3.0 V 1.62 V to 1.98 V
2.4 V 1.62 V to 1.98 V
3.0 V 1.62 V to 1.98 V
1.8 V 1.62 V to 1.80 V
3.0 V 1.62 V to 1.98 V
2.4 V 1.62 V to 1.98 V
3.0 V 1.62 V to 1.98 V
1.8 V 1.62 V to 1.80 V
3.0 V 1.62 V to 1.98 V
2.4 V 1.62 V to 1.98 V
3.0 V 1.62 V to 1.98 V
1.8 V 1.62 V to 1.80 V
3.0 V 1.62 V to 1.98 V
2.4 V 1.62 V to 1.98 V
3.0 V 1.62 V to 1.98 V
1.8 V 1.62 V to 1.80 V
PMMCOREV = 0
tSTE,LEAD STE lead time, STE low to clock
ns
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
6
tSTE,LAG
tSTE,ACC
tSTE,DIS
tSU,SI
STE lag time, Last clock to STE high
ns
6
6
65
65
ns
45
STE access time, STE low to SOMI
data out
45
35
35
ns
25
STE disable time, STE high to SOMI
high impedance
25
5
5
5
5
5
5
5
5
SIMO input data setup time
SIMO input data hold time
ns
tHD,SI
ns
UCLK edge to SOMI valid,
CL = 20 pF,
PMMCOREV = 0
75
75
3.0 V 1.62 V to 1.98 V
2.4 V 1.62 V to 1.98 V
3.0 V 1.62 V to 1.98 V
tVALID,SO SOMI output data valid time(2)
ns
UCLK edge to SOMI valid,
CL = 20 pF,
PMMCOREV = 3
50
50
1.8 V 1.62 V to 1.80 V
3.0 V 1.62 V to 1.98 V
2.4 V 1.62 V to 1.98 V
3.0 V 1.62 V to 1.98 V
18
18
10
10
CL = 20 pF,
PMMCOREV = 0
tHD,SO
SOMI output data hold time(3)
ns
CL = 20 pF,
PMMCOREV = 3
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)
)
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-15 and Figure 5-16.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-15
and Figure 5-16.
44
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tSU,SI
tLO/HI
tLO/HI
tHD,SI
SIMO
SOMI
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
Figure 5-15. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
SOMI
tHD,MO
tVALID,SO
tSTE,ACC
tSTE,DIS
Figure 5-16. SPI Slave Mode, CKPH = 1
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5.40 USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-17)
(1)
PARAMETER
TEST CONDITIONS
VCC
VIO
MIN
MAX UNIT
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
fUSCI
USCI input clock frequency
fSYSTEM
400
MHz
fSCL
SCL clock frequency
2.2 V, 3 V
2.2 V, 3 V
1.62 V to 1.98 V
1.62 V to 1.98 V
0
4.0
0.6
4.7
0.6
0
kHz
µs
f
SCL ≤ 100 kHz
fSCL > 100 kHz
SCL ≤ 100 kHz
fSCL > 100 kHz
tHD,STA
Hold time (repeated) START
f
tSU,STA
Setup time for a repeated START
2.2 V, 3 V
1.62 V to 1.98 V
µs
tHD,DAT
tSU,DAT
Data hold time
Data setup time
2.2 V, 3 V
2.2 V, 3 V
1.62 V to 1.98 V
1.62 V to 1.98 V
ns
ns
250
4.0
0.6
fSCL ≤ 100 kHz
tSU,STO
tSP
Setup time for STOP
2.2 V, 3 V
2.2 V, 3 V
1.62 V to 1.98 V
1.62 V to 1.98 V
µs
ns
fSCL > 100 kHz
Pulse duration of spikes
suppressed by input filter
50
600
(1) In all test conditions, VIO ≤ VCC
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-17. I2C Mode Timing
46
Specifications
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5.41 10-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
AVCC
V(Ax)
Analog supply voltage
1.8
3.6
V
V
All ADC10_A pins: P1.0 to P1.5 and P3.6 and
P3.7 terminals
Analog input voltage range(2)
0
AVCC
Operating supply current into
AVCC terminal, REF module
and reference buffer off
fADC10CLK = 5.0 MHz, ADC10ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC10DIV = 0, ADC10SREF = 00
2.2 V
3 V
60
75
100
110
Operating supply current into
AVCC terminal, REF module
on, reference buffer on
fADC10CLK = 5.0 MHz, ADC10ON = 1,
REFON = 1, SHT0 = 0, SHT1 = 0,
ADC10DIV = 0, ADC10SREF = 01
3 V
3 V
113
105
150
140
fADC10CLK = 5.0 MHz, ADC10ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC10DIV = 0, ADC10SREF = 10,
VEREF = 2.5 V
IADC10_A
µA
Operating supply current into
AVCC terminal, REF module
off, reference buffer on
fADC10CLK = 5.0 MHz, ADC10ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC10DIV = 0, ADC10SREF = 11,
VEREF = 2.5 V
Operating supply current into
AVCC terminal, REF module
off, reference buffer off
3 V
70
110
Only one terminal Ax can be selected at one
time from the pad to the ADC10_A capacitor
array including wiring and pad.
CI
RI
Input capacitance
2.2 V
3.5
pF
AVCC > 2 V, 0 V ≤ VAx ≤ AVCC
36
96
Input MUX ON resistance
kΩ
1.8 V < AVCC < 2 V, 0 V ≤ VAx ≤ AVCC
(1) The leakage current is defined in the leakage current table with P6.x/Ax parameter.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The external
reference voltage requires decoupling capacitors. See ()
.
5.42 10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
For specified performance of ADC10_A linearity
parameters
fADC10CLK
fADC10OSC
Input clock frequency
2.2 V, 3 V
0.45
5
5.5 MHz
Internal ADC10_A
oscillator(1)
ADC10DIV = 0, fADC10CLK = fADC10OSC
2.2 V, 3 V
2.2 V, 3 V
4.2
2.4
4.8
5.4 MHz
REFON = 0, Internal oscillator, 12 ADC10CLK
cycles, 10-bit mode,
fADC10OSC = 4 MHz to 5 MHz
3.0
µs
tCONVERT
Conversion time
External fADC10CLK from ACLK, MCLK or
12 ×
SMCLK, ADC10SSEL ≠ 0
1 / fADC10CLK
Turn on settling time of
the ADC
(2)
tADC10ON
tSample
See
100
ns
1.8 V
3.0 V
3
1
µs
µs
Sampling time
RS = 1000 Ω, RI = 96 k Ω, CI = 3.5 pF(3)
(1) The ADC10OSC is sourced directly from MODOSC inside the UCS.
(2) The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
(3) Approximately 8 Tau (τ) are needed to get an error of less than ±0.5 LSB
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Specifications
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MAX UNIT
5.43 10-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
1.4 V ≤ (VeREF+ – VeREF–) ≤ 1.6 V, CVeREF+ = 20 pF
1.6 V < (VeREF+ – VeREF–) ≤ VAVCC, CVeREF+ = 20 pF
±1.0
LSB
±1.0
Integral
linearity error
EI
2.2 V, 3 V
Differential
linearity error
ED
EO
EG
ET
1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
±1.0 LSB
±1.0 LSB
±1.0 LSB
±2.0 LSB
1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF
Internal impedance of source RS < 100 Ω
Offset error
Gain error
1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF,
ADC10SREFx = 11b
Total unadjusted
error
1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF,
ADC10SREFx = 11b
±1.0
5.44 REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Positive external
reference voltage input
(2)
VeREF+
VeREF+ > VeREF–
1.4
AVCC
1.2
V
V
V
Negative external
reference voltage input
(3)
(4)
VeREF–
VeREF+ > VeREF–
VeREF+ > VeREF–
0
(VeREF+
–
Differential external
reference voltage input
1.4
AVCC
VeREF–
)
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHz, ADC10SHTx = 0x0001,
Conversion rate = 200 ksps
2.2 V, 3 V
2.2 V, 3 V
–26
26
1
IVeREF+
IVeREF–
,
Static input current
µA
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHZ, ADC10SHTX = 0x1000,
Conversion rate = 20 ksps
–1
10
CVREF+
CVREF-
,
Capacitance at VeREF+
or VeREF- terminal
(5)
µF
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance (CI) is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC10_A. See also the MSP430F5xx and MSP430F6xx Family User's Guide.
48
Specifications
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5.45 REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
REFVSEL = {2} for 2.5 V, REFON = 1
REFVSEL = {1} for 2.0 V, REFON = 1
REFVSEL = {0} for 1.5 V, REFON = 1
REFVSEL = {0} for 1.5 V
VCC
3 V
MIN
2.472
1.96
TYP
2.51 2.548
1.99 2.02
MAX UNIT
Positive built-in reference
voltage
VREF+
3 V
V
V
2.2 V, 3 V
1.472 1.495 1.518
1.8
2.2
2.7
AVCC minimum voltage,
Positive built-in reference
active
AVCC(min)
REFVSEL = {1} for 2.0 V
REFVSEL = {2} for 2.5 V
fADC10CLK = 5.0 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {2} for 2.5 V
3 V
3 V
3 V
18
24
21
fADC10CLK = 5.0 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {1} for 2.0 V
Operating supply current
into AVCC terminal(2)
IREF+
15.5
µA
fADC10CLK = 5.0 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {0} for 1.5 V
13.5
30
21
50
Temperature coefficient of
built-in reference(3)
IVREF+ = 0 A,
REFVSEL = (0, 1, 2}, REFON = 1
ppm/
°C
TCREF+
ISENSOR
2.2 V
3 V
20
20
22
22
Operating supply current
into AVCC terminal(4)
REFON = 0, INCH = 0Ah,
ADC10ON = N A, TA = 30°C
µA
mV
V
2.2 V
3 V
770
770
1.1
1.5
ADC10ON = 1, INCH = 0Ah,
TA = 30°C
(5)
VSENSOR
See
2.2 V
3 V
1.06
1.46
1.14
1.54
ADC10ON = 1, INCH = 0Bh,
VMID
tSENSOR(sample)
tVMID(sample)
AVCC divider at channel 11
VMID ≈ 0.5 × VAVCC
Sample time required if
channel 10 is selected(6)
ADC10ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
30
1
µs
µs
Sample time required if
channel 11 is selected(7)
ADC10ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
AVCC = AVCC (min) to AVCC(max)
TA = 25°C,
,
Power supply rejection ratio
(DC)
PSRR_DC
120
µV/V
REFVSEL = {0, 1, 2}, REFON = 1
AVCC = AVCC (min) to AVCC(max)
,
Power supply rejection ratio
(AC)
PSRR_AC
tSETTLE
TA = 25°C, f = 1 kHz, ΔVpp = 100 mV
REFVSEL = {0, 1, 2}, REFON = 1
6.4
75
mV/V
µs
Settling time of reference
voltage(8)
AVCC = AVCC (min) to AVCC(max)
REFVSEL = {0, 1, 2}, REFON = 0 → 1
(1) The leakage current is defined in the leakage current table with P6.x/Ax parameter.
(2) The internal reference current is supplied from terminal AVCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an analog-to-digital conversion.
(3) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
(4) The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is already included in IREF+
.
(5) The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
(6) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
(7) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
(8) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
.
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MAX UNIT
5.46 Comparator_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
VCC
Supply voltage
1.8
3.6
38
38
39
V
1.8 V
2.2 V
3 V
CBPWRMD = 00, CBON = 1,
CBRSx = 00
31
32
Comparator operating supply
IAVCC_COMP current into AVCC, excludes
reference resistor ladder
µA
CBPWRMD = 01, CBON = 1,
CBRSx = 00
2.2 V,
3 V
10
17
CBPWRMD = 10, CBON = 1,
CBRSx = 00
2.2 V,
3 V
0.2
0.85
CBREFLx = 01, CBREFACC = 0
CBREFLx = 10, CBREFACC = 0
CBREFLx = 11, CBREFACC = 0
≥ 1.8 V
≥ 2.2 V
≥ 3.0 V
1.44
1.92
2.39
±2.5%
±2.5%
±2.5%
VREF
Reference voltage level
V
CBREFACC = 1, CBREFLx = 01,
CBRSx = 10, REFON = 0, CBON = 0
2.2 V,
3 V
17
33
22
40
Quiescent current of resistor
ladder into AVCC, including
REF module current
IAVCC_REF
µA
CBREFACC = 0, CBREFLx = 01,
CBRSx = 10, REFON = 0, CBON = 0
2.2 V,
3 V
VIC
Common mode input range
Input offset voltage
0
–20
–10
VCC – 1
20
V
CBPWRMD = 00
VOFFSET
CIN
mV
CBPWRMD = 01 or 10
10
Input capacitance
5
3
pF
kΩ
On (switch closed)
4
RSIN
Series input resistance
Off (switch open)
50
MΩ
CBPWRMD = 00, CBF = 0
CBPWRMD = 01, CBF = 0
CBPWRMD = 10, CBF = 0
450
600
50
ns
µs
Propagation delay, response
time
tPD
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 00
0.35
0.6
0.6
1.0
1.8
3.4
1
1.5
1.8
3.4
6.5
2
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 01
Propagation delay with filter
active
tPD,filter
µs
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 10
1.0
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 11
1.8
CBON = 0 → 1, CBPWRMD = 00 or
01
tEN_CMP
Comparator enable time
µs
µs
CBON = 0 → 1, CBPWRMD = 10
100
1.5
tEN_REF
Resistor reference enable time CBON = 0 → 1
1.0
Temperature coefficient
reference of VCB_REF
ppm/
°C
TCCB_REF
50
VIN
(n + 0.5)
/ 32
×
VIN
(n + 1) (n + 1.5)
/ 32 / 32
×
VIN ×
Reference voltage for a given
tap
VIN = reference into resistor ladder,
n = 0 to 31
VCB_REF
V
50
Specifications
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5.47 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TJ
MIN
TYP
MAX UNIT
DVCC(PGM/ERASE) Program and erase supply voltage
1.8
3.6
5
V
mA
IPGM
Average supply current from DVCC during program
3
6
6
IERASE
Average supply current from DVCC during erase
Average supply current from DVCC during mass erase or bank erase
Cumulative program time(1)
11
11
16
mA
IMERASE, IBANK
tCPT
mA
ms
Program and erase endurance
104
100
64
105
cycles
years
µs
tRetention
tWord
Data retention duration
Word or byte program time(2)
Block program time for first byte or word(2)
25°C
85
65
tBlock, 0
49
µs
Block program time for each additional byte or word, except for last byte or
word(2)
tBlock, 1–(N–1)
37
49
µs
tBlock, N
tErase
Block program time for last byte or word(2)
Erase time for segment, mass erase, and bank erase when available(2)
55
23
73
32
µs
ms
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
fMCLK,MGR
0
1
MHz
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word or byte write mode and block write mode.
(2) These values are hardwired into the state machine of the flash controller.
5.48 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
VIO
MIN
TYP
MAX UNIT
1.62 V to
1.98 V
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3 V
0
20
15
1
MHz
µs
1.62 V to
1.98 V
tSBW,Low Spy-Bi-Wire low clock pulse duration
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V
0.025
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
1.62 V to
1.98 V
tSBW, En
edge)(1)
µs
1.62 V to
1.98 V
tSBW,Rst
Spy-Bi-Wire return to normal operation time
TCK input frequency for 4-wire JTAG(2)
Internal pulldown resistance on TEST
15
0
100
5
µs
1.62 V to
1.98 V
fTCK
MHz
1.62 V to
1.98 V
3 V
0
10
80
1.62 V to
1.98 V
Rinternal
2.2 V, 3 V
45
60
kΩ
(1) Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
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5.49 DVIO BSL Entry
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tSU, BSLEN Setup time BSLEN to RST/NMI(1)
tHO, BSLEN Hold time BSLEN to RST/NMI(2)
VCC
VIO
MIN
100
350
MAX UNIT
2.2 V, 3 V 1.62 V to 1.98 V
2.2 V, 3 V 1.62 V to 1.98 V
ns
µs
(1) AVCC, DVCC, and DVIO stable and within specification.
(2) BSLEN must remain logic high long enough for the boot code to detect its level and enter the BSL sequence. After the minimum hold
time is achieved, BSLEN is a don't care.
BSLEN
VIT+
VIT-
tHO,BSLEN
VIT+
VIT-
RST/NMI
(DVIO domain)
t
tSU,BSLEN
Figure 5-18. DVIO BSL Entry Timing
52
Specifications
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6 Detailed Description
6.1 CPU (Link to user's guide)
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers (see Figure 6-1).
Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be handled
with all instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data.
Program Counter
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
Figure 6-1. CPU Registers
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Detailed Description
53
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6.2 Operating Modes
These MCUs have one active mode and six software selectable low-power modes of operation. An
interrupt event can wake up the device from any of the low-power modes, service the request, and restore
back to the low-power mode on return from the interrupt program.
Software can configure the following operating modes:
•
Active mode (AM)
All clocks are active
Low-power mode 0 (LPM0)
–
•
–
–
–
CPU is disabled
ACLK and SMCLK remain active, MCLK is disabled
FLL loop control remains active
•
•
Low-power mode 1 (LPM1)
–
–
–
CPU is disabled
FLL loop control is disabled
ACLK and SMCLK remain active, MCLK is disabled
Low-power mode 2 (LPM2)
–
–
–
–
CPU is disabled
MCLK, FLL loop control, and DCOCLK are disabled
DCO dc-generator remains enabled
ACLK remains active
•
•
Low-power mode 3 (LPM3)
–
–
–
–
CPU is disabled
MCLK, FLL loop control, and DCOCLK are disabled
DCO dc generator is disabled
ACLK remains active
Low-power mode 4 (LPM4)
–
–
–
–
–
–
CPU is disabled
ACLK is disabled
MCLK, FLL loop control, and DCOCLK are disabled
DCO dc generator is disabled
Crystal oscillator is stopped
Complete data retention
•
Low-power mode 4.5 (LPM4.5)
–
–
–
Internal regulator disabled
No data retention
Wake-up signal from RST/NMI, P1, and P2
54
Detailed Description
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6.3 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see
Table 6-1). The vector contains the 16-bit address of the appropriate interrupt-handler instruction
sequence.
Table 6-1. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
System Reset
Power up
External reset
Watchdog time-out, password
violation
WDTIFG, KEYV (SYSRSTIV)(1)(2)
Reset
0FFFEh
63, highest
Flash memory password violation
PMM password violation
System NMI
PMM
Vacant memory access
JTAG mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
JMBOUTIFG (SYSSNIV)(1)
(Non)maskable
(Non)maskable
0FFFCh
0FFFAh
62
61
User NMI
NMI
Oscillator fault
NMIIFG, OFIFG, ACCVIFG, BUSIFG
(SYSUNIV)(1)(2)
Flash memory access violation
COMP_B
TB0
Comparator B interrupt flags (CBIV)(1)(3)
Maskable
Maskable
0FFF8h
0FFF6h
60
59
(3)
TB0CCR0 CCIFG0
TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
TB0IFG (TB0IV)(1)(3)
TB0
Maskable
Maskable
0FFF4h
0FFF2h
58
57
Watchdog timer interval timer
mode
WDTIFG
USCI_A0 receive or transmit
USCI_B0 receive or transmit
ADC10_A
UCA0RXIFG, UCA0TXIFG (UCA0IV)(1)(3)
UCB0RXIFG, UCB0TXIFG (UCB0IV)(1)(3)
ADC10IFG0(1)(3)(4)
Maskable
Maskable
Maskable
Maskable
0FFF0h
0FFEEh
0FFECh
0FFEAh
56
55
54
53
TA0
TA0CCR0 CCIFG0(3)
TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0IFG (TA0IV)(1)(3)
TA0
Maskable
0FFE8h
52
Reserved
DMA
Reserved
Maskable
Maskable
Maskable
0FFE6h
0FFE4h
0FFE2h
51
50
49
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1)(3)
TA1CCR0 CCIFG0(3)
TA1
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG (TA1IV)(1)(3)
TA1
Maskable
0FFE0h
48
I/O Port P1
USCI_A1 receive or transmit
USCI_B1 receive or transmit
TA2
P1IFG.0 to P1IFG.7 (P1IV)(1)(3)
UCA1RXIFG, UCA1TXIFG (UCA1IV)(1)(3)
UCB1RXIFG, UCB1TXIFG (UCB1IV)(1)(3)
TA2CCR0 CCIFG0(3)
Maskable
Maskable
Maskable
Maskable
0FFDEh
0FFDCh
0FFDAh
0FFD8h
47
46
45
44
TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
TA2IFG (TA2IV)(1)(3)
TA2
Maskable
Maskable
Maskable
0FFD6h
0FFD4h
0FFD2h
43
42
41
I/O port P2
RTC_A
P2IFG.0 to P2IFG.7 (P2IV)(1)(3)
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG (RTCIV)(1)(3)
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(3) Interrupt flags are located in the module.
(4) Only on devices with ADC, otherwise reserved
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PRIORITY
Table 6-1. Interrupt Sources, Flags, and Vectors (continued)
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
0FFD0h
⋮
40
Reserved
Reserved(5)
⋮
0FF80h
0, lowest
(5) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, TI recommends reserving these locations.
6.4 Memory Organization
Table 6-2 summarizes the memory map.
Table 6-2. Memory Organization(1)
MSP430F5227
MSP430F5222
MSP430F5217
MSP430F5212
MSP430F5229
MSP430F5224
MSP430F5219
MSP430F5214
Memory (flash)
Main: interrupt vector
64KB
00FFFFh to 00FF80h
128KB
00FFFFh to 00FF80h
Total Size
Bank D
Bank C
Bank B
Bank A
Sector 3
Sector 2
Sector 1
Sector 0
A
32KB
0243FFh to 01C400h
N/A
N/A
32KB
01C3FFh to 014400h
Main: code memory
32KB
0143FFh to 00C400h
32KB
0143FFh to 00C400h
32KB
00C3FFh to 004400h
32KB
00C3FFh to 004400h
2KB
2KB
0043FFh to 003C00h
0043FFh to 003C00h
2KB
2KB
003BFFh to 003400h
003BFFh to 003400h
RAM
2KB
2KB
0033FFh to 002C00h
0033FFh to 002C00h
2KB
2KB
002BFFh to 002400h
002BFFh to 002400h
128 B
001BFFh to 001B80h
128 B
001BFFh to 001B80h
128 B
001B7Fh to 001B00h
128 B
001B7Fh to 001B00h
B
TI factory memory (ROM)
128 B
001AFFh to 001A80h
128 B
001AFFh to 001A80h
C
128 B
001A7Fh to 001A00h
128 B
001A7Fh to 001A00h
D
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
Info A
Info B
Info C
Info D
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
Information memory (flash)
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
(1) N/A = Not available
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Table 6-2. Memory Organization(1) (continued)
MSP430F5227
MSP430F5229
MSP430F5224
MSP430F5219
MSP430F5214
MSP430F5222
MSP430F5217
MSP430F5212
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
BSL 3
BSL 2
BSL 1
BSL 0
Size
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
Bootloader (BSL) memory (flash)
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
4KB
000FFFh to 0h
4KB
000FFFh to 0h
Peripherals
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6.5 Bootloader (BSL)
The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the
device memory by the BSL is protected by an user-defined password. Because the F522x and F521x
have split I/O power domains, it is possible to interface with the BSL from either the DVCC or DVIO supply
domains. This is useful when the MSP430 is interfacing to a host on the DVIO supply domain. The BSL
interface on the DVIO supply domain (see Table 6-3) uses the USCI_A0 module configured as a UART.
The BSL interface on the DVCC supply domain (see Table 6-4) uses a timer-based UART.
NOTE
Devices from TI come factory programmed with the timer-based UART BSL only. If the
USCI-based BSL is preferred, it is also available, but it must be programmed by the user.
When using the DVIO supply domain for the BSL, entry to the BSL requires a specific sequence on the
RST/NMI and BSLEN pins. Table 6-3 shows the required pins and their functions. For further details on
interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide.
For a complete description of the features of the BSL and its implementation, see the MSP430 Flash
Device Bootloader (BSL) User's Guide. The BSL on the DVIO supply domain uses the USCI_A0 module
configured as a UART.
NOTE
To invoke the BSL from the DVIO domain, the RST/NMI and BSLEN pins must be used for
the entry sequence (see Section 5.49). It is critical not to confuse the RST/NMI pin with the
RSTDVCC/SBWTDIO pin. In other MSP430 devices, SBWTDIO is shared with the RST/NMI
pin and RSTDVCC does not exist. Additional information can be found in Designing With
MSP430F522x and MSP430F521x Devices.
Table 6-3. DVIO BSL Pin Requirements and Functions
DEVICE SIGNAL
RST/NMI
BSLEN
BSL FUNCTION
External reset
Enable BSL
P3.3
Data transmit
P3.4
Data receive
DVCC, AVCC
DVIO
Device power supply
I/O power supply
Ground supply
DVSS
For applications in which it is desirable to have BSL communication based on the DVCC supply domain,
entry to the BSL requires a specific sequence on the RSTDVCC/SBWTDIO and TEST/SBWTCK pins.
Table 6-4 shows the required pins and their function.
NOTE
To invoke the BSL from the DVCC domain, the RSTDVCC/SBWTDIO and TEST/SBWTCK
pins must be used for the entry sequence. It is critical not to confuse the RST/NMI pin with
the RSTDVCC/SBWTDIO pin. In other MSP430 devices, SBWTDIO is shared with the
RST/NMI pin and RSTDVCC does not exist. Additional information can be found in
Designing With MSP430F522x and MSP430F521x Devices.
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Table 6-4. DVCC BSL Pin Requirements and Functions
DEVICE SIGNAL
RSTDVCC/SBWTDIO
TEST/SBWTCK
P1.1
BSL FUNCTION
External reset
Enable BSL
Data transmit
P1.2
Data receive
DVCC, AVCC
DVIO
Device power supply
I/O power supply
Ground supply
DVSS
6.6 JTAG Operation
6.6.1 JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RSTDVCC/SBWTDIO is required to interface
with MSP430 development tools and device programmers. The JTAG pin requirements are shown in
Table 6-5. For further details on interfacing to development tools and device programmers, see the
MSP430 Hardware Tools User's Guide. For a complete description of the features of the JTAG interface
and its implementation, see MSP430 Programming With the JTAG Interface. Additional information can be
found in Designing With MSP430F522x and MSP430F521x Devices.
NOTE
All JTAG I/O pins are supplied by DVCC.
NOTE
On other MSP430 devices, the RST/NMI pin has been used for SBWTDIO, so care must be
taken not to mistakenly use the incorrect pin. On the F522x and F521x series of devices,
RSTDVCC is used for SBWTDIO as shown in Table 6-5. Additional information can be found
in Designing With MSP430F522x and MSP430F521x Devices.
Table 6-5. JTAG Pin Requirements and Functions
DEVICE SIGNAL
PJ.3/TCK
DIRECTION
FUNCTION
JTAG clock input
JTAG state control
JTAG data input, TCLK input
JTAG data output
Enable JTAG pins
External reset
IN
IN
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
IN
OUT
IN
TEST/SBWTCK
RSTDVCC/SBWTDIO
DVCC, AVCC
DVIO
IN
Device power supply
I/O power supply
DVSS
Ground supply
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6.6.2 Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the 2-wire Spy-Bi-Wire interface.
Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-
Bi-Wire interface pin requirements are shown in Table 6-6. For further details on interfacing to
development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For a
complete description of the features of the JTAG interface and its implementation, see MSP430
Programming With the JTAG Interface.Additional information can be found in Designing With
MSP430F522x and MSP430F521x Devices.
NOTE
All SBW I/O pins are supplied by DVCC.
NOTE
On other MSP430 devices, the RST/NMI pin has been used for SBWTDIO, so care must be
taken not to mistakenly use the incorrect pin. On the F522x and F521x series of devices,
RSTDVCC is used for SBWTDIO as shown in Table 6-6. Additional information can be found
in Designing With MSP430F522x and MSP430F521x Devices.
Table 6-6. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RSTDVCC/SBWTDIO
DVCC, AVCC
DVIO
DIRECTION
IN
FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input/output
Device power supply
I/O power supply
IN, OUT
DVSS
Ground supply
6.7 Flash Memory (Link to user's guide)
The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system
by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory.
Features of the flash memory include:
•
Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
•
•
•
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually. Segments A to D are also called information memory.
Segment A can be locked separately.
6.8 RAM (Link to user's guide)
The RAM is made up of n sectors. Each sector can be completely powered down to reduce leakage;
however, all data is lost during power down. Features of the RAM include:
•
•
•
RAM has n sectors. The sizes of the sectors can be found in Section 6.4.
Each sector 0 to n can be complete disabled; however, all data in a sector is lost when it is disabled.
Each sector 0 to n automatically enters low-power retention mode when possible.
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6.9 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430F5xx and
MSP430F6xx Family User's Guide.
6.9.1 Digital I/O (Link to user's guide)
•
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Pullup or pulldown on all ports is programmable.
Drive strength on all ports is programmable.
Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1 and
P2.
•
•
Read and write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise or word-wise in pairs.
6.9.2 Port Mapping Controller (Link to user's guide)
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4.
Table 6-7 lists the valid settings.
Table 6-7. Port Mapping Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
PM_NONE
INPUT PIN FUNCTION
None
OUTPUT PIN FUNCTION
DVSS
0
PM_CBOUT0
–
COMP_B output
1
2
3
PM_TB0CLK
TB0 clock input
–
PM_ADC10CLK
PM_DMAE0
–
ADC10CLK
DMAE0 input
–
PM_SVMOUT
PM_TB0OUTH
PM_TB0CCR0A
PM_TB0CCR1A
PM_TB0CCR2A
PM_TB0CCR3A
PM_TB0CCR4A
PM_TB0CCR5A
PM_TB0CCR6A
PM_UCA1RXD
PM_UCA1SOMI
PM_UCA1TXD
PM_UCA1SIMO
PM_UCA1CLK
PM_UCB1STE
PM_UCB1SOMI
PM_UCB1SCL
PM_UCB1SIMO
PM_UCB1SDA
PM_UCB1CLK
PM_UCA1STE
PM_CBOUT1
–
SVM output
TB0 high-impedance input TB0OUTH
TB0 CCR0 capture input CCI0A
TB0 CCR1 capture input CCI1A
TB0 CCR2 capture input CCI2A
TB0 CCR3 capture input CCI3A
TB0 CCR4 capture input CCI4A
TB0 CCR5 capture input CCI5A
TB0 CCR6 capture input CCI6A
–
4
5
TB0 CCR0 compare output Out0
TB0 CCR1 compare output Out1
TB0 CCR2 compare output Out2
TB0 CCR3 compare output Out3
TB0 CCR4 compare output Out4
TB0 CCR5 compare output Out5
TB0 CCR6 compare output Out6
6
7
8
9
10
USCI_A1 UART RXD (direction controlled by USCI – input)
USCI_A1 SPI slave out master in (direction controlled by USCI)
USCI_A1 UART TXD (direction controlled by USCI – output)
USCI_A1 SPI slave in master out (direction controlled by USCI)
USCI_A1 clock input/output (direction controlled by USCI)
USCI_B1 SPI slave transmit enable (direction controlled by USCI)
USCI_B1 SPI slave out master in (direction controlled by USCI)
USCI_B1 I2C clock (open drain and direction controlled by USCI)
USCI_B1 SPI slave in master out (direction controlled by USCI)
USCI_B1 I2C data (open drain and direction controlled by USCI)
USCI_B1 clock input/output (direction controlled by USCI)
USCI_A1 SPI slave transmit enable (direction controlled by USCI)
11
12
13
14
15
16
17
18
None
None
COMP_B output
MCLK
PM_MCLK
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Table 6-7. Port Mapping Mnemonics and Functions (continued)
VALUE
PxMAPy MNEMONIC
PM_RTCCLK
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
RTCCLK output
19
None
PM_UCA0RXD
PM_UCA0SOMI
PM_UCA0TXD
PM_UCA0SIMO
PM_UCA0CLK
PM_UCB0STE
PM_UCB0SOMI
PM_UCB0SCL
PM_UCB0SIMO
PM_UCB0SDA
PM_UCB0CLK
PM_UCA0STE
Reserved
USCI_A0 UART RXD (direction controlled by USCI - input)
USCI_A0 SPI slave out master in (direction controlled by USCI)
USCI_A0 UART TXD (direction controlled by USCI - output)
USCI_A0 SPI slave in master out (direction controlled by USCI)
USCI_A0 clock input/output (direction controlled by USCI)
USCI_B0 SPI slave transmit enable (direction controlled by USCI)
USCI_B0 SPI slave out master in (direction controlled by USCI)
USCI_B0 I2C clock (open drain and direction controlled by USCI)
USCI_B0 SPI slave in master out (direction controlled by USCI)
USCI_B0 I2C data (open drain and direction controlled by USCI)
USCI_B0 clock input/output (direction controlled by USCI)
USCI_A0 SPI slave transmit enable (direction controlled by USCI)
20
21
22
23
24
25
26 - 30
None
DVSS
Disables the output driver and the input Schmitt trigger to prevent parasitic
cross currents when applying analog signals
31 (0FFh)(1)
PM_ANALOG
(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored,
resulting in a read out value of 31.
Table 6-8. Default Mapping
PIN
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
USCI_B1 SPI slave transmit enable (direction controlled by USCI)
USCI_A1 clock input/output (direction controlled by USCI)
P4.0/P4MAP0
PM_UCB1STE/PM_UCA1CLK
USCI_B1 SPI slave in master out (direction controlled by USCI)
USCI_B1 I2C data (open drain and direction controlled by USCI)
P4.1/P4MAP1
P4.2/P4MAP2
P4.3/P4MAP3
P4.4/P4MAP4
P4.5/P4MAP5
PM_UCB1SIMO/PM_UCB1SDA
PM_UCB1SOMI/PM_UCB1SCL
PM_UCB1CLK/PM_UCA1STE
PM_UCA1TXD/PM_UCA1SIMO
PM_UCA1RXD/PM_UCA1SOMI
USCI_B1 SPI slave out master in (direction controlled by USCI)
USCI_B1 I2C clock (open drain and direction controlled by USCI)
USCI_A1 SPI slave transmit enable (direction controlled by USCI)
USCI_B1 clock input/output (direction controlled by USCI)
USCI_A1 UART TXD (Direction controlled by USCI - output)
USCI_A1 SPI slave in master out (direction controlled by USCI)
USCI_A1 UART RXD (Direction controlled by USCI - input)
USCI_A1 SPI slave out master in (direction controlled by USCI)
P4.6/P4MAP6
P4.7/P4MAP7(1)
PM_NONE
PM_NONE
None
None
DVSS
DVSS
(1) Not available on all devices
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6.9.3 Oscillator and System Clock (Link to user's guide)
The clock system in the MSP430F522x and MSP430F521x family of devices is supported by the Unified
Clock System (UCS) module, which includes support for a 32-kHz watch crystal oscillator (XT1 LF mode)
(XT1 HF mode is not supported), an internal very-low-power low-frequency oscillator (VLO), an internal
trimmed low-frequency oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a
high-frequency crystal oscillator (XT2). The UCS module is designed to meet the requirements of both low
system cost and low power consumption. The UCS module features digital frequency locked loop (FLL)
hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable
multiple of the selected FLL reference frequency. The internal DCO provides a fast turnon clock source
and stabilizes in 3.5 µs (typical). The UCS module provides the following clock signals:
•
Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the
internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal
digitally controlled oscillator DCO.
•
•
•
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources made available to ACLK.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
6.9.4 Power-Management Module (PMM) (Link to user's guide)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and
contains programmable output levels to provide for power optimization. The PMM also includes supply
voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, and brownout protection. The
brownout circuit is implemented to provide the proper internal reset signal to the device during power-on
and power-off. The SVS and SVM circuitry detects if the supply voltage drops below a user-selectable
level and supports both supply voltage supervision (the device is automatically reset) and supply voltage
monitoring (the device is not automatically reset). SVS and SVM circuitry is available on the primary
supply and core supply.
6.9.5 Hardware Multiplier (Link to user's guide)
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication
as well as signed and unsigned multiply-and-accumulate operations.
6.9.6 Real-Time Clock (RTC_A) (Link to user's guide)
The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated
real-time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit
timers that can be cascaded to form a 16-bit timer or counter. Both timers can be read and written by
software. Calendar mode integrates an internal calendar that compensates for months with less than
31 days and includes leap year correction. The RTC_A also supports flexible alarm functions and offset-
calibration hardware.
6.9.7 Watchdog Timer (WDT_A) (Link to user's guide)
The primary function of the WDT_A module is to perform a controlled system restart after a software
problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function
is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
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6.9.8 System Module (SYS) (Link to user's guide)
The SYS module handles many of the system functions within the device. These include power-on reset
(POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector
generators, bootloader (BSL) entry mechanisms, and configuration management (device descriptors). It
also includes a data exchange mechanism when using JTAG that is called a JTAG mailbox and that can
be used in the application. Table 6-9 lists the SYS module interrupt vector registers.
Table 6-9. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER
ADDRESS
INTERRUPT EVENT
No interrupt pending
Brownout (BOR)
RST/NMI (BOR)
PMMSWBOR (BOR)
Wakeup from LPMx.5
Security violation (BOR)
SVSL (POR)
VALUE
00h
PRIORITY
02h
Highest
04h
06h
08h
0Ah
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
SVMH_OVP (POR)
PMMSWPOR (POR)
WDT time-out (PUC)
WDT password violation (PUC)
KEYV flash password violation (PUC)
Reserved
10h
SYSRSTIV, System Reset
019Eh
12h
14h
16h
18h
1Ah
1Ch
Peripheral area fetch (PUC)
PMM password violation (PUC)
Reserved
1Eh
20h
22h to 3Eh
00h
Lowest
Highest
No interrupt pending
SVMLIFG
02h
SVMHIFG
04h
SVSMLDLYIFG
SVSMHDLYIFG
VMAIFG
06h
08h
SYSSNIV, System NMI
019Ch
0Ah
JMBINIFG
0Ch
JMBOUTIFG
0Eh
SVMLVLRIFG
10h
SVMHVLRIFG
12h
Reserved
14h to 1Eh
00h
Lowest
Highest
No interrupt pending
NMIIFG
02h
OFIFG
04h
SYSUNIV, User NMI
019Ah
ACCVIFG
06h
Reserved
08h
Reserved
0Ah to 1Eh
Lowest
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6.9.9 DMA Controller (Link to user's guide)
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC10_A conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral. Table 6-10 lists the trigger assignments.
Table 6-10. DMA Trigger Assignments(1)
CHANNEL
TRIGGER
0
1
2
0
DMAREQ
DMAREQ
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA2CCR2 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA2CCR2 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA2CCR2 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
Reserved
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB1RXIFG
UCB1TXIFG
ADC10IFG0(2)
Reserved
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB1RXIFG
UCB1TXIFG
ADC10IFG0(2)
Reserved
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB1RXIFG
UCB1TXIFG
ADC10IFG0(2)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MPY ready
MPY ready
MPY ready
DMA2IFG
DMA0IFG
DMA1IFG
DMAE0
DMAE0
DMAE0
(1) If a reserved trigger source is selected, no trigger is generated.
(2) Only on devices with ADC; reserved on devices without ADC
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6.9.10 Universal Serial Communication Interface (USCI) (Links to user's guide: UART
Mode, SPI Mode, I2C Mode)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3- or 4-pin) and I2C, and asynchronous communication protocols
such as UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module
contains two portions, A and B.
The USCI_An module provides support for SPI (3- or 4-pin), UART, enhanced UART, or IrDA.
The USCI_Bn module provides support for SPI (3- or 4-pin) or I2C.
The MSP430F522x and MSP430F521x series include two complete USCI modules (n = 0, 1).
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6.9.11 TA0 (Link to user's guide)
TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 can support multiple
captures or compares, PWM outputs, and interval timing (see Table 6-11). TA0 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
Table 6-11. TA0 Signal Connections
INPUT PIN NUMBER
OUTPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
MODULE
BLOCK
RGC, ZQE,
RGZ
RGC, ZQE, YFF
RGZ
YFF
18, H2, B7-
13-P1.0
P1.0
TA0CLK
TACLK
ACLK
ACLK
(internal)
Timer
NA
NA
SMCLK
(internal)
SMCLK
TACLK
CCI0A
18, H2, B7-
13-P1.0
P1.0
TA0CLK
TA0.0
19, H3, C7-
14-P1.1
P1.1
19, H3, C7-P1.1
20, J3, C8-P1.2
14-P1.1
15-P1.2
DVSS
DVSS
DVCC
CCI0B
GND
VCC
CCR0
CCR1
TA0
TA1
TA0.0
TA0.1
20, J3, C8-
15-P1.2
P1.2
TA0.1
CCI1A
ADC10 (internal) ADC10 (internal)
ADC10SHSx =
{1}
CBOUT
(internal)
CCI1B
ADC10SHSx =
{1}
DVSS
DVCC
GND
VCC
21, G4, C6-
16-P1.3
P1.3
TA0.2
CCI2A
CCI2B
21, G4, C6-P1.3
16-P1.3
ACLK
(internal)
CCR2
TA2
TA0.2
DVSS
DVCC
GND
VCC
22, H4, C5-
17-P1.4
P1.4
TA0.3
CCI3A
22, H4, C5-P1.4
23, J4, D8-P1.5
17-P1.4
18-P1.5
DVSS
DVSS
DVCC
CCI3B
GND
VCC
CCR3
CCR4
TA3
TA4
TA0.3
TA0.4
23, J4, D8-
18-P1.5
P1.5
TA0.4
CCI4A
DVSS
DVSS
DVCC
CCI4B
GND
VCC
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6.9.12 TA1 (Link to user's guide)
TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 can support
multiple captures or compares, PWM outputs, and interval timing (see Table 6-12). TA1 also has
extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and
from each of the capture/compare registers.
Table 6-12. TA1 Signal Connections
INPUT PIN NUMBER
OUTPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
MODULE
BLOCK
RGC, ZQE,
RGZ
RGC, ZQE,
RGZ
YFF
YFF
24, G5, D7-
19-P1.6
P1.6
TA1CLK
TACLK
ACLK
ACLK
(internal)
Timer
NA
NA
SMCLK
(internal)
SMCLK
TACLK
CCI0A
24, G5, D7-
19-P1.6
P1.6
TA1CLK
TA1.0
25, H5, D6-
20-P1.7
P1.7
25, H5, D6-
20-P1.7
P1.7
DVSS
DVSS
DVCC
CCI0B
GND
VCC
CCR0
CCR1
TA0
TA1
TA1.0
TA1.1
26, J5, E8-
P2.0
26, J5, E8-
P2.0
TA1.1
CCI1A
CCI1B
CBOUT
(internal)
DVSS
DVCC
GND
VCC
27, G6, D5-
P2.1
27, G6, D5-
P2.1
TA1.2
CCI2A
CCI2B
ACLK
(internal)
CCR2
TA2
TA1.2
DVSS
DVCC
GND
VCC
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6.9.13 TA2 (Link to user's guide)
TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA2 can support
multiple captures or compares, PWM outputs, and interval timing (see Table 6-13). TA2 also has
extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and
from each of the capture/compare registers.
Table 6-13. TA2 Signal Connections
INPUT PIN NUMBER
OUTPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
MODULE
BLOCK
RGC, ZQE,
RGZ
RGC, ZQE,
RGZ
YFF
YFF
28, J6, E7-
P2.2
TA2CLK
TACLK
ACLK
ACLK
(internal)
Timer
NA
NA
SMCLK
(internal)
SMCLK
TACLK
CCI0A
28, J6, E7-
P2.2
TA2CLK
TA2.0
29, H6, F8-
P2.3
29, H6, F8-
P2.3
DVSS
DVSS
DVCC
CCI0B
GND
VCC
CCR0
CCR1
TA0
TA1
TA2.0
TA2.1
30, J7, E6-
P2.4
30, J7, E6-
P2.4
TA2.1
CCI1A
CCI1B
CBOUT
(internal)
DVSS
DVCC
GND
VCC
31, J8, F7-
P2.5
31, J8, F7-
P2.5
TA2.2
CCI2A
CCI2B
ACLK
(internal)
CCR2
TA2
TA2.2
DVSS
DVCC
GND
VCC
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6.9.14 TB0 (Link to user's guide)
TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. TB0 can support
multiple captures or compares, PWM outputs, and interval timing (see Table 6-14). TB0 also has
extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and
from each of the capture/compare registers.
Table 6-14. TB0 Signal Connections
INPUT PIN NUMBER
OUTPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
MODULE
BLOCK
RGC, ZQE,
RGZ
RGC, ZQE, YFF
RGZ
YFF
(1)
(1)
TB0CLK
TBCLK
ACLK
ACLK
(internal)
Timer
CCR0
CCR1
CCR2
CCR3
CCR4
NA
NA
SMCLK
(internal)
SMCLK
TBCLK
CCI0A
(1)
(1)
(1)
TB0CLK
TB0.0
49, B8(9), H1-
P7.0(1)
49, B8(9), H1-
P7.0(1)
(1)
49, B8(9), H1-
P7.0(1)
ADC10 (internal)
ADC10SHSx = {2}
ADC10 (internal)
ADC10SHSx = {2}
(1)
TB0.0
CCI0B
TB0
TB1
TB2
TB3
TB4
TB0.0
TB0.1
TB0.2
TB0.3
TB0.4
DVSS
DVCC
GND
VCC
50, A9, G2-
P7.1(1)
(1)
(1)
TB0.1
CCI1A
CCI1B
50, A9, G2-P7.1(1)
CBOUT
(internal)
ADC10 (internal)
ADC10SHSx = {3}
ADC10 (internal)
ADC10SHSx = {3}
DVSS
DVCC
GND
VCC
51, B7, F3-
P7.2(1)
(1)
(1)
(1)
(1)
(1)
TB0.2
TB0.2
CCI2A
CCI2B
51, B7, F3-P7.2(1)
52, A8, G1-P7.3(1)
53, A7, F2-P7.4(1)
51, B7, F3-
P7.2(1)
DVSS
DVCC
GND
VCC
52, A8, G1-
P7.3(1)
(1)
(1)
TB0.3
TB0.3
CCI3A
CCI3B
52, A8, G1-
P7.3(1)
DVSS
DVCC
GND
VCC
53, A7, F2-
P7.4(1)
(1)
(1)
TB0.4
TB0.4
CCI4A
CCI4B
53, A7, F2-
P7.4(1)
DVSS
DVCC
GND
VCC
54, A6, F1-
P7.5(1)
(1)
(1)
(1)
TB0.5
TB0.5
CCI5A
CCI5B
54, A6, F1-P7.5(1)
54, A6, F1-
P7.5(1)
CCR5
CCR6
TB5
TB6
TB0.5
TB0.6
DVSS
DVCC
TB0.6
GND
VCC
(1)
(1)
(1)
(1)
CCI6A
ACLK
(internal)
CCI6B
DVSS
DVCC
GND
VCC
(1) Timer functions can be assigned by the port mapping controller.
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6.9.15 Comparator_B (Link to user's guide)
The primary function of the Comparator_B module is to support precision slope analog-to-digital
conversions, battery voltage supervision, and monitoring of external analog signals.
6.9.16 ADC10_A (Link to user's guide)
The ADC10_A module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit
SAR core, sample select control, reference generator, and a conversion result buffer. A window
comparator with lower and upper limits allows CPU-independent result monitoring with three window
comparator interrupt flags.
6.9.17 CRC16 (Link to user's guide)
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
6.9.18 REF Voltage Reference (Link to user's guide)
The REF is responsible for generation of all critical reference voltages that can be used by the various
analog peripherals in the device.
6.9.19 Embedded Emulation Module (EEM) (S Version) (Link to user's guide)
The EEM supports real-time in-system debugging. The S version of the EEM has the following features:
•
•
•
•
•
Three hardware triggers or breakpoints on memory access
One hardware trigger or breakpoint on CPU register write access
Up to four hardware triggers can be combined to form complex triggers or breakpoints
One cycle counter
Clock control on module level
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6.9.20 Peripheral File Map
Table 6-15 lists the base address for the registers of each peripheral.
Table 6-15. Peripherals
OFFSET ADDRESS
RANGE
MODULE NAME
BASE ADDRESS
Special Functions (see Table 6-16)
PMM (see Table 6-17)
0100h
0120h
0140h
0150h
0158h
015Ch
0160h
0180h
01B0h
01C0h
01E0h
0200h
0220h
0240h
0260h
0320h
0340h
0380h
03C0h
0400h
04A0h
04C0h
0500h
0510h
0520h
0530h
05C0h
05E0h
0600h
0620h
0740h
08C0h
000h-01Fh
000h-010h
000h-00Fh
000h-007h
000h-001h
000h-001h
000h-01Fh
000h-01Fh
000h-001h
000h-002h
000h-007h
000h-01Fh
000h-00Bh
000h-00Bh
000h-00Bh
000h-01Fh
000h-02Eh
000h-02Eh
000h-02Eh
000h-02Eh
000h-01Bh
000h-02Fh
000h-00Fh
000h-00Ah
000h-00Ah
000h-00Ah
000h-01Fh
000h-01Fh
000h-01Fh
000h-01Fh
000h-01Fh
000h-00Fh
Flash Control (see Table 6-18)
CRC16 (see Table 6-19)
RAM Control (see Table 6-20)
Watchdog (see Table 6-21)
UCS (see Table 6-22)
SYS (see Table 6-23)
Shared Reference (see Table 6-24)
Port Mapping Control (see Table 6-25)
Port Mapping Port P4 (see Table 6-25)
Port P1, P2 (see Table 6-26)
Port P3, P4 (see Table 6-27)
Port P5, P6 (see Table 6-28)
Port P7 (see Table 6-29)
Port PJ (see Table 6-30)
TA0 (see Table 6-31)
TA1 (see Table 6-32)
TB0 (see Table 6-33)
TA2 (see Table 6-34)
Real-Time Clock (RTC_A) (see Table 6-35)
32-Bit Hardware Multiplier (see Table 6-36)
DMA General Control (see Table 6-37)
DMA Channel 0 (see Table 6-37)
DMA Channel 1 (see Table 6-37)
DMA Channel 2 (see Table 6-37)
USCI_A0 (see Table 6-38)
USCI_B0 (see Table 6-39)
USCI_A1 (see Table 6-40)
USCI_B1 (see Table 6-41)
ADC10_A (see Table 6-42)
Comparator_B (see Table 6-43)
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Table 6-16. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
SFRIE1
OFFSET
SFR interrupt enable
SFR interrupt flag
00h
02h
04h
SFRIFG1
SFR reset pin control
SFRRPCR
Table 6-17. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
PMMCTL0
OFFSET
PMM control 0
00h
02h
04h
06h
0Ch
0Eh
10h
PMM control 1
PMMCTL1
SVSMHCTL
SVSMLCTL
PMMIFG
SVS high-side control
SVS low-side control
PMM interrupt flags
PMM interrupt enable
PMM power mode 5 control
PMMIE
PM5CTL0
Table 6-18. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Flash control 1
Flash control 3
Flash control 4
FCTL1
FCTL3
FCTL4
00h
04h
06h
Table 6-19. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
CRC16DI
OFFSET
CRC data input
00h
02h
04h
06h
CRC data input reverse byte
CRC initialization and result
CRC result reverse byte
CRCDIRB
CRCINIRES
CRCRESR
Table 6-20. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
REGISTER
RCCTL0
OFFSET
OFFSET
OFFSET
RAM control 0
00h
00h
Table 6-21. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
REGISTER
WDTCTL
Watchdog timer control
Table 6-22. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
UCSCTL0
UCS control 0
UCS control 1
UCS control 2
UCS control 3
UCS control 4
UCS control 5
UCS control 6
UCS control 7
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
UCSCTL1
UCSCTL2
UCSCTL3
UCSCTL4
UCSCTL5
UCSCTL6
UCSCTL7
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Table 6-22. UCS Registers (Base Address: 0160h) (continued)
REGISTER DESCRIPTION
REGISTER
UCSCTL8
UCSCTL9
OFFSET
UCS control 8
UCS control 9
10h
12h
Table 6-23. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
SYSCTL
OFFSET
System control
00h
02h
06h
08h
0Ah
0Ch
0Eh
1Ah
1Ch
1Eh
Bootloader configuration area
JTAG mailbox control
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
User NMI vector generator
System NMI vector generator
Reset vector generator
SYSBSLC
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSUNIV
SYSSNIV
SYSRSTIV
Table 6-24. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
REGISTER
REFCTL
OFFSET
OFFSET
Shared reference control
00h
Table 6-25. Port Mapping Registers
(Base Address of Port Mapping Control: 01C0h, Port P4: 01E0h)
REGISTER DESCRIPTION
REGISTER
PMAPKEYID
Port mapping key/ID
Port mapping control
Port P4.0 mapping
Port P4.1 mapping
Port P4.2 mapping
Port P4.3 mapping
Port P4.4 mapping
Port P4.5 mapping
Port P4.6 mapping
Port P4.7 mapping
00h
02h
00h
01h
02h
03h
04h
05h
06h
07h
PMAPCTL
P4MAP0
P4MAP1
P4MAP2
P4MAP3
P4MAP4
P4MAP5
P4MAP6
P4MAP7
Table 6-26. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
02h
04h
06h
08h
0Ah
0Eh
18h
1Ah
1Ch
Port P1 output
P1OUT
P1DIR
P1REN
P1DS
P1SEL
P1IV
Port P1 direction
Port P1 resistor enable
Port P1 drive strength
Port P1 selection
Port P1 interrupt vector word
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
P1IES
P1IE
P1IFG
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Table 6-26. Port P1, P2 Registers (Base Address: 0200h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P2 input
P2IN
01h
03h
05h
07h
09h
0Bh
1Eh
19h
1Bh
1Dh
Port P2 output
P2OUT
P2DIR
P2REN
P2DS
P2SEL
P2IV
Port P2 direction
Port P2 resistor enable
Port P2 drive strength
Port P2 selection
Port P2 interrupt vector word
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
P2IES
P2IE
P2IFG
Table 6-27. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
02h
04h
06h
08h
0Ah
01h
03h
05h
07h
09h
0Bh
Port P3 output
P3OUT
P3DIR
P3REN
P3DS
Port P3 direction
Port P3 resistor enable
Port P3 drive strength
Port P3 selection
Port P4 input
P3SEL
P4IN
Port P4 output
P4OUT
P4DIR
P4REN
P4DS
Port P4 direction
Port P4 resistor enable
Port P4 drive strength
Port P4 selection
P4SEL
Table 6-28. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
02h
04h
06h
08h
0Ah
01h
03h
05h
07h
09h
0Bh
Port P5 output
P5OUT
P5DIR
P5REN
P5DS
Port P5 direction
Port P5 resistor enable
Port P5 drive strength
Port P5 selection
Port P6 input
P5SEL
P6IN
Port P6 output
P6OUT
P6DIR
P6REN
P6DS
Port P6 direction
Port P6 resistor enable
Port P6 drive strength
Port P6 selection
P6SEL
Table 6-29. Port P7 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 input
P7IN
00h
02h
04h
Port P7 output
Port P7 direction
P7OUT
P7DIR
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Table 6-29. Port P7 Registers (Base Address: 0260h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 resistor enable
Port P7 drive strength
Port P7 selection
P7REN
P7DS
06h
08h
0Ah
P7SEL
Table 6-30. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
02h
04h
06h
08h
Port PJ output
PJOUT
PJDIR
PJREN
PJDS
Port PJ direction
Port PJ resistor enable
Port PJ drive strength
Table 6-31. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
TA0CTL
OFFSET
TA0 control
00h
02h
04h
06h
08h
0Ah
10h
12h
14h
16h
18h
1Ah
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Capture/compare control 3
Capture/compare control 4
TA0 counter
TA0CCTL0
TA0CCTL1
TA0CCTL2
TA0CCTL3
TA0CCTL4
TA0R
Capture/compare 0
Capture/compare 1
Capture/compare 2
Capture/compare 3
Capture/compare 4
TA0 expansion 0
TA0CCR0
TA0CCR1
TA0CCR2
TA0CCR3
TA0CCR4
TA0EX0
TA0 interrupt vector
TA0IV
Table 6-32. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
TA1CTL
OFFSET
TA1 control
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA1 counter
TA1CCTL0
TA1CCTL1
TA1CCTL2
TA1R
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA1 expansion 0
TA1CCR0
TA1CCR1
TA1CCR2
TA1EX0
TA1 interrupt vector
TA1IV
Table 6-33. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
TB0CTL
TB0CCTL0
OFFSET
TB0 control
00h
02h
Capture/compare control 0
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Table 6-33. TB0 Registers (Base Address: 03C0h) (continued)
REGISTER DESCRIPTION
REGISTER
TB0CCTL1
OFFSET
Capture/compare control 1
Capture/compare control 2
Capture/compare control 3
Capture/compare control 4
Capture/compare control 5
Capture/compare control 6
TB0 counter
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Eh
TB0CCTL2
TB0CCTL3
TB0CCTL4
TB0CCTL5
TB0CCTL6
TB0R
Capture/compare 0
TB0CCR0
TB0CCR1
TB0CCR2
TB0CCR3
TB0CCR4
TB0CCR5
TB0CCR6
TB0EX0
Capture/compare 1
Capture/compare 2
Capture/compare 3
Capture/compare 4
Capture/compare 5
Capture/compare 6
TB0 expansion 0
TB0 interrupt vector
TB0IV
Table 6-34. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
TA2CTL
OFFSET
TA2 control
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA2 counter
TA2CCTL0
TA2CCTL1
TA2CCTL2
TA2R
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA2 expansion 0
TA2CCR0
TA2CCR1
TA2CCR2
TA2EX0
TA2 interrupt vector
TA2IV
Table 6-35. Real-Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
RTCCTL0
OFFSET
RTC control 0
00h
01h
02h
03h
08h
0Ah
0Ch
0Dh
0Eh
10h
11h
12h
13h
14h
15h
RTC control 1
RTCCTL1
RTC control 2
RTCCTL2
RTC control 3
RTCCTL3
RTC prescaler 0 control
RTC prescaler 1 control
RTC prescaler 0
RTCPS0CTL
RTCPS1CTL
RTCPS0
RTC prescaler 1
RTCPS1
RTC interrupt vector word
RTC seconds/counter 1
RTC minutes/counter 2
RTC hours/counter 3
RTC day of week/counter 4
RTC days
RTCIV
RTCSEC/RTCNT1
RTCMIN/RTCNT2
RTCHOUR/RTCNT3
RTCDOW/RTCNT4
RTCDAY
RTC month
RTCMON
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Table 6-35. Real-Time Clock Registers (Base Address: 04A0h) (continued)
REGISTER DESCRIPTION
REGISTER
RTCYEARL
OFFSET
RTC year low
16h
17h
18h
19h
1Ah
1Bh
RTC year high
RTCYEARH
RTCAMIN
RTC alarm minutes
RTC alarm hours
RTC alarm day of week
RTC alarm days
RTCAHOUR
RTCADOW
RTCADAY
Table 6-36. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
16-bit operand 1 – signed multiply
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
MPYS
MAC
MACS
OP2
16 × 16 result low word
RESLO
RESHI
16 × 16 result high word
16 × 16 sum extension
SUMEXT
MPY32L
MPY32H
MPYS32L
MPYS32H
MAC32L
MAC32H
MACS32L
MACS32H
OP2L
32-bit operand 1 – multiply low word
32-bit operand 1 – multiply high word
32-bit operand 1 – signed multiply low word
32-bit operand 1 – signed multiply high word
32-bit operand 1 – multiply accumulate low word
32-bit operand 1 – multiply accumulate high word
32-bit operand 1 – signed multiply accumulate low word
32-bit operand 1 – signed multiply accumulate high word
32-bit operand 2 – low word
32-bit operand 2 – high word
OP2H
32 × 32 result 0 – least significant word
32 × 32 result 1
RES0
RES1
32 × 32 result 2
RES2
32 × 32 result 3 – most significant word
MPY32 control 0
RES3
MPY32CTL0
Table 6-37. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTION
REGISTER
DMA0CTL
OFFSET
DMA channel 0 control
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
DMA channel 0 source address low
DMA channel 0 source address high
DMA channel 0 destination address low
DMA channel 0 destination address high
DMA channel 0 transfer size
DMA0SAL
DMA0SAH
DMA0DAL
DMA0DAH
DMA0SZ
DMA channel 1 control
DMA1CTL
DMA1SAL
DMA1SAH
DMA1DAL
DMA1DAH
DMA channel 1 source address low
DMA channel 1 source address high
DMA channel 1 destination address low
DMA channel 1 destination address high
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Table 6-37. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h) (continued)
REGISTER DESCRIPTION
REGISTER
DMA1SZ
OFFSET
DMA channel 1 transfer size
DMA channel 2 control
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Eh
DMA2CTL
DMA2SAL
DMA2SAH
DMA2DAL
DMA2DAH
DMA2SZ
DMA channel 2 source address low
DMA channel 2 source address high
DMA channel 2 destination address low
DMA channel 2 destination address high
DMA channel 2 transfer size
DMA module control 0
DMACTL0
DMACTL1
DMACTL2
DMACTL3
DMACTL4
DMAIV
DMA module control 1
DMA module control 2
DMA module control 3
DMA module control 4
DMA interrupt vector
Table 6-38. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
UCA0CTL1
OFFSET
USCI control 1
00h
01h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ch
1Dh
1Eh
USCI control 0
UCA0CTL0
UCA0BR0
USCI baud rate 0
USCI baud rate 1
UCA0BR1
USCI modulation control
USCI status
UCA0MCTL
UCA0STAT
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
UCA0IRTCTL
UCA0IRRCTL
UCA0IE
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
UCA0IFG
UCA0IV
Table 6-39. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
REGISTER
UCB0CTL1
OFFSET
USCI synchronous control 1
USCI synchronous control 0
USCI synchronous bit rate 0
USCI synchronous bit rate 1
USCI synchronous status
00h
01h
06h
07h
0Ah
0Ch
0Eh
10h
12h
1Ch
1Dh
1Eh
UCB0CTL0
UCB0BR0
UCB0BR1
UCB0STAT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA
UCB0I2CSA
UCB0IE
USCI synchronous receive buffer
USCI synchronous transmit buffer
USCI I2C own address
USCI I2C slave address
USCI interrupt enable
USCI interrupt flags
UCB0IFG
USCI interrupt vector word
UCB0IV
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Table 6-40. USCI_A1 Registers (Base Address: 0600h)
REGISTER DESCRIPTION
REGISTER
UCA1CTL1
OFFSET
USCI control 1
00h
01h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ch
1Dh
1Eh
USCI control 0
UCA1CTL0
UCA1BR0
USCI baud rate 0
USCI baud rate 1
UCA1BR1
USCI modulation control
USCI status
UCA1MCTL
UCA1STAT
UCA1RXBUF
UCA1TXBUF
UCA1ABCTL
UCA1IRTCTL
UCA1IRRCTL
UCA1IE
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
UCA1IFG
UCA1IV
Table 6-41. USCI_B1 Registers (Base Address: 0620h)
REGISTER DESCRIPTION
REGISTER
UCB1CTL1
OFFSET
USCI synchronous control 1
USCI synchronous control 0
USCI synchronous bit rate 0
USCI synchronous bit rate 1
USCI synchronous status
00h
01h
06h
07h
0Ah
0Ch
0Eh
10h
12h
1Ch
1Dh
1Eh
UCB1CTL0
UCB1BR0
UCB1BR1
UCB1STAT
UCB1RXBUF
UCB1TXBUF
UCB1I2COA
UCB1I2CSA
UCB1IE
USCI synchronous receive buffer
USCI synchronous transmit buffer
USCI I2C own address
USCI I2C slave address
USCI interrupt enable
USCI interrupt flags
UCB1IFG
USCI interrupt vector word
UCB1IV
Table 6-42. ADC10_A Registers (Base Address: 0740h)
REGISTER DESCRIPTION
REGISTER
ADC10CTL0
OFFSET
ADC10_A control 0
00h
02h
04h
06h
08h
0Ah
12h
1Ah
1Ch
1Eh
ADC10_A control 1
ADC10CTL1
ADC10CTL2
ADC10LO
ADC10_A control 2
ADC10_A window comparator low threshold
ADC10_A window comparator high threshold
ADC10_A memory control 0
ADC10_A conversion memory
ADC10_A interrupt enable
ADC10_A interrupt flags
ADC10HI
ADC10MCTL0
ADC10MEM0
ADC10IE
ADC10IGH
ADC10IV
ADC10_A interrupt vector word
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Table 6-43. Comparator_B Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
CBCTL0
OFFSET
Comp_B control 0
Comp_B control 1
Comp_B control 2
Comp_B control 3
Comp_B interrupt
00h
02h
04h
06h
0Ch
0Eh
CBCTL1
CBCTL2
CBCTL3
CBINT
Comp_B interrupt vector word
CBIV
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6.10 Input/Output Diagrams
6.10.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
Figure 6-2 shows the port diagram. Table 6-44 summarizes the selection of the port function.
Pad Logic
P1REN.x
DVSS
0
1
1
(P1.0 to P1.3) DVCC
(P1.4 to P1.7) DVIO
P1DIR.x
0
1
Direction
0: Input
1: Output
From module
P1OUT.x
0
1
From module
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
P1.5/TA0.4
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
EN
D
To module
P1IRQ.x
P1IE.x
EN
Q
P1IFG.x
Set
P1SEL.x
P1IES.x
Interrupt
Edge
Select
Figure 6-2. Port P1 (P1.0 to P1.7) Diagram
82
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Table 6-44. Port P1 (P1.0 to P1.7) Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
P1.0 (I/O)
TA0CLK
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
P1.0/TA0CLK/ACLK
P1.1/TA0.0
0
0
ACLK
1
P1.1 (I/O)
TA0.CCI0A
TA0.0
I: 0; O: 1
1
2
3
4
5
6
7
0
1
P1.2 (I/O)
TA0.CCI1A
TA0.1
I: 0; O: 1
P1.2/TA0.1
0
1
P1.3 (I/O)
TA0.CCI2A
TA0.2
I: 0; O: 1
P1.3/TA0.2
0
1
P1.4 (I/O)
TA0.CCI3A
TA0.3
I: 0; O: 1
P1.4/TA0.3
0
1
P1.5 (I/O)
TA0.CCI4A
TA0.4
I: 0; O: 1
P1.5/TA0.4
0
1
P1.6 (I/O)
TA1CLK
I: 0; O: 1
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
0
CBOUT comparator B
P1.7 (I/O)
TA1.CCI0A
TA1.0
1
I: 0; O: 1
0
1
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6.10.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
Figure 6-3 shows the port diagram. Table 6-45 summarizes the selection of the port function.
Pad Logic
P2REN.x
DVSS
DVIO
0
1
1
P2DIR.x
0
1
Direction
0: Input
1: Output
From module
P2OUT.x
0
1
From module
P2.0/TA1.1
P2.1/TA1.2
P2.2/TA2CLK/SMCLK
P2.3/TA2.0
P2.4/TA2.1
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
P2.5/TA2.2
P2.6/RTCCLK/DMAE0
P2.7/UB0STE/UCA0CLK
EN
D
To module
To module
P2IE.x
EN
Q
P2IFG.x
Set
P2SEL.x
P2IES.x
Interrupt
Edge
Select
Figure 6-3. Port P2 (P2.0 to P2.7) Diagram
84
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Table 6-45. Port P2 (P2.0 to P2.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL.x
P2.0 (I/O)
TA1.CCI1A
TA1.1
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
P2.0/TA1.1(2)
0
0
1
P2.1 (I/O)
TA1.CCI2A
TA1.2
I: 0; O: 1
P2.1/TA1.2(2)
1
2
3
4
5
0
1
P2.2 (I/O)
TA2CLK
I: 0; O: 1
P2.2/TA2CLK/SMCLK(2)
P2.3/TA2.0(2)
0
SMCLK
1
P2.3 (I/O)
TA2.CCI0A
TA2.0
I: 0; O: 1
0
1
P2.4 (I/O)
TA2.CCI1A
TA2.1
I: 0; O: 1
P2.4/TA2.1(2)
0
1
P2.5 (I/O)
TA2.CCI2A
TA2.2
I: 0; O: 1
P2.5/TA2.2(2)
0
1
P2.6 (I/O)
DMAE0
I: 0; O: 1
P2.6/RTCCLK/DMAE0(2)
6
7
0
RTCCLK
P2.7 (I/O)
UCB0STE/UCA0CLK(3) (4)
1
I: 0; O: 1
X
P2.7/UCB0STE/UCA0CLK
(1) X = Don't care
(2) Not available on RGZ package types.
(3) The pin direction is controlled by the USCI module.
(4) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_B0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
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6.10.3 Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
Figure 6-4 shows the port diagram. Table 6-46 summarizes the selection of the port function.
Pad Logic
P3REN.x
DVSS
DVIO
0
1
1
P3DIR.x
0
1
Direction
0: Input
1: Output
From module
P3OUT.x
0
1
From module
P3.0/UCB0SIMO/UCB0SDA
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
P3.4/UCA0RXD/UCA0SOMI
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
EN
D
To module
Figure 6-4. Port P3 (P3.0 to P3.4) Diagram
Table 6-46. Port P3 (P3.0 to P3.4) Pin Functions
FUNCTION
CONTROL BITS OR SIGNALS(1)
PIN NAME (P3.x)
x
0
1
2
3
4
P3DIR.x
P3SEL.x
P3.0 (I/O)
UCB0SIMO/UCB0SDA(2) (3)
I: 0; O: 1
0
1
0
1
0
1
0
1
0
1
P3.0/UCB0SIMO/UCB0SDA
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
X
P3.1 (I/O)
I: 0; O: 1
UCB0SOMI/UCB0SCL(2) (3)
P3.2 (I/O)
UCB0CLK/UCA0STE(2) (4)
X
I: 0; O: 1
X
I: 0; O: 1
X
P3.3 (I/O)
UCA0TXD/UCA0SIMO(2)
P3.4 (I/O)
UCA0RXD/UCA0SOMI(2)
I: 0; O: 1
X
P3.4/UCA0RXD/UCA0SOMI
(1) X = Don't care
(2) The pin direction is controlled by the USCI module.
(3) If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
(4) UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI_A0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
86
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6.10.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
Figure 6-5 shows the port diagram. Table 6-47 summarizes the selection of the port function.
Pad Logic
P4REN.x
DVSS
DVIO
0
1
1
P4DIR.x
0
1
Direction
0: Input
1: Output
From Port Mapping Control
P4OUT.x
0
1
From Port Mapping Control
P4.0/P4MAP0
P4.1/P4MAP1
P4.2/P4MAP2
P4.3/P4MAP3
P4.4/P4MAP4
P4.5/P4MAP5
P4.6/P4MAP6
P4.7/P4MAP7
P4DS.x
0: Low drive
1: High drive
P4SEL.x
P4IN.x
EN
D
To Port Mapping Control
Figure 6-5. Port P4 (P4.0 to P4.7) Diagram
Table 6-47. Port P4 (P4.0 to P4.7) Pin Functions
FUNCTION
CONTROL BITS OR SIGNALS(1)
PIN NAME (P4.x)
P4.0/P4MAP0
P4.1/P4MAP1
P4.2/P4MAP2
P4.3/P4MAP3
P4.4/P4MAP4
P4.5/P4MAP5
P4.6/P4MAP6
x
0
1
2
3
4
5
6
7
P4DIR.x(2)
P4SEL.x
P4MAPx
P4.0 (I/O)
I: 0; O: 1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
≤ 30
X
Mapped secondary digital function
P4.1 (I/O)
X
I: 0; O: 1
Mapped secondary digital function
P4.2 (I/O)
X
≤ 30
X
I: 0; O: 1
Mapped secondary digital function
P4.3 (I/O)
X
≤ 30
X
I: 0; O: 1
Mapped secondary digital function
P4.4 (I/O)
X
≤ 30
X
I: 0; O: 1
Mapped secondary digital function
P4.5 (I/O)
X
≤ 30
X
I: 0; O: 1
Mapped secondary digital function
P4.6 (I/O)
X
I: 0; O: 1
X
≤ 30
X
Mapped secondary digital function
P4.7 (I/O)
≤ 30
X
I: 0; O: 1
X
P4.7/P4MAP7(3)
Mapped secondary digital function
≤ 30
(1) X = Don't care
(2) The direction of some mapped secondary functions are controlled directly by the module. See Table 6-7 for specific direction control
information of mapped secondary functions.
(3) Not available on RGZ package types.
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6.10.5 Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
Figure 6-6 shows the port diagram. Table 6-48 summarizes the selection of the port function.
Pad Logic
To or from Reference
(not available on F521x)
(not available on F521x)
to ADC10
(not available on F521x)
INCHx = x
P5REN.x
DVSS
DVCC
0
1
1
P5DIR.x
0
1
P5OUT.x
0
1
From module
P5.0/(A8/VeREF+)
P5.1/(A9/VeREF–)
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
EN
D
To module
Figure 6-6. Port P5 (P5.0 and P5.1) Diagram
Table 6-48. Port P5 (P5.0 and P5.1) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL.x
REFOUT(2)
P5.0 (I/O)(3)
A8/VeREF+(4)
P5.1 (I/O)(3)
A9/VeREF–(5)
I: 0; O: 1
0
1
0
1
X
0
X
0
P5.0/A8/VeREF+
0
1
X
I: 0; O: 1
X
P5.1/A9/VeREF–
(1) X = Don't care
(2) REFOUT resides in the REF module.
(3) Default condition
(4) Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC10_A. Channel A8, when selected with
the INCHx bits, is connected to the VeREF+ pin.
(5) Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. An external voltage can be applied to VeREF- and used as the reference for the ADC10_A. Channel A9, when selected with the
INCHx bits, is connected to the VeREF- pin.
88
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6.10.6 Port P5 (P5.2) Input/Output With Schmitt Trigger
Figure 6-7 shows the port diagram. Table 6-49 summarizes the selection of the port function.
Pad Logic
To XT2
P5REN.2
DVSS
DVCC
0
1
1
P5DIR.2
0
1
P5OUT.2
0
1
Module X OUT
P5.2/XT2IN
P5DS.2
0: Low drive
1: High drive
P5SEL.2
P5IN.2
Bus
Keeper
EN
D
Module X IN
Figure 6-7. Port P5 (P5.2) Diagram
6.10.7 Port P5 (P5.3) Input/Output With Schmitt Trigger
Figure 6-8 shows the port diagram. Table 6-49 summarizes the selection of the port function.
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Pad Logic
To XT2
P5REN.3
DVSS
DVCC
0
1
1
P5DIR.3
0
1
P5OUT.3
0
1
Module X OUT
P5SEL.2
P5.3/XT2OUT
P5DS.3
0: Low drive
1: High drive
XT2BYPASS
P5SEL.3
P5IN.3
Bus
Keeper
EN
D
Module X IN
Figure 6-8. Port P5 (P5.3) Diagram
Table 6-49. Port P5 (P5.2 and P5.3) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL.2
P5SEL.3
XT2BYPASS
P5.2 (I/O)
I: 0; O: 1
0
1
1
0
1
1
X
X
X
0
X
0
1
X
0
1
P5.2/XT2IN
2
XT2IN crystal mode(2)
XT2IN bypass mode(2)
P5.3 (I/O)
XT2OUT crystal mode(3)
P5.3 (I/O)(3)
X
X
I: 0; O: 1
P5.3/XT2OUT
3
X
X
X
0
(1) X = Don't care
(2) Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal
mode or bypass mode.
(3) Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as
general-purpose I/O.
90
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6.10.8 Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
Figure 6-9 and Figure 6-10 show the port diagrams. Table 6-50 summarizes the selection of the port
function.
Pad Logic
to XT1
P5REN.4
DVSS
DVCC
0
1
1
P5DIR.4
0
1
P5OUT.4
0
1
Module X OUT
P5.4/XIN
P5DS.4
0: Low drive
1: High drive
P5SEL.4
P5IN.4
Bus
Keeper
EN
D
Module X IN
Figure 6-9. Port P5 (P5.4) Diagram
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Pad Logic
to XT1
P5REN.5
DVSS
DVCC
0
1
1
P5DIR.5
0
1
P5OUT.5
0
1
Module X OUT
P5.5/XOUT
P5SEL.4
P5DS.5
0: Low drive
1: High drive
XT1BYPASS
P5SEL.5
P5IN.5
Bus
Keeper
EN
D
Module X IN
Figure 6-10. Port P5 (P5.5) Diagram
Table 6-50. Port P5 (P5.4 and P5.5) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL.4
P5SEL.5
XT1BYPASS
P5.4 (I/O)
I: 0; O: 1
0
1
1
0
1
1
X
X
X
0
X
0
1
X
0
1
P5.4/XIN
4
XIN crystal mode(2)
XIN bypass mode(2)
P5.5 (I/O)
XOUT crystal mode(3)
P5.5 (I/O)(3)
X
X
I: 0; O: 1
P5.5/XOUT
5
X
X
X
0
(1) X = Don't care
(2) Setting P5SEL.4 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.4 is configured for crystal
mode or bypass mode.
(3) Setting P5SEL.4 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.5 can be used as
general-purpose I/O.
92
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6.10.9 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
Figure 6-11 shows the port diagram. Table 6-51 summarizes the selection of the port function.
Pad Logic
to ADC10
(n/a MSPF430F521x)
INCHx = x
(n/a MSPF430F521x)
to Comparator_B
from Comparator_B
CBPD.x
P6REN.x
DVSS
DVCC
0
1
1
P6DIR.x
0
1
Direction
0: Input
1: Output
P6OUT.x
0
1
From module
P6.0/CB0/(A0)
P6.1/CB1/(A1)
P6.2/CB2/(A2)
P6.3/CB3/(A3)
P6.4/CB4/(A4)
P6.5/CB5/(A5)
P6.6/CB6/(A6)
P6.7/CB7/(A7)
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
EN
D
To module
Figure 6-11. Port P6 (P6.0 to P6.7) Diagram
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MSP430F5214 MSP430F5212
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
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Table 6-51. Port P6 (P6.0 to P6.7) Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (P6.x)
x
FUNCTION
P6DIR.x
P6SEL.x
CBPD
0
P6.0 (I/O)
A0
CB0(1)
P6.1 (I/O)
A1
CB1(1)
P6.2 (I/O)
A2
CB2(1)
P6.3 (I/O)
A3
CB3(1)
P6.4 (I/O)
A4
CB4(1)
P6.5 (I/O)
A5
CB5(1)
P6.6 (I/O)
A6
CB6(1)
P6.7 (I/O)
A7
I: 0; O: 1
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
P6.0/CB0/(A0)
0
X
X
1
X
I: 0; O: 1
0
P6.1/CB1/(A1)
P6.2/CB2/(A2)
P6.3/CB3/(A3)
P6.4/CB4/(A4)
P6.5/CB5/(A5)
P6.6/CB6/(A6)(2)
P6.7/CB7/(A7)(2)
1
2
3
4
5
6
7
X
X
1
X
I: 0; O: 1
0
X
X
1
X
I: 0; O: 1
0
X
X
1
X
I: 0; O: 1
0
X
X
1
X
I: 0; O: 1
0
X
X
1
X
I: 0; O: 1
0
X
X
1
X
I: 0; O: 1
0
X
X
X
1
CB7(1)
(1) Setting the CBPD.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input buffer
for that pin, regardless of the state of the associated CBPD.x bit.
(2) Not available on RGZ package types.
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6.10.10 Port P7 (P7.0 to P7.5) Input/Output With Schmitt Trigger
Figure 6-12 shows the port diagram. Table 6-52 summarizes the selection of the port function.
Pad Logic
P7REN.x
DVSS
DVIO
0
1
1
P7DIR.x
0
1
Direction
0: Input
1: Output
From module
P7OUT.x
0
1
P7.0/TB0.0
P7.1/TB0.1
P7.2/TB0.2
P7.3/TB0.3
P7.4/TB0.4
P7.5/TB0.5
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7IN.x
EN
D
To module
Figure 6-12. Port P7 (P7.0 to P7.5) Diagram
Table 6-52. Port P7 (P7.0 to P7.5) Pin Functions
FUNCTION
CONTROL BITS OR SIGNALS
PIN NAME (P7.x)
x
P7DIR.x
P7SEL.x
P7.0 (I/O)
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
P7.0/TB0.0(1)
0
TB0.CCI0A
TB0.0
0
1
P7.1 (I/O)
TB0.CCI1A
TB0.1
I: 0; O: 1
P7.1/TB0.1(1)
P7.2/TB0.2(1)
P7.3/TB0.3(1)
P7.4/TB0.4(1)
P7.5/TB0.5(1)
1
2
3
4
5
0
1
P7.2 (I/O)
TB0.CCI2A
TB0.2
I: 0; O: 1
0
1
P7.3 (I/O)
TB0.CCI3A
TB0.3
I: 0; O: 1
0
1
P7.4 (I/O)
TB0.CCI4A
TB0.4
I: 0; O: 1
0
1
P7.5 (I/O)
TB0.CCI5A
TB0.5
I: 0; O: 1
0
1
(1) Not available on RGZ package types.
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6.10.11 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
Figure 6-13 shows the port diagram. Table 6-53 summarizes the selection of the port function.
Pad Logic
PJREN.0
0
1
DVSS
DVCC
1
PJDIR.0
DVCC
0
1
PJOUT.0
0
1
From JTAG
PJ.0/TDO
PJDS.0
0: Low drive
1: High drive
From JTAG
PJIN.0
EN
D
Figure 6-13. Port PJ (PJ.0) Diagram
6.10.12 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt
Trigger or Output
Figure 6-14 shows the port diagram. Table 6-53 summarizes the selection of the port function.
96
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Pad Logic
PJREN.x
0
1
DVSS
DVCC
1
PJDIR.x
DVSS
0
1
PJOUT.x
0
1
From JTAG
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
PJDS.x
0: Low drive
1: High drive
From JTAG
PJIN.x
EN
D
To JTAG
Figure 6-14. Port PJ (PJ.1 to PJ.3) Diagram
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Table 6-53. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS OR
SIGNALS(1)
PIN NAME (PJ.x)
x
FUNCTION
PJDIR.x
PJ.0 (I/O)(2)
TDO(3)
PJ.1 (I/O)(2)
TDI/TCLK(3) (4)
PJ.2 (I/O)(2)
TMS(3) (4)
I: 0; O: 1
PJ.0/TDO
0
1
2
3
X
I: 0; O: 1
PJ.1/TDI/TCLK
PJ.2/TMS
X
I: 0; O: 1
X
PJ.3 (I/O)(2)
TCK(3) (4)
I: 0; O: 1
X
PJ.3/TCK
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.
98
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6.11 Device Descriptors
Table 6-54 and Table 6-55 list the contents of the device descriptor tag-length-value (TLV) structure for
each device type.
Table 6-54. MSP430F522x Device Descriptor Table(1)
VALUE
SIZE
(BYTES)
DESCRIPTION
Info length
ADDRESS
F5229
06h
F5227
06h
F5224
06h
F5222
06h
01A00h
01A01h
01A02h
01A04h
01A05h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Eh
01A10h
01A12h
01A14h
01A15h
01A16h
01A18h
1
1
2
1
1
1
1
1
1
4
2
2
2
1
1
2
2
CRC length
CRC value
06h
06h
06h
06h
Per unit
51h
Per unit
4Fh
Per unit
4Ch
Per unit
4Ah
Info Block
Device ID
Device ID
81h
81h
81h
81h
Hardware revision
Firmware revision
Die record tag
Die record length
Lot/wafer ID
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
0Ah
0Ah
0Ah
0Ah
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Die Record
Die X position
Die Y position
Test results
ADC10 calibration tag
ADC10 calibration length
ADC gain factor
ADC offset
10h
10h
10h
10h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 30°C
01A1Ah
01A1Ch
01A1Eh
01A20h
01A22h
01A24h
2
2
2
2
2
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 85°C
ADC10
Calibration
ADC 2.0-V reference
Temperature sensor 30°C
ADC 2.0-V reference
Temperature sensor 85°C
ADC 2.5-V reference
Temperature sensor 30°C
ADC 2.5-V reference
Temperature sensor 85°C
REF calibration tag
REF calibration length
01A26h
01A27h
01A28h
01A2Ah
01A2Ch
1
1
2
2
2
12h
12h
12h
12h
06h
06h
06h
06h
REF Calibration
REF 1.5-V reference factor
REF 2.0-V reference factor
REF 2.5-V reference factor
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
(1) NA = Not applicable
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Table 6-54. MSP430F522x Device Descriptor Table(1) (continued)
VALUE
SIZE
(BYTES)
DESCRIPTION
ADDRESS
F5229
02h
F5227
02h
F5224
02h
F5222
02h
Peripheral descriptor tag
01A2Eh
01A2Fh
1
1
Peripheral descriptor length
Memory 1
5Fh
5Fh
5Dh
5Dh
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
2
2
2
2
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
Memory 2
Memory 3
Memory 4
12h
2Eh
12h
2Eh
12h
2Eh
12h
2Eh
22h
96h
22h
94h
22h
96h
22h
94h
Memory 5
Memory 6
2
1/2
1
N/A
N/A
00h
20h
N/A
N/A
00h
20h
N/A
N/A
00h
1Fh
N/A
N/A
00h
1Fh
Delimiter
Peripheral count
1
00h
23h
00h
23h
00h
23h
00h
23h
MSP430CPUXV2
JTAG
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
00h
09h
00h
09h
00h
09h
00h
09h
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
SBW
00h
03h
00h
03h
00h
03h
00h
05h
EEM-S
TI BSL
00h
FCh
00h
FCh
00h
FCh
00h
FCh
10h
41h
10h
41h
10h
41h
10h
41h
SFR
Peripheral
Descriptor
02h
30h
02h
30h
02h
30h
02h
30h
PMM
02h
38h
02h
38h
02h
38h
02h
38h
FCTL
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
CRC16
CRC16_RB
RAMCTL
WDT_A
UCS
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
44h
00h
44h
00h
44h
00h
44h
00h
40h
00h
40h
00h
40h
00h
40h
01h
48h
01h
48h
01h
48h
01h
48h
02h
42h
02h
42h
02h
42h
02h
42h
SYS
03h
A0h
03h
A0h
03h
A0h
03h
A0h
REF
01h
10h
01h
10h
01h
10h
01h
10h
Port mapping
Port 1/2
Port 3/4
Port 5/6
04h
51h
04h
51h
04h
51h
04h
51h
02h
52h
02h
52h
02h
52h
02h
52h
02h
53h
02h
53h
02h
53h
02h
53h
100
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Table 6-54. MSP430F522x Device Descriptor Table(1) (continued)
VALUE
SIZE
(BYTES)
DESCRIPTION
Port 7/8
ADDRESS
F5229
F5227
F5224
F5222
02h
54h
02h
54h
2
2
2
2
2
2
2
2
2
2
2
2
2
N/A
N/A
0Ch
5Fh
0Ch
5Fh
0Eh
5Fh
0Eh
5Fh
JTAG
TA0
02h
62h
02h
62h
02h
62h
02h
62h
04h
61h
04h
61h
04h
61h
04h
61h
TA1
04h
67h
04h
67h
04h
67h
04h
67h
TB0
04h
61h
04h
61h
04h
61h
04h
61h
TA2
Peripheral
Descriptor
(continued)
0Ah
68h
0Ah
68h
0Ah
68h
0Ah
68h
RTC
02h
85h
02h
85h
02h
85h
02h
85h
MPY32
DMA-3
USCI_A/B
USCI_A/B
ADC10_A
COMP_B
04h
47h
04h
47h
04h
47h
04h
47h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
04h
90h
04h
90h
04h
90h
04h
90h
14h
D3h
14h
D3h
14h
D3h
14h
D3h
18h
A8h
18h
A8h
18h
A8h
18h
A8h
COMP_B
TB0.CCIFG0
TB0.CCIFG1..6
WDTIFG
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A8h
64h
65h
40h
90h
91h
D0h
60h
61h
01h
46h
62h
63h
50h
92h
93h
66h
67h
51h
68h
00h
A8h
64h
65h
40h
90h
91h
D0h
60h
61h
01h
46h
62h
63h
50h
92h
93h
66h
67h
51h
68h
00h
A8h
64h
65h
40h
90h
91h
D0h
60h
61h
01h
46h
62h
63h
50h
92h
93h
66h
67h
51h
68h
00h
A8h
64h
65h
40h
90h
91h
D0h
60h
61h
01h
46h
62h
63h
50h
92h
93h
66h
67h
51h
68h
00h
USCI_A0
USCI_B0
ADC10_A
TA0.CCIFG0
TA0.CCIFG1..4
Reserved
DMA
Interrupts
TA1.CCIFG0
TA1.CCIFG1..2
P1
USCI_A1
USCI_B1
TA1.CCIFG0
TA1.CCIFG1..2
P2
RTC_A
Delimiter
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Table 6-55. MSP430F521x Device Descriptor Table(1)
VALUE
SIZE
(BYTES)
DESCRIPTION
Info length
ADDRESS
F5219
06h
F5217
06h
F5214
06h
F5212
06h
01A00h
01A01h
01A02h
01A04h
01A05h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Eh
01A10h
01A12h
01A14h
01A15h
01A16h
01A18h
1
1
2
1
1
1
1
1
1
4
2
2
2
1
1
2
2
CRC length
CRC value
06h
06h
06h
06h
Per unit
47h
Per unit
45h
Per unit
42h
Per unit
40h
Info Block
Device ID
Device ID
81h
81h
81h
81h
Hardware revision
Firmware revision
Die record tag
Die record length
Lot/wafer ID
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
0Ah
0Ah
0Ah
0Ah
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Die Record
Die X position
Die Y position
Test results
ADC10 calibration tag
ADC10 calibration length
ADC gain factor
ADC offset
10h
10h
10h
10h
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
ADC 1.5-V reference
Temperature sensor 30°C
01A1Ah
01A1Ch
01A1Eh
01A20h
01A22h
01A24h
2
2
2
2
2
2
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
ADC 1.5-V Reference
Temperature sensor 85°C
ADC10
Calibration
ADC 2.0-V reference
Temperature sensor 30°C
ADC 2.0-V reference
Temperature sensor 85°C
ADC 2.5-V reference
Temperature sensor 30°C
ADC 2.5-V reference
Temperature sensor 85°C
REF calibration tag
REF calibration length
01A26h
01A27h
01A28h
01A2Ah
01A2Ch
1
1
2
2
2
12h
12h
12h
12h
06h
06h
06h
06h
REF Calibration
REF 1.5-V reference factor
REF 2.0-V reference factor
REF 2.5-V reference factor
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
(1) NA = Not applicable, Blank = unused and reads FFh
102 Detailed Description
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Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217
MSP430F5214 MSP430F5212
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
www.ti.com.cn
Table 6-55. MSP430F521x Device Descriptor Table(1) (continued)
VALUE
SIZE
(BYTES)
DESCRIPTION
ADDRESS
F5219
02h
F5217
02h
F5214
02h
F5212
02h
Peripheral descriptor tag
01A2Eh
01A2Fh
1
1
Peripheral descriptor length
Memory 1
5Dh
5Dh
5Bh
5Bh
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
2
2
2
2
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
Memory 2
Memory 3
Memory 4
12h
2Eh
12h
2Eh
12h
2Eh
12h
2Eh
22h
96h
22h
94h
22h
96h
22h
94h
Memory 5
Memory 6
2
1/2
1
N/A
N/A
00h
1Fh
N/A
N/A
00h
1Fh
N/A
N/A
00h
1Eh
N/A
N/A
00h
1Eh
Delimiter
Peripheral count
1
00h
23h
00h
23h
00h
23h
00h
23h
MSP430CPUXV2
JTAG
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
00h
09h
00h
09h
00h
09h
00h
09h
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
SBW
00h
03h
00h
03h
00h
03h
00h
05h
EEM-S
TI BSL
00h
FCh
00h
FCh
00h
FCh
00h
FCh
10h
41h
10h
41h
10h
41h
10h
41h
SFR
Peripheral
Descriptor
02h
30h
02h
30h
02h
30h
02h
30h
PMM
02h
38h
02h
38h
02h
38h
02h
38h
FCTL
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
CRC16
CRC16_RB
RAMCTL
WDT_A
UCS
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
44h
00h
44h
00h
44h
00h
44h
00h
40h
00h
40h
00h
40h
00h
40h
01h
48h
01h
48h
01h
48h
01h
48h
02h
42h
02h
42h
02h
42h
02h
42h
SYS
03h
A0h
03h
A0h
03h
A0h
03h
A0h
REF
01h
10h
01h
10h
01h
10h
01h
10h
Port mapping
Port 1/2
Port 3/4
Port 5/6
04h
51h
04h
51h
04h
51h
04h
51h
02h
52h
02h
52h
02h
52h
02h
52h
02h
53h
02h
53h
02h
53h
02h
53h
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Detailed Description
103
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MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
www.ti.com.cn
Table 6-55. MSP430F521x Device Descriptor Table(1) (continued)
VALUE
SIZE
(BYTES)
DESCRIPTION
Port 7/8
ADDRESS
F5219
F5217
F5214
F5212
02h
54h
02h
54h
2
2
2
2
2
2
2
2
2
2
N/A
N/A
0Ch
5Fh
0Ch
5Fh
0Eh
5Fh
0Eh
5Fh
JTAG
TA0
02h
62h
02h
62h
02h
62h
02h
62h
04h
61h
04h
61h
04h
61h
04h
61h
TA1
04h
67h
04h
67h
04h
67h
04h
67h
TB0
04h
61h
04h
61h
04h
61h
04h
61h
TA2
Peripheral
Descriptor
(continued)
0Ah
68h
0Ah
68h
0Ah
68h
0Ah
68h
RTC
02h
85h
02h
85h
02h
85h
02h
85h
MPY32
DMA-3
USCI_A/B
04h
47h
04h
47h
04h
47h
04h
47h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
04h
90h
04h
90h
04h
90h
04h
90h
USCI_A/B
ADC10_A
COMP_B
2
2
2
N/A
N/A
N/A
N/A
2Ch
A8h
2Ch
A8h
2Ch
A8h
2Ch
A8h
COMP_B
TB0.CCIFG0
TB0.CCIFG1..6
WDTIFG
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A8h
64h
65h
40h
90h
91h
01h
60h
61h
01h
46h
62h
63h
50h
92h
93h
66h
67h
51h
68h
00h
A8h
64h
65h
40h
90h
91h
01h
60h
61h
01h
46h
62h
63h
50h
92h
93h
66h
67h
51h
68h
00h
A8h
64h
65h
40h
90h
91h
01h
60h
61h
01h
46h
62h
63h
50h
92h
93h
66h
67h
51h
68h
00h
A8h
64h
65h
40h
90h
91h
01h
60h
61h
01h
46h
62h
63h
50h
92h
93h
66h
67h
51h
68h
00h
USCI_A0
USCI_B0
Reserved
TA0.CCIFG0
TA0.CCIFG1..4
Reserved
DMA
Interrupts
TA1.CCIFG0
TA1.CCIFG1..2
P1
USCI_A1
USCI_B1
TA2.CCIFG0
TA2.CCIFG1..2
P2
RTC_A
Delimiter
104
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ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
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7 器件和文档支持
7.1 开始使用
有关 MSP430 系列器件以及开发协助工具和库的更多信息，请访问 MSP430 超低功耗传感和测量 MCU 概
述。
7.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS.
These prefixes represent evolutionary stages of product development from engineering prototypes (XMS)
through fully qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical
specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production
devices. TI recommends that these devices not be used in any production system because their expected
end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
temperature range, package type, and distribution format. 图 7-1 provides a legend for reading the
complete device name.
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MSP430F5214 MSP430F5212
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
www.ti.com.cn
MSP 430 F 5 438 A I ZQW T -EP
Processor Family
MCU Platform
Device Type
Series
Feature Set
Optional: Additional Features
Optional: Tape and Reel
Packaging
Optional: Temperature Range
Optional: A = Revision
Processor Family
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
MCU Platform
Device Type
430 = MSP430 low-power microcontroller platform
Memory Type
C = ROM
Specialized Application
AFE = Analog Front End
BQ = Contactless Power
CG = ROM Medical
F = Flash
FR = FRAM
G = Flash or FRAM (Value Line)
L = No Nonvolatile Memory
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
Series
1 = Up to 8 MHz
5 = Up to 25 MHz
6 = Up to 25 MHz with LCD
0 = Low-Voltage Series
2 = Up to 16 MHz
3 = Legacy
4 = Up to 16 MHz with LCD
Feature Set
Various levels of integration within a series
N/A
Optional: A = Revision
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small reel
R = Large reel
No markings = Tube or tray
Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C)
-HT = Extreme Temperature Parts (–55°C to 150°C)
-Q1 = Automotive Q100 Qualified
图 7-1. Device Nomenclature
106
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MSP430F5214 MSP430F5212
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
www.ti.com.cn
7.3 工具与软件
所有 MSP 微控制器均受多种软件和硬件开发工具的支持。相关工具由 TI 以及多家第三方供应商提供。请参
阅 MSP430 超低功耗 MCU – 工具与软件，了解所有工具。
表 7-1 列出了 MSP430F522x 和 MSP430F521x MCU 的 调试 功能。请参阅《适用于 MSP430 的 Code
Composer Studio 用户指南》，以了解可用功能的 详细信息。
表 7-1. 硬件调试 特性
四线制
JTAG
两线制
JTAG
断点
(N)
状态序列发生
器
LPMx.5 调试支 EnergyTrace++ 技
MSP430 架构
范围断点
有
时钟控制
是
跟踪缓冲器
否
持
术
MSP430Xv2
有
有
3
否
有
有
设计套件与评估模块
MSP-TS430RGC64C - 适用于 MSP430F5x MCU 的 64 引脚目标开发板 MSP-TS430RGC64C 是一款独
立的 64 引脚 ZIF 插座目标板，用于通过 JTAG 接口或 Spy-Bi-Wire（两线制 JTAG）协议在
系统内对 MSP430 MCU 进行编程和调试。
Bluetooth® 和 MSP430 音频源参考设计电路板 客户可以使用蓝牙和 MSP430 音频源参考设计为适用于玩
具、投影仪、智能遥控器 和所有 音频流配件等应用的 低端 低功耗音频源解决方案创建各种应
用。
带有集成天线的双模蓝牙 CC2564 模块评估板 CC2564MODAEM 评估板包含蓝牙 BR/EDR/LE HCI 解决方
案。bCC2564MODA 基于 TI 的 CC2564B 双模蓝牙单芯片器件，旨在用于评估和设计，能够
减少设计工作量，实现产品快速上市。
软件
MSP430Ware™ 软件 MSP430Ware 软件集合了所有 MSP430 器件的代码示例、数据表以及其他设计资
源，打包提供给用户。除了提供已有 MSP430 MCU 设计资源的完整集合外，MSP430Ware
软件还包含名为 MSP 驱动程序库的高级 API。借助该库可以轻松地对 MSP430 硬件进行编
程。MSP430Ware 软件以 CCS 组件或独立软件包两种形式提供。
MSP430F522x、MSP430F521x 代码示例 根据不同应用需求配置各集成外设的 C 代码示例。
MSP 驱动程序库 MSP 驱动程序库的抽象 API 提供易用的函数调用，无需直接操纵 MSP430 硬件的位与字
节。完整的文档通过具有帮助意义的 API 指南交付，其中包括有关每个函数调用和经过验证的
参数的详细信息。开发人员可以使用驱动程序库功能，以最低开销编写完整项目。
MSP EnergyTrace™ 技术 适用于 MSP430 微控制器的 EnergyTrace 技术是基于电能的代码分析工具，适
用于测量和显示应用的电能系统配置并帮助优化应用以实现超低功耗。
ULP（超低功耗）Advisor ULP Advisor™软件是一款辅助工具，旨在指导开发人员编写更为高效的代码，
从而充分利用 MSP430 和 MSP432 微控制器 独特 功能。ULP Advisor 的目标人群是微控制器
的资深开发者和开发新手，可以根据详尽的 ULP 检验表检查代码，以便最大限度地减少应用
程序的能耗。在编译时，ULP Advisor 会提供通知和备注以突出显示代码中可以进一步优化的
区域，进而实现更低功耗。
IEC60730 软件包 IEC60730 MSP430 软件包经过专门开发，用于协助客户达到 IEC 60730-1:2010（家用
及类似用途的自动化电气控制 - 第 1 部分：一般要求）B 类产品的要求。其中涵盖家用电器、
电弧检测器、电源转换器、电动工具、电动自行车及其他诸多产品。IEC60730 MSP430 软件
包可以嵌入在 MSP430 MCU 中 运行的客户应用， 从而帮助客户简化其消费类器件在功能安
全方面遵循 IEC 60730-1:2010 B 类规范的认证工作。
适用于 MSP 的定点数学运算库 MSP IQmath 和 Qmath 库是为 C 语言开发者提供的一套经过高度优化的高
精度数学运算函数集合，能够将浮点算法无缝嵌入 MSP430 和 MSP432 器件的定点代码中。
这些例程通常用于计算密集型实时 应用， 而优化的执行速度、高精度以及超低能耗通常是影
响这些实时应用的关键因素。与使用浮点数学算法编写的同等代码相比，使用
Qmath 库可以大幅提高执行速度并显著降低能耗。
IQmath
和
适用于 MSP430 的浮点数学运算库
TI
在低功耗和低成本微控制器领域锐意创新，为您提供
MSPMATHLIB。此标量函数的浮点数学运算库，能够充分利用器件的智能外设，使速度最高
达到标准 MSP430 数学函数的 26 倍。Mathlib 能够轻松集成到您的设计中。该运算库免费使
用并集成在 Code Composer Studio IDE 和 IAR Embedded Workbench IDE 中。
开发工具
适用于 MSP 微控制器的 Code Composer Studio™ 集成开发环境 Code Composer Studio (CCS) 集成开
发环境 (IDE) 支持所有 MSP 微控制器器件。CCS 包含一整套用于开发和调试嵌入式 应用的
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MSP430F5214 MSP430F5212
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
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嵌入式软件实用程序。CCS 包含了优化的 C/C++ 编译器、源代码编辑器、项目构建环境、调
试器、描述器以及其他众多 功能。
命令行编程器 MSP Flasher 是一款基于 shell 的开源接口，可使用 JTAG 或 Spy-Bi-Wire (SBW) 通信通过
FET 编程器或 eZ430 对 MSP 微控制器进行编程。MSP Flasher 可用于将二进制文件（.txt 或
.hex 文件）直接下载到 MSP 微控制器，而无需使用 IDE。
MSP MCU 编程器和调试器 MSP-FET 是一款强大的仿真开发工具（通常称为调试探针），可帮助用户在
MSP 低功耗微控制器 (MCU) 中快速开发应用。创建 MCU 软件通常需要将生成的二进制程序
下载到 MSP 器件中，从而进行验证和调试。
MSP-GANG 生产编程器 MSP Gang 编程器是一款 MSP430 或 MSP432 器件编程器，可同时对多达八个
完全相同的 MSP430 或 MSP432 闪存或 FRAM 器件进行编程。MSP Gang 编程器可使用标
准的 RS-232 或 USB 连接与主机 PC 相连并提供灵活的编程选项，允许用户完全自定义流
程。
7.4 文档支持
以下文档对 MSP430F522x 和 MSP430F521x MCU 进行了介绍。www.ti.com.cn 网站上提供了这些文档的
副本。
接收文档更新通知
要接收文档更新通知（包括芯片勘误表），请转至 ti.com.cn 上您的器件对应的产品文件夹（请参见节 7.5
获取产品文件夹链接）。请单击右上角的“通知我”按钮。点击注册后，即可收到产品信息更改每周摘要（如
有）。有关更改的详细信息，请查阅已修订文档的修订历史记录。
勘误
《MSP430F5229 器件勘误表》 说明了针对 MSP430F5229 器件功能技术规格的已知例外情况。
《MSP430F5227 器件勘误表》 说明了针对 MSP430F5227 器件功能技术规格的已知例外情况。
《MSP430F5224 器件勘误表》 说明了针对 MSP430F5224 器件功能技术规格的已知例外情况。
《MSP430F5222 器件勘误表》 说明了针对 MSP430F5222 器件功能技术规格的已知例外情况。
《MSP430F5219 器件勘误表》 说明了针对 MSP430F5219 器件功能技术规格的已知例外情况。
《MSP430F5217 器件勘误表》 说明了针对 MSP430F5217 器件功能技术规格的已知例外情况。
《MSP430F5214 器件勘误表》 说明了针对 MSP430F5214 器件功能技术规格的已知例外情况。
《MSP430F5212 器件勘误表》 说明了针对 MSP430F5212 器件功能技术规格的已知例外情况。
用户指南
《MSP430F5xx 和 MSP430F6xx 系列用户指南》 详细介绍了该器件系列提供的模块和外设。
《MSP430 闪存器件引导加载程序 (BSL) 用户指南》 MSP430 引导加载程序（bootloader，简称 BSL，以
前称为 bootstrap loader）允许用户在原型设计、最终生产和投用阶段与 MSP430 微控制器中
的嵌入式存储器进行通信。可编程存储器（闪存）和数据存储器 (RAM) 能够按照要求进行变
更。不要将此处的引导加载程序与某些数字信号处理器 (DSP) 中将外部存储器中的程序代码
（和数据）自动加载到 DSP 内部存储器的引导装载程序混为一谈。
《通过 JTAG 接口对 MSP430 进行编程》
此文档介绍了使用 JTAG 通信端口擦除、编程和验证基于
MSP430 闪存和 FRAM 的微控制器系列的存储器模块所需的功能。此外，该文档还介绍了如
何编程所有 MSP430 器件上均具备的 JTAG 访问安全保险丝。此文档介绍了使用标准四线制
JTAG 接口和两线制 JTAG 接口（也称为 Spy-Bi-Wire (SBW)）的器件访问。
《MSP430 硬件工具用户指南》 此手册介绍了 TI MSP-FET430 闪存仿真工具 (FET) 的硬件。FET 是针对
MSP430 超低功耗微控制器的程序开发工具。
应用报告
《使用 MSP430F522x 和 MSP430F521x 器件进行设计》 MSP430F522x 和 MSP430F521x 器件支持双电
源 I/O 系统，在要求 MCU 连接工作电压电平与 MCU 器件电源不同的外部器件（如传感器或
其他处理器）的系统中，该 I/O 系统至关重要。此外，F522x 和 F521x 器件的双电源输入电压
范围低至 1.62V（请参阅器件数据表规格），这样就允许使用标称 1.8V 的 I/O 接口，无需外
部电平转换。该应用报告介绍了在应用中设计 F522x 和 F521x 器件时需要牢记的各种设计注
意事项。
《对 MSP ADC 进行一般过采样以获得更高分辨率》 多个 MSP 超低功耗微控制器可以提供用于将物理量
108
器件和文档支持
版权 © 2012–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217
MSP430F5214 MSP430F5212
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
www.ti.com.cn
转换成数字（这是一种广泛用于大量应用的功能）的模数 转换器 (ADC)。但是，有时客户设计
要求的分辨率会高于所选 MSP 可提供的 ADC 分辨率。该应用报告基于之前发布的《对
ADC12 进行过采样以实现更高的分辨率》(SLAA323)，因此介绍了如何结合过采样方法来提
高 ADC 分辨率，使其超过当前可用的位数。
《MSP430 32kHz 晶体振荡器》 对于稳定的晶体振荡器，选择合适的晶振、正确的负载电路和适当的电路
板布局布线至关重要。该应用报告总结了晶体振荡器的功能，介绍了用于选择合适的晶体以实
现 MSP430 超低功耗运行的参数。此外，还给出了正确电路板布局的提示和示例。此外，为
了确保振荡器在大规模生产后能够稳定运行，还可能需要进行一些振荡器测试，该文档中提供
了有关这些测试的详细信息。
《MSP430 系统级 ESD 注意事项》
随着芯片技术向更低电压方向发展以及设计具有成本效益的超低功耗
组件的需求的出现，系统级 ESD 要求变得越来越苛刻。该应用报告阐述了三个不同的 ESD 主
题，以帮助电路板设计人员和 OEM 了解并实现强大的系统级设计：(1) 组件级 ESD 测试和系
统级 ESD 测试；(2) 实现系统级 ESD 保护的通用设计指南；(3) 系统高效 ESD 设计 (SEED)
简介，这是一种板载和片上 ESD 保护协同设计方法。该应用报告介绍了一些真实的系统级
ESD 保护设计示例及其结果。
版权 © 2012–2018, Texas Instruments Incorporated
器件和文档支持
109
提交文档反馈意见
产品主页链接: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217
MSP430F5214 MSP430F5212
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
ZHCSAJ5H –NOVEMBER 2012–REVISED SEPTEMBER 2018
www.ti.com.cn
7.5 相关链接
表 7-2 列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品
的快速链接。
表 7-2. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
MSP430F5229
MSP430F5227
MSP430F5224
MSP430F5222
MSP430F5219
MSP430F5217
MSP430F5214
MSP430F5212
7.6 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术
规范，并且不一定反映 TI 的观点；请参见 TI 的 《使用条款》。
TI E2E™ 社区
TI 的工程师交流 (E2E) 社区. 此社区的创建目的是为了促进工程师之间协作。在 e2e.ti.com 中，您可以提
问、共享知识、拓展思路，在同领域工程师的帮助下解决问题。
TI 嵌入式处理器维基网页
德州仪器 (TI) 嵌入式处理器维基网页。此网站的建立是为了帮助开发人员熟悉德州仪器 (TI) 的嵌入式处理
器，并且也为了促进与这些器件相关的硬件和软件的总体知识的创新和增长。
7.7 商标
MSP430, MSP430Ware, EnergyTrace, ULP Advisor, 适用于 MSP 微控制器的 Code Composer Studio,
E2E are trademarks of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG.
All other trademarks are the property of their respective owners.
7.8 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
7.9 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
8 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通
知，且不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
110
机械、封装和可订购信息
版权 © 2012–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217
MSP430F5214 MSP430F5212
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430F5212IRGZT
MSP430F5214IRGZR
MSP430F5217IRGCT
MSP430F5217IYFFR
MSP430F5219IYFFT
MSP430F5222IRGZR
MSP430F5222IRGZT
MSP430F5224IRGZR
MSP430F5229IRGCR
MSP430F5229IRGCT
MSP430F5229IYFFR
MSP430F5229IYFFT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
DSBGA
DSBGA
VQFN
VQFN
VQFN
VQFN
VQFN
DSBGA
DSBGA
RGZ
RGZ
RGC
YFF
YFF
RGZ
RGZ
RGZ
RGC
RGC
YFF
YFF
48
48
64
64
64
48
48
48
64
64
64
64
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
F5212
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
NIPDAU
NIPDAU
SNAGCU
SNAGCU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
SNAGCU
SNAGCU
F5214
F5217
M430F5217
M430F5219
F5222
F5222
2500 RoHS & Green
2000 RoHS & Green
F5224
F5229
250
2500 RoHS & Green
250 RoHS & Green
RoHS & Green
F5229
M430F5229
M430F5229
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jan-2021
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430F5212IRGZT
MSP430F5214IRGZR
MSP430F5217IRGCT
MSP430F5217IYFFR
MSP430F5219IYFFT
MSP430F5222IRGZR
MSP430F5222IRGZT
MSP430F5224IRGZR
MSP430F5229IRGCR
MSP430F5229IRGCT
MSP430F5229IYFFR
MSP430F5229IYFFT
VQFN
VQFN
VQFN
DSBGA
DSBGA
VQFN
VQFN
VQFN
VQFN
VQFN
DSBGA
DSBGA
RGZ
RGZ
RGC
YFF
YFF
RGZ
RGZ
RGZ
RGC
RGC
YFF
YFF
48
48
64
64
64
48
48
48
64
64
64
64
250
2500
250
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
330.0
180.0
330.0
180.0
16.4
16.4
16.4
12.4
12.4
16.4
16.4
16.4
16.4
16.4
12.4
12.4
7.3
7.3
7.3
7.3
1.1
1.1
12.0
12.0
12.0
8.0
16.0
16.0
16.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
9.3
9.3
1.1
2500
250
3.54
3.54
7.3
3.66
3.66
7.3
0.81
0.81
1.1
8.0
2500
250
12.0
12.0
12.0
12.0
12.0
8.0
7.3
7.3
1.1
2500
2000
250
7.3
7.3
1.1
9.3
9.3
1.1
9.3
9.3
1.1
2500
250
3.54
3.54
3.66
3.66
0.81
0.81
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430F5212IRGZT
MSP430F5214IRGZR
MSP430F5217IRGCT
MSP430F5217IYFFR
MSP430F5219IYFFT
MSP430F5222IRGZR
MSP430F5222IRGZT
MSP430F5224IRGZR
MSP430F5229IRGCR
MSP430F5229IRGCT
MSP430F5229IYFFR
MSP430F5229IYFFT
VQFN
VQFN
VQFN
DSBGA
DSBGA
VQFN
VQFN
VQFN
VQFN
VQFN
DSBGA
DSBGA
RGZ
RGZ
RGC
YFF
YFF
RGZ
RGZ
RGZ
RGC
RGC
YFF
YFF
48
48
64
64
64
48
48
48
64
64
64
64
250
2500
250
210.0
367.0
210.0
335.0
210.0
367.0
210.0
367.0
367.0
210.0
335.0
182.0
185.0
367.0
185.0
335.0
185.0
367.0
185.0
367.0
367.0
185.0
335.0
182.0
35.0
38.0
35.0
25.0
35.0
38.0
35.0
38.0
38.0
35.0
25.0
20.0
2500
250
2500
250
2500
2000
250
2500
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGC 64
9 x 9, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224597/A
www.ti.com
PACKAGE OUTLINE
RGC0064B
VQFN - 1 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
9.15
8.85
A
B
PIN 1 INDEX AREA
9.15
8.85
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2X 7.5
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
17
32
16
33
65
SYMM
2X 7.5
4.25 0.1
60X
0.5
1
48
0.30
0.18
64X
49
64
PIN 1 ID
0.1
C A B
0.5
0.3
64X
0.05
4219010/A 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGC0064B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.25)
SEE SOLDER MASK
DETAIL
SYMM
64X (0.6)
49
64
64X (0.24)
1
48
60X (0.5)
(R0.05) TYP
(1.18) TYP
(8.8)
65
SYMM
(0.695) TYP
(
0.2) TYP
VIA
33
16
32
17
(0.695) TYP
(1.18) TYP
(8.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219010/A 10/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGC0064B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
64X (0.6)
64
49
64X (0.24)
1
48
60X (0.5)
(R0.05) TYP
9X ( 1.19)
65
SYMM
(8.8)
(1.39)
33
16
17
32
(1.39)
(8.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 65
71% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219010/A 10/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
A
7.1
6.9
B
(0.1) TYP
7.1
6.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
PIN 1 INDEX AREA
(0.45) TYP
CHAMFERED LEAD
CORNER LEAD OPTION
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 5.5
5.15±0.1
(0.2) TYP
13
24
44X 0.5
12
25
SEE SIDE WALL
DETAIL
SYMM
2X
5.5
1
36
0.30
0.18
PIN1 ID
(OPTIONAL)
48X
48
37
SYMM
0.1
C A B
C
0.5
0.3
48X
0.05
SEE LEAD OPTION
4219044/D 02/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
5.15)
SYMM
(
48X (0.6)
37
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(1.26)
2X
(1.065)
(R0.05)
TYP
25
12
21X (Ø0.2) VIA
TYP
24
13
2X (1.065)
2X (1.26)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219044/D 02/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
SYMM
(
1.06)
37
48X (0.6)
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(0.63)
2X
(1.26)
(R0.05)
TYP
25
12
24
13
2X
(1.26)
2X (0.63)
2X (5.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 15X
4219044/D 02/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
D: Max = 3.565 mm, Min =3.505 mm
E: Max = 3.445 mm, Min =3.385 mm
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