MSP430F5522IZXHR [TI]
MSP430F552x, MSP430F551x Mixed-Signal Microcontrollers;
| 型号： | MSP430F5522IZXHR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MSP430F552x, MSP430F551x Mixed-Signal Microcontrollers 微控制器 |
| 文件： | 总139页 (文件大小：4653K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
MSP430F552x, MSP430F551x Mixed-Signal Microcontrollers
•
•
•
16-bit timer TA2, Timer_A with three capture/
compare registers
16-bit timer TB0, Timer_B with seven capture/
compare shadow registers
Two universal serial communication interfaces
(USCIs)
1 Features
•
Low supply voltage range:
3.6 V down to 1.8 V
•
Ultra-low power consumption
– Active mode (AM):
•
All system clocks active:
– USCI_A0 and USCI_A1 each support:
– 290 µA/MHz at 8 MHz, 3.0 V, flash
program execution (typical)
•
Enhanced UART supports automatic baud-
rate detection
– 150 µA/MHz at 8 MHz, 3.0 V, RAM
program execution (typical)
•
•
IrDA encoder and decoder
Synchronous SPI
– Standby mode (LPM3):
– USCI_B0 and USCI_B1 each support:
•
•
I2C
•
Real-time clock (RTC) with crystal,
watchdog, and supply supervisor
operational, full RAM retention, fast wakeup:
– 1.9 µA at 2.2 V, 2.1 µA at 3.0 V (typical)
Low-power oscillator (VLO), general-
purpose counter, watchdog, and supply
supervisor operational, full RAM retention,
fast wakeup:
Synchronous SPI
•
•
Full-speed universal serial bus (USB)
– Integrated USB-PHY
– Integrated 3.3-V and 1.8-V USB power system
– Integrated USB-PLL
– Eight input and eight output endpoints
12-bit analog-to-digital converter (ADC)
(MSP430F552x only) with internal reference,
sample-and-hold, and autoscan features
Comparator
Hardware multiplier supports 32-bit operations
Serial onboard programming, no external
programming voltage needed
3-channel internal DMA
•
– 1.4 µA at 3.0 V (typical)
– Off mode (LPM4):
Full RAM retention, supply supervisor
•
•
•
•
operational, fast wakeup:
– 1.1 µA at 3.0 V (typical)
– Shutdown mode (LPM4.5):
0.18 µA at 3.0 V (typical)
•
•
•
•
•
•
Wake up from standby mode in 3.5 µs (typical)
16-bit RISC architecture, extended memory, up to
25-MHz system clock
Flexible power-management system
– Fully integrated LDO with programmable
regulated core supply voltage
– Supply voltage supervision, monitoring, and
brownout
Unified clock system
– FLL control loop for frequency stabilization
– Low-power low-frequency internal clock source
(VLO)
– Low-frequency trimmed internal reference
source (REFO)
– 32-kHz watch crystals (XT1)
– High-frequency crystals up to 32 MHz (XT2)
16-bit timer TA0, Timer_A with five capture/
compare registers
Basic timer with RTC feature
Development tools and software (also see Tools
and Software)
•
– LaunchPad™ development kit
(MSP‑EXP430F5529LP)
– MSP430F5529 experimenter’s board
(MSP‑EXP430F5529)
– 80-pin target development board
•
(MSP‑TS430PN80USB)
– 64-pin target development board
(MSP‑TS430RGC64USB)
– USB developers package
(MSP430USBDEVPACK)
– MSP430Ware™ code examples
Device Comparison summarizes the available
family members
•
•
•
2 Applications
16-bit timer TA1, Timer_A with three capture/
compare registers
•
•
•
Analog and digital sensor systems
Data loggers
Connection to USB hosts
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
www.ti.com
3 Description
The Texas Instruments MSP430F55xx microcontrollers (MCUs) are part of the MSP430™ system control &
communication family of ultra-low-power microcontrollers consists of several devices featuring peripheral sets
targeted for a variety of applications. The architecture, combined with extensive low-power modes, is optimized
to achieve extended battery life in portable measurement applications. The microcontroller features a powerful
16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The
digitally controlled oscillator (DCO) allows the devices to wake up from low-power modes to active mode in 3.5
µs (typical).
The MSP430F5529, MSP430F5527, MSP430F5525, and MSP430F5521 microcontrollers have integrated USB
and PHY supporting USB 2.0, four 16-bit timers, a high-performance 12-bit analog-to-digital converter (ADC),
two USCIs, a hardware multiplier, DMA, an RTC module with alarm capabilities, and 63 I/O pins. The
MSP430F5528, MSP430F5526, MSP430F5524, and MSP430F5522 microcontrollers include all of these
peripherals but have 47 I/O pins.
The MSP430F5519, MSP430F5517, and MSP430F5515 microcontrollers have integrated USB and PHY
supporting USB 2.0, four 16-bit timers, two USCIs, a hardware multiplier, DMA, an RTC module with alarm
capabilities, and 63 I/O pins. The MSP430F5514 and MSP430FF5513 microcontrollers include all of these
peripherals but have 47 I/O pins.
Typical applications include analog and digital sensor systems, data loggers, and others that require connectivity
to various USB hosts.
The MSP430F55xx MCUs are supported by an extensive hardware and software ecosystem with reference
designs and code examples to get your design started quickly. Development kits include the MSP430F5529 USB
LaunchPad™ development kit and the MSP430F5529 experimenter’s board as well as the MSP-
TS430PN80USB 80-pin target development board and the MSP-TS430RGC64USB 64-pin target development
board. TI also provides free MSP430Ware™ software, which is available as a component of Code Composer
Studio™ IDE desktop and cloud versions within TI Resource Explorer. The MSP430 MCUs are also supported by
extensive online collateral, training, and online support through the TI E2E™ support forum.
For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide.
Device Information
PART NUMBER(1)
MSP430F5529IPN
PACKAGE
BODY SIZE(2)
12 mm × 12 mm
9 mm × 9 mm
See Section 11
5 mm × 5 mm
5 mm × 5 mm
LQFP (80)
MSP430F5528IRGC
MSP430F5528IYFF
MSP430F5528IZXH
MSP430F5528IZQE(3)
VQFN (64)
DSBGA (64)
nFBGA (80)
MicroStar Junior™ BGA (80)
(1) For the most current part, package, and ordering information for all available devices, see the
Package Option Addendum in Section 11, or see the TI website at www.ti.com.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 11.
(3) All orderable part numbers in the ZQE (MicroStar Junior BGA) package have been changed to a
status of Last Time Buy. Visit the Product life cycle page for details on this status.
Copyright © 2020 Texas Instruments Incorporated
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Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525
MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
www.ti.com
4 Functional Block Diagrams
Figure 4-1 shows the functional block diagram for the MSP430F5529, MSP430F5527, MSP430F5525, and
MSP430F5521 devices in the PN package.
PA
PB
PC
PD
XIN XOUT
DVCC DVSS VCORE AVCC AVSS
RST/NMI
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x
DP,DM,PUR
XT2IN
SYS
ACLK
Power
Management
I/O Ports
P1, P2
2×8 I/Os
Interrupt,
Wakeup
I/O Ports
P3, P4
2×8 I/Os
I/O Ports
P5, P6
2×8 I/Os
I/O Ports
P7, P8
1×8 I/Os
1×3 I/Os
Unified
Clock
System
Full-speed
USB
Watchdog
128KB
96KB
64KB
32KB
8KB+2KB
6KB+2KB
4KB+2KB
XT2OUT
SMCLK
Port Map
Control
(P4)
USB-PHY
USB-LDO
USB-PLL
LDO
SVM, SVS
Brownout
MCLK
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
PD
1×11 I/Os
Flash
RAM
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 channels
EEM
(L: 8+2)
ADC12_A
USCI0,1
TA2
TB0
12 Bit
200 ksps
16 Channels
(14 ext, 2 int)
Autoscan
TA0
TA1
USCI_Ax:
UART,
IrDA, SPI
JTAG,
SBW
Interface
REF
COMP_B
RTC_A
MPY32
CRC16
Timer_A
5 CC
Registers
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
Timer_B
7 CC
Registers
12 channels
USCI_Bx:
SPI, I2C
Figure 4-1. Functional Block Diagram – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN,
MSP430F5521IPN
Figure 4-2 shows the functional block diagram for the MSP430F5528, MSP430F5526, MSP430F5524, and
MSP430F5522 devices in the RGC, ZXH, and ZQE packages and for the MSP430F5528 device in the YFF
package.
PA
PB
PC
XIN XOUT
DVCC DVSS VCORE AVCC AVSS
RST/NMI
P1.x P2.x P3.x P4.x P5.x P6.x
DP,DM,PUR
XT2IN
SYS
ACLK
Power
Management
I/O Ports
P1, P2
2×8 I/Os
Interrupt,
Wakeup
I/O Ports
P3, P4
1×5 I/Os
1×8 I/Os
I/O Ports
P5, P6
1×6 I/Os
1×8 I/Os
Unified
Clock
System
Full-speed
USB
Watchdog
128KB
96KB
64KB
32KB
8KB+2KB
6KB+2KB
4KB+2KB
XT2OUT
SMCLK
Port Map
Control
(P4)
USB-PHY
USB-LDO
USB-PLL
LDO
SVM, SVS
Brownout
MCLK
PA
1×16 I/Os
PB
1×13 I/Os
PC
1×14 I/Os
Flash
RAM
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 channels
EEM
(L: 8+2)
ADC12_A
USCI0,1
TA2
TB0
12 Bit
200 ksps
TA0
TA1
USCI_Ax:
UART,
IrDA, SPI
JTAG,
SBW
Interface
REF
COMP_B
RTC_A
MPY32
CRC16
Timer_A
5 CC
Registers
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
Timer_B
7 CC
Registers
8 channels
12 Channels
(10 ext, 2 int)
Autoscan
USCI_Bx:
SPI, I2C
Figure 4-2. Functional Block Diagram – MSP430F5528IRGC, MSP430F5526IRGC, MSP430F5524IRGC,
MSP430F5522IRGC,
MSP430F5528IZXH, MSP430F5526IZXH, MSP430F5524IZXH, MSP430F5522IZXH,
MSP430F5528IZQE, MSP430F5526IZQE, MSP430F5524IZQE, MSP430F5522IZQE,
MSP430F5528IYFF
Copyright © 2020 Texas Instruments Incorporated
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Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525
MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
www.ti.com
Figure 4-3 shows the functional block diagram for the MSP430F5519, MSP430F5517, and MSP430F5515
devices in the PN package.
PA
PB
PC
PD
XIN XOUT
DVCC DVSS VCORE AVCC AVSS
RST/NMI
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x
DP,DM,PUR
XT2IN
SYS
ACLK
Power
Management
I/O Ports
P1, P2
2×8 I/Os
Interrupt
& Wakeup
I/O Ports
P3, P4
2×8 I/Os
I/O Ports
P5, P6
2×8 I/Os
I/O Ports
P7, P8
1×8 I/Os
1×3 I/Os
Unified
Clock
System
Full-speed
USB
Watchdog
128KB
96KB
64KB
4KB+2KB
RAM
XT2OUT
SMCLK
Port Map
Control
(P4)
USB-PHY
USB-LDO
USB-PLL
LDO
SVM, SVS
Brownout
MCLK
Flash
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
PD
1×11 I/Os
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 channels
EEM
(L: 8+2)
USCI0,1
TA0
TA1
TA2
TB0
USCI_Ax:
UART,
IrDA, SPI
JTAG,
SBW
Interface
COMP_B
RTC_A
MPY32
CRC16
REF
Timer_A
5 CC
Registers
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
Timer_B
7 CC
Registers
12 channels
USCI_Bx:
SPI, I2C
Figure 4-3. Functional Block Diagram – MSP430F5519IPN, MSP430F5517IPN, MSP430F5515IPN
Figure 4-4 shows the functional block diagram for the MSP430F5514 and MSP430F5513 devices in the RGC,
ZXH, and ZQE packages.
PA
PB
PC
XIN XOUT
DVCC DVSS VCORE AVCC AVSS
RST/NMI
P1.x P2.x P3.x P4.x P5.x P6.x
DP,DM,PUR
XT2IN
SYS
ACLK
Power
Management
I/O Ports
P1, P2
2×8 I/Os
Interrupt,
Wakeup
I/O Ports
P3, P4
1×5 I/Os
1×8 I/Os
I/O Ports
P5, P6
1×6 I/Os
1×8 I/Os
Unified
Clock
System
Full-speed
USB
Watchdog
64KB
32KB
4KB+2KB
RAM
XT2OUT
SMCLK
Port Map
Control
(P4)
USB-PHY
USB-LDO
USB-PLL
LDO
SVM, SVS
Brownout
MCLK
Flash
PA
1×16 I/Os
PB
1×13 I/Os
PC
1×14 I/Os
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 channels
EEM
(L: 8+2)
USCI0,1
TA0
TA1
TA2
TB0
USCI_Ax:
UART,
IrDA, SPI
JTAG,
SBW
Interface
COMP_B
RTC_A
MPY32
CRC16
REF
Timer_A
5 CC
Registers
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
Timer_B
7 CC
Registers
8 channels
USCI_Bx:
SPI, I2C
Figure 4-4. Functional Block Diagram – MSP430F5514IRGC, MSP430F5513IRGC, MSP430F5514IZXH,
MSP430F5513IZXH, MSP430F5514IZQE, MSP430F5513IZQE
Copyright © 2020 Texas Instruments Incorporated
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Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525
MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................2
4 Functional Block Diagrams............................................ 3
5 Revision History.............................................................. 6
6 Device Comparison.........................................................9
6.1 Related Products........................................................ 9
7 Terminal Configuration and Functions........................10
7.1 Pin Diagrams............................................................ 10
7.2 Signal Descriptions................................................... 16
8 Specifications................................................................ 22
8.1 Absolute Maximum Ratings...................................... 22
8.2 ESD Ratings............................................................. 22
8.3 Recommended Operating Conditions.......................23
8.4 Active Mode Supply Current Into VCC Excluding
8.25 PMM, SVM Low Side..............................................36
8.26 Wake-up Times From Low-Power Modes and
Reset...........................................................................37
8.27 Timer_A...................................................................37
8.28 Timer_B...................................................................37
8.29 USCI (UART Mode) Clock Frequency.................... 38
8.30 USCI (UART Mode)................................................ 38
8.31 USCI (SPI Master Mode) Clock Frequency............ 39
8.32 USCI (SPI Master Mode)........................................ 39
8.33 USCI (SPI Slave Mode).......................................... 41
8.34 USCI (I2C Mode).....................................................43
8.35 12-Bit ADC, Power Supply and Input Range
Conditions................................................................... 44
8.36 12-Bit ADC, Timing Parameters..............................44
8.37 12-Bit ADC, Linearity Parameters Using an
External Current.......................................................... 24
External Reference Voltage or AVCC as
8.5 Low-Power Mode Supply Currents (Into VCC
)
Reference Voltage.......................................................45
8.38 12-Bit ADC, Linearity Parameters Using the
Internal Reference Voltage..........................................45
8.39 12-Bit ADC, Temperature Sensor and Built-In
Excluding External Current..........................................25
8.6 Thermal Resistance Characteristics......................... 26
8.7 Schmitt-Trigger Inputs – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to
P4.7, P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7,
P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)......................... 26
8.8 Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to
P2.7)............................................................................26
8.9 Leakage Current – General-Purpose I/O (P1.0 to
P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)
(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to
P8.2, PJ.0 to PJ.3, RST/NMI)......................................27
8.10 Outputs – General-Purpose I/O (Full Drive
Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to
P3.7, P4.0 to P4.7, P5.0 to P5.7, P6.0 to P6.7,
VMID ............................................................................46
8.40 REF, External Reference........................................ 47
8.41 REF, Built-In Reference.......................................... 47
8.42 Comparator_B.........................................................49
8.43 Ports PU.0 and PU.1...............................................49
8.44 USB Output Ports DP and DM................................51
8.45 USB Input Ports DP and DM...................................51
8.46 USB-PWR (USB Power System)............................51
8.47 USB-PLL (USB Phase-Locked Loop)..................... 52
8.48 Flash Memory......................................................... 52
8.49 JTAG and Spy-Bi-Wire Interface.............................52
9 Detailed Description......................................................53
9.1 CPU.......................................................................... 53
9.2 Operating Modes...................................................... 54
9.3 Interrupt Vector Addresses....................................... 55
9.4 Memory Organization................................................56
9.5 Bootloader (BSL)...................................................... 57
9.6 JTAG Operation........................................................ 58
9.7 Flash Memory........................................................... 59
9.8 RAM..........................................................................59
9.9 Peripherals................................................................59
9.10 Input/Output Diagrams............................................83
9.11 Device Descriptors (TLV)...................................... 107
10 Device and Documentation Support........................113
10.1 Getting Started and Next Steps............................ 113
10.2 Device Nomenclature............................................113
10.3 Tools and Software................................................115
10.4 Documentation Support........................................ 117
10.5 Related Links........................................................ 119
10.6 Support Resources............................................... 120
10.7 Trademarks...........................................................120
10.8 Electrostatic Discharge Caution............................120
10.9 Export Control Notice............................................120
10.10 Glossary..............................................................120
11 Mechanical, Packaging, and Orderable
P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3).................... 27
8.11 Outputs – General-Purpose I/O (Reduced Drive
Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to
P3.7, P4.0 to P4.7, P5.0 to P5.7, P6.0 to P6.7,
P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3).................... 27
8.12 Output Frequency – General-Purpose I/O (P1.0
to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7,
P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to
P8.2, PJ.0 to PJ.3)...................................................... 28
8.13 Typical Characteristics – Outputs, Reduced
Drive Strength (PxDS.y = 0)........................................29
8.14 Typical Characteristics – Outputs, Full Drive
Strength (PxDS.y = 1)................................................. 30
8.15 Crystal Oscillator, XT1, Low-Frequency Mode........31
8.16 Crystal Oscillator, XT2............................................ 32
8.17 Internal Very-Low-Power Low-Frequency
Oscillator (VLO)...........................................................33
8.18 Internal Reference, Low-Frequency Oscillator
(REFO)........................................................................33
8.19 DCO Frequency......................................................34
8.20 PMM, Brownout Reset (BOR).................................35
8.21 PMM, Core Voltage.................................................35
8.22 PMM, SVS High Side..............................................35
8.23 PMM, SVM High Side............................................. 36
8.24 PMM, SVS Low Side...............................................36
Information.................................................................. 121
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Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525
MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
www.ti.com
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from revision O to revision P
Changes from May 1, 2019 to September 11, 2020
Page
•
•
•
•
•
Updated the numbering for sections, tables, figures, and cross-references throughout the document..............1
Added nFBGA package (ZXH) information throughout document......................................................................2
Added note about status change for all orderable part numbers in the ZQE package in Device Information ... 2
Added note (1) in Section 8.6, Thermal Resistance Characteristics ............................................................... 26
Changed the MAX value of the IERASE and IMERASE, IBANK parameters in Section 8.48, Flash Memory ......... 52
Changes from revision N to revision O
Changes from September 21, 2018 to April 30, 2019
Page
•
•
•
Updated Section 1, Features .............................................................................................................................1
Updated Section 3, Description ......................................................................................................................... 2
Removed the YFF package option for the MSP430F5526 and MSP430F5524 in Section 4, Functional Block
Diagrams ........................................................................................................................................................... 3
Removed the YFF package option for the MSP430F5526 and MSP430F5524 in Section 6, Device
Comparison ....................................................................................................................................................... 9
Removed the YFF package option for the MSP430F5526 and MSP430F5524 in Figure 7-6, 64-Pin YFF
Package – MSP430F5528IYFF .......................................................................................................................10
•
•
Changes from revision M to revision N
Changes from November 3, 2015 to September 20, 2018
Page
•
•
•
Changed entry for Body Size of DSBGA package in Device Information table .................................................2
Added Section 6.1, Related Products ................................................................................................................9
Removed D and E dimension lines from the YFF pinout (for package dimensions, see the Mechanical Data in
Section 11) .......................................................................................................................................................10
Added typical conditions statements at the beginning of Section 8, Specifications .........................................22
Changed the MIN value of the V(DVCC_BOR_hys) parameter from 60 mV to 50 mV in Section 8.20, PMM,
Brownout Reset (BOR) ....................................................................................................................................35
Updated notes (1) and (2) and added note (3) in Section 8.26, Wake-up Times From Low-Power Modes and
Reset ............................................................................................................................................................... 37
Removed ADC12DIV from the formula for the TYP value in the second row of the tCONVERT parameter in
Section 8.36, 12-Bit ADC, Timing Parameters, because ADC12CLK is after division..................................... 44
Added second row for tEN_CMP with Test Conditions of "CBPWRMD = 10" and MAX value of 100 µs in Section
8.42, Comparator_B ........................................................................................................................................ 49
Renamed FCTL4.MGR0 and MGR1 bits in the fMCLK,MGR parameter in Section 8.48, Flash Memory, to be
consistent with header files ..............................................................................................................................52
Throughout document, changed all instances of "bootstrap loader" to "bootloader"........................................57
Added YFF pin numbers to Table 9-11, TA0 Signal Connections ....................................................................65
Added YFF pin numbers to Table 9-12, TA1 Signal Connections ....................................................................66
Added YFF pin numbers to Table 9-13, TA2 Signal Connections ....................................................................67
Replaced former section Development Tools Support with Section 10.3, Tools and Software ......................115
Changed format and added content to Section 10.4, Documentation Support ..............................................117
•
•
•
•
•
•
•
•
•
•
•
•
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Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525
MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Changes from revision L to revision M
Changes from June 17, 2013 to November 2, 2015
Page
•
•
•
•
•
•
•
•
•
•
Added Device Information table..........................................................................................................................2
Added Section 4 and moved all functional block diagrams to it..........................................................................3
Added Section 6 and moved Table 6-1 table to it............................................................................................... 9
Added Section 8.2, ESD Ratings .....................................................................................................................22
Moved Section 8.6, Thermal Resistance Characteristics ................................................................................ 26
Changed the TYP value of CL,eff with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF.................31
Corrected MRG0 and MRG1 bit names in fMCLK,MRG parameter description................................................... 52
Corrected spelling of NMIIFG in Table 9-9, System Module Interrupt Vector Registers ..................................62
Corrected register names (added "USB" prefix as necessary) in Table 9-45, USB Control Registers ............ 70
Changed P5.3 schematic (added P5SEL.2 and XT2BYPASS inputs, AND gate, and OR gate after P5SEL.3)..
92
•
•
Changed P5SEL.3 column from X to 0 for "P5.3 (I/O)" rows............................................................................92
Changed P5.5 schematic (change input from P5SEL.5 to P5SEL.4 and added P5SEL.5 input and the
following OR gate)............................................................................................................................................ 94
Changed P5SEL.5 column from X to 0 for "P5.5 (I/O)" rows............................................................................94
Added Section 11, Mechanical, Packaging, and Orderable Information ........................................................121
•
•
The following table lists the changes to this data sheet from the initial release through revision L.
REVISION
DESCRIPTION
Production release of F5226 and F5224 in YFF package.
SLAS590L
June 2013
Section 7.2, Added note regarding pullup resistor on RST/NMI/SBWTDIO pin.
Figure 7-6, Added ball-side view and changed top-side view.
SLAS590K
February 2013
Section 8.48, Changed IERASE and IMERASE values.
Section 8.3, Added TYP test conditions
SLAS590J
December 2012
Section 8.19, Added note (1)
Section 8.48, Restored Flash erase currents to previous values (changed from TBD).
Changed MSP430F5528IYFF to Production Data.
Section 7.2, Changed PUR pin description.
Section 9.5.1, Added note regarding PUR pin.
SLAS590I
August 2012
Table 9-9, Changed SYSRSTIV interrupt event with value 1Ch to Reserved.
Section 8.3, Added note regarding interaction between minimum VCC and SVSH.
Section 8.39, Changed tSENSOR(sample) MIN to 100 µs, and changed note (2).
Corrected lost and corrupted symbols throughout. Affected symbols include: Δ θ Ω → ≥ ≤ ≠
Changed ACLK signal description in Section 7.2.
SLAS590H
February 2012
Changed note on Section 8.37.
Changed notes regarding UCA0CLK and UCB0CLK function on Table 9-47 and Table 9-48.
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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REVISION
DESCRIPTION
Changed limits for wake-up time, LPM3/4 current, reference current, ADC12 maximum frequency, ADC linearity — see
the following tables:
Section 8.5
Section 8.35
Section 8.36
Section 8.37
Section 8.38
Section 8.40
Section 8.41
SLAS590G
November 2011
Changed notes regarding crystal capacitance in Section 8.15
SLAS590F
November 2011
Corrected terminal assignments for YFF package in Section 7.1 and Section 7.2
Updated YFF and ZQE pinout drawings.
SLAS590E
April 2011
Changed Tstg maximum to 150°C in Section 8.1.
Changed fXT2,HF,SW MIN to 0.7 MHz in Section 8.16.
SLAS590D
April 2010
Production data release
SLAS590C
January 2010
Changes throughout for updated preview
Changes throughout for updated preview
Changes throughout for XMS430F5529 sampling
Limited product preview release
SLAS590B
July 2009
SLAS590A
May 2009
SLAS590
September 2008
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
www.ti.com
6 Device Comparison
Table 6-1 summarizes the available family members.
Table 6-1. Device Comparison
USCI_A:
UART, IrDA,
SPI
FLASH
(KB)
SRAM
(KB)(5)
USCI_B:
SPI, I2C
ADC12_A
(channels)
COMP_B
(channels)
DEVICE(1) (2)
Timer_A(3)
Timer_B(4)
I/Os
PACKAGE
MSP430F5529
128
128
8 + 2
8 + 2
5, 3, 3
7
2
2
2
14 ext, 2 int
10 ext, 2 int
12
8
63
80 PN
64 RGC,
64 YFF,
80 ZXH,
80 ZQE
MSP430F5528
5, 3, 3
7
2
47
MSP430F5527
MSP430F5526
MSP430F5525
MSP430F5524
96
96
64
64
6 + 2
6 + 2
4 + 2
4 + 2
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
7
7
7
7
2
2
2
2
2
2
2
2
14 ext, 2 int
10 ext, 2 int
14 ext, 2 int
10 ext, 2 int
12
8
63
47
63
47
80 PN
64 RGC,
80 ZXH,
80 ZQE
12
8
80 PN
64 RGC,
80 ZXH,
80 ZQE
64 RGC,
80 ZXH,
80 ZQE
MSP430F5522
32
8 + 2
5, 3, 3
7
2
2
10 ext, 2 int
8
47
MSP430F5521
MSP430F5519
MSP430F5517
MSP430F5515
32
128
96
6 + 2
8 + 2
6 + 2
4 + 2
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
7
7
7
7
2
2
2
2
2
2
2
2
14 ext, 2 int
12
12
12
12
63
63
63
63
80 PN
80 PN
80 PN
80 PN
–
–
–
64
64 RGC,
80 ZXH,
80 ZQE
MSP430F5514
MSP430F5513
64
32
4 + 2
4 + 2
5, 3, 3
5, 3, 3
7
7
2
2
2
2
–
–
8
8
47
47
64 RGC,
80 ZXH,
80 ZQE
(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section
11, or see the TI website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and
PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and
PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
(5) The additional 2KB of USB SRAM that is listed can be used as general-purpose SRAM when USB is not in use.
6.1 Related Products
For information about other devices in this family of products or related products, see the following links.
TI 16-bit and 32-bit microcontrollers
High-performance, low-power solutions to enable the autonomous future
Products for MSP430 ultra-low-power sensing & measurement MCUs
One platform. One ecosystem. Endless possibilities.
Companion products for MSP430F5529
Review products that are frequently purchased or used with this product.
Reference designs for MSP430F5529
Find reference designs leveraging the best in TI technology to solve your system-level challenges.
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Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525
MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
www.ti.com
7 Terminal Configuration and Functions
7.1 Pin Diagrams
Figure 7-1 shows the pinout for the MSP430F5529, MSP430F5527, MSP430F5525, and MSP430F5521 devices
in the 80-pin PN package.
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P7.7/TB0CLK/MCLK
P7.6/TB0.4
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6
P6.7/CB7/A7
P7.0/CB8/A12
P7.1/CB9/A13
2
3
P7.5/TB0.3
4
P7.4/TB0.2
5
P5.7/TB0.1
6
P5.6/TB0.0
P4.7/PM_NONE
P7.2/CB10/A14
P7.3/CB11/A15
7
P4.6/PM_NONE
8
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF−/VeREF−
AVCC1
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P4.4/PM_UCA1TXD/PM_UCA1SIMO
DVCC2
9
MSP430F5529
MSP430F5527
MSP430F5525
MSP430F5521
10
11
12
13
14
15
16
17
18
19
20
DVSS2
P5.4/XIN
P5.5/XOUT
AVSS1
P4.3/PM_UCB1CLK/PM_UCA1STE
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P4.0/PM_UCB1STE/PM_UCA1CLK
P8.0
P8.1
P8.2
P3.7/TB0OUTH/SVMOUT
P3.6/TB0.6
DVCC1
DVSS1
VCORE
P3.5/TB0.5
P3.4/UCA0RXD/UCA0SOMI
A0.3
A0.4
A1.0
P1.4/T
P1.5/T
P1.7/T
A2CLK/SMCLK
A1CLK/CBOUT
P2.2/T
P1.6/T
Figure 7-1. 80-Pin PN Package (Top View) – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN,
MSP430F5521IPN
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
www.ti.com
Figure 7-2 shows the pinout for the MSP430F5528, MSP430F5526, MSP430F5524, and MSP430F5522 devices
in the 64-pin RGC package.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P4.7/PM_NONE
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P6.0/CB0/A0
P6.1/CB1/A1
P4.6/PM_NONE
2
3
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P4.4/PM_UCA1TXD/PM_UCA1SIMO
P4.3/PM_UCB1CLK/PM_UCA1STE
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P4.0/PM_UCB1STE/PM_UCA1CLK
DVCC2
P6.2/CB2/A2
4
P6.3/CB3/A3
P6.4/CB4/A4
5
P6.5/CB5/A5
6
P6.6/CB6/A6
7
MSP430F5528
MSP430F5526
MSP430F5524
MSP430F5522
P6.7/CB7/A7
8
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF−/VeREF−
AVCC1
9
DVSS2
10
11
12
13
14
15
16
P3.4/UCA0RXD/UCA0SOMI
P3.3/UCA0TXD/UCA0SIMO
P3.2/UCB0CLK/UCA0STE
P3.1/UCB0SOMI/UCB0SCL
P3.0/UCB0SIMO/UCB0SDA
P2.7/UCB0STE/UCA0CLK
P5.4/XIN
P5.5/XOUT
AVSS1
DVCC1
DVSS1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
A0.3
A0.4
A1.0
A1.2
A1.1
P1.4/T
P1.5/T
P1.7/T
P2.1/T
P2.0/T
A1CLK/CBOUT
A2CLK/SMCLK
P1.6/T
P2.2/T
TI recommends connecting the exposed thermal pad to VSS
.
Figure 7-2. 64-Pin RGC Package (Top View) – MSP430F5528IRGC, MSP430F5526IRGC,
MSP430F5524IRGC, MSP430F5522IRGC
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
www.ti.com
Figure 7-3 shows the pinout for the MSP430F5519, MSP430F5517, and MSP430F5515 devices in the 80-pin
PN package.
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P7.7/TB0CLK/MCLK
P7.6/TB0.4
P6.4/CB4
P6.5/CB5
P6.6/CB6
P6.7/CB7
P7.0/CB8
P7.1/CB9
2
3
P7.5/TB0.3
4
P7.4/TB0.2
5
P5.7/TB0.1
6
P5.6/TB0.0
P4.7/PM_NONE
P7.2/CB10
P7.3/CB11
P5.0
7
P4.6/PM_NONE
8
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P4.4/PM_UCA1TXD/PM_UCA1SIMO
DVCC2
9
MSP430F5519
MSP430F5517
MSP430F5515
P5.1
10
11
12
13
14
15
16
17
18
19
20
AVCC1
DVSS2
P5.4/XIN
P5.5/XOUT
AVSS1
P4.3/PM_UCB1CLK/PM_UCA1STE
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P4.0/PM_UCB1STE/PM_UCA1CLK
P8.0
P8.1
P8.2
P3.7/TB0OUTH/SVMOUT
P3.6/TB0.6
DVCC1
DVSS1
VCORE
P3.5/TB0.5
P3.4/UCA0RXD/UCA0SOMI
A0.3
A0.4
A1.0
P1.4/T
P1.5/T
P1.7/T
A2CLK/SMCLK
A1CLK/CBOUT
P2.2/T
P1.6/T
Figure 7-3. 80-Pin PN Package (Top View) – MSP430F5519IPN, MSP430F5517IPN, MSP430F5515IPN
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
www.ti.com
Figure 7-4 shows the pinout for the MSP430F5514 and MSP430F5513 devices in the 64-pin RGC package.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P4.7/PM_NONE
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P6.0/CB0
P6.1/CB1
P6.2/CB2
P6.3/CB3
P6.4/CB4
P6.5/CB5
P6.6/CB6
P6.7/CB7
P5.0
P4.6/PM_NONE
2
3
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P4.4/PM_UCA1TXD/PM_UCA1SIMO
P4.3/PM_UCB1CLK/PM_UCA1STE
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P4.0/PM_UCB1STE/PM_UCA1CLK
DVCC2
4
5
6
7
8
MSP430F5514
MSP430F5513
9
P5.1
DVSS2
10
11
12
13
14
15
16
AVCC1
P3.4/UCA0RXD/UCA0SOMI
P3.3/UCA0TXD/UCA0SIMO
P3.2/UCB0CLK/UCA0STE
P3.1/UCB0SOMI/UCB0SCL
P3.0/UCB0SIMO/UCB0SDA
P2.7/UCB0STE/UCA0CLK
P5.4/XIN
P5.5/XOUT
AVSS1
DVCC1
DVSS1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
A1.1
A0.3
A0.4
A1.0
A1.2
P2.0/T
P1.4/T
P1.5/T
P1.7/T
P2.1/T
A2CLK/SMCLK
A1CLK/CBOUT
P2.2/T
P1.6/T
TI recommends connecting the exposed thermal pad to VSS
.
Figure 7-4. 64-Pin RGC Package (Top View) – MSP430F5514IRGC, MSP430F5513IRGC
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
www.ti.com
Figure 7-5 shows the pinout for the MSP430F5528, MSP430F5526, MSP430F5524, MSP430F5522,
MSP430F5514, and MSP430F5513 devices in the 80-pin ZXH or ZQE package.
P6.0 RST/NMI PJ.2
TEST AVSS2 VUSB VBUS
PU.1
A8
PU.0
A9
A1
A2
A3
A4
A5
A6
A7
P6.2
B1
P6.1
B2
PJ.3
B3
P5.3
B4
P5.2
B5
V18
B6
PUR
B7
VSSU VSSU
B8
B9
P6.4
C1
PJ.0 Reserved
C5 C6
P4.6
C8
P4.5
C9
P6.3
C2
PJ.1
C4
P4.7
C7
P6.6
D1
P6.5
D2
P6.7 Reserved Reserved Reserved P4.4
D3 D4 D7
D5 D6
P4.3
D8
P4.2
D9
P5.0
E1
P5.1 Reserved Reserved Reserved Reserved P4.1
E2 E3 E4 E7
E5 E6
P4.0 DVCC2
E8 E9
P5.4 AVCC1 Reserved Reserved Reserved Reserved Reserved Reserved DVSS2
F1
F2
F3
F4
F5
F6
F7
F8
F9
P5.5 AVSS1 Reserved P1.3
P1.6
G5
P2.1
G6
P3.4
G7
P3.2
G8
P3.3
G9
G1
G2
G3
G4
DVCC1 P1.0
H1 H2
P1.1
H3
P1.4
H4
P1.7
H5
P2.3
H6
P2.7
H7
P3.0
H8
P3.1
H9
DVSS1 VCORE P1.2
J1 J2 J3
P1.5
J4
P2.0
J5
P2.2
J6
P2.4
J7
P2.5
J8
P2.6
J9
Figure 7-5. 80-Pin ZXH or ZQE Package (Top View) –
MSP430F5528IZXH, MSP430F5526IZXH, MSP430F5524IZXH, MSP430F5522IZXH, MSP430F5514IZXH,
MSP430F5513IZXH,
MSP430F5528IZQE, MSP430F5526IZQE, MSP430F5524IZQE, MSP430F5522IZQE, MSP430F5514IZQE,
MSP430F5513IZQE
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
www.ti.com
Figure 7-6 shows the pinout for the MSP430F5528 device in the 64-pin YFF package. For package dimensions,
see the Mechanical Data in Section 11.
Top View
Ball-Side View
H8
H7
H6
H5
H4
H3
H2
H1
H1
H2
H3
H4
H5
H6
H7
H8
P2.7
P3.1 DVSS2 DVCC2 P4.1
P4.4 VSSU PU.0
PU.0
P4.4
P4.1 DVCC2 DVSS2 P3.1
P2.7
VSSU
G8
G7
G6
G5
G4
G3
G2
G1
G1
G2
G3
G4
G5
G6
G7
G8
P3.0
P3.2
P3.3
P3.4
P4.2
P4.5
PUR
PU.1
PU.1
PUR
P4.5
P4.2
P3.4
P3.3
P3.2
P3.0
F8
F7
F6
F5
F4
F3
F2
F1
F1
F2
F3
F4
F5
F6
F7
F8
P2.4
P2.5
P2.6
P4.0
P4.3
P4.6 VBUS VUSB
VUSB VBUS P4.6
P4.3
P4.0
P2.6
P2.5
P2.4
E8
E7
E6
E5
E4
E3
E2
E1
E1
E2
E3
E4
E5
E6
E7
E8
P2.1
P2.2
P2.0
P4.7 TEST
V18
P5.2
P5.2
V18
TEST P4.7
P2.0
P2.2
P2.1
P2.3
P2.3
D8
D7
D6
D5
D4 D3
D2
D1
D1
D2
D3 D4
D5
D6
D7
D8
P1.7
P1.6
P1.5 RST/NMI PJ.1
PJ.0 AVSS2 P5.3
P5.3 AVSS2 PJ.0
PJ.1 RST/NMI P1.5
P1.6
P1.7
C8
C7
C6
C5
C4
C2
C1
C1
C2
C4
C5
C6
C7
C8
C3
C3
P1.3
P1.4
P1.2
P6.7
P6.3
PJ.3
PJ.2
PJ.2
PJ.3
P6.3
P6.7
P1.2
P1.4
P1.3
P6.1
P6.1
B8
B7
B6
B5
B4
B3
B2
B1
B1
B2
B3
B4
B5
B6
B7
B8
VCORE P1.0
P1.1
P5.1
P5.0
P6.5
P6.4
P6.0
P6.0
P6.4
P6.5
P5.0
P5.1
P1.1
P1.0 VCORE
A8
A7
A6
A5
A4
A3
A2
A1
A1
A2
A3
A4
A5
A6
A7
A8
DVSS1 DVCC1 P5.5
P5.4 AVSS1 AVCC1 P6.6
P6.2
P6.2
P6.6 AVCC1 AVSS1 P5.4
P5.5 DVCC1 DVSS1
Figure 7-6. 64-Pin YFF Package – MSP430F5528IYFF
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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7.2 Signal Descriptions
Table 7-1 describes the signals for all device and package options.
Table 7-1. Terminal Functions
TERMINAL
NO.
I/O(1)
DESCRIPTION
NAME
ZXH,
ZQE
PN
RGC YFF
General-purpose digital I/O
I/O Comparator_B input CB4
P6.4/CB4/A4
1
5
6
7
8
B2
B3
A2
C5
C1
D2
D1
D3
Analog input A4 for ADC (not available on F551x devices)
General-purpose digital I/O
P6.5/CB5/A5
P6.6/CB6/A6
P6.7/CB7/A7
2
3
4
I/O Comparator_B input CB5
Analog input A5 for ADC (not available on F551x devices)
General-purpose digital I/O
I/O Comparator_B input CB6
Analog input A6 for ADC (not available on F551x devices)
General-purpose digital I/O
I/O Comparator_B input CB7
Analog input A7 for ADC (not available on F551x devices)
General-purpose digital I/O (not available on F5528, F5526, F5524,
F5522, F5514, F5513 devices)
P7.0/CB8/A12
P7.1/CB9/A13
P7.2/CB10/A14
P7.3/CB11/A15
5
6
7
8
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
I/O Comparator_B input CB8 (not available on F5528, F5526, F5524,
F5522, F5514, F5513 devices)
Analog input A12 for ADC (not available on F551x devices)
General-purpose digital I/O (not available on F5528, F5526, F5524,
F5522, F5514, F5513 devices)
I/O Comparator_B input CB9 (not available on F5528, F5526, F5524,
F5522, F5514, F5513 devices)
Analog input A13 for ADC (not available on F551x devices)
General-purpose digital I/O (not available on F5528, F5526, F5524,
F5522, F5514, F5513 devices)
I/O Comparator_B input CB10 (not available on F5528, F5526, F5524,
F5522, F5514, F5513 devices)
Analog input A14 for ADC (not available on F551x devices)
General-purpose digital I/O (not available on F5528, F5526, F5524,
F5522, F5514, F5513 devices)
I/O Comparator_B input CB11 (not available on F5528, F5526, F5524,
F5522, F5514, F5513 devices)
Analog input A15 for ADC (not available on F551x devices)
General-purpose digital I/O
Output of reference voltage to the ADC (not available on F551x
devices)
P5.0/A8/VREF+/VeREF+
9
9
B4
E1
I/O
Input for an external reference voltage to the ADC (not available on
F551x devices)
Analog input A8 for ADC (not available on F551x devices)
General-purpose digital I/O
Negative terminal for the ADC reference voltage for both sources, the
I/O internal reference voltage, or an external applied reference voltage (not
available on F551x devices)
P5.1/A9/VREF-/VeREF-
AVCC1
10
11
10
11
B5
A3
E2
F2
Analog input A9 for ADC (not available on F551x devices)
Analog power supply
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Table 7-1. Terminal Functions (continued)
TERMINAL
NO.
I/O(1)
DESCRIPTION
NAME
ZXH,
ZQE
PN
RGC YFF
General-purpose digital I/O
P5.4/XIN
12
12
13
A5
A6
F1
I/O
I/O
Input terminal for crystal oscillator XT1
General-purpose digital I/O
P5.5/XOUT
13
G1
Output terminal of crystal oscillator XT1
Analog ground supply
AVSS1
P8.0
14
15
16
17
18
19
14
N/A
N/A
N/A
15
A4
N/A
N/A
N/A
A7
G2
N/A
N/A
N/A
H1
I/O General-purpose digital I/O
I/O General-purpose digital I/O
I/O General-purpose digital I/O
Digital power supply
P8.1
P8.2
DVCC1
DVSS1
16
A8
J1
Digital ground supply
Regulated core power supply output (internal use only, no external
current loading)
VCORE(3)
20
17
B8
J2
General-purpose digital I/O with port interrupt
I/O TA0 clock signal TA0CLK input
P1.0/TA0CLK/ACLK
21
18
B7
H2
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
General-purpose digital I/O with port interrupt
I/O TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output
P1.1/TA0.0
P1.2/TA0.1
22
23
19
20
B6
C6
H3
J3
General-purpose digital I/O with port interrupt
I/O TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input
General-purpose digital I/O with port interrupt
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
24
25
26
21
22
23
C8
C7
D6
G4
H4
J4
I/O
TA0 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O with port interrupt
I/O
TA0 CCR3 capture: CCI3A input compare: Out3 output
General-purpose digital I/O with port interrupt
I/O
TA0 CCR4 capture: CCI4A input, compare: Out4 output
General-purpose digital I/O with port interrupt
I/O TA1 clock signal TA1CLK input
Comparator_B output
P1.6/TA1CLK/CBOUT
27
24
D7
G5
General-purpose digital I/O with port interrupt
P1.7/TA1.0
P2.0/TA1.1
P2.1/TA1.2
28
29
30
25
26
27
D8
E5
E8
H5
J5
I/O
TA1 CCR0 capture: CCI0A input, compare: Out0 output
General-purpose digital I/O with port interrupt
I/O
TA1 CCR1 capture: CCI1A input, compare: Out1 output
General-purpose digital I/O with port interrupt
G6
I/O
TA1 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O with port interrupt
I/O TA2 clock signal TA2CLK input
SMCLK output
P2.2/TA2CLK/SMCLK
31
28
E7
J6
General-purpose digital I/O with port interrupt
P2.3/TA2.0
P2.4/TA2.1
32
33
29
30
E6
F8
H6
J7
I/O
TA2 CCR0 capture: CCI0A input, compare: Out0 output
General-purpose digital I/O with port interrupt
I/O
TA2 CCR1 capture: CCI1A input, compare: Out1 output
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
www.ti.com
Table 7-1. Terminal Functions (continued)
TERMINAL
NO.
I/O(1)
DESCRIPTION
NAME
ZXH,
ZQE
PN
RGC YFF
General-purpose digital I/O with port interrupt
TA2 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O with port interrupt
P2.5/TA2.2
34
31
32
F7
F6
J8
I/O
P2.6/RTCCLK/DMAE0
35
36
J9
I/O RTC clock output for calibration
DMA external trigger input
General-purpose digital I/O with port interrupt
Slave transmit enable – USCI_B0 SPI mode
I/O
P2.7/UCB0STE/UCA0CLK
33
H8
H7
Clock signal input – USCI_A0 SPI slave mode
Clock signal output – USCI_A0 SPI master mode
General-purpose digital I/O
P3.0/UCB0SIMO/
UCB0SDA
37
38
34
35
G8
H7
H8
H9
I/O Slave in, master out – USCI_B0 SPI mode
I2C data – USCI_B0 I2C mode
General-purpose digital I/O
P3.1/UCB0SOMI/
UCB0SCL
I/O Slave out, master in – USCI_B0 SPI mode
I2C clock – USCI_B0 I2C mode
General-purpose digital I/O
Clock signal input – USCI_B0 SPI slave mode
I/O
P3.2/UCB0CLK/UCA0STE
39
36
G7
G8
Clock signal output – USCI_B0 SPI master mode
Slave transmit enable – USCI_A0 SPI mode
General-purpose digital I/O
P3.3/UCA0TXD/
UCA0SIMO
40
41
37
38
G6
G5
G9
G7
I/O Transmit data – USCI_A0 UART mode
Slave in, master out – USCI_A0 SPI mode
General-purpose digital I/O
P3.4/UCA0RXD/
UCA0SOMI
I/O Receive data – USCI_A0 UART mode
Slave out, master in – USCI_A0 SPI mode
General-purpose digital I/O (not available on F5528, F5526, F5524,
F5522, F5514, F5513 devices)
P3.5/TB0.5
P3.6/TB0.6
42
43
N/A
N/A
N/A
N/A
N/A
N/A
I/O
I/O
TB0 CCR5 capture: CCI5A input, compare: Out5 output
General-purpose digital I/O (not available on F5528, F5526, F5524,
F5522, F5514, F5513 devices)
TB0 CCR6 capture: CCI6A input, compare: Out6 output
General-purpose digital I/O (not available on F5528, F5526, F5524,
F5522, F5514, F5513 devices)
Switch all PWM outputs high impedance input – TB0 (not available on
F5528, F5526, F5524, F5522, F5514, F5513 devices)
P3.7/TB0OUTH/SVMOUT
44
N/A
N/A
N/A
I/O
SVM output (not available on F5528, F5526, F5524, F5522, F5514,
F5513 devices)
General-purpose digital I/O with reconfigurable port mapping secondary
function
P4.0/PM_UCB1STE/
PM_UCA1CLK
Default mapping: Slave transmit enable – USCI_B1 SPI mode
Default mapping: Clock signal input – USCI_A1 SPI slave mode
Default mapping: Clock signal output – USCI_A1 SPI master mode
45
46
41
42
F5
H4
E8
E7
I/O
I/O
General-purpose digital I/O with reconfigurable port mapping secondary
function
P4.1/PM_UCB1SIMO/
PM_UCB1SDA
Default mapping: Slave in, master out – USCI_B1 SPI mode
Default mapping: I2C data – USCI_B1 I2C mode
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Table 7-1. Terminal Functions (continued)
TERMINAL
NO.
I/O(1)
DESCRIPTION
NAME
ZXH,
ZQE
PN
RGC YFF
General-purpose digital I/O with reconfigurable port mapping secondary
function
P4.2/PM_UCB1SOMI/
PM_UCB1SCL
47
43
44
G4
F4
D9
I/O
Default mapping: Slave out, master in – USCI_B1 SPI mode
Default mapping: I2C clock – USCI_B1 I2C mode
General-purpose digital I/O with reconfigurable port mapping secondary
function
P4.3/PM_UCB1CLK/
PM_UCA1STE
Default mapping: Clock signal input – USCI_B1 SPI slave mode
Default mapping: Clock signal output – USCI_B1 SPI master mode
Default mapping: Slave transmit enable – USCI_A1 SPI mode
Digital ground supply
48
D8
I/O
DVSS2
DVCC2
49
50
39
40
H6
H5
F9
E9
Digital power supply
General-purpose digital I/O with reconfigurable port mapping secondary
function
P4.4/PM_UCA1TXD/
PM_UCA1SIMO
51
52
45
46
H3
G3
D7
C9
I/O
I/O
Default mapping: Transmit data – USCI_A1 UART mode
Default mapping: Slave in, master out – USCI_A1 SPI mode
General-purpose digital I/O with reconfigurable port mapping secondary
function
P4.5/PM_UCA1RXD/
PM_UCA1SOMI
Default mapping: Receive data – USCI_A1 UART mode
Default mapping: Slave out, master in – USCI_A1 SPI mode
General-purpose digital I/O with reconfigurable port mapping secondary
function
P4.6/PM_NONE
P4.7/PM_NONE
53
54
47
48
F3
E4
C8
C7
I/O
I/O
Default mapping: no secondary function.
General-purpose digital I/O with reconfigurable port mapping secondary
function
Default mapping: no secondary function.
General-purpose digital I/O (not available on F5528, F5526, F5524,
F5522, F5514, F5513 devices)
P5.6/TB0.0
P5.7/TB0.1
P7.4/TB0.2
P7.5/TB0.3
55
56
57
58
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
I/O
I/O
I/O
I/O
TB0 CCR0 capture: CCI0A input, compare: Out0 output (not available
on F5528, F5526, F5524, F5522, F5514, F5513 devices)
General-purpose digital I/O (not available on F5528, F5526, F5524,
F5522, F5514, F5513 devices)
TB0 CCR1 capture: CCI1A input, compare: Out1 output (not available
on F5528, F5526, F5524, F5522, F5514, F5513 devices)
General-purpose digital I/O (not available on F5528, F5526, F5524,
F5522, F5514, F5513 devices)
TB0 CCR2 capture: CCI2A input, compare: Out2 output (not available
on F5528, F5526, F5524, F5522, F5514, F5513 devices)
General-purpose digital I/O (not available on F5528, F5526, F5524,
F5522, F5514, F5513 devices)
TB0 CCR3 capture: CCI3A input, compare: Out3 output (not available
on F5528, F5526, F5524, F5522, F5514, F5513 devices)
General-purpose digital I/O (not available on F5528, F5526, F5524,
F5522, F5514, F5513 devices)
P7.6/TB0.4
59
60
N/A
N/A
N/A
N/A
N/A
N/A
I/O
I/O
TB0 CCR4 capture: CCI4A input, compare: Out4 output (not available
on F5528, F5526, F5524, F5522, F5514, F5513 devices)
General-purpose digital I/O (not available on F5528, F5526, F5524,
F5522, F5514, F5513 devices)
P7.7/TB0CLK/MCLK
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Table 7-1. Terminal Functions (continued)
TERMINAL
NO.
I/O(1)
DESCRIPTION
NAME
ZXH,
ZQE
PN
RGC YFF
TB0 clock signal TBCLK input (not available on F5528, F5526, F5524,
F5522, F5514, F5513 devices)
MCLK output (not available on F5528, F5526, F5524, F5522, F5514,
F5513 devices)
VSSU
61
62
49
50
H2 B8, B9
USB PHY ground supply
General-purpose digital I/O. Controlled by USB control register
USB data terminal DP
PU.0/DP
H1
G2
G1
A9
B7
A8
I/O
USB pullup resistor pin (open drain). The voltage level at the PUR pin is
I/O used to invoke the default USB BSL. Recommended 1-MΩ resistor to
ground. See Section 9.5.1 for more information.
PUR
63
64
51
52
General-purpose digital I/O. Controlled by USB control register
PU.1/DM
I/O
USB data terminal DM
VBUS
VUSB
V18
65
66
67
68
53
54
55
56
F2
F1
E2
D2
A7
A6
B6
A5
USB LDO input (connect to USB power source)
USB LDO output
USB regulated power (internal use only, no external current loading)
Analog ground supply
AVSS2
General-purpose digital I/O
I/O
P5.2/XT2IN
69
70
71
72
57
58
59
60
E1
D1
E3
D3
B5
B4
A4
C5
Input terminal for crystal oscillator XT2
General-purpose digital I/O
I/O
P5.3/XT2OUT
TEST/SBWTCK(4)
PJ.0/TDO(5)
Output terminal of crystal oscillator XT2
Test mode pin – selects 4-wire JTAG operation
I
Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated
General-purpose digital I/O
I/O
JTAG test data output port
General-purpose digital I/O
I/O JTAG test data input
Test clock input
PJ.1/TDI/TCLK(5)
73
61
D4
C4
General-purpose digital I/O
I/O
PJ.2/TMS(5)
PJ.3/TCK(5)
74
75
62
63
C1
C2
A3
B3
JTAG test mode select
General-purpose digital I/O
I/O
JTAG test clock
Reset input, active low(6)
RST/NMI/SBWTDIO(4)
P6.0/CB0/A0
76
77
78
64
1
D5
B1
C3
A2
A1
B2
I/O Nonmaskable interrupt input
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated
General-purpose digital I/O
I/O Comparator_B input CB0
Analog input A0 for ADC (not available on F551x devices)
General-purpose digital I/O
P6.1/CB1/A1
2
I/O Comparator_B input CB1
Analog input A1 for ADC (not available on F551x devices)
General-purpose digital I/O
P6.2/CB2/A2
P6.3/CB3/A3
79
80
3
4
A1
C4
B1
C2
I/O Comparator_B input CB2
Analog input A2 for ADC (not available on F551x devices)
General-purpose digital I/O
I/O
Comparator_B input CB3
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Table 7-1. Terminal Functions (continued)
TERMINAL
NO.
I/O(1)
DESCRIPTION
NAME
ZXH,
ZQE
PN
RGC YFF
Analog input A3 for ADC (not available on F551x devices)
Reserved. Connect to ground.
(2)
Reserved
QFN Pad
N/A
N/A
N/A
Pad
N/A
N/A
N/A
QFN package pad. TI recommends connecting to VSS.
(1) I = input, O = output, N/A = not available
(2) C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.
(3) VCORE is for internal use only. No external current loading is possible. Connect VCORE to the recommended capacitor value, CVCORE
(see Section 8.3).
(4) See Section 9.5 and Section 9.6 for use with BSL and JTAG functions.
(5) See Section 9.6 for use with JTAG function.
(6) When this pin is configured as reset, the internal pullup resistor is enabled by default.
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8 Specifications
All graphs in this section are for typical conditions, unless otherwise noted.
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
4.1
UNIT
V
Voltage applied at VCC to VSS
–0.3
–0.3
Voltage applied to any pin (excluding VCORE, VBUS, V18)(2)
VCC + 0.3
±2
V
Diode current at any device pin
mA
°C
Maximum operating junction temperature, TJ
95
(3)
Storage temperature, Tstg
–55
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
8.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD) Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as
±250 V may actually have higher performance.
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MSP430F5513
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8.3 Recommended Operating Conditions
MIN NOM
1.8
MAX UNIT
PMMCOREVx = 0
3.6
PMMCOREVx = 0, 1
PMMCOREVx = 0, 1, 2
PMMCOREVx = 0, 1, 2, 3
PMMCOREVx = 0
2.0
3.6
V
Supply voltage during program execution and flash
VCC
(1) (2)
programming (AVCC = DVCC1 = DVCC2 = DVCC
)
2.2
3.6
2.4
3.6
3.6
3.6
1.8
PMMCOREVx = 0, 1
PMMCOREVx = 0, 1, 2
PMMCOREVx = 0, 1, 2, 3
PMMCOREVx = 2
2.0
Supply voltage during USB operation, USB PLL disabled,
USB_EN = 1, UPLLEN = 0
2.2
3.6
V
3.6
VCC, USB
2.4
Supply voltage during USB operation, USB PLL enabled(3)
USB_EN = 1, UPLLEN = 1
,
2.2
3.6
3.6
V
PMMCOREVx = 2, 3
2.4
VSS
TA
Supply voltage (AVSS = DVSS1 = DVSS2 = DVSS
Operating free-air temperature
)
0
I version
I version
–40
–40
470
85
85
°C
°C
nF
TJ
Operating junction temperature
CVCORE
Recommended capacitor at VCORE(4)
CDVCC
CVCORE
/
Capacitor ratio of DVCC to VCORE
10
0
ratio
MHz
PMMCOREVx = 0,
1.8 V ≤ VCC ≤ 3.6 V
(default condition)
8.0
PMMCOREVx = 1,
2.0 V ≤ VCC ≤ 3.6 V
Processor frequency (maximum MCLK frequency)(5)
(see Figure 8-1)
0
0
0
12.0
20.0
25.0
fSYSTEM
PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V
PMMCOREVx = 3,
2.4 V ≤ VCC ≤ 3.6 V
fSYSTEM_USB Minimum processor frequency for USB operation
USB_wait Wait state cycles during USB operation
1.5
MHz
16
cycles
(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 8.22 threshold parameters for
the exact values and further details.
(3) USB operation with USB PLL enabled requires PMMCOREVx ≥ 2 for proper operation.
(4) A capacitor tolerance of ±20% or better is required.
(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
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25
3
20
2, 3
2
12
8
1, 2
1, 2, 3
1
0
0, 1
0, 1, 2
0, 1, 2, 3
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
NOTE: The numbers within the fields denote the supported PMMCOREVx settings.
Figure 8-1. Maximum System Frequency
8.4 Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted)(1) (2) (3)
FREQUENCY (fDCO = fMCLK = fSMCLK
8 MHz 12 MHz 20 MHz
TYP MAX TYP MAX
)
EXECUTION
MEMORY
PARAMETER
VCC
PMMCOREVx
1 MHz
25 MHz
UNIT
TYP
MAX
TYP
MAX
TYP
10.1
5.3
MAX
11.0
6.2
0
1
2
3
0
1
2
3
0.36
0.40
0.44
0.46
0.20
0.22
0.24
0.26
0.47
2.32
2.65
2.90
3.10
1.20
1.35
1.50
1.60
2.60
4.0
4.3
4.6
4.4
2.2
IAM, Flash
Flash
3.0 V
mA
mA
7.1
7.6
7.7
4.2
0.24
1.30
2.0
2.2
2.4
IAM, RAM
RAM
3.0 V
3.7
3.9
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external
load capacitance are chosen to closely match the required 12.5 pF.
(3) Characterized with program executing typical data processing. USB disabled (VUSBEN = 0, SLDOEN = 0).
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.
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8.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
–40°C
TYP MAX
73
25°C
60°C
TYP MAX
80
85°C
PARAMETER
VCC
PMMCOREVx
UNIT
TYP MAX
TYP MAX
2.2 V
3.0 V
2.2 V
3.0 V
0
3
0
3
0
1
2
0
1
2
3
0
1
2
3
0
1
2
3
—
77
83
85
92
12
13
85
95
97
105
17
ILPM0,1MHz Low-power mode 0(3) (4)
µA
79
88
6.5
6.5
7.0
1.90
2.00
2.15
2.1
2.3
2.4
2.5
1.4
1.4
1.5
1.6
1.1
1.2
1.2
1.3
0.18
10
11
ILPM2
Low-power mode 2(5) (4)
µA
7.0
11
12
18
1.60
1.65
1.75
1.8
2.6
5.6
5.9
6.1
5.8
6.1
6.3
6.4
4.9
5.2
5.3
5.4
4.8
5.1
5.2
5.3
0.5
2.2 V
2.7
2.9
Low-power mode 3,
crystal mode(6) (4)
ILPM3,XT1LF
2.9
2.8
8.3
µA
µA
1.9
2.9
3.0 V
2.0
3.0
2.0
3.9
2.7
3.1
9.3
7.4
1.1
1.9
1.1
2.0
Low-power mode 3,
VLO mode(7) (4)
ILPM3,VLO
3.0 V
1.2
2.1
1.3
3.0
1.5
2.2
8.5
7.3
0.9
1.8
1.1
2.0
ILPM4
Low-power mode 4(8) (4)
Low-power mode 4.5(9)
3.0 V
3.0 V
µA
µA
1.2
2.1
1.3
1.6
2.2
8.1
1.0
ILPM4.5
0.15
0.35
0.26
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external
load capacitance are chosen to closely match the required 12.5 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0).
(4) Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor and monitor disabled (SVSL, SVML).
High-side monitor disabled (SVMH). RAM retention enabled.
(5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO setting = 1
MHz operation, DCO bias generator enabled.
USB disabled (VUSBEN = 0, SLDOEN = 0)
(6) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0)
(7) Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0)
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0)
(9) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
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UNIT
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
8.6 Thermal Resistance Characteristics
THERMAL METRIC(1)
VALUE
70
LQFP (PN)
Low-K board (JESD51-3)
High-K board (JESD51-7)
VQFN (RGC)
BGA (ZQE)
LQFP (PN)
VQFN (RGC)
BGA (ZQE)
LQFP (PN)
VQFN (RGC)
BGA (ZQE)
LQFP (PN)
VQFN (RGC)
BGA (ZQE)
55
84
RθJA
Junction-to-ambient thermal resistance, still air
°C/W
45
25
46
12
RθJC
RθJB
Junction-to-case thermal resistance
Junction-to-board thermal resistance
12
°C/W
°C/W
30
22
6
20
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.7 Schmitt-Trigger Inputs – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7,
P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
VCC
1.8 V
3 V
MIN
0.80
1.50
0.45
0.75
0.3
TYP
MAX UNIT
1.40
V
2.10
VIT+
VIT–
Vhys
Positive-going input threshold voltage
1.8 V
3 V
1.00
V
1.65
Negative-going input threshold voltage
1.8 V
3 V
0.85
V
1.0
Input voltage hysteresis (VIT+ – VIT–
)
0.4
For pullup: VIN = VSS
For pulldown: VIN = VCC
RPull
CI
Pullup and pulldown resistor(2)
Input capacitance
20
35
5
50
kΩ
pF
VIN = VSS or VCC
(1) Same parametrics apply to clock input pin when the crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
(2) Also applies to RST pin when pullup or pulldown resistor is enabled.
8.8 Inputs – Ports P1 and P2
(P1.0 to P1.7, P2.0 to P2.7)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
VCC
MIN
MAX UNIT
t(int)
External interrupt timing(2)
External trigger pulse duration to set interrupt flag
2.2 V, 3 V
20
ns
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int)
.
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8.9 Leakage Current – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)
(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See (1) (2)
VCC
MIN
MAX UNIT
Ilkg(Px.y)
High-impedance leakage current
1.8 V, 3 V
–50
50 nA
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
8.10 Outputs – General-Purpose I/O (Full Drive Strength)
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7,
P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA(1)
VCC
MIN
VCC – 0.25
VCC – 0.60
VCC – 0.25
VCC – 0.60
MAX UNIT
VCC
1.8 V
I(OHmax) = –10 mA(2)
I(OHmax) = –5 mA(1)
I(OHmax) = –15 mA(2)
I(OLmax) = 3 mA(1)
I(OLmax) = 10 mA(2)
I(OLmax) = 5 mA(1)
I(OLmax) = 15 mA(2)
VCC
High-level output voltage
(see Figure 8-8 and Figure 8-9)
VOH
V
VCC
3 V
1.8 V
3 V
VCC
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
VSS VSS + 0.60
Low-level output voltage
(see Figure 8-6 and Figure 8-7)
VOL
V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage
drop specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
8.11 Outputs – General-Purpose I/O (Reduced Drive Strength)
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7,
P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(3)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA(1)
VCC
MIN
VCC – 0.25
VCC – 0.60
VCC – 0.25
VCC – 0.60
MAX UNIT
VCC
1.8 V
I(OHmax) = –3 mA(2)
I(OHmax) = –2 mA(1)
I(OHmax) = –6 mA(2)
I(OLmax) = 1 mA(1)
I(OLmax) = 3 mA(2)
I(OLmax) = 2 mA(1)
I(OLmax) = 6 mA(2)
VCC
High-level output voltage
(see Figure 8-4 and Figure 8-5)
VOH
V
VCC
3.0 V
1.8 V
3.0 V
VCC
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
VSS VSS + 0.60
Low-level output voltage
(see Figure 8-2 and Figure 8-3)
VOL
V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
(3) Selecting reduced drive strength may reduce EMI.
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8.12 Output Frequency – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7,
P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
VCC = 1.8 V,
PMMCOREVx = 0
16
Port output frequency
(with load)
fPx.y
See (1) (2)
MHz
25
VCC = 3 V,
PMMCOREVx = 3
VCC = 1.8 V,
PMMCOREVx = 0
16
ACLK, SMCLK, MCLK,
CL = 20 pF(2)
fPort_CLK
Clock output frequency
MHz
25
VCC = 3 V,
PMMCOREVx = 3
(1) A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS
.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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8.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
25.0
20.0
15.0
10.0
5.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
TA = 25°C
TA = 85°C
VCC = 3.0 V
Px.y
VCC = 1.8 V
Px.y
TA = 25°C
TA = 85°C
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
Figure 8-3. Typical Low-Level Output Current vs
Low-Level Output Voltage
Figure 8-2. Typical Low-Level Output Current vs
Low-Level Output Voltage
0.0
0.0
VCC = 1.8 V
VCC = 3.0 V
Px.y
Px.y
−1.0
−5.0
−2.0
−3.0
−4.0
−10.0
TA = 85°C
−5.0
−15.0
TA = 85°C
−6.0
TA = 25°C
−20.0
TA = 25°C
−7.0
−8.0
−25.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
Figure 8-4. Typical High-Level Output Current vs
High-Level Output Voltage
Figure 8-5. Typical High-Level Output Current vs
High-Level Output Voltage
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8.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
60.0
24
20
16
12
8
TA = 25°C
TA = 85°C
VCC = 1.8 V
Px.y
VCC = 3.0 V
Px.y
55.0
50.0
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
TA = 25°C
TA = 85°C
4
0.0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
Figure 8-6. Typical Low-Level Output Current vs
Low-Level Output Voltage
Figure 8-7. Typical Low-Level Output Current vs
Low-Level Output Voltage
0.0
0
VCC = 1.8 V
Px.y
VCC = 3.0 V
−5.0
Px.y
−10.0
−15.0
−20.0
−25.0
−30.0
−35.0
−40.0
−4
−8
−12
−45.0
TA = 85°C
−16
TA = 85°C
−50.0
−55.0
TA = 25°C
−60.0
TA = 25°C
−20
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
Figure 8-8. Typical High-Level Output Current vs
High-Level Output Voltage
Figure 8-9. Typical High-Level Output Current vs
High-Level Output Voltage
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8.15 Crystal Oscillator, XT1, Low-Frequency Mode
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 1, TA = 25°C
0.075
Differential XT1 oscillator
crystal current consumption
from lowest drive setting, LF XT1DRIVEx = 2, TA = 25°C
mode
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
ΔIDVCC.LF
3.0 V
0.170
0.290
32768
µA
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 3, TA = 25°C
XT1 oscillator crystal
frequency, LF mode
fXT1,LF0
XTS = 0, XT1BYPASS = 0
Hz
XT1 oscillator logic-level
fXT1,LF,SW
square-wave input frequency, XTS = 0, XT1BYPASS = 1(2) (3)
LF mode
10 32.768
50 kHz
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
210
300
Oscillation allowance for
LF crystals(4)
OALF
kΩ
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, XCAPx = 0(6)
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
XTS = 0, XCAPx = 3
1
5.5
Integrated effective load
capacitance, LF mode(5)
CL,eff
pF
8.5
12.0
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
Duty cycle, LF mode
30%
10
70%
Oscillator fault frequency,
LF mode(7)
fFault,LF
XTS = 0(8)
10000
Hz
ms
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 0, TA = 25°C, CL,eff = 6 pF
1000
500
tSTART,LF
Start-up time, LF mode
3.0 V
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 3, TA = 25°C, CL,eff = 12 pF
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
•
•
•
•
•
•
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined
in the Schmitt-trigger Inputs section of this data sheet.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
•
•
•
•
For XT1DRIVEx = 0, CL,eff ≤ 6 pF.
For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF.
For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF.
For XT1DRIVEx = 3, CL,eff ≥ 6 pF.
(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the
effective load capacitance should always match the specification of the used crystal.
(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.
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8.16 Crystal Oscillator, XT2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 4 MHz, XT2OFF = 0, XT2BYPASS = 0,
XT2DRIVEx = 0, TA = 25°C
200
fOSC = 12 MHz, XT2OFF = 0, XT2BYPASS = 0,
XT2DRIVEx = 1, TA = 25°C
260
325
450
XT2 oscillator crystal
current consumption
IDVCC.XT2
3.0 V
µA
fOSC = 20 MHz, XT2OFF = 0, XT2BYPASS = 0,
XT2DRIVEx = 2, TA = 25°C
fOSC = 32 MHz, XT2OFF = 0, XT2BYPASS = 0,
XT2DRIVEx = 3, TA = 25°C
XT2 oscillator crystal
frequency, mode 0
fXT2,HF0
fXT2,HF1
fXT2,HF2
fXT2,HF3
XT2DRIVEx = 0, XT2BYPASS = 0(3)
XT2DRIVEx = 1, XT2BYPASS = 0(3)
XT2DRIVEx = 2, XT2BYPASS = 0(3)
XT2DRIVEx = 3, XT2BYPASS = 0(3)
4
8
8
MHz
XT2 oscillator crystal
frequency, mode 1
16 MHz
24 MHz
32 MHz
XT2 oscillator crystal
frequency, mode 2
16
24
XT2 oscillator crystal
frequency, mode 3
XT2 oscillator logic-level
square-wave input
fXT2,HF,SW
XT2BYPASS = 1(4) (3)
0.7
32 MHz
frequency, bypass mode
XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 6 MHz, CL,eff = 15 pF
450
320
200
200
0.5
XT2DRIVEx = 1, XT2BYPASS = 0,
fXT2,HF1 = 12 MHz, CL,eff = 15 pF
Oscillation allowance for
HF crystals(5)
OAHF
Ω
XT2DRIVEx = 2, XT2BYPASS = 0,
fXT2,HF2 = 20 MHz, CL,eff = 15 pF
XT2DRIVEx = 3, XT2BYPASS = 0,
fXT2,HF3 = 32 MHz, CL,eff = 15 pF
fOSC = 6 MHz, XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C, CL,eff = 15 pF
tSTART,HF
Start-up time
3.0 V
ms
pF
fOSC = 20 MHz, XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C, CL,eff = 15 pF
0.3
Integrated effective load
CL,eff
capacitance, HF mode(6)
1
(1)
Duty cycle
Measured at ACLK, fXT2,HF2 = 20 MHz
40%
30
50%
60%
300 kHz
fFault,HF
Oscillator fault frequency(7) XT2BYPASS = 1(8)
(1) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. In general, an effective load capacitance
of up to 18 pF can be supported.
(2) To improve EMI on the XT2 oscillator the following guidelines should be observed.
•
•
•
•
•
•
Keep the traces between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(3) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device
operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.
(4) When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined
in the Schmitt-trigger Inputs section of this data sheet.
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the
effective load capacitance should always match the specification of the used crystal.
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(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.
8.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLO frequency
VLO frequency temperature drift
TEST CONDITIONS
VCC
MIN
TYP
9.4
0.5
4
MAX UNIT
14 kHz
%/°C
fVLO
Measured at ACLK
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
6
dfVLO/dT
Measured at ACLK(1)
Measured at ACLK(2)
Measured at ACLK
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
%/V
40%
50%
60%
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
8.18 Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
IREFO
REFO oscillator current consumption TA = 25°C
1.8 V to 3.6 V
1.8 V to 3.6 V
3
µA
REFO frequency calibrated
Measured at ACLK
32768
Hz
fREFO
Full temperature range
TA = 25°C
1.8 V to 3.6 V –3.5%
3.5%
1.5%
%/°C
%/V
REFO absolute tolerance calibrated
3 V
–1.5%
dfREFO/dT
REFO frequency temperature drift
Measured at ACLK(1)
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
0.01
1.0
dfREFO/dVCC
REFO frequency supply voltage drift Measured at ACLK(2)
Duty cycle
Measured at ACLK
40%/60% duty cycle
40%
50%
25
60%
tSTART
REFO start-up time
µs
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
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8.19 DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0.07
0.70
0.15
1.47
0.32
3.17
0.64
6.07
1.3
TYP
MAX UNIT
0.20 MHz
1.70 MHz
0.36 MHz
3.45 MHz
0.75 MHz
7.38 MHz
1.51 MHz
14.0 MHz
3.2 MHz
fDCO(0,0)
fDCO(0,31)
fDCO(1,0)
fDCO(1,31)
fDCO(2,0)
fDCO(2,31)
fDCO(3,0)
fDCO(3,31)
fDCO(4,0)
fDCO(4,31)
fDCO(5,0)
fDCO(5,31)
fDCO(6,0)
fDCO(6,31)
fDCO(7,0)
fDCO(7,31)
DCO frequency (0, 0)(1)
DCO frequency (0, 31)(1)
DCO frequency (1, 0)(1)
DCO frequency (1, 31)(1)
DCO frequency (2, 0)(1)
DCO frequency (2, 31)(1)
DCO frequency (3, 0)(1)
DCO frequency (3, 31)(1)
DCO frequency (4, 0)(1)
DCO frequency (4, 31)(1)
DCO frequency (5, 0)(1)
DCO frequency (5, 31)(1)
DCO frequency (6, 0)(1)
DCO frequency (6, 31)(1)
DCO frequency (7, 0)(1)
DCO frequency (7, 31)(1)
DCORSELx = 0, DCOx = 0, MODx = 0
DCORSELx = 0, DCOx = 31, MODx = 0
DCORSELx = 1, DCOx = 0, MODx = 0
DCORSELx = 1, DCOx = 31, MODx = 0
DCORSELx = 2, DCOx = 0, MODx = 0
DCORSELx = 2, DCOx = 31, MODx = 0
DCORSELx = 3, DCOx = 0, MODx = 0
DCORSELx = 3, DCOx = 31, MODx = 0
DCORSELx = 4, DCOx = 0, MODx = 0
DCORSELx = 4, DCOx = 31, MODx = 0
DCORSELx = 5, DCOx = 0, MODx = 0
DCORSELx = 5, DCOx = 31, MODx = 0
DCORSELx = 6, DCOx = 0, MODx = 0
DCORSELx = 6, DCOx = 31, MODx = 0
DCORSELx = 7, DCOx = 0, MODx = 0
DCORSELx = 7, DCOx = 31, MODx = 0
12.3
2.5
28.2 MHz
6.0 MHz
23.7
4.6
54.1 MHz
10.7 MHz
88.0 MHz
19.6 MHz
135 MHz
39.0
8.5
60
Frequency step between range
DCORSEL and DCORSEL + 1
SDCORSEL
SDCO
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
1.2
2.3 ratio
Frequency step between tap DCO
and DCO + 1
1.02
40%
1.12 ratio
Duty cycle
Measured at SMCLK
fDCO = 1 MHz
50%
0.1
60%
%/°C
%/V
dfDCO/dT
DCO frequency temperature drift(2)
dfDCO/dVCC DCO frequency voltage drift(3)
fDCO = 1 MHz
1.9
(1) When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the
range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31
(DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual
fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the
selected range is at its minimum or maximum tap setting.
(2) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(3) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
100
VCC = 3.0 V
TA = 25°C
10
DCOx = 31
1
DCOx = 0
0.1
0
1
2
3
4
5
6
7
DCORSEL
Figure 8-10. Typical DCO Frequency
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8.20 PMM, Brownout Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
| dDVCC/dt | < 3 V/s
| dDVCC/dt | < 3 V/s
MIN
TYP
MAX UNIT
V(DVCC_BOR_IT–)
V(DVCC_BOR_IT+)
V(DVCC_BOR_hys)
BORH on voltage, DVCC falling level
BORH off voltage, DVCC rising level
BORH hysteresis
1.45
1.50
250
V
V
0.80
50
1.30
mV
Pulse duration required at RST/NMI pin to
accept a reset
tRESET
2
µs
8.21 PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
2.4 V ≤ DVCC ≤ 3.6 V
2.2 V ≤ DVCC ≤ 3.6 V
2.0 V ≤ DVCC ≤ 3.6 V
1.8 V ≤ DVCC ≤ 3.6 V
2.4 V ≤ DVCC ≤ 3.6 V
2.2 V ≤ DVCC ≤ 3.6 V
2.0 V ≤ DVCC ≤ 3.6 V
1.8 V ≤ DVCC ≤ 3.6 V
MIN
TYP
1.90
1.80
1.60
1.40
1.94
1.84
1.64
1.44
MAX UNIT
VCORE3(AM)
VCORE2(AM)
VCORE1(AM)
VCORE0(AM)
VCORE3(LPM)
VCORE2(LPM)
VCORE1(LPM)
VCORE0(LPM)
Core voltage, active mode, PMMCOREV = 3
Core voltage, active mode, PMMCOREV = 2
Core voltage, active mode, PMMCOREV = 1
Core voltage, active mode, PMMCOREV = 0
Core voltage, low-current mode, PMMCOREV = 3
Core voltage, low-current mode, PMMCOREV = 2
Core voltage, low-current mode, PMMCOREV = 1
Core voltage, low-current mode, PMMCOREV = 0
V
V
V
V
V
V
V
V
8.22 PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SVSHE = 0, DVCC = 3.6 V
0
nA
I(SVSH)
SVS current consumption
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
SVSHE = 1, SVSHRVL = 0
200
1.5
µA
1.57
1.79
1.98
2.10
1.62
1.88
2.07
2.20
2.32
2.52
2.90
2.90
1.68
1.88
2.08
2.18
1.74
1.94
2.14
2.30
2.40
2.70
3.10
3.10
2.5
1.78
SVSHE = 1, SVSHRVL = 1
1.98
V
V(SVSH_IT–)
SVSH on voltage level(1)
SVSHE = 1, SVSHRVL = 2
2.21
SVSHE = 1, SVSHRVL = 3
2.31
1.85
2.07
2.28
SVSHE = 1, SVSMHRRL = 0
SVSHE = 1, SVSMHRRL = 1
SVSHE = 1, SVSMHRRL = 2
SVSHE = 1, SVSMHRRL = 3
2.42
V
V(SVSH_IT+)
SVSH off voltage level(1)
SVSHE = 1, SVSMHRRL = 4
2.55
SVSHE = 1, SVSMHRRL = 5
2.88
3.23
3.23
SVSHE = 1, SVSMHRRL = 6
SVSHE = 1, SVSMHRRL = 7
SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1
SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0
SVSHE = 0 → 1, SVSHFP = 1
SVSHE = 0 → 1, SVSHFP = 0
tpd(SVSH)
SVSH propagation delay
µs
µs
20
12.5
100
t(SVSH)
SVSH on or off delay time
DVCC rise time
dVDVCC/dt
0
1000
V/s
(1) The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and use.
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8.23 PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SVMHE = 0, DVCC = 3.6 V
0
nA
I(SVMH)
SVMH current consumption
SVMHE= 1, DVCC = 3.6 V, SVMHFP = 0
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
SVMHE = 1, SVSMHRRL = 0
200
1.5
µA
1.85
1.62
1.88
2.07
2.20
2.32
2.52
2.90
2.90
1.74
1.94
2.14
2.30
2.40
2.70
3.10
3.10
3.75
2.5
SVMHE = 1, SVSMHRRL = 1
2.07
SVMHE = 1, SVSMHRRL = 2
2.28
SVMHE = 1, SVSMHRRL = 3
2.42
V(SVMH)
SVMH on or off voltage level(1)
SVMHE = 1, SVSMHRRL = 4
2.55
2.88
3.23
3.23
V
SVMHE = 1, SVSMHRRL = 5
SVMHE = 1, SVSMHRRL = 6
SVMHE = 1, SVSMHRRL = 7
SVMHE = 1, SVMHOVPE = 1
SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1
SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0
SVMHE = 0 → 1, SVMHFP = 1
SVMHE = 0 → 1, SVMHFP = 0
tpd(SVMH) SVMH propagation delay
µs
µs
20
12.5
100
t(SVMH)
SVMH on or off delay time
(1) The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and use.
8.24 PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SVSLE = 0, PMMCOREV = 2
0
nA
µA
µs
I(SVSL)
SVSL current consumption
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
200
1.5
2.5
20
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
SVSLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
SVSLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
tpd(SVSL)
SVSL propagation delay
SVSL on or off delay time
12.5
100
t(SVSL)
µs
8.25 PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SVMLE = 0, PMMCOREV = 2
0
nA
µA
µs
I(SVML)
SVML current consumption
SVMLE= 1, PMMCOREV = 2, SVMLFP = 0
200
1.5
2.5
20
SVMLE= 1, PMMCOREV = 2, SVMLFP = 1
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
SVMLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
SVMLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
tpd(SVML) SVML propagation delay
12.5
100
t(SVML)
SVML on or off delay time
µs
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8.26 Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
fMCLK ≥ 4.0 MHz
3.5
7.5
Wake-up time from LPM2,
LPM3, or LPM4 to active
mode(1)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1
tWAKE-UP-FAST
µs
9
1.0 MHz < fMCLK
< 4.0 MHz
4.5
Wake-up time from LPM2,
LPM3 or LPM4 to active
mode(2) (3)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3), SVSLFP = 0
tWAKE-UP-SLOW
150
165
µs
Wake-up time from LPM4.5 to
active mode(4)
tWAKE-UP-LPM5
tWAKE-UP-RESET
2
2
3
3
ms
ms
Wake-up time from RST or
BOR event to active mode(4)
(1) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the
performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in
full performance mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode
Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx
Family User's Guide.
(2) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the
performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in
normal mode (low current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode
Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx
Family User's Guide.
(3) The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by
the performance mode settings as for LPM2, LPM3, and LPM4.
(4) This value represents the time from the wake-up event to the reset vector execution.
8.27 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK or ACLK,
External: TACLK,
fTA
Timer_A input clock frequency
1.8 V, 3 V
25 MHz
Duty cycle = 50% ±10%
All capture inputs, minimum pulse
duration required for capture
tTA,cap
Timer_A capture timing
1.8 V, 3 V
20
ns
8.28 Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK or ACLK,
External: TBCLK,
fTB
Timer_B input clock frequency
1.8 V, 3 V
25 MHz
Duty cycle = 50% ±10%
All capture inputs, minimum pulse
duration required for capture
tTB,cap
Timer_B capture timing
1.8 V, 3 V
20
ns
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8.29 USCI (UART Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
MAX UNIT
Internal: SMCLK or ACLK,
fUSCI
USCI input clock frequency
External: UCLK,
fSYSTEM MHz
Duty cycle = 50% ±10%
BITCLK clock frequency
(equals baud rate in MBaud)
fBITCLK
1
MHz
8.30 USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
2.2 V
3 V
MIN
MAX UNIT
50
600
ns
600
tt
UART receive deglitch time(1)
50
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
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8.31 USCI (SPI Master Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Internal: SMCLK or ACLK,
Duty cycle = 50% ±10%
MIN
MAX UNIT
fUSCI
USCI input clock frequency
fSYSTEM MHz
8.32 USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 8-11 and Figure 8-12)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
SMCLK or ACLK,
fUSCI
USCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ±10%
PMMCOREV = 0
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
55
38
30
25
0
tSU,MI
SOMI input data setup time
SOMI input data hold time
ns
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
0
tHD,MI
ns
0
0
20
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 0
18
ns
16
tVALID,MO SIMO output data valid time(2)
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 3
15
–10
–8
CL = 20 pF, PMMCOREV = 0
CL = 20 pF, PMMCOREV = 3
tHD,MO
SIMO output data hold time(3)
ns
–10
–8
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)
)
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 8-11 and Figure 8-12.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure
8-11 and Figure 8-12.
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
SIMO
tHD,MO
tVALID,MO
Figure 8-11. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLO/HI
tLO/HI
tHD,MI
tSU,MI
SOMI
SIMO
tHD,MO
tVALID,MO
Figure 8-12. SPI Master Mode, CKPH = 1
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8.33 USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 8-13 and Figure 8-14)
PARAMETER
TEST CONDITIONS
VCC
MIN
11
8
MAX UNIT
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
PMMCOREV = 0
tSTE,LEAD STE lead time, STE low to clock
ns
7
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
6
3
3
tSTE,LAG
STE lag time, Last clock to STE high
ns
3
3
66
50
ns
36
tSTE,ACC STE access time, STE low to SOMI data out
30
30
23
ns
16
tSTE,DIS
STE disable time, STE high to SOMI high impedance
13
5
5
2
2
5
5
5
5
tSU,SI
SIMO input data setup time
ns
tHD,SI
SIMO input data hold time
ns
76
UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 0
60
ns
44
tVALID,SO SOMI output data valid time(2)
UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 3
40
18
12
10
8
CL = 20 pF, PMMCOREV = 0
CL = 20 pF, PMMCOREV = 3
tHD,SO
SOMI output data hold time(3)
ns
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)
)
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 8-13 and Figure 8-14.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure
8-13 and Figure 8-14.
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tSU,SI
tLO/HI
tLO/HI
tHD,SI
SIMO
SOMI
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
Figure 8-13. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
SOMI
tHD,MO
tVALID,SO
tSTE,ACC
tSTE,DIS
Figure 8-14. SPI Slave Mode, CKPH = 1
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8.34 USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see
Figure 8-15)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK or ACLK,
External: UCLK,
fUSCI
USCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ±10%
fSCL
SCL clock frequency
2.2 V, 3 V
2.2 V, 3 V
0
4.0
0.6
4.7
0.6
0
400
kHz
µs
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
2.2 V, 3 V
µs
tHD,DAT
tSU,DAT
Data hold time
Data setup time
2.2 V, 3 V
2.2 V, 3 V
ns
ns
250
4.0
0.6
50
fSCL ≤ 100 kHz
fSCL > 100 kHz
tSU,STO
Setup time for STOP
2.2 V, 3 V
µs
ns
2.2 V
3 V
600
600
tSP
Pulse duration of spikes suppressed by input filter
50
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
SCL
tLOW
tHIGH
tSP
tSU,DAT
tSU,STO
tHD,DAT
Figure 8-15. I2C Mode Timing
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8.35 12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.2
0
TYP
MAX UNIT
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
AVCC
Analog supply voltage
3.6
V
V(Ax)
Analog input voltage range(2) All ADC12 analog input pins Ax
AVCC
155
V
2.2 V
3 V
125
150
Operating supply current into
fADC12CLK = 5.0 MHz(4)
AVCC terminal(3)
IADC12_A
µA
220
Only one terminal Ax can be selected at one
time
CI
RI
Input capacitance
2.2 V
20
25
pF
Ω
Input MUX ON resistance
0 V ≤ VAx ≤ AVCC
10
200
1900
(1) The leakage current is specified by the digital I/O input leakage.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If the
reference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling
capacitors are required. See Section 8.40 and Section 8.41.
(3) The internal reference supply current is not included in current consumption parameter IADC12_A
(4) ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0
.
8.36 12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
For specified performance of ADC12 linearity
parameters using an external reference voltage or
AVCC as reference(1)
0.45
4.8
5.0
ADC conversion
clock
fADC12CLK
For specified performance of ADC12 linearity
parameters using the internal reference(2)
2.2 V, 3 V
MHz
4.0
0.45
0.45
4.2
2.4
2.4
4.8
For specified performance of ADC12 linearity
parameters using the internal reference(3)
2.7
Internal ADC12
oscillator(4)
fADC12OSC
ADC12DIV = 0, fADC12CLK = fADC12OSC
2.2 V, 3 V
2.2 V, 3 V
5.4 MHz
REFON = 0, internal oscillator,
ADC12OSC used for ADC conversion clock
2.4
3.1
µs
tCONVERT Conversion time
External fADC12CLK from ACLK, MCLK, or SMCLK,
ADC12SSEL ≠ 0
13 ×
1 / fADC12CLK
RS = 400 Ω, RI = 1000 Ω, CI = 20 pF,
t = (RS + RI) × CI
tSample
Sampling time
2.2 V, 3 V
1000
ns
(5)
(1) REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0,
SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the
specified performance of the ADC12 linearity is ensured with fADC12CLK maximum of 5.0 MHz.
(2) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1
(3) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when
using the ADC12OSC divided by 2.
(4) The ADC12OSC is sourced directly from MODOSC inside the UCS.
(5) Approximately 10 Tau (t) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance
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8.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as
Reference Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Integral linearity error(1)
Differential linearity error(1)
Offset error(3)
TEST CONDITIONS
1.4 V ≤ dVREF ≤ 1.6 V(2)
VCC
MIN
TYP
MAX UNIT
±2.0
LSB
±1.7
EI
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
1.6 V < dVREF(2)
See (2)
ED
EO
EG
ET
±1.0 LSB
dVREF ≤ 2.2 V(2)
dVREF > 2.2 V(2)
See (2)
±1.0
±1.0
±1.0
±1.4
±1.4
±2.0
LSB
±2.0
Gain error(3)
±2.0 LSB
dVREF ≤ 2.2 V(2)
dVREF > 2.2 V(2)
±3.5
LSB
±3.5
Total unadjusted error
(1) Parameters are derived using the histogram method.
(2) The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = VR+ – VR–, VR+ < AVCC, VR–
>
AVSS. Unless otherwise mentioned, dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω, and two decoupling
capacitors, 10 µF and 100 nF, should be connected to VREF+ and VREF- to decouple the dynamic current. Also see the MSP430F5xx
and MSP430F6xx Family User's Guide.
(3) Parameters are derived using a best fit curve.
8.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
VCC
MIN
TYP
MAX UNIT
ADC12SR = 0, REFOUT = 1
fADC12CLK = 4.0 MHz
fADC12CLK = 2.7 MHz
fADC12CLK = 4.0 MHz
fADC12CLK = 2.7 MHz
fADC12CLK = 2.7 MHz
fADC12CLK = 4.0 MHz
fADC12CLK = 2.7 MHz
fADC12CLK = 4.0 MHz
fADC12CLK = 2.7 MHz
fADC12CLK = 4.0 MHz
fADC12CLK = 2.7 MHz
±1.7
LSB
±2.5
Integral linearity
error(2)
EI
2.2 V, 3 V
ADC12SR = 0, REFOUT = 0
ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 0
ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 0
ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 0
ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 0
–1.0
–1.0
–1.0
+2.0
Differential
ED
2.2 V, 3 V
+1.5 LSB
+2.5
linearity error(2)
±1.0
±1.0
±1.0
±2.0
LSB
±2.0
EO
EG
ET
Offset error(3)
Gain error(3)
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
±2.0 LSB
±1.5%(4) VREF
±3.5 LSB
±1.4
Total unadjusted
error
±1.5%(4) VREF
(1) The internal reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 1. dVREF = VR+ – VR–
.
(2) Parameters are derived using the histogram method.
(3) Parameters are derived using a best fit curve.
(4) The gain error and total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In this
mode the reference voltage used by the ADC12_A is not available on a pin.
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8.39 12-Bit ADC, Temperature Sensor and Built-In VMID
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see
Figure 8-16)
PARAMETER(1)
TEST CONDITIONS
VCC
2.2 V
3 V
MIN
TYP
680
680
2.25
2.25
MAX UNIT
ADC12ON = 1, INCH = 0Ah,
TA = 0°C
VSENSOR
See (2)
mV
2.2 V
3 V
TCSENSOR
ADC12ON = 1, INCH = 0Ah
mV/°C
2.2 V
3 V
100
100
Sample time required if
channel 10 is selected(3)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
tSENSOR(sample)
µs
AVCC divider at channel 11,
VAVCC factor
ADC12ON = 1, INCH = 0Bh
ADC12ON = 1, INCH = 0Bh
0.48
0.5
0.52 VAVCC
VMID
2.2 V
3 V
1.06
1.44
1.1
1.5
1.14
V
1.56
AVCC divider at channel 11
Sample time required if
channel 11 is selected(4)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
tVMID(sample)
2.2 V, 3 V
1000
ns
(1) The temperature sensor is provided by the REF module. See the REF module parametric, IREF+, regarding the current consumption of
the temperature sensor.
(2) The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor. The TLV structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference
voltage levels. The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature,°C) + VSENSOR, where TCSENSOR and
VSENSOR can be computed from the calibration values for higher accuracy. See also the MSP430F5xx and MSP430F6xx Family User's
Guide.
(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
.
(4) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
1000
950
900
850
800
750
700
650
600
550
500
-40 -30 -20 -10
0 10 20 30 40 50 60 70 80
Ambient Temperature (°C)
Figure 8-16. Typical Temperature Sensor Voltage
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8.40 REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Positive external reference
voltage input
(2)
VeREF+
VeREF+ > VREF– and VeREF–
1.4
AVCC
1.2
V
V
V
Negative external reference
voltage input
(3)
VREF–, VeREF–
VeREF+ > VREF– and VeREF–
0
(VeREF+
–
Differential external reference
VREF- or VeREF-) voltage input
(4)
VeREF+ > VREF– and VeREF–
1.4
AVCC
1.4 V ≤ VeREF+ ≤ VAVCC
,
VeREF– = 0 V, fADC12CLK = 5 MHz,
ADC12SHTx = 1h,
Conversion rate 200 ksps
–26
26
1
µA
IVeREF+, IVREF-,
Static input current
2.2 V, 3 V
VeREF-
1.4 V ≤ VeREF+ ≤ VAVCC
,
VeREF– = 0 V, fADC12CLK = 5 MHz,
ADC12SHTx = 8h,
Conversion rate 20 ksps
–1
10
µA
µF
Capacitance at VVREF+, VVREF-
terminal
(5)
CVREF+, CVREF-
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance (Ci) is
also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_A. See also the MSP430F5xx and MSP430F6xx Family User's Guide.
8.41 REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
REFVSEL = {2} for 2.5 V,
REFON = REFOUT = 1, IVREF+ = 0 A
2.4625
2.50 2.5375
1.98 2.0097
1.49 1.5124
3 V
Positive built-in reference
voltage output
REFVSEL = {1} for 2.0 V,
REFON = REFOUT = 1, IVREF+ = 0 A
VREF+
1.9503
V
REFVSEL = {0} for 1.5 V,
REFON = REFOUT = 1, IVREF+ = 0 A
2.2 V, 3 V 1.4677
REFVSEL = {0} for 1.5 V
REFVSEL = {1} for 2.0 V
REFVSEL = {2} for 2.5 V
2.2
2.3
2.8
AVCC minimum voltage,
Positive built-in reference
active
AVCC(min)
V
ADC12SR = 1(4), REFON = 1, REFOUT = 0,
REFBURST = 0
70
0.45
210
100
µA
ADC12SR = 1(4), REFON = 1, REFOUT = 1,
REFBURST = 0
0.75 mA
310 µA
Operating supply current into
AVCC terminal(2) (3)
IREF+
3 V
ADC12SR = 0(4), REFON = 1, REFOUT = 0,
REFBURST = 0
ADC12SR = 0(4), REFON = 1, REFOUT = 1,
REFBURST = 0
0.95
1.7 mA
REFVSEL = (0, 1, 2),
Load-current regulation,
VREF+ terminal(5)
IVREF+ = +10 µA, –1000 µA,
AVCC = AVCC(min) for each reference level,
REFVSEL = (0, 1, 2), REFON = REFOUT = 1
IL(VREF+)
2500 µV/mA
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8.41 REF, Built-In Reference (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Capacitance at VREF+
terminal
CVREF+
REFON = REFOUT = 1
20
100
50
pF
IVREF+ = 0 A,
REFVSEL = (0, 1, 2), REFON = 1,
REFOUT = 0 or 1
Temperature coefficient of
built-in reference(6)
ppm/
°C
TCREF+
30
AVCC = AVCC(min) to AVCC(max),
Power supply rejection ratio TA = 25°C,
PSRR_DC
PSRR_AC
120
300 µV/V
(DC)
REFVSEL = (0, 1, 2), REFON = 1,
REFOUT = 0 or 1
AVCC = AVCC(min) to AVCC(max),
TA = 25°C,
f = 1 kHz, ΔVpp = 100 mV,
REFVSEL = (0, 1, 2), REFON = 1,
REFOUT = 0 or 1
Power supply rejection ratio
(AC)
6.4
mV/V
AVCC = AVCC(min) to AVCC(max),
REFVSEL = (0, 1, 2), REFOUT = 0,
REFON = 0 → 1
75
75
Settling time of reference
voltage(7)
tSETTLE
µs
AVCC = AVCC(min) to AVCC(max),
CVREF = CVREF(max),
REFVSEL = (0, 1, 2), REFOUT = 1,
REFON = 0 → 1
(1) The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers,
one smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal, as
well as, used as the reference for the conversion and uses the larger buffer. When REFOUT = 0, the reference is only used as the
reference for the conversion and uses the smaller buffer.
(2) The internal reference current is supplied by the AVCC terminal. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current
contribution of the larger buffer without external load.
(3) The temperature sensor is provided by the REF module. Its current is supplied via terminal AVCC and is equivalent to IREF+ with
REFON =1 and REFOUT = 0.
(4) For devices without the ADC12, the parametrics with ADC12SR = 0 are applicable.
(5) Contribution only due to the reference and buffer including package. This does not include resistance due to PCB trace.
(6) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
(7) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load when REFOUT = 1.
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8.42 Comparator_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
3.6
40
UNIT
VCC
Supply voltage
1.8
V
1.8 V
2.2 V
CBPWRMD = 00
30
40
50
Comparator operating supply
IAVCC_COMP current into AVCC, excludes
reference resistor ladder
3.0 V
65
µA
µA
CBPWRMD = 01
CBPWRMD = 10
2.2 V, 3 V
2.2 V, 3 V
10
30
0.1
0.5
Quiescent current of local
reference voltage amplifier into
AVCC
CBREFACC = 1,
CBREFLx = 01
IAVCC_REF
22
VIC
Common mode input range
0
–20
–10
VCC – 1
20
V
CBPWRMD = 00
VOFFSET
CIN
Input offset voltage
mV
CBPWRMD = 01, 10
10
Input capacitance
5
3
pF
kΩ
On (switch closed)
4
RSIN
Series input resistance
Off (switch open)
30
MΩ
CBPWRMD = 00, CBF = 0
CBPWRMD = 01, CBF = 0
CBPWRMD = 10, CBF = 0
450
600
50
ns
µs
Propagation delay, response
time
tPD
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 00
0.35
0.6
1.0
1.8
0.6
1.0
1.8
3.4
1
1.0
1.8
3.4
6.5
2
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 01
Propagation delay with filter
active
tPD,filter
µs
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 10
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 11
CBON = 0 to CBON = 1,
CBPWRMD = 00, 01
Comparator enable time,
settling time
tEN_CMP
µs
CBON = 0 to CBON = 1,
CBPWRMD = 10
100
tEN_REF
Resistor reference enable time CBON = 0 to CBON = 1
1
1.5
µs
V
VIN ×
VIN ×
VIN ×
Reference voltage for a given
tap
VIN = reference into resistor
ladder (n = 0 to 31)
VCB_REF
(n + 0.5) / (n + 1) / 3 (n + 1.5) / 3
32
2
2
8.43 Ports PU.0 and PU.1
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
VUSB = 3.3 V ±10%, IOH = –25 mA,
see Figure 8-18 for typical characteristics
VOH
VOL
VIH
VIL
High-level output voltage
2.4
V
VUSB = 3.3 V ±10%, IOL = 25 mA,
see Figure 8-17 for typical characteristics
Low-level output voltage
High-level input voltage
Low-level input voltage
0.4
V
V
V
VUSB = 3.3 V ±10%,
see Figure 8-19 for typical characteristics
2.0
VUSB = 3.3 V ±10%,
see Figure 8-19 for typical characteristics
0.8
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
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90
VCC = 3.0 V
TA = 25 ºC
VCC = 3.0 V
TA = 85 ºC
80
70
60
50
40
30
20
10
0
VCC = 1.8 V
TA = 25 ºC
VCC = 1.8 V
TA = 85 ºC
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
VOL - Low-Level Output Voltage - V
Figure 8-17. Ports PU.0, PU.1 Typical Low-Level Output Characteristics
0
-10
-20
-30
VCC = 1.8 V
TA = 85 ºC
-40
-50
VCC = 3.0 V
TA = 85 ºC
-60
-70
-80
-90
VCC = 1.8 V
TA = 25 ºC
VCC = 3.0 V
TA = 25 ºC
0.5
1
1.5
2
2.5
3
VOH - High-Level Output Voltage - V
Figure 8-18. Ports PU.0, PU.1 Typical High-Level Output Characteristics
2.0
TA = 25°C, 85°C
1.8
VIT+, postive-going input threshold
1.6
1.4
1.2
VIT-, negative-going input threshold
1.0
0.8
0.6
0.4
0.2
0.0
1.8
2.2
2.6
VUSB Supply Voltage - V
3
3.4
Figure 8-19. Ports PU.0, PU.1 Typical Input Threshold Characteristics
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
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8.44 USB Output Ports DP and DM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.8
0
MAX
3.6
0.3
44
UNIT
V
VOH
VOL
D+, D– single ended
D+, D– single ended
USB 2.0 load conditions
USB 2.0 load conditions
V
Z(DRV) D+, D– impedance
Including external series resistor of 27 Ω
28
4
Ω
tRISE
tFALL
Rise time
Fall time
Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+
Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+
20
ns
ns
4
20
8.45 USB Input Ports DP and DM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
V
V(CM)
Z(IN)
VCRS
VIL
Differential input common mode range
0.8
2.5
Input impedance
300
1.3
kΩ
V
Crossover voltage
2.0
0.8
Static SE input logic low level
Static SE input logic high level
Differential input voltage
V
VIH
2.0
V
VDI
0.2
V
8.46 USB-PWR (USB Power System)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VBUS detection threshold
USB bus voltage
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
VLAUNCH
VBUS
VUSB
V18
3.75
5.5
V
V
V
V
Normal operation
3.76
USB LDO output voltage
Internal USB voltage(1)
3.003
3.3 3.597
1.8
Maximum external current from VUSB
terminal(2)
IUSB_EXT
IDET
USB LDO is on
12
100
250
mA
mA
µA
USB LDO current overload detection(3)
60
Operating supply current into VBUS
terminal(4)
USB LDO is on,
USB PLL disabled
ISUSPEND
USB LDO is on,
USB 1.8-V LDO is disabled,
VBUS = 5.0 V,
Operating supply current into VBUS
terminal, represents the current of the 3.3-V
LDO only
IUSB_LDO
1.8 V, 3 V
1.8 V, 3 V
60
30
µA
µA
USBDETEN = 0 or 1
USB LDO is disabled,
USB 1.8-V LDO is disabled,
Operating supply current into VBUS
IVBUS_DETECT terminal, represents the current of the
VBUS detection logic
VBUS > VLAUNCH
USBDETEN = 1
,
CBUS
CUSB
C18
VBUS terminal recommended capacitance
VUSB terminal recommended capacitance
V18 terminal recommended capacitance
4.7
220
220
µF
nF
nF
Within 2%,
recommended capacitances
tENABLE
RPUR
Settling time VUSB and V18
2
ms
Ω
Pullup resistance of PUR terminal(5)
70
110
150
(1) This voltage is for internal uses only. No external DC loading should be applied.
(2) This represents additional current that can be supplied to the application from the VUSB terminal beyond the needs of the USB
operation.
(3) A current overload is detected when the total current supplied from the USB LDO, including IUSB_EXT, exceeds this value.
(4) Does not include current contribution of Rpu and Rpd as outlined in the USB specification.
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
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(5) This value, in series with an external resistor between PUR and D+, produces the Rpu as outlined in the USB specification.
8.47 USB-PLL (USB Phase-Locked Loop)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Operating supply current
PLL frequency
TEST CONDITIONS
MIN
TYP
MAX UNIT
IPLL
7
mA
MHz
MHz
ms
fPLL
48
fUPD
tLOCK
tJitter
PLL reference frequency
PLL lock time
1.5
3
2
PLL jitter
1000
ps
8.48 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TJ
MIN
TYP
MAX UNIT
DVCC(PGM,ERASE) Program and erase supply voltage
1.8
3.6
5
V
mA
IPGM
Average supply current from DVCC during program(1)
3
6
6
IERASE
Average supply current from DVCC during erase(1)
Average supply current from DVCC during mass erase or bank erase(1)
Cumulative program time(2)
15
15
16
mA
IMERASE, IBANK
tCPT
mA
ms
Program and erase endurance
104
100
64
105
cycles
years
µs
tRetention
tWord
Data retention duration
25°C
Word or byte program time(3)
85
65
tBlock, 0
Block program time for first byte or word(3)
49
µs
Block program time for each additional byte or word, except for last byte
or word(3)
tBlock, 1–(N–1)
37
49
µs
tBlock, N
tErase
Block program time for last byte or word(3)
55
23
73
32
µs
Erase time for segment, mass erase, and bank erase when available(3)
ms
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4.MGR1 = 1)
fMCLK,MGR
0
1
MHz
(1) Default clock system frequency of MCLK = 1 MHz, ACLK = 32768 Hz, SMCLK = 1 MHz. No peripherals are enabled or active.
(2) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word- or byte-write and block-write modes.
(3) These values are hardwired into the state machine of the flash controller.
8.49 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
0
20 MHz
tSBW,Low
tSBW, En
tSBW,Rst
Spy-Bi-Wire low clock pulse duration
0.025
15
1
µs
µs
µs
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)(1)
Spy-Bi-Wire return to normal operation time
15
0
100
5
2.2 V
3 V
fTCK
TCK input frequency, 4-wire JTAG(2)
Internal pulldown resistance on TEST
MHz
kΩ
0
10
80
Rinternal
2.2 V, 3 V
45
60
(1) Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
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9 Detailed Description
9.1 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,
other than program-flow instructions, are performed as register operations in conjunction with seven addressing
modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant
generator, respectively. The remaining registers are general-purpose registers (see Figure 9-1).
Peripherals are connected to the CPU using data, address, and control buses. The peripherals can be managed
with all instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes and
additional instructions for the expanded address range. Each instruction can operate on word and byte data.
Program Counter
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
Figure 9-1. Integrated CPU Registers
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
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9.2 Operating Modes
These microcontrollers have one active mode and six software-selectable low-power modes of operation. An
interrupt event can wake up the device from any of the low-power modes, service the request, and restore back
to the low-power mode on return from the interrupt program.
Software can configure the following operating modes:
•
Active mode (AM)
– All clocks are active
•
Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
Low-power mode 1 (LPM1)
•
•
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO remains enabled
– ACLK remains active
•
•
Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– ACLK remains active
Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– Crystal oscillator is stopped
– Complete data retention
•
Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No data retention
– Wake-up signal from RST/NMI, P1, and P2
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
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9.3 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table
9-1). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 9-1. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
System Reset
Power up
External reset
WDTIFG, KEYV (SYSRSTIV)(1) (2)
Reset
0FFFEh
63, highest
Watchdog time-out, password violation
Flash memory password violation
System NMI
PMM
Vacant memory access
JTAG mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
JMBOUTIFG (SYSSNIV)(1)
(Non)maskable
(Non)maskable
0FFFCh
0FFFAh
62
61
User NMI
NMI
Oscillator fault
NMIIFG, OFIFG, ACCVIFG, BUSIFG
(SYSUNIV)(1) (2)
Flash memory access violation
Comp_B
TB0
Comparator B interrupt flags (CBIV)(1) (3)
TB0CCR0 CCIFG0(3)
Maskable
Maskable
0FFF8h
0FFF6h
60
59
TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
TB0IFG (TB0IV)(1) (3)
TB0
Maskable
0FFF4h
58
Watchdog Timer_A interval timer mode
USCI_A0 receive or transmit
USCI_B0 receive or transmit
ADC12_A
WDTIFG
Maskable
Maskable
Maskable
Maskable
Maskable
0FFF2h
0FFF0h
0FFEEh
0FFECh
0FFEAh
57
56
55
54
53
UCA0RXIFG, UCA0TXIFG (UCA0IV)(1) (3)
UCB0RXIFG, UCB0TXIFG (UCB0IV)(1) (3)
ADC12IFG0 to ADC12IFG15 (ADC12IV)(1) (3) (4)
TA0CCR0 CCIFG0(3)
TA0
TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0IFG (TA0IV)(1) (3)
TA0
Maskable
0FFE8h
52
USB_UBM
DMA
USB interrupts (USBIV)(1) (3)
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1) (3)
TA1CCR0 CCIFG0(3)
Maskable
Maskable
Maskable
0FFE6h
0FFE4h
0FFE2h
51
50
49
TA1
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG (TA1IV)(1) (3)
TA1
Maskable
0FFE0h
48
I/O port P1
USCI_A1 receive or transmit
USCI_B1 receive or transmit
TA2
P1IFG.0 to P1IFG.7 (P1IV)(1) (3)
UCA1RXIFG, UCA1TXIFG (UCA1IV)(1) (3)
UCB1RXIFG, UCB1TXIFG (UCB1IV)(1) (3)
TA2CCR0 CCIFG0(3)
Maskable
Maskable
Maskable
Maskable
0FFDEh
0FFDCh
0FFDAh
0FFD8h
47
46
45
44
TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
TA2IFG (TA2IV)(1) (3)
TA2
Maskable
Maskable
Maskable
0FFD6h
0FFD4h
0FFD2h
43
42
41
I/O port P2
RTC_A
P2IFG.0 to P2IFG.7 (P2IV)(1) (3)
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG (RTCIV)(1) (3)
0FFD0h
⋮
40
Reserved
Reserved(5)
⋮
0FF80h
0, lowest
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it.
(3) Interrupt flags are in the module.
(4) Only on devices with ADC, otherwise reserved.
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
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(5) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To
maintain compatibility with other devices, TI recommends reserving these locations.
9.4 Memory Organization
Table 9-2 summarizes the memory map of the devices.
Table 9-2. Memory Organization (1)
MSP430F5525
MSP430F5522
MSP430F5521
MSP430F5513
MSP430F5527
MSP430F5526
MSP430F5517
MSP430F5529
MSP430F5528
MSP430F5519
MSP430F5524
MSP430F5515
MSP430F5514
Memory (flash)
Main: interrupt vector
32KB
00FFFFh to 00FF80h
64KB
00FFFFh to 00FF80h
96KB
00FFFFh to 00FF80h
128KB
00FFFFh to 00FF80h
Total Size
Bank D
Bank C
Bank B
Bank A
Sector 3
Sector 2
Sector 1
Sector 0
Sector 7
Info A
32KB
0243FFh to 01C400h
N/A
N/A
N/A
N/A
N/A
32KB
01C3FFh to 014400h
32KB
01C3FFh to 014400h
Main: code memory
15KB
00FFFFh to 00C400h
32KB
0143FFh to 00C400h
32KB
0143FFh to 00C400h
32KB
0143FFh to 00C400h
17KB
00C3FFh to 008000h
32KB
00C3FFh to 004400h
32KB
00C3FFh to 004400h
32KB
00C3FFh to 004400h
2KB(2)
0043FFh to 003C00h
2KB
N/A
N/A
N/A
0043FFh to 003C00h
2KB(3)
003BFFh to 003400h
2KB
2KB
003BFFh to 003400h
003BFFh to 003400h
RAM
2KB
2KB
2KB
2KB
0033FFh to 002C00h
0033FFh to 002C00h
0033FFh to 002C00h
0033FFh to 002C00h
2KB
2KB
2KB
2KB
002BFFh to 002400h
002BFFh to 002400h
002BFFh to 002400h
002BFFh to 002400h
2KB
2KB
2KB
2KB
USB RAM(4)
0023FFh to 001C00h
0023FFh to 001C00h
0023FFh to 001C00h
0023FFh to 001C00h
128 bytes
0019FFh to 001980h
128 bytes
0019FFh to 001980h
128 bytes
0019FFh to 001980h
128 bytes
0019FFh to 001980h
128 bytes
00197Fh to 001900h
128 bytes
00197Fh to 001900h
128 bytes
00197Fh to 001900h
128 bytes
00197Fh to 001900h
Info B
Information memory
(flash)
128 bytes
0018FFh to 001880h
128 bytes
0018FFh to 001880h
128 bytes
0018FFh to 001880h
128 bytes
0018FFh to 001880h
Info C
128 bytes
00187Fh to 001800h
128 bytes
00187Fh to 001800h
128 bytes
00187Fh to 001800h
128 bytes
00187Fh to 001800h
Info D
512 bytes
0017FFh to 001600h
512 bytes
0017FFh to 001600h
512 bytes
0017FFh to 001600h
512 bytes
0017FFh to 001600h
BSL 3
512 bytes
0015FFh to 001400h
512 bytes
0015FFh to 001400h
512 bytes
0015FFh to 001400h
512 bytes
0015FFh to 001400h
BSL 2
Bootloader (BSL)
memory (flash)
512 bytes
0013FFh to 001200h
512 bytes
0013FFh to 001200h
512 bytes
0013FFh to 001200h
512 bytes
0013FFh to 001200h
BSL 1
512 bytes
0011FFh to 001000h
512 bytes
0011FFh to 001000h
512 bytes
0011FFh to 001000h
512 bytes
0011FFh to 001000h
BSL 0
4KB
000FFFh to 0h
4KB
000FFFh to 0h
4KB
000FFFh to 0h
4KB
000FFFh to 0h
Peripherals
Size
(1) N/A = Not available
(2) MSP430F5522 only
(3) MSP430F5522 and MSP430F5521 only
(4) USB RAM can be used as general purpose RAM when not used for USB operation.
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9.5 Bootloader (BSL)
The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the
device memory by the BSL is protected by an user-defined password. For further details on interfacing to
development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For complete
description of the features of the BSL and its implementation, see MSP430 Programming With the Bootloader
(BSL) User's Guide.
9.5.1 USB BSL
All devices come preprogrammed with the USB BSL. Table 9-3 lists the required pins for the USB BSL. In
addition to these pins, the application must support external components necessary for normal USB operation;
for example, the proper crystal on XT2IN and XT2OUT, proper decoupling, and so on.
Table 9-3. USB BSL Pin Requirements and
Functions
DEVICE SIGNAL
PU.0/DP
PU.1/DM
PUR
BSL FUNCTION
USB data terminal DP
USB data terminal DM
USB pullup resistor terminal
USB bus power supply
USB ground supply
VBUS
VSSU
Note
The default USB BSL evaluates the logic level of the PUR pin after a BOR reset. If the PUR pin is
pulled high externally, then the BSL is invoked. Therefore, unless the application is invoking the BSL,
it is important to keep PUR pulled low after a BOR reset, even if BSL or USB is never used. TI
recommends applying a 1-MΩ resistor to ground.
9.5.2 UART BSL
A UART BSL is also available that can be programmed by the user into the BSL memory by replacing the
preprogrammed, factory supplied, USB BSL. Table 9-4 lists the required pins for the UART BSL.
Table 9-4. UART BSL Pin Requirements and
Functions
DEVICE SIGNAL
BSL FUNCTION
Entry sequence signal
Entry sequence signal
Data transmit
RST/NMI/SBWTDIO
TEST/SBWTCK
P1.1
P1.2
VCC
VSS
Data receive
Power supply
Ground supply
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
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9.6 JTAG Operation
9.6.1 JTAG Standard Interface
The MSP430 family supports the standard JTAG interface, which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. Table 9-5 lists the required pins for the JTAG interface. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's
Guide. For a complete description of the features of the JTAG interface and its implementation, see MSP430
Programming With the JTAG Interface.
Table 9-5. JTAG Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
JTAG clock input
JTAG state control
JTAG data input, TCLK input
JTAG data output
Enable JTAG pins
External reset
PJ.3/TCK
IN
IN
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
IN
OUT
IN
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
IN
Power supply
VSS
Ground supply
9.6.2 Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. Spy-
Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table 9-6 lists the
required pins for the Spy-Bi-Wire interface. For further details on interfacing to development tools and device
programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the
JTAG interface and its implementation, see MSP430 Programming With the JTAG Interface.
Table 9-6. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
DIRECTION
FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input/output
Power supply
IN
IN, OUT
VSS
Ground supply
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9.7 Flash Memory
The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:
•
Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
•
•
•
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually. Segments A to D are also called information memory.
Segment A can be locked separately.
9.8 RAM
The RAM is made up of n sectors. Each sector can be completely powered down to save leakage; however; all
data is lost. Features of the RAM include:
•
•
•
•
RAM has n sectors. The size of a sector can be found in Section 9.4.
Each sector 0 to n can be complete disabled; however, data retention is lost.
Each sector 0 to n automatically enters low-power retention mode when possible.
For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.
9.9 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be controlled
using all instructions. For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's
Guide.
9.9.1 Digital I/O
Up to eight 8-bit I/O ports are implemented: For 80-pin packages, P1, P2, P3, P4, P5, P6, and P7 are complete,
and P8 is reduced to 3-bit I/O. For 64-pin packages, P3 and P5 are reduced to 5-bit I/O and 6-bit I/O,
respectively, and P7 and P8 are completely removed. Port PJ contains four individual I/O ports, common to all
devices.
•
•
•
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Pullup or pulldown on all ports is programmable.
Drive strength on all ports is programmable.
All bits of ports P1 and P2 support edge-selectable interrupt and LPM4.5 wake-up input.
Read and write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise (P1 through P8) or word-wise in pairs (PA through PD).
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
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9.9.2 Port Mapping Controller
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4 (see
Table 9-7). Table 9-8 shows the default mappings.
Table 9-7. Port Mapping Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
DVSS
0
PM_NONE
None
PM_CBOUT0
PM_TB0CLK
-
Comparator_B output
1
2
3
TB0 clock input
PM_ADC12CLK
PM_DMAE0
-
ADC12CLK
SVM output
DMAE0 input
PM_SVMOUT
PM_TB0OUTH
PM_TB0CCR0A
PM_TB0CCR1A
PM_TB0CCR2A
PM_TB0CCR3A
PM_TB0CCR4A
PM_TB0CCR5A
PM_TB0CCR6A
PM_UCA1RXD
PM_UCA1SOMI
PM_UCA1TXD
PM_UCA1SIMO
PM_UCA1CLK
PM_UCB1STE
PM_UCB1SOMI
PM_UCB1SCL
PM_UCB1SIMO
PM_UCB1SDA
PM_UCB1CLK
PM_UCA1STE
PM_CBOUT1
PM_MCLK
-
TB0 high impedance input TB0OUTH
TB0 CCR0 capture input CCI0A
TB0 CCR1 capture input CCI1A
TB0 CCR2 capture input CCI2A
TB0 CCR3 capture input CCI3A
TB0 CCR4 capture input CCI4A
TB0 CCR5 capture input CCI5A
TB0 CCR6 capture input CCI6A
4
5
TB0 CCR0 compare output Out0
TB0 CCR1 compare output Out1
TB0 CCR2 compare output Out2
TB0 CCR3 compare output Out3
TB0 CCR4 compare output Out4
TB0 CCR5 compare output Out5
TB0 CCR6 compare output Out6
6
7
8
9
10
USCI_A1 UART RXD (Direction controlled by USCI – input)
USCI_A1 SPI slave out master in (direction controlled by USCI)
USCI_A1 UART TXD (Direction controlled by USCI – output)
USCI_A1 SPI slave in master out (direction controlled by USCI)
USCI_A1 clock input/output (direction controlled by USCI)
USCI_B1 SPI slave transmit enable (direction controlled by USCI)
USCI_B1 SPI slave out master in (direction controlled by USCI)
USCI_B1 I2C clock (open drain and direction controlled by USCI)
USCI_B1 SPI slave in master out (direction controlled by USCI)
USCI_B1 I2C data (open drain and direction controlled by USCI)
USCI_B1 clock input/output (direction controlled by USCI)
USCI_A1 SPI slave transmit enable (direction controlled by USCI)
11
12
13
14
15
16
17
18
None
None
None
Comparator_B output
MCLK
19–30
Reserved
DVSS
Disables the output driver and the input Schmitt-trigger to prevent parasitic
cross currents when applying analog signals.
31 (0FFh)(1)
PM_ANALOG
(1) The value of the PM_ANALOG mnemonic is 0FFh. The port mapping registers are 5 bits wide, and the upper bits are ignored, which
results in a read value of 31.
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MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
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Table 9-8. Default Mapping
PIN
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
USCI_B1 SPI slave transmit enable (direction controlled by USCI)
USCI_A1 clock input/output (direction controlled by USCI)
P4.0/P4MAP0
P4.1/P4MAP1
P4.2/P4MAP2
P4.3/P4MAP3
P4.4/P4MAP4
P4.5/P4MAP5
PM_UCB1STE/PM_UCA1CLK
USCI_B1 SPI slave in master out (direction controlled by USCI)
USCI_B1 I2C data (open drain and direction controlled by USCI)
PM_UCB1SIMO/PM_UCB1SDA
PM_UCB1SOMI/PM_UCB1SCL
PM_UCB1CLK/PM_UCA1STE
PM_UCA1TXD/PM_UCA1SIMO
PM_UCA1RXD/PM_UCA1SOMI
USCI_B1 SPI slave out master in (direction controlled by USCI)
USCI_B1 I2C clock (open drain and direction controlled by USCI)
USCI_A1 SPI slave transmit enable (direction controlled by USCI)
USCI_B1 clock input/output (direction controlled by USCI)
USCI_A1 UART TXD (Direction controlled by USCI – output)
USCI_A1 SPI slave in master out (direction controlled by USCI)
USCI_A1 UART RXD (Direction controlled by USCI – input)
USCI_A1 SPI slave out master in (direction controlled by USCI)
P4.6/P4MAP6
P4.7/P4MAP7
PM_NONE
PM_NONE
None
None
DVSS
DVSS
9.9.3 Oscillator and System Clock
The clock system in the MSP430F552x and MSP430F551x family of devices is supported by the Unified Clock
System (UCS) module that includes support for a 32-kHz watch crystal oscillator (XT1 in LF mode) (XT1 in HF
mode is not supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-
frequency oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency
crystal oscillator (XT2). The UCS module is designed to meet the requirements of both low system cost and low
power consumption. The UCS module features digital frequency-locked loop (FLL) hardware that, in conjunction
with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the selected FLL reference
frequency. The internal DCO provides a fast turnon clock source and stabilizes in 3.5 µs (typical). The UCS
module provides the following clock signals:
•
Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the
internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally
controlled oscillator (DCO).
•
•
•
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources made available to ACLK.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
9.9.4 Power-Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor
(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power on and power off. The SVS
and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply
voltage supervision (SVS) (the device is automatically reset) and supply voltage monitoring (SVM) (the device is
not automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.
9.9.5 Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs operations
with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication as well as signed
and unsigned multiply-and-accumulate operations.
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9.9.6 Real-Time Clock (RTC_A)
The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated real-
time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers that
can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar mode
integrates an internal calendar that compensates for months with less than 31 days and includes leap year
correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware.
9.9.7 Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
9.9.8 System Module (SYS)
The SYS module handles many of the system functions within the device. These include power-on reset and
power-up clear handling, NMI source selection and management, reset interrupt vector generators, bootstrap
loader entry mechanisms, and configuration management (device descriptors). It also includes a data exchange
mechanism through JTAG called a JTAG mailbox that can be used in the application. Table 9-9 lists the SYS
module interrupt vector registers.
Table 9-9. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER
ADDRESS
INTERRUPT EVENT
No interrupt pending
Brownout (BOR)
VALUE
00h
PRIORITY
02h
Highest
RST/NMI (POR)
04h
PMMSWBOR (BOR)
Wakeup from LPMx.5
Security violation (BOR)
SVSL (POR)
06h
08h
0Ah
0Ch
0Eh
10h
SVSH (POR)
SVML_OVP (POR)
SVMH_OVP (POR)
PMMSWPOR (POR)
WDT time-out (PUC)
WDT password violation (PUC)
KEYV flash password violation (PUC)
Reserved
SYSRSTIV, System Reset
019Eh
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
Peripheral area fetch (PUC)
PMM password violation (PUC)
Reserved
22h to 3Eh
00h
Lowest
Highest
No interrupt pending
SVMLIFG
02h
SVMHIFG
04h
SVSMLDLYIFG
06h
SVSMHDLYIFG
08h
SYSSNIV, System NMI
019Ch
VMAIFG
0Ah
0Ch
0Eh
10h
JMBINIFG
JMBOUTIFG
SVMLVLRIFG
SVMHVLRIFG
12h
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Table 9-9. System Module Interrupt Vector Registers (continued)
INTERRUPT VECTOR REGISTER
ADDRESS
INTERRUPT EVENT
VALUE
14h to 1Eh
00h
PRIORITY
Reserved
Lowest
No interrupt pending
NMIIFG
02h
Highest
Lowest
OFIFG
04h
SYSUNIV, User NMI
019Ah
ACCVIFG
06h
BUSIFG
08h
Reserved
0Ah to 1Eh
9.9.9 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM.
Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces
system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move
data to or from a peripheral.
The USB timestamp generator also uses the DMA trigger assignments described in Table 9-10.
Table 9-10. DMA Trigger Assignments
CHANNEL
TRIGGER(1)
0
1
2
0
1
DMAREQ
DMAREQ
DMAREQ
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA2CCR2 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA2CCR2 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA2CCR2 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
Reserved
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB1RXIFG
UCB1TXIFG
ADC12IFGx(2)
Reserved
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB1RXIFG
UCB1TXIFG
ADC12IFGx(2)
Reserved
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB1RXIFG
UCB1TXIFG
ADC12IFGx(2)
Reserved
Reserved
Reserved
Reserved
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Table 9-10. DMA Trigger Assignments (continued)
CHANNEL
TRIGGER(1)
0
1
2
27
28
29
30
31
USB FNRXD
USB ready
MPY ready
DMA2IFG
DMAE0
USB FNRXD
USB ready
MPY ready
DMA0IFG
DMAE0
USB FNRXD
USB ready
MPY ready
DMA1IFG
DMAE0
(1) If a reserved trigger source is selected, no Trigger1 is generated.
(2) Only on devices with ADC. Reserved on devices without ADC.
9.9.10 Universal Serial Communication Interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3- or 4-pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baud-rate detection, and IrDA. Each USCI module contains two portions,
A and B.
The USCI_An module provides support for SPI (3- or 4-pin), UART, enhanced UART, or IrDA.
The USCI_Bn module provides support for SPI (3- or 4-pin) or I2C.
The MSP430F55xx series includes two complete USCI modules (n = 0, 1).
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9.9.11 TA0
TA0 is a 16-bit timer and counter (Timer_A type) with five capture/compare registers. TA0 can support multiple
capture/compare registers, PWM outputs, and interval timing (see Table 9-11). TA0 also has extensive interrupt
capabilities. Interrupts can be generated from the counter on overflow conditions and from each of the capture/
compare registers.
Table 9-11. TA0 Signal Connections
INPUT PIN NUMBER
OUTPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
MODULE
BLOCK
RGC, YFF,
PN
RGC, YFF, ZXH,
PN
ZXH, ZQE
ZQE
18, B7, H2 -
21 - P1.0
P1.0
TA0CLK
TACLK
ACLK
ACLK
(internal)
Timer
NA
NA
SMCLK
(internal)
SMCLK
TACLK
CCI0A
18, B7, H2 -
21 - P1.0
P1.0
TA0CLK
TA0.0
19, B6, H3 -
22 - P1.1
P1.1
19, B6, H3 - P1.1
20, C6, J3 - P1.2
22 - P1.1
23 - P1.2
DVSS
DVSS
DVCC
CCI0B
GND
VCC
CCR0
CCR1
TA0
TA1
TA0.0
TA0.1
20, C6, J3 -
23 - P1.2
P1.2
TA0.1
CCI1A
CCI1B
ADC12 (internal) ADC12 (internal)
CBOUT
(internal)
(1)
(1)
ADC12SHSx = {1} ADC12SHSx = {1}
DVSS
DVCC
GND
VCC
21, C8, G4 -
24 - P1.3
P1.3
TA0.2
CCI2A
CCI2B
21, C8, G4 - P1.3
24 - P1.3
ACLK
(internal)
CCR2
TA2
TA0.2
DVSS
DVCC
GND
VCC
22, C7, H4 -
25 - P1.4
P1.4
TA0.3
CCI3A
22, C7, H4 - P1.4
23, D6, J4 - P1.5
25 - P1.4
26 - P1.5
DVSS
DVSS
DVCC
CCI3B
GND
VCC
CCR3
CCR4
TA3
TA4
TA0.3
TA0.4
23, D6, J4 -
26 - P1.5
P1.5
TA0.4
CCI4A
DVSS
DVSS
DVCC
CCI4B
GND
VCC
(1) Only on devices with ADC.
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
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9.9.12 TA1
TA1 is a 16-bit timer and counter (Timer_A type) with three capture/compare registers. TA1 can support multiple
capture/compare registers, PWM outputs, and interval timing (see Table 9-12). TA1 also has extensive interrupt
capabilities. Interrupts can be generated from the counter on overflow conditions and from each of the capture/
compare registers.
Table 9-12. TA1 Signal Connections
INPUT PIN NUMBER
OUTPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
MODULE
BLOCK
RGC, YFF,
PN
RGC, YFF,
PN
ZXH, ZQE
ZXH, ZQE
24, D7, G5 -
27 - P1.6
P1.6
TA1CLK
TACLK
ACLK
ACLK
(internal)
Timer
NA
NA
SMCLK
(internal)
SMCLK
TACLK
CCI0A
24, D7, G5 -
27 - P1.6
P1.6
TA1CLK
TA1.0
25, D8, H5 -
28 - P1.7
P1.7
25, D8, H5 -
28 - P1.7
P1.7
DVSS
DVSS
DVCC
CCI0B
GND
VCC
CCR0
CCR1
TA0
TA1
TA1.0
TA1.1
26, E5, J5 -
29 - P2.0
P2.0
26, E5, J5 -
29 - P2.0
P2.0
TA1.1
CCI1A
CCI1B
CBOUT
(internal)
DVSS
DVCC
GND
VCC
27, E8, G6 -
30 - P2.1
P2.1
27, E8, G6 -
30 - P2.1
P2.1
TA1.2
CCI2A
CCI2B
ACLK
(internal)
CCR2
TA2
TA1.2
DVSS
DVCC
GND
VCC
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
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9.9.13 TA2
TA2 is a 16-bit timer and counter (Timer_A type) with three capture/compare registers. TA2 can support multiple
capture/compare registers, PWM outputs, and interval timing (see Table 9-13). TA2 also has extensive interrupt
capabilities. Interrupts can be generated from the counter on overflow conditions and from each of the capture/
compare registers.
Table 9-13. TA2 Signal Connections
INPUT PIN NUMBER
OUTPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
MODULE
BLOCK
RGC, YFF,
PN
RGC, YFF,
PN
ZXH, ZQE
ZXH, ZQE
28, E7, J6 -
31 - P2.2
P2.2
TA2CLK
TACLK
ACLK
ACLK
(internal)
Timer
NA
NA
SMCLK
(internal)
SMCLK
TACLK
CCI0A
28, E7, J6 -
31 - P2.2
P2.2
TA2CLK
TA2.0
29, E6, H6 -
32 - P2.3
P2.3
29, E6, H6 -
32 - P2.3
P2.3
DVSS
DVSS
DVCC
CCI0B
GND
VCC
CCR0
CCR1
TA0
TA1
TA2.0
TA2.1
30, F8, J7 -
33 - P2.4
P2.4
30, F8, J7 -
33 - P2.4
P2.4
TA2.1
CCI1A
CCI1B
CBOUT
(internal)
DVSS
DVCC
GND
VCC
31, F7, J8 -
34 - P2.5
P2.5
31, F7, J8 -
34 - P2.5
P2.5
TA2.2
CCI2A
CCI2B
ACLK
(internal)
CCR2
TA2
TA2.2
DVSS
DVCC
GND
VCC
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
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9.9.14 TB0
TB0 is a 16-bit timer and counter (Timer_B type) with seven capture/compare registers. TB0 can support
multiple capture/compare registers, PWM outputs, and interval timing (see Table 9-14). TB0 also has extensive
interrupt capabilities. Interrupts can be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 9-14. TB0 Signal Connections
INPUT PIN NUMBER
OUTPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
MODULE
BLOCK
RGC, YFF,
PN
RGC, YFF, ZXH,
ZQE(1)
PN
ZXH, ZQE(1)
60 - P7.7
TB0CLK
TBCLK
ACLK
ACLK
(internal)
Timer
NA
NA
SMCLK
(internal)
SMCLK
60 - P7.7
55 - P5.6
TB0CLK
TB0.0
TBCLK
CCI0A
55 - P5.6
ADC12 (internal) ADC12 (internal)
(2)
(2)
55 - P5.6
TB0.0
CCI0B
CCR0
CCR1
TB0
TB1
TB0.0
TB0.1
ADC12SHSx = {2} ADC12SHSx = {2}
DVSS
DVCC
TB0.1
GND
VCC
56 - P5.7
CCI1A
56 - P5.7
CBOUT
(internal)
ADC12 (internal) ADC12 (internal)
ADC12SHSx = {3} ADC12SHSx = {3}
CCI1B
DVSS
DVCC
TB0.2
TB0.2
DVSS
DVCC
TB0.3
TB0.3
DVSS
DVCC
TB0.4
TB0.4
DVSS
DVCC
TB0.5
TB0.5
DVSS
DVCC
TB0.6
GND
VCC
57 - P7.4
57 - P7.4
CCI2A
CCI2B
GND
57 - P7.4
58 - P7.5
59 - P7.6
42 - P3.5
43 - P3.6
CCR2
CCR3
CCR4
CCR5
TB2
TB3
TB4
TB5
TB0.2
TB0.3
TB0.4
TB0.5
VCC
58 - P7.5
58 - P7.5
CCI3A
CCI3B
GND
VCC
59 - P7.6
59 - P7.6
CCI4A
CCI4B
GND
VCC
42 - P3.5
42 - P3.5
CCI5A
CCI5B
GND
VCC
43 - P3.6
CCI6A
ACLK
(internal)
CCI6B
CCR6
TB6
TB0.6
DVSS
DVCC
GND
VCC
(1) Timer functions are selectable through the port mapping controller.
(2) Only on devices with ADC
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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9.9.15 Comparator_B
The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,
battery voltage supervision, and monitoring of external analog signals.
9.9.16 ADC12_A
The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator, and a 16 word conversion-and-control buffer. The conversion-
and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU
intervention.
9.9.17 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used for data
checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
9.9.18 Voltage Reference (REF) Module
The REF module generates all critical reference voltages that can be used by the various analog peripherals in
the device.
9.9.19 Universal Serial Bus (USB)
The USB module is a fully integrated USB interface that is compliant with the USB 2.0 specification. The module
supports full-speed operation of control, interrupt, and bulk transfers. The module includes an integrated LDO,
PHY, and PLL. The PLL is highly flexible and supports a wide range of input clock frequencies. USB RAM, when
not used for USB communication, can be used by the system.
9.9.20 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The L version of the EEM has the following features:
•
•
•
•
•
•
•
Eight hardware triggers or breakpoints on memory access
Two hardware triggers or breakpoints on CPU register write access
Up to 10 hardware triggers can be combined to form complex triggers or breakpoints
Two cycle counters
Sequencer
State storage
Clock control on module level
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
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9.9.21 Peripheral File Map
Table 9-15 lists the base address for the registers of each module. Table 9-16 through Table 9-45 list the
available registers in each module.
Table 9-15. Peripherals
OFFSET ADDRESS
MODULE NAME
BASE ADDRESS
RANGE
Special Functions (see Table 9-16)
PMM (see Table 9-17)
0100h
0120h
0140h
0150h
0158h
015Ch
0160h
0180h
01B0h
01C0h
01E0h
0200h
0220h
0240h
0260h
0320h
0340h
0380h
03C0h
0400h
04A0h
04C0h
0500h
0510h
0520h
0530h
05C0h
05E0h
0600h
0620h
0700h
08C0h
0900h
0920h
000h to 01Fh
000h to 010h
000h to 00Fh
000h to 007h
000h to 001h
000h to 001h
000h to 01Fh
000h to 01Fh
000h to 001h
000h to 002h
000h to 007h
000h to 01Fh
000h to 00Bh
000h to 00Bh
000h to 00Bh
000h to 01Fh
000h to 02Eh
000h to 02Eh
000h to 02Eh
000h to 02Eh
000h to 01Bh
000h to 02Fh
000h to 00Fh
000h to 00Ah
000h to 00Ah
000h to 00Ah
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 03Eh
000h to 00Fh
000h to 014h
000h to 01Fh
Flash Control (see Table 9-18)
CRC16 (see Table 9-19)
RAM Control (see Table 9-20)
Watchdog (see Table 9-21)
UCS (see Table 9-22)
SYS (see Table 9-23)
Shared Reference (see Table 9-24)
Port Mapping Control (see Table 9-25)
Port Mapping Port P4 (see Table 9-25)
Port P1 and P2 (see Table 9-26)
Port P3 and P4 (see Table 9-27)
Port P5 and P6 (see Table 9-28)
Port P7 and P8 (see Table 9-29)
Port PJ (see Table 9-30)
TA0 (see Table 9-31)
TA1 (see Table 9-32)
TB0 (see Table 9-33)
TA2 (see Table 9-34)
Real-Time Clock (RTC_A) (see Table 9-35)
32-Bit Hardware Multiplier (see Table 9-36)
DMA General Control (see Table 9-37)
DMA Channel 0 (see Table 9-37)
DMA Channel 1 (see Table 9-37)
DMA Channel 2 (see Table 9-37)
USCI_A0 (see Table 9-38)
USCI_B0 (see Table 9-39)
USCI_A1 (see Table 9-40)
USCI_B1 (see Table 9-41)
ADC12_A (see Table 9-42)
Comparator_B (see Table 9-43)
USB Configuration (see Table 9-44)
USB Control (see Table 9-45)
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
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Table 9-16. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SFR interrupt enable
SFR interrupt flag
SFRIE1
00h
02h
04h
SFRIFG1
SFR reset pin control
SFRRPCR
Table 9-17. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PMM control 0
PMMCTL0
00h
02h
04h
06h
0Ch
0Eh
10h
PMM control 1
PMMCTL1
SVSMHCTL
SVSMLCTL
PMMIFG
SVS high-side control
SVS low-side control
PMM interrupt flags
PMM interrupt enable
PMM power mode 5 control
PMMIE
PM5CTL0
Table 9-18. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
OFFSET
Flash control 1
Flash control 3
Flash control 4
FCTL1
FCTL3
FCTL4
00h
04h
06h
Table 9-19. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
CRC data input
CRC16DI
00h
02h
04h
06h
CRC data input reverse byte
CRC initialization and result
CRC result reverse byte
CRCDIRB
CRCINIRES
CRCRESR
Table 9-20. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
REGISTER
OFFSET
OFFSET
RAM control 0
RCCTL0
00h
00h
Table 9-21. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
REGISTER
Watchdog timer control
WDTCTL
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
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Table 9-22. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
OFFSET
UCS control 0
UCS control 1
UCS control 2
UCS control 3
UCS control 4
UCS control 5
UCS control 6
UCS control 7
UCS control 8
UCSCTL0
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
UCSCTL1
UCSCTL2
UCSCTL3
UCSCTL4
UCSCTL5
UCSCTL6
UCSCTL7
UCSCTL8
Table 9-23. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
02h
06h
08h
0Ah
0Ch
0Eh
18h
1Ah
1Ch
1Eh
Bootloader configuration area
JTAG mailbox control
SYSBSLC
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSBERRIV
SYSUNIV
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
Bus error vector generator
User NMI vector generator
System NMI vector generator
Reset vector generator
SYSSNIV
SYSRSTIV
Table 9-24. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
OFFSET
Shared reference control
REFCTL
00h
Table 9-25. Port Mapping Registers
(Base Address of Port Mapping Control: 01C0h, Port P4: 01E0h)
REGISTER DESCRIPTION
REGISTER
Port mapping key and ID
Port mapping control
Port P4.0 mapping
Port P4.1 mapping
Port P4.2 mapping
Port P4.3 mapping
Port P4.4 mapping
Port P4.5 mapping
Port P4.6 mapping
Port P4.7 mapping
PMAPKEYID
00h
02h
00h
01h
02h
03h
04h
05h
06h
07h
PMAPCTL
P4MAP0
P4MAP1
P4MAP2
P4MAP3
P4MAP4
P4MAP5
P4MAP6
P4MAP7
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
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Table 9-26. Port P1 and P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
02h
04h
06h
08h
0Ah
0Eh
18h
1Ah
1Ch
01h
03h
05h
07h
09h
0Bh
1Eh
19h
1Bh
1Dh
Port P1 output
P1OUT
P1DIR
P1REN
P1DS
P1SEL
P1IV
Port P1 direction
Port P1 resistor enable
Port P1 drive strength
Port P1 selection
Port P1 interrupt vector word
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
P1IES
P1IE
P1IFG
P2IN
Port P2 output
P2OUT
P2DIR
P2REN
P2DS
P2SEL
P2IV
Port P2 direction
Port P2 resistor enable
Port P2 drive strength
Port P2 selection
Port P2 interrupt vector word
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
P2IES
P2IE
P2IFG
Table 9-27. Port P3 and P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
02h
04h
06h
08h
0Ah
01h
03h
05h
07h
09h
0Bh
Port P3 output
P3OUT
P3DIR
P3REN
P3DS
Port P3 direction
Port P3 resistor enable
Port P3 drive strength
Port P3 selection
Port P4 input
P3SEL
P4IN
Port P4 output
P4OUT
P4DIR
P4REN
P4DS
Port P4 direction
Port P4 resistor enable
Port P4 drive strength
Port P4 selection
P4SEL
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Table 9-28. Port P5 and P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
02h
04h
06h
08h
0Ah
01h
03h
05h
07h
09h
0Bh
Port P5 output
P5OUT
P5DIR
P5REN
P5DS
Port P5 direction
Port P5 resistor enable
Port P5 drive strength
Port P5 selection
Port P6 input
P5SEL
P6IN
Port P6 output
P6OUT
P6DIR
P6REN
P6DS
Port P6 direction
Port P6 resistor enable
Port P6 drive strength
Port P6 selection
P6SEL
Table 9-29. Port P7 and P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 input
P7IN
00h
02h
04h
06h
08h
0Ah
01h
03h
05h
07h
09h
0Bh
Port P7 output
P7OUT
P7DIR
P7REN
P7DS
Port P7 direction
Port P7 resistor enable
Port P7 drive strength
Port P7 selection
Port P8 input
P7SEL
P8IN
Port P8 output
P8OUT
P8DIR
P8REN
P8DS
Port P8 direction
Port P8 resistor enable
Port P8 drive strength
Port P8 selection
P8SEL
Table 9-30. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
02h
04h
06h
08h
Port PJ output
PJOUT
PJDIR
PJREN
PJDS
Port PJ direction
Port PJ resistor enable
Port PJ drive strength
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Table 9-31. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0 control
TA0CTL
00h
02h
04h
06h
08h
0Ah
10h
12h
14h
16h
18h
1Ah
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Capture/compare control 3
Capture/compare control 4
TA0 counter
TA0CCTL0
TA0CCTL1
TA0CCTL2
TA0CCTL3
TA0CCTL4
TA0R
Capture/compare 0
Capture/compare 1
Capture/compare 2
Capture/compare 3
Capture/compare 4
TA0 expansion 0
TA0CCR0
TA0CCR1
TA0CCR2
TA0CCR3
TA0CCR4
TA0EX0
TA0 interrupt vector
TA0IV
Table 9-32. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA1 control
TA1CTL
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA1 counter
TA1CCTL0
TA1CCTL1
TA1CCTL2
TA1R
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA1 expansion 0
TA1CCR0
TA1CCR1
TA1CCR2
TA1EX0
TA1 interrupt vector
TA1IV
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Table 9-33. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB0 control
TB0CTL
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Capture/compare control 3
Capture/compare control 4
Capture/compare control 5
Capture/compare control 6
TB0 counter
TB0CCTL0
TB0CCTL1
TB0CCTL2
TB0CCTL3
TB0CCTL4
TB0CCTL5
TB0CCTL6
TB0R
Capture/compare 0
TB0CCR0
TB0CCR1
TB0CCR2
TB0CCR3
TB0CCR4
TB0CCR5
TB0CCR6
TB0EX0
Capture/compare 1
Capture/compare 2
Capture/compare 3
Capture/compare 4
Capture/compare 5
Capture/compare 6
TB0 expansion 0
TB0 interrupt vector
TB0IV
Table 9-34. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA2 control
TA2CTL
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA2 counter
TA2CCTL0
TA2CCTL1
TA2CCTL2
TA2R
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA2 expansion 0
TA2CCR0
TA2CCR1
TA2CCR2
TA2EX0
TA2 interrupt vector
TA2IV
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Table 9-35. Real-Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RTC control 0
RTCCTL0
00h
01h
02h
03h
08h
0Ah
0Ch
0Dh
0Eh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
RTC control 1
RTCCTL1
RTC control 2
RTCCTL2
RTC control 3
RTCCTL3
RTC prescaler 0 control
RTC prescaler 1 control
RTC prescaler 0
RTC prescaler 1
RTC interrupt vector word
RTCPS0CTL
RTCPS1CTL
RTCPS0
RTCPS1
RTCIV
RTC seconds, RTC counter 1
RTC minutes, RTC counter 2
RTC hours, RTC counter 3
RTC day of week, RTC counter 4
RTC days
RTCSEC, RTCNT1
RTCMIN, RTCNT2
RTCHOUR, RTCNT3
RTCDOW, RTCNT4
RTCDAY
RTC month
RTCMON
RTC year low
RTCYEARL
RTCYEARH
RTCAMIN
RTC year high
RTC alarm minutes
RTC alarm hours
RTCAHOUR
RTCADOW
RTCADAY
RTC alarm day of week
RTC alarm days
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Table 9-36. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
16-bit operand 1 – signed multiply
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
MPYS
MAC
MACS
OP2
16 × 16 result low word
RESLO
RESHI
16 × 16 result high word
16 × 16 sum extension
SUMEXT
MPY32L
MPY32H
MPYS32L
MPYS32H
MAC32L
MAC32H
MACS32L
MACS32H
OP2L
32-bit operand 1 – multiply low word
32-bit operand 1 – multiply high word
32-bit operand 1 – signed multiply low word
32-bit operand 1 – signed multiply high word
32-bit operand 1 – multiply accumulate low word
32-bit operand 1 – multiply accumulate high word
32-bit operand 1 – signed multiply accumulate low word
32-bit operand 1 – signed multiply accumulate high word
32-bit operand 2 – low word
32-bit operand 2 – high word
OP2H
32 × 32 result 0 – least significant word
32 × 32 result 1
RES0
RES1
32 × 32 result 2
RES2
32 × 32 result 3 – most significant word
MPY32 control 0
RES3
MPY32CTL0
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Table 9-37. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 0 control
DMA0CTL
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Eh
DMA channel 0 source address low
DMA channel 0 source address high
DMA channel 0 destination address low
DMA channel 0 destination address high
DMA channel 0 transfer size
DMA0SAL
DMA0SAH
DMA0DAL
DMA0DAH
DMA0SZ
DMA channel 1 control
DMA1CTL
DMA1SAL
DMA1SAH
DMA1DAL
DMA1DAH
DMA1SZ
DMA channel 1 source address low
DMA channel 1 source address high
DMA channel 1 destination address low
DMA channel 1 destination address high
DMA channel 1 transfer size
DMA channel 2 control
DMA2CTL
DMA2SAL
DMA2SAH
DMA2DAL
DMA2DAH
DMA2SZ
DMA channel 2 source address low
DMA channel 2 source address high
DMA channel 2 destination address low
DMA channel 2 destination address high
DMA channel 2 transfer size
DMA module control 0
DMACTL0
DMACTL1
DMACTL2
DMACTL3
DMACTL4
DMAIV
DMA module control 1
DMA module control 2
DMA module control 3
DMA module control 4
DMA interrupt vector
Table 9-38. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 1
UCA0CTL1
00h
01h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ch
1Dh
1Eh
USCI control 0
UCA0CTL0
UCA0BR0
USCI baud rate 0
USCI baud rate 1
UCA0BR1
USCI modulation control
USCI status
UCA0MCTL
UCA0STAT
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
UCA0IRTCTL
UCA0IRRCTL
UCA0IE
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
UCA0IFG
UCA0IV
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Table 9-39. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 1
USCI synchronous control 0
USCI synchronous bit rate 0
USCI synchronous bit rate 1
USCI synchronous status
UCB0CTL1
00h
01h
06h
07h
0Ah
0Ch
0Eh
10h
12h
1Ch
1Dh
1Eh
UCB0CTL0
UCB0BR0
UCB0BR1
UCB0STAT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA
UCB0I2CSA
UCB0IE
USCI synchronous receive buffer
USCI synchronous transmit buffer
USCI I2C own address
USCI I2C slave address
USCI interrupt enable
USCI interrupt flags
UCB0IFG
USCI interrupt vector word
UCB0IV
Table 9-40. USCI_A1 Registers (Base Address: 0600h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 1
UCA1CTL1
00h
01h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ch
1Dh
1Eh
USCI control 0
UCA1CTL0
UCA1BR0
USCI baud rate 0
USCI baud rate 1
UCA1BR1
USCI modulation control
USCI status
UCA1MCTL
UCA1STAT
UCA1RXBUF
UCA1TXBUF
UCA1ABCTL
UCA1IRTCTL
UCA1IRRCTL
UCA1IE
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
UCA1IFG
UCA1IV
Table 9-41. USCI_B1 Registers (Base Address: 0620h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 1
USCI synchronous control 0
USCI synchronous bit rate 0
USCI synchronous bit rate 1
USCI synchronous status
UCB1CTL1
00h
01h
06h
07h
0Ah
0Ch
0Eh
10h
12h
1Ch
1Dh
1Eh
UCB1CTL0
UCB1BR0
UCB1BR1
UCB1STAT
UCB1RXBUF
UCB1TXBUF
UCB1I2COA
UCB1I2CSA
UCB1IE
USCI synchronous receive buffer
USCI synchronous transmit buffer
USCI I2C own address
USCI I2C slave address
USCI interrupt enable
USCI interrupt flags
UCB1IFG
USCI interrupt vector word
UCB1IV
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Table 9-42. ADC12_A Registers (Base Address: 0700h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Control 0
ADC12CTL0
00h
02h
04h
0Ah
0Ch
0Eh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
36h
38h
3Ah
3Ch
3Eh
Control 1
ADC12CTL1
Control 2
ADC12CTL2
Interrupt flag
ADC12IFG
Interrupt enable
ADC12IE
Interrupt vector word
ADC memory control 0
ADC memory control 1
ADC memory control 2
ADC memory control 3
ADC memory control 4
ADC memory control 5
ADC memory control 6
ADC memory control 7
ADC memory control 8
ADC memory control 9
ADC memory control 10
ADC memory control 11
ADC memory control 12
ADC memory control 13
ADC memory control 14
ADC memory control 15
Conversion memory 0
Conversion memory 1
Conversion memory 2
Conversion memory 3
Conversion memory 4
Conversion memory 5
Conversion memory 6
Conversion memory 7
Conversion memory 8
Conversion memory 9
Conversion memory 10
Conversion memory 11
Conversion memory 12
Conversion memory 13
Conversion memory 14
Conversion memory 15
ADC12IV
ADC12MCTL0
ADC12MCTL1
ADC12MCTL2
ADC12MCTL3
ADC12MCTL4
ADC12MCTL5
ADC12MCTL6
ADC12MCTL7
ADC12MCTL8
ADC12MCTL9
ADC12MCTL10
ADC12MCTL11
ADC12MCTL12
ADC12MCTL13
ADC12MCTL14
ADC12MCTL15
ADC12MEM0
ADC12MEM1
ADC12MEM2
ADC12MEM3
ADC12MEM4
ADC12MEM5
ADC12MEM6
ADC12MEM7
ADC12MEM8
ADC12MEM9
ADC12MEM10
ADC12MEM11
ADC12MEM12
ADC12MEM13
ADC12MEM14
ADC12MEM15
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Table 9-43. Comparator_B Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Comp_B control 0
Comp_B control 1
Comp_B control 2
Comp_B control 3
Comp_B interrupt
CBCTL0
00h
02h
04h
06h
0Ch
0Eh
CBCTL1
CBCTL2
CBCTL3
CBINT
Comp_B interrupt vector word
CBIV
Table 9-44. USB Configuration Registers (Base Address: 0900h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USB key and ID
USBKEYID
00h
02h
04h
08h
10h
12h
14h
USB module configuration
USB PHY control
USB power control
USB PLL control
USBCNF
USBPHYCTL
USBPWRCTL
USBPLLCTL
USBPLLDIV
USBPLLIR
USB PLL divider
USB PLL interrupts
Table 9-45. USB Control Registers (Base Address: 0920h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Input endpoint_0 configuration
Input endpoint_0 byte count
Output endpoint_0 configuration
Output endpoint_0 byte count
Input endpoint interrupt enables
Output endpoint interrupt enables
Input endpoint interrupt flags
Output endpoint interrupt flags
USB interrupt vector
USBIEPCNF_0
00h
01h
02h
03h
0Eh
0Fh
10h
11h
12h
16h
18h
1Ah
1Ch
1Dh
1Eh
1Fh
USBIEPCNT_0
USBOEPCNF_0
USBOEPCNT_0
USBIEPIE
USBOEPIE
USBIEPIFG
USBOEPIFG
USBIV
USB maintenance
USBMAINT
USBTSREG
USBFN
Timestamp
USB frame number
USB control
USBCTL
USB interrupt enables
USB interrupt flags
USBIE
USBIFG
Function address
USBFUNADR
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
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9.10 Input/Output Diagrams
9.10.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
Figure 9-2 shows the port diagram. Table 9-46 summarizes the selection of the pin function.
Pad Logic
P1REN.x
DVSS
DVCC
0
1
1
P1DIR.x
0
1
Direction
0: Input
1: Output
From module
P1OUT.x
0
1
From module
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
P1.5/TA0.4
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
EN
D
To module
P1IRQ.x
P1IE.x
EN
Q
P1IFG.x
Set
P1SEL.x
P1IES.x
Interrupt
Edge
Select
Figure 9-2. Port P1 (P1.0 to P1.7) Diagram
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Table 9-46. Port P1 (P1.0 to P1.7) Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
P1.0 (I/O)
TA0CLK
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
P1.0/TA0CLK/ACLK
0
0
ACLK
1
P1.1 (I/O)
TA0.CCI0A
TA0.0
I: 0; O: 1
P1.1/TA0.0
1
2
3
4
5
6
7
0
1
P1.2 (I/O)
TA0.CCI1A
TA0.1
I: 0; O: 1
P1.2/TA0.1
0
1
P1.3 (I/O)
TA0.CCI2A
TA0.2
I: 0; O: 1
P1.3/TA0.2
0
1
P1.4 (I/O)
TA0.CCI3A
TA0.3
I: 0; O: 1
P1.4/TA0.3
0
1
P1.5 (I/O)
TA0.CCI4A
TA0.4
I: 0; O: 1
P1.5/TA0.4
0
1
P1.6 (I/O)
TA1CLK
I: 0; O: 1
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
0
CBOUT comparator B
P1.7 (I/O)
TA1.CCI0A
TA1.0
1
I: 0; O: 1
0
1
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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9.10.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
Figure 9-3 shows the port diagram. Table 9-47 summarizes the selection of the pin function.
Pad Logic
P2REN.x
DVSS
DVCC
0
1
1
P2DIR.x
0
1
Direction
0: Input
1: Output
From module
P2OUT.x
0
1
From module
P2.0/TA1.1
P2.1/TA1.2
P2.2/TA2CLK/SMCLK
P2.3/TA2.0
P2.4/TA2.1
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
P2.5/TA2.2
P2.6/RTCCLK/DMAE0
P2.7/UB0STE/UCA0CLK
EN
D
To module
To module
P2IE.x
EN
Q
P2IFG.x
Set
P2SEL.x
P2IES.x
Interrupt
Edge
Select
Figure 9-3. Port P2 (P2.0 to P2.7) Diagram
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Table 9-47. Port P2 (P2.0 to P2.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL.x
P2.0 (I/O)
TA1.CCI1A
TA1.1
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
P2.0/TA1.1
0
0
1
P2.1 (I/O)
TA1.CCI2A
TA1.2
I: 0; O: 1
P2.1/TA1.2
1
2
3
4
5
0
1
P2.2 (I/O)
TA2CLK
I: 0; O: 1
P2.2/TA2CLK/SMCLK
P2.3/TA2.0
0
SMCLK
1
P2.3 (I/O)
TA2.CCI0A
TA2.0
I: 0; O: 1
0
1
P2.4 (I/O)
TA2.CCI1A
TA2.1
I: 0; O: 1
P2.4/TA2.1
0
1
P2.5 (I/O)
TA2.CCI2A
TA2.2
I: 0; O: 1
P2.5/TA2.2
0
1
P2.6 (I/O)
DMAE0
I: 0; O: 1
P2.6/RTCCLK/DMAE0
6
7
0
RTCCLK
P2.7 (I/O)
UCB0STE/UCA0CLK(2) (3)
1
I: 0; O: 1
X
P2.7/UCB0STE/UCA0CLK
(1) X = Don't care
(2) The pin direction is controlled by the USCI module.
(3) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI B0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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9.10.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
Figure 9-4 shows the port diagram. Table 9-48 summarizes the selection of the pin function.
Pad Logic
P3REN.x
DVSS
DVCC
0
1
1
P3DIR.x
0
1
Direction
0: Input
1: Output
From module
P3OUT.x
0
1
From module
P3.0/UCB0SIMO/UCB0SDA
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
P3.4/UCA0RXD/UCA0SOMI
P3.5/TB0.5
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
P3.6/TB0.6
P3.7/TB0OUTH/SVMOUT
EN
D
To module
Figure 9-4. Port P3 (P3.0 to P3.7) Diagram
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Table 9-48. Port P3 (P3.0 to P3.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P3.x)
x
0
1
2
3
4
FUNCTION
P3DIR.x
P3SEL.x
P3.0 (I/O)
I: 0; O: 1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
1
0
1
1
P3.0/UCB0SIMO/UCB0SDA
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
P3.4/UCA0RXD/UCA0SOMI
UCB0SIMO/UCB0SDA(2) (3)
X
P3.1 (I/O)
I: 0; O: 1
UCB0SOMI/UCB0SCL(2) (3)
P3.2 (I/O)
X
I: 0; O: 1
UCB0CLK/UCA0STE(2) (4)
X
P3.3 (I/O)
I: 0; O: 1
UCA0TXD/UCA0SIMO(2)
P3.4 (I/O)
X
I: 0; O: 1
UCA0RXD/UCA0SOMI(2)
X
P3.5 (I/O)
I: 0; O: 1
P3.5/TB0.5(5)
P3.6/TB0.6(5)
5
6
7
TB0.CCI5A
0
TB0.5
1
P3.6 (I/O)
I: 0; O: 1
TB0.CCI6A
0
TB0.6
1
P3.7 (I/O)
I: 0; O: 1
P3.7/TB0OUTH/SVMOUT(5)
(1) X = Don't care
TB0OUTH
0
1
SVMOUT
(2) The pin direction is controlled by the USCI module.
(3) If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
(4) UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI A0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
(5) F5529, F5527, F5525, F5521, F5519, F5517, F5515 devices only.
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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9.10.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
Figure 9-5 shows the port diagram. Table 9-49 summarizes the selection of the pin function.
Pad Logic
P4REN.x
DVSS
DVCC
0
1
1
P4DIR.x
0
1
Direction
0: Input
1: Output
from Port Mapping Control
P4OUT.x
0
1
from Port Mapping Control
P4.0/P4MAP0
P4.1/P4MAP1
P4.2/P4MAP2
P4.3/P4MAP3
P4.4/P4MAP4
P4.5/P4MAP5
P4.6/P4MAP6
P4.7/P4MAP7
P4DS.x
0: Low drive
1: High drive
P4SEL.x
P4IN.x
EN
D
to Port Mapping Control
Figure 9-5. Port P4 (P4.0 to P4.7) Diagram
Table 9-49. Port P4 (P4.0 to P4.7) Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (P4.x)
P4.0/P4MAP0
P4.1/P4MAP1
P4.2/P4MAP2
P4.3/P4MAP3
P4.4/P4MAP4
P4.5/P4MAP5
P4.6/P4MAP6
P4.7/P4MAP7
x
0
1
2
3
4
5
6
7
FUNCTION
P4DIR.x(1)
P4SEL.x
P4MAPx
P4.0 (I/O)
I: 0; O: 1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
≤ 30
X
Mapped secondary digital function
P4.1 (I/O)
X
I: 0; O: 1
Mapped secondary digital function
P4.2 (I/O)
X
≤ 30
X
I: 0; O: 1
Mapped secondary digital function
P4.3 (I/O)
X
≤ 30
X
I: 0; O: 1
Mapped secondary digital function
P4.4 (I/O)
X
≤ 30
X
I: 0; O: 1
Mapped secondary digital function
P4.5 (I/O)
X
≤ 30
X
I: 0; O: 1
Mapped secondary digital function
P4.6 (I/O)
X
I: 0; O: 1
X
≤ 30
X
Mapped secondary digital function
P4.7 (I/O)
≤ 30
X
I: 0; O: 1
X
Mapped secondary digital function
≤ 30
(1) The direction of some mapped secondary functions are controlled directly by the module. See Table 9-7 for specific direction control
information of mapped secondary functions.
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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9.10.5 Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
Figure 9-6 shows the port diagram. Table 9-50 summarizes the selection of the pin function.
Pad Logic
to/from Reference
(n/a MSP430F551x)
(n/a MSPF430F551x)
to ADC12
(n/a MSPF430F551x)
INCHx = x
P5REN.x
DVSS
DVCC
0
1
1
P5DIR.x
0
1
P5OUT.x
0
1
From module
P5.0/(A8/VREF+/VeREF+)
P5.1/(A9/VREF–/VeREF–)
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
EN
D
To module
Figure 9-6. Port P5 (P5.0 and P5.1) Diagram
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Table 9-50. Port P5 (P5.0 and P5.1) Pin Functions
CONTROL BITS OR SIGNALS(3)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL.x
REFOUT
P5.0 (I/O)(4)
A8/VeREF+(5)
A8/VREF+(6)
P5.1 (I/O)(4)
A9/VeREF–(7)
A9/VREF–(8)
I: 0; O: 1
0
1
1
0
1
1
X
0
1
X
0
1
P5.0/A8/VREF+/VeREF+(1)
P5.1/A9/VREF-/VeREF-(2)
0
X
X
I: 0; O: 1
1
X
X
(1) VREF+/VeREF+ available on MSP430F552x devices only.
(2) VREF-/VeREF- available on MSP430F552x devices only.
(3) X = Don't care
(4) Default condition
(5) Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A when available. Channel
A8, when selected with the INCHx bits, is connected to the VREF+/VeREF+ pin.
(6) Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. The VREF+ reference is available at the pin. Channel A8, when selected with the INCHx bits, is connected to the
VREF+/VeREF+ pin.
(7) Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A when available. Channel
A9, when selected with the INCHx bits, is connected to the VREF-/VeREF- pin.
(8) Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. The VREF– reference is available at the pin. Channel A9, when selected with the INCHx bits, is connected to the
VREF-/VeREF- pin.
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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9.10.6 Port P5 (P5.2 and P5.3) Input/Output With Schmitt Trigger
Figure 9-7 and Figure 9-8 show the port diagrams. Table 9-51 summarizes the selection of the pin function.
Pad Logic
To XT2
P5REN.2
DVSS
DVCC
0
1
1
P5DIR.2
0
1
P5OUT.2
0
1
Module X OUT
P5.2/XT2IN
P5DS.2
0: Low drive
1: High drive
P5SEL.2
P5IN.2
Bus
Keeper
EN
D
Module X IN
Figure 9-7. Port P5 (P5.2) Diagram
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Pad Logic
To XT2
P5REN.3
DVSS
DVCC
0
1
1
P5DIR.3
0
1
P5OUT.3
0
1
Module X OUT
P5.3/XT2OUT
P5SEL.2
P5DS.3
0: Low drive
1: High drive
XT2BYPASS
P5SEL.3
P5IN.3
EN
D
Bus
Keeper
Module X IN
Figure 9-8. Port P5 (P5.3) Diagram
Table 9-51. Port P5 (P5.2 and P5.3) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL.2
P5SEL.3
XT2BYPASS
P5.2 (I/O)
I: 0; O: 1
0
1
1
0
1
1
X
X
X
0
X
0
1
X
0
1
P5.2/XT2IN
2
XT2IN crystal mode(2)
XT2IN bypass mode(2)
P5.3 (I/O)
X
X
I: 0; O: 1
P5.3/XT2OUT
3
XT2OUT crystal mode(3)
P5.3 (I/O)(3)
X
X
X
0
(1) X = Don't care
(2) Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal
mode or bypass mode.
(3) Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as
general-purpose I/O.
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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9.10.7 Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
Figure 9-9 and Figure 9-10 show the port diagrams. Table 9-52 summarizes the selection of the pin function.
Pad Logic
to XT1
P5REN.4
DVSS
DVCC
0
1
1
P5DIR.4
0
1
P5OUT.4
0
1
Module X OUT
P5.4/XIN
P5DS.4
0: Low drive
1: High drive
P5SEL.4
P5IN.4
Bus
Keeper
EN
D
Module X IN
Figure 9-9. Port P5 (P5.4) Diagram
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Pad Logic
to XT1
P5REN.5
DVSS
DVCC
0
1
1
P5DIR.5
0
1
P5OUT.5
0
1
Module X OUT
P5.5/XOUT
P5SEL.4
P5DS.5
0: Low drive
1: High drive
XT1BYPASS
P5SEL.5
P5IN.5
Bus
Keeper
EN
D
Module X IN
Figure 9-10. Port P5 (P5.5) Diagram
Table 9-52. Port P5 (P5.4 and P5.5) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL.4
P5SEL.5
XT1BYPASS
P5.4 (I/O)
I: 0; O: 1
0
1
1
0
1
1
X
X
X
0
X
0
1
X
0
1
P5.4/XIN
4
XIN crystal mode(2)
XIN bypass mode(2)
P5.5 (I/O)
X
X
I: 0; O: 1
P5.5/XOUT
5
XOUT crystal mode(3)
P5.5 (I/O)(3)
X
X
X
0
(1) X = Don't care
(2) Setting P5SEL.4 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.4 is configured for crystal
mode or bypass mode.
(3) Setting P5SEL.4 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.5 can be used as
general-purpose I/O.
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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9.10.8 Port P5 (P5.6 and P5.7) Input/Output With Schmitt Trigger
Figure 9-11 shows the port diagram. Table 9-53 summarizes the selection of the pin function.
Pad Logic
P5REN.x
DVSS
DVCC
0
1
1
P5DIR.x
0
1
Direction
0: Input
1: Output
From Module
P5OUT.x
0
1
P5DS.x
0: Low drive
1: High drive
P5.6/TB0.0
P5.7/TB0.1
P5SEL.x
P5IN.x
EN
D
To module
Figure 9-11. Port P5 (P5.6 and P5.7) Diagram
Table 9-53. Port P5 (P5.6 and P5.7) Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (P5.x)
x
6
7
FUNCTION
P5DIR.x
P5SEL.x
P5.6 (I/O)
TB0.CCI0A
TB0.0
I: 0; O: 1
0
1
1
1
1
P5.6/TB0.0(1)
P5.7/TB0.1(1)
0
1
0
1
TB0.CCI1A
TB0.1
(1) F5529, F5527, F5525, F5521, F5519, F5517, F5515 devices only.
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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9.10.9 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
Figure 9-12 shows the port diagram. Table 9-54 summarizes the selection of the pin function.
Pad Logic
to ADC12
(n/a MSPF430F551x)
INCHx = x
(n/a MSPF430F551x)
to Comparator_B
from Comparator_B
CBPD.x
P6REN.x
P6DIR.x
DVSS
DVCC
0
1
1
0
1
Direction
0: Input
1: Output
P6OUT.x
0
1
From module
P6.0/CB0/(A0)
P6.1/CB1/(A1)
P6.2/CB2/(A2)
P6.3/CB3/(A3)
P6.4/CB4/(A4)
P6.5/CB5/(A5)
P6.6/CB6/(A6)
P6.7/CB7/(A7)
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
EN
D
To module
Figure 9-12. Port P6 (P6.0 to P6.7) Diagram
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Table 9-54. Port P6 (P6.0 to P6.7) Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (P6.x)
x
FUNCTION
P6DIR.x
P6SEL.x
CBPD
0
P6.0 (I/O)
I: 0; O: 1
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
P6.0/CB0/(A0)
0
A0 (only MSP430F552x)
CB0(1)
X
X
1
X
P6.1 (I/O)
I: 0; O: 1
0
P6.1/CB1/(A1)
P6.2/CB2/(A2)
P6.3/CB3/(A3)
P6.4/CB4/(A4)
P6.5/CB5/(A5)
P6.6/CB6/(A6)
P6.7/CB7/(A7)
1
2
3
4
5
6
7
A1 (only MSP430F552x)
CB1(1)
X
X
1
X
P6.2 (I/O)
I: 0; O: 1
0
A2 (only MSP430F552x)
CB2(1)
X
X
1
X
P6.3 (I/O)
I: 0; O: 1
0
A3 (only MSP430F552x)
CB3(1)
X
X
1
X
P6.4 (I/O)
I: 0; O: 1
0
A4 (only MSP430F552x)
CB4(1)
X
X
1
X
P6.5 (I/O)
I: 0; O: 1
0
A5 (only MSP430F552x)
CB5(1)
X
X
1
X
P6.6 (I/O)
I: 0; O: 1
0
A6 (only MSP430F552x)
CB6(1)
X
X
1
X
P6.7 (I/O)
I: 0; O: 1
0
A7 (only MSP430F552x)
CB7(1)
X
X
X
1
(1) Setting the CBPD.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input
buffer for that pin, regardless of the state of the associated CBPD.x bit.
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
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9.10.10 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
Figure 9-13 shows the port diagram. Table 9-55 summarizes the selection of the pin function.
Pad Logic
to ADC12
(n/a MSPF430F551x)
INCHx = x
(n/a MSPF430F551x)
to Comparator_B
from Comparator_B
CBPD.x
P7REN.x
P7DIR.x
DVSS
DVCC
0
1
1
0
1
Direction
0: Input
1: Output
P7OUT.x
0
1
From module
P7.0/CB8/(A12)
P7.1/CB9/(A13)
P7.2/CB10/(A14)
P7.3/CB11/(A15)
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7IN.x
Bus
Keeper
EN
D
To module
Figure 9-13. Port P7 (P7.0 to P7.3) Diagram
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Table 9-55. Port P7 (P7.0 to P7.3) Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (P7.x)
x
FUNCTION
P7DIR.x
P7SEL.x
CBPD
P7.0 (I/O) (1)
A12 (2)
I: 0; O: 1
0
1
X
0
1
X
0
1
X
0
1
X
0
X
1
0
X
1
0
X
1
0
X
1
P7.0/CB8/(A12)
0
X
CB8(3) (1)
P7.1 (I/O)(1)
A13 (2)
X
I: 0; O: 1
P7.1/CB9/(A13)
P7.2/CB10/(A14)
P7.3/CB11/(A15)
1
2
3
X
CB9(3) (1)
P7.2 (I/O)(1)
A14(2)
X
I: 0; O: 1
X
CB10(3) (1)
P7.3 (I/O)(1)
A15(2)
X
I: 0; O: 1
X
X
CB11(3) (1)
(1) F5529, F5527, F5525, F5521, F5519, F5517, F5515 devices only
(2) F5529, F5527, F5525, F5521 devices only
(3) Setting the CBPD.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input
buffer for that pin, regardless of the state of the associated CBPD.x bit.
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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9.10.11 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
Figure 9-14 shows the port diagram. Table 9-56 summarizes the selection of the pin function.
Pad Logic
P7REN.x
DVSS
DVCC
0
1
1
P7DIR.x
0
1
Direction
0: Input
1: Output
From module
P7OUT.x
0
1
P7DS.x
0: Low drive
1: High drive
P7.4/TB0.2
P7.5/TB0.3
P7.6/TB0.4
P7.7/TB0CLK/MCLK
P7SEL.x
P7IN.x
EN
D
To module
Figure 9-14. Port P7 (P7.4 to P7.7) Diagram
Table 9-56. Port P7 (P7.4 to P7.7) Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (P7.x)
x
FUNCTION
P7DIR.x
P7SEL.x
P7.4 (I/O)
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
P7.4/TB0.2(1)
4
TB0.CCI2A
TB0.2
0
1
P7.5 (I/O)
TB0.CCI3A
TB0.3
I: 0; O: 1
P7.5/TB0.3(1)
5
6
7
0
1
P7.6 (I/O)
TB0.CCI4A
TB0.4
I: 0; O: 1
P7.6/TB0.4(1)
0
1
P7.7 (I/O)
TB0CLK
MCLK
I: 0; O: 1
P7.7/TB0CLK/MCLK(1)
0
1
(1) F5529, F5527, F5525, F5521, F5519, F5517, F5515 devices only
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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9.10.12 Port P8 (P8.0 to P8.2) Input/Output With Schmitt Trigger
Figure 9-15 shows the port diagram. Table 9-57 summarizes the selection of the pin function.
Pad Logic
P8REN.x
DVSS
DVCC
0
1
1
P8DIR.x
0
1
Direction
0: Input
1: Output
from Port Mapping Control
P8OUT.x
0
1
from Port Mapping Control
P8.0
P8.1
P8.2
P8DS.x
0: Low drive
1: High drive
P8SEL.x
P8IN.x
EN
D
to Port Mapping Control
Figure 9-15. Port P8 (P8.0 to P8.2) Diagram
Table 9-57. Port P8 (P8.0 to P8.2) Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (P8.x)
x
FUNCTION
P8DIR.x
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
P8SEL.x
P8.0(1)
P8.1(1)
P8.2(1)
0
1
2
P8.0(I/O)
0
0
0
P8.1(I/O)
P8.2(I/O)
(1) F5529, F5527, F5525, F5521, F5519, F5517, F5515 devices only
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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9.10.13 Port PU (PU.0/DP, PU.1/DM, PUR) USB Ports
Figure 9-16 shows the port diagram. Table 9-58 through Table 9-60 summarize the pin function selection.
PUSEL
VUSB
VSSU
Pad Logic
PUOPE
0
1
USB output enable
PUOUT0
0
1
PU.0/DP
USB DP output
PUIN0
USB DP input
PUIPE
PUIN1
USB DM input
PUOUT1
0
1
PU.1/DM
USB DM output
VUSB
VSSU
Pad Logic
PUREN
PUR
“1”
PUSEL
PURIN
Figure 9-16. Port PU (PU.0/DP, PU.1/DM) Diagram
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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Table 9-58. Port PU (PU.0/DP, PU.1/DM) Output Functions
CONTROL BITS(1)
PIN NAME
PUSEL
PUOPE PUOUT1
PUOUT0
PU.1/DM
PU.0/DP
Output disabled
Output low
Output high
Output low
Output high
DP(2)
0
0
0
0
0
1
0
X
X
0
1
0
1
X
Output disabled
Output low
Output low
Output high
Output high
DM(2)
1
1
1
1
X
0
0
1
1
X
(1) PU.1/DM and PU.0/DP inputs and outputs are supplied from VUSB. VUSB can be generated by the
device using the integrated 3.3-V LDO when enabled. VUSB can also be supplied externally when
the 3.3-V LDO is not being used and is disabled.
(2) Output state set by the USB module.
Table 9-59. Port PU (PU.0/DP, PU.1/DM) Input Functions
CONTROL BITS(1)
PIN NAME
PUSEL
PUIPE
PU.1/DM
Input disabled
Input enabled
DM input
PU.0/DP
Input disabled
Input enabled
DP input
0
0
1
0
1
X
(1) PU.1/DM and PU.0/DP inputs and outputs are supplied from VUSB. VUSB can be generated by the
device using the integrated 3.3-V LDO when enabled. VUSB can also be supplied externally when
the 3.3-V LDO is not being used and is disabled.
Table 9-60. Port PUR Input Functions
CONTROL BITS
FUNCTION
PUSEL
PUREN
Input disabled
Pullup disabled
0
0
Input disabled
Pullup enabled
0
1
1
1
0
1
Input enabled
Pullup disabled
Input enabled
Pullup enabled
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
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9.10.14 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
Figure 9-17 shows the port diagram. Table 9-61 summarizes the selection of the pin function.
Pad Logic
PJREN.0
0
1
DVSS
DVCC
1
PJDIR.0
DVCC
0
1
PJOUT.0
0
1
From JTAG
PJ.0/TDO
PJDS.0
0: Low drive
1: High drive
From JTAG
PJIN.0
EN
D
Figure 9-17. Port J (PJ.0) Diagram
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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9.10.15 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or
Output
Figure 9-18 shows the port diagram. Table 9-61 summarizes the selection of the pin function.
Pad Logic
PJREN.x
0
1
DVSS
DVCC
1
PJDIR.x
DVSS
0
1
PJOUT.x
0
1
From JTAG
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
PJDS.x
0: Low drive
1: High drive
From JTAG
PJIN.x
EN
D
To JTAG
Figure 9-18. Port J (PJ.1 to PJ.3) Diagram
Table 9-61. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS
OR SIGNALS(1)
PIN NAME (PJ.x)
x
FUNCTION
PJDIR.x
I: 0; O: 1
X
PJ.0 (I/O)(2)
PJ.0/TDO
0
1
2
3
TDO(3)
PJ.1 (I/O)(2)
TDI/TCLK(3) (4)
PJ.2 (I/O)(2)
TMS(3) (4)
I: 0; O: 1
X
PJ.1/TDI/TCLK
PJ.2/TMS
I: 0; O: 1
X
PJ.3 (I/O)(2)
TCK(3) (4)
I: 0; O: 1
X
PJ.3/TCK
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
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9.11 Device Descriptors (TLV)
Table 9-62 and Table 9-63 list the complete contents of the device descriptor tag-length-value (TLV) structure for
each device type.
Table 9-62. MSP430F552x Device Descriptor Table
VALUE
SIZE
(bytes)
DESCRIPTION(1)
Info length
ADDRESS
F5529
06h
F5528
06h
F5527
06h
F5526
06h
F5525
06h
F5524
06h
F5522
06h
F5521
06h
01A00h
01A01h
01A02h
01A04h
01A05h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Eh
01A10h
01A12h
01A14h
01A15h
01A16h
01A18h
1
1
2
1
1
1
1
1
1
4
2
2
2
1
1
2
2
CRC length
CRC value
06h
06h
06h
06h
06h
06h
06h
06h
Per unit
55h
Per unit
55h
Per unit
55h
Per unit
55h
Per unit
55h
Per unit
55h
Per unit
55h
Per unit
55h
Info Block
Device ID
Device ID
29h
28h
27h
26h
25h
24h
22h
21h
Hardware revision
Firmware revision
Die record tag
Die record length
Lot/wafer ID
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
Per unit
Per unit
Per unit
Per unit
11h
Per unit
Per unit
Per unit
Per unit
11h
Per unit
Per unit
Per unit
Per unit
11h
Per unit
Per unit
Per unit
Per unit
11h
Per unit
Per unit
Per unit
Per unit
11h
Per unit
Per unit
Per unit
Per unit
11h
Per unit
Per unit
Per unit
Per unit
11h
Per unit
Per unit
Per unit
Per unit
11h
Die Record
Die X position
Die Y position
Test results
ADC12 calibration tag
ADC12 calibration length
ADC gain factor
ADC offset
10h
10h
10h
10h
10h
10h
10h
10h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 30°C
01A1Ah
01A1Ch
01A1Eh
01A20h
01A22h
01A24h
2
2
2
2
2
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 85°C
ADC12
Calibration
ADC 2.0-V reference
Temperature sensor 30°C
ADC 2.0-V reference
Temperature sensor 85°C
ADC 2.5-V reference
Temperature sensor 30°C
ADC 2.5-V reference
Temperature sensor 85°C
REF calibration tag
01A26h
01A27h
1
1
12h
06h
12h
06h
12h
06h
12h
06h
12h
06h
12h
06h
12h
06h
12h
06h
REF calibration length
REF 1.5-V reference
factor
01A28h
01A2Ah
2
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
REF Calibration
REF 2.0-V reference
factor
REF 2.5-V reference
factor
01A2Ch
01A2Eh
01A2Fh
2
1
1
Per unit
02h
Per unit
02h
Per unit
02h
Per unit
02h
Per unit
02h
Per unit
02h
Per unit
02h
Per unit
02h
Peripheral descriptor tag
Peripheral descriptor
length
63h
61h
65h
63h
63h
61h
61h
64h
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
Memory 1
Memory 2
Memory 3
Memory 4
2
2
2
2
Peripheral
Descriptor
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Eh
2Ah
0Eh
2Ah
0Eh
2Ah
0Eh
2Ah
0Eh
2Ah
0Eh
2Ah
0Eh
2Ah
0Eh
2Ah
12h
2Eh
12h
2Eh
12h
2Dh
12h
2Dh
12h
2Ch
12h
2Ch
12h
2Eh
12h
2Dh
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
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F5521
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
Table 9-62. MSP430F552x Device Descriptor Table (continued)
VALUE
SIZE
(bytes)
DESCRIPTION(1)
ADDRESS
F5529
F5528
F5527
F5526
F5525
F5524
F5522
22h
96h
22h
96h
2Ah
22h
2Ah
22h
22h
94h
22h
94h
40h
92h
2Ah
40h
Memory 5
2
95h
92h
95h
92h
Memory 6
1/2
N/A
N/A
N/A
N/A
N/A
92h
Delimiter
1
1
00h
21h
00h
20h
00h
21h
00h
20h
00h
21h
00h
20h
00h
20h
00h
21h
Peripheral count
00h
23h
00h
23h
00h
23h
00h
23h
00h
23h
00h
23h
00h
23h
00h
23h
MSP430CPUXV2
JTAG
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
00h
09h
00h
09h
00h
09h
00h
09h
00h
09h
00h
09h
00h
09h
00h
09h
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
SBW
00h
05h
00h
05h
00h
05h
00h
05h
00h
05h
00h
05h
00h
05h
00h
05h
EEM-L
TI BSL
SFR
00h
FCh
00h
FCh
00h
FCh
00h
FCh
00h
FCh
00h
FCh
00h
FCh
00h
FCh
10h
41h
10h
41h
10h
41h
10h
41h
10h
41h
10h
41h
10h
41h
10h
41h
02h
30h
02h
30h
02h
30h
02h
30h
02h
30h
02h
30h
02h
30h
02h
30h
PMM
02h
38h
02h
38h
02h
38h
02h
38h
02h
38h
02h
38h
02h
38h
02h
38h
FCTL
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
CRC16
CRC16_RB
RAMCTL
WDT_A
UCS
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
44h
00h
44h
00h
44h
00h
44h
00h
44h
00h
44h
00h
44h
00h
44h
00h
40h
00h
40h
00h
40h
00h
40h
00h
40h
00h
40h
00h
40h
00h
40h
01h
48h
01h
48h
01h
48h
01h
48h
01h
48h
01h
48h
01h
48h
01h
48h
02h
42h
02h
42h
02h
42h
02h
42h
02h
42h
02h
42h
02h
42h
02h
42h
SYS
03h
A0h
03h
A0h
03h
A0h
03h
A0h
03h
A0h
03h
A0h
03h
A0h
03h
A0h
REF
01h
10h
01h
10h
01h
10h
01h
10h
01h
10h
01h
10h
01h
10h
01h
10h
Port mapping
Port 1 and 2
Port 3 and 4
Port 5 and 6
Port 7 and 8
JTAG
04h
51h
04h
51h
04h
51h
04h
51h
04h
51h
04h
51h
04h
51h
04h
51h
02h
52h
02h
52h
02h
52h
02h
52h
02h
52h
02h
52h
02h
52h
02h
52h
02h
53h
02h
53h
02h
53h
02h
53h
02h
53h
02h
53h
02h
53h
02h
53h
02h
54h
02h
54h
02h
54h
02h
54h
N/A
N/A
N/A
N/A
0Ch
5Fh
0Eh
5Fh
0Ch
5Fh
0Eh
5Fh
0Ch
5Fh
0Eh
5Fh
0Eh
5Fh
0Ch
5Fh
02h
62h
02h
62h
02h
62h
02h
62h
02h
62h
02h
62h
02h
62h
02h
62h
TA0
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
TA1
Peripheral
Descriptor
(continued)
04h
67h
04h
67h
04h
67h
04h
67h
04h
67h
04h
67h
04h
67h
04h
67h
TB0
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
TA2
0Ah
68h
0Ah
68h
0Ah
68h
0Ah
68h
0Ah
68h
0Ah
68h
0Ah
68h
0Ah
68h
RTC
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MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
www.ti.com
Table 9-62. MSP430F552x Device Descriptor Table (continued)
VALUE
SIZE
DESCRIPTION(1)
ADDRESS
(bytes)
F5529
F5528
F5527
F5526
F5525
F5524
F5522
F5521
02h
85h
02h
85h
02h
85h
02h
85h
02h
85h
02h
85h
02h
85h
02h
85h
MPY32
2
2
2
2
2
2
2
04h
47h
04h
47h
04h
47h
04h
47h
04h
47h
04h
47h
04h
47h
04h
47h
DMA-3
USCI_A and USCI_B
USCI_A and USCI_B
ADC12_A
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
04h
90h
04h
90h
04h
90h
04h
90h
04h
90h
04h
90h
04h
90h
04h
90h
10h
D1h
10h
D1h
10h
D1h
10h
D1h
10h
D1h
10h
D1h
10h
D1h
10h
D1h
1Ch
A8h
1Ch
A8h
1Ch
A8h
1Ch
A8h
1Ch
A8h
1Ch
A8h
1Ch
A8h
1Ch
A8h
COMP_B
04h
98h
04h
98h
04h
98h
04h
98h
04h
98h
04h
98h
04h
98h
04h
98h
USB
COMP_B
TB0.CCIFG0
TB0.CCIFG1..6
WDTIFG
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A8h
64h
65h
40h
90h
91h
D0h
60h
61h
98h
46h
62h
63h
50h
92h
93h
66h
67h
51h
68h
00h
A8h
64h
65h
40h
90h
91h
D0h
60h
61h
98h
46h
62h
63h
50h
92h
93h
66h
67h
51h
68h
00h
A8h
64h
65h
40h
90h
91h
D0h
60h
61h
98h
46h
62h
63h
50h
92h
93h
66h
67h
51h
68h
00h
A8h
64h
65h
40h
90h
91h
D0h
60h
61h
98h
46h
62h
63h
50h
92h
93h
66h
67h
51h
68h
00h
A8h
64h
65h
40h
90h
91h
D0h
60h
61h
98h
46h
62h
63h
50h
92h
93h
66h
67h
51h
68h
00h
A8h
64h
65h
40h
90h
91h
D0h
60h
61h
98h
46h
62h
63h
50h
92h
93h
66h
67h
51h
68h
00h
A8h
64h
65h
40h
90h
91h
D0h
60h
61h
98h
46h
62h
63h
50h
92h
93h
66h
67h
51h
68h
00h
A8h
64h
65h
40h
90h
91h
D0h
60h
61h
98h
46h
62h
63h
50h
92h
93h
66h
67h
51h
68h
00h
USCI_A0
USCI_B0
ADC12_A
TA0.CCIFG0
TA0.CCIFG1..4
USB
Interrupts
DMA
TA1.CCIFG0
TA1.CCIFG1..2
P1
USCI_A1
USCI_B1
TA1.CCIFG0
TA1.CCIFG1..2
P2
RTC_A
Delimiter
(1) N/A = Not applicable, blank = unused and reads FFh.
Copyright © 2020 Texas Instruments Incorporated
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
www.ti.com
Table 9-63. MSP430F551x Device Descriptor Table
VALUE
SIZE
(bytes)
DESCRIPTION(1)
ADDRESS
F5519
55h
F5517
55h
F5515
55h
F5514
55h
F5513
55h
Info length
01A00h
01A01h
01A02h
01A04h
01A05h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Eh
01A10h
01A12h
01A14h
01A15h
01A16h
01A18h
1
1
2
1
1
1
1
1
1
4
2
2
2
1
1
2
2
CRC length
CRC value
19h
17h
15h
14h
13h
Per unit
22h
Per unit
21h
Per unit
55h
Per unit
55h
Per unit
20h
Info Block
Device ID
Device ID
80h
80h
15h
14h
80h
Hardware revision
Firmware revision
Die record tag
Die record length
Lot/wafer ID
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
0Ah
0Ah
0Ah
0Ah
0Ah
Per unit
Per unit
Per unit
Per unit
05h
Per unit
Per unit
Per unit
Per unit
05h
Per unit
Per unit
Per unit
Per unit
11h
Per unit
Per unit
Per unit
Per unit
11h
Per unit
Per unit
Per unit
Per unit
05h
Die Record
Die X position
Die Y position
Test results
ADC12 calibration tag
ADC12 calibration length
ADC gain factor
ADC offset
10h
10h
10h
10h
10h
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
ADC 1.5-V reference
Temperature sensor 30°C
01A1Ah
01A1Ch
01A1Eh
01A20h
01A22h
01A24h
2
2
2
2
2
2
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
ADC 1.5-V reference
Temperature sensor 85°C
ADC12 Calibration
ADC 2.0-V reference
Temperature sensor 30°C
ADC 2.0-V reference
Temperature sensor 85°C
ADC 2.5-V reference
Temperature sensor 30°C
ADC 2.5-V reference
Temperature sensor 85°C
REF calibration tag
REF calibration length
01A26h
01A27h
01A28h
01A2Ah
01A2Ch
01A2Eh
01A2Fh
1
1
2
2
2
1
1
12h
06h
12h
06h
12h
06h
12h
06h
12h
06h
REF Calibration
REF 1.5-V reference factor
REF 2.0-V reference factor
REF 2.5-V reference factor
Peripheral descriptor tag
Peripheral descriptor length
Per unit
Per unit
Per unit
02h
Per unit
Per unit
Per unit
02h
Per unit
Per unit
Per unit
02h
Per unit
Per unit
Per unit
02h
Per unit
Per unit
Per unit
02h
61h
63h
61h
5Fh
5Fh
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
Memory 1
Memory 2
Memory 3
Memory 4
Memory 5
Memory 6
2
2
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Eh
2Ah
0Eh
2Ah
0Eh
2Ah
0Eh
2Ah
0Eh
2Ah
2
12h
2Eh
12h
2Dh
12h
2Ch
12h
2Ch
12h
2Ch
2
Peripheral Descriptor
22h
96h
2Ah
22h
22h
94h
22h
94h
40h
92h
2
95h
92h
1/2
N/A
N/A
N/A
N/A
Delimiter
1
1
00h
20h
00h
20h
00h
20h
00h
1Fh
00h
1Fh
Peripheral count
00h
23h
00h
23h
00h
23h
00h
23h
00h
23h
MSP430CPUXV2
JTAG
2
2
00h
09h
00h
09h
00h
09h
00h
09h
00h
09h
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
www.ti.com
Table 9-63. MSP430F551x Device Descriptor Table (continued)
VALUE
SIZE
(bytes)
DESCRIPTION(1)
ADDRESS
F5519
F5517
F5515
F5514
F5513
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
SBW
EEM-L
2
00h
05h
00h
05h
00h
05h
00h
05h
00h
05h
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
00h
FCh
00h
FCh
00h
FCh
00h
FCh
00h
FCh
TI BSL
10h
41h
10h
41h
10h
41h
10h
41h
10h
41h
SFR
02h
30h
02h
30h
02h
30h
02h
30h
02h
30h
PMM
02h
38h
02h
38h
02h
38h
02h
38h
02h
38h
FCTL
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
CRC16
CRC16_RB
RAMCTL
WDT_A
UCS
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
44h
00h
44h
00h
44h
00h
44h
00h
44h
00h
40h
00h
40h
00h
40h
00h
40h
00h
40h
01h
48h
01h
48h
01h
48h
01h
48h
01h
48h
02h
42h
02h
42h
02h
42h
02h
42h
02h
42h
SYS
03h
A0h
03h
A0h
03h
A0h
03h
A0h
03h
A0h
REF
01h
10h
01h
10h
01h
10h
01h
10h
01h
10h
Port mapping
Port 1 and 2
Port 3 and 4
Port 5 and 6
Port 7 and 8
JTAG
04h
51h
04h
51h
04h
51h
04h
51h
04h
51h
02h
52h
02h
52h
02h
52h
02h
52h
02h
52h
02h
53h
02h
53h
02h
53h
02h
53h
02h
53h
02h
54h
02h
54h
02h
54h
N/A
N/A
0Ch
5Fh
0Ch
5Fh
0Ch
5Fh
0Eh
5Fh
0Eh
5Fh
02h
62h
02h
62h
02h
62h
02h
62h
02h
62h
TA0
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
TA1
04h
67h
04h
67h
04h
67h
04h
67h
04h
67h
TB0
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
TA2
Peripheral Descriptor
(continued)
0Ah
68h
0Ah
68h
0Ah
68h
0Ah
68h
0Ah
68h
RTC
02h
85h
02h
85h
02h
85h
02h
85h
02h
85h
MPY32
DMA-3
04h
47h
04h
47h
04h
47h
04h
47h
04h
47h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
USCI_A and USCI_B
04h
90h
04h
90h
04h
90h
04h
90h
04h
90h
USCI_A and USCI_B
ADC12_A
2
2
N/A
N/A
N/A
N/A
N/A
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
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F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
Table 9-63. MSP430F551x Device Descriptor Table (continued)
VALUE
SIZE
(bytes)
DESCRIPTION(1)
ADDRESS
F5519
F5517
F5515
F5514
2Ch
A8h
2Ch
A8h
2Ch
A8h
2Ch
A8h
2Ch
A8h
COMP_B
2
04h
98h
04h
98h
04h
98h
04h
98h
04h
98h
USB
2
COMP_B
TB0.CCIFG0
TB0.CCIFG1..6
WDTIFG
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A8h
64h
65h
40h
90h
91h
01h
60h
61h
98h
46h
62h
63h
50h
92h
93h
66h
67h
51h
68h
00h
A8h
64h
65h
40h
90h
91h
01h
60h
61h
98h
46h
62h
63h
50h
92h
93h
66h
67h
51h
68h
00h
A8h
64h
65h
40h
90h
91h
01h
60h
61h
98h
46h
62h
63h
50h
92h
93h
66h
67h
51h
68h
00h
A8h
64h
65h
40h
90h
91h
01h
60h
61h
98h
46h
62h
63h
50h
92h
93h
66h
67h
51h
68h
00h
A8h
64h
65h
40h
90h
91h
01h
60h
61h
98h
46h
62h
63h
50h
92h
93h
66h
67h
51h
68h
00h
USCI_A0
USCI_B0
ADC12_A
TA0.CCIFG0
TA0.CCIFG1..4
USB
Interrupts
DMA
TA1.CCIFG0
TA1.CCIFG1..2
P1
USCI_A1
USCI_B1
TA1.CCIFG0
TA1.CCIFG1..2
P2
RTC_A
Delimiter
(1) N/A = not applicable, blank = unused and reads FFh.
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
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10 Device and Documentation Support
10.1 Getting Started and Next Steps
For an introduction to the MSP family of devices and the tools and libraries that are available to help with your
development, visit the MSP430™ ultra-low-power sensing & measurement MCUs overview.
10.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP
MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These
prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully
qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated
fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.
TI recommends that these devices not be used in any production system because their expected end-use failure
rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature
range, package type, and distribution format. Figure 10-1 provides a legend for reading the complete device
name.
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
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MSP 430 F 5 438 A I PM T -EP
Processor Family
MCU Platform
Device Type
Series
Feature Set
Optional: Additional Features
Optional: Tape and Reel
Packaging
Optional: Temperature Range
Optional: Revision
Processor Family
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
MCU Platform
Device Type
430 = MSP430 low-power microcontroller platform
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash
L = No nonvolatile memory
Specialized Application
AFE = Analog front end
BQ = Contactless power
CG = ROM medical
FE = Flash energy meter
FG = Flash medical
FW = Flash electronic flow meter
Series
1 = Up to 8 MHz
2 = Up to 16 MHz
3 = Legacy
4 = Up to 16 MHz with LCD driver
5 = Up to 25 MHz
6 = Up to 25 MHz with LCD driver
0 = Low-voltage series
Feature Set
Various levels of integration within a series
Updated version of the base part number
Optional: Revision
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small reel
R = Large reel
No markings = Tube or tray
Optional: Additional Features -EP = Enhanced product (–40°C to 105°C)
-HT = Extreme temperature parts (–55°C to 150°C)
-Q1 = Automotive Q100 qualified
Figure 10-1. Device Nomenclature
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
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10.3 Tools and Software
All MSP microcontrollers are supported by a wide variety of software and hardware development tools. Tools are
available from TI and various third parties. See them all at MSP430 ultra-low-power mcus – tools & software.
Table 10-1 lists the debug features of these MCUs. See the Code Composer Studio IDE for MSP430 MCUs
user's guide for details on the available features.
Table 10-1. Hardware Debug Features
BREAK-
POINTS
(N)
RANGE
BREAK-
POINTS
LPMx.5
DEBUGGING
SUPPORT
MSP430
ARCHITECTURE
CLOCK
CONTROL
STATE
SEQUENCER
TRACE
BUFFER
4-WIRE JTAG 2-WIRE JTAG
Yes Yes
MSP430Xv2
8
Yes
Yes
Yes
Yes
No
Design Kits and Evaluation Modules
MSP430F5529 USB LaunchPad Development Kit
Develop low-power PC-connected applications with integrated full-speed USB 2.0 (HID, MSC, CDC). The MSP-
EXP430F5529LP LaunchPad kit is an inexpensive, simple microcontroller development kit for the
MSP430F5529 USB microcontroller. It’s an easy way to start developing on the MSP430 MCU, with an on-board
emulation for programming and debugging, as well as buttons and LEDs for simple user interface.
MSP430F5529 USB Experimenter’s Board
The MSP430F5529 Experimenter Board (MSP-EXP430F5529) is a development platform for the MSP430F5529
device, from the latest generation of MSP430 devices with integrated USB. The board is compatible with many
TI low-power RF wireless evaluation modules such as the CC2520EMK. The Experimenter Board helps
designers quickly learn and develop using the new F55xx MCUs, which provide the industry's lowest active
power consumption, integrated USB, and more memory and leading integration for applications such as energy
harvesting, wireless sensing and automatic metering infrastructure (AMI).
64-pin target development board and MSP-FET programmer bundle for MSP430F5x MCUs
The MSP-FET430U64USB is a powerful flash emulation tool that allows you to quickly begin application
development on the MSP430 MCU. It includes USB debugging interface used to program and debug the
MSP430 in-system through the JTAG interface or the pin saving Spy Bi-Wire (2-wire JTAG) protocol. The flash
memory can be erased and programmed in seconds with only a few keystrokes, and because the MSP430 flash
is ultra-low power, no external power supply is required.
80-pin target development board and MSP-FET programmer bundle for MSP430F5x MCUs
The MSP-FET is a powerful flash emulation tool to quickly begin application development on the MSP430 MCU.
It includes USB debugging interface used to program and debug the MSP430 in-system through the JTAG
interface or the pin-saving Spy-Bi-Wire (2-wire JTAG) protocol. The flash memory can be erased and
programmed in seconds with only a few keystrokes, and because the MSP430 flash is ultra-low power, no
external power supply is required. The debugging tool interfaces the MSP430 to the included integrated software
environment and includes code to start your design immediately.
Software
MSP430Ware™ Software
MSP430Ware software is a collection of code examples, data sheets, and other design resources for all
MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 design resources, MSP430Ware software also includes a high-level API called MSP Driver Library. This
library makes it easy to program MSP430 hardware. MSP430Ware software is available as a component of
Code Composer Studio™ IDE or as a stand-alone package.
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
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MSP430F552x Code Examples
C code examples are available for every MSP device that configures each of the integrated peripherals for
various application needs.
MSP Driver Library
Driver Library's abstracted API keeps you above the bits and bytes of the MSP430 hardware by providing easy-
to-use function calls. Thorough documentation is delivered through a helpful API Guide, which includes details
on each function call and the recognized parameters. Developers can use Driver Library functions to write
complete projects with minimal overhead.
MSP EnergyTrace™ Technology
EnergyTrace technology for MSP430 microcontrollers is an energy-based code analysis tool that measures and
displays the application’s energy profile and helps to optimize it for ultra-low-power consumption.
ULP (Ultra-Low Power) Advisor
ULP Advisor™ software is a tool for guiding developers to write more efficient code to fully utilize the unique
ultra-low power features of MSP and MSP432 microcontrollers. Aimed at both experienced and new
microcontroller developers, ULP Advisor checks your code against a thorough ULP checklist to squeeze every
last nano amp out of your application. At build time, ULP Advisor will provide notifications and remarks to
highlight areas of your code that can be further optimized for lower power.
IEC60730 Software Package
The IEC60730 MSP430 software package was developed to be useful in assisting customers in complying with
IEC 60730-1:2010 (Automatic Electrical Controls for Household and Similar Use – Part 1: General
Requirements) for up to Class B products, which includes home appliances, arc detectors, power converters,
power tools, e-bikes, and many others. The IEC60730 MSP430 software package can be embedded in customer
applications running on MSP430s to help simplify the customer’s certification efforts of functional safety-
compliant consumer devices to IEC 60730-1:2010 Class B.
Fixed Point Math Library for MSP
The MSP IQmath and Qmath Libraries are a collection of highly optimized and high-precision mathematical
functions for C programmers to seamlessly port a floating-point algorithm into fixed-point code on MSP430 and
MSP432 devices. These routines are typically used in computationally intensive real-time applications where
optimal execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and Qmath
libraries, it is possible to achieve execution speeds considerably faster and energy consumption considerably
lower than equivalent code written using floating-point math.
Floating Point Math Library for MSP430
Continuing to innovate in the low power and low cost microcontroller space, TI brings you MSPMATHLIB.
Leveraging the intelligent peripherals of our devices, this floating point math library of scalar functions brings you
up to 26x better performance. Mathlib is easy to integrate into your designs. This library is free and is integrated
in both Code Composer Studio and IAR IDEs. Read the user’s guide for an in depth look at the math library and
relevant benchmarks.
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
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Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code Composer Studio integrated development environment (IDE) supports all MSP microcontroller devices.
Code Composer Studio IDE comprises a suite of embedded software utilities used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features.
Code Composer Studio IDE combines the advantages of the Eclipse software framework with advanced
embedded debug capabilities from TI resulting in a compelling feature-rich development environment for
embedded developers. When using CCS with an MSP430 MCU, a unique and powerful set of plugins and
embedded software utilities are made available to fully leverage the MSP430 microcontroller.
Command-Line Programmer
MSP Flasher is an open-source shell-based interface for programming MSP microcontrollers through a FET
programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can download binary
files (.txt or .hex) files directly to the MSP microcontroller without an IDE.
MSP MCU Programmer and Debugger
The MSP-FET is a powerful emulation development tool – often called a debug probe – that allows users to
quickly begin application development on MSP low-power microcontrollers (MCU). Creating MCU software
usually requires downloading the resulting binary program to the MSP device for validation and debugging. The
MSP-FET provides a debug communication pathway between a host computer and the target MSP.
Furthermore, the MSP-FET also provides a Backchannel UART connection between the computer's USB
interface and the MSP UART. This affords the MSP programmer a convenient method for communicating serially
between the MSP and a terminal running on the computer. It also supports loading programs (often called
firmware) to the MSP target using the BSL (bootloader) through the UART and I2C communication protocols.
MSP-GANG Production Programmer
The MSP Gang Programmer is a device programmer that can program up to eight identical MSP430 or MSP432
flash or FRAM devices at the same time. The MSP Gang Programmer connects to a host PC using a standard
RS-232 or USB connection and provides flexible programming options that allow the user to fully customize the
process. The MSP Gang Programmer is provided with an expansion board, called the Gang Splitter, that
implements the interconnections between the MSP Gang Programmer and multiple target devices. Eight cables
are provided that connect the expansion board to eight target devices (through JTAG or Spy-Bi-Wire
connectors). The programming can be done with a PC or as a stand-alone device. A PC-side graphical user
interface is also available and is DLL-based.
10.4 Documentation Support
The following documents describe the MSP430F552x and MSP430F551x devices. Copies of these documents
are available on the Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for your
device on ti.com (for links to the product folders, see Section 10.5). In the upper right corner, click the "Alert me"
button. This registers you to receive a weekly digest of product information that has changed (if any). For change
details, check the revision history of any revised document.
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
www.ti.com
Errata
MSP430F5529 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430F5528 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430F5527 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430F5526 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430F5525 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430F5524 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430F5522 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430F5521 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430F5519 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430F5517 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430F5515 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430F5514 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430F5513 Device Erratasheet
Describes the known exceptions to the functional specifications.
User's Guides
MSP430x5xx and MSP430x6xx Family User's Guide
Detailed information on the modules and peripherals available in this device family.
MSP430 Flash Device Bootloader (BSL) User's Guide
The MSP430 bootloader (BSL) lets users communicate with embedded memory in the MSP430 microcontroller
during the prototyping phase, final production, and in service. Both the programmable memory (flash memory)
and the data memory (RAM) can be modified as required. Do not confuse the bootloader with the bootstrap
loader programs found in some digital signal processors (DSPs) that automatically load program code (and data)
from external memory to the internal memory of the DSP.
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
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MSP430 Programming With the JTAG Interface
This document describes the functions that are required to erase, program, and verify the memory module of the
MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition,
it describes how to program the JTAG access security fuse that is available on all MSP430 devices. This
document describes device access using both the standard 4-wire JTAG interface and the 2-wire JTAG
interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide
This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the
program development tool for the MSP430 ultra-low-power microcontroller. Both available interface types, the
parallel port interface and the USB interface, are described.
Application Reports
MSP430 32-kHz Crystal Oscillators
Selection of the right crystal, correct load circuit, and proper board layout are important for a stable crystal
oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the
correct crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout
are given. The document also contains detailed information on the possible oscillator tests to ensure stable
oscillator operation in mass production.
MSP430 System-Level ESD Considerations
System-level ESD has become increasingly demanding with silicon technology scaling towards lower voltages
and the need for designing cost-effective and ultra-low-power components. This application report addresses
different ESD topics to help board designers and OEMs understand and design robust system-level designs. A
few real-world system-level ESD protection design examples and their results are also discussed.
10.5 Related Links
Table 10-2 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 10-2. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
MSP430F5529
MSP430F5528
MSP430F5527
MSP430F5526
MSP430F5525
MSP430F5524
MSP430F5522
MSP430F5521
MSP430F5519
MSP430F5517
MSP430F5515
MSP430F5514
MSP430F5513
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MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
www.ti.com
10.6 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.7 Trademarks
LaunchPad™, MSP430Ware™, MSP430™, Code Composer Studio™, TI E2E™, MicroStar Junior™,
EnergyTrace™, ULP Advisor™, are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
10.8 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.9 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as
defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.
10.10 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2020 Texas Instruments Incorporated
120 Submit Document Feedback
Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525
MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,
MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,
MSP430F5513
SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020
www.ti.com
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback 121
Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525
MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514
MSP430F5513
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2000
250
(1)
(2)
(3)
(4/5)
(6)
ASP00886IRGCR
ASP00886IRGCT
ACTIVE
VQFN
VQFN
VQFN
RGC
64
64
64
80
Green (RoHS
& no Sb/Br)
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
M430F5522
ACTIVE
ACTIVE
ACTIVE
RGC
Green (RoHS
& no Sb/Br)
NIPDAU
M430F5522
M430F5513
M430F5513
MSP430F5513IRGCR
MSP430F5513IZQER
RGC
2000
2500
Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR
& no Sb/Br)
BGA
ZQE
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MICROSTAR
JUNIOR
MSP430F5514IRGCR
MSP430F5514IRGCT
MSP430F5514IZQE
ACTIVE
ACTIVE
ACTIVE
VQFN
RGC
RGC
ZQE
64
64
80
2000
250
Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
M430F5514
M430F5514
M430F5514
VQFN
Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR
& no Sb/Br)
BGA
MICROSTAR
JUNIOR
490
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F5514IZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
M430F5514
MSP430F5515IPN
MSP430F5515IPNR
MSP430F5517IPN
MSP430F5517IPNR
MSP430F5519IPN
MSP430F5519IPNR
MSP430F5521IPN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
PN
PN
PN
PN
PN
PN
PN
80
80
80
80
80
80
80
119
1000
119
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
M430F5515
M430F5515
M430F5517
M430F5517
M430F5519
M430F5519
M430F5521
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
1000
119
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
1000
119
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
1000
2000
250
(1)
(2)
(3)
(4/5)
(6)
MSP430F5521IPNR
MSP430F5522IRGCR
MSP430F5522IRGCT
MSP430F5522IZQE
ACTIVE
LQFP
VQFN
VQFN
PN
80
64
64
80
Green (RoHS
& no Sb/Br)
NIPDAU
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
M430F5521
ACTIVE
ACTIVE
ACTIVE
RGC
RGC
ZQE
Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR
& no Sb/Br)
M430F5522
M430F5522
M430F5522
Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR
& no Sb/Br)
BGA
490
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MICROSTAR
JUNIOR
MSP430F5522IZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
M430F5522
MSP430F5522IZXH
MSP430F5522IZXHR
MSP430F5524IRGCR
MSP430F5524IRGCT
MSP430F5524IZQE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NFBGA
NFBGA
VQFN
ZXH
ZXH
RGC
RGC
ZQE
80
80
64
64
80
490
2500
2000
250
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
F5522
Green (RoHS
& no Sb/Br)
F5522
Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR
& no Sb/Br)
M430F5524
M430F5524
M430F5524
VQFN
Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR
& no Sb/Br)
BGA
MICROSTAR
JUNIOR
490
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F5524IZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
M430F5524
MSP430F5524IZXH
MSP430F5524IZXHR
MSP430F5525IPN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NFBGA
NFBGA
LQFP
ZXH
ZXH
PN
80
80
80
80
64
490
2500
119
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
F5524
Green (RoHS
& no Sb/Br)
F5524
Green (RoHS
& no Sb/Br)
M430F5525
M430F5525
M430F5526
MSP430F5525IPNR
MSP430F5526IRGCR
LQFP
PN
1000
2000
Green (RoHS
& no Sb/Br)
VQFN
RGC
Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR
& no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
250
490
(1)
(2)
(3)
(4/5)
(6)
MSP430F5526IRGCT
MSP430F5526IZQE
ACTIVE
VQFN
RGC
64
80
Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR
& no Sb/Br)
-40 to 85
-40 to 85
M430F5526
ACTIVE
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
M430F5526
M430F5526
MSP430F5526IZQER
BGA
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
MICROSTAR
JUNIOR
MSP430F5526IZXH
MSP430F5526IZXHR
MSP430F5527IPN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NFBGA
NFBGA
LQFP
ZXH
ZXH
PN
80
80
80
80
64
64
64
80
490
2500
119
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
F5526
Green (RoHS
& no Sb/Br)
F5526
Green (RoHS
& no Sb/Br)
M430F5527
M430F5527
M430F5528
M430F5528
M430F5528
M430F5528
MSP430F5527IPNR
MSP430F5528IRGCR
MSP430F5528IRGCT
MSP430F5528IYFFR
MSP430F5528IZQE
LQFP
PN
1000
2000
250
Green (RoHS
& no Sb/Br)
VQFN
VQFN
DSBGA
RGC
RGC
YFF
ZQE
Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR
& no Sb/Br)
Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR
& no Sb/Br)
2500
490
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
BGA
MICROSTAR
JUNIOR
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F5528IZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
M430F5528
MSP430F5528IZXH
MSP430F5528IZXHR
MSP430F5529IPN
MSP430F5529IPNR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NFBGA
NFBGA
LQFP
ZXH
ZXH
PN
80
80
80
80
490
2500
119
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
F5528
Green (RoHS
& no Sb/Br)
F5528
Green (RoHS
& no Sb/Br)
M430F5529
M430F5529
LQFP
PN
1000
Green (RoHS
& no Sb/Br)
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2020
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Sep-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430F5513IRGCR
MSP430F5513IZQER
VQFN
RGC
ZQE
64
80
2000
2500
330.0
330.0
16.4
12.4
9.3
5.3
9.3
5.3
1.5
1.5
12.0
8.0
16.0
12.0
Q2
Q1
BGA MI
CROSTA
R JUNI
OR
MSP430F5514IRGCT
MSP430F5514IZQER
VQFN
RGC
ZQE
64
80
250
180.0
330.0
16.4
12.4
9.3
5.3
9.3
5.3
1.5
1.5
12.0
8.0
16.0
12.0
Q2
Q1
BGA MI
CROSTA
R JUNI
OR
2500
MSP430F5515IPNR
MSP430F5517IPNR
MSP430F5519IPNR
MSP430F5521IPNR
MSP430F5522IRGCT
MSP430F5522IZQER
LQFP
LQFP
LQFP
LQFP
VQFN
PN
PN
80
80
80
80
64
80
1000
1000
1000
1000
250
330.0
330.0
330.0
330.0
180.0
330.0
24.4
24.4
24.4
24.4
16.4
12.4
15.0
15.0
15.0
15.0
9.3
15.0
15.0
15.0
15.0
9.3
2.1
2.1
2.1
2.1
1.5
1.5
20.0
20.0
20.0
20.0
12.0
8.0
24.0
24.0
24.0
24.0
16.0
12.0
Q2
Q2
Q2
Q2
Q2
Q1
PN
PN
RGC
ZQE
BGA MI
CROSTA
R JUNI
OR
2500
5.3
5.3
MSP430F5522IZXHR
MSP430F5524IRGCT
NFBGA
VQFN
ZXH
80
64
2500
250
330.0
180.0
12.4
16.4
5.3
9.3
5.3
9.3
1.5
1.5
8.0
12.0
16.0
Q1
Q2
RGC
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Sep-2020
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430F5524IZQER
BGA MI
CROSTA
R JUNI
OR
ZQE
80
2500
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q1
MSP430F5524IZXHR
MSP430F5525IPNR
MSP430F5526IRGCR
MSP430F5526IRGCT
MSP430F5526IZQER
NFBGA
LQFP
ZXH
PN
80
80
64
64
80
2500
1000
2000
250
330.0
330.0
330.0
180.0
330.0
12.4
24.4
16.4
16.4
12.4
5.3
15.0
9.3
5.3
15.0
9.3
1.5
2.1
1.5
1.5
1.5
8.0
20.0
12.0
12.0
8.0
12.0
24.0
16.0
16.0
12.0
Q1
Q2
Q2
Q2
Q1
VQFN
VQFN
RGC
RGC
ZQE
9.3
9.3
BGA MI
CROSTA
R JUNI
OR
2500
5.3
5.3
MSP430F5527IPNR
MSP430F5528IRGCT
MSP430F5528IZQER
LQFP
VQFN
PN
80
64
80
1000
250
330.0
180.0
330.0
24.4
16.4
12.4
15.0
9.3
15.0
9.3
2.1
1.5
1.5
20.0
12.0
8.0
24.0
16.0
12.0
Q2
Q2
Q1
RGC
ZQE
BGA MI
CROSTA
R JUNI
OR
2500
5.3
5.3
MSP430F5529IPNR
LQFP
PN
80
1000
330.0
24.4
15.0
15.0
2.1
20.0
24.0
Q2
*All dimensions are nominal
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Sep-2020
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430F5513IRGCR
MSP430F5513IZQER
VQFN
RGC
ZQE
64
80
2000
2500
367.0
350.0
367.0
350.0
38.0
43.0
BGA MICROSTAR
JUNIOR
MSP430F5514IRGCT
MSP430F5514IZQER
VQFN
RGC
ZQE
64
80
250
210.0
350.0
185.0
350.0
35.0
43.0
BGA MICROSTAR
JUNIOR
2500
MSP430F5515IPNR
MSP430F5517IPNR
MSP430F5519IPNR
MSP430F5521IPNR
MSP430F5522IRGCT
MSP430F5522IZQER
LQFP
LQFP
LQFP
LQFP
VQFN
PN
PN
80
80
80
80
64
80
1000
1000
1000
1000
250
350.0
350.0
350.0
350.0
210.0
350.0
350.0
350.0
350.0
350.0
185.0
350.0
43.0
43.0
43.0
43.0
35.0
43.0
PN
PN
RGC
ZQE
BGA MICROSTAR
JUNIOR
2500
MSP430F5522IZXHR
MSP430F5524IRGCT
MSP430F5524IZQER
NFBGA
VQFN
ZXH
RGC
ZQE
80
64
80
2500
250
350.0
210.0
350.0
350.0
185.0
350.0
43.0
35.0
43.0
BGA MICROSTAR
JUNIOR
2500
MSP430F5524IZXHR
MSP430F5525IPNR
MSP430F5526IRGCR
MSP430F5526IRGCT
MSP430F5526IZQER
NFBGA
LQFP
ZXH
PN
80
80
64
64
80
2500
1000
2000
250
350.0
350.0
367.0
210.0
350.0
350.0
350.0
367.0
185.0
350.0
43.0
43.0
38.0
35.0
43.0
VQFN
VQFN
RGC
RGC
ZQE
BGA MICROSTAR
JUNIOR
2500
MSP430F5527IPNR
MSP430F5528IRGCT
MSP430F5528IZQER
LQFP
VQFN
PN
80
64
80
1000
250
350.0
210.0
350.0
350.0
185.0
350.0
43.0
35.0
43.0
RGC
ZQE
BGA MICROSTAR
JUNIOR
2500
MSP430F5529IPNR
LQFP
PN
80
1000
350.0
350.0
43.0
Pack Materials-Page 3
GENERIC PACKAGE VIEW
RGC 64
9 x 9, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224597/A
www.ti.com
PACKAGE OUTLINE
RGC0064B
VQFN - 1 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
9.15
8.85
A
B
PIN 1 INDEX AREA
9.15
8.85
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2X 7.5
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
17
32
16
33
65
SYMM
2X 7.5
4.25 0.1
60X
0.5
1
48
0.30
0.18
64X
49
64
PIN 1 ID
0.1
C A B
0.5
0.3
64X
0.05
4219010/A 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGC0064B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.25)
SEE SOLDER MASK
DETAIL
SYMM
64X (0.6)
49
64
64X (0.24)
1
48
60X (0.5)
(R0.05) TYP
(1.18) TYP
(8.8)
65
SYMM
(0.695) TYP
(
0.2) TYP
VIA
33
16
32
17
(0.695) TYP
(1.18) TYP
(8.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219010/A 10/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGC0064B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
64X (0.6)
64
49
64X (0.24)
1
48
60X (0.5)
(R0.05) TYP
9X ( 1.19)
65
SYMM
(8.8)
(1.39)
33
16
17
32
(1.39)
(8.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 65
71% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219010/A 10/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
ZXH0080A
NFBGA - 1 mm max height
S
C
A
L
E
3
.
0
0
0
BALL GRID ARRAY
5.1
4.9
A
B
BALL A1 CORNER
INDEX AREA
5.1
4.9
0.7
0.6
C
1 MAX
SEATING PLANE
0.08 C
BALL TYP
0.25
TYP
0.15
4 TYP
SYMM
J
H
G
F
SYMM
80X
4
E
D
C
B
A
TYP
0.35
0.25
0.15
0.05
C B
C
A
0.5 TYP
1
2
3
4
5
6
7
8
9
0.5 TYP
4221325/A 01/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis is for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This is a Pb-free solder ball design.
www.ti.com
EXAMPLE BOARD LAYOUT
ZXH0080A
NFBGA - 1 mm max height
BALL GRID ARRAY
(0.5) TYP
0.265
0.235
80X
6
7
9
2
3
4
5
8
1
A
B
C
(0.5) TYP
D
E
F
G
H
J
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MAX
0.05 MIN
METAL
UNDER
MASK
(
0.25)
METAL
(
0.25)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4221325/A 01/2014
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SBVA017 (www.ti.com/lit/sbva017).
www.ti.com
EXAMPLE STENCIL DESIGN
ZXH0080A
NFBGA - 1 mm max height
BALL GRID ARRAY
(0.5) TYP
80X ( 0.25)
(R0.05) TYP
5
4
3
6
7
9
2
8
1
A
(0.5)
TYP
B
C
METAL
TYP
D
E
F
G
H
J
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:20X
4221325/A 01/2014
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
60
M
0,08
41
61
40
0,13 NOM
80
21
1
20
Gage Plane
9,50 TYP
0,25
12,20
SQ
11,80
0,05 MIN
0°–7°
14,20
SQ
13,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D: Max = 3.79 mm, Min = 3.73 mm
E: Max = 3.79 mm, Min = 3.73 mm
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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