MSP430F5635IZCAT_技术文档

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

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SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

MSP430F563x Mixed-Signal Microcontrollers

– USCI_A0 and USCI_A1 each support:

1 Features

•

Enhanced UART supports automatic baud-

rate detection

•

Low supply voltage range: 1.8 V to 3.6 V

Ultra-low power consumption

– Active mode (AM):

•

IrDA encoder and decoder

Synchronous SPI

All system clocks active:

270 µA/MHz at 8 MHz, 3.0 V, flash program

execution (typical)

– USCI_B0 and USCI_B1 each support:

•

I²C

Synchronous SPI

– Standby mode (LPM3):

•

Full-speed universal serial bus (USB)

– Integrated USB-PHY

– Integrated 3.3-V and 1.8-V USB power system

– Integrated USB-PLL

– Eight input and eight output endpoints

12-bit analog-to-digital converter (ADC) with

internal shared reference, sample-and-hold, and

autoscan feature

Dual 12-bit digital-to-analog converters (DACs)

with synchronization

Watchdog with crystal and supply supervisor

operational, full RAM retention, fast wakeup:

1.8 µA at 2.2 V, 2.1 µA at 3.0 V (typical)

– Shutdown real-time clock (RTC) mode

(LPM3.5):

Shutdown mode, active RTC with crystal:

1.1 µA at 3.0 V (typical)

– Shutdown mode (LPM4.5):

0.3 µA at 3.0 V (typical)

•

Wake up from standby mode in 3 µs (typical)

16-bit RISC architecture, extended memory, up to

20-MHz system clock

•

Voltage comparator

Hardware multiplier supports 32-bit operations

Serial onboard programming, no external

programming voltage needed

•

Flexible power-management system

– Fully integrated LDO with programmable

regulated core supply voltage

– Supply voltage supervision, monitoring, and

brownout

•

6-channel internal DMA

RTC module with supply voltage backup switch

Table 6-1 summarizes the available family

members

•

Unified clock system

– FLL control loop for frequency stabilization

– Low-power low-frequency internal clock source

(VLO)

– Low-frequency trimmed internal reference

source (REFO)

2 Applications

•

Analog and digital sensor systems

Digital motor control

Remote controls

Thermostats

Digital timers

– 32-kHz crystals (XT1)

– High-frequency crystals up to 32 MHz (XT2)

Four 16-bit timers with 3, 5, or 7 capture/compare

registers

Hand-held meters

•

Two universal serial communication interfaces

(USCIs)

3 Description

The TI MSP430^™family of ultra-low-power microcontrollers consists of several devices featuring different sets of

peripherals targeted for various applications. The architecture, combined with five low-power modes, is

optimized to achieve extended battery life in portable measurement applications. The device features a powerful

16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The

digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active mode in 3 µs

(typical).

The MSP430F563x devices are microcontrollers with a high-performance 12-bit ADC, a comparator, two USCIs,

USB 2.0, a hardware multiplier, DMA, four 16-bit timers, an RTC module with alarm capabilities, and up to 74 I/O

pins.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

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For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide.

Device Information

PART NUMBER⁽¹⁾

MSP430F5638IPZ

PACKAGE

BODY SIZE⁽²⁾

14 mm × 14 mm

7 mm × 7 mm

LQFP (100)

MSP430F5638IZCA

nFBGA (113)

MSP430F5638IZQW⁽³⁾

MicroStar Junior^™BGA (113)

(1) For the most current device, package, and ordering information, see the Package Option

Addendum in Section 11, or see the TI website at www.ti.com.

(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the

Mechanical Data in Section 11.

(3) All orderable part numbers in the ZQW (MicroStar Junior BGA) package have been changed to a

status of Last Time Buy. Visit the Product life cycle page for details on this status.

2

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

4 Functional Block Diagrams

Figure 4-1 shows the functional block diagram for the MSP430F5638, MSP430F5637, and MSP430F5636

devices.

PA

PB

PC

PD

XIN XOUT

DV_CCDV_SS

AV_CCAV_SS

RST/NMI

P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x

P9.x

XT2IN

I/O Ports

P1, P2

2×8 I/Os

Interrupt

Capability

I/O Ports

P3, P4

2×8 I/Os

Interrupt

Capability

I/O Ports

P5, P6

2×8 I/Os

16KB

RAM

I/O Ports

P7, P8

1×6 I/Os

1×8 I/Os

ACLK

SYS

Power

Management

I/O Ports

P9

1×8 I/Os

Unified

Clock

System

USCI0,

USCI1

USB

256KB

192KB

128KB

XT2OUT

Watchdog

Full-speed

SMCLK

+2KB RAM

USB Buffer

Ax: UART,

IrDA, SPI

P2 Port

Mapping

Controller

LDO,

SVM, SVS,

Brownout

Flash

PE

1×8 I/Os

MCLK

PA

1×16 I/Os

PB

1×16 I/Os

PC

1×16 I/Os

Bx: SPI, I²C

+8B Backup

RAM

PD

1×14 I/Os

CPUXV2

and

Working

Registers

EEM

(L: 8+2)

ADC12_A

DMA

TA1 and

TA2

RTC_B

DAC12_A

REF

TA0

TB0

12 bit

6 Channel

200 ksps

JTAG,

SBW

Interface

12 bit

2 channels

voltage out

Comp_B

Reference

1.5 V, 2.0 V,

2.5 V

MPY32

CRC16

2 Timer_A

each with

3 CC

Timer_A

5 CC

Registers

Timer_B

7 CC

Registers

Battery

Backup

System

16 channels

(12 ext, 4 int)

Autoscan

Registers

Port PJ

Figure 4-1. Functional Block Diagram – MSP430F5638, MSP430F5637, MSP430F5636

Figure 4-2 shows the functional block diagram for the MSP430F5635, MSP430F5634, and MSP430F5633

devices.

PA

PB

PC

PD

XIN XOUT

DV_CCDV_SS

AV_CCAV_SS

RST/NMI

P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x

P9.x

XT2IN

I/O Ports

P1, P2

2×8 I/Os

Interrupt

Capability

I/O Ports

P3, P4

2×8 I/Os

Interrupt

Capability

I/O Ports

P5, P6

2×8 I/Os

16KB

RAM

I/O Ports

P7, P8

1×6 I/Os

1×8 I/Os

ACLK

Power

Management

SYS

I/O Ports

P9

1×8 I/Os

Unified

Clock

System

USCI0,

USCI1

USB

256KB

192KB

128KB

XT2OUT

Watchdog

Full-speed

SMCLK

+2KB RAM

USB Buffer

Ax: UART,

IrDA, SPI

LDO,

SVM, SVS,

Brownout

P2 Port

Mapping

Controller

Flash

PE

1×8 I/Os

MCLK

PA

1×16 I/Os

PB

1×16 I/Os

PC

1×16 I/Os

Bx: SPI, I²C

+8B Backup

RAM

PD

1×14 I/Os

CPUXV2

and

Working

Registers

EEM

(L: 8+2)

ADC12_A

DMA

TA1 and

TA2

RTC_B

REF

TA0

TB0

12 bit

6 Channel

200 ksps

JTAG,

SBW

Interface

Comp_B

Reference

1.5 V, 2.0 V,

2.5 V

MPY32

CRC16

2 Timer_A

each with

3 CC

Timer_A

5 CC

Registers

Timer_B

7 CC

Registers

Battery

Backup

System

16 channels

(12 ext, 4 int)

Autoscan

Registers

Port PJ

Figure 4-2. Functional Block Diagram – MSP430F5635, MSP430F5634, MSP430F5633

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

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Figure 4-3 shows the functional block diagram for the MSP430F5632, MSP430F5631, and MSP430F5630

devices.

PA

PB

PC

PD

XIN XOUT

DV_CCDV_SS

AV_CCAV_SS

RST/NMI

P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x

P9.x

XT2IN

I/O Ports

P1, P2

2×8 I/Os

Interrupt

Capability

I/O Ports

P3, P4

2×8 I/Os

Interrupt

Capability

I/O Ports

P5, P6

2×8 I/Os

16KB

RAM

I/O Ports

P7, P8

1×6 I/Os

1×8 I/Os

ACLK

Power

Management

SYS

I/O Ports

P9

1×8 I/Os

Unified

Clock

System

USCI0,

USCI1

USB

256KB

192KB

128KB

XT2OUT

Watchdog

Full-speed

SMCLK

+2KB RAM

USB Buffer

Ax: UART,

IrDA, SPI

LDO,

SVM, SVS,

Brownout

P2 Port

Mapping

Controller

Flash

PE

1×8 I/Os

MCLK

PA

1×16 I/Os

PB

1×16 I/Os

PC

1×16 I/Os

Bx: SPI, I²C

+8B Backup

RAM

PD

1×14 I/Os

CPUXV2

and

Working

Registers

EEM

(L: 8+2)

DMA

TA1 and

TA2

RTC_B

TA0

TB0

REF

6 Channel

JTAG,

SBW

Interface

Timer_A

5 CC

Registers

2 Timer_A

each with

3 CC

Timer_B

7 CC

Registers

Comp_B

Reference

1.5 V, 2.0 V,

2.5 V

MPY32

CRC16

Battery

Backup

System

Registers

Port PJ

Figure 4-3. Functional Block Diagram – MSP430F5632, MSP430F5631, MSP430F5630

4

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MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

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SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Functional Block Diagrams............................................ 3

5 Revision History.............................................................. 6

6 Device Comparison.........................................................8

6.1 Related Products........................................................ 8

7 Terminal Configuration and Functions..........................9

7.1 Pin Diagrams.............................................................. 9

7.2 Signal Descriptions................................................... 13

8 Specifications................................................................ 19

8.1 Absolute Maximum Ratings...................................... 19

8.2 ESD Ratings............................................................. 19

8.3 Recommended Operating Conditions.......................19

8.4 Active Mode Supply Current Into V_CCExcluding

8.35 12-Bit ADC, Timing Parameters..............................41

8.36 12-Bit ADC, Linearity Parameters Using an

External Reference Voltage.........................................42

8.37 12-Bit ADC, Linearity Parameters Using AVCC

as Reference Voltage..................................................42

8.38 12-Bit ADC, Linearity Parameters Using the

Internal Reference Voltage..........................................42

8.39 12-Bit ADC, Temperature Sensor and Built-In

V_MID............................................................................43

8.40 REF, External Reference........................................ 44

8.41 REF, Built-In Reference.......................................... 45

8.42 12-Bit DAC, Supply Specifications..........................46

8.43 12-Bit DAC, Linearity Specifications....................... 47

8.44 12-Bit DAC, Output Specifications..........................48

8.45 12-Bit DAC, Reference Input Specifications........... 49

8.46 12-Bit DAC, Dynamic Specifications.......................49

8.47 12-Bit DAC, Dynamic Specifications (Continued)...50

8.48 Comparator_B.........................................................51

8.49 Ports PU.0 and PU.1...............................................52

8.50 USB Output Ports DP and DM................................52

8.51 USB Input Ports DP and DM...................................52

8.52 USB-PWR (USB Power System)............................53

8.53 USB-PLL (USB Phase-Locked Loop)..................... 53

8.54 Flash Memory......................................................... 54

8.55 JTAG and Spy-Bi-Wire Interface.............................54

9 Detailed Description......................................................55

9.1 Overview...................................................................55

9.2 CPU.......................................................................... 55

9.3 Instruction Set...........................................................56

9.4 Operating Modes...................................................... 57

9.5 Interrupt Vector Addresses....................................... 58

9.6 Memory.....................................................................59

9.7 Bootloader (BSL)...................................................... 60

9.8 JTAG Operation........................................................ 60

9.9 Flash Memory .......................................................... 61

9.10 RAM .......................................................................62

9.11 Backup RAM........................................................... 62

9.12 Peripherals..............................................................62

9.13 Input/Output Diagrams............................................84

9.14 Device Descriptors................................................105

10 Device and Documentation Support........................106

10.1 Getting Started and Next Steps............................ 106

10.2 Device Nomenclature............................................106

10.3 Tools and Software............................................... 108

10.4 Documentation Support........................................ 110

10.5 Related Links........................................................ 112

10.6 Support Resources............................................... 112

10.7 Trademarks........................................................... 112

10.8 Electrostatic Discharge Caution............................112

10.9 Export Control Notice............................................112

10.10 Glossary..............................................................112

11 Mechanical, Packaging, and Orderable

External Current.......................................................... 21

8.5 Low-Power Mode Supply Currents (Into V_CC

)

Excluding External Current..........................................21

8.6 Thermal Resistance Characteristics......................... 22

8.7 Schmitt-Trigger Inputs – General-Purpose I/O..........23

8.8 Inputs – Ports P1, P2, P3, and P4............................ 23

8.9 Leakage Current – General-Purpose I/O..................23

8.10 Outputs – General-Purpose I/O (Full Drive

Strength)......................................................................23

8.11 Outputs – General-Purpose I/O (Reduced Drive

Strength)......................................................................24

8.12 Output Frequency – Ports P1, P2, and P3..............24

8.13 Typical Characteristics – Outputs, Reduced

Drive Strength (PxDS.y = 0)........................................25

8.14 Typical Characteristics – Outputs, Full Drive

Strength (PxDS.y = 1)................................................. 26

8.15 Crystal Oscillator, XT1, Low-Frequency Mode........27

8.16 Crystal Oscillator, XT2............................................ 28

8.17 Internal Very-Low-Power Low-Frequency

Oscillator (VLO)...........................................................29

8.18 Internal Reference, Low-Frequency Oscillator

(REFO)........................................................................29

8.19 DCO Frequency......................................................30

8.20 PMM, Brownout Reset (BOR).................................31

8.21 PMM, Core Voltage.................................................31

8.22 PMM, SVS High Side..............................................32

8.23 PMM, SVM High Side............................................. 32

8.24 PMM, SVS Low Side...............................................33

8.25 PMM, SVM Low Side..............................................33

8.26 Wake-up Times From Low-Power Modes and

Reset...........................................................................33

8.27 Timer_A, Timers TA0, TA1, and TA2.......................34

8.28 Timer_B, Timer TB0................................................34

8.29 Battery Backup........................................................35

8.30 USCI (UART Mode)................................................ 36

8.31 USCI (SPI Master Mode)........................................ 36

8.32 USCI (SPI Slave Mode).......................................... 38

8.33 USCI (I²C Mode).....................................................40

8.34 12-Bit ADC, Power Supply and Input Range

Information.................................................................. 113

Conditions................................................................... 41

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

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5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from revision F to revision G

Changes from September 18, 2018 to September 10, 2020

Page

•

Updated the numbering for sections, tables, figures, and cross-references throughout the document..............1

Added nFBGA package (ZCA) information throughout document......................................................................1

Removed package options that are no longer available in Table 6-1, Device Comparison (MSP430F5637 and

MSP430F5631 in ZQW) .................................................................................................................................... 8

Updated the list of devices available in the 113-Pin ZQW package in the caption of Figure 7-4 .......................9

Changed the MAX value of the I_ERASEand I_MERASE, I_BANKparameters in Section 8.54, Flash Memory ......... 54

Corrected the connection of the P7SEL.x signal in Figure 9-11, Port P7 (P7.4 to P7.7) Diagram .................. 98

•

Changes from revision E to revision F

Changes from December 9, 2015 to September 17, 2018

Page

•

Added Section 6.1, Related Products ................................................................................................................8

Added typical conditions statements at the beginning of Section 8, Specifications .........................................19

Changed the MIN value of the V_{(DVCC_BOR_hys)}parameter from 60 mV to 50 mV in Section 8.20, PMM,

Brownout Reset (BOR) ....................................................................................................................................31

Updated notes (1) and (2) and added note (3) in Section 8.26, Wake-up Times From Low-Power Modes and

Reset ............................................................................................................................................................... 33

Removed ADC12DIV from the formula for the TYP value in the second row of the t_CONVERTparameter in

Section 8.35, 12-Bit ADC, Timing Parameters, because ADC12CLK is after division..................................... 41

Removed the note that started "This impedance depends on..." from the "Reference input resistance"

parameter in Section 8.45, 12-Bit DAC, Reference Input Specifications .........................................................49

Added second row for t_{EN_CMP}with Test Conditions of "CBPWRMD = 10" and MAX value of 100 µs in Section

8.48, Comparator_B ........................................................................................................................................ 51

Renamed FCTL4.MGR0 and MGR1 in the f_MCLK,MGRparameter in Section 8.54, Flash Memory to be

consistent with header files ..............................................................................................................................54

Replaced former section Development Tools Support with Section 10.3, Tools and Software ..................... 108

•

Changes from revision D to revision E

Changes from August 6, 2013 to December 8, 2015

Page

•

Document format and organization changes throughout, including addition of section numbering....................1

Moved all functional block diagrams to Section 4, Functional Block Diagrams .................................................3

Added USB column to Table 6-1, Family Members ...........................................................................................8

Added Section 6, Device Comparison, and moved Table 6-1 to it......................................................................8

Added "Port U is supplied by the LDOO rail" to the PU.0 and PU.1 descriptions in Section 7.2, Signal

Descriptions .....................................................................................................................................................13

Added Section 8.2, ESD Ratings .....................................................................................................................19

Added note to C_VCORE..................................................................................................................................... 19

Added note to R_Pull.......................................................................................................................................... 23

Changed TYP value of C_L,effwith Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF.......................27

In V_BAT3parameter description, changed from "V_BAT3≠ V_BAT/3" to "V_BAT3= V_BAT/3"....................................... 35

Changed from f_{DAC12_0OUT}to f_{DAC12_1OUT}in the first row of the Test Conditions for the "Channel-to-channel

crosstalk" parameter.........................................................................................................................................50

Changed the value of DAC12_xDAT from 7F7h to F7Fh and changed the x-axis label from f_Toggleto 1/f_Togglein

Figure 8-22, Crosstalk Test Conditions ............................................................................................................50

•

6

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MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

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SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

•

Added note to R_PUR......................................................................................................................................... 53

Corrected the spelling of the MRG bits in the f_MCLK,MRGparameter in Section 8.54, Flash Memory .............. 54

Removed RTC_B from LPM4.5 wake-up options.............................................................................................57

Throughout document, changed all instances of "bootstrap loader" to "bootloader" .......................................60

Added the paragraph that starts "Using the MSP430 RTC_B Module With Battery Backup Supply describes

how..." .............................................................................................................................................................. 64

Corrected names of interrupt events PMMSWBOR (BOR) and PMMSWPOR (POR) in Table 9-11, System

Module Interrupt Vector Registers ................................................................................................................... 65

Corrected spelling of NMIIFG (added missing "I") in Table 9-11, System Module Interrupt Vector Registers ....

65

•

Corrected register acronyms (added "USB" prefix as required) in Table 9-50, USB Control Registers .......... 72

Added P7SEL.2 and XT2BYPASS inputs with AND and OR gates in Figure 9-10, Port P7 (P7.3) Diagram .. 97

Changed P7SEL.3 column from X to 0 for "P7.3 (I/O)" rows............................................................................97

Added Section 10 and moved Development Tools Support, Device and Development Tool Nomenclature,

Trademarks, and Electrostatic Discharge Caution sections to it.....................................................................106

Added Section 11, Mechanical, Packaging, and Orderable Information ........................................................113

•

The following table lists the changes to this data sheet from the original release through revision D.

REVISION

COMMENTS

Signal Descriptions, Added note regarding pullup resistor to RST/NMI/SBWTDIO pin.

Added Applications, Development Tools Support, and Device and Development Tool Nomenclature

Section 9.12.1, Changed the description of the number of I/Os in each port.

Table 9-19, Added PM5CTL0 register.

SLAS650D

August 2013

Section 8.42, Fixed typo in I_DDTest Conditions (changed from DAC12IOG to DAC12OG).

Section 8.51, Corrected V_ILand V_IHlimits.

Section 8.54, Changed I_ERASEand I_MERASE, I_BANKlimits.

Changed description of ACLK and PUR in Signal Descriptions.

Changed typos to Interrupt Flag names on Timer TA2 rows in Table 9-3.

Changed SYSRSTIV, System Reset offset 1Ch to Reserved in Table 9-11.

Corrected names of SVMLVLRIFG and SVMHVLRIFG bits in Table 9-11.

Corrected right-most column in Table 9-4.

SLAS650C

August 2012

Added note regarding evaluation of PUR in Section 9.7.1.

Changed notes on Section 8.41.

Changed t_{SENSOR(sample)}MIN to 100 µs in Section 8.39.

Changed note (2) in Section 8.39.

Editorial changes throughout.

SLAS650B

August 2011

Production Data release

SLAS650A

July 2010

Updated Product Preview including electrical specifications

Product Preview release

SLAS650

May 2010

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

www.ti.com

6 Device Comparison

Table 6-1 summarizes the available family members.

Table 6-1. Device Comparison

USCI_A:

UART,

IrDA, SPI

FLASH SRAM

(KB)

USCI_B:

SPI, I²C

ADC12_A DAC12_A Comp_B

DEVICE^{(1) (2)}

Timer_A⁽³⁾Timer_B⁽⁴⁾

USB

I/O

PACKAGE

(KB)⁽⁵⁾

(Ch)

100 PZ,

113 ZCA,

113 ZQW

MSP430F5638

MSP430F5637

MSP430F5636

256

192

128

16 + 2

5, 3, 3

7

2

12 ext, 4 int

2

12

Yes

74

100 PZ

100 PZ,

113 ZCA,

113 ZQW

100 PZ,

113 ZCA,

113 ZQW

MSP430F5635

MSP430F5634

MSP430F5633

256

192

128

16 + 2

5, 3, 3

7

2

12 ext, 4 int

–

12

Yes

74

100 PZ,

113 ZCA,

113 ZQW

100 PZ,

113 ZCA,

113 ZQW

100 PZ,

113 ZCA,

113 ZQW

MSP430F5632

MSP430F5631

MSP430F5630

256

192

128

16 + 2

5, 3, 3

7

2

–

12

Yes

74

100 PZ

100 PZ,

113 ZCA,

113 ZQW

(1) For the most current package and ordering information, see the Package Option Addendum in Section 11, or see the TI website at

www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/

packaging.

(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and

PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first

instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.

(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and

PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first

instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.

(5) The additional 2KB of USB SRAM that is listed can be used as general-purpose SRAM when USB is not in use.

6.1 Related Products

For information about other devices in this family of products or related products, see the following links.

TI 16-bit and 32-bit microcontrollers

High-performance, low-power solutions to enable the autonomous future

Products for MSP430 ultra-low-power sensing & measurement MCUs

One platform. One ecosystem. Endless possibilities.

Companion products for MSP430F5638

Review products that are frequently purchased or used in conjunction with this product.

Reference designs

Find reference designs leveraging the best in TI technology to solve your system-level challenges

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Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634

MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

7 Terminal Configuration and Functions

7.1 Pin Diagrams

Figure 7-1 shows the pinout for the MSP430F5638, MSP430F5637, and MSP430F5636 devices in the 100-pin

PZ package.

P6.4/CB4/A4

P6.5/CB5/A5

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

P9.7

2

P9.6

P6.6/CB6/A6/DAC0

P6.7/CB7/A7/DAC1

P7.4/CB8/A12

P7.5/CB9/A13

P7.6/CB10/A14/DAC0

P7.7/CB11/A15/DAC1

P5.0/VREF+/VeREF+

P5.1/VREF−/VeREF−

AVCC1

3

P9.5

4

P9.4

5

P9.3

6

P9.2

7

P9.1

8

P9.0

9

P8.7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

P8.6/UCB1SOMI/UCB1SCL

P8.5/UCB1SIMO/UCB1SDA

DVCC2

AVSS1

MSP430F5638

MSP430F5637

MSP430F5636

XIN

DVSS2

XOUT

P8.4/UCB1CLK/UCA1STE

P8.3/UCA1RXD/UCA1SOMI

P8.2/UCA1TXD/UCA1SIMO

P8.1/UCB1STE/UCA1CLK

P8.0/TB0CLK

P4.7/TB0OUTH/SVMOUT

P4.6/TB0.6

AVSS2

P5.6/ADC12CLK/DMAE0

P2.0/P2MAP0

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

P2.6/P2MAP6

P2.7/P2MAP7

DVCC1

P4.5/TB0.5

P4.4/TB0.4

P4.3/TB0.3

P4.2/TB0.2

P4.1/TB0.1

NOTE: DNC = Do not connect

Figure 7-1. 100-Pin PZ Package (Top View) – MSP430F5638, MSP430F5637, MSP430F5636

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

www.ti.com

Figure 7-2 shows the pinout for the MSP430F5635, MSP430F5634, and MSP430F5633 devices in the 100-pin

PZ package.

P6.4/CB4/A4

P6.5/CB5/A5

P6.6/CB6/A6

P6.7/CB7/A7

P7.4/CB8/A12

P7.5/CB9/A13

P7.6/CB10/A14

P7.7/CB11/A15

P5.0/VREF+/VeREF+

P5.1/VREF−/VeREF−

AVCC1

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

P9.7

2

P9.6

3

P9.5

4

P9.4

5

P9.3

6

P9.2

7

P9.1

8

P9.0

9

P8.7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

P8.6/UCB1SOMI/UCB1SCL

P8.5/UCB1SIMO/UCB1SDA

DVCC2

AVSS1

MSP430F5635

MSP430F5634

MSP430F5633

XIN

DVSS2

XOUT

P8.4/UCB1CLK/UCA1STE

P8.3/UCA1RXD/UCA1SOMI

P8.2/UCA1TXD/UCA1SIMO

P8.1/UCB1STE/UCA1CLK

P8.0/TB0CLK

P4.7/TB0OUTH/SVMOUT

P4.6/TB0.6

AVSS2

P5.6/ADC12CLK/DMAE0

P2.0/P2MAP0

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

P2.6/P2MAP6

P2.7/P2MAP7

DVCC1

P4.5/TB0.5

P4.4/TB0.4

P4.3/TB0.3

P4.2/TB0.2

P4.1/TB0.1

NOTE: DNC = Do not connect

Figure 7-2. 100-Pin PZ Package (Top View) – MSP430F5635, MSP430F5634, MSP430F5633

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

Figure 7-3 shows the pinout for the MSP430F5632, MSP430F5631, and MSP430F5630 devices in the 100-pin

PZ package.

P6.4/CB4

P6.5/CB5

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

P9.7

2

P9.6

P6.6/CB6

3

P9.5

P6.7/CB7

4

P9.4

P7.4/CB8

5

P9.3

P7.5/CB9

6

P9.2

P7.6/CB10

P7.7/CB11

P5.0/VREF+/VeREF+

P5.1/VREF−/VeREF−

AVCC1

7

P9.1

8

P9.0

9

P8.7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

P8.6/UCB1SOMI/UCB1SCL

P8.5/UCB1SIMO/UCB1SDA

DVCC2

AVSS1

MSP430F5632

MSP430F5631

MSP430F5630

XIN

DVSS2

XOUT

P8.4/UCB1CLK/UCA1STE

P8.3/UCA1RXD/UCA1SOMI

P8.2/UCA1TXD/UCA1SIMO

P8.1/UCB1STE/UCA1CLK

P8.0/TB0CLK

P4.7/TB0OUTH/SVMOUT

P4.6/TB0.6

AVSS2

P5.6/DMAE0

P2.0/P2MAP0

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

P2.6/P2MAP6

P2.7/P2MAP7

DVCC1

P4.5/TB0.5

P4.4/TB0.4

P4.3/TB0.3

P4.2/TB0.2

P4.1/TB0.1

NOTE: DNC = Do not connect

Figure 7-3. 100-Pin PZ Package (Top View) – MSP430F5632, MSP430F5631, MSP430F5630

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

www.ti.com

Figure 7-4 shows the pinout for all devices in the 113-pin ZCA or ZQW package. See Table 7-1 for pin

assignments and descriptions.

A1

B1

C1

D1

E1

F1

G1

H1

J1

A2

B2

C2

D2

E2

F2

G2

H2

J2

A3

B3

C3

A4

B4

A5

B5

A6

B6

A7

B7

A8

B8

A9

B9

A10

B10

A11

B11

C11

D11

E11

F11

G11

H11

J11

A12

B12

C12

D12

E12

F12

G12

H12

J12

D4

E4

F4

G4

H4

J4

D5

E5

F5

G5

H5

J5

D6

E6

D7

E7

D8

E8

F8

G8

H8

J8

D9

E9

F9

G9

H9

J9

H6

J6

H7

J7

K1

L1

K2

L2

K11

L11

M11

K12

L12

M12

L3

L4

L5

L6

L7

L8

L9

L10

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

NOTE: For terminal assignments, see Table 7-1.

Figure 7-4. 113-Pin ZCA or ZQW Package (Top View) – MSP430F5638, MSP430F5636, MSP430F5635,

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5630

12

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

7.2 Signal Descriptions

Table 7-1 describes the signals for all device variants and packages.

Table 7-1. Signal Descriptions

TERMINAL

NO.⁽⁴⁾

I/O⁽¹⁾

DESCRIPTION

NAME

ZCA,

PZ

ZQW

General-purpose digital I/O

Comparator_B input CB4

P6.4/CB4/A4

P6.5/CB5/A5

1

A1

B2

I/O

Analog input A4 – ADC (not available on F5632, F5631, and F5630 devices)

General-purpose digital I/O

Comparator_B input CB5

2

3

Analog input A5 – ADC (not available on F5632, F5631, and F5630 devices)

General-purpose digital I/O

Comparator_B input CB6

P6.6/CB6/A6/DAC0

P6.7/CB7/A7/DAC1

B1

C2

I/O

Analog input A6 – ADC (not available on F5632, F5631, and F5630 devices)

DAC12.0 output (not available on F5635, F5634, F5633, F5632, F5631, and F5630

devices)

General-purpose digital I/O

Comparator_B input CB7

4

Analog input A7 – ADC (not available on F5632, F5631, and F5630 devices)

DAC12.1 output (not available on F5635, F5634, F5633, F5632, F5631, and F5630

devices)

General-purpose digital I/O

Comparator_B input CB8

P7.4/CB8/A12

P7.5/CB9/A13

5

6

C1

C3

I/O

Analog input A12 –ADC (not available on F5632, F5631, and F5630 devices)

General-purpose digital I/O

Comparator_B input CB9

Analog input A13 – ADC (not available on F5632, F5631, and F5630 devices)

General-purpose digital I/O

Comparator_B input CB10

P7.6/CB10/A14/DAC0

P7.7/CB11/A15/DAC1

7

8

D2

D1

I/O

Analog input A14 – ADC (not available on F5632, F5631, and F5630 devices)

DAC12.0 output (not available on F5635, F5634, F5633, F5632, F5631, and F5630

devices)

General-purpose digital I/O

Comparator_B input CB11

Analog input A15 – ADC (not available on F5632, F5631, and F5630 devices)

DAC12.1 output (not available on F5635, F5634, F5633, F5632, F5631, and F5630

devices)

General-purpose digital I/O

Output of reference voltage to the ADC

Input for an external reference voltage to the ADC

P5.0/VREF+/VeREF+

P5.1/VREF-/VeREF-

9

D4

E4

I/O

General-purpose digital I/O

10

Negative terminal for the reference voltage of the ADC for both sources, the

internal reference voltage, or an external applied reference voltage

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

www.ti.com

Table 7-1. Signal Descriptions (continued)

TERMINAL

NO.⁽⁴⁾

I/O⁽¹⁾

DESCRIPTION

NAME

ZCA,

ZQW

PZ

E1,

E2

AVCC1

11

Analog power supply

AVSS1

XIN

12

13

14

15

F2

F1

G1

G2

Analog ground supply

I

Input terminal for crystal oscillator XT1

Output terminal of crystal oscillator XT1

Analog ground supply

XOUT

AVSS2

O

General-purpose digital I/O

Conversion clock output ADC (not available on F5632, F5631, and F5630 devices)

DMA external trigger input

P5.6/ADC12CLK/DMAE0

16

H1

I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output

P2.0/P2MAP0

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

P2.6/P2MAP6

P2.7/P2MAP7

17

18

19

20

21

22

23

24

G4

H2

J1

I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I²C data

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I²C clock

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable

H4

J2

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in

K1

K2

L2

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: no secondary function

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: no secondary function

DVCC1

DVSS1

VCORE⁽²⁾

P5.2

25

26

27

28

29

30

31

32

33

L1

M1

M2

L3

Digital power supply

Digital ground supply

Regulated core power supply (internal use only, no external current loading)

I/O General-purpose digital I/O

DVSS

DNC

M3

J4

Digital ground supply

Do not connect. It is strongly recommended to leave this terminal open.

I/O General-purpose digital I/O

P5.3

L4

P5.4

M4

J5

I/O General-purpose digital I/O

P5.5

I/O General-purpose digital I/O

General-purpose digital I/O with port interrupt

Timer TA0 clock signal TACLK input

P1.0/TA0CLK/ACLK

P1.1/TA0.0

34

35

L5

I/O

ACLK output (divided by 1, 2, 4, 8, 16, or 32)

General-purpose digital I/O with port interrupt

Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output

BSL transmit output

M5

14

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

Table 7-1. Signal Descriptions (continued)

TERMINAL

NO.⁽⁴⁾

I/O⁽¹⁾

DESCRIPTION

NAME

ZCA,

ZQW

PZ

General-purpose digital I/O with port interrupt

Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output

BSL receive input

P1.2/TA0.1

36

J6

I/O

General-purpose digital I/O with port interrupt

P1.3/TA0.2

P1.4/TA0.3

P1.5/TA0.4

P1.6/TA0.1

P1.7/TA0.2

37

38

39

40

41

H6

M6

L6

I/O

Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output

General-purpose digital I/O with port interrupt

Timer TA0 CCR3 capture: CCI3A input compare: Out3 output

General-purpose digital I/O with port interrupt

Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output

General-purpose digital I/O with port interrupt

J7

Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output

General-purpose digital I/O with port interrupt

M7

Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output

General-purpose digital I/O with port interrupt

Timer TA1 clock input

P3.0/TA1CLK/CBOUT

42

L7

I/O

Comparator_B output

General-purpose digital I/O with port interrupt

P3.1/TA1.0

P3.2/TA1.1

P3.3/TA1.2

43

44

45

H7

M8

L8

I/O

Timer TA1 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

General-purpose digital I/O with port interrupt

Timer TA1 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

General-purpose digital I/O with port interrupt

Timer TA1 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

General-purpose digital I/O with port interrupt

Timer TA2 clock input

P3.4/TA2CLK/SMCLK

46

J8

I/O

SMCLK output

General-purpose digital I/O with port interrupt

P3.5/TA2.0

P3.6/TA2.1

P3.7/TA2.2

P4.0/TB0.0

P4.1/TB0.1

P4.2/TB0.2

47

48

49

50

51

52

M9

L9

I/O

Timer TA2 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

General-purpose digital I/O with port interrupt

Timer TA2 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

General-purpose digital I/O with port interrupt

M10 I/O

Timer TA2 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

General-purpose digital I/O with port interrupt

J9

I/O

Timer TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

General-purpose digital I/O with port interrupt

M11

L10

Timer TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

General-purpose digital I/O with port interrupt

Timer TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

www.ti.com

Table 7-1. Signal Descriptions (continued)

TERMINAL

NO.⁽⁴⁾

I/O⁽¹⁾

DESCRIPTION

NAME

ZCA,

ZQW

PZ

General-purpose digital I/O with port interrupt

P4.3/TB0.3

P4.4/TB0.4

P4.5/TB0.5

P4.6/TB0.6

53

M12 I/O

Timer TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output

General-purpose digital I/O with port interrupt

54

55

56

L12

L11

K11

I/O

Timer TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output

General-purpose digital I/O with port interrupt

Timer TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output

General-purpose digital I/O with port interrupt

Timer TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output

General-purpose digital I/O with port interrupt

Timer TB0: Switch all PWM outputs high impedance

SVM output

P4.7/TB0OUTH/SVMOUT

57

K12

I/O

General-purpose digital I/O

Timer TB0 clock input

P8.0/TB0CLK

58

59

60

J11

J12

H11

I/O

General-purpose digital I/O

P8.1/UCB1STE/UCA1CLK

P8.2/UCA1TXD/UCA1SIMO

USCI_B1 SPI slave transmit enable; USCI_A1 clock input/output

General-purpose digital I/O

USCI_A1 UART transmit data; USCI_A1 SPI slave in/master out

General-purpose digital I/O

P8.3/UCA1RXD/UCA1SOMI

P8.4/UCB1CLK/UCA1STE

61

62

H12

G11

I/O

USCI_A1 UART receive data; USCI_A1 SPI slave out/master in

General-purpose digital I/O

USCI_B1 clock input/output; USCI_A1 SPI slave transmit enable

DVSS2

DVCC2

63

64

G12

F12

Digital ground supply

Digital power supply

General-purpose digital I/O

P8.5/UCB1SIMO/UCB1SDA

P8.6/UCB1SOMI/UCB1SCL

65

66

F11

G9

I/O

USCI_B1 SPI slave in/master out; USCI_B1 I²C data

General-purpose digital I/O

USCI_B1 SPI slave out/master in; USCI_B1 I²C clock

P8.7

P9.0

P9.1

P9.2

67

68

69

70

E12

E11

F9

I/O General-purpose digital I/O

D12

P9.3

71

D11

I/O General-purpose digital I/O

P9.4

P9.5

P9.6

P9.7

72

73

74

75

E9

C12

C11

D9

I/O General-purpose digital I/O

B11,

B12

VSSU

76

USB PHY ground supply

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Table 7-1. Signal Descriptions (continued)

TERMINAL

NO.⁽⁴⁾

I/O⁽¹⁾

DESCRIPTION

NAME

ZCA,

ZQW

PZ

General-purpose digital I/O, controlled by USB control register. Port U is supplied

by the LDOO rail.

PU.0/DP

PUR

77

A12

I/O

USB data terminal DP

USB pullup resistor pin (open drain). The voltage level at the PUR pin is used to

I/O invoke the default USB BSL. TI recommends a 1-MΩ resistor to ground. See

Section 9.7.1 for more information.

78

79

B10

A11

General-purpose digital I/O, controlled by USB control register. Port U is supplied

by the LDOO rail.

PU.1/DM

I/O

USB data terminal DM

VBUS

VUSB

V18

80

81

82

83

A10

A9

USB LDO input (connect to USB power source)

USB LDO output

B9

USB regulated power (internal use only, no external current loading)

Analog ground supply

AVSS3

A8

General-purpose digital I/O

P7.2/XT2IN

84

85

B8

B7

I/O

Input terminal for crystal oscillator XT2

General-purpose digital I/O

P7.3/XT2OUT

I/O

Output terminal of crystal oscillator XT2

Capacitor for backup subsystem. Do not load this pin externally. For capacitor

values, see C_BAKin Section 8.3.

VBAK

VBAT

86

87

A7

D8

Backup or secondary supply voltage. If backup voltage is not supplied, connect to

DVCC externally.

General-purpose digital I/O

P5.7/RTCCLK

88

D7

I/O

RTCCLK output

DVCC3

DVSS3

89

90

A6

A5

Digital power supply

Digital ground supply

Test mode pin; selects digital I/O on JTAG pins

TEST/SBWTCK

PJ.0/TDO

91

92

93

94

95

B6

B5

A4

E7

D6

I

Spy-Bi-Wire input clock

General-purpose digital I/O

I/O

Test data output port

General-purpose digital I/O

PJ.1/TDI/TCLK

PJ.2/TMS

I/O

Test data input or test clock input

General-purpose digital I/O

I/O

Test mode select

General-purpose digital I/O

PJ.3/TCK

I/O

Test clock

Reset input (active low)⁽³⁾

Nonmaskable interrupt input

Spy-Bi-Wire data input/output

RST/NMI/SBWTDIO

P6.0/CB0/A0

96

97

A3

B4

I/O

General-purpose digital I/O

Comparator_B input CB0

Analog input A0 – ADC (not available on F5632, F5631, and F5630 devices)

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Table 7-1. Signal Descriptions (continued)

TERMINAL

NO.⁽⁴⁾

I/O⁽¹⁾

DESCRIPTION

NAME

ZCA,

ZQW

PZ

General-purpose digital I/O

Comparator_B input CB1

P6.1/CB1/A1

P6.2/CB2/A2

P6.3/CB3/A3

98

B3

A2

D5

I/O

Analog input A1 – ADC (not available on F5632, F5631, and F5630 devices)

General-purpose digital I/O

Comparator_B input CB2

99

Analog input A2 – ADC (not available on F5632, F5631, and F5630 devices)

General-purpose digital I/O

Comparator_B input CB3

100

Analog input A3 – ADC (not available on F5632, F5631, and F5630 devices)

E5,

E6,

E8,

F4,

F5,

F8,

G5,

G8,

H5,

H8,

H9

Reserved

N/A

Reserved. TI recommends connecting to ground (DVSS, AVSS).

(1) I = input, O = output, N/A = not available on this package offering

(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended

capacitor value, C_VCORE

.

(3) When this pin is configured as reset, the internal pullup resistor is enabled by default.

(4) See the Package Option Addendum in Section 11 to determine which devices are available in each package.

18

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8 Specifications

All graphs in this section are for typical conditions, unless otherwise noted.

Typical (TYP) values are specified at V_CC= 3.3 V and T_A= 25°C, unless otherwise noted.

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

MAX

4.1

UNIT

V

Voltage applied at V_CCto V_SS

–0.3

Voltage applied to any pin (excluding VCORE, VBUS, V18)⁽²⁾

V_CC+ 0.3

±2

V

Diode current at any device pin

mA

°C

Maximum junction temperature, T_J

95

(3)

Storage temperature, T_stg

–55

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS. VCORE is for internal device use only. No external DC loading or voltage should be applied.

(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

8.2 ESD Ratings

VALUE

±1000

±250

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±1000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as

±250 V may actually have higher performance.

8.3 Recommended Operating Conditions

MIN

1.8

2.0

2.2

2.4

1.8

2.0

2.2

2.4

2.2

2.4

NOM

MAX UNIT

PMMCOREVx = 0

3.6

Supply voltage during program execution and flash

PMMCOREVx = 0, 1

PMMCOREVx = 0, 1, 2

PMMCOREVx = 0, 1, 2, 3

PMMCOREVx = 0

3.6

V

3.6

V_CC

programming (AVCC1 = DVCC1 = DVCC2 = DVCC3 =

(1) (2)

DV_CC= V_CC

)

3.6

PMMCOREVx = 0, 1

PMMCOREVx = 0, 1, 2

PMMCOREVx = 0, 1, 2, 3

PMMCOREVx = 2

Supply voltage during USB operation, USB PLL disabled

(USB_EN = 1, UPLLEN = 0)

3.6

V

3.6

V_CC,USB

Supply voltage during USB operation, USB PLL enabled⁽⁶⁾

(USB_EN = 1, UPLLEN = 1)

3.6

PMMCOREVx = 2, 3

Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 =

V_SS

0

V

DVSS2 = DVSS3 = V_SS

)

T_A= 0°C to 85°C

T_A= –40°C to +85°C

I version

1.55

1.70

1.20

–40

1

3.6

V

V_BAT,RTC

Backup-supply voltage with RTC operational

3.6

V_BAT,MEM

T_A

Backup-supply voltage with backup memory retained

Operating free-air temperature

3.6

85

10

V

°C

nF

T_J

Operating junction temperature

I version

C_BAK

Capacitance at pin VBAK

4.7

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8.3 Recommended Operating Conditions (continued)

MIN

NOM

MAX UNIT

C_VCORE

C_DVCC

C_VCORE

Capacitor at VCORE⁽⁴⁾

470

nF

/

Capacitor ratio of DVCC to VCORE

10

0

PMMCOREVx = 0,

1.8 V ≤ V_CC≤ 3.6 V

(default condition)

8.0

PMMCOREVx = 1,

2 V ≤ V_CC≤ 3.6 V

Processor frequency (maximum MCLK frequency)^{(3) (5)}

(see Figure 8-1)

0

12.0

MHz

f_SYSTEM

PMMCOREVx = 2,

2.2 V ≤ V_CC≤ 3.6 V

16.0

20.0

PMMCOREVx = 3,

2.4 V ≤ V_CC≤ 3.6 V

0

f_{SYSTEM_USB}Minimum processor frequency for USB operation

USB_wait Wait state cycles during USB operation

1.5

MHz

16

cycles

(1) TI recommends powering AV_CCand DV_CCfrom the same source. A maximum difference of 0.3 V between AV_CCand DV_CCcan be

tolerated during power up and operation.

(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the threshold parameters in Section 8.22

for the exact values and more details.

(3) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the

specified maximum frequency.

(4) A capacitor tolerance of ±20% or better is required.

(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

(6) USB operation with USB PLL enabled requires PMMCOREVx ≥ 2 for proper operation.

25

20

3

16

2, 3

2

12

8

1, 2

1, 2, 3

1

0

0, 1

0, 1, 2

0, 1, 2, 3

0

1.8

2.0

2.2

2.4

3.6

Supply Voltage - V

NOTE: The numbers within the fields denote the supported PMMCOREVx settings.

Figure 8-1. Frequency vs Supply Voltage

20

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8.4 Active Mode Supply Current Into V_CCExcluding External Current

over recommended operating free-air temperature (unless otherwise noted)^{(1) (2) (3)}

FREQUENCY (f_DCO= f_MCLK= f_SMCLK

8 MHz 12 MHz

TYP MAX

)

EXECUTION

MEMORY

PARAMETER

V_CC

PMMCOREVx

1 MHz

20 MHz

UNIT

TYP

MAX

TYP

MAX

TYP

MAX

0

1

2

3

0

1

2

3

0.32

0.36

0.37

0.39

0.18

0.20

0.22

0.23

0.36

2.1

2.4

2.5

2.7

1.0

1.2

1.3

1.4

2.4

3.6

3.8

4.0

I_{AM, Flash}

Flash

RAM

3 V

mA

6.6

0.21

1.2

1.7

2.0

2.1

1.9

I_{AM, RAM}

3 V

mA

3.6

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external

load capacitance are chosen to closely match the required 12.5 pF.

(3) Characterized with program executing typical data processing. USB disabled (VUSBEN = 0, SLDOEN = 0).

f_ACLK= 32786 Hz, f_DCO= f_MCLK= f_SMCLKat specified frequency.

XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.

8.5 Low-Power Mode Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)^{(1) (2)}

TEMPERATURE (T_A)

PARAMETER

V_CC

PMMCOREVx

–40°C

TYP MAX

71

25°C

60°C

TYP MAX

81

85°C

UNIT

TYP MAX

2.2 V

3 V

0

3

0

3

0

1

2

0

1

2

3

0

1

2

3

0

1

2

3

75

83

87

98

85

94

99

108

16

I_LPM0,1MHzLow-power mode 0^{(3) (9)}

µA

78

89

2.2 V

3 V

6.3

6.7

7.0

1.8

1.9

2.0

2.1

2.2

1.2

1.3

1.1

1.2

9.9

11

9.0

11

I_LPM2

Low-power mode 2^{(4) (9)}

6.6

10

12

18

1.6

2.4

4.7

6.5

6.6

6.7

6.8

7.0

7.1

7.3

5.9

6.0

6.1

6.3

5.8

5.9

6.1

6.2

10.5

2.2 V

1.6

4.8

1.7

4.9

Low-power mode 3,

crystal mode^{(5) (9)}

I_LPM3,XT1LF

1.9

2.7

5.0

10.8

µA

1.9

5.1

3 V

2.0

5.2

2.0

2.9

1.9

5.4

12.6

10.3

0.9

4.0

Low-power mode 3,

VLO mode, Watchdog

enabled^{(6) (9)}

0.9

4.1

I_LPM3,

3 V

VLO,WDT

1.0

4.2

1.0

2.2

1.8

4.3

11.3

10

0.9

3.9

0.9

4.0

I_LPM4

Low-power mode 4^{(7) (9)}

3 V

µA

1.0

4.1

1.0

2.1

4.2

11

Low-power mode 3.5

(LPM3.5) current with

active RTC into primary

I_LPM3.5,

0.5

0.8

1.4

RTC,VCC

(10)

supply pin DV_CC

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8.5 Low-Power Mode Supply Currents (Into V_CC) Excluding External Current (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)^{(1) (2)}

TEMPERATURE (T_A)

PARAMETER

V_CC

PMMCOREVx

–40°C

25°C

60°C

85°C

UNIT

TYP MAX

Low-power mode 3.5

(LPM3.5) current with

active RTC into backup

supply pin VBAT⁽¹¹⁾

I_LPM3.5,

3 V

0.6

1.1

0.8

1.4

µA

RTC,VBAT

Total low-power mode 3.5

(LPM3.5) current with

active RTC⁽¹²⁾

I_LPM3.5,

3 V

1.0

0.2

1.3

0.7

1.6

0.9

2.8

1.4

µA

RTC,TOT

Low-power mode 4.5

(LPM4.5)⁽⁸⁾

I_LPM4.5

0.3

0.6

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external

load capacitance are chosen to closely match the required 9 pF.

(3) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), f_ACLK= 32768 Hz, f_MCLK= 0 MHz, f_SMCLK= f_DCO= 1 MHz

USB disabled (VUSBEN = 0, SLDOEN = 0).

(4) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation

(XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), f_ACLK= 32768 Hz, f_MCLK= 0 MHz, f_SMCLK= f_DCO= 0 MHz; DCO

setting = 1 MHz operation, DCO bias generator enabled.

USB disabled (VUSBEN = 0, SLDOEN = 0).

(5) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation

(XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), f_ACLK= 32768 Hz, f_MCLK= f_SMCLK= f_DCO= 0 MHz

USB disabled (VUSBEN = 0, SLDOEN = 0).

(6) Current for watchdog timer clocked by VLO included.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), f_ACLK= f_MCLK= f_SMCLK= f_DCO= 0 MHz

USB disabled (VUSBEN = 0, SLDOEN = 0).

(7) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), f_DCO= f_ACLK= f_MCLK= f_SMCLK= 0 MHz

USB disabled (VUSBEN = 0, SLDOEN = 0).

(8) Internal regulator disabled. No data retention.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), f_DCO= f_ACLK= f_MCLK= f_SMCLK= 0 MHz

(9) Current for brownout included. Low-side supervisor (SVS_L) and low-side monitor (SVM_L) disabled. High-side supervisor (SVS_H) and

high-side monitor (SVM_H) disabled. RAM retention enabled.

(10) V_VBAT= V_CC– 0.2 V, f_DCO= f_MCLK= f_SMCLK= 0 MHz, f_ACLK= 32768 Hz, PMMREGOFF = 1, RTC in backup domain active

(11) V_VBAT= V_CC– 0.2 V, f_DCO= f_MCLK= f_SMCLK= 0 MHz, f_ACLK= 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no

current drawn on VBAK

(12) f_DCO= f_MCLK= f_SMCLK= 0 MHz, f_ACLK= 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no current drawn on VBAK

8.6 Thermal Resistance Characteristics

PARAMETER

VALUE

122

108

83

UNIT

LQFP (PZ)

BGA (ZQW)

LQFP (PZ)

BGA (ZQW)

LQFP (PZ)

BGA (ZQW)

Rθ_JA

Junction-to-ambient thermal resistance, still air⁽¹⁾

°C/W

Rθ_JC(TOP)

Junction-to-case (top) thermal resistance⁽²⁾

Junction-to-board thermal resistance⁽³⁾

°C/W

72

98

Rθ_JB

76

(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board,

as specified in JESD51-7, in an environment described in JESD51-2a.

(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

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8.7 Schmitt-Trigger Inputs – General-Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

1.8 V

3 V

MIN

0.80

1.50

0.45

0.75

0.3

TYP

MAX UNIT

1.40

V

2.10

V_IT+

V_IT–

V_hys

Positive-going input threshold voltage

1.8 V

3 V

1.00

V

1.65

Negative-going input threshold voltage

1.8 V

3 V

0.8

V

1.0

Input voltage hysteresis (V_IT+– V_IT–

)

0.4

For pullup: V_IN= V_SS

For pulldown: V_IN= V_CC

R_Pull

C_I

Pullup or pulldown resistor⁽²⁾

Input capacitance

20

35

5

50

kΩ

pF

V_IN= V_SSor V_CC

(1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).

(2) Also applies to RST pin when pullup or pulldown resistor is enabled.

8.8 Inputs – Ports P1, P2, P3, and P4

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Port P1, P2, P3, P4: P1.x to P4.x,

External trigger pulse duration to set interrupt flag

t_(int)

External interrupt timing⁽²⁾

2.2 V, 3 V

20

ns

(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.

(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t_(int)is met. It may be set by trigger signals

shorter than t_(int)

.

8.9 Leakage Current – General-Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

See ^{(1) (2)}

V_CC

MIN

MAX UNIT

I_lkg(Px.x)

High-impedance leakage current

1.8 V, 3 V

±50 nA

(1) The leakage current is measured with V_SSor V_CCapplied to the corresponding pins, unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is

disabled.

8.10 Outputs – General-Purpose I/O (Full Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_(OHmax)= –3 mA⁽¹⁾

V_CC

MIN

V_CC– 0.25

V_CC– 0.60

V_CC– 0.25

V_CC– 0.60

MAX UNIT

V_CC

1.8 V

I_(OHmax)= –10 mA⁽²⁾

I_(OHmax)= –5 mA⁽¹⁾

I_(OHmax)= –15 mA⁽²⁾

I_(OLmax)= 3 mA⁽¹⁾

I_(OLmax)= 10 mA⁽²⁾

I_(OLmax)= 5 mA⁽¹⁾

I_(OLmax)= 15 mA⁽²⁾

V_CC

V_OH

High-level output voltage

V

V_CC

3 V

1.8 V

3 V

V_CC

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

V_OL

Low-level output voltage

V

(1) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage

drop specified.

(2) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage

drop specified.

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8.11 Outputs – General-Purpose I/O (Reduced Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽³⁾

PARAMETER

TEST CONDITIONS

I_(OHmax)= –1 mA⁽¹⁾

V_CC

MIN

V_CC– 0.25

V_CC– 0.60

V_CC– 0.25

V_CC– 0.60

MAX UNIT

V_CC

1.8 V

I_(OHmax)= –3 mA⁽²⁾

I_(OHmax)= –2 mA⁽¹⁾

I_(OHmax)= –6 mA⁽²⁾

I_(OLmax)= 1 mA⁽¹⁾

I_(OLmax)= 3 mA⁽²⁾

I_(OLmax)= 2 mA⁽¹⁾

I_(OLmax)= 6 mA⁽²⁾

V_CC

V_OH

High-level output voltage

V

V_CC

3 V

1.8 V

3 V

V_CC

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

V_SSV_SS+ 0.25

V_SSV_SS+ 0.60

V_OL

Low-level output voltage

V

(1) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage

drop specified.

(2) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage

drop specified.

(3) Selecting reduced drive strength may reduce EMI.

8.12 Output Frequency – Ports P1, P2, and P3

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

V_CC= 1.8 V,

PMMCOREVx = 0

8

Port output frequency

(with load)

P3.4/TA2CLK/SMCLK/S27,

f_Px.y

MHz

20

C_L= 20 pF, R_L= 1 kΩ⁽¹⁾or 3.2 kΩ^{(2) (3)}

V_CC= 3 V,

PMMCOREVx = 3

V_CC= 1.8 V,

PMMCOREVx = 0

P1.0/TA0CLK/ACLK/S39,

P3.4/TA2CLK/SMCLK/S27,

P2.0/P2MAP0 (P2MAP0 = PM_MCLK ),

C_L= 20 pF⁽³⁾

8

f_{Port_CLK}

Clock output frequency

MHz

20

V_CC= 3 V,

PMMCOREVx = 3

(1) Full drive strength of port: A resistive divider with 2 × 0.5 kΩ between V_CCand V_SSis used as load. The output is connected to the

center tap of the divider.

(2) Reduced drive strength of port: A resistive divider with 2 × 1.6 kΩ between V_CCand V_SSis used as load. The output is connected to

the center tap of the divider.

(3) The output voltage reaches at least 10% and 90% V_CCat the specified toggle frequency.

24

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8.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

25.0

20.0

15.0

10.0

5.0

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0.0

V_CC= 3.0 V

P3.2

V_CC= 1.8 V

P3.2

T_A= 25°C

T_A= 85°C

T_A= 25°C

T_A= 85°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

V_OL– Low-Level Output Voltage – V

Figure 8-3. Typical Low-Level Output Current vs

Low-Level Output Voltage

Figure 8-2. Typical Low-Level Output Current vs

Low-Level Output Voltage

0.0

V_CC= 3.0 V

P3.2

V_CC= 1.8 V

P3.2

−1.0

−5.0

−2.0

−3.0

−4.0

−10.0

−15.0

T_A= 85°C

−5.0

T_A= 85°C

−6.0

−20.0

T_A= 25°C

−7.0

−8.0

−25.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

V_OH– High-Level Output Voltage – V

Figure 8-4. Typical High-Level Output Current vs

High-Level Output Voltage

Figure 8-5. Typical High-Level Output Current vs

High-Level Output Voltage

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8.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

60.0

24

V_CC= 1.8 V

P3.2

V_CC= 3.0 V

P3.2

T_A= 25°C

T_A= 85°C

55.0

50.0

45.0

40.0

35.0

30.0

25.0

20.0

15.0

10.0

5.0

T_A= 25°C

T_A= 85°C

20

16

12

8

4

0.0

0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

V_OL– Low-Level Output Voltage – V

Figure 8-6. Typical Low-Level Output Current vs

Low-Level Output Voltage

Figure 8-7. Typical Low-Level Output Current vs

Low-Level Output Voltage

0.0

0

V_CC= 1.8 V

P3.2

V_CC= 3.0 V

−5.0

P3.2

−10.0

−15.0

−20.0

−25.0

−30.0

−35.0

−40.0

−4

−8

−12

−45.0

T_A= 85°C

−16

T_A= 85°C

−50.0

−55.0

T_A= 25°C

−60.0

T_A= 25°C

−20

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

V_OH– High-Level Output Voltage – V

Figure 8-8. Typical High-Level Output Current vs

High-Level Output Voltage

Figure 8-9. Typical High-Level Output Current vs

High-Level Output Voltage

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8.15 Crystal Oscillator, XT1, Low-Frequency Mode

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽⁵⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 1,

T_A= 25°C

0.075

Differential XT1 oscillator crystal f_OSC= 32768 Hz, XTS = 0,

ΔI_DVCC,LF

current consumption from lowest XT1BYPASS = 0, XT1DRIVEx = 2,

3 V

0.170

µA

drive setting, LF mode

T_A= 25°C

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 3,

T_A= 25°C

0.290

XT1 oscillator crystal frequency,

LF mode

f_XT1,LF0

XTS = 0, XT1BYPASS = 0

32768

Hz

XT1 oscillator logic-level square-

wave input frequency, LF mode

f_XT1,LF,SW

XTS = 0, XT1BYPASS = 1^{(6) (7)}

10 32.768

210

50 kHz

XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 0,

f_XT1,LF= 32768 Hz, C_L,eff= 6 pF

Oscillation allowance for

LF crystals⁽⁸⁾

OA_LF

kΩ

XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 1,

f_XT1,LF= 32768 Hz, C_L,eff= 12 pF

300

XTS = 0, XCAPx = 0⁽²⁾

XTS = 0, XCAPx = 1

XTS = 0, XCAPx = 2

XTS = 0, XCAPx = 3

1

5.5

Integrated effective load

capacitance, LF mode⁽¹⁾

C_L,eff

pF

8.5

12.0

XTS = 0, Measured at ACLK,

f_XT1,LF= 32768 Hz

Duty cycle, LF mode

30%

10

70%

Oscillator fault frequency,

LF mode⁽⁴⁾

f_Fault,LF

XTS = 0⁽³⁾

10000

Hz

ms

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 0,

T_A= 25°C,

1000

500

C_L,eff= 6 pF

t_START,LF

Start-up time, LF mode

3 V

f_OSC= 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 3,

T_A= 25°C,

C_L,eff= 12 pF

(1) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the used crystal.

(2) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

(3) Measured with logic-level input frequency but also applies to operation with crystals.

(4) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(5) To improve EMI on the XT1 oscillator, the following guidelines should be observed.

•

Keep the trace between the device and the crystal as short as possible.

Design a good ground plane around the oscillator pins.

Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.

If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.

(6) When XT1BYPASS is set, XT1 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined in

the Schmitt-trigger Inputs section of this datasheet.

(7) Maximum frequency of operation of the entire device cannot be exceeded.

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(8) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the

XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following

guidelines, but should be evaluated based on the actual crystal selected for the application:

•

For XT1DRIVEx = 0, C_L,eff≤ 6 pF.

For XT1DRIVEx = 1, 6 pF ≤ C_L,eff≤ 9 pF.

For XT1DRIVEx = 2, 6 pF ≤ C_L,eff≤ 10 pF.

For XT1DRIVEx = 3, C_L,eff≥ 6 pF.

8.16 Crystal Oscillator, XT2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)^{(2) (5)}

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

f_OSC= 4 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 0,

T_A= 25°C

200

f_OSC= 12 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 1,

T_A= 25°C

260

325

450

XT2 oscillator crystal current

consumption

I_DVCC,XT2

3 V

µA

f_OSC= 20 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 2,

T_A= 25°C

f_OSC= 32 MHz, XT2OFF = 0,

XT2BYPASS = 0, XT2DRIVEx = 3,

T_A= 25°C

XT2 oscillator crystal frequency,

mode 0

f_XT2,HF0

f_XT2,HF1

f_XT2,HF2

f_XT2,HF3

f_XT2,HF,SW

XT2DRIVEx = 0, XT2BYPASS = 0⁽⁷⁾

XT2DRIVEx = 1, XT2BYPASS = 0⁽⁷⁾

XT2DRIVEx = 2, XT2BYPASS = 0⁽⁷⁾

XT2DRIVEx = 3, XT2BYPASS = 0⁽⁷⁾

XT2BYPASS = 1^{(6) (7)}

4

8

MHz

XT2 oscillator crystal frequency,

mode 1

16 MHz

24 MHz

32 MHz

XT2 oscillator crystal frequency,

mode 2

16

24

0.7

XT2 oscillator crystal frequency,

mode 3

XT2 oscillator logic-level square-

wave input frequency

XT2DRIVEx = 0, XT2BYPASS = 0,

f_XT2,HF0= 6 MHz, C_L,eff= 15 pF

450

320

200

XT2DRIVEx = 1, XT2BYPASS = 0,

f_XT2,HF1= 12 MHz, C_L,eff= 15 pF

Oscillation allowance for

HF crystals⁽⁸⁾

OA_HF

Ω

XT2DRIVEx = 2, XT2BYPASS = 0,

f_XT2,HF2= 20 MHz, C_L,eff= 15 pF

XT2DRIVEx = 3, XT2BYPASS = 0,

f_XT2,HF3= 32 MHz, C_L,eff= 15 pF

f_OSC= 6 MHz

XT2BYPASS = 0, XT2DRIVEx = 0,

T_A= 25°C, C_L,eff= 15 pF

0.5

0.3

t_START,HF

Start-up time

3 V

ms

pF

f_OSC= 20 MHz

XT2BYPASS = 0, XT2DRIVEx = 3,

T_A= 25°C, C_L,eff= 15 pF

Integrated effective load

C_L,eff

1

capacitance, HF mode^{(1) (2)}

Duty cycle

Measured at ACLK, f_XT2,HF2= 20 MHz

XT2BYPASS = 1⁽³⁾

40%

30

50%

60%

300 kHz

f_Fault,HF

Oscillator fault frequency⁽⁴⁾

(1) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the used crystal.

(2) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

(3) Measured with logic-level input frequency but also applies to operation with crystals.

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(4) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies between the MIN and MAX specifications might set the flag.

(5) To improve EMI on the XT2 oscillator the following guidelines should be observed.

•

Keep the traces between the device and the crystal as short as possible.

Design a good ground plane around the oscillator pins.

Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.

Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.

Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.

If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.

(6) When XT2BYPASS is set, the XT2 circuit is automatically powered down.

(7) Maximum frequency of operation of the entire device cannot be exceeded.

(8) Oscillation allowance is based on a safety factor of 5 for recommended crystals.

8.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

VLO frequency

VLO frequency temperature drift

TEST CONDITIONS

V_CC

MIN

TYP

9.4

0.5

4

MAX UNIT

14 kHz

%/°C

f_VLO

Measured at ACLK

1.8 V to 3.6 V

6

df_VLO/d_T

Measured at ACLK⁽¹⁾

Measured at ACLK⁽²⁾

Measured at ACLK

df_VLO/dV_CCVLO frequency supply voltage drift

Duty cycle

%/V

40%

50%

60%

(1) Calculated using the box method: (MAX(–40°C to +85°C) – MIN(–40°C to +85°C)) / MIN(–40°C to +85°C) / (85°C – (–40°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

8.18 Internal Reference, Low-Frequency Oscillator (REFO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

REFO oscillator current

consumption

I_REFO

T_A= 25°C

1.8 V to 3.6 V

3

µA

REFO frequency calibrated

Measured at ACLK

Full temperature range

T_A= 25°C

1.8 V to 3.6 V

3 V

32768

Hz

±3.5%

f_REFO

REFO absolute tolerance

calibrated

±1.5%

df_REFO/d_T

REFO frequency temperature drift Measured at ACLK⁽¹⁾

1.8 V to 3.6 V

0.01

1.0

%/°C

REFO frequency supply voltage

Measured at ACLK⁽²⁾

drift

df_REFO/dV_CC

1.8 V to 3.6 V

%/V

Duty cycle

Measured at ACLK

40%/60% duty cycle

1.8 V to 3.6 V

40%

50%

25

60%

µs

t_START

REFO start-up time

(1) Calculated using the box method: (MAX(–40°C to +85°C) – MIN(–40°C to +85°C)) / MIN(–40°C to +85°C) / (85°C – (–40°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

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8.19 DCO Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

DCORSELx = 0, DCOx = 0, MODx = 0

DCORSELx = 0, DCOx = 31, MODx = 0

DCORSELx = 1, DCOx = 0, MODx = 0

DCORSELx = 1, DCOx = 31, MODx = 0

DCORSELx = 2, DCOx = 0, MODx = 0

DCORSELx = 2, DCOx = 31, MODx = 0

DCORSELx = 3, DCOx = 0, MODx = 0

DCORSELx = 3, DCOx = 31, MODx = 0

DCORSELx = 4, DCOx = 0, MODx = 0

DCORSELx = 4, DCOx = 31, MODx = 0

DCORSELx = 5, DCOx = 0, MODx = 0

DCORSELx = 5, DCOx = 31, MODx = 0

DCORSELx = 6, DCOx = 0, MODx = 0

DCORSELx = 6, DCOx = 31, MODx = 0

DCORSELx = 7, DCOx = 0, MODx = 0

DCORSELx = 7, DCOx = 31, MODx = 0

MIN

0.07

0.70

0.15

1.47

0.32

3.17

0.64

6.07

1.3

TYP

MAX UNIT

0.20 MHz

1.70 MHz

0.36 MHz

3.45 MHz

0.75 MHz

7.38 MHz

1.51 MHz

14.0 MHz

3.2 MHz

f_DCO(0,0)

f_DCO(0,31)

f_DCO(1,0)

f_DCO(1,31)

f_DCO(2,0)

f_DCO(2,31)

f_DCO(3,0)

f_DCO(3,31)

f_DCO(4,0)

f_DCO(4,31)

f_DCO(5,0)

f_DCO(5,31)

f_DCO(6,0)

f_DCO(6,31)

f_DCO(7,0)

f_DCO(7,31)

DCO frequency (0, 0)

DCO frequency (0, 31)

DCO frequency (1, 0)

DCO frequency (1, 31)

DCO frequency (2, 0)

DCO frequency (2, 31)

DCO frequency (3, 0)

DCO frequency (3, 31)

DCO frequency (4, 0)

DCO frequency (4, 31)

DCO frequency (5, 0)

DCO frequency (5, 31)

DCO frequency (6, 0)

DCO frequency (6, 31)

DCO frequency (7, 0)

DCO frequency (7, 31)

12.3

2.5

28.2 MHz

6.0 MHz

23.7

4.6

54.1 MHz

10.7 MHz

88.0 MHz

19.6 MHz

135 MHz

39.0

8.5

60

Frequency step between range

DCORSEL and DCORSEL + 1

S_DCORSEL

S_DCO

S_RSEL= f_{DCO(DCORSEL+1,DCO)}/f_{DCO(DCORSEL,DCO)}

1.2

2.3 ratio

Frequency step between tap

DCO and DCO + 1

S_DCO= f_{DCO(DCORSEL,DCO+1)}/f_{DCO(DCORSEL,DCO)}

Measured at SMCLK

1.02

40%

1.12 ratio

Duty cycle

50%

0.1

60%

%/°C

%/V

df_DCO/dT

DCO frequency temperature drift f_DCO= 1 MHz

df_DCO/dV_CC

DCO frequency voltage drift

f_DCO= 1 MHz

1.9

100

V_CC= 3.0 V

T_A= 25°C

10

DCOx = 31

1

DCOx = 0

0.1

0

1

2

3

4

5

6

7

DCORSEL

Figure 8-10. Typical DCO Frequency

30

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8.20 PMM, Brownout Reset (BOR)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

| dDV_CC/d_t| < 3 V/s

MIN

TYP

MAX UNIT

BOR_Hon voltage,

DV_CCfalling level

V_{(DVCC_BOR_IT–)}

1.45

1.50

V

BOR_Hoff voltage,

DV_CCrising level

V_{(DVCC_BOR_IT+)}

V_{(DVCC_BOR_hys)}

t_RESET

0.80

50

2

1.30

BOR_Hhysteresis

250 mV

µs

Pulse duration required at RST/NMI pin to accept

a reset

8.21 PMM, Core Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Core voltage, active mode,

PMMCOREV = 3

V_CORE3(AM)

V_CORE2(AM)

V_CORE1(AM)

V_CORE0(AM)

V_CORE3(LPM)

V_CORE2(LPM)

V_CORE1(LPM)

V_CORE0(LPM)

2.4 V ≤ DV_CC≤ 3.6 V, 0 mA ≤ I(V_CORE) ≤ 21 mA

1.90

V

Core voltage, active mode,

PMMCOREV = 2

2.2 V ≤ DV_CC≤ 3.6 V, 0 mA ≤ I(V_CORE) ≤ 21 mA

2 V ≤ DV_CC≤ 3.6 V, 0 mA ≤ I(V_CORE) ≤ 17 mA

1.8 V ≤ DV_CC≤ 3.6 V, 0 mA ≤ I(V_CORE) ≤ 13 mA

2.4 V ≤ DV_CC≤ 3.6 V, 0 µA ≤ I(V_CORE) ≤ 30 µA

2.2 V ≤ DV_CC≤ 3.6 V, 0 µA ≤ I(V_CORE) ≤ 30 µA

2 V ≤ DV_CC≤ 3.6 V, 0 µA ≤ I(V_CORE) ≤ 30 µA

1.8 V ≤ DV_CC≤ 3.6 V, 0 µA ≤ I(V_CORE) ≤ 30 µA

1.80

1.60

1.40

1.94

1.84

1.64

1.44

V

Core voltage, active mode,

PMMCOREV = 1

Core voltage, active mode,

PMMCOREV = 0

Core voltage, low-current

mode, PMMCOREV = 3

Core voltage, low-current

mode, PMMCOREV = 2

Core voltage, low-current

mode, PMMCOREV = 1

Core voltage, low-current

mode, PMMCOREV = 0

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8.22 PMM, SVS High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SVSHE = 0, DV_CC= 3.6 V

0

nA

I_(SVSH)

SVS current consumption

SVSHE = 1, DV_CC= 3.6 V, SVSHFP = 0

SVSHE = 1, DV_CC= 3.6 V, SVSHFP = 1

SVSHE = 1, SVSHRVL = 0

200

2.0

µA

1.59

1.79

1.98

2.10

1.62

1.88

2.07

2.20

2.32

2.56

2.85

1.64

1.84

2.04

2.16

1.74

1.94

2.14

2.26

2.40

2.70

3.00

2.5

1.69

SVSHE = 1, SVSHRVL = 1

1.91

V

V_{(SVSH_IT–)}

SVS_Hon voltage level⁽¹⁾

SVSHE = 1, SVSHRVL = 2

2.11

SVSHE = 1, SVSHRVL = 3

2.23

1.81

2.01

2.21

SVSHE = 1, SVSMHRRL = 0

SVSHE = 1, SVSMHRRL = 1

SVSHE = 1, SVSMHRRL = 2

SVSHE = 1, SVSMHRRL = 3

2.33

V

V_{(SVSH_IT+)}

SVS_Hoff voltage level⁽¹⁾

SVSHE = 1, SVSMHRRL = 4

2.48

SVSHE = 1, SVSMHRRL = 5

2.84

3.15

SVSHE = 1, SVSMHRRL = 6

SVSHE = 1, SVSMHRRL = 7

SVSHE = 1, dV_DVCC/dt = 10 mV/µs, SVSHFP = 1

SVSHE = 1, dV_DVCC/dt = 1 mV/µs, SVSHFP = 0

SVSHE = 0→1, SVSHFP = 1

SVSHE = 0→1, SVSHFP = 0

t_pd(SVSH)

SVS_Hpropagation delay

µs

20

12.5

100

t_(SVSH)

SVS_Hon or off delay time

DV_CCrise time

dV_DVCC/dt

0

1000

V/s

(1) The SVS_Hsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage

Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and usage.

8.23 PMM, SVM High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SVMHE = 0, DVCC = 3.6 V

0

nA

I_(SVMH)

SVM_Hcurrent consumption

SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0

SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1

SVMHE = 1, SVSMHRRL = 0

200

2.0

µA

1.86

1.65

1.85

2.02

2.18

2.32

2.56

2.85

1.74

1.94

2.14

2.26

2.40

2.70

3.00

3.75

2.5

SVMHE = 1, SVSMHRRL = 1

2.02

SVMHE = 1, SVSMHRRL = 2

2.22

SVMHE = 1, SVSMHRRL = 3

2.35

V_(SVMH)

SVM_Hon or off voltage level⁽¹⁾

SVMHE = 1, SVSMHRRL = 4

2.48

2.84

3.15

V

SVMHE = 1, SVSMHRRL = 5

SVMHE = 1, SVSMHRRL = 6

SVMHE = 1, SVSMHRRL = 7

SVMHE = 1, SVMHOVPE = 1

SVMHE = 1, dV_DVCC/dt = 10 mV/µs, SVMHFP = 1

SVMHE = 1, dV_DVCC/dt = 1 mV/µs, SVMHFP = 0

SVMHE = 0→1, SVSMFP = 1

t_pd(SVMH)

SVM_Hpropagation delay

SVM_Hon or off delay time

µs

20

12.5

100

t_(SVMH)

SVMHE = 0→1, SVMHFP = 0

(1) The SVM_Hsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage

Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and usage.

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8.24 PMM, SVS Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SVSLE = 0, PMMCOREV = 2

0

nA

µA

µs

I_(SVSL)

SVS_Lcurrent consumption

SVSLE = 1, PMMCOREV = 2, SVSLFP = 0

SVSLE = 1, PMMCOREV = 2, SVSLFP = 1

SVSLE = 1, dV_CORE/dt = 10 mV/µs, SVSLFP = 1

SVSLE = 1, dV_CORE/dt = 1 mV/µs, SVSLFP = 0

SVSLE = 0→1, SVSLFP = 1

200

2.0

2.5

20

t_pd(SVSL)

SVS_Lpropagation delay

SVS_Lon or off delay time

12.5

100

t_(SVSL)

µs

SVSLE = 0→1, SVSLFP = 0

8.25 PMM, SVM Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SVMLE = 0, PMMCOREV = 2

0

nA

µA

µs

I_(SVML)

SVM_Lcurrent consumption

SVMLE = 1, PMMCOREV = 2, SVMLFP = 0

SVMLE = 1, PMMCOREV = 2, SVMLFP = 1

SVMLE = 1, dV_CORE/dt = 10 mV/µs, SVMLFP = 1

SVMLE = 1, dV_CORE/dt = 1 mV/µs, SVMLFP = 0

SVMLE = 0→1, SVMLFP = 1

200

2.0

2.5

20

t_pd(SVML)SVM_Lpropagation delay

12.5

100

t_(SVML)

SVM_Lon or off delay time

µs

SVMLE = 0→1, SVMLFP = 0

8.26 Wake-up Times From Low-Power Modes and Reset

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

f_MCLK≥ 4 MHz

3

6.5

Wake-up time from LPM2,

LPM3, or LPM4 to active

mode⁽¹⁾

PMMCOREV = SVSMLRRL = n

(where n = 0, 1, 2, or 3),

SVSLFP = 1

t_WAKE-UP-FAST

µs

1 MHz < f_MCLK

4 MHz

<

4

8.0

Wake-up time from LPM2,

LPM3, or LPM4 to active

mode^{(2) (3)}

PMMCOREV = SVSMLRRL = n

(where n = 0, 1, 2, or 3),

SVSLFP = 0

t_WAKE-UP-SLOW

150

165

µs

Wake-up time from LPM3.5 or

LPM4.5 to active mode⁽⁴⁾

t_WAKE-UP-LPM5

t_{WAKE-UP-RESET}

2

3

ms

Wake-up time from RST or

BOR event to active mode⁽⁴⁾

(1) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the

performance mode of the low-side supervisor (SVS_L) and low-side monitor (SVM_L). t_WAKE-UP-FASTis possible with SVS_Land SVM_Lin

full performance mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode

Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx

Family User's Guide.

(2) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the

performance mode of the low-side supervisor (SVS_L) and low-side monitor (SVM_L). t_WAKE-UP-SLOWis set with SVS_Land SVM_Lin

normal mode (low current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode

Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx

Family User's Guide.

(3) The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by

the performance mode settings as for LPM2, LPM3, and LPM4.

(4) This value represents the time from the wake-up event to the reset vector execution.

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8.27 Timer_A, Timers TA0, TA1, and TA2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Internal: SMCLK or ACLK,

External: TACLK,

f_TA

Timer_A input clock frequency

1.8 V, 3 V

20 MHz

Duty cycle = 50% ±10%

All capture inputs, Minimum pulse

duration required for capture

t_TA,cap

Timer_A capture timing

1.8 V, 3 V

20

ns

8.28 Timer_B, Timer TB0

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Internal: SMCLK or ACLK,

External: TBCLK,

f_TB

Timer_B input clock frequency

1.8 V, 3 V

20 MHz

Duty cycle = 50% ±10%

All capture inputs, Minimum pulse

duration required for capture

t_TB,cap

Timer_B capture timing

1.8 V, 3 V

20

ns

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8.29 Battery Backup

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

0.43

MAX UNIT

T_A= –40°C

VBAT = 1.7 V,

DVCC not connected,

RTC running

T_A= 25°C

T_A= 60°C

T_A= 85°C

T_A= –40°C

T_A= 25°C

T_A= 60°C

T_A= 85°C

T_A= –40°C

T_A= 25°C

T_A= 60°C

T_A= 85°C

General

0.52

0.58

0.64

0.50

VBAT = 2.2 V,

DVCC not connected,

RTC running

0.59

Current into VBAT terminal if no

primary battery is connected

I_VBAT

µA

0.64

0.71

0.68

VBAT = 3 V,

DVCC not connected,

RTC running

0.75

0.79

0.86

V_{SVSH_IT-}

SVSHRL = 0

SVSHRL = 1

SVSHRL = 2

SVSHRL = 3

1.59

1.79

1.98

2.10

1.69

V_SWITCH

Switch-over level (V_CCto VBAT) C_VCC= 4.7 µF

1.91

2.11

2.23

V

ON-resistance of switch between

V_BAT= 1.8 V

R_{ON_VBAT}

0 V

0.35

1

kΩ

V

VBAT and VBAK

1.8 V

3 V

0.6

1.0

1.2

±5%

VBAT to ADC input channel 12:

V_BATdivided, V_BAT3= V_BAT/3

V_BAT3

3.6 V

t_Sample,

VBAT to ADC: Sampling time

required if VBAT3 selected

ADC12ON = 1,

Error of conversion result ≤ 1 LSB

1000

2.65

ns

V

VBAT3

V_CHVx

Charger end voltage

CHVx = 2

CHCx = 1

CHCx = 2

CHCx = 3

2.7

2.9

5

R_CHARGE

Charge limiting resistor

10

20

kΩ

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8.30 USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Internal: SMCLK or ACLK,

External: UCLK,

f_USCI

USCI input clock frequency

f_SYSTEMMHz

Duty cycle = 50% ±10%

BITCLK clock frequency

(equals baud rate in MBaud)

f_BITCLK

1

MHz

ns

2.2 V

3 V

50

600

t_τ

UART receive deglitch time⁽¹⁾

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized their width should exceed the maximum specification of the deglitch time.

8.31 USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

(see Figure 8-11 and Figure 8-12)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

SMCLK or ACLK,

f_USCI

USCI input clock frequency

f_SYSTEMMHz

Duty cycle = 50% ±10%

PMMCOREV = 0

1.8 V

3 V

55

38

30

25

0

t_SU,MI

SOMI input data setup time

SOMI input data hold time

ns

2.4 V

3 V

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

1.8 V

3 V

0

t_HD,MI

ns

2.4 V

3 V

0

1.8 V

3 V

20

UCLK edge to SIMO valid,

C_L= 20 pF, PMMCOREV = 0

18

ns

16

t_VALID,MOSIMO output data valid time⁽²⁾

2.4 V

3 V

UCLK edge to SIMO valid,

C_L= 20 pF, PMMCOREV = 3

15

1.8 V

3 V

–10

–8

C_L= 20 pF, PMMCOREV = 0

C_L= 20 pF, PMMCOREV = 3

t_HD,MO

SIMO output data hold time⁽³⁾

ns

2.4 V

3 V

–10

–8

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI≥ max(t_{VALID,MO(USCI)}+ t_SU,SI(Slave), t_SU,MI(USCI)+ t_{VALID,SO(Slave)}

)

For the slave parameters t_SU,SI(Slave)and t_{VALID,SO(Slave)}, see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams

in Figure 8-11 and Figure 8-12.

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure

8-11 and Figure 8-12.

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1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LO/HI

t_SU,MI

t_HD,MI

SOMI

SIMO

t_HD,MO

t_VALID,MO

Figure 8-11. SPI Master Mode, CKPH = 0

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LO/HI

t_HD,MI

t_SU,MI

SOMI

SIMO

t_HD,MO

t_VALID,MO

Figure 8-12. SPI Master Mode, CKPH = 1

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8.32 USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

(see Figure 8-13 and Figure 8-14)

PARAMETER

TEST CONDITIONS

V_CC

1.8 V

3 V

MIN

11

8

MAX UNIT

PMMCOREV = 0

t_STE,LEADSTE lead time, STE low to clock

ns

2.4 V

3 V

7

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

PMMCOREV = 0

PMMCOREV = 3

6

1.8 V

3 V

3

t_STE,LAG

t_STE,ACC

t_STE,DIS

t_SU,SI

STE lag time, Last clock to STE high

STE access time, STE low to SOMI data out

STE disable time, STE high to SOMI high impedance

SIMO input data setup time

ns

2.4 V

3 V

3

1.8 V

3 V

66

50

ns

36

2.4 V

3 V

30

1.8 V

3 V

23

ns

16

2.4 V

3 V

13

1.8 V

3 V

5

2

5

ns

2.4 V

3 V

1.8 V

3 V

t_HD,SI

SIMO input data hold time

ns

2.4 V

3 V

UCLK edge to SOMI valid,

C_L= 20 pF,

PMMCOREV = 0

1.8 V

76

60

3 V

2.4 V

3 V

t_VALID,SO

SOMI output data valid time⁽²⁾

SOMI output data hold time⁽³⁾

ns

UCLK edge to SOMI valid,

C_L= 20 pF,

PMMCOREV = 3

44

40

1.8 V

3 V

18

12

10

8

C_L= 20 pF,

PMMCOREV = 0

t_HD,SO

ns

2.4 V

3 V

C_L= 20 pF,

PMMCOREV = 3

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI≥ max(t_{VALID,MO(Master)}+ t_SU,SI(USCI), t_{SU,MI(Master)}+ t_{VALID,SO(USCI)}

)

For the master parameters t_{SU,MI(Master)}and t_{VALID,MO(Master)}, see the SPI parameters of the attached master.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams

in Figure 8-13 and Figure 8-14.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure

8-13 and Figure 8-14.

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t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_SU,SI

t_LO/HI

t_HD,SI

SIMO

SOMI

t_HD,SO

t_VALID,SO

t_STE,ACC

t_STE,DIS

Figure 8-13. SPI Slave Mode, CKPH = 0

t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LO/HI

t_HD,SI

t_SU,SI

SIMO

SOMI

t_HD,MO

t_VALID,SO

t_STE,ACC

t_STE,DIS

Figure 8-14. SPI Slave Mode, CKPH = 1

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8.33 USCI (I²C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see

Figure 8-15)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Internal: SMCLK or ACLK,

External: UCLK

f_USCI

USCI input clock frequency

f_SYSTEMMHz

Duty cycle = 50% ±10%

f_SCL

SCL clock frequency

2.2 V, 3 V

0

4.0

0.6

4.7

0.6

0

400 kHz

µs

f_SCL≤ 100 kHz

f_SCL> 100 kHz

f_SCL≤ 100 kHz

f_SCL> 100 kHz

t_HD,STA

Hold time (repeated) START

t_SU,STA

Setup time for a repeated START

2.2 V, 3 V

µs

t_HD,DAT

t_SU,DAT

Data hold time

Data setup time

2.2 V, 3 V

ns

250

4.0

0.6

50

f_SCL≤ 100 kHz

f_SCL> 100 kHz

t_SU,STO

Setup time for STOP

2.2 V, 3 V

µs

2.2 V

3 V

600

ns

600

Pulse duration of spikes suppressed by

input filter

t_SP

50

t_HD,STA

t_SU,STA

t_HD,STA

t_BUF

SDA

SCL

t_LOW

t_HIGH

t_SP

t_SU,DAT

t_SU,STO

t_HD,DAT

Figure 8-15. I²C Mode Timing

40

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SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

8.34 12-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽²⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

2.2

0

TYP

MAX UNIT

AVCC and DVCC are connected together,

AVSS and DVSS are connected together,

V_(AVSS)= V_(DVSS)= 0 V

AV_CC

Analog supply voltage

3.6

V

V_(Ax)

Analog input voltage range⁽³⁾All ADC12 analog input pins Ax

AV_CC

200

V

2.2 V

3 V

150

Operating supply current into

f_ADC12CLK= 5 MHz⁽¹⁾

AV_CCterminal⁽⁴⁾

I_{ADC12_A}

µA

250

Only one terminal Ax can be selected at one

time

C_I

R_I

Input capacitance

2.2 V

20

25

pF

Ω

Input MUX ON resistance

0 V ≤ V_IN≤ V_(AVCC)

10

200

1900

(1) ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0

(2) The leakage current is specified by the digital I/O input leakage.

(3) The analog input voltage range must be within the selected reference voltage range V_R+to V_R–for valid conversion results. If the

reference voltage is supplied by an external source or if the internal voltage is used and REFOUT = 1, then decoupling capacitors are

required. See Section 8.40 and Section 8.41.

(4) The internal reference supply current is not included in current consumption parameter I_ADC12

.

8.35 12-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

For specified performance of ADC12 linearity

parameters using an external reference

voltage or AVCC as reference⁽¹⁾

0.45

4.8

5.0

f_ADC12CLK

ADC conversion clock

For specified performance of ADC12 linearity 2.2 V, 3 V

parameters using the internal reference⁽²⁾

MHz

4.0

0.45

4.2

2.4

4.8

For specified performance of ADC12 linearity

parameters using the internal reference⁽³⁾

2.7

Internal ADC12

oscillator⁽⁵⁾

f_ADC12OSC

t_CONVERT

t_Sample

ADC12DIV = 0, f_ADC12CLK= f_ADC12OSC

2.2 V, 3 V

5.4 MHz

REFON = 0, Internal oscillator,

ADC12OSC used for ADC conversion clock

2.4

3.1

µs

Conversion time

Sampling time

External f_ADC12CLKfrom ACLK, MCLK or

SMCLK, ADC12SSEL ≠ 0

13 ×

1 / f_ADC12CLK

R_S= 400 Ω, R_I= 200 Ω, C_I= 20 pF,

τ = (R_S+ R_I) × C_I

2.2 V, 3 V

1000

ns

(4)

(1) REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0,

SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the

specified performance of the ADC12 linearity is ensured with f_ADC12CLKmaximum of 5 MHz.

(2) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1

(3) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when

using the ADC12OSC divided by 2.

(4) Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:

t_Sample= ln(2ⁿ⁺¹) x (R_S+ R_I) × C_I+ 800 ns, where n = ADC resolution = 12, R_S= external source resistance

(5) The ADC12OSC is sourced directly from MODOSC inside the UCS.

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8.36 12-Bit ADC, Linearity Parameters Using an External Reference Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Integral linearity error⁽²⁾

Differential linearity error⁽²⁾

Offset error⁽³⁾

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

1.4 V ≤ dVREF ≤ 1.6 V⁽¹⁾

±2

LSB

±1.7

E_I

2.2 V, 3 V

1.6 V < dVREF ⁽¹⁾

See ⁽¹⁾

E_D

E_O

E_G

E_T

2.2 V, 3 V

±1

±5.6

±3.5

±2.5

±7.1

±5

LSB

dVREF ≤ 2.2 V⁽¹⁾

dVREF > 2.2 V⁽¹⁾

See ⁽¹⁾

±3

±1.5

±1

Gain error⁽³⁾

dVREF ≤ 2.2 V⁽¹⁾

dVREF > 2.2 V⁽¹⁾

±3.5

±2

Total unadjusted error

(1) The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = V_R+- V_R-. V_R+< AVCC. V_R-> AVSS.

Unless otherwise mentioned, dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω, and two decoupling capacitors,

10 µF and 100 nF, should be connected to VREF+/VREF- to decouple the dynamic current. See also the MSP430F5xx and

MSP430F6xx Family User's Guide.

(2) Parameters are derived using the histogram method.

(3) Parameters are derived using a best fit curve.

8.37 12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

E_I

Integral linearity error⁽²⁾

See ⁽¹⁾

2.2 V, 3 V

±1.7

±1

LSB

E_D

E_O

E_G

E_T

Differential linearity error⁽²⁾

Offset error⁽³⁾

±1

±2

Gain error⁽³⁾

±4

Total unadjusted error

±5

(1) AVCC as reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 0.

(2) Parameters are derived using the histogram method.

(3) Parameters are derived using a best fit curve.

8.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS⁽¹⁾

V_CC

MIN

TYP

MAX UNIT

ADC12SR = 0, REFOUT = 1

f_ADC12CLK≤ 4.0 MHz

f_ADC12CLK≤ 2.7 MHz

f_ADC12CLK≤ 4.0 MHz

f_ADC12CLK≤ 2.7 MHz

f_ADC12CLK≤ 4.0 MHz

f_ADC12CLK≤ 2.7 MHz

f_ADC12CLK≤ 4.0 MHz

f_ADC12CLK≤ 2.7 MHz

f_ADC12CLK≤ 4.0 MHz

f_ADC12CLK≤ 2.7 MHz

±1.7

LSB

±2.5

E_I

Integral linearity error⁽²⁾

2.2 V, 3 V

ADC12SR = 0, REFOUT = 0

ADC12SR = 0, REFOUT = 1

ADC12SR = 0, REFOUT = 0

ADC12SR = 0, REFOUT = 1

ADC12SR = 0, REFOUT = 0

ADC12SR = 0, REFOUT = 1

ADC12SR = 0, REFOUT = 0

ADC12SR = 0, REFOUT = 1

ADC12SR = 0, REFOUT = 0

–1

+1.5

Differential

E_D

2.2 V, 3 V

±1

+2.5

±4

LSB

linearity error⁽²⁾

±2

±1

E_O

E_G

E_T

Offset error⁽³⁾

2.2 V, 3 V

LSB

±4

±2.5

Gain error⁽³⁾

±1%⁽⁴⁾VREF

±5 LSB

±1%⁽⁴⁾VREF

±2

Total unadjusted error

(1) The external reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 1. dVREF = V_R+- V_R-

.

(2) Parameters are derived using the histogram method.

(3) Parameters are derived using a best fit curve.

(4) The gain error and the total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In

this mode the reference voltage used by the ADC12_A is not available on a pin.

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8.39 12-Bit ADC, Temperature Sensor and Built-In V_MID

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

2.2 V

3 V

MIN

TYP

MAX UNIT

Temperature sensor voltage⁽²⁾

(see )Figure 8-16

ADC12ON = 1, INCH = 0Ah,

T_A= 0°C

680

V_SENSOR

mV

680

2.2 V

3 V

2.25

Temperature coefficient of

sensor⁽²⁾

TC_SENSOR

ADC12ON = 1, INCH = 0Ah

mV/°C

µs

2.2 V

3 V

100

Sample time required if

channel 10 is selected⁽³⁾

ADC12ON = 1, INCH = 0Ah,

Error of conversion result ≤ 1 LSB

t_{SENSOR(sample)}

2.2 V

3 V

1.06

1.46

1.1

1.5

1.14

V

1.54

ADC12ON = 1, INCH = 0Bh,

V_MID≈ 0.5 × V_AVCC

V_MID

AV_CCdivider at channel 11

Sample time required if

channel 11 is selected⁽⁴⁾

ADC12ON = 1, INCH = 0Bh,

Error of conversion result ≤ 1 LSB

t_VMID(sample)

2.2 V, 3 V

1000

ns

(1) The temperature sensor is provided by the REF module. See the REF module parametric, I_REF+, regarding the current consumption of

the temperature sensor.

(2) The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in

temperature sensor. The TLV structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference

voltage levels. The sensor voltage can be computed as V_SENSE= TC_SENSOR× (Temperature,°C) + V_SENSOR, where TC_SENSORand

V_SENSORcan be computed from the calibration values for higher accuracy. See also the MSP430F5xx and MSP430F6xx Family User's

Guide.

(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t_SENSOR(on)

(4) The on-time t_VMID(on)is included in the sampling time t_VMID(sample); no additional on time is needed.

.

1000

950

900

850

800

750

700

650

600

550

500

-40 -30 -20 -10

0 10 20 30 40 50 60 70 80

Ambient Temperature (°C)

Figure 8-16. Typical Temperature Sensor Voltage

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8.40 REF, External Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Positive external reference

voltage input

(2)

V_eREF+

V_eREF+> V_REF-/V_eREF-

1.4

AV_CC

1.2

V

Negative external

reference voltage input

(3)

(4)

V_REF-/V_eREF-

V_eREF+> V_REF-/V_eREF-

0

V_eREF+

V_REF-/V_eREF-

–

Differential external

reference voltage input

1.4

AV_CC

1.4 V ≤ V_eREF+≤ V_AVCC, V_eREF-= 0 V,

f_ADC12CLK= 5 MHz, ADC12SHTx = 1h,

Conversion rate 200 ksps

2.2 V, 3 V

–26

26

I_VeREF+, I_VREF-/

Static input current

µA

VeREF-

1.4 V ≤ V_eREF+≤ V_AVCC, V_eREF-= 0 V,

f_ADC12CLK= 5 MHz, ADC12SHTx = 8h,

Conversion rate 20 ksps

–1.2

10

+1.2

Capacitance at VREF+ or

VREF- terminal⁽⁵⁾

C_VREF+/-

µF

(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, C_i, is

also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the

recommendations on analog-source impedance to let the charge settle for 12-bit accuracy.

(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

accuracy requirements.

(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with

reduced accuracy requirements.

(5) Connect two decoupling capacitors, 10 µF and 100 nF, to VREF to decouple the dynamic current required for an external reference

source if it is used for the ADC12_A. Also see the MSP430F5xx and MSP430F6xx Family User's Guide.

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SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

8.41 REF, Built-In Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

REFVSEL = {2} for 2.5 V,

3 V

2.5

±1%

REFON = REFOUT = 1 , I_VREF+= 0 A

REFVSEL = {1} for 2 V,

Positive built-in

V_REF+

3 V

2.0

1.5

±1%

V

reference voltage output REFON = REFOUT = 1, I_VREF+= 0 A

REFVSEL = {0} for 1.5 V,

REFON = REFOUT = 1, I_VREF+= 0 A

2.2 V, 3 V

REFVSEL = {0} for 1.5 V

AVCC minimum voltage,

2.2

2.3

2.8

AV_CC(min)

Positive built-in

reference active

REFVSEL = {1} for 2 V

V

REFVSEL = {2} for 2.5 V

ADC12SR = 1⁽⁸⁾, REFON = 1, REFOUT = 0,

REFBURST = 0

70

0.45

210

100

µA

ADC12SR = 1⁽⁸⁾, REFON = 1, REFOUT = 1,

REFBURST = 0

0.75 mA

310 µA

Operating supply current

into AVCC terminal ^{(2) (7)}

I_REF+

3 V

ADC12SR = 0⁽⁸⁾, REFON = 1, REFOUT = 0,

REFBURST = 0

ADC12SR = 0⁽⁸⁾, REFON = 1, REFOUT = 1,

REFBURST = 0

0.95

1.7 mA

REFVSEL = {0, 1, 2},

Load-current regulation, I_VREF+= +10 µA , –1000 µA,

I_L(VREF+)

1500

2500 µV/mA

VREF+ terminal⁽³⁾

AV_CC= AV_CC(min)for each reference level,

REFVSEL = {0, 1, 2}, REFON = REFOUT = 1

Capacitance at VREF+

terminal

REFON = REFOUT = 1⁽⁶⁾

0 mA ≤ I_VREF+≤ I_VREF+(max)

,

C_VREF+

TC_REF+

2.2 V, 3 V

20

100

50

pF

Temperature coefficient I_VREF+is a constant in the range

of built-in reference⁽⁴⁾

of 0 mA ≤ I_VREF+≤ –1 mA

ppm/

°C

REFOUT = 0

REFOUT = 1

20

Temperature coefficient I_VREF+is a constant in the range

ppm/

°C

of built-in reference⁽⁴⁾

of 0 mA ≤ I_VREF+≤ –1 mA

AV_CC= AV_CC(min) to AV_CC(max),

T_A= 25°C, REFVSEL = {0, 1, 2}, REFON = 1,

REFOUT = 0 or 1

Power supply rejection

ratio (DC)

PSRR_DC

PSRR_AC

120

1

300 µV/V

mV/V

AV_CC= AV_CC(min) to AV_CC(max),

T_A= 25°C, REFVSEL = {0, 1, 2}, REFON = 1,

REFOUT = 0 or 1

Power supply rejection

ratio (AC)

AV_CC= AV_CC(min) to AV_CC(max),

REFVSEL = {0, 1, 2}, REFOUT = 0,

REFON = 0 → 1

75

Settling time of reference

voltage⁽⁵⁾

t_SETTLE

µs

AV_CC= AV_CC(min) to AV_CC(max),

C_VREF= C_VREF(max), REFVSEL = {0, 1, 2},

REFOUT = 1, REFON = 0 → 1

(1) The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers,

one smaller and one larger for driving the V_REF+terminal. When REFOUT = 1, the reference is available at the V_REF+terminal, as well

as, used as the reference for the conversion and uses the larger buffer. When REFOUT = 0, the reference is only used as the

reference for the conversion and uses the smaller buffer.

(2) The internal reference current is supplied by the AVCC terminal. Consumption is independent of the ADC12ON control bit, unless a

conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current

contribution of the larger buffer without external load.

(3) Contribution only due to the reference and buffer including package. This does not include resistance due to PCB traces or other

external factors.

(4) Calculated using the box method: (MAX(–40°C to +85°C) – MIN(–40°C to +85°C)) / MIN(–40°C to +85°C)/(85°C – (–40°C)).

(5) The condition is that the error in a conversion started after t_REFONis less than ±0.5 LSB. The settling time depends on the external

capacitive load when REFOUT = 1.

(6) Connect two decoupling capacitors, 10 µF and 100 nF, to VREF to decouple the dynamic current required for an external reference

source if it is used for the ADC12_A. Also see the MSP430F5xx and MSP430F6xx Family User's Guide.

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(7) The temperature sensor is provided by the REF module. Its current is supplied by terminal AVCC and is equivalent to I_REF+with

REFON = 1 and REFOUT = 0.

(8) For devices without the ADC12, the parametric with ADC12SR = 0 are applicable.

8.42 12-Bit DAC, Supply Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

AV_CCAnalog supply voltage

AV_CC= DV_CC, AV_SS= DV_SS= 0 V

2.20

3.60

110

V

DAC12AMPx = 2, DAC12IR = 0,

DAC12OG = 1, DAC12_xDAT = 0800h,

VeREF+ = VREF+ = 1.5 V

3 V

65

125

250

750

DAC12AMPx = 2, DAC12IR = 1,

DAC12_xDAT = 0800h,

VeREF+ = VREF+ = AV_CC

165

350

Supply current, single DAC

I_DD

µA

channel^{(1) (2)}

DAC12AMPx = 5, DAC12IR = 1,

DAC12_xDAT = 0800h,

VeREF+ = VREF+ = AV_CC

2.2 V, 3 V

DAC12AMPx = 7, DAC12IR = 1,

DAC12_xDAT = 0800h,

1100

VeREF+ = VREF+ = AV_CC

DAC12_xDAT = 800h,

VeREF+ = 1.5 V, ΔAV_CC= 100 mV

2.2 V

3 V

70

PSRR Power supply rejection ratio^{(3) (4)}

dB

DAC12_xDAT = 800h,

VeREF+ = 1.5 V or 2.5 V, ΔAV_CC= 100 mV

(1) No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.

(2) Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input

specifications.

(3) PSRR = 20 log (ΔAV_CC/ ΔV_{DAC12_xOUT}

(4) The internal reference is not used.

)

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SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

8.43 12-Bit DAC, Linearity Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see

Figure 8-17)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Resolution

12-bit monotonic

12

bits

VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1

VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1

VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1

VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1

2.2 V

3 V

±2

±4⁽¹⁾

LSB

±4

INL

Integral nonlinearity⁽²⁾

2.2 V

3 V

±0.4

±1⁽¹⁾

LSB

±1

DNL

Differential nonlinearity⁽²⁾

VeREF+ = 1.5 V,

DAC12AMPx = 7,

DAC12IR = 1

2.2 V

3 V

±21⁽¹⁾

Without calibration^{(2) (3)}

VeREF+ = 2.5 V,

DAC12AMPx = 7,

DAC12IR = 1

±21

mV

E_O

Offset voltage

VeREF+ = 1.5 V,

DAC12AMPx = 7,

2.2 V

±1.5⁽¹⁾

DAC12IR = 1

With calibration^{(2) (3)}

VeREF+ = 2.5 V,

DAC12AMPx = 7,

DAC12IR = 1

3 V

±1.5

Offset error temperature

coefficient⁽²⁾

d_E(O)/d_T

With calibration

2.2 V, 3 V

±10

10

µV/°C

VeREF+ = 1.5 V

VeREF+ = 2.5 V

2.2 V

3 V

±2.5

E_G

Gain error

%FSR

±2.5

ppm of

FSR/

°C

Gain temperature

coefficient⁽²⁾

d_E(G)/d_T

2.2 V, 3 V

DAC12AMPx = 2

165

Time for offset

calibration⁽⁴⁾

t_{Offset_Cal}

DAC12AMPx = 3, 5

DAC12AMPx = 4, 6, 7

66

ms

16.5

(1) This parameter is not production tested.

(2) Parameters calculated from the best-fit curve from 0x0F to 0xFFF. The best-fit curve method is used to deliver coefficients "a" and "b"

of the first-order equation: y = a + bx. V_{DAC12_xOUT}= E_O+ (1 + E_G) × (VeREF+ / 4095) × DAC12_xDAT, DAC12IR = 1.

(3) The offset calibration works on the output operational amplifier. Offset calibration is triggered by setting the DAC12CALON bit.

(4) The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx

= {0, 1}. TI recommends configuring the DAC12 module before initiating calibration. Port activity during calibration may effect accuracy

and is not recommended.

DAC V_OUT

DAC Output

V_R+

R_Load= ¥

Ideal transfer

function

AV_CC

2

Offset Error

Positive

Gain Error

C_Load= 100 pF

Negative

DAC Code

Figure 8-17. Linearity Test Load Conditions and Gain and Offset Definitions

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8.44 12-Bit DAC, Output Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

No load, VeREF+ = AV_CC

,

DAC12_xDAT = 0h, DAC12IR = 1,

DAC12AMPx = 7

0

0.005

No load, VeREF+ = AV_CC

DAC12_xDAT = 0FFFh, DAC12IR = 1,

DAC12AMPx = 7

,

AV_CC

0.05

–

AV_CC

Output voltage range⁽¹⁾

(see Figure 8-18)

V_O

2.2 V, 3 V

V

R_Load= 3 kΩ, VeREF+ = AV_CC

,

DAC12_xDAT = 0h, DAC12IR = 1,

DAC12AMPx = 7

0

0.1

R_Load= 3 kΩ, VeREF+ = AV_CC

DAC12_xDAT = 0FFFh, DAC12IR = 1,

DAC12AMPx = 7

,

AV_CC

0.13

–

AV_CC

Maximum DAC12 load

capacitance

C_L(DAC12)

2.2 V, 3 V

100

pF

DAC12AMPx = 2, DAC12_xDAT = 0FFFh,

V_O/P(DAC12)> AV_CC– 0.3

–1

Maximum DAC12 load

current

I_L(DAC12)

mA

DAC12AMPx = 2, DAC12_xDAT = 0h,

V_O/P(DAC12)< 0.3 V

1

250

6

R_Load= 3 kΩ, V_O/P(DAC12)< 0.3 V,

DAC12AMPx = 2, DAC12_xDAT = 0h

150

Output resistance (see R_Load= 3 kΩ, V_O/P(DAC12)> AV_CC– 0.3 V,

Figure 8-18)

R_O/P(DAC12)

2.2 V, 3 V

Ω

DAC12_xDAT = 0FFFh

R_Load= 3 kΩ,

0.3 V ≤ V_O/P(DAC12)≤ AV_CC– 0.3 V

(1) Data is valid after the offset calibration of the output amplifier.

R_{O/P(DAC12_x)}

Max

R_Load

I_Load

AV_CC

DAC12

2

C_Load= 100 pF

O/P(DAC12_x)

Min

0.3

AV_CC– 0.3 V

V_OUT

AV_CC

Figure 8-18. DAC12_x Output Resistance Tests

48

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8.45 12-Bit DAC, Reference Input Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

DAC12IR = 0^{(1) (2)}

V_CC

MIN

TYP

MAX UNIT

AV_CC/ 3 AV_CC+ 0.2

AV_CCAV_CC+ 0.2

Reference input voltage

range

VeREF+

2.2 V, 3 V

V

DAC12IR = 1^{(3) (4)}

DAC12_0 IR = DAC12_1 IR = 0

DAC12_0 IR = 1, DAC12_1 IR = 0

DAC12_0 IR = 0, DAC12_1 IR = 1

20

MΩ

48

Ri_(VREF+)

Ri_(VeREF+)

,

Reference input resistance

2.2 V, 3 V

kΩ

DAC12_0 IR = DAC12_1 IR = 1,

24

DAC12_0 SREFx = DAC12_1 SREFx⁽⁵⁾

(1) For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).

(2) The maximum voltage applied at reference input voltage terminal VeREF+ = (AV_CC– V_E(O)) / (3 × (1 + E_G)).

(3) For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).

(4) The maximum voltage applied at reference input voltage terminal VeREF+ = (AV_CC– V_E(O)) / (1 + E_G).

(5) When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel

reducing the reference input resistance.

8.46 12-Bit DAC, Dynamic Specifications

V_REF= V_CC, DAC12IR = 1 (see Figure 8-19 and Figure 8-20), over recommended ranges of supply voltage and

operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

DAC12AMPx = 0 → {2, 3, 4}

60

120

DAC12_xDAT = 800h,

Error_V(O)< ±0.5 LSB⁽¹⁾

(see Figure 8-19)

t_ON

DAC12 on time

DAC12AMPx = 0 → {5, 6}

DAC12AMPx = 0 → 7

DAC12AMPx = 2

2.2 V, 3 V

15

30

12

µs

6

100

40

200

80

DAC12_xDAT =

80h → F7Fh → 80h

t_S(FS)

t_S(C-C)

SR

Settling time, full scale

DAC12AMPx = 3, 5

DAC12AMPx = 4, 6, 7

DAC12AMPx = 2

2.2 V, 3 V

15

30

5

DAC12_xDAT =

3F8h → 408h → 3F8h,

BF8h → C08h → BF8h

Settling time, code to

code

DAC12AMPx = 3, 5

DAC12AMPx = 4, 6, 7

DAC12AMPx = 2

2

1

0.05

0.35

1.50

0.35

1.10

5.20

DAC12_xDAT =

Slew rate

DAC12AMPx = 3, 5

DAC12AMPx = 4, 6, 7

2.2 V, 3 V

V/µs

nV-s

80h → F7Fh → 80h⁽²⁾

DAC12_xDAT =

800h → 7FFh → 800h

Glitch energy

DAC12AMPx = 7

35

(1) R_Loadand C_Loadconnected to AV_SS(not AV_CC/2) in Figure 8-19.

(2) Slew rate applies to output voltage steps ≥ 200 mV.

Conversion 1

Conversion 2

1/2 LꢀS

Conversion 3

V_OUT

DAC Output

Glitch

Energy

R_Load= 3 kW

I_Load

AV_CC

2

1/2 LꢀS

C_Load= 100 pF

R_O/P(DAC12.x)

t_settleLH

t_settleHL

Figure 8-19. Settling Time and Glitch Energy Testing

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Conversion 1

Conversion 2

Conversion 3

V_OUT

90%

10%

t_SRLH

t_SRHL

Figure 8-20. Slew Rate Testing

8.47 12-Bit DAC, Dynamic Specifications (Continued)

over recommended ranges of supply voltage and T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,

DAC12IR = 1, DAC12_xDAT = 800h

40

3-dB bandwidth,

V_DC= 1.5 V,

V_AC= 0.1 V_PP

(see Figure 8-21)

DAC12AMPx = {5, 6}, DAC12SREFx = 2,

DAC12IR = 1, DAC12_xDAT = 800h

BW_–3dB

2.2 V, 3 V

180

550

kHz

DAC12AMPx = 7, DAC12SREFx = 2,

DAC12IR = 1, DAC12_xDAT = 800h

DAC12_0DAT = 800h, No load,

DAC12_1DAT = 80h ↔ F7Fh, R_Load= 3 kΩ,

f_{DAC12_1OUT}= 10 kHz at 50/50 duty cycle

–80

Channel-to-channel

crosstalk⁽¹⁾(see Figure

8-22)

2.2 V, 3 V

dB

DAC12_0DAT = 80h ↔ F7Fh, R_Load= 3 kΩ,

DAC12_1DAT = 800h, No load,

f_{DAC12_0OUT}= 10 kHz at 50/50 duty cycle

(1) R_Load= 3 kΩ, C_Load= 100 pF

R_Load= 3 kW

I_Load

Ve_REF+

AV_CC

2

DAC12_x

DACx

AC

DC

C_Load= 100 pF

Figure 8-21. Test Conditions for 3-dB Bandwidth Specification

R_Load

I_Load

AV_CC

DAC12_xDAT

V_OUT

080h

F7Fh

080h

F7Fh

DAC12_0

DAC12_1

2

DAC0

C_Load= 100 pF

R_Load

V_REF+

V_{DAC12_yOUT}

I_Load

V_{DAC12_xOUT}

AV_CC

2

1/f_Toggle

DAC1

C_Load= 100 pF

Figure 8-22. Crosstalk Test Conditions

50

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SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

8.48 Comparator_B

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

V_CC

Supply voltage

1.8

3.6

40

50

V

1.8 V

2.2 V

CBPWRMD = 00

30

40

Comparator operating supply current

I_{AVCC_COMP}into AVCC terminal, excludes

reference resistor ladder

3 V

65 µA

30

CBPWRMD = 01

CBPWRMD = 10

2.2 V, 3 V

10

0.1

0.5

Quiescent current of local reference

I_{AVCC_REF}

CBREFACC = 1, CBREFLx = 01

22 µA

voltage amplifier into AVCC terminal

V_IC

Common-mode input range

Input offset voltage

0

V_CC– 1

V

CBPWRMD = 00

±20

±10

V_OFFSET

C_IN

mV

CBPWRMD = 01, 10

Input capacitance

5

3

pF

kΩ

On (switch closed)

4

R_SIN

Series input resistance

Off (switch open)

50

MΩ

CBPWRMD = 00, CBF = 0

CBPWRMD = 01, CBF = 0

CBPWRMD = 10, CBF = 0

450

600

50

ns

µs

t_PD

Propagation delay, response time

Propagation delay with filter active

CBPWRMD = 00, CBON = 1,

CBF = 1, CBFDLY = 00

0.35

0.6

1.0

1.8

0.6

1.0

1.8

3.4

1

1.0

1.8

3.4

6.5

2

CBPWRMD = 00, CBON = 1,

CBF = 1, CBFDLY = 01

t_PD,filter

µs

CBPWRMD = 00, CBON = 1,

CBF = 1, CBFDLY = 10

CBPWRMD = 00, CBON = 1,

CBF = 1, CBFDLY = 11

CBON = 0 to CBON = 1,

CBPWRMD = 00, 01

t_{EN_CMP}

Comparator enable time, settling time

µs

CBON = 0 to CBON = 1,

CBPWRMD = 10

100

t_{EN_REF}

Resistor reference enable time

Reference voltage for a given tap

CBON = 0 to CBON = 1

0.3

1.5

µs

V

VIN ×

(n + 0.5)

/ 32

VIN ×

(n + 1) (n + 1.5)

/ 32 / 32

VIN ×

VIN = reference into resistor

ladder, n = 0 to 31

V_{CB_REF}

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8.49 Ports PU.0 and PU.1

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

High-level output voltage

Low-level output voltage

High-level input voltage

Low-level input voltage

TEST CONDITIONS

V_USB= 3.3 V ±10%, I_OH= –25 mA

V_USB= 3.3 V ±10%, I_OL= 25 mA

V_USB= 3.3 V ±10%

MIN

MAX

UNIT

V_OH

V_OL

V_IH

V_IL

2.4

V

0.4

2.0

V_USB= 3.3 V ±10%

0.8

8.50 USB Output Ports DP and DM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

D+, D– single ended

D+, D– impedance

Rise time

TEST CONDITIONS

MIN

2.8

0

MAX UNIT

V_OH

USB 2.0 load conditions

3.6

0.3

44

V

V_OL

Z_(DRV)

t_RISE

t_FALL

Including external series resistor of 27 Ω

28

4

Ω

Full speed, differential, C_L= 50 pF, 10%/90%, Rpu on D+

20

ns

Fall time

4

20

8.51 USB Input Ports DP and DM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

MIN

MAX UNIT

V_(CM)

Z_(IN)

V_CRS

V_IL

Differential input common-mode range

0.8

2.5

V

kΩ

V

Input impedance

300

1.3

Crossover voltage

2.0

0.8

Static SE input logic low level

Static SE input logic high level

Differential input voltage

V

V_IH

2.0

V

VDI

0.2

V

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8.52 USB-PWR (USB Power System)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_LAUNCH

V_BUS

V_BUSdetection threshold

3.75

5.5

V

USB bus voltage

Normal operation

3.76

V_USB

USB LDO output voltage

3.3

1.8

±9%

V₁₈

Internal USB voltage⁽¹⁾

I_{USB_EXT}

I_DET

Maximum external current from VUSB terminal⁽²⁾

USB LDO current overload detection⁽³⁾

USB LDO is on

12 mA

60

100 mA

USB LDO is on,

USB PLL disabled

I_SUSPEND

Operating supply current into VBUS terminal.⁽⁴⁾

250

µA

C_BUS

C_USB

C₁₈

VBUS terminal recommended capacitance

VUSB terminal recommended capacitance

V18 terminal recommended capacitance

4.7

220

µF

nF

Within 2%,

recommended capacitances

t_ENABLE

R_PUR

Settling time V_USBand V₁₈

2

ms

Ω

Pullup resistance of PUR terminal⁽⁵⁾

70

110

150

(1) This voltage is for internal use only. No external DC loading should be applied.

(2) This represents additional current that can be supplied to the application from the VUSB terminal beyond the needs of the USB

operation.

(3) A current overload is detected when the total current supplied from the USB LDO, including I_{USB_EXT}, exceeds this value.

(4) Does not include current contribution of R_puand R_pdas outlined in the USB specification.

(5) This value, in series with an external resistor between PUR and D+, produces the R_puas outlined in the USB specification.

8.53 USB-PLL (USB Phase-Locked Loop)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

MIN

TYP

MAX UNIT

I_PLL

Operating supply current

PLL frequency

7

mA

MHz

ms

f_PLL

48

f_UPD

t_LOCK

t_Jitter

PLL reference frequency

PLL lock time

1.5

3

2

PLL jitter

1000

ps

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8.54 Flash Memory

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

T_J

MIN

TYP

MAX UNIT

DV_{CC(PGM/ERASE)}Program and erase supply voltage

1.8

3.6

5

V

mA

I_PGM

Average supply current from DVCC during program

3

6

I_ERASE

Average supply current from DVCC during erase

Average supply current from DVCC during mass erase or bank erase

Cumulative program time⁽¹⁾

15

16

mA

I_MERASE, I_BANK

t_CPT

mA

ms

Program and erase endurance

10⁴

100

64

10⁵

cycles

years

µs

t_Retention

t_Word

Data retention duration

25°C

Word or byte program time⁽²⁾

85

65

t_{Block, 0}

Block program time for first byte or word⁽²⁾

49

µs

Block program time for each additional byte or word, except for last byte

or word⁽²⁾

t_{Block, 1–(N–1)}

37

49

µs

t_{Block, N}

Block program time for last byte or word⁽²⁾

55

23

73

32

µs

t_{Seg Erase}

Erase time for segment, mass erase, and bank erase when available⁽²⁾

ms

MCLK frequency in marginal read mode

(FCTL4.MGR0 = 1 or FCTL4.MGR1 = 1)

f_MCLK,MGR

0

1

MHz

(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming

methods: individual word or byte write and block write modes.

(2) These values are hardwired into the state machine of the flash controller.

8.55 JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX UNIT

f_SBW

Spy-Bi-Wire input frequency

2.2 V, 3 V

0

20 MHz

t_SBW,LowSpy-Bi-Wire low clock pulse duration

2.2 V, 3 V

0.025

15

1

µs

t_{SBW, En}

t_SBW,Rst

Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)⁽¹⁾

Spy-Bi-Wire return to normal operation time

2.2 V, 3 V

15

0

100

5

µs

2.2 V

3 V

MHz

f_TCK

TCK input frequency (4-wire JTAG)⁽²⁾

Internal pulldown resistance on TEST

0

10 MHz

80 kΩ

R_internal

2.2 V, 3 V

45

60

(1) Tools that access the Spy-Bi-Wire interface must wait for the t_SBW,Entime after pulling the TEST/SBWTCK pin high before applying the

first SBWTCK clock edge.

(2) f_TCKmay be restricted to meet the timing requirements of the module selected.

54

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9 Detailed Description

9.1 Overview

The MSP430F563x devices include a high-performance 12-bit ADC, a comparator, two USCIs, USB 2.0, a

hardware multiplier, DMA, four 16-bit timers, an RTC module with alarm capabilities, and up to 74 I/O pins.

9.2 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,

other than program-flow instructions, are performed as register operations in conjunction with seven addressing

modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register

operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant

generator, respectively. The remaining registers are general-purpose registers (see Figure 9-1).

Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be managed with

all instructions.

Program Counter

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R4

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15

Figure 9-1. Integrated CPU Registers

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MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

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9.3 Instruction Set

The instruction set consists of the original 51 instructions with three formats and seven address modes and

additional instructions for the expanded address range. Each instruction can operate on word and byte data.

Table 9-1 lists examples of the three types of instruction formats; Table 9-2 lists the address modes.

Table 9-1. Instruction Word Formats

INSTRUCTION WORD FORMAT

Dual operands, source-destination

Single operands, destination only

Relative jump, un/conditional

EXAMPLE

ADD R4,R5

CALL R8

JNE

OPERATION

R4 + R5 → R5

PC → (TOS), R8 → PC

Jump-on-equal bit = 0

Table 9-2. Address Mode Descriptions

ADDRESS MODE

Register

S⁽¹⁾

+

D⁽¹⁾

+

SYNTAX

EXAMPLE

OPERATION

R10 → R11

MOV Rs,Rd

MOV R10,R11

Indexed

+

MOV X(Rn),Y(Rm)

MOV EDE,TONI

MOV &MEM, &TCDAT

MOV @Rn,Y(Rm)

MOV 2(R5),6(R6)

M(2+R5) → M(6+R6)

M(EDE) → M(TONI)

M(MEM) → M(TCDAT)

M(R10) → M(Tab+R6)

Symbolic (PC relative)

Absolute

+

Indirect

+

MOV @R10,Tab(R6)

MOV @R10+,R11

MOV #45,TONI

M(R10) → R11

R10 + 2 → R10

Indirect auto-increment

Immediate

+

MOV @Rn+,Rm

MOV #X,TONI

#45 → M(TONI)

(1) S = source, D = destination

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9.4 Operating Modes

These devices have one active mode and seven software-selectable low-power modes of operation. An interrupt

event can wake up the device from any of the low-power modes, service the request, and restore back to the

low-power mode on return from the interrupt program.

Software can configure the following operating modes:

•

Active mode (AM)

– All clocks are active

•

Low-power mode 0 (LPM0)

– CPU is disabled

– ACLK and SMCLK remain active, MCLK is disabled

– FLL loop control remains active

Low-power mode 1 (LPM1)

•

– CPU is disabled

– FLL loop control is disabled

– ACLK and SMCLK remain active, MCLK is disabled

Low-power mode 2 (LPM2)

– CPU is disabled

– MCLK, FLL loop control, and DCOCLK are disabled

– DC generator of the DCO remains enabled

– ACLK remains active

•

Low-power mode 3 (LPM3)

– CPU is disabled

– MCLK, FLL loop control, and DCOCLK are disabled

– DC generator of the DCO is disabled

– ACLK remains active

Low-power mode 4 (LPM4)

– CPU is disabled

– ACLK is disabled

– MCLK, FLL loop control, and DCOCLK are disabled

– DC generator of the DCO is disabled

– Crystal oscillator is stopped

– Complete data retention

•

Low-power mode 3.5 (LPM3.5)

– Internal regulator disabled

– No data retention

– RTC enabled and clocked by low-frequency oscillator

– Wake-up signal from RST/NMI, RTC_B, P1, P2, P3, and P4

Low-power mode 4.5 (LPM4.5)

– Internal regulator disabled

– No data retention

– Wake-up signal from RST/NMI, P1, P2, P3, and P4

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9.5 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table

9-3). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 9-3. Interrupt Sources, Flags, and Vectors of MSP430F563x Configurations

WORD

ADDRESS

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT

PRIORITY

System Reset

Power-Up, External Reset

Watchdog Time-out, Key Violation

Flash Memory Key Violation

WDTIFG, KEYV (SYSRSTIV)^{(1) (3)}

Reset

0FFFEh

63, highest

System NMI

PMM

Vacant Memory Access

JTAG Mailbox

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG,

VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV)

(Non)maskable

0FFFCh

0FFFAh

62

61

(1)

User NMI

NMI

Oscillator Fault

NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV)^{(1) (3)}

Flash Memory Access Violation

Comp_B

Comparator B interrupt flags (CBIV)^{(1) (2)}

TB0CCR0 CCIFG0⁽²⁾

Maskable

0FFF8h

0FFF6h

60

59

Timer TB0

TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,

TB0IFG (TBIV)^{(1) (2)}

Timer TB0

Maskable

0FFF4h

58

Watchdog Interval Timer Mode

USCI_A0 Receive or Transmit

USCI_B0 Receive or Transmit

ADC12_A⁽⁵⁾

WDTIFG

Maskable

0FFF2h

0FFF0h

0FFEEh

0FFECh

0FFEAh

57

56

55

54

53

UCA0RXIFG, UCA0TXIFG (UCA0IV)^{(1) (2)}

UCB0RXIFG, UCB0TXIFG (UCB0IV)^{(1) (2)}

ADC12IFG0 to ADC12IFG15 (ADC12IV)^{(1) (2)}

TA0CCR0 CCIFG0⁽²⁾

Timer TA0

TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,

TA0IFG (TA0IV)^{(1) (2)}

Timer TA0

USB_UBM

DMA

Maskable

0FFE8h

0FFE6h

0FFE4h

0FFE2h

0FFE0h

52

51

50

49

48

USB interrupts (USBIV)^{(1) (2)}

DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG, DMA4IFG,

DMA5IFG (DMAIV)^{(1) (2)}

Timer TA1

TA1CCR0 CCIFG0⁽²⁾

TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,

TA1IFG (TA1IV)^{(1) (2)}

I/O Port P1

USCI_A1 Receive or Transmit

USCI_B1 Receive or Transmit

I/O Port P2

P1IFG.0 to P1IFG.7 (P1IV)^{(1) (2)}

UCA1RXIFG, UCA1TXIFG (UCA1IV)^{(1) (2)}

UCB1RXIFG, UCB1TXIFG (UCB1IV)^{(1) (2)}

P2IFG.0 to P2IFG.7 (P2IV)^{(1) (2)}

Reserved

Maskable

0FFDEh

0FFDCh

0FFDAh

0FFD8h

0FFD6h

47

46

45

44

43

Reserved

RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG,

RT1PSIFG, RTCOFIFG (RTCIV)^{(1) (2)}

RTC_B

Maskable

0FFD4h

42

DAC12_A⁽⁶⁾

Timer TA2

DAC12_0IFG, DAC12_1IFG^{(1) (2)}

TA2CCR0 CCIFG0⁽²⁾

Maskable

0FFD2h

0FFD0h

41

40

TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,

TA2IFG (TA2IV)^{(1) (2)}

Timer TA2

Maskable

0FFCEh

39

I/O Port P3

I/O Port P4

P3IFG.0 to P3IFG.7 (P3IV)^{(1) (2)}

P4IFG.0 to P4IFG.7 (P4IV)^{(1) (2)}

Maskable

0FFCCh

0FFCAh

0FFC8h

⋮

38

37

36

Reserved

Reserved⁽⁴⁾

⋮

0FF80h

0, lowest

(1) Multiple source flags

(2) Interrupt flags are in the module.

(3) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.

(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To

maintain compatibility with other devices, TI recommends reserving these locations.

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(5) Only on devices with peripheral module ADC12_A, otherwise reserved.

(6) Only on devices with peripheral module DAC12_A, otherwise reserved.

9.6 Memory

Table 9-4 summarizes the memory map for all device variants.

Table 9-4. Memory Organization

MSP430F5636

MSP430F5633

MSP430F5630

MSP430F5637

MSP430F5634

MSP430F5631

MSP430F5638

MSP430F5635

MSP430F5632

(1) (3)

Memory (flash)

Main: interrupt vector

128KB

00FFFFh to 00FF80h

192KB

00FFFFh to 00FF80h

256KB

00FFFFh to 00FF80h

Total Size

Bank 3

64KB

047FFFh to 038000h

N/A

64KB

037FFFh to 028000h

64KB

037FFFh to 028000h

Bank 2

Main: code memory

64KB

027FFFh to 018000h

64KB

027FFFh to 018000h

64KB

027FFFh to 018000h

Bank 1

64KB

017FFFh to 008000h

64KB

017FFFh to 008000h

64KB

017FFFh to 008000h

Bank 0

4KB

Sector 3

Sector 2

Sector 1

Sector 0

0063FFh to 005400h

4KB

0053FFh to 004400h

RAM

4KB

0043FFh to 003400h

4KB

0033FFh to 002400h

Size

RAM

2KB

USB RAM⁽²⁾

0023FFh to 001C00h

128 bytes

0019FFh to 001980h

128 bytes

0019FFh to 001980h

128 bytes

0019FFh to 001980h

Info A

Info B

Info C

Info D

BSL 3

BSL 2

BSL 1

BSL 0

Size

128 bytes

00197Fh to 001900h

128 bytes

00197Fh to 001900h

128 bytes

00197Fh to 001900h

Information memory

(flash)

128 bytes

0018FFh to 001880h

128 bytes

0018FFh to 001880h

128 bytes

0018FFh to 001880h

128 bytes

00187Fh to 001800h

128 bytes

00187Fh to 001800h

128 bytes

00187Fh to 001800h

512 bytes

0017FFh to 001600h

512 bytes

0017FFh to 001600h

512 bytes

0017FFh to 001600h

512 bytes

0015FFh to 001400h

512 bytes

0015FFh to 001400h

512 bytes

0015FFh to 001400h

Bootloader (BSL)

memory (flash)

512 bytes

0013FFh to 001200h

512 bytes

0013FFh to 001200h

512 bytes

0013FFh to 001200h

512 bytes

0011FFh to 001000h

512 bytes

0011FFh to 001000h

512 bytes

0011FFh to 001000h

4KB

Peripherals

000FFFh to 000000h

(1) N/A = Not available.

(2) USB RAM can be used as general-purpose RAM when not used for USB operation.

(3) Backup RAM is accessed through the control registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.

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9.7 Bootloader (BSL)

The BSL lets users program the flash memory or RAM using various serial interfaces. Access to the device

memory by the BSL is protected by an user-defined password. For complete description of the features of the

BSL and its implementation, see MSP430™ Flash Devices Bootloader (BSL) User's Guide.

9.7.1 USB BSL

All devices come preprogrammed with the USB BSL. Use of the USB BSL requires external access to six pins

(see Table 9-5). In addition to these pins, the application must support external components necessary for

normal USB operation; for example, the proper crystal on XT2IN and XT2OUT or proper decoupling.

Table 9-5. USB BSL Pin Requirements and

Functions

DEVICE SIGNAL

RST/NMI/SBWTDIO

PU.0/DP

BSL FUNCTION

Entry sequence signal

USB data terminal DP

USB data terminal DM

USB pullup resistor terminal

USB bus power supply

USB ground supply

PU.1/DM

PUR

VBUS

VSSU

Note

The default USB BSL evaluates the logic level of the PUR pin after a BOR reset. If the PUR pin is

pulled high externally, the BSL is invoked. Therefore, unless the application is invoking the BSL, it is

important to keep PUR pulled low after a BOR reset, even if BSL or USB is never used. TI

recommends applying a 1-MΩ resistor to ground.

9.7.2 UART BSL

A UART BSL is also available that can be programmed by the user into the BSL memory by replacing the

preprogrammed, factory supplied, USB BSL. Use of the UART BSL requires external access to six pins (see

Table 9-6).

Table 9-6. UART BSL Pin Requirements and

Functions

DEVICE SIGNAL

BSL FUNCTION

Entry sequence signal

Data transmit

RST/NMI/SBWTDIO

TEST/SBWTCK

P1.1

P1.2

VCC

VSS

Data receive

Power supply

Ground supply

9.8 JTAG Operation

9.8.1 JTAG Standard Interface

The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving

data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the

JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430

development tools and device programmers. Table 9-7 lists the JTAG pin requirements. For further details on

interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For a

complete description of the features of the JTAG interface and its implementation, see MSP430 Programming

With the JTAG Interface.

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Table 9-7. JTAG Pin Requirements and Functions

DEVICE SIGNAL

DIRECTION

FUNCTION

JTAG clock input

JTAG state control

JTAG data input, TCLK input

JTAG data output

Enable JTAG pins

External reset

PJ.3/TCK

IN

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

IN

OUT

IN

TEST/SBWTCK

RST/NMI/SBWTDIO

VCC

IN

Power supply

VSS

Ground supply

9.8.2 Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. Spy-

Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table 9-8 lists the

Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and device

programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the

JTAG interface and its implementation, see MSP430 pRogramming With the JTAG Interface.

Table 9-8. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL

TEST/SBWTCK

RST/NMI/SBWTDIO

VCC

DIRECTION

FUNCTION

Spy-Bi-Wire clock input

Spy-Bi-Wire data input/output

Power supply

IN

IN, OUT

VSS

Ground supply

9.9 Flash Memory

The flash memory can be programmed by the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the

CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the

flash memory include:

•

Flash memory has n segments of main memory and four segments of information memory (A to D) of

128 bytes each. Each segment in main memory is 512 bytes in size.

•

Segments 0 to n may be erased in one step, or each segment may be individually erased.

Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also

called information memory.

•

Segment A can be locked separately.

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9.10 RAM

The RAM is made up of n sectors. Each sector can be completely powered down to save leakage; however, all

data is lost. Features of the RAM include:

•

RAM has n sectors. The size of a sector can be found in Section 9.6.

Each sector 0 to n can be complete disabled; however, data retention is lost.

Each sector 0 to n automatically enters low power retention mode when possible.

For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.

9.11 Backup RAM

The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during

operation from a backup supply if the Battery Backup System module is implemented.

Eight bytes of backup RAM are available. The backup RAM can be wordwise accessed by the control registers

BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.

9.12 Peripherals

Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be managed

using all instructions. For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's

Guide.

9.12.1 Digital I/O

Up to nine 8-bit I/O ports are implemented: P1 through P6, P8, and P9 are complete, P7 contains six individual

I/O ports, and PJ contains four individual I/O ports.

•

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt conditions is possible.

Programmable pullup or pulldown on all ports.

Programmable drive strength on all ports.

All eight bits of ports P1, P2, P3, and P4 support edge-selectable interrupt input.

All instructions support read and write access to port-control registers.

Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PD).

9.12.2 Port Mapping Controller

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2. Table

9-9 lists the mnemonic for each function that can be assigned.

Table 9-9. Port Mapping Mnemonics and Functions

VALUE

PxMAPy MNEMONIC

INPUT PIN FUNCTION

OUTPUT PIN FUNCTION

0

PM_NONE

None

DV_SS

PM_CBOUT

–

Comparator_B output

1

2

PM_TB0CLK

Timer TB0 clock input

–

PM_ADC12CLK

PM_DMAE0

–

ADC12CLK

–

DMAE0 Input

–

PM_SVMOUT

SVM output

3

Timer TB0 high-impedance input

TB0OUTH

PM_TB0OUTH

–

4

5

6

7

8

9

PM_TB0CCR0B

PM_TB0CCR1B

PM_TB0CCR2B

PM_TB0CCR3B

PM_TB0CCR4B

PM_TB0CCR5B

Timer TB0 CCR0 capture input CCI0B

Timer TB0 CCR1 capture input CCI1B

Timer TB0 CCR2 capture input CCI2B

Timer TB0 CCR3 capture input CCI3B

Timer TB0 CCR4 capture input CCI4B

Timer TB0 CCR5 capture input CCI5B

Timer TB0: TB0.0 compare output Out0

Timer TB0: TB0.1 compare output Out1

Timer TB0: TB0.2 compare output Out2

Timer TB0: TB0.3 compare output Out3

Timer TB0: TB0.4 compare output Out4

Timer TB0: TB0.5 compare output Out5

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Table 9-9. Port Mapping Mnemonics and Functions (continued)

VALUE

PxMAPy MNEMONIC

INPUT PIN FUNCTION

Timer TB0 CCR6 capture input CCI6B

USCI_A0 UART RXD (Direction controlled by USCI – input)

OUTPUT PIN FUNCTION

10

PM_TB0CCR6B

PM_UCA0RXD

PM_UCA0SOMI

PM_UCA0TXD

PM_UCA0SIMO

PM_UCA0CLK

PM_UCB0STE

PM_UCB0SOMI

PM_UCB0SCL

PM_UCB0SIMO

PM_UCB0SDA

PM_UCB0CLK

PM_UCA0STE

PM_MCLK

Timer TB0: TB0.6 compare output Out6

11

12

13

14

15

16

USCI_A0 SPI slave out master in (direction controlled by USCI)

USCI_A0 UART TXD (Direction controlled by USCI – output)

USCI_A0 SPI slave in master out (direction controlled by USCI)

USCI_A0 clock input/output (direction controlled by USCI)

USCI_B0 SPI slave transmit enable (direction controlled by USCI – input)

USCI_B0 SPI slave out master in (direction controlled by USCI)

USCI_B0 I²C clock (open drain and direction controlled by USCI)

USCI_B0 SPI slave in master out (direction controlled by USCI)

USCI_B0 I²C data (open drain and direction controlled by USCI)

USCI_B0 clock input/output (direction controlled by USCI)

USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)

17

18

–

MCLK

Reserved

Reserved for test purposes. Do not use this setting.

19

Reserved

20–30

Reserved

None

DVSS

Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents

when applying analog signals.

31 (0FFh)⁽¹⁾

PM_ANALOG

(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are 5 bits wide, and the upper bits are ignored,

which results in a maximum value of 31.

Table 9-10 lists the default values for all pins that support port mapping.

Table 9-10. Default Mapping

PxMAPy

MNEMONIC

INPUT PIN FUNCTION

OUTPUT PIN FUNCTION

PM_UCB0STE,

PM_UCA0CLK

USCI_B0 SPI slave transmit enable (direction controlled by USCI – input),

USCI_A0 clock input/output (direction controlled by USCI)

P2.0/P2MAP0

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

PM_UCB0SIMO,

PM_UCB0SDA

USCI_B0 SPI slave in master out (direction controlled by USCI),

USCI_B0 I²C data (open drain and direction controlled by USCI)

PM_UCB0SOMI,

PM_UCB0SCL

USCI_B0 SPI slave out master in (direction controlled by USCI),

USCI_B0 I²C clock (open drain and direction controlled by USCI)

PM_UCB0CLK,

PM_UCA0STE

USCI_B0 clock input/output (direction controlled by USCI),

USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)

PM_UCA0TXD,

PM_UCA0SIMO

USCI_A0 UART TXD (direction controlled by USCI – output),

USCI_A0 SPI slave in master out (direction controlled by USCI)

PM_UCA0RXD,

PM_UCA0SOMI

USCI_A0 UART RXD (direction controlled by USCI – input),

USCI_A0 SPI slave out master in (direction controlled by USCI)

P2.6/P2MAP6

P2.7/P2MAP7

PM_NONE

–

DVSS

9.12.3 Oscillator and System Clock

The clock system is supported by the Unified Clock System (UCS) module that includes support for a 32-kHz

watch crystal oscillator (in XT1 LF mode; XT1 HF mode is not supported), an internal very-low-power low-

frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal digitally

controlled oscillator (DCO), and a high-frequency crystal oscillator XT2. The UCS module is designed to meet

the requirements of both low system cost and low power consumption. The UCS module features digital

frequency-locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency

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to a programmable multiple of the watch-crystal frequency. The internal DCO provides a fast turnon clock source

and stabilizes in 3 µs (typical). The UCS module provides the following clock signals:

•

Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the

internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally-

controlled oscillator DCO.

•

Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources available to

ACLK.

Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by

same sources available to ACLK.

ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

9.12.4 Power-Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains

programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor

(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is

implemented to provide the proper internal reset signal to the device during power-on and power-off. The SVS

and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply

voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not

automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.

9.12.5 Hardware Multiplier (MPY) (Link to User's Guide)

The multiplication operation is supported by a dedicated peripheral module. The module performs operations

with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication as well as signed

and unsigned multiply-and-accumulate operations.

9.12.6 Real-Time Clock (RTC_B)

The RTC_B module can be configured for real-time clock (RTC) or calendar mode providing seconds, minutes,

hours, day of week, day of month, month, and year. Calendar mode integrates an internal calendar which

compensates for months with less than 31 days and includes leap year correction. The RTC_B also supports

flexible alarm functions and offset-calibration hardware. The implementation on this device supports operation in

LPM3.5 mode and operation from a backup supply.

Using the MSP430 RTC_B Module With Battery Backup Supply describes how to use the RTC_B with battery

backup supply functionality to retain the time and keep the RTC counting through loss of main power supply, and

how to perform correct reinitialization when the main power supply is restored.

9.12.7 Watchdog Timer (WDT_A)

The primary function of the WDT_A module is to perform a controlled system restart after a software problem

occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed

in an application, the module can be configured as an interval timer and can generate interrupts at selected time

intervals.

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9.12.8 System Module (SYS)

The SYS module handles many of the system functions within the device. These include power-on reset and

power-up clear handling, NMI source selection and management, reset interrupt vector generators, bootloader

entry mechanisms, and configuration management (device descriptors). SYS also includes a data exchange

mechanism through JTAG called a JTAG mailbox that can be used in the application.

Table 9-11 lists the SYS interrupt vector registers.

Table 9-11. System Module Interrupt Vector Registers

INTERRUPT VECTOR REGISTER

INTERRUPT EVENT

No interrupt pending

Brownout (BOR)

RST/NMI (BOR)

PMMSWBOR (BOR)

LPM3.5 or LPM4.5 wakeup (BOR)

Security violation (BOR)

SVSL (POR)

WORD ADDRESS

OFFSET

00h

PRIORITY

02h

Highest

04h

06h

08h

0Ah

0Ch

SVSH (POR)

0Eh

SVML_OVP (POR)

SVMH_OVP (POR)

PMMSWPOR (POR)

WDT time-out (PUC)

WDT key violation (PUC)

KEYV flash key violation (PUC)

Reserved

10h

SYSRSTIV, System Reset

019Eh

12h

14h

16h

18h

1Ah

1Ch

Peripheral area fetch (PUC)

PMM key violation (PUC)

Reserved

1Eh

20h

22h to 3Eh

00h

Lowest

Highest

No interrupt pending

SVMLIFG

02h

SVMHIFG

04h

DLYLIFG

06h

DLYHIFG

08h

SYSSNIV, System NMI

VMAIFG

019Ch

0Ah

JMBINIFG

0Ch

JMBOUTIFG

0Eh

SVMLVLRIFG

10h

SVMHVLRIFG

12h

Reserved

14h to 1Eh

00h

Lowest

Highest

No interrupt pending

NMIIFG

02h

OFIFG

04h

SYSUNIV, User NMI

019Ah

0198h

ACCVIFG

06h

BUSIFG

08h

Reserved

0Ah to 1Eh

00h

Lowest

No interrupt pending

USB wait state time-out

Reserved

SYSBERRIV, Bus Error

02h

Highest

Lowest

04h to 1Eh

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9.12.9 DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention.

For example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM.

Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces

system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move

data to or from a peripheral. Table 9-12 lists the trigger assignments for each DMA channel.

The USB timestamp generator also uses the channel 0, 1, and 2 DMA trigger assignments.

Table 9-12. DMA Trigger Assignments

CHANNEL

TRIGGE

R⁽¹⁾

0

1

2

3

4

5

0

DMAREQ

1

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA2CCR2 CCIFG

TBCCR0 CCIFG

TBCCR2 CCIFG

Reserved

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Reserved

UCA0RXIFG

UCA0TXIFG

UCB0RXIFG

UCB0TXIFG

UCA1RXIFG

UCA1TXIFG

UCB1RXIFG

UCB1TXIFG

ADC12IFGx⁽²⁾

DAC12_0IFG⁽³⁾

DAC12_1IFG⁽³⁾

USB FNRXD

USB ready

MPY ready

DMA5IFG

DMA0IFG

DMA1IFG

DMA2IFG

DMAE0

DMA3IFG

DMA4IFG

(1) Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers will not

cause any DMA trigger event when selected.

(2) Only on devices with peripheral module ADC12_A. Reserved on devices without ADC.

(3) Only on devices with peripheral module DAC12_A. Reserved on devices without DAC.

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9.12.10 Universal Serial Communication Interface (USCI)

The USCI modules are used for serial data communication. The USCI module supports synchronous

communication protocols such as SPI (3 or 4 pin) and I²C, and asynchronous communication protocols such as

UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions,

A and B.

The USCI_An module provides support for SPI (3 or 4 pin), UART, enhanced UART, or IrDA.

The USCI_Bn module provides support for SPI (3 or 4 pin) or I²C.

The MSP430F563x series includes two complete USCI modules (n = 0 or 1).

9.12.11 Timer TA0

Timer TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 can support multiple

capture/compares, PWM outputs, and interval timing (see Table 9-13). TA0 also has extensive interrupt

capabilities. Interrupts may be generated from the counter on overflow conditions and from each capture/

compare register.

Table 9-13. Timer TA0 Signal Connections

INPUT PIN NUMBER

DEVICE

INPUT

SIGNAL

MODULE

INPUT

SIGNAL

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

MODULE

BLOCK

PZ

ZQW

PZ

ZQW

34-P1.0

L5-P1.0

TA0CLK

ACLK

SMCLK

TA0CLK

TA0.0

DV_SS

TACLK

ACLK

SMCLK

TACLK

CCI0A

CCI0B

GND

Timer

CCR0

NA

34-P1.0

35-P1.1

L5-P1.0

M5-P1.1

35-P1.1

M5-P1.1

TA0

TA0.0

DV_SS

DV_CC

V_CC

36-P1.2

40-P1.6

J6-P1.2

J7-P1.6

TA0.1

CCI1A

CCI1B

36-P1.2

40-P1.6

J6-P1.2

J7-P1.6

ADC12_A (internal)⁽¹⁾

ADC12SHSx = {1}

CCR1

TA1

TA0.1

DV_SS

GND

DV_CC

TA0.2

DV_SS

DV_CC

TA0.3

DV_SS

DV_CC

TA0.4

DV_SS

DV_CC

V_CC

CCI2A

CCI2B

GND

37-P1.3

41-P1.7

H6-P1.3

M7-P1.7

37-P1.3

41-P1.7

H6-P1.3

M7-P1.7

CCR2

CCR3

CCR4

TA2

TA3

TA4

TA0.2

TA0.3

TA0.4

V_CC

38-P1.4

39-P1.5

M6-P1.4

L6-P1.5

CCI3A

CCI3B

GND

38-P1.4

39-P1.5

M6-P1.4

L6-P1.5

V_CC

CCI4A

CCI4B

GND

V_CC

(1) Only on devices with peripheral module ADC12_A.

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9.12.12 Timer TA1

Timer TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 supports multiple

capture/compares, PWM outputs, and interval timing (see Table 9-14). TA1 also has extensive interrupt

capabilities. Interrupts may be generated from the counter on overflow conditions and from each capture/

compare register.

Table 9-14. Timer TA1 Signal Connections

INPUT PIN NUMBER

DEVICE

INPUT

SIGNAL

MODULE

INPUT

SIGNAL

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

MODULE

BLOCK

PZ

ZCA, ZQW

PZ

ZCA, ZQW

42-P3.0

L7-P3.0

TA1CLK

ACLK

TACLK

ACLK

SMCLK

TACLK

CCI0A

CCI0B

GND

Timer

CCR0

NA

SMCLK

TA1CLK

TA1.0

42-P3.0

43-P3.1

L7-P3.0

H7-P3.1

43-P3.1

44-P3.2

H7-P3.1

M8-P3.2

DV_SS

TA0

TA1.0

DV_SS

DV_CC

V_CC

44-P3.2

45-P3.3

M8-P3.2

L8-P3.3

TA1.1

CCI1A

DAC12_A⁽¹⁾

DAC12_0, DAC12_1

(internal)

CBOUT

(internal)

CCI1B

CCR1

CCR2

TA1

TA2

TA1.1

TA1.2

DV_SS

DV_CC

TA1.2

GND

V_CC

CCI2A

45-P3.3

L8-P3.3

ACLK

(internal)

CCI2B

DV_SS

DV_CC

GND

V_CC

(1) Only on devices with peripheral module DAC12_A.

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9.12.13 Timer TA2

Timer TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA2 supports multiple

capture/compares, PWM outputs, and interval timing (see Table 9-15). TA2 also has extensive interrupt

capabilities. Interrupts may be generated from the counter on overflow conditions and from each capture/

compare register.

Table 9-15. Timer TA2 Signal Connections

INPUT PIN NUMBER

DEVICE

INPUT

SIGNAL

MODULE

INPUT

SIGNAL

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

MODULE

BLOCK

PZ

ZCA, ZQW

PZ

ZCA, ZQW

46-P3.4

J8-P3.4

TA2CLK

ACLK

TACLK

ACLK

SMCLK

TACLK

CCI0A

CCI0B

GND

Timer

CCR0

NA

SMCLK

TA2CLK

TA2.0

46-P3.4

47-P3.5

J8-P3.4

M9-P3.5

47-P3.5

48-P3.6

M9-P3.5

L9-P3.6

DV_SS

TA0

TA2.0

DV_SS

DV_CC

V_CC

48-P3.6

49-P3.7

L9-P3.6

TA2.1

CCI1A

CBOUT

(internal)

CCI1B

CCR1

CCR2

TA1

TA2

TA2.1

TA2.2

DV_SS

DV_CC

TA2.2

GND

V_CC

M10-P3.7

CCI2A

49-P3.7

M10-P3.7

ACLK

(internal)

CCI2B

DV_SS

DV_CC

GND

V_CC

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9.12.14 Timer TB0

Timer TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. TB0 supports multiple

capture/compares, PWM outputs, and interval timing (see Table 9-16). TB0 also has extensive interrupt

capabilities. Interrupts may be generated from the counter on overflow conditions and from each capture/

compare register.

Table 9-16. Timer TB0 Signal Connections

INPUT PIN NUMBER

DEVICE

INPUT

SIGNAL

MODULE

INPUT

SIGNAL

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

MODULE

BLOCK

PZ

ZCA, ZQW

PZ

ZCA, ZQW

58-P8.0

J11-P8.0

TB0CLK

P2MAPx⁽³⁾

ACLK

Timer

NA

SMCLK

58-P8.0

J11-P8.0

TB0CLK

P2MAPx⁽³⁾

50-P4.0

J9-P4.0

TB0.0

CCI0A

CCI0B

50-P4.0

J9-P4.0

P2MAPx⁽³⁾

ADC12 (internal) ⁽¹⁾

ADC12SHSx = {2}

CCR0

CCR1

TB0

TB1

TB0.0

TB0.1

DV_SS

GND

DV_CC

TB0.1

V_CC

51-P4.1

M11-P4.1

CCI1A

CCI1B

51-P4.1

P2MAPx⁽³⁾

M11-P4.1

P2MAPx⁽³⁾

ADC12 (internal) ⁽¹⁾

ADC12SHSx = {3}

DV_SS

GND

DV_CC

TB0.2

V_CC

52-P4.2

L10-P4.2

CCI2A

CCI2B

52-P4.2

P2MAPx⁽³⁾

L10-P4.2

P2MAPx⁽³⁾

DAC12_A⁽²⁾

DAC12_0, DAC12_1

(internal)

CCR2

TB2

TB0.2

DV_SS

GND

DV_CC

TB0.3

DV_SS

DV_CC

TB0.4

DV_SS

DV_CC

TB0.5

DV_SS

DV_CC

TB0.6

DV_SS

DV_CC

V_CC

CCI3A

CCI3B

GND

53-P4.3

M12-P4.3

53-P4.3

M12-P4.3

P2MAPx⁽³⁾

CCR3

CCR4

CCR5

CCR6

TB3

TB4

TB5

TB6

TB0.3

TB0.4

TB0.5

TB0.6

V_CC

54-P4.4

L12-P4.4

CCI4A

CCI4B

GND

54-P4.4

L12-P4.4

P2MAPx⁽³⁾

V_CC

55-P4.5

L11-P4.5

CCI5A

CCI5B

GND

55-P4.5

L11-P4.5

P2MAPx⁽³⁾

V_CC

56-P4.6

K11-P4.6

CCI6A

CCI6B

GND

56-P4.6

K11-P4.6

P2MAPx⁽³⁾

V_CC

(1) Only on devices with peripheral module ADC12_A.

(2) Only on devices with peripheral module DAC12_A.

(3) Timer functions selectable by the port mapping controller.

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9.12.15 Comparator_B

The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,

battery voltage supervision, and monitoring of external analog signals.

9.12.16 ADC12_A

The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR

core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversion-

and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU

intervention.

The DAC12_A module is a 12-bit R-ladder voltage-output DAC. The DAC12_A may be used in 8-bit or 12-bit

mode, and may be used with the DMA controller. When multiple DAC12_A modules are present, they may be

grouped together for synchronous operation.

9.12.18 CRC16

The CRC16 module produces a signature based on a sequence of entered data values and can be used for data

checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.

9.12.19 Voltage Reference (REF) Module

The REF module generates all of the critical reference voltages that can be used by the various analog

peripherals in the device.

9.12.20 USB Universal Serial Bus

The USB module is a fully integrated USB interface that is compliant with the USB 2.0 specification. The module

supports full-speed operation of control, interrupt, and bulk transfers. The module includes an integrated LDO,

PHY, and PLL. The PLL is highly flexible and can support a wide range of input clock frequencies. USB RAM,

when not used for USB communication, can be used by the system.

9.12.21 Embedded Emulation Module (EEM)

The EEM supports real-time in-system debugging. The L version of the EEM has the following features:

•

Eight hardware triggers or breakpoints on memory access

Two hardware triggers or breakpoints on CPU register write access

Up to 10 hardware triggers can be combined to form complex triggers or breakpoints

Two cycle counters

Sequencer

State storage

Clock control on module level

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9.12.22 Peripheral File Map

Table 9-17 lists the register base address for all of the available peripheral modules.

Table 9-17. Peripherals

MODULE NAME

Special Functions (see Table 9-18)

PMM (see Table 9-19)

BASE ADDRESS

0100h

0120h

0140h

0150h

0158h

015Ch

0160h

0180h

01B0h

01C0h

01D0h

0200h

0220h

0240h

0260h

0280h

0320h

0340h

0380h

03C0h

0400h

0480h

04A0h

04C0h

0500h

0510h

0520h

0530h

0540h

0550h

0560h

05C0h

05E0h

0600h

0620h

0700h

0780h

08C0h

0900h

0920h

OFFSET ADDRESS RANGE⁽¹⁾

000h to 01Fh

000h to 010h

000h to 00Fh

000h to 007h

000h to 001h

000h to 01Fh

000h to 001h

000h to 003h

000h to 007h

000h to 01Fh

000h to 00Bh

000h to 01Fh

000h to 02Eh

000h to 01Fh

000h to 02Fh

000h to 00Fh

000h to 00Ah

000h to 01Fh

000h to 03Fh

000h to 01Fh

000h to 00Fh

000h to 014h

000h to 01Fh

Flash Control (see Table 9-20)

CRC16 (see Table 9-21)

RAM Control (see Table 9-22)

Watchdog (see Table 9-23)

UCS (see Table 9-24)

SYS (see Table 9-25)

Shared Reference (see Table 9-26)

Port Mapping Control (see Table 9-27)

Port Mapping Port P2 (see Table 9-27)

Port P1, P2 (see Table 9-28)

Port P3, P4 (see Table 9-29)

Port P5, P6 (see Table 9-30)

Port P7, P8 (see Table 9-31)

Port P9 (see Table 9-32)

Port PJ (see Table 9-33)

Timer TA0 (see Table 9-34)

Timer TA1 (see Table 9-35)

Timer TB0 (see Table 9-36)

Timer TA2 (see Table 9-37)

Battery Backup (see Table 9-38)

RTC_B (see Table 9-39)

32-bit Hardware Multiplier (see Table 9-40)

DMA General Control (see Table 9-41)

DMA Channel 0 (see Table 9-41)

DMA Channel 1 (see Table 9-41)

DMA Channel 2 (see Table 9-41)

DMA Channel 3 (see Table 9-41)

DMA Channel 4 (see Table 9-41)

DMA Channel 5 (see Table 9-41)

USCI_A0 (see Table 9-42)

USCI_B0 (see Table 9-43)

USCI_A1 (see Table 9-44)

USCI_B1 (see Table 9-45)

ADC12_A (see Table 9-46)

DAC12_A (see Table 9-47)

Comparator_B (see Table 9-48)

USB configuration (see Table 9-49)

USB control (see Table 9-50)

(1) For a detailed description of the individual control register offset addresses, see the MSP430F5xx and MSP430F6xx Family User's

Guide.

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Table 9-18. Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION

REGISTER

OFFSET

SFR interrupt enable

SFR interrupt flag

SFRIE1

00h

02h

04h

SFRIFG1

SFR reset pin control

SFRRPCR

Table 9-19. PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION

REGISTER

OFFSET

PMM control 0

PMMCTL0

00h

02h

04h

06h

0Ch

0Eh

10h

PMM control 1

PMMCTL1

SVSMHCTL

SVSMLCTL

PMMIFG

SVS high-side control

SVS low-side control

PMM interrupt flags

PMM interrupt enable

PMM power mode 5 control

PMMIE

PM5CTL0

Table 9-20. Flash Control Registers (Base Address: 0140h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Flash control 1

Flash control 3

Flash control 4

FCTL1

FCTL3

FCTL4

00h

04h

06h

Table 9-21. CRC16 Registers (Base Address: 0150h)

REGISTER DESCRIPTION

REGISTER

CRC data input

CRC result

CRC16DI

00h

04h

CRC16INIRES

Table 9-22. RAM Control Registers (Base Address: 0158h)

REGISTER DESCRIPTION

REGISTER

OFFSET

RAM control 0

RCCTL0

00h

Table 9-23. Watchdog Registers (Base Address: 015Ch)

REGISTER DESCRIPTION

REGISTER

Watchdog timer control

WDTCTL

Table 9-24. UCS Registers (Base Address: 0160h)

REGISTER DESCRIPTION

REGISTER

UCS control 0

UCS control 1

UCS control 2

UCS control 3

UCS control 4

UCS control 5

UCS control 6

UCS control 7

UCS control 8

UCSCTL0

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

UCSCTL1

UCSCTL2

UCSCTL3

UCSCTL4

UCSCTL5

UCSCTL6

UCSCTL7

UCSCTL8

Table 9-25. SYS Registers (Base Address: 0180h)

REGISTER DESCRIPTION

REGISTER

OFFSET

System control

SYSCTL

00h

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Table 9-25. SYS Registers (Base Address: 0180h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

Bootloader configuration area

SYSBSLC

02h

06h

08h

0Ah

0Ch

0Eh

18h

1Ah

1Ch

1Eh

JTAG mailbox control

SYSJMBC

SYSJMBI0

SYSJMBI1

SYSJMBO0

SYSJMBO1

SYSBERRIV

SYSUNIV

JTAG mailbox input 0

JTAG mailbox input 1

JTAG mailbox output 0

JTAG mailbox output 1

Bus error vector generator

User NMI vector generator

System NMI vector generator

Reset vector generator

SYSSNIV

SYSRSTIV

Table 9-26. Shared Reference Registers (Base Address: 01B0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Shared reference control

REFCTL

00h

Table 9-27. Port Mapping Registers

(Base Address of Port Mapping Control: 01C0h, Port P2: 01D0h)

REGISTER DESCRIPTION

REGISTER

Port mapping password

Port mapping control

Port P2.0 mapping

Port P2.1 mapping

Port P2.2 mapping

Port P2.3 mapping

Port P2.4 mapping

Port P2.5 mapping

Port P2.6 mapping

Port P2.7 mapping

PMAPPWD

00h

02h

00h

01h

02h

03h

04h

05h

06h

07h

PMAPCTL

P2MAP0

P2MAP1

P2MAP2

P2MAP3

P2MAP4

P2MAP5

P2MAP6

P2MAP7

Table 9-28. Port P1, P2 Registers (Base Address: 0200h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P1 input

P1IN

00h

02h

04h

06h

08h

0Ah

0Eh

18h

1Ah

1Ch

01h

03h

05h

07h

09h

0Bh

Port P1 output

Port P1 direction

P1OUT

P1DIR

P1REN

P1DS

P1SEL

P1IV

Port P1 pullup/pulldown enable

Port P1 drive strength

Port P1 selection

Port P1 interrupt vector word

Port P1 interrupt edge select

Port P1 interrupt enable

Port P1 interrupt flag

Port P2 input

P1IES

P1IE

P1IFG

P2IN

Port P2 output

P2OUT

P2DIR

P2REN

P2DS

P2SEL

Port P2 direction

Port P2 pullup/pulldown enable

Port P2 drive strength

Port P2 selection

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Table 9-28. Port P1, P2 Registers (Base Address: 0200h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P2 interrupt vector word

Port P2 interrupt edge select

Port P2 interrupt enable

Port P2 interrupt flag

P2IV

1Eh

19h

1Bh

1Dh

P2IES

P2IE

P2IFG

Table 9-29. Port P3, P4 Registers (Base Address: 0220h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P3 input

P3IN

00h

02h

04h

06h

08h

0Ah

0Eh

18h

1Ah

1Ch

01h

03h

05h

07h

09h

0Bh

1Eh

19h

1Bh

1Dh

Port P3 output

Port P3 direction

P3OUT

P3DIR

P3REN

P3DS

P3SEL

P3IV

Port P3 pullup/pulldown enable

Port P3 drive strength

Port P3 selection

Port P3 interrupt vector word

Port P3 interrupt edge select

Port P3 interrupt enable

Port P3 interrupt flag

P3IES

P3IE

P3IFG

P4IN

Port P4 input

Port P4 output

P4OUT

P4DIR

P4REN

P4DS

P4SEL

P4IV

Port P4 direction

Port P4 pullup/pulldown enable

Port P4 drive strength

Port P4 selection

Port P4 interrupt vector word

Port P4 interrupt edge select

Port P4 interrupt enable

Port P4 interrupt flag

P4IES

P4IE

P4IFG

Table 9-30. Port P5, P6 Registers (Base Address: 0240h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P5 input

P5IN

00h

02h

04h

06h

08h

0Ah

01h

03h

05h

07h

09h

0Bh

Port P5 output

P5OUT

P5DIR

P5REN

P5DS

Port P5 direction

Port P5 pullup/pulldown enable

Port P5 drive strength

Port P5 selection

P5SEL

P6IN

Port P6 input

Port P6 output

P6OUT

P6DIR

P6REN

P6DS

Port P6 direction

Port P6 pullup/pulldown enable

Port P6 drive strength

Port P6 selection

P6SEL

Table 9-31. Port P7, P8 Registers (Base Address: 0260h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P7 input

P7IN

00h

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Table 9-31. Port P7, P8 Registers (Base Address: 0260h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P7 output

P7OUT

P7DIR

P7REN

P7DS

02h

04h

06h

08h

0Ah

01h

03h

05h

07h

09h

0Bh

Port P7 direction

Port P7 pullup/pulldown enable

Port P7 drive strength

Port P7 selection

P7SEL

P8IN

Port P8 input

Port P8 output

P8OUT

P8DIR

P8REN

P8DS

Port P8 direction

Port P8 pullup/pulldown enable

Port P8 drive strength

Port P8 selection

P8SEL

Table 9-32. Port P9 Register (Base Address: 0280h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port P9 input

P9IN

00h

02h

04h

06h

08h

0Ah

Port P9 output

P9OUT

P9DIR

P9REN

P9DS

Port P9 direction

Port P9 pullup/pulldown enable

Port P9 drive strength

Port P9 selection

P9SEL

Table 9-33. Port J Registers (Base Address: 0320h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Port PJ input

PJIN

00h

02h

04h

06h

08h

Port PJ output

PJOUT

PJDIR

PJREN

PJDS

Port PJ direction

Port PJ pullup/pulldown enable

Port PJ drive strength

Table 9-34. TA0 Registers (Base Address: 0340h)

REGISTER DESCRIPTION

REGISTER

OFFSET

TA0 control

TA0CTL

00h

02h

04h

06h

08h

0Ah

10h

12h

14h

16h

18h

1Ah

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

Capture/compare control 3

Capture/compare control 4

TA0 counter

TA0CCTL0

TA0CCTL1

TA0CCTL2

TA0CCTL3

TA0CCTL4

TA0R

Capture/compare 0

Capture/compare 1

Capture/compare 2

Capture/compare 3

Capture/compare 4

TA0 expansion 0

TA0CCR0

TA0CCR1

TA0CCR2

TA0CCR3

TA0CCR4

TA0EX0

TA0 interrupt vector

TA0IV

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Table 9-35. TA1 Registers (Base Address: 0380h)

REGISTER DESCRIPTION

REGISTER

OFFSET

TA1 control

TA1CTL

00h

02h

04h

06h

10h

12h

14h

16h

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

TA1 counter

TA1CCTL0

TA1CCTL1

TA1CCTL2

TA1R

Capture/compare 0

Capture/compare 1

Capture/compare 2

TA1 expansion 0

TA1CCR0

TA1CCR1

TA1CCR2

TA1EX0

TA1 interrupt vector

TA1IV

Table 9-36. TB0 Registers (Base Address: 03C0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

TB0 control

TB0CTL

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

18h

1Ah

1Ch

1Eh

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

Capture/compare control 3

Capture/compare control 4

Capture/compare control 5

Capture/compare control 6

TB0 counter

TB0CCTL0

TB0CCTL1

TB0CCTL2

TB0CCTL3

TB0CCTL4

TB0CCTL5

TB0CCTL6

TB0R

Capture/compare 0

TB0CCR0

TB0CCR1

TB0CCR2

TB0CCR3

TB0CCR4

TB0CCR5

TB0CCR6

TB0EX0

Capture/compare 1

Capture/compare 2

Capture/compare 3

Capture/compare 4

Capture/compare 5

Capture/compare 6

TB0 expansion 0

TB0 interrupt vector

TB0IV

Table 9-37. TA2 Registers (Base Address: 0400h)

REGISTER DESCRIPTION

REGISTER

OFFSET

TA2 control

TA2CTL

00h

02h

04h

06h

10h

12h

14h

16h

20h

2Eh

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

TA2 counter

TA2CCTL0

TA2CCTL1

TA2CCTL2

TA2R

Capture/compare 0

Capture/compare 1

Capture/compare 2

TA2 expansion 0

TA2CCR0

TA2CCR1

TA2CCR2

TA2EX0

TA2 interrupt vector

TA2IV

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Table 9-38. Battery Backup Registers (Base Address: 0480h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Battery backup memory 0

Battery backup memory 1

Battery backup memory 2

Battery backup memory 3

Battery backup control

Battery charger control

BAKMEM0

00h

02h

04h

06h

1Ch

1Eh

BAKMEM1

BAKMEM2

BAKMEM3

BAKCTL

BAKCHCTL

Table 9-39. Real-Time Clock Registers (Base Address: 04A0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

RTC control 0

RTCCTL0

00h

01h

02h

03h

08h

0Ah

0Ch

0Dh

0Eh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Eh

RTC control 1

RTCCTL1

RTCCTL2

RTCCTL3

RTCPS0CTL

RTCPS1CTL

RTCPS0

RTC control 2

RTC control 3

RTC prescaler 0 control

RTC prescaler 1 control

RTC prescaler 0

RTC prescaler 1

RTC interrupt vector word

RTC seconds

RTCPS1

RTCIV

RTCSEC

RTC minutes

RTCMIN

RTC hours

RTCHOUR

RTCDOW

RTCDAY

RTC day of week

RTC days

RTC month

RTCMON

RTCYEARL

RTCYEARH

RTCAMIN

RTCAHOUR

RTCADOW

RTCADAY

BIN2BCD

BCD2BIN

RTC year low

RTC year high

RTC alarm minutes

RTC alarm hours

RTC alarm day of week

RTC alarm days

Binary-to-BCD conversion

BCD-to-binary conversion

Table 9-40. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

16-bit operand 1 – multiply

MPY

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16-bit operand 1 – signed multiply

16-bit operand 1 – multiply accumulate

16-bit operand 1 – signed multiply accumulate

16-bit operand 2

MPYS

MAC

MACS

OP2

16 × 16 result low word

RESLO

RESHI

16 × 16 result high word

16 × 16 sum extension

SUMEXT

MPY32L

MPY32H

MPYS32L

32-bit operand 1 – multiply low word

32-bit operand 1 – multiply high word

32-bit operand 1 – signed multiply low word

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Table 9-40. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

32-bit operand 1 – signed multiply high word

32-bit operand 1 – multiply accumulate low word

32-bit operand 1 – multiply accumulate high word

32-bit operand 1 – signed multiply accumulate low word

32-bit operand 1 – signed multiply accumulate high word

32-bit operand 2 – low word

MPYS32H

16h

18h

1Ah

1Ch

1Eh

20h

22h

24h

26h

28h

2Ah

2Ch

MAC32L

MAC32H

MACS32L

MACS32H

OP2L

32-bit operand 2 – high word

OP2H

32 × 32 result 0 – least significant word

32 × 32 result 1

RES0

RES1

32 × 32 result 2

RES2

32 × 32 result 3 – most significant word

MPY32 control 0

RES3

MPY32CTL0

Table 9-41. DMA Registers (Base Address DMA General Control: 0500h,

DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA

Channel 4: 0550h, DMA Channel 5: 0560h)

REGISTER DESCRIPTION

REGISTER

OFFSET

DMA general control: DMA module control 0

DMACTL0

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

DMA general control: DMA module control 1

DMA general control: DMA module control 2

DMA general control: DMA module control 3

DMA general control: DMA module control 4

DMA general control: DMA interrupt vector

DMA channel 0 control

DMACTL1

DMACTL2

DMACTL3

DMACTL4

DMAIV

DMA0CTL

DMA0SAL

DMA0SAH

DMA0DAL

DMA0DAH

DMA0SZ

DMA channel 0 source address low

DMA channel 0 source address high

DMA channel 0 destination address low

DMA channel 0 destination address high

DMA channel 0 transfer size

DMA channel 1 control

DMA1CTL

DMA1SAL

DMA1SAH

DMA1DAL

DMA1DAH

DMA1SZ

DMA channel 1 source address low

DMA channel 1 source address high

DMA channel 1 destination address low

DMA channel 1 destination address high

DMA channel 1 transfer size

DMA channel 2 control

DMA2CTL

DMA2SAL

DMA2SAH

DMA2DAL

DMA2DAH

DMA2SZ

DMA channel 2 source address low

DMA channel 2 source address high

DMA channel 2 destination address low

DMA channel 2 destination address high

DMA channel 2 transfer size

DMA channel 3 control

DMA3CTL

DMA3SAL

DMA3SAH

DMA3DAL

DMA3DAH

DMA channel 3 source address low

DMA channel 3 source address high

DMA channel 3 destination address low

DMA channel 3 destination address high

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Table 9-41. DMA Registers (Base Address DMA General Control: 0500h,

DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA

Channel 4: 0550h, DMA Channel 5: 0560h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

DMA channel 3 transfer size

DMA channel 4 control

DMA3SZ

0Ah

00h

02h

04h

06h

08h

0Ah

00h

02h

04h

06h

08h

0Ah

DMA4CTL

DMA4SAL

DMA4SAH

DMA4DAL

DMA4DAH

DMA4SZ

DMA channel 4 source address low

DMA channel 4 source address high

DMA channel 4 destination address low

DMA channel 4 destination address high

DMA channel 4 transfer size

DMA channel 5 control

DMA5CTL

DMA5SAL

DMA5SAH

DMA5DAL

DMA5DAH

DMA5SZ

DMA channel 5 source address low

DMA channel 5 source address high

DMA channel 5 destination address low

DMA channel 5 destination address high

DMA channel 5 transfer size

Table 9-42. USCI_A0 Registers (Base Address: 05C0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI control 0

UCA0CTL0

00h

01h

06h

07h

08h

0Ah

0Ch

0Eh

10h

12h

13h

1Ch

1Dh

1Eh

USCI control 1

UCA0CTL1

UCA0BR0

USCI baud rate 0

USCI baud rate 1

UCA0BR1

USCI modulation control

USCI status

UCA0MCTL

UCA0STAT

UCA0RXBUF

UCA0TXBUF

UCA0ABCTL

UCA0IRTCTL

UCA0IRRCTL

UCA0IE

USCI receive buffer

USCI transmit buffer

USCI LIN control

USCI IrDA transmit control

USCI IrDA receive control

USCI interrupt enable

USCI interrupt flags

USCI interrupt vector word

UCA0IFG

UCA0IV

Table 9-43. USCI_B0 Registers (Base Address: 05E0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI synchronous control 0

USCI synchronous control 1

USCI synchronous bit rate 0

USCI synchronous bit rate 1

USCI synchronous status

UCB0CTL0

00h

01h

06h

07h

0Ah

0Ch

0Eh

10h

12h

1Ch

1Dh

UCB0CTL1

UCB0BR0

UCB0BR1

UCB0STAT

UCB0RXBUF

UCB0TXBUF

UCB0I2COA

UCB0I2CSA

UCB0IE

USCI synchronous receive buffer

USCI synchronous transmit buffer

USCI I2C own address

USCI I2C slave address

USCI interrupt enable

USCI interrupt flags

UCB0IFG

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Table 9-43. USCI_B0 Registers (Base Address: 05E0h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI interrupt vector word

UCB0IV

1Eh

Table 9-44. USCI_A1 Registers (Base Address: 0600h)

REGISTER DESCRIPTION

REGISTER

USCI control 0

UCA1CTL0

00h

01h

06h

07h

08h

0Ah

0Ch

0Eh

10h

12h

13h

1Ch

1Dh

1Eh

USCI control 1

UCA1CTL1

UCA1BR0

USCI baud rate 0

USCI baud rate 1

UCA1BR1

USCI modulation control

USCI status

UCA1MCTL

UCA1STAT

UCA1RXBUF

UCA1TXBUF

UCA1ABCTL

UCA1IRTCTL

UCA1IRRCTL

UCA1IE

USCI receive buffer

USCI transmit buffer

USCI LIN control

USCI IrDA transmit control

USCI IrDA receive control

USCI interrupt enable

USCI interrupt flags

USCI interrupt vector word

UCA1IFG

UCA1IV

Table 9-45. USCI_B1 Registers (Base Address: 0620h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USCI synchronous control 0

USCI synchronous control 1

USCI synchronous bit rate 0

USCI synchronous bit rate 1

USCI synchronous status

UCB1CTL0

00h

01h

06h

07h

0Ah

0Ch

0Eh

10h

12h

1Ch

1Dh

1Eh

UCB1CTL1

UCB1BR0

UCB1BR1

UCB1STAT

UCB1RXBUF

UCB1TXBUF

UCB1I2COA

UCB1I2CSA

UCB1IE

USCI synchronous receive buffer

USCI synchronous transmit buffer

USCI I2C own address

USCI I2C slave address

USCI interrupt enable

USCI interrupt flags

UCB1IFG

USCI interrupt vector word

UCB1IV

Table 9-46. ADC12_A Registers (Base Address: 0700h)

REGISTER DESCRIPTION

REGISTER

OFFSET

ADC12 control 0

ADC12CTL0

00h

02h

04h

0Ah

0Ch

0Eh

10h

11h

12h

13h

ADC12 control 1

ADC12CTL1

ADC12CTL2

ADC12IFG

ADC12 control 2

Interrupt flag

Interrupt enable

ADC12IE

Interrupt vector word

ADC memory control 0

ADC memory control 1

ADC memory control 2

ADC memory control 3

ADC12IV

ADC12MCTL0

ADC12MCTL1

ADC12MCTL2

ADC12MCTL3

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MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

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Table 9-46. ADC12_A Registers (Base Address: 0700h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

ADC memory control 4

ADC memory control 5

ADC memory control 6

ADC memory control 7

ADC memory control 8

ADC memory control 9

ADC memory control 10

ADC memory control 11

ADC memory control 12

ADC memory control 13

ADC memory control 14

ADC memory control 15

Conversion memory 0

Conversion memory 1

Conversion memory 2

Conversion memory 3

Conversion memory 4

Conversion memory 5

Conversion memory 6

Conversion memory 7

Conversion memory 8

Conversion memory 9

Conversion memory 10

Conversion memory 11

Conversion memory 12

Conversion memory 13

Conversion memory 14

Conversion memory 15

ADC12MCTL4

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

22h

24h

26h

28h

2Ah

2Ch

2Eh

30h

32h

34h

36h

38h

3Ah

3Ch

3Eh

ADC12MCTL5

ADC12MCTL6

ADC12MCTL7

ADC12MCTL8

ADC12MCTL9

ADC12MCTL10

ADC12MCTL11

ADC12MCTL12

ADC12MCTL13

ADC12MCTL14

ADC12MCTL15

ADC12MEM0

ADC12MEM1

ADC12MEM2

ADC12MEM3

ADC12MEM4

ADC12MEM5

ADC12MEM6

ADC12MEM7

ADC12MEM8

ADC12MEM9

ADC12MEM10

ADC12MEM11

ADC12MEM12

ADC12MEM13

ADC12MEM14

ADC12MEM15

Table 9-47. DAC12_A Registers (Base Address: 0780h)

REGISTER DESCRIPTION

REGISTER

OFFSET

DAC12_A channel 0 control 0

DAC12_A channel 0 control 1

DAC12_A channel 0 data

DAC12_0CTL0

00h

02h

04h

06h

08h

10h

12h

14h

16h

18h

1Eh

DAC12_0CTL1

DAC12_0DAT

DAC12_A channel 0 calibration control

DAC12_A channel 0 calibration data

DAC12_A channel 1 control 0

DAC12_A channel 1 control 1

DAC12_A channel 1 data

DAC12_0CALCTL

DAC12_0CALDAT

DAC12_1CTL0

DAC12_1CTL1

DAC12_1DAT

DAC12_A channel 1 calibration control

DAC12_A channel 1 calibration data

DAC12_A interrupt vector word

DAC12_1CALCTL

DAC12_1CALDAT

DAC12IV

Table 9-48. Comparator_B Registers (Base Address: 08C0h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Comp_B control 0

CBCTL0

00h

82

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SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

Table 9-48. Comparator_B Registers (Base Address: 08C0h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

Comp_B control 1

Comp_B control 2

Comp_B control 3

Comp_B interrupt

CBCTL1

02h

04h

06h

0Ch

0Eh

CBCTL2

CBCTL3

CBINT

CBIV

Comp_B interrupt vector word

Table 9-49. USB Configuration Registers (Base Address: 0900h)

REGISTER DESCRIPTION

REGISTER

OFFSET

USB key/ID

USBKEYID

00h

02h

04h

08h

0Ah

10h

12h

14h

USB module configuration

USB PHY control

USBCNF

USBPHYCTL

USBPWRCTL

USBPWRVSR

USBPLLCTL

USBPLLDIV

USBPLLIR

USB power control

USB power voltage setting

USB PLL control

USB PLL divider

USB PLL interrupts

Table 9-50. USB Control Registers (Base Address: 0920h)

REGISTER DESCRIPTION

REGISTER

OFFSET

Input endpoint_0 configuration

Input endpoint_0 byte count

Output endpoint_0 configuration

Output endpoint_0 byte count

Input endpoint interrupt enables

Output endpoint interrupt enables

Input endpoint interrupt flags

Output endpoint interrupt flags

USB interrupt vector

USBIEPCNF_0

00h

01h

02h

03h

0Eh

0Fh

10h

11h

12h

16h

18h

1Ah

1Ch

1Dh

1Eh

1Fh

USBIEPCNT_0

USBOEPCNF_0

USBOEPCNT_0

USBIEPIE

USBOEPIE

USBIEPIFG

USBOEPIFG

USBIV

USB maintenance

USBMAINT

USBTSREG

USBFN

Timestamp

USB frame number

USB control

USBCTL

USB interrupt enables

USB interrupt flags

USBIE

USBIFG

Function address

USBFUNADR

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MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

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9.13 Input/Output Diagrams

9.13.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger

Figure 9-2 shows the pin diagram. Table 9-51 summarizes how to select the pin function.

Pad Logic

P1REN.x

DV_SS

DV_CC

0

1

Direction

0: Input

1: Output

P1DIR.x

P1OUT.x

0

1

Module X OUT

P1.0/TA0CLK/ACLK

P1.1/TA0.0

P1.2/TA0.1

P1.3/TA0.2

P1.4/TA0.3

P1DS.x

0: Low drive

1: High drive

P1SEL.x

P1IN.x

P1.5/TA0.4

P1.6/TA0.1

P1.7/TA0.2

EN

D

Module X IN

P1IRQ.x

P1IE.x

EN

Q

P1IFG.x

Set

P1SEL.x

P1IES.x

Interrupt

Edge

Select

Figure 9-2. Port P1 (P1.0 to P1.7) Diagram

84

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SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

Table 9-51. Port P1 (P1.0 to P1.7) Pin Functions

CONTROL BITS OR SIGNALS

FUNCTION

PIN NAME (P1.x)

x

P1DIR.x

P1SEL.x

P1.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P1.0/TA0CLK/ACLK

P1.1/TA0.0

0

Timer TA0.TA0CLK

ACLK

0

1

P1.1 (I/O)

I: 0; O: 1

1

2

3

4

5

6

7

Timer TA0.CCI0A capture input

Timer TA0.0 output

P1.2 (I/O)

0

1

I: 0; O: 1

P1.2/TA0.1

Timer TA0.CCI1A capture input

Timer TA0.1 output

P1.3 (I/O)

0

1

I: 0; O: 1

P1.3/TA0.2

Timer TA0.CCI2A capture input

Timer TA0.2 output

P1.4 (I/O)

0

1

I: 0; O: 1

P1.4/TA0.3

Timer TA0.CCI3A capture input

Timer TA0.3 output

P1.5 (I/O)

0

1

I: 0; O: 1

P1.5/TA0.4

Timer TA0.CCI4A capture input

Timer TA0.4 output

P1.6 (I/O)

0

1

I: 0; O: 1

P1.6/TA0.1

Timer TA0.CCI1B capture input

Timer TA0.1 output

P1.7 (I/O)

0

1

I: 0; O: 1

P1.7/TA0.2

Timer TA0.CCI2B capture input

Timer TA0.2 output

0

1

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SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

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9.13.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger

Figure 9-3 shows the pin diagram. Table 9-52 summarizes how to select the pin function.

Pad Logic

P2REN.x

DV_SS

DV_CC

0

1

P2DIR.x

0

1

Direction

0: Input

1: Output

From Port Mapping

P2OUT.x

0

1

From Port Mapping

P2.0/P2MAP0

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

P2.6/P2MAP6

P2.7/P2MAP7

P2DS.x

0: Low drive

1: High drive

P2SEL.x

P2IN.x

EN

D

To Port Mapping

P2IRQ.x

P2IE.x

EN

Q

P2IFG.x

Set

P2SEL.x

P2IES.x

Interrupt

Edge

Select

Figure 9-3. Port P2 (P2.0 to P2.7) Diagram

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MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

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SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

Table 9-52. Port P2 (P2.0 to P2.7) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

FUNCTION

PIN NAME (P2.x)

x

0

1

2

3

4

5

6

7

P2DIR.x

P2SEL.x

P2MAPx

P2.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P2.0/P2MAP0

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

P2.6/P2MAP6

P2.7/P2MAP7

Mapped secondary digital function

P2.1 (I/O)

X

≤ 19

I: 0; O: 1

Mapped secondary digital function

P2.2 (I/O)

X

≤ 19

I: 0; O: 1

Mapped secondary digital function

P2.3 (I/O)

X

≤ 19

I: 0; O: 1

Mapped secondary digital function

P2.4 (I/O)

X

≤ 19

I: 0; O: 1

Mapped secondary digital function

P2.5 (I/O

X

≤ 19

I: 0; O: 1

Mapped secondary digital function

P2.6 (I/O)

X

I: 0; O: 1

X

≤ 19

Mapped secondary digital function

P2.7 (I/O)

≤ 19

I: 0; O: 1

X

Mapped secondary digital function

≤ 19

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MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

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9.13.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger

Figure 9-4 shows the pin diagram. Table 9-53 summarizes how to select the pin function.

Pad Logic

P3REN.x

DV_SS

DV_CC

0

1

Direction

0: Input

1: Output

P3DIR.x

P3OUT.x

0

1

Module X OUT

P3.0/TA1CLK/CBOUT

P3.1/TA1.0

P3.2/TA1.1

P3DS.x

0: Low drive

1: High drive

P3SEL.x

P3IN.x

P3.3/TA1.2

P3.4/TA2CLK/SMCLK

P3.5/TA2.0

P3.6/TA2.1

EN

D

P3.7/TA2.2

Module X IN

P3IRQ.x

P3IE.x

EN

Q

P3IFG.x

Set

P3SEL.x

P3IES.x

Interrupt

Edge

Select

Figure 9-4. Port P3 (P3.0 to P3.7) Diagram

88

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SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

Table 9-53. Port P3 (P3.0 to P3.7) Pin Functions

CONTROL BITS OR SIGNALS

FUNCTION

PIN NAME (P3.x)

x

P3DIR.x

P3SEL.x

P3.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P3.0/TA1CLK/CBOUT

P3.1/TA1.0

0

Timer TA1.TA1CLK

CBOUT

0

1

P3.1 (I/O)

I: 0; O: 1

1

2

3

4

5

6

7

Timer TA1.CCI0A capture input

Timer TA1.0 output

P3.2 (I/O)

0

1

I: 0; O: 1

P3.2/TA1.1

Timer TA1.CCI1A capture input

Timer TA1.1 output

P3.3 (I/O)

0

1

I: 0; O: 1

P3.3/TA1.2

Timer TA1.CCI2A capture input

Timer TA1.2 output

P3.4 (I/O)

0

1

I: 0; O: 1

P3.4/TA2CLK/SMCLK

P3.5/TA2.0

Timer TA2.TA2CLK

SMCLK

0

1

P3.5 (I/O)

I: 0; O: 1

Timer TA2.CCI0A capture input

Timer TA2.0 output

P3.6 (I/O)

0

1

I: 0; O: 1

P3.6/TA2.1

Timer TA2.CCI1A capture input

Timer TA2.1 output

P3.7 (I/O)

0

1

I: 0; O: 1

P3.7/TA2.2

Timer TA2.CCI2A capture input

Timer TA2.2 output

0

1

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MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

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9.13.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger

Figure 9-5 shows the pin diagram. Table 9-54 summarizes how to select the pin function.

Pad Logic

P4REN.x

DV_SS

DV_CC

0

1

Direction

0: Input

1: Output

P4DIR.x

P4OUT.x

0

1

Module X OUT

P4.0/TB0.0

P4.1/TB0.1

P4.2/TB0.2

P4.3/TB0.3

P4.4/TB0.4

P4.5/TB0.5

P4.6/TB0.6

P4DS.x

0: Low drive

1: High drive

P4SEL.x

P4IN.x

EN

D

P4.7/TB0OUTH/SVMOUT

Module X IN

P4IRQ.x

P4IE.x

EN

Q

P4IFG.x

Set

P4SEL.x

P4IES.x

Interrupt

Edge

Select

Figure 9-5. Port P4 (P4.0 to P4.7) Diagram

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MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

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SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

Table 9-54. Port P4 (P4.0 to P4.7) Pin Functions

CONTROL BITS OR SIGNALS

FUNCTION

PIN NAME (P4.x)

x

P4DIR.x

P4SEL.x

P4.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P4.0/TB0.0

0

Timer TB0.CCI0A capture input

Timer TB0.0 output⁽¹⁾

P4.1 (I/O)

0

1

I: 0; O: 1

P4.1/TB0.1

1

2

3

4

5

6

7

Timer TB0.CCI1A capture input

Timer TB0.1 output⁽¹⁾

P4.2 (I/O)

0

1

I: 0; O: 1

P4.2/TB0.2

Timer TB0.CCI2A capture input

Timer TB0.2 output⁽¹⁾

P4.3 (I/O)

0

1

I: 0; O: 1

P4.3/TB0.3

Timer TB0.CCI3A capture input

Timer TB0.3 output⁽¹⁾

P4.4 (I/O)

0

1

I: 0; O: 1

P4.4/TB0.4

Timer TB0.CCI4A capture input

Timer TB0.4 output⁽¹⁾

P4.5 (I/O)

0

1

I: 0; O: 1

P4.5/TB0.5

Timer TB0.CCI5A capture input

Timer TB0.5 output⁽¹⁾

P4.6 (I/O)

0

1

I: 0; O: 1

P4.6/TB0.6

Timer TB0.CCI6A capture input

Timer TB0.6 output⁽¹⁾

P4.7 (I/O)

0

1

I: 0; O: 1

P4.7/TB0OUTH/ SVMOUT

Timer TB0.TB0OUTH

SVMOUT

0

1

(1) Setting TB0OUTH causes all Timer_B configured outputs to be set to high impedance.

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MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

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9.13.5 Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger

Figure 9-6 shows the pin diagram. Table 9-55 summarizes how to select the pin function.

Pad Logic

To/From

Reference

P5REN.x

DV_SS

DV_CC

0

1

P5DIR.x

0

1

P5OUT.x

0

1

Module X OUT

P5.0/VREF+/VeREF+

P5.1/VREF–/VeREF–

P5DS.x

0: Low drive

1: High drive

P5SEL.x

P5IN.x

Bus

Keeper

EN

D

Module X IN

Figure 9-6. Port P5 (P5.0 and P5.1) Diagram

Table 9-55. Port P5 (P5.0 and P5.1) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

P5SEL.x

REFOUT

P5.0 (I/O)⁽²⁾

VeREF+⁽³⁾

VREF+⁽⁴⁾

I: 0; O: 1

0

1

0

1

X

0

1

X

0

1

P5.0/VREF+/VeREF+

0

X

P5.1 (I/O)⁽²⁾

VeREF-⁽⁵⁾

VREF-⁽⁶⁾

I: 0; O: 1

P5.1/VREF-/VeREF-

1

X

(1) X = Don't care

(2) Default condition

(3) Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A, Comparator_B, or

DAC12_A.

(4) Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. The ADC12_A VREF+ reference is available at the pin.

(5) Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A, Comparator_B, or

DAC12_A.

(6) Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. The ADC12_A VREF- reference is available at the pin.

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SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

9.13.6 Port P5 (P5.2 to P5.7) Input/Output With Schmitt Trigger

Figure 9-7 shows the pin diagram. Table 9-56 summarizes how to select the pin function.

Pad Logic

P5REN.x

DV_SS

DV_CC

0

1

Direction

0: Input

1: Output

P5DIR.x

P5OUT.x

0

1

Module X OUT

P5.2

P5.3

P5.4

P5.5

P5DS.x

0: Low drive

1: High drive

P5SEL.x

P5IN.x

P5.6/ADC12CLK/DMAE0

P5.7/RTCCLK

EN

D

Module X IN

Figure 9-7. Port P5 (P5.2 to P5.7) Diagram

Table 9-56. Port P5 (P5.2 to P5.7) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

I: 0; O: 1

1

P5SEL.x

P5.2

P5.3

P5.4

P5.5

2

3

4

5

P5.2 (I/O)

P5.3 (I/O)

P5.4 (I/O)

P5.5 (I/O)

P5.6 (I/O)

ADC12CLK

DMAE0

0

1

0

1

P5.6/ADC12CLK/DMAE0

P5.7/RTCCLK

6

7

0

P5.7 (I/O)

RTCCLK

I: 0; O: 1

1

9.13.7 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger

Figure 9-8 shows the pin diagram. Table 9-57 summarizes how to select the pin function.

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MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

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Pad Logic

To ADC12

INCHx = y

0

Dvss

1

2

0 if DAC12AMPx=0

1 if DAC12AMPx=1

2 if DAC12AMPx>1

From DAC12_A

To Comparator_B

From Comparator_B

CBPD.x

DAC12AMPx>0

DAC12OPS

P6REN.x

DV_SS

DV_CC

0

1

P6DIR.x

P6OUT.x

P6.0/CB0/A0

P6.1/CB1/A1

P6.2/CB2/A2

P6.3/CB3/A3

P6.4/CB4/A4

P6.5/CB5/A5

P6DS.x

0: Low drive

1: High drive

P6SEL.x

P6IN.x

P6.6/CB6/A6/DAC0

P6.7/CB7/A7/DAC1

Bus

Keeper

Figure 9-8. Port P6 (P6.0 to P6.7) Diagram

94

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MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

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SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

Table 9-57. Port P6 (P6.0 to P6.7) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

FUNCTION

PIN NAME (P6.x)

x

P6DIR.x

P6SEL.x

CBPD.x

DAC12OPS

DAC12AMPx

P6.0 (I/O)

CB0

I: 0; O: 1

0

X

1

0

X

1

0

X

1

0

X

1

0

X

1

0

X

1

0

X

1

X

0

X

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

n/a

X

n/a

0

P6.0/CB0/A0

P6.1/CB1/A1

P6.2/CB2/A2

P6.3/CB3/A3

P6.4/CB4/A4

P6.5/CB5/A5

0

X

A0^{(1) (2)}

P6.1 (I/O)

CB1

X

I: 0; O: 1

1

2

3

4

5

X

A1^{(1) (2)}

P6.2 (I/O)

CB2

X

I: 0; O: 1

X

A2^{(1) (2)}

P6.3 (I/O)

CB3

X

I: 0; O: 1

X

A3^{(1) (2)}

P6.4 (I/O)

CB4

X

I: 0; O: 1

X

A4^{(1) (2)}

P6.5 (I/O)

CB5

X

I: 0; O: 1

X

A5 ^{(1) (2)}

P6.6 (I/O)

CB6

X

I: 0; O: 1

X

0

P6.6/CB6/A6/DAC0

P6.7/CB7/A7/DAC1

6

7

A6^{(1) (2)}

X

0

DAC0

X

0

>1

0

P6.7 (I/O)

CB7

I: 0; O: 1

X

0

A7^{(1) (2)}

X

0

DAC1

0

>1

(1) Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals.

(2) The ADC12_A channel Ax is connected internally to AV_SSif not selected by the respective INCHx bits.

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MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

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9.13.8 Port P7 (P7.2) Input/Output With Schmitt Trigger

Figure 9-9 shows the pin diagram. Table 9-58 summarizes how to select the pin function.

Pad Logic

To XT2

P7REN.2

DV_SS

DV_CC

0

1

P7DIR.2

P7OUT.2

0

1

P7.2/XT2IN

P7DS.2

0: Low drive

1: High drive

P7SEL.2

P7IN.2

Bus

Keeper

Figure 9-9. Port P7 (P7.2) Diagram

96

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MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

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SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

9.13.9 Port P7 (P7.3) Input/Output With Schmitt Trigger

Figure 9-10 shows the pin diagram. Table 9-58 summarizes how to select the pin function.

Pad Logic

To XT2

P7REN.3

DV_SS

DV_CC

0

1

P7DIR.3

0

1

P7OUT.3

P7SEL.2

P7.3/XT2OUT

P7DS.3

0: Low drive

1: High drive

XT2BYPASS

P7SEL.3

P7IN.3

Bus

Keeper

Figure 9-10. Port P7 (P7.3) Diagram

Table 9-58. Port P7 (P7.2 and P7.3) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PIN NAME (P5.x)

x

FUNCTION

P7DIR.x

P7SEL.2

P7SEL.3

XT2BYPASS

P7.2 (I/O)

I: 0; O: 1

0

1

0

1

X

0

X

0

1

X

0

1

P7.2/XT2IN

2

XT2IN crystal mode⁽¹⁾

XT2IN bypass mode⁽¹⁾

P7.3 (I/O)

X

I: 0; O: 1

P7.3/XT2OUT

3

XT2OUT crystal mode⁽²⁾

P7.3 (I/O)⁽²⁾

X

0

(1) Setting P7SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P7.2 is configured for crystal

mode or bypass mode.

(2) Setting P7SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.3 can be used as

general-purpose I/O.

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MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

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9.13.10 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger

Figure 9-11 shows the pin diagram. Table 9-59 summarizes how to select the pin function.

0

Pad Logic

DVSS

1

2

0 if DAC12AMPx = 0

1 if DAC12AMPx = 1

2 if DAC12AMPx > 1

From DAC12_A

To ADC12

INCHx = y

To Comparator_B

From Comparator_B

CBPD.x

DAC12AMPx>0

DAC12OPS

P7REN.x

P7SEL.x

P7DIR.x

DV_SS

DV_CC

0

1

P7OUT.x

P7.4/CB8/A12

P7.5/CB9/A13

P7.6/CB10/A14/DAC0

P7.7/CB11/A15/DAC1

P7DS.x

0: Low drive

1: High drive

P7IN.x

Bus

Keeper

Figure 9-11. Port P7 (P7.4 to P7.7) Diagram

98

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MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

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SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

Table 9-59. Port P7 (P7.4 to P7.7) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

FUNCTION

PIN NAME (P7.x)

x

P7DIR.x

P7SEL.x

CBPD.x

DAC12OPS

DAC12AMPx

P7.4 (I/O)

I: 0; O: 1

0

X

1

0

X

1

0

X

1

X

0

X

1

X

0

1

X

0

1

X

0

1

X

0

1

X

n/a

X

n/a

0

P7.4/CB8/A12

P7.5/CB9/A13

4

Comparator_B input CB8

A12^{(1) (2)}

X

P7.5 (I/O)

I: 0; O: 1

5

6

Comparator_B input CB9

A13^{(1) (2)}

X

P7.6 (I/O)

I: 0; O: 1

Comparator_B input CB10

A14^{(1) (2)}

X

0

P7.6/CB10/A14/DAC0

P7.7/CB11/A15/DAC1

X

0

DAC12_A output DAC0

P7.7 (I/O)

X

1

>1

0

I: 0; O: 1

X

Comparator_B input CB11

A15^{(1) (2)}

X

0

7

X

0

DAC12_A output DAC1

1

>1

(1) Setting the P7SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals.

(2) The ADC12_A channel Ax is connected internally to AV_SSif not selected by the respective INCHx bits.

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MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

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9.13.11 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger

Figure 9-12 shows the pin diagram. Table 9-60 summarizes how to select the pin function.

Pad Logic

P8REN.x

DV_SS

DV_CC

0

1

P8DIR.x

0

1

Direction

0: Input

1: Output

From module

0

1

P8OUT.x

Module X OUT

P8.0/TB0CLK

P8DS.x

0: Low drive

1: High drive

P8.1/UCB1STE/UCA1CLK

P8.2/UCA1TXD/UCA1SIMO

P8.3/UCA1RXD/UCA1SOMI

P8.4/UCB1CLK/UCA1STE

P8.5/UCB1SIMO//UCB1SDA

P8.6/UCB1SOMI/UCB1SCL

P8.7

P8SEL.x

P8IN.x

EN

D

Module X IN

Figure 9-12. Port P8 (P8.0 to P8.7) Diagram

Table 9-60. Port P8 (P8.0 to P8.7) Pin Functions

CONTROL BITS OR

SIGNALS⁽¹⁾

PIN NAME (P9.x)

x

FUNCTION

P8DIR.x

P8SEL.x

P8.0 (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

P8.0/TB0CLK

0

1

2

3

4

5

Timer TB0.TB0CLK clock input

P8.1 (I/O)

0

I: 0; O: 1

X

P8.1/UCB1STE/UCA1CLK

P8.2/UCA1TXD/UCA1SIMO

P8.3/UCA1RXD/UCA1SOMI

P8.4/UCB1CLK/UCA1STE

P8.5/UCB1SIMO/UCB1SDA

UCB1STE/UCA1CLK

P8.2 (I/O)

I: 0; O: 1

X

UCA1TXD/UCA1SIMO

P8.3 (I/O)

I: 0; O: 1

X

UCA1RXD/UCA1SOMI

P8.4 (I/O)

I: 0; O: 1

X

UCB1CLK/UCA1STE

P8.5 (I/O)

I: 0; O: 1

X

UCB1SIMO/UCB1SDA

P8.6 (I/O)

I: 0; O: 1

X

P8.6/UCB1SOMI/UCB1SCL

P8.7

6

7

UCB1SOMI/UCB1SCL

P8.7 (I/O)

I: 0; O: 1

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SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

9.13.12 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger

Figure 9-13 shows the pin diagram. Table 9-61 summarizes how to select the pin function.

Pad Logic

P9REN.x

0

1

DV_SS

DV_CC

1

Direction

0: Input

1: Output

P9DIR.x

P9OUT.x

P9.0

P9.1

P9.2

P9.3

P9.4

P9.5

P9.6

P9.7

P9DS.x

0: Low drive

1: High drive

P9IN.x

Figure 9-13. Port P9 (P9.0 to P9.7) Diagram

Table 9-61. Port P9 (P9.0 to P9.7) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P9.x)

x

FUNCTION

P9DIR.x

I: 0; O: 1

P9SEL.x

P9.0

0

1

2

3

4

5

6

7

P9.0 (I/O)

P9.1 (I/O)

P9.2 (I/O)

P9.3 (I/O)

P9.4 (I/O)

P9.5 (I/O)

P9.6 (I/O)

P9.7 (I/O)

0

P9.1

P9.2

P9.3

P9.4

P9.5

P9.6

P9.7

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MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

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9.13.13 Port PU (PU.0/DP, PU.1/DM, PUR) USB Ports

Figure 9-14 shows the pin diagram. Table 9-62 summarizes how to select the pin function.

PUSEL

VUSB

VSSU

Pad Logic

PUOPE

0

1

USB output enable

PUOUT0

0

1

PU.0/DP

USB DP output

PUIN0

USB DP input

PUIPE

PUIN1

USB DM input

PUOUT1

0

1

PU.1/DM

USB DM output

VUSB

VSSU

Pad Logic

PUREN

PUR

“1”

PUSEL

PURIN

Figure 9-14. Port PU (PU.0 and PU.1) Diagram

Table 9-62. Port PU.0/DP and PU.1/DM Output Functions

CONTROL BITS

PIN NAME

FUNCTION

PUSEL

PUDIR

PUOUT1

PUOUT0

PU.1/DM

PU.0/DP

0

1

0

1

X

0

1

X

0

1

0

1

X

Hi-Z

0

Hi-Z

0

Outputs off

Outputs enabled

0

1

0

1

DM

DP

Direction set by USB module

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SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

Table 9-63. Port PUR Input Functions

CONTROL BITS

FUNCTION

PUSEL

PUREN

Input disabled

Pullup disabled

0

1

0

Input disabled

Pullup enabled

1

0

1

Input enabled

Pullup disabled

Input enabled

Pullup enabled

9.13.14 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output

Figure 9-15 shows the pin diagram. Table 9-64 summarizes how to select the pin function.

Pad Logic

PJREN.0

0

1

DV_SS

DV_CC

1

PJDIR.0

DVCC

0

1

PJOUT.0

0

1

From JTAG

PJ.0/TDO

PJDS.0

0: Low drive

1: High drive

From JTAG

PJIN.0

EN

D

Figure 9-15. Port J (PJ.0) Diagram

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MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

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9.13.15 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or

Output

Figure 9-16 shows the pin diagram. Table 9-64 summarizes how to select the pin function.

Pad Logic

PJREN.x

0

1

DV_SS

DV_CC

1

PJDIR.x

DVSS

0

1

PJOUT.x

0

1

From JTAG

PJ.1/TDI/TCLK

PJ.2/TMS

PJ.3/TCK

PJDS.x

0: Low drive

1: High drive

From JTAG

PJIN.x

EN

D

To JTAG

Figure 9-16. Port PJ (PJ.1 to PJ.3) Diagram

Table 9-64. Port PJ (PJ.0 to PJ.3) Pin Functions

CONTROL BITS

OR SIGNALS⁽¹⁾

PIN NAME (PJ.x)

x

FUNCTION

PJDIR.x

I: 0; O: 1

X

PJ.0 (I/O)⁽¹⁾

PJ.0/TDO

0

1

2

3

TDO⁽²⁾

PJ.1 (I/O)⁽¹⁾

TDI/TCLK^{(2) (3)}

PJ.2 (I/O)⁽¹⁾

TMS^{(2) (3)}

I: 0; O: 1

X

PJ.1/TDI/TCLK

PJ.2/TMS

I: 0; O: 1

X

PJ.3 (I/O)⁽¹⁾

TCK^{(2) (3)}

I: 0; O: 1

X

PJ.3/TCK

(1) Default condition

(2) The pin direction is controlled by the JTAG module.

(3) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.

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SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

9.14 Device Descriptors

Table 9-65 list the contents of the device descriptor tag-length-value (TLV) structure.

Table 9-65. MSP430F563x Device Descriptor Table

VALUE

SIZE

(bytes)

DESCRIPTION⁽¹⁾

Info length

ADDRESS

F5638

06h

F5637

06h

F5636

06h

F5635

06h

F5634

06h

F5633

06h

F5632

06h

F5631

06h

F5630

06h

01A00h

01A01h

01A02h

01A04h

01A06h

01A07h

01A08h

01A09h

01A0Ah

01A0Eh

01A10h

01A12h

01A14h

01A15h

01A16h

01A18h

1

2

1

4

2

1

2

CRC length

CRC value

06h

Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit

8014h 8012h 8010h 800Eh 8044h 8042h 8040h 803Eh 803Ch

Info Block

Device ID

Hardware revision

Firmware revision

Die record tag

Die record length

Lot/wafer ID

Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit

08h

0Ah

08h

0Ah

08h

0Ah

08h

0Ah

08h

0Ah

08h

0Ah

08h

0Ah

08h

0Ah

08h

0Ah

Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit

Die Record

Die X position

Die Y position

Test results

ADC12 calibration tag

ADC12 calibration length

ADC gain factor

ADC offset

11h

10h

11h

10h

11h

10h

11h

10h

11h

10h

11h

10h

11h

10h

11h

10h

11h

10h

Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit

ADC 1.5-V reference

temp. l 30°C

01A1Ah

01A1Ch

01A1Eh

01A20h

01A22h

01A24h

2

Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit

ADC 1.5-V reference

Temperature sensor 85°C

ADC12

Calibration

ADC 2.0-V reference

Temperature sensor 30°C

ADC 2.0-V reference

Temperature sensor 85°C

ADC 2.5-V reference

Temperature sensor 30°C

ADC 2.5-V reference

Temperature sensor 85°C

(1) NA = Not applicable

Submit Document Feedback 105

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634

MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

www.ti.com

10 Device and Documentation Support

10.1 Getting Started and Next Steps

For more information on the MSP430^™family of devices and the tools and libraries that are available to help with

your development, visit the MSP430 ultra-low-power sensing & measurement MCUs overview.

10.2 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP

MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These

prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully

qualified production devices (MSP).

XMS – Experimental device that is not necessarily representative of the final device's electrical specifications

MSP – Fully qualified production device

XMS devices are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated

fully. TI's standard warranty applies.

Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.

TI recommends that these devices not be used in any production system because their expected end-use failure

rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature

range, package type, and distribution format. Figure 10-1 provides a legend for reading the complete device

name.

106 Submit Document Feedback

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

MSP 430 F 5 438 A I PM T -EP

Processor Family

MCU Platform

Device Type

Series

Feature Set

Optional: Additional Features

Optional: Tape and Reel

Packaging

Optional: Temperature Range

Optional: Revision

Processor Family

CC = Embedded RF Radio

MSP = Mixed-Signal Processor

XMS = Experimental Silicon

PMS = Prototype Device

MCU Platform

Device Type

430 = MSP430 low-power microcontroller platform

Memory Type

C = ROM

F = Flash

FR = FRAM

G = Flash

L = No nonvolatile memory

Specialized Application

AFE = Analog front end

BQ = Contactless power

CG = ROM medical

FE = Flash energy meter

FG = Flash medical

FW = Flash electronic flow meter

Series

1 = Up to 8 MHz

2 = Up to 16 MHz

3 = Legacy

4 = Up to 16 MHz with LCD driver

5 = Up to 25 MHz

6 = Up to 25 MHz with LCD driver

0 = Low-voltage series

Feature Set

Various levels of integration within a series

Updated version of the base part number

Optional: Revision

Optional: Temperature Range S = 0°C to 50°C

C = 0°C to 70°C

I = –40°C to 85°C

T = –40°C to 105°C

Packaging

http://www.ti.com/packaging

Optional: Tape and Reel

T = Small reel

R = Large reel

No markings = Tube or tray

Optional: Additional Features -EP = Enhanced product (–40°C to 105°C)

-HT = Extreme temperature parts (–55°C to 150°C)

-Q1 = Automotive Q100 qualified

Figure 10-1. Device Nomenclature

Submit Document Feedback 107

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

www.ti.com

10.3 Tools and Software

All MSP microcontrollers are supported by a wide variety of software and hardware development tools. Tools are

available from TI and various third parties. See them all at MSP430 ultra-low-power MCUs – Design &

development.

Table 10-1 lists the debug features of the MSP430F563x MCUs. See the Code Composer Studio™ IDE for

MSP430™ MCUs User's Guide for details on the available features.

Table 10-1. Hardware Debug Features

BREAK-

POINTS

(N)

RANGE

BREAK-

POINTS

LPMx.5

DEBUGGING

SUPPORT

MSP430

ARCHITECTURE

4-WIRE

JTAG

2-WIRE

JTAG

CLOCK

CONTROL SEQUENCER

STATE

TRACE

BUFFER

MSP430Xv2

Yes

8

Yes

No

Design Kits and Evaluation Modules

MSP-TS430PZ100USB - 100-pin Target Development Board for MSP430F5x and MSP430F6x MCUs

The MSP-TS430PZ100USB is a stand-alone 100-pin ZIF socket target board used to program and debug the

MSP430 MCU in-system through the JTAG interface or the Spy Bi-Wire (2-wire JTAG) protocol.

100-pin Target Development Board and MSP-FET Programmer Bundle for MSP430F5x and MSP430F6x MCUs

The MSP-FET is a powerful flash emulation tool to quickly begin application development on the MSP430 MCU.

It includes USB debugging interface used to program and debug the MSP430 in-system through the JTAG

interface or the pin saving Spy Bi-Wire (2-wire JTAG) protocol. The flash memory can be erased and

programmed in seconds with only a few keystrokes, and because the MSP430 flash is ultra-low power, no

external power supply is required.

Software

MSP430Ware^™Software

MSP430Ware software is a collection of code examples, data sheets, and other design resources for all

MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing

MSP430 design resources, MSP430Ware software also includes a high-level API called MSP430 Driver Library.

This library makes it easy to program MSP430 hardware. MSP430Ware software is available as a component of

CCS or as a stand-alone package.

MSP430F563x, MSP430F663x Code Examples

C code examples are available for every MSP device that configures each of the integrated peripherals for

various application needs.

MSP Driver Library

Driver Library's abstracted API keeps you above the bits and bytes of the MSP430 hardware by providing easy-

to-use function calls. Thorough documentation is delivered through a helpful API Guide, which includes details

on each function call and the recognized parameters. Developers can use Driver Library functions to write

complete projects with minimal overhead.

MSP EnergyTrace^™Technology

EnergyTrace technology for MSP430 microcontrollers is an energy-based code analysis tool that measures and

displays the application's energy profile and helps to optimize it for ultra-low-power consumption.

108 Submit Document Feedback

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

ULP (Ultra-Low Power) Advisor

ULP Advisor^™software is a tool for guiding developers to write more efficient code to fully utilize the unique

ultra-low power features of MSP and MSP432 microcontrollers. Aimed at both experienced and new

microcontroller developers, ULP Advisor checks your code against a thorough ULP checklist to squeeze every

last nano amp out of your application. At build time, ULP Advisor will provide notifications and remarks to

highlight areas of your code that can be further optimized for lower power.

IEC 60730 Software Package

The IEC 60730 MSP430 software package was developed to be useful in assisting customers in complying with

IEC 60730-1:2010 (Automatic Electrical Controls for Household and Similar Use – Part 1: General

Requirements) for up to Class B products, which includes home appliances, arc detectors, power converters,

power tools, e-bikes, and many others. The IEC 60730 MSP430 software package can be embedded in

customer applications running on MSP430s to help simplify the customer’s certification efforts of functional

safety-compliant consumer devices to IEC 60730-1:2010 Class B.

Fixed Point Math Library for MSP

The MSP IQmath and Qmath Libraries are a collection of highly optimized and high-precision mathematical

functions for C programmers to seamlessly port a floating-point algorithm into fixed-point code on MSP430

MCUs. These routines are typically used in computationally intensive real-time applications where optimal

execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and Qmath libraries, it is

possible to achieve execution speeds considerably faster and energy consumption considerably lower than

equivalent code written using floating-point math.

Floating Point Math Library for MSP430

Continuing to innovate in the low-power and low-cost microcontroller space, TI brings you MSPMATHLIB.

Leveraging the intelligent peripherals of our devices, this floating point math library of scalar functions brings you

up to 26x better performance. Mathlib is easy to integrate into your designs. This library is free and is integrated

in both Code Composer Studio and IAR IDEs. Read the user’s guide for an in depth look at the math library and

relevant benchmarks.

Development Tools

Code Composer Studio^™Integrated Development Environment for MSP Microcontrollers

The Code Composer Studio integrated development environment (IDE) supports all MSP microcontroller

devices. The Code Composer Studio IDE comprises a suite of embedded software utilities used to develop and

debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build

environment, debugger, profiler, and many other features. The intuitive IDE provides a single user interface

taking you through each step of the application development flow. Familiar utilities and interfaces allow users to

get started faster than ever before. The Code Composer Studio IDE combines the advantages of the Eclipse

software framework with advanced embedded debug capabilities from TI resulting in a compelling feature-rich

development environment for embedded developers. When using the Code Composer Studio IDE with an

MSP430 MCU, a unique and powerful set of plugins and embedded software utilities are made available to fully

leverage the MSP430 microcontroller.

Command-Line Programmer

MSP Flasher is an open-source shell-based interface for programming MSP microcontrollers through a FET

programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can download binary

files (.txt or .hex) files directly to the MSP microcontroller without an IDE.

Submit Document Feedback 109

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

www.ti.com

MSP MCU Programmer and Debugger

The MSP-FET is a powerful emulation development tool – often called a debug probe – that lets users quickly

begin application development on MSP low-power microcontrollers (MCU). Creating MCU software usually

requires downloading the resulting binary program to the MSP device for validation and debugging. The MSP-

FET provides a debug communication pathway between a host computer and the target MSP. Furthermore, the

MSP-FET also provides a Backchannel UART connection between the computer's USB interface and the MSP

UART. This gives the MSP programmer a convenient method to communicate serially between the MSP and a

terminal running on the computer. It also supports loading programs (often called firmware) to the MSP target

using the BSL (bootloader) through the UART and I²C communication protocols.

MSP-GANG Production Programmer

The MSP Gang Programmer is a device programmer that can program up to eight identical MSP430 or MSP432

flash or FRAM devices at the same time. The MSP Gang Programmer connects to a host PC using a standard

RS-232 or USB connection and provides flexible programming options that allow the user to fully customize the

process. The MSP Gang Programmer is provided with an expansion board, called the Gang Splitter, that

implements the interconnections between the MSP Gang Programmer and multiple target devices. Eight cables

are provided that connect the expansion board to eight target devices (through JTAG or Spy-Bi-Wire

connectors). The programming can be done with a PC or as a stand-alone device. A PC-side graphical user

interface is also available and is DLL-based.

10.4 Documentation Support

The following documents describe the MSP430F563x MCUs. Copies of these documents are available on the

Internet at www.ti.com.

Receiving Notification of Document Updates

To receive notification of documentation updates—including silicon errata—go to the product folder for your

device on ti.com (for links to the product folders, see Section 10.5). In the upper right corner, click the "Alert me"

button. This registers you to receive a weekly digest of product information that has changed (if any). For change

details, check the revision history of any revised document.

Errata

MSP430F5638 Device Erratasheet

Describes the known exceptions to the functional specifications for this device.

MSP430F5637 Device Erratasheet

Describes the known exceptions to the functional specifications for this device.

MSP430F5636 Device Erratasheet

Describes the known exceptions to the functional specifications for this device.

MSP430F5635 Device Erratasheet

Describes the known exceptions to the functional specifications for this device.

MSP430F5634 Device Erratasheet

Describes the known exceptions to the functional specifications for this device.

MSP430F5633 Device Erratasheet

Describes the known exceptions to the functional specifications for this device.

MSP430F5632 Device Erratasheet

Describes the known exceptions to the functional specifications for this device.

110

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Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634

MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

MSP430F5631 Device Erratasheet

Describes the known exceptions to the functional specifications for this device.

MSP430F5630 Device Erratasheet

Describes the known exceptions to the functional specifications for this device.

User's Guides

MSP430x5xx and MSP430x6xx Family User's Guide

Detailed information on the modules and peripherals available in this device family.

IAR Embedded Workbench IDE for MSP430 MCUs User's Guide

This manual describes the use of IAR Embedded Workbench (EW430) with the MSP430 ultra-low-power

microcontrollers.

MSP430™ Flash Devices Bootloader (BSL) User's Guide

The MSP430 BSL lets users communicate with embedded memory in the MSP430 microcontroller during the

prototyping phase, final production, and in service. Both the programmable memory (flash memory) and the data

memory (RAM) can be modified as required. Do not confuse the bootloader with the bootstrap loader programs

found in some digital signal processors (DSPs) that automatically load program code (and data) from external

memory to the internal memory of the DSP.

MSP430 Programming With the JTAG Interface

This document describes the functions that are required to erase, program, and verify the memory module of the

MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition,

it describes how to program the JTAG access security fuse that is available on all MSP430 devices. This

document describes device access using both the standard 4-wire JTAG interface and the 2-wire JTAG

interface, which is also referred to as Spy-Bi-Wire (SBW).

MSP430 Hardware Tools User's Guide

This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the

program development tool for the MSP430 ultra-low-power microcontroller. Both available interface types, the

parallel port interface and the USB interface, are described.

Application Reports

MSP430 32-kHz Crystal Oscillators

Selection of the right crystal, correct load circuit, and proper board layout are important for a stable crystal

oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the

correct crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout

are given. The document also contains detailed information on the possible oscillator tests to ensure stable

oscillator operation in mass production.

MSP430 System-Level ESD Considerations

System-level ESD has become increasingly demanding with silicon technology scaling towards lower voltages

and the need for designing cost-effective and ultra-low-power components. This application report addresses

three different ESD topics to help board designers and OEMs understand and design robust system-level

designs.

Submit Document Feedback

111

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634

MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

www.ti.com

10.5 Related Links

Table 10-2 lists quick access links. Categories include technical documents, support and community resources,

tools and software, and quick access to sample or buy.

Table 10-2. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

ORDER NOW

MSP430F5638

MSP430F5637

MSP430F5636

MSP430F5635

MSP430F5634

MSP430F5633

MSP430F5632

MSP430F5631

MSP430F5630

Click here

10.6 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

10.7 Trademarks

MSP430^™, MicroStar Junior^™, MSP430Ware^™, EnergyTrace^™, ULP Advisor^™, Code Composer Studio^™, and TI

E2E^™are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

10.8 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

10.9 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as

defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled

product restricted by other applicable national regulations, received from disclosing party under nondisclosure

obligations (if any), or any direct product of such technology, to any destination to which such export or re-export

is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.

Department of Commerce and other competent Government authorities to the extent required by those laws.

10.10 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

112

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Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634

MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

113

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634

MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

PACKAGE MATERIALS INFORMATION

www.ti.com

13-Sep-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

MSP430F5630IZQWR BGA MI

ZQW

113

2500

330.0

16.4

7.3

1.5

12.0

16.0

Q1

CROSTA

R JUNI

OR

MSP430F5630IZQWT BGA MI

ZQW

113

250

180.0

16.4

7.3

1.5

12.0

16.0

Q1

CROSTA

R JUNI

OR

MSP430F5632IPZR

MSP430F5632IZCAR

LQFP

PZ

100

113

1000

2500

330.0

24.4

16.4

17.0

7.3

17.0

7.3

2.1

1.5

20.0

12.0

24.0

16.0

Q2

Q1

NFBGA

ZCA

ZQW

MSP430F5632IZQWR BGA MI

7.3

CROSTA

R JUNI

OR

MSP430F5633IPZR

LQFP

PZ

100

113

1000

2500

330.0

24.4

16.4

17.0

7.3

17.0

7.3

2.1

1.5

20.0

12.0

24.0

16.0

Q2

Q1

MSP430F5633IZQWR BGA MI

ZQW

CROSTA

R JUNI

OR

MSP430F5633IZQWT BGA MI

ZQW

113

250

180.0

16.4

7.3

1.5

12.0

16.0

Q1

CROSTA

R JUNI

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

13-Sep-2020

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

OR

MSP430F5634IZQWT BGA MI

ZQW

113

250

180.0

16.4

7.3

1.5

12.0

16.0

Q1

CROSTA

R JUNI

OR

MSP430F5635IPZR

MSP430F5635IZCAR

MSP430F5635IZCAT

LQFP

NFBGA

PZ

100

113

1000

2500

250

330.0

180.0

330.0

24.4

16.4

17.0

7.3

17.0

7.3

2.1

1.5

20.0

12.0

24.0

16.0

Q2

Q1

ZCA

ZQW

MSP430F5635IZQWR BGA MI

2500

CROSTA

R JUNI

OR

MSP430F5635IZQWT BGA MI

ZQW

113

250

180.0

16.4

7.3

1.5

12.0

16.0

Q1

CROSTA

R JUNI

OR

MSP430F5637IPZR

MSP430F5638IZCAR

MSP430F5638IZCAT

LQFP

NFBGA

PZ

100

113

1000

2500

250

330.0

180.0

330.0

24.4

16.4

17.0

7.3

17.0

7.3

2.1

1.5

20.0

12.0

24.0

16.0

Q2

Q1

ZCA

ZQW

MSP430F5638IZQWR BGA MI

2500

CROSTA

R JUNI

OR

MSP430F5638IZQWT BGA MI

ZQW

113

250

180.0

16.4

7.3

1.5

12.0

16.0

Q1

CROSTA

R JUNI

OR

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

13-Sep-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

MSP430F5630IZQWR BGA MICROSTAR

JUNIOR

ZQW

113

2500

350.0

43.0

MSP430F5630IZQWT BGA MICROSTAR

JUNIOR

ZQW

113

250

213.0

191.0

55.0

MSP430F5632IPZR

MSP430F5632IZCAR

LQFP

PZ

100

113

1000

2500

350.0

43.0

NFBGA

ZCA

ZQW

MSP430F5632IZQWR BGA MICROSTAR

JUNIOR

MSP430F5633IPZR

LQFP

PZ

100

113

1000

2500

350.0

43.0

MSP430F5633IZQWR BGA MICROSTAR

JUNIOR

ZQW

MSP430F5633IZQWT BGA MICROSTAR

JUNIOR

ZQW

113

250

213.0

191.0

55.0

MSP430F5634IZQWT BGA MICROSTAR

JUNIOR

MSP430F5635IPZR

MSP430F5635IZCAR

MSP430F5635IZCAT

LQFP

NFBGA

PZ

100

113

1000

2500

250

350.0

213.0

350.0

191.0

350.0

43.0

55.0

43.0

ZCA

ZQW

MSP430F5635IZQWR BGA MICROSTAR

JUNIOR

2500

MSP430F5635IZQWT BGA MICROSTAR

JUNIOR

ZQW

PZ

113

100

250

213.0

350.0

191.0

350.0

55.0

43.0

MSP430F5637IPZR

LQFP

1000

Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

13-Sep-2020

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

MSP430F5638IZCAR

MSP430F5638IZCAT

NFBGA

ZCA

ZQW

113

2500

250

350.0

213.0

350.0

191.0

350.0

43.0

55.0

43.0

MSP430F5638IZQWR BGA MICROSTAR

JUNIOR

2500

MSP430F5638IZQWT BGA MICROSTAR

JUNIOR

ZQW

113

250

213.0

191.0

55.0

Pack Materials-Page 4

PACKAGE OUTLINE

NFBGA - 1 mm max height

PLASTIC BALL GRID ARRAY

ZCA0113A

A

7.1

6.9

B

BALL A1 CORNER

7.1

6.9

1 MAX

C

SEATING PLANE

0.08 C

0.25

0.15

BALL TYP

5.5

TYP

(0.75) TYP

SYMM

M

L

K

J

(0.75) TYP

H

G

F

E

D

C

SYMM

5.5

TYP

0.35

0.25

113X Ø

B

A

0.15

0.05

C

A B

1

2

3

4

5

6

7

8

9 10 11 12

0.5 TYP

4225149/A 08/2019

NanoFree is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

NFBGA - 1 mm max height

PLASTIC BALL GRID ARRAY

ZCA0113A

(0.5) TYP

1

2

3

4

5

6

7

8

9

10 11 12

A

B

C

D

E

F

113X (Ø0.25)

SYMM

G

H

J

K

L

M

SYMM

LAND PATTERN EXAMPLE

SCALE: 10X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

EXPOSED

METAL

(Ø 0.25)

METAL

(Ø 0.25)

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON- SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4225149/A 08/2019

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments

Literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com

EXAMPLE STENCIL DESIGN

NFBGA - 1 mm max height

PLASTIC BALL GRID ARRAY

ZCA0113A

(0.5) TYP

1

2

3

4

5

6

7

8

9

10 11 12

A

B

C

D

E

F

(R0.05)

SYMM

G

H

J

METAL TYP

113X ( 0.25)

K

L

M

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.100 mm THICK STENCIL

SCALE: 10X

4225149/A 08/2019

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

MECHANICAL DATA

MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996

PZ (S-PQFP-G100)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

75

M

0,08

51

50

76

26

100

0,13 NOM

1

25

12,00 TYP

Gage Plane

14,20

SQ

13,80

0,25

16,20

SQ

0,05 MIN

0°–7°

15,80

1,45

1,35

0,75

0,45

Seating Plane

0,08

1,60 MAX

4040149/B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,

damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	MSP430F5635IZCAT
厂家：	TEXAS INSTRUMENTS
描述：	MSP430F563x Mixed-Signal Microcontrollers 微控制器
文件：	总127页 (文件大小：3489K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MSP430F5635IZCAT [TI]

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