MSP430F6659IPZR [TI]
MSP430F665x, MSP430F645x, MSP430F565x, MSP430F535x Mixed-Signal Microcontrollers;
| 型号： | MSP430F6659IPZR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MSP430F665x, MSP430F645x, MSP430F565x, MSP430F535x Mixed-Signal Microcontrollers 微控制器 |
| 文件： | 总144页 (文件大小：3707K) |
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MSP430F6659, MSP430F6658, MSP430F6459, MSP430F6458
MSP430F5659, MSP430F5658,MSP430F5359, MSP430F5358
SLAS700E – OCTOBER 2012 – REVISED SEPTEMBER 2020
MSP430F665x, MSP430F645x, MSP430F565x, MSP430F535x Mixed-Signal
Microcontrollers
– USCI_A0, USCI_A1, and USCI_A2 each
1 Features
support:
•
Low supply voltage range:
3.6 V down to 1.8 V
•
Enhanced UART with automatic baud-rate
detection
•
Ultra-low power consumption
– Active mode (AM):
•
•
IrDA encoder and decoder
Synchronous SPI
All system clocks active:
295 µA/MHz at 8 MHz, 3.0 V, flash program
execution (typical)
– USCI_B0, USCI_B1, and USCI_B2 each
support:
•
•
I2C
– Standby mode (LPM3):
Synchronous SPI
Watchdog with crystal, and supply supervisor
operational, full RAM retention, fast wakeup:
2.0 µA at 2.2 V, 2.2 µA at 3.0 V (typical)
– Shutdown, real-time clock (RTC) mode
(LPM3.5):
•
Full-speed universal serial bus (USB)
– Integrated USB-PHY
– Integrated 3.3-V and 1.8-V USB power system
– Integrated USB-PLL
– Eight input and eight output endpoints
12-bit analog-to-digital converter (ADC) with
internal shared reference, sample-and-hold, and
autoscan feature
Two 12-bit digital-to-analog converters (DACs) with
synchronization
Voltage comparator
Integrated LCD driver with contrast control for up
to 160 segments
Shutdown mode, active RTC with crystal:
1.1 µA at 3.0 V (typical)
– Shutdown mode (LPM4.5):
0.45 µA at 3.0 V (typical)
Wake up from standby mode in 3 µs (typical)
16-bit RISC architecture, extended memory, up to
20-MHz system clock
Flexible power-management system
– Fully integrated LDO with programmable
regulated core supply voltage
– Supply voltage supervision, monitoring, and
brownout
•
•
•
•
•
•
•
•
•
Hardware multiplier supports 32-bit operations
Serial onboard programming, no external
programming voltage needed
•
•
•
6-channel internal DMA
•
Unified clock system
RTC module with supply voltage backup switch
Device Comparison summarizes the available
family members
– FLL control loop for frequency stabilization
– Low-power low-frequency internal clock source
(VLO)
– Low-frequency trimmed internal reference
source (REFO)
– 32-kHz crystals (XT1)
– High-frequency crystals up to 32 MHz (XT2)
Four 16-bit timers with 3, 5, or 7 capture/compare
registers
Three universal serial communication interfaces
(USCIs)
2 Applications
•
•
•
•
•
•
Analog and digital sensor systems
Digital motor controls
Remote controls
Thermostats
Digital timers
•
•
Hand-held meters
3 Description
The TI MSP family of ultra-low-power microcontrollers consists of several devices that feature different sets of
peripherals targeted for various applications. The architecture, combined with five low-power modes, is
optimized to achieve extended battery life in portable measurement applications. The device features a powerful
16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The
digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active mode in 3 µs
(typical).
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430F6659, MSP430F6658, MSP430F6459, MSP430F6458
MSP430F5659, MSP430F5658, MSP430F5359, MSP430F5358
SLAS700E – OCTOBER 2012 – REVISED SEPTEMBER 2020
www.ti.com
The MSP430F665x and MSP430F565x series are microcontroller configurations with four 16-bit timers, a high-
performance 12-bit ADC, three USCIs, a hardware multiplier, DMA, an RTC module with alarm capabilities, a
comparator, USB 2.0, and up to 74 I/O pins.
The MSP430F645x and MSP430F535x series are microcontroller configurations with an integrated 3.3-V LDO,
four 16-bit timers, a high-performance 12-bit ADC, three USCIs, a hardware multiplier, DMA, an RTC module
with alarm capabilities, a comparator, and up to 74 I/O pins.
For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide.
Device Information
PART NUMBER(1)
MSP430F6659IPZ
PACKAGE
BODY SIZE(2)
14 mm × 14 mm
7 mm × 7 mm
7 mm × 7 mm
LQFP (100)
MSP430F6659IZCA
nFBGA (113)
MSP430F6659IZQW(3)
MicroStar Junior™ BGA (113)
(1) For the most current device, package, and ordering information, see the Package Option Addendum in Section 11, or see the TI
website at www.ti.com.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 11.
(3) All orderable part numbers in the ZQW (MicroStar Junior BGA) package have been changed to a status of Last Time Buy. Visit the
Product life cycle page for details on this status.
Copyright © 2020 Texas Instruments Incorporated
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Product Folder Links: MSP430F6659 MSP430F6658 MSP430F6459 MSP430F6458 MSP430F5659
MSP430F5658 MSP430F5359 MSP430F5358
MSP430F6659, MSP430F6658, MSP430F6459, MSP430F6458
MSP430F5659, MSP430F5658, MSP430F5359, MSP430F5358
www.ti.com
SLAS700E – OCTOBER 2012 – REVISED SEPTEMBER 2020
4 Functional Block Diagrams
Figure 4-1 shows the functional block diagram for the MSP430F6659 and MSP430F6658 MCUs.
PA
PB
PC
PD
XIN XOUT
DVCC DVSS
AVCC AVSS
RST/NMI
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x
P9.x
XT2IN
64KB
32KB
RAM
I/O Ports
P1, P2
2×8 I/Os
Interrupt
Capability
I/O Ports
P3, P4
2×8 I/Os
Interrupt
Capability
I/O Ports
P5, P6
2×8 I/Os
USCI0,
USCI1,
USCI2
I/O Ports
P7, P8
1×6 I/Os
1×8 I/Os
ACLK
SMCLK
SYS
Power
Management
I/O Ports
P9
1×8 I/Os
Unified
Clock
System
USB
512KB
384KB
MID
XT2OUT
Watchdog
Full-speed
Memory
Integrity
Detection
+2KB RAM
USB Buffer
Ax: UART,
IrDA, SPI
P2 Port
Mapping
Controller
LDO,
SVM, SVS,
Brownout
PE
1×8 I/Os
Flash
MCLK
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
PD
1×14 I/Os
Bx: SPI, I2C
+8B Backup
RAM
CPUXV2
and
Working
Registers
EEM
(L: 8+2)
DMA
ADC12_A
TA1, TA2
RTC_B
6 Channel
TA0
TB0
DAC12_A
REF
LCD_B
12 bit
JTAG,
SBW
Interface
2 Timer_A
each with
3 CC
200 ksps
Timer_A
5 CC
Registers
Timer_B
7 CC
Registers
Comp_B
12 bit
2 channels
voltage out
MPY32
CRC16
Reference
1.5 V, 2.0 V,
2.5 V
160
Segments
Battery
Backup
System
16 channels
(12 ext, 4 int)
Autoscan
Registers
Port PJ
Functional Block Diagram – MSP430F6659, MSP430F6658
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Product Folder Links: MSP430F6659 MSP430F6658 MSP430F6459 MSP430F6458 MSP430F5659
MSP430F5658 MSP430F5359 MSP430F5358
MSP430F6659, MSP430F6658, MSP430F6459, MSP430F6458
MSP430F5659, MSP430F5658, MSP430F5359, MSP430F5358
SLAS700E – OCTOBER 2012 – REVISED SEPTEMBER 2020
www.ti.com
Figure 4-1 shows the functional block diagram for the MSP430F6459 and MSP430F6458 MCUs
PA
PB
PC
PD
PU.0
PU.1
XIN XOUT
DVCC DVSS
AVCC AVSS
RST/NMI
LDOO LDOI
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x
P9.x
XT2IN
64KB
32KB
RAM
I/O Ports
P1, P2
2×8 I/Os
Interrupt
Capability
I/O Ports
P3, P4
2×8 I/Os
Interrupt
Capability
I/O Ports
P5, P6
2×8 I/Os
USCI0,
USCI1,
USCI2
I/O Ports
P7, P8
1×6 I/Os
1×8 I/Os
ACLK
SMCLK
SYS
Power
Management
I/O Ports
P9
1×8 I/Os
Unified
Clock
System
512KB
384KB
MID
PU Port
LDO
XT2OUT
Watchdog
Memory
Integrity
Detection
+2KB RAM
Ax: UART,
IrDA, SPI
P2 Port
Mapping
Controller
LDO,
SVM, SVS,
Brownout
PE
1×8 I/Os
Flash
MCLK
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
PD
1×14 I/Os
Bx: SPI, I2C
+8B Backup
RAM
CPUXV2
and
Working
Registers
EEM
(L: 8+2)
DMA
ADC12_A
TA1, TA2
RTC_B
6 Channel
TA0
TB0
DAC12_A
REF
LCD_B
12 bit
JTAG,
SBW
Interface
2 Timer_A
each with
3 CC
200 ksps
Timer_A
5 CC
Registers
Timer_B
7 CC
Registers
Comp_B
12 bit
2 channels
voltage out
MPY32
CRC16
Reference
1.5 V, 2.0 V,
2.5 V
160
Segments
Battery
Backup
System
16 channels
(12 ext, 4 int)
Autoscan
Registers
Port PJ
Figure 4-1. Functional Block Diagram – MSP430F6459, MSP430F6458
Figure 4-2 shows the functional block diagram for the MSP430F5659 and MSP430F5658 MCUs.
PA
PB
PC
PD
XIN XOUT
DVCC DVSS
AVCC AVSS
RST/NMI
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x
P9.x
XT2IN
64KB
32KB
RAM
I/O Ports
P1, P2
2×8 I/Os
Interrupt
Capability
I/O Ports
P3, P4
2×8 I/Os
Interrupt
Capability
I/O Ports
P5, P6
2×8 I/Os
USCI0,
USCI1,
USCI2
I/O Ports
P7, P8
1×6 I/Os
1×8 I/Os
ACLK
SMCLK
SYS
Power
Management
I/O Ports
P9
1×8 I/Os
Unified
Clock
System
USB
512KB
384KB
MID
XT2OUT
Watchdog
Full-speed
Memory
Integrity
Detection
+2KB RAM
USB Buffer
Ax: UART,
IrDA, SPI
P2 Port
Mapping
Controller
LDO,
SVM, SVS,
Brownout
PE
1×8 I/Os
Flash
MCLK
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
PD
1×14 I/Os
Bx: SPI, I2C
+8B Backup
RAM
CPUXV2
and
Working
Registers
EEM
(L: 8+2)
DMA
ADC12_A
TA1, TA2
RTC_B
6 Channel
TA0
TB0
DAC12_A
REF
12 bit
JTAG,
SBW
Interface
2 Timer_A
each with
3 CC
200 ksps
Timer_A
5 CC
Registers
Timer_B
7 CC
Registers
Comp_B
12 bit
2 channels
voltage out
MPY32
CRC16
Reference
1.5 V, 2.0 V,
2.5 V
Battery
Backup
System
16 channels
(12 ext, 4 int)
Autoscan
Registers
Port PJ
Figure 4-2. Functional Block Diagram – MSP430F5659, MSP430F5658
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MSP430F5658 MSP430F5359 MSP430F5358
MSP430F6659, MSP430F6658, MSP430F6459, MSP430F6458
MSP430F5659, MSP430F5658, MSP430F5359, MSP430F5358
www.ti.com
SLAS700E – OCTOBER 2012 – REVISED SEPTEMBER 2020
Figure 4-3 shows the functional block diagram for the MSP430F5359 and MSP430F5358 MCUs.
PA
PB
PC
PD
PU.0
PU.1
XIN XOUT
DVCC DVSS
AVCC AVSS
RST/NMI
LDOO LDOI
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x
P9.x
XT2IN
64KB
32KB
RAM
I/O Ports
P1, P2
2×8 I/Os
Interrupt
Capability
I/O Ports
P3, P4
2×8 I/Os
Interrupt
Capability
I/O Ports
P5, P6
2×8 I/Os
USCI0,
USCI1,
USCI2
I/O Ports
P7, P8
1×6 I/Os
1×8 I/Os
ACLK
SMCLK
SYS
Power
Management
I/O Ports
P9
1×8 I/Os
Unified
Clock
System
512KB
384KB
MID
PU Port
LDO
XT2OUT
Watchdog
Memory
Integrity
Detection
+2KB RAM
Ax: UART,
IrDA, SPI
P2 Port
Mapping
Controller
LDO,
SVM, SVS,
Brownout
PE
1×8 I/Os
Flash
MCLK
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
PD
1×14 I/Os
Bx: SPI, I2C
+8B Backup
RAM
CPUXV2
and
Working
Registers
EEM
(L: 8+2)
DMA
ADC12_A
TA1, TA2
RTC_B
6 Channel
TA0
TB0
DAC12_A
REF
12 bit
JTAG,
SBW
Interface
2 Timer_A
each with
3 CC
200 ksps
Timer_A
5 CC
Registers
Timer_B
7 CC
Registers
Comp_B
12 bit
2 channels
voltage out
MPY32
CRC16
Reference
1.5 V, 2.0 V,
2.5 V
Battery
Backup
System
16 channels
(12 ext, 4 int)
Autoscan
Registers
Port PJ
Figure 4-3. Functional Block Diagram – MSP430F5359, MSP430F5358
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MSP430F5658 MSP430F5359 MSP430F5358
MSP430F6659, MSP430F6658, MSP430F6459, MSP430F6458
MSP430F5659, MSP430F5658, MSP430F5359, MSP430F5358
SLAS700E – OCTOBER 2012 – REVISED SEPTEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Functional Block Diagrams............................................ 3
5 Revision History.............................................................. 7
6 Device Comparison.........................................................9
6.1 Related Products...................................................... 10
7 Terminal Configuration and Functions........................11
7.1 Pin Diagrams.............................................................11
7.2 Signal Descriptions................................................... 16
8 Specifications................................................................ 24
8.1 Absolute Maximum Ratings...................................... 24
8.2 ESD Ratings............................................................. 24
8.3 Recommended Operating Conditions.......................24
8.4 Active Mode Supply Current Into VCC Excluding
8.37 12-Bit ADC, Power Supply and Input Range
Conditions................................................................... 47
8.38 12-Bit ADC, Timing Parameters..............................48
8.39 12-Bit ADC, Linearity Parameters Using an
External Reference Voltage.........................................48
8.40 12-Bit ADC, Linearity Parameters Using AVCC
as Reference Voltage..................................................49
8.41 12-Bit ADC, Linearity Parameters Using the
Internal Reference Voltage..........................................49
8.42 12-Bit ADC, Temperature Sensor and Built-In
VMID ............................................................................49
8.43 REF, External Reference........................................ 50
8.44 REF, Built-In Reference.......................................... 51
8.45 12-Bit DAC, Supply Specifications..........................52
8.46 12-Bit DAC, Linearity Specifications....................... 53
8.47 12-Bit DAC, Output Specifications..........................54
8.48 12-Bit DAC, Reference Input Specifications........... 55
8.49 12-Bit DAC, Dynamic Specifications.......................55
8.50 12-Bit DAC, Dynamic Specifications (Continued)...56
8.51 Comparator_B.........................................................57
8.52 Ports PU.0 and PU.1...............................................58
8.53 USB Output Ports DP and DM................................58
8.54 USB Input Ports DP and DM...................................58
8.55 USB-PWR (USB Power System)............................59
8.56 USB-PLL (USB Phase Locked Loop)..................... 59
8.57 Flash Memory......................................................... 60
8.58 JTAG and Spy-Bi-Wire Interface.............................60
9 Detailed Description......................................................61
9.1 CPU ......................................................................... 61
9.2 Instruction Set...........................................................62
9.3 Operating Modes...................................................... 63
9.4 Interrupt Vector Addresses....................................... 64
9.5 Memory Organization................................................66
9.6 Bootloader (BSL)...................................................... 67
9.7 JTAG Operation........................................................ 68
9.8 Flash Memory .......................................................... 68
9.9 Memory Integrity Detection (MID) ............................69
9.10 RAM .......................................................................69
9.11 Backup RAM .......................................................... 69
9.12 Peripherals..............................................................70
9.13 Input/Output Diagrams............................................95
9.14 Device Descriptors................................................121
10 Device and Documentation Support........................122
10.1 Getting Started and Next Steps............................ 122
10.2 Device Nomenclature............................................122
10.3 Tools and Software............................................... 124
10.4 Documentation Support........................................ 126
10.5 Related Links........................................................ 128
10.6 Community Resources..........................................128
10.7 Trademarks...........................................................128
10.8 Electrostatic Discharge Caution............................128
10.9 Export Control Notice............................................128
10.10 Glossary..............................................................128
11 Mechanical, Packaging, and Orderable
External Current.......................................................... 26
8.5 Low-Power Mode Supply Currents (Into VCC
)
Excluding External Current..........................................26
8.6 Low-Power Mode With LCD Supply Currents
(Into VCC) Excluding External Current.........................28
8.7 Thermal Resistance Characteristics......................... 28
8.8 Schmitt-Trigger Inputs – General-Purpose I/O..........29
8.9 Inputs – Ports P1, P2, P3, and P4............................ 29
8.10 Leakage Current – General-Purpose I/O................29
8.11 Outputs – General-Purpose I/O (Full Drive
Strength)......................................................................29
8.12 Outputs – General-Purpose I/O (Reduced
Drive Strength)............................................................ 30
8.13 Output Frequency – Ports P1, P2, and P3..............30
8.14 Typical Characteristics – Outputs, Reduced
Drive Strength (PxDS.y = 0)........................................31
8.15 Typical Characteristics – Outputs, Full Drive
Strength (PxDS.y = 1)................................................. 32
8.16 Crystal Oscillator, XT1, Low-Frequency Mode........33
8.17 Crystal Oscillator, XT2............................................ 34
8.18 Internal Very-Low-Power Low-Frequency
Oscillator (VLO)...........................................................35
8.19 Internal Reference, Low-Frequency Oscillator
(REFO)........................................................................35
8.20 DCO Frequency......................................................36
8.21 PMM, Brownout Reset (BOR).................................37
8.22 PMM, Core Voltage.................................................37
8.23 PMM, SVS High Side..............................................38
8.24 PMM, SVM High Side............................................. 38
8.25 PMM, SVS Low Side...............................................39
8.26 PMM, SVM Low Side..............................................39
8.27 Wake-up Times From Low-Power Modes...............39
8.28 Timer_A – Timers TA0, TA1, and TA2.....................40
8.29 Timer_B – Timer TB0..............................................40
8.30 Battery Backup........................................................40
8.31 USCI (UART Mode)................................................ 41
8.32 USCI (SPI Master Mode)........................................ 41
8.33 USCI (SPI Slave Mode).......................................... 43
8.34 USCI (I2C Mode).....................................................45
8.35 LCD_B Operating Characteristics...........................46
8.36 LCD_B Electrical Characteristics............................47
Information.................................................................. 129
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Product Folder Links: MSP430F6659 MSP430F6658 MSP430F6459 MSP430F6458 MSP430F5659
MSP430F5658 MSP430F5359 MSP430F5358
MSP430F6659, MSP430F6658, MSP430F6459, MSP430F6458
MSP430F5659, MSP430F5658, MSP430F5359, MSP430F5358
www.ti.com
SLAS700E – OCTOBER 2012 – REVISED SEPTEMBER 2020
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changed from revision D to revision E
Changes from September 27, 2018 to September 11, 2020
Page
•
•
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•
Updated the numbering for sections, tables, figures, and cross-references throughout the document..............1
Added nFBGA package (ZCA) information throughout document......................................................................1
Added note about status change for all orderable part numbers in the ZQW package in Device Information .. 1
Removed package options that are no longer available (MSP430F6658 and MSP430F6458 in the ZQW
package) in Table 6-1, Device Comparison .......................................................................................................9
Removed packge options that are no longer available (MSP430F6658IZQW and MSP430F6458IZQW) from
the caption of Figure 7-5, 113-Pin ZQW Package (Top View) – MSP430F6659IZQW, MSP430F6459IZQW,
MSP430F5659IZQW, MSP430F5658IZQW, MSP430F5359IZQW, MSP430F5358IZQW ..............................11
Changed the MAX value of the IERASE and IMERASE, IBANK parameters in Section 8.57, Flash Memory ......... 60
Corrected the connection of the P7SEL.x signal in Figure 9-11, Port P7 (P7.4 to P7.7) Diagram .................110
•
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•
Changes from revision C to revision D
Changes from October 22, 2013 to September 26, 2018
Page
•
•
•
•
•
Format and organization changes throughout document, including addition of section numbering...................1
Added Device Information table..........................................................................................................................1
Added Section 4 and moved all functional block diagrams to it..........................................................................3
Added Section 6.1, Related Products ..............................................................................................................10
Added "Port U is supplied the LDOO rail" to the description of PU.0 and PU.1 in Section 7.2, Signal
Descriptions .....................................................................................................................................................16
Added Section 8 and moved all electrical specifications to it........................................................................... 24
Added typical conditions statements at the beginning of Section 8, Specifications .........................................24
Added Section 8.2, ESD Ratings .....................................................................................................................24
Moved Section 8.7, Thermal Resistance Characteristics ................................................................................ 28
Changed the TYP value of the CL,eff parameter with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to
1 pF in Section 8.16, Crystal Oscillator, XT1, Low-Frequency Mode .............................................................. 33
Changed the MIN value of the V(DVCC_BOR_hys) parameter from 60 mV to 50 mV in Section 8.21, PMM,
Brownout Reset (BOR) ....................................................................................................................................37
Updated notes (1) and (2) and added note (3) in Section 8.27, Wake-up Times From Low-Power Modes and
Reset ............................................................................................................................................................... 39
Corrected typo in the description of the VBAT3 parameter: changed "VBAT3 ≠ VBAT/3" to "VBAT3 ≈ VBAT/3" in
Section 8.30, Battery Backup .......................................................................................................................... 40
Removed ADC12DIV from the formula for the TYP value in the second row of the tCONVERT parameter in
Section 8.38, 12-Bit ADC, Timing Parameters, because ADC12CLK is after division..................................... 48
Added the TCSENSOR parameter in Section 8.42, 12-Bit ADC, Temperature Sensor and Built-In VMID ...........49
Changed the note that starts "The temperature sensor offset ..." from "...offset can be as much as ±20°C" to
"...offset can be significant"...............................................................................................................................49
Changed DAC12xDAT to DAC12_xDAT in IL(DAC12) Test Conditions in Section 8.47, 12-Bit DAC, Output
Specifications ...................................................................................................................................................54
Removed note from "Ri(VREF+), Ri(VeREF+)" parameter in Section 8.48, 12-Bit DAC, Reference Input
Specifications ...................................................................................................................................................55
Changed from fDAC12_0OUT to fDAC12_1OUT in the first row of the Test Conditions for the "Channel-to-channel
crosstalk" parameter in Section 8.50, 12-Bit DAC, Dynamic Specifications (Continued) ................................ 56
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•
•
•
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MSP430F5658 MSP430F5359 MSP430F5358
MSP430F6659, MSP430F6658, MSP430F6459, MSP430F6458
MSP430F5659, MSP430F5658, MSP430F5359, MSP430F5358
SLAS700E – OCTOBER 2012 – REVISED SEPTEMBER 2020
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•
•
Changed the value of DAC12_xDAT from 7F7h to F7Fh and changed the x-axis label from fToggle to 1/fToggle in
Figure 8-22, Crosstalk Test Conditions ............................................................................................................56
Section 8.51, Comparator_B: Added second row for the tEN_CMP parameter with Test Conditions of
"CBPWRMD = 10" and MAX value of 100 µs; Removed "CBPWRMD = 10" option in first row of Test
Conditions.........................................................................................................................................................57
Added note on RPUR in Section 8.55, USB-PWR (USB Power System) ......................................................... 59
Removed RTC_B from LPM4.5 wake-up options in Section 9.3, Operating Modes ....................................... 63
Throughout document, changed "bootstrap loader" to "bootloader".................................................................67
Added the paragraph that begins "Using the MSP430 RTC_B Module With Battery Backup Supply describes
how to..." ..........................................................................................................................................................72
Corrected spelling of NMIIFG in Table 9-12, System Module Interrupt Vector Registers ................................72
Corrected register names (added "USB" prefix as required) in Table 9-53, USB Control Registers ............... 80
Added P7SEL.2 and XT2BYPASS inputs with AND and OR gates in Figure 9-10, Port P7 (P7.3) Diagram 109
Changed P7SEL.3 column from X to 0 for "P7.3 (I/O)" rows in Table 9-63, Port P7 (P7.2 and P7.3) Pin
Functions ....................................................................................................................................................... 109
Updated Table 9-67, Port PU.0, PU.1 Functions ............................................................................................116
Added Section 9.13.14, Port PU.0, PU.1 Ports (F645x, F535x) .................................................................... 118
Added Section 10, Device and Documentation Support, and moved Development Tools Support, Device and
Development Tool Nomenclature, Trademarks, and Electrostatic Discharge Caution sections to it.............. 122
Replaced former section Development Tools Support with Section 10.3, Tools and Software ..................... 124
Added Section 11, Mechanical, Packaging, and Orderable Information ........................................................129
•
•
•
•
•
•
•
•
•
•
•
•
•
The following table lists changes to this data sheet from the original release to revision C.
REVISION
COMMENTS
Added Section 2
Removed Ordering Information table—refer to the Package Option Addendum
Table 9-12, Corrected Interrupt Event names for PMMSWBOR (BOR) and PMMSWPOR (POR)
Table 9-20, Added PM5CTL0 register
SLAS700C
October 2013
Section 8.3, Added note to CVCORE
Section 8.8, Added note to RPull
Section 8.54, Corrected VIL and VIH limits
Ordering Information, Corrected package type for PZ package (LQFP)
Changed functional block diagrams
Table 7-1, Added note to the RST/NMI/SBWTDIO pin
Added Development Tools Support and Device and Development Tool Nomenclature
Section 8.3, Fixed typo in fSYSTEM conditions
SLAS700B
June 2013
Section 8.20, Added note (1)
SLAS700A
December 2012
PRODUCTION DATA release
PRODUCT PREVIEW release
SLAS700
October 2012
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MSP430F6659, MSP430F6658, MSP430F6459, MSP430F6458
MSP430F5659, MSP430F5658, MSP430F5359, MSP430F5358
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SLAS700E – OCTOBER 2012 – REVISED SEPTEMBER 2020
6 Device Comparison
Table 6-1 summarizes the available family members.
Table 6-1. Device Comparison
USCI_:
UART, IrDA,
SPI
FLASH SRAM
USCI_:B:
SPI, I2C
ADC12_A
(channels)
DAC12_A
(channels)
Comp_B
(channels)
DEVICE(1)
Timer_A(3)
Timer_B(4)
I/O
USB
LCD
PACKAGE
(KB)(2)
(KB)(5)
100 PZ,
113 ZCA,
113 ZQW
MSP430F6659
MSP430F6658
MSP430F6459
MSP430F6458
MSP430F5659
512
384
512
384
512
64 + 2
32 + 2
66
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
7
7
7
7
7
3
3
3
3
3
3
3
3
3
3
12 ext, 4 int
12 ext, 4 int
12 ext, 4 int
12 ext, 4 int
12 ext, 4 int
2
2
2
2
2
12
12
12
12
12
74
74
74
74
74
Yes
Yes
No
Yes
Yes
Yes
Yes
No
100 PZ
100 PZ,
113 ZCA,
113 ZQW
34
No
100 PZ
100 PZ,
113 ZCA,
113 ZQW
64 + 2
Yes
100 PZ,
113 ZCA,
113 ZQW
MSP430F5658
MSP430F5359
MSP430F5358
384
512
384
32 + 2
66
5, 3, 3
5, 3, 3
5, 3, 3
7
7
7
3
3
3
3
3
3
12 ext, 4 int
12 ext, 4 int
12 ext, 4 int
2
2
2
12
12
12
74
74
74
Yes
No
No
No
No
No
100 PZ,
113 ZCA,
113 ZQW
100 PZ,
113 ZCA,
113 ZQW
34
(1) For the most current device, package, and ordering information, see the Package Option Addendum in Section 11, or see the TI website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
(5) The additional 2KB of USB SRAM that is listed can be used as general-purpose SRAM when USB is not in use.
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MSP430F5659, MSP430F5658, MSP430F5359, MSP430F5358
SLAS700E – OCTOBER 2012 – REVISED SEPTEMBER 2020
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6.1 Related Products
For information about other devices in this family of products or related products, see the following links.
16-bit and 32-bit microcontrollers
High-performance, low-power solutions to enable the autonomous future
Products for MSP430 ultra-low-power sensing & measurement MCUs
One platform. One ecosystem. Endless possibilities.
Companion products for MSP430F6659
Review products that are frequently purchased or used with this product.
TI reference designs
Find reference designs leveraging the best in TI technology to solve your system-level challenges
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MSP430F6659, MSP430F6658, MSP430F6459, MSP430F6458
MSP430F5659, MSP430F5658, MSP430F5359, MSP430F5358
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SLAS700E – OCTOBER 2012 – REVISED SEPTEMBER 2020
7 Terminal Configuration and Functions
7.1 Pin Diagrams
Figure 7-1 shows the pinout of the 100-pin PZ package for the MSP430F6659 and MSP430F6658 devices.
P6.4/CB4/A4
P6.5/CB5/A5
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P9.7/S0
2
P9.6/UCB2SOMI/UCB2SCL/S1
P9.5/UCB2SIMO/UCB2SDA/S2
P9.4/UCB2CLK/UCA2STE/S3
P9.3/UCA2RXD/UCA2SOMI/S4
P9.2/UCA2TXD/UCA2SIMO/S5
P9.1/UCB2STE/UCA2CLK/S6
P9.0/S7
P6.6/CB6/A6/DAC0
P6.7/CB7/A7/DAC1
P7.4/CB8/A12
P7.5/CB9/A13
P7.6/CB10/A14/DAC0
P7.7/CB11/A15/DAC1
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−
AVCC1
3
4
5
6
7
8
9
P8.7/S8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P8.6/UCB1SOMI/UCB1SCL/S9
P8.5/UCB1SIMO/UCB1SDA/S10
DVCC2
AVSS1
MSP430F6659
MSP430F6658
XIN
DVSS2
XOUT
P8.4/UCB1CLK/UCA1STE/S11
P8.3/UCA1RXD/UCA1SOMI/S12
P8.2/UCA1TXD/UCA1SIMO/S13
P8.1/UCB1STE/UCA1CLK/S14
P8.0/TB0CLK/S15
AVSS2
P5.6/ADC12CLK/DMAE0
P2.0/P2MAP0
P2.1/P2MAP1
P4.7/TB0OUTH/SVMOUT/S16
P4.6/TB0.6/S17
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P4.5/TB0.5/S18
P2.5/P2MAP5
P4.4/TB0.4/S19
P2.6/P2MAP6/R03
P2.7/P2MAP7/LCDREF/R13
DVCC1
P4.3/TB0.3/S20
P4.2/TB0.2/S21
P4.1/TB0.1/S22
Figure 7-1. 100-Pin PZ Package (Top View) – MSP430F6659IPZ, MSP430F6658IPZ
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MSP430F5659, MSP430F5658, MSP430F5359, MSP430F5358
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Figure 7-1 shows the pinout of the 100-pin PZ package for the MSP430F6459 and MSP430F6458 devices.
P6.4/CB4/A4
P6.5/CB5/A5
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P9.7/S0
2
P9.6/UCB2SOMI/UCB2SCL/S1
P9.5/UCB2SIMO/UCB2SDA/S2
P9.4/UCB2CLK/UCA2STE/S3
P9.3/UCA2RXD/UCA2SOMI/S4
P9.2/UCA2TXD/UCA2SIMO/S5
P9.1/UCB2STE/UCA2CLK/S6
P9.0/S7
P6.6/CB6/A6/DAC0
P6.7/CB7/A7/DAC1
P7.4/CB8/A12
P7.5/CB9/A13
P7.6/CB10/A14/DAC0
P7.7/CB11/A15/DAC1
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−
AVCC1
3
4
5
6
7
8
9
P8.7/S8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P8.6/UCB1SOMI/UCB1SCL/S9
P8.5/UCB1SIMO/UCB1SDA/S10
DVCC2
AVSS1
MSP430F6459
MSP430F6458
XIN
DVSS2
XOUT
P8.4/UCB1CLK/UCA1STE/S11
P8.3/UCA1RXD/UCA1SOMI/S12
P8.2/UCA1TXD/UCA1SIMO/S13
P8.1/UCB1STE/UCA1CLK/S14
P8.0/TB0CLK/S15
AVSS2
P5.6/ADC12CLK/DMAE0
P2.0/P2MAP0
P2.1/P2MAP1
P4.7/TB0OUTH/SVMOUT/S16
P4.6/TB0.6/S17
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P4.5/TB0.5/S18
P2.5/P2MAP5
P4.4/TB0.4/S19
P2.6/P2MAP6/R03
P2.7/P2MAP7/LCDREF/R13
DVCC1
P4.3/TB0.3/S20
P4.2/TB0.2/S21
P4.1/TB0.1/S22
Figure 7-2. 100-Pin PZ Package (Top View) – MSP430F6459IPZ, MSP430F6458IPZ
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MSP430F5659, MSP430F5658, MSP430F5359, MSP430F5358
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SLAS700E – OCTOBER 2012 – REVISED SEPTEMBER 2020
Figure 7-3 shows the pinout of the 100-pin PZ package for the MSP430F5659 and MSP430F5658 devices.
P6.4/CB4/A4
P6.5/CB5/A5
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P9.7
2
P9.6/UCB2SOMI/UCB2SCL
P9.5/UCB2SIMO/UCB2SDA
P9.4/UCB2CLK/UCA2STE
P9.3/UCA2RXD/UCA2SOMI
P9.2/UCA2TXD/UCA2SIMO
P9.1/UCB2STE/UCA2CLK
P9.0
P6.6/CB6/A6/DAC0
P6.7/CB7/A7/DAC1
P7.4/CB8/A12
P7.5/CB9/A13
P7.6/CB10/A14/DAC0
P7.7/CB11/A15/DAC1
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−
AVCC1
3
4
5
6
7
8
9
P8.7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P8.6/UCB1SOMI/UCB1SCL
P8.5/UCB1SIMO/UCB1SDA
DVCC2
AVSS1
MSP430F5659
MSP430F5658
XIN
DVSS2
XOUT
P8.4/UCB1CLK/UCA1STE
P8.3/UCA1RXD/UCA1SOMI
P8.2/UCA1TXD/UCA1SIMO
P8.1/UCB1STE/UCA1CLK
P8.0/TB0CLK
AVSS2
P5.6/ADC12CLK/DMAE0
P2.0/P2MAP0
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6
P2.7/P2MAP7
DVCC1
P4.7/TB0OUTH/SVMOUT
P4.6/TB0.6
P4.5/TB0.5
P4.4/TB0.4
P4.3/TB0.3
P4.2/TB0.2
P4.1/TB0.1
Figure 7-3. 100-Pin PZ Package (Top View) – MSP430F5659IPZ, MSP430F5658IPZ
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MSP430F5659, MSP430F5658, MSP430F5359, MSP430F5358
SLAS700E – OCTOBER 2012 – REVISED SEPTEMBER 2020
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Figure 7-4 shows the pinout of the 100-pin PZ package for the MSP430F5359 and MSP430F5358 devices.
P6.4/CB4/A4
P6.5/CB5/A5
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P9.7
2
P9.6/UCB2SOMI/UCB2SCL
P9.5/UCB2SIMO/UCB2SDA
P9.4/UCB2CLK/UCA2STE
P9.3/UCA2RXD/UCA2SOMI
P9.2/UCA2TXD/UCA2SIMO
P9.1/UCB2STE/UCA2CLK
P9.0
P6.6/CB6/A6/DAC0
P6.7/CB7/A7/DAC1
P7.4/CB8/A12
P7.5/CB9/A13
P7.6/CB10/A14/DAC0
P7.7/CB11/A15/DAC1
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−
AVCC1
3
4
5
6
7
8
9
P8.7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P8.6/UCB1SOMI/UCB1SCL
P8.5/UCB1SIMO/UCB1SDA
DVCC2
AVSS1
MSP430F5359
MSP430F5358
XIN
DVSS2
XOUT
P8.4/UCB1CLK/UCA1STE
P8.3/UCA1RXD/UCA1SOMI
P8.2/UCA1TXD/UCA1SIMO
P8.1/UCB1STE/UCA1CLK
P8.0/TB0CLK
AVSS2
P5.6/ADC12CLK/DMAE0
P2.0/P2MAP0
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6
P2.7/P2MAP7
DVCC1
P4.7/TB0OUTH/SVMOUT
P4.6/TB0.6
P4.5/TB0.5
P4.4/TB0.4
P4.3/TB0.3
P4.2/TB0.2
P4.1/TB0.1
Figure 7-4. 100-Pin PZ Package (Top View) – MSP430F5359IPZ, MSP430F5358IPZ
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MSP430F5659, MSP430F5658, MSP430F5359, MSP430F5358
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SLAS700E – OCTOBER 2012 – REVISED SEPTEMBER 2020
Figure 7-4 shows the pinout of the 113-pin ZCA or ZQW package. See Section 7.2 for the pin assignments.
A1
B1
C1
D1
E1
F1
G1
H1
J1
A2
B2
C2
D2
E2
F2
G2
H2
J2
A3
B3
C3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
A9
B9
A10
B10
A11
B11
C11
D11
E11
F11
G11
H11
J11
A12
B12
C12
D12
E12
F12
G12
H12
J12
D4
E4
F4
G4
H4
J4
D5
E5
F5
G5
H5
J5
D6
E6
D7
E7
D8
E8
F8
G8
H8
J8
D9
E9
F9
G9
H9
J9
H6
J6
H7
J7
K1
L1
K2
L2
K11
L11
M11
K12
L12
M12
L3
L4
L5
L6
L7
L8
L9
L10
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
Figure 7-5. 113-Pin ZCA or ZQW Package (Top View) – MSP430F6659IZCA, MSP430F6459IZCA,
MSP430F5659IZCA, MSP430F5658IZCA, MSP430F5359IZCA, MSP430F5358IZCA, MSP430F6659IZQW,
MSP430F6459IZQW, MSP430F5659IZQW, MSP430F5658IZQW, MSP430F5359IZQW, MSP430F5358IZQW
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MSP430F5659, MSP430F5658, MSP430F5359, MSP430F5358
SLAS700E – OCTOBER 2012 – REVISED SEPTEMBER 2020
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7.2 Signal Descriptions
Table 7-1 describes the signals for all device variants and package options.
Table 7-1. Signal Descriptions
TERMINAL
NO.
I/O(1)
DESCRIPTION
NAME
ZCA,
ZQW
PZ
General-purpose digital I/O
Comparator_B input CB4
Analog input A4 for ADC
P6.4/CB4/A4
P6.5/CB5/A5
1
A1
B2
I/O
I/O
General-purpose digital I/O
Comparator_B input CB5
Analog input A5 for ADC
2
3
General-purpose digital I/O
Comparator_B input CB6
Analog input A6 for ADC
DAC12.0 output
P6.6/CB6/A6/DAC0
P6.7/CB7/A7/DAC1
B1
C2
I/O
I/O
General-purpose digital I/O
Comparator_B input CB7
Analog input A7 for ADC
DAC12.1 output
4
General-purpose digital I/O
Comparator_B input CB8
Analog input A12 for ADC
P7.4/CB8/A12
P7.5/CB9/A13
5
6
C1
C3
I/O
I/O
General-purpose digital I/O
Comparator_B input CB9
Analog input A13 for ADC
General-purpose digital I/O
Comparator_B input CB10
Analog input A14 for ADC
DAC12.0 output
P7.6/CB10/A14/DAC0
7
D2
D1
I/O
I/O
General-purpose digital I/O
Comparator_B input CB11
Analog input A15 for ADC
DAC12.1 output
P7.7/CB11/A15/DAC1
P5.0/VREF+/VeREF+
8
9
General-purpose digital I/O
Output of reference voltage to the ADC
Input for an external reference voltage to the ADC
D4
E4
I/O
I/O
General-purpose digital I/O
P5.1/VREF-/VeREF-
AVCC1
10
11
Negative terminal for the ADC's reference voltage for both sources, the internal
reference voltage, or an external applied reference voltage
E1,
E2
Analog power supply
AVSS1
XIN
12
13
F2
F1
Analog ground supply
I
Input terminal for crystal oscillator XT1
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Table 7-1. Signal Descriptions (continued)
TERMINAL
NO.
ZCA,
I/O(1)
DESCRIPTION
NAME
PZ
ZQW
XOUT
14
15
G1
O
Output terminal of crystal oscillator XT1
AVSS2
G2
Analog ground supply
General-purpose digital I/O
Conversion clock output ADC
DMA external trigger input
P5.6/ADC12CLK/DMAE0
16
H1
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output
P2.0/P2MAP0
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
17
18
19
20
21
22
G4
H2
J1
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave in, master out; USCI_B0 I2C data
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave out, master in; USCI_B0 I2C clock
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable
H4
J2
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in, master out
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART receive data; USCI_A0 slave out, master in
K1
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: no secondary function
P2.6/P2MAP6/R03
23
24
K2
L2
I/O
I/O
Input/output port of lowest analog LCD voltage (V5) (not available on F5659,
F5658, F5359, F5358 devices)
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: no secondary function
External reference voltage input for regulated LCD voltage (not available on F5659,
F5658, F5359, F5358 devices)
P2.7/P2MAP7/LCDREF/R13
Input/output port of third most positive analog LCD voltage (V3 or V4) (not
available on F5659, F5658, F5359, F5358 devices)
DVCC1
DVSS1
25
26
27
L1
M1
M2
Digital power supply
Digital ground supply
VCORE(2)
Regulated core power supply (internal use only, no external current loading)
General-purpose digital I/O
P5.2/R23
28
29
L3
I/O
I/O
Input/output port of second most positive analog LCD voltage (V2) (not available
on F5659, F5658, F5359, F5358 devices)
LCD capacitor connection (not available on F5659, F5658, F5359, F5358 devices)
LCDCAP/R33
M3
Input/output port of most positive analog LCD voltage (V1) (not available on F5659,
F5658, F5359, F5358 devices)
DVSS
COM0
29
30
M3
J4
Digital ground supply (not available on F6659, F6658, F6459, and F6458 devices)
LCD common output COM0 for LCD backplane (not available on F5659, F5658,
F5359, F5358 devices)
O
Do not connect. TI strongly recommends leaving this terminal open (not available
on F6659, F6658, F6459, and F6458 devices)
DNC
30
J4
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Table 7-1. Signal Descriptions (continued)
TERMINAL
NO.
ZCA,
I/O(1)
DESCRIPTION
NAME
PZ
ZQW
General-purpose digital I/O
LCD common output COM1 for LCD backplane (not available on F5659, F5658,
F5359, F5358 devices)
P5.3/COM1/S42
31
L4
I/O
LCD segment output S42 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O
LCD common output COM2 for LCD backplane (not available on F5659, F5658,
F5359, F5358 devices)
P5.4/COM2/S41
P5.5/COM3/S40
32
33
M4
J5
I/O
I/O
LCD segment output S41 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O
LCD common output COM3 for LCD backplane (not available on F5659, F5658,
F5359, F5358 devices)
LCD segment output S40 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O with port interrupt
Timer TA0 clock signal TACLK input
P1.0/TA0CLK/ACLK/S39
P1.1/TA0.0/S38
34
35
36
L5
M5
J6
I/O
I/O
I/O
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
LCD segment output S39 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O with port interrupt
Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output
LCD segment output S38 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O with port interrupt
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input
P1.2/TA0.1/S37
LCD segment output S37 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O with port interrupt
Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output
LCD segment output S36 (not available on F5659, F5658, F5359, F5358 devices)
P1.3/TA0.2/S36
P1.4/TA0.3/S35
P1.5/TA0.4/S34
P1.6/TA0.1/S33
P1.7/TA0.2/S32
37
38
39
40
41
H6
M6
L6
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O with port interrupt
Timer TA0 CCR3 capture: CCI3A input compare: Out3 output
LCD segment output S35 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O with port interrupt
Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output
LCD segment output S34 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O with port interrupt
Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output
LCD segment output S33 (not available on F5659, F5658, F5359, F5358 devices)
J7
General-purpose digital I/O with port interrupt
Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output
LCD segment output S32 (not available on F5659, F5658, F5359, F5358 devices)
M7
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Table 7-1. Signal Descriptions (continued)
TERMINAL
NO.
ZCA,
I/O(1)
DESCRIPTION
NAME
PZ
ZQW
General-purpose digital I/O with port interrupt
Timer TA1 clock input
P3.0/TA1CLK/CBOUT/S31
42
L7
I/O
Comparator_B output
LCD segment output S31 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O with port interrupt
Timer TA1 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
LCD segment output S30 (not available on F5659, F5658, F5359, F5358 devices)
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P3.3/TA1.2/S28
43
44
45
H7
M8
L8
I/O
I/O
I/O
General-purpose digital I/O with port interrupt
Timer TA1 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
LCD segment output S29 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O with port interrupt
Timer TA1 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
LCD segment output S28 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O with port interrupt
Timer TA2 clock input
P3.4/TA2CLK/SMCLK/S27
46
J8
I/O
SMCLK output
LCD segment output S27 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O with port interrupt
Timer TA2 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
LCD segment output S26 (not available on F5659, F5658, F5359, F5358 devices)
P3.5/TA2.0/S26
P3.6/TA2.1/S25
P3.7/TA2.2/S24
P4.0/TB0.0/S23
P4.1/TB0.1/S22
P4.2/TB0.2/S21
P4.3/TB0.3/S20
47
48
49
50
51
52
53
M9
L9
I/O
I/O
General-purpose digital I/O with port interrupt
Timer TA2 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
LCD segment output S25 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O with port interrupt
Timer TA2 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
LCD segment output S24 (not available on F5659, F5658, F5359, F5358 devices)
M10 I/O
General-purpose digital I/O with port interrupt
Timer TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
LCD segment output S23 (not available on F5659, F5658, F5359, F5358 devices)
J9
I/O
I/O
I/O
General-purpose digital I/O with port interrupt
Timer TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
LCD segment output S22 (not available on F5659, F5658, F5359, F5358 devices)
M11
L10
General-purpose digital I/O with port interrupt
Timer TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
LCD segment output S21 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O with port interrupt
Timer TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output
LCD segment output S20 (not available on F5659, F5658, F5359, F5358 devices)
M12 I/O
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Table 7-1. Signal Descriptions (continued)
TERMINAL
NO.
ZCA,
I/O(1)
DESCRIPTION
NAME
PZ
ZQW
General-purpose digital I/O with port interrupt
Timer TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output
P4.4/TB0.4/S19
54
L12
I/O
I/O
I/O
LCD segment output S19 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O with port interrupt
Timer TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output
LCD segment output S18 (not available on F5659, F5658, F5359, F5358 devices)
P4.5/TB0.5/S18
P4.6/TB0.6/S17
55
56
L11
K11
General-purpose digital I/O with port interrupt
Timer TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output
LCD segment output S17 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O with port interrupt
Timer TB0: Switch all PWM outputs high impedance
SVM output
P4.7/TB0OUTH/SVMOUT/S16
P8.0/TB0CLK/S15
57
58
59
K12
J11
J12
I/O
I/O
I/O
LCD segment output S16 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O
Timer TB0 clock input
LCD segment output S15 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O
USCI_B1 SPI slave transmit enable
P8.1/UCB1STE/UCA1CLK/S14
USCI_A1 clock input/output
LCD segment output S14 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O
USCI_A1 UART transmit data
P8.2/UCA1TXD/UCA1SIMO/S13
P8.3/UCA1RXD/UCA1SOMI/S12
P8.4/UCB1CLK/UCA1STE/S11
60
61
62
H11
H12
G11
I/O
I/O
I/O
USCI_A1 SPI slave in, master out
LCD segment output S13 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O
USCI_A1 UART receive data
USCI_A1 SPI slave out, master in
LCD segment output S12 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O
USCI_B1 clock input/output
USCI_A1 SPI slave transmit enable
LCD segment output S11 (not available on F5659, F5658, F5359, F5358 devices)
DVSS2
DVCC2
63
64
G12
F12
Digital ground supply
Digital power supply
General-purpose digital I/O
USCI_B1 SPI slave in, master out
USCI_B1 I2C data
P8.5/UCB1SIMO/UCB1SDA/S10
65
F11
I/O
LCD segment output S10 (not available on F5659, F5658, F5359, F5358 devices)
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Table 7-1. Signal Descriptions (continued)
TERMINAL
NO.
ZCA,
I/O(1)
DESCRIPTION
NAME
PZ
ZQW
General-purpose digital I/O
USCI_B1 SPI slave out, master in
USCI_B1 I2C clock
P8.6/UCB1SOMI/UCB1SCL/S9
66
G9
I/O
LCD segment output S9 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O
P8.7/S8
P9.0/S7
67
68
E12
E11
I/O
I/O
LCD segment output S8 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O
LCD segment output S7 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O
USCI_B2 SPI slave transmit enable
P9.1/UCB2STE/UCA2CLK/S6
P9.2/UCA2TXD/UCA2SIMO/S5
P9.3/UCA2RXD/UCA2SOMI/S4
P9.4/UCB2CLK/UCA2STE/S3
P9.5/UCB2SIMO/UCB2SDA/S2
P9.6/UCB2SOMI/UCB2SCL/S1
69
70
71
72
73
74
F9
D12
D11
E9
I/O
I/O
I/O
I/O
I/O
USCI_A2 clock input/output
LCD segment output S6 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O
USCI_A2 UART transmit data
USCI_A2 SPI slave in, master out
LCD segment output S5 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O
USCI_A2 UART receive data
USCI_A2 SPI slave out, master in
LCD segment output S4 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O
USCI_B2 clock input/output
USCI_A2 SPI slave transmit enable
LCD segment output S3 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O
USCI_B2 SPI slave in, master out
C12
USCI_B2 I2C data
LCD segment output S2 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O
USCI_B2 SPI slave out, master in
C11
D9
I/O
I/O
USCI_B2 I2C clock
LCD segment output S1 (not available on F5659, F5658, F5359, F5358 devices)
General-purpose digital I/O
P9.7/S0
VSSU
75
76
LCD segment output S0 (not available on F5659, F5658, F5359, F5358 devices)
B11,
B12
USB PHY or PU ground supply
General-purpose digital I/O – controlled by USB or PU control register (Port U is
supplied the LDOO rail)
PU.0/DP
77
A12
I/O
USB data terminal DP (not available on F6459, F6458, F5359, F5358 devices)
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Table 7-1. Signal Descriptions (continued)
TERMINAL
NO.
ZCA,
I/O(1)
DESCRIPTION
NAME
PZ
ZQW
USB pullup resistor pin (open drain) (not available on F6459, F6458, F5359, F5358
devices)
PUR
NC
78
78
B10
I/O
B10
Not connected (not available on F6659, F6658, F5659, F5658 devices)
General-purpose digital I/O – controlled by USB or PU control register (Port U is
supplied the LDOO rail)
PU.1/DM
79
A11
I/O
USB data terminal DM (not available on F6459, F6458, F5359, F5358 devices)
USB LDO input (connect to USB power source) (not available on F6459, F6458,
F5359, F5358 devices)
VBUS
80
A10
LDOI
80
81
81
A10
A9
LDO input (not available on F6659, F6658, F5659, F5658 devices)
USB LDO output (not available on F6459, F6458, F5359, F5358 devices)
LDO output (not available on F6659, F6658, F5659, F5658 devices)
VUSB
LDOO
A9
USB regulated power (internal use only, no external current loading) (not available
on F6459, F6458, F5359, F5358 devices)
V18
82
B9
NC
82
83
B9
A8
Not connected (not available on F6659, F6658, F5659, F5658 devices)
Analog ground supply
AVSS3
General-purpose digital I/O
P7.2/XT2IN
84
85
B8
B7
I/O
I/O
Input terminal for crystal oscillator XT2
General-purpose digital I/O
P7.3/XT2OUT
Output terminal of crystal oscillator XT2
Capacitor for backup subsystem. Do not load this pin externally. For capacitor
values, see CBAK in Section 8.3.
VBAK
VBAT
86
87
A7
D8
Backup supply voltage. If backup voltage is not supplied, connect to DVCC
externally.
General-purpose digital I/O
RTCCLK output
P5.7/RTCCLK
88
D7
I/O
DVCC3
DVSS3
89
90
A6
A5
Digital power supply
Digital ground supply
Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
TEST/SBWTCK
PJ.0/TDO
91
92
93
94
95
B6
B5
A4
E7
D6
I
General-purpose digital I/O
Test data output port
I/O
I/O
I/O
I/O
General-purpose digital I/O
PJ.1/TDI/TCLK
PJ.2/TMS
Test data input or test clock input
General-purpose digital I/O
Test mode select
General-purpose digital I/O
Test clock
PJ.3/TCK
Reset input active low(3)
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
RST/NMI/SBWTDIO
96
A3
I/O
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Table 7-1. Signal Descriptions (continued)
TERMINAL
NO.
ZCA,
I/O(1)
DESCRIPTION
NAME
PZ
ZQW
General-purpose digital I/O
Comparator_B input CB0
Analog input A0 for ADC
P6.0/CB0/A0
P6.1/CB1/A1
P6.2/CB2/A2
P6.3/CB3/A3
97
B4
I/O
I/O
I/O
I/O
General-purpose digital I/O
Comparator_B input CB1
Analog input A1 for ADC
98
99
B3
A2
D5
General-purpose digital I/O
Comparator_B input CB2
Analog input A2 for ADC
General-purpose digital I/O
Comparator_B input CB3
Analog input A3 for ADC
100
E5,
E6,
E8,
F4,
F5,
F8,
G5,
G8,
H5,
H8,
H9
Reserved BGA package balls. TI recommends connecting to ground (DVSS,
AVSS).
Reserved
N/A
(1) I = input, O = output, N/A = not available on this package offering
(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE
.
(3) When this pin is configured as reset, the internal pullup resistor is enabled by default.
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8 Specifications
All graphs in this section are for typical conditions, unless otherwise noted.
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
4.1
UNIT
V
Voltage applied at VCC to VSS
–0.3
–0.3
Voltage applied to any pin (excluding VCORE, VBUS, V18)(2)
VCC + 0.3
±2
V
Diode current at any device pin
mA
°C
(3)
Storage temperature, Tstg
–55
150
Maximum junction temperature, TJ
95
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
8.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD) Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as
±250 V may actually have higher performance.
8.3 Recommended Operating Conditions
MIN
1.8
2.0
2.2
2.4
1.8
2.0
2.2
2.4
2.2
2.4
NOM
MAX UNIT
PMMCOREVx = 0
3.6
Supply voltage during program execution and flash
PMMCOREVx = 0, 1
PMMCOREVx = 0, 1, 2
PMMCOREVx = 0, 1, 2, 3
PMMCOREVx = 0
3.6
V
3.6
VCC
programming (AVCC1 = DVCC1 = DVCC2 = DVCC3 =
(1) (2)
DVCC = VCC
)
3.6
3.6
3.6
PMMCOREVx = 0, 1
PMMCOREVx = 0, 1, 2
PMMCOREVx = 0, 1, 2, 3
PMMCOREVx = 2
Supply voltage during USB operation, USB PLL disabled,
USB_EN = 1, UPLLEN = 0
3.6
V
3.6
VCC,USB
3.6
3.6
V
Supply voltage during USB operation, USB PLL
enabled(6), USB_EN = 1, UPLLEN = 1
PMMCOREVx = 2, 3
VSS
Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 = DVSS2 = DVSS3 = VSS
)
0
TA = 0°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
I version
1.55
1.70
1.20
–40
–40
1
3.6
V
VBAT,RTC
Backup-supply voltage with RTC operational
3.6
VBAT,MEM
TA
Backup-supply voltage with backup memory retained.
Operating free-air temperature
Operating junction temperature
Capacitance at pin VBAK
3.6
85
85
10
V
°C
°C
nF
nF
TJ
I version
CBAK
CVCORE
4.7
Capacitor at VCORE(3)
470
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MIN
NOM
MAX UNIT
CDVCC
CVCORE
/
Capacitor ratio of DVCC to VCORE
10
PMMCOREVx = 0,
1.8 V ≤ VCC ≤ 3.6 V
(default condition)
0
8.0
PMMCOREVx = 1,
2 V ≤ VCC ≤ 3.6 V
Processor frequency (maximum MCLK frequency)(4) (5)
(see Figure 8-1)
0
0
12.0
MHz
fSYSTEM
PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V
16.0
20.0
PMMCOREVx = 3,
2.4 V ≤ VCC ≤ 3.6 V
0
fSYSTEM_USB Minimum processor frequency for USB operation
USB_wait Wait state cycles during USB operation
1.5
MHz
16
cycles
(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 8.23 threshold parameters for
the exact values and further details.
(3) A capacitor tolerance of ±20% or better is required.
(4) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(6) USB operation with USB PLL enabled requires PMMCOREVx ≥ 2 for proper operation.
25
20
3
16
2, 3
2
12
8
1, 2
1, 2, 3
1
0
0, 1
0, 1, 2
0, 1, 2, 3
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
NOTE: The numbers within the fields denote the supported PMMCOREVx settings.
Figure 8-1. Frequency vs Supply Voltage
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8.4 Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted)(1) (2) (3)
FREQUENCY (fDCO = fMCLK = fSMCLK
8 MHz 12 MHz
TYP MAX
)
EXECUTION
MEMORY
PARAMETER
VCC
PMMCOREVx
1 MHz
20 MHz
UNIT
TYP
MAX
TYP
MAX
TYP
MAX
0
1
2
3
0
1
2
3
0.36
0.41
0.46
0.51
0.18
0.20
0.22
0.23
0.45
2.4
2.7
2.9
3.1
1.0
1.2
1.3
1.4
2.7
4.0
4.3
4.5
4.4
IAM, Flash
Flash
RAM
3 V
mA
7.4
0.23
1.3
1.7
2.0
2.2
1.9
IAM, RAM
3 V
mA
3.6
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external
load capacitance are chosen to closely match the required 12.5 pF.
(3) Characterized with program executing typical data processing. USB disabled (VUSBEN = 0, SLDOEN = 0).
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.
8.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
–40°C
TYP MAX
69
25°C
60°C
TYP MAX
79
85°C
PARAMETER
VCC
PMMCOREVx
UNIT
TYP MAX
TYP MAX
2.2 V
3 V
0
3
0
3
0
1
2
0
1
2
3
0
1
2
3
0
1
2
3
73
83
95
120
9.0
9.5
3.3
85
96
125
155
32
ILPM0,1MHz Low-power mode 0(3) (9)
µA
79
87
2.2 V
3 V
6.1
6.7
7.1
2.0
2.2
2.4
2.2
2.4
2.6
2.6
1.3
1.5
1.6
1.6
1.3
1.3
1.4
1.4
8.0
13
ILPM2
Low-power mode 2(4) (9)
µA
6.5
8.5
14
34
1.5
3.3
8.2
8.7
8.9
8.6
9.0
9.1
9.1
7.4
7.7
7.8
7.8
6.8
7.0
7.2
7.2
27
2.2 V
1.7
3.6
1.9
3.8
Low-power mode 3,
crystal mode(5) (9)
ILPM3,XT1LF
1.8
3.5
3.6
28
µA
µA
1.9
3.8
3 V
2.1
4.0
2.1
4.2
2.7
4.0
29
26
1.0
2.7
Low-power mode 3,
VLO mode, Watchdog
enabled(6) (9)
1.1
2.8
ILPM3,VLO,
3 V
WDT
1.1
2.9
1.1
3.2
2.5
2.9
30
26
0.9
2.5
1.0
2.6
ILPM4
Low-power mode 4(7) (9)
Low-power mode 3.5
3 V
3 V
µA
µA
1.0
2.7
1.0
3.1
2.7
27
ILPM3.5,RTC, (LPM3.5) current with
0.5
0.75
1.8
active RTC into primary
supply pin DVCC
VCC
(10)
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over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
–40°C
25°C
60°C
85°C
PARAMETER
VCC
PMMCOREVx
UNIT
TYP MAX
TYP MAX
TYP MAX
TYP MAX
Low-power mode 3.5
ILPM3.5,RTC, (LPM3.5) current with
3 V
0.6
1.1
0.75
1.0
µA
active RTC into backup
VBAT
supply pin VBAT(11)
Total low-power mode 3.5
ILPM3.5,RTC,
(LPM3.5) current with
3 V
3 V
1.0
0.4
1.2
0.5
1.5
2.8
1.8
µA
µA
TOT
active RTC(12)
ILPM4.5
Low-power mode 4.5(8)
0.45
0.6
0.76
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0).
(4) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCO
setting = 1-MHz operation, DCO bias generator enabled.
USB disabled (VUSBEN = 0, SLDOEN = 0)
(5) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0)
(6) Current for watchdog timer clocked by VLO included.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fMCLK = fSMCLK = fDCO = 0 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0)
(7) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0)
(8) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
(9) Current for brownout included. Low-side supervisor and monitors disabled (SVSL, SVML). High-side supervisor and monitor disabled
(SVSH, SVMH). RAM retention enabled.
(10) VVBAT = VCC - 0.2 V, fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active
(11) VVBAT = VCC - 0.2 V, fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no
current drawn on VBAK
(12) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no current drawn on VBAK
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8.6 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
TEMPERATURE (TA)
PARAMETER
VCC
PMMCOREVx
–40°C
TYP MAX
25°C
TYP
60°C
TYP
85°C
TYP
UNIT
MAX
MAX
MAX
0
1
2
3
0
1
2
0
1
2
3
2.7
2.9
3.0
3.1
3.3
3.5
3.7
3.7
3.6
3.7
4.0
3.5
3.7
3.8
3.9
4.8
4.7
5.0
5.2
5.2
9.5
9.9
28
Low-power mode 3
(LPM3) current, LCD 4-
mux mode, internal
biasing, charge pump
disabled(1) (2)
ILPM3 LCD,
3 V
µA
int. bias
10.2
10.2
5.3
30
2.2 V
3 V
Low-power mode 3
(LPM3) current, LCD 4-
mux mode, internal
biasing, charge pump
enabled(1) (3)
ILPM3
µA
LCD,CP
(1) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for brownout included. Low-side supervisor (SVSL) and low-side monitor (SVML) disabled. High-side supervisor (SVSH) and
high-side monitor (SVMH) disabled. RAM retention enabled.
(2) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
(3) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump
enabled), VLCDx = 1000 (VLCD = 3 V, typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
8.7 Thermal Resistance Characteristics
THERMAL METRIC
PACKAGE
QFP (PZ)
VALUE
122
108
83
UNIT
θJA
Junction-to-ambient thermal resistance, still air(1)
°C/W
BGA (ZQW)
QFP (PZ)
θJC(TOP)
Junction-to-case (top) thermal resistance(2)
Junction-to-board thermal resistance(3)
°C/W
°C/W
BGA (ZQW)
QFP (PZ)
72
98
θJB
BGA (ZQW)
76
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board,
as specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
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8.8 Schmitt-Trigger Inputs – General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
VCC
1.8 V
3 V
MIN
0.80
1.50
0.45
0.75
0.3
TYP
MAX UNIT
1.40
V
2.10
VIT+
VIT–
Vhys
Positive-going input threshold voltage
1.8 V
3 V
1.00
V
1.65
Negative-going input threshold voltage
1.8 V
3 V
0.8
V
1.0
Input voltage hysteresis (VIT+ – VIT–
)
0.4
For pullup: VIN = VSS
For pulldown: VIN = VCC
RPull
CI
Pullup or pulldown resistor(2)
Input capacitance
20
35
5
50
kΩ
pF
VIN = VSS or VCC
(1) The same parametrics apply to the clock input pin when the crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
(2) Also applies to RST pin when pullup or pulldown resistor is enabled.
8.9 Inputs – Ports P1, P2, P3, and P4
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
VCC
MIN
MAX UNIT
Port P1, P2, P3, P4: P1.x to P4.x,
External trigger pulse duration to set interrupt flag
t(int)
External interrupt timing(2)
2.2 V, 3 V
20
ns
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int)
.
8.10 Leakage Current – General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See (1) (2)
VCC
MIN
MAX UNIT
Ilkg(Px.y) High-impedance leakage current
1.8 V, 3 V
±50 nA
(1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input, and the pullup or pulldown resistor is
disabled.
8.11 Outputs – General-Purpose I/O (Full Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA(1)
VCC
MIN
VCC – 0.25
VCC – 0.60
VCC – 0.25
VCC – 0.60
MAX UNIT
VCC
1.8 V
I(OHmax) = –10 mA(2)
I(OHmax) = –5 mA(1)
I(OHmax) = –15 mA(2)
I(OLmax) = 3 mA(1)
I(OLmax) = 10 mA(2)
I(OLmax) = 5 mA(1)
I(OLmax) = 15 mA(2)
VCC
VOH
High-level output voltage
V
VCC
3 V
1.8 V
3 V
VCC
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
VSS VSS + 0.60
VOL
Low-level output voltage
V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage
drop specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
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8.12 Outputs – General-Purpose I/O (Reduced Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(3)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA(1)
VCC
MIN
VCC – 0.25
VCC – 0.60
VCC – 0.25
VCC – 0.60
MAX UNIT
VCC
1.8 V
I(OHmax) = –3 mA(2)
I(OHmax) = –2 mA(1)
I(OHmax) = –6 mA(2)
I(OLmax) = 1 mA(1)
I(OLmax) = 3 mA(2)
I(OLmax) = 2 mA(1)
I(OLmax) = 6 mA(2)
VCC
VOH
High-level output voltage
V
VCC
3 V
1.8 V
3 V
VCC
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
VSS VSS + 0.60
VOL
Low-level output voltage
V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
(3) Selecting reduced drive strength may reduce EMI.
8.13 Output Frequency – Ports P1, P2, and P3
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
VCC = 1.8 V,
PMMCOREVx = 0
8
Port output frequency
(with load)
P3.4/TA2CLK/SMCLK/S27,
fPx.y
MHz
20
CL = 20 pF, RL = 1 kΩ (1) or 3.2 kΩ(2) (3)
VCC = 3 V,
PMMCOREVx = 3
VCC = 1.8 V,
PMMCOREVx = 0
P1.0/TA0CLK/ACLK/S39,
P3.4/TA2CLK/SMCLK/S27,
P2.0/P2MAP0 (P2MAP0 = PM_MCLK),
CL = 20 pF(3)
8
fPort_CLK Clock output frequency
MHz
20
VCC = 3 V,
PMMCOREVx = 3
(1) Full drive strength of port: A resistive divider with two 0.5-kΩ resistors between VCC and VSS is used as load. The output is connected
to the center tap of the divider.
(2) Reduced drive strength of port: A resistive divider with two 1.6-kΩ resistors between VCC and VSS is used as load. The output is
connected to the center tap of the divider.
(3) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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8.14 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
25.0
20.0
15.0
10.0
5.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
VCC = 3.0 V
P3.2
VCC = 1.8 V
P3.2
TA = 25°C
TA = 85°C
TA = 25°C
TA = 85°C
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
Figure 8-3. Typical Low-Level Output Current vs
Low-Level Output Voltage
Figure 8-2. Typical Low-Level Output Current vs
Low-Level Output Voltage
0.0
0.0
VCC = 3.0 V
P3.2
VCC = 1.8 V
P3.2
−1.0
−5.0
−2.0
−3.0
−4.0
−10.0
−15.0
TA = 85°C
−5.0
TA = 85°C
−6.0
−20.0
TA = 25°C
TA = 25°C
−7.0
−8.0
−25.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
Figure 8-4. Typical High-Level Output Current vs
High-Level Output Voltage
Figure 8-5. Typical High-Level Output Current vs
High-Level Output Voltage
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8.15 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
60.0
24
VCC = 1.8 V
P3.2
VCC = 3.0 V
P3.2
TA = 25°C
TA = 85°C
55.0
50.0
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
TA = 25°C
TA = 85°C
20
16
12
8
4
0.0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
Figure 8-6. Typical Low-Level Output Current vs
Low-Level Output Voltage
Figure 8-7. Typical Low-Level Output Current vs
Low-Level Output Voltage
0.0
0
VCC = 1.8 V
P3.2
VCC = 3.0 V
−5.0
P3.2
−10.0
−15.0
−20.0
−25.0
−30.0
−35.0
−40.0
−4
−8
−12
−45.0
TA = 85°C
−16
TA = 85°C
−50.0
−55.0
TA = 25°C
−60.0
TA = 25°C
−20
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
Figure 8-8. Typical High-Level Output Current vs
High-Level Output Voltage
Figure 8-9. Typical High-Level Output Current vs
High-Level Output Voltage
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8.16 Crystal Oscillator, XT1, Low-Frequency Mode
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER(5)
TEST CONDITIONS
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1, TA = 25°C
VCC
MIN
TYP
MAX UNIT
0.075
Differential XT1 oscillator
crystal current consumption fOSC = 32768 Hz, XTS = 0,
from lowest drive setting, LF XT1BYPASS = 0, XT1DRIVEx = 2, TA = 25°C
ΔIDVCC,LF
3 V
0.170
0.290
32768
µA
mode
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3, TA = 25°C
XT1 oscillator crystal
XTS = 0, XT1BYPASS = 0
frequency, LF mode
fXT1,LF0
Hz
XT1 oscillator logic-level
square-wave input
frequency, LF mode
fXT1,LF,SW
XTS = 0, XT1BYPASS = 1(6) (7)
10 32.768
50 kHz
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF, TA = 25°C
210
300
Oscillation allowance for
LF crystals(8)
OALF
3 V
kΩ
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF, TA = 25°C
XTS = 0, XCAPx = 0(2)
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
XTS = 0, XCAPx = 3
1
5.5
Integrated effective load
capacitance, LF mode(1)
CL,eff
pF
8.5
12.0
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
Duty cycle, LF mode
30%
10
70%
Oscillator fault frequency,
LF mode(4)
fFault,LF
XTS = 0(3)
10000
Hz
ms
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C, CL,eff = 6 pF
1000
500
tSTART,LF
Start-up time, LF mode
3 V
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C, CL,eff = 12 pF
(1) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the
effective load capacitance should always match the specification of the used crystal.
(2) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(3) Measured with logic-level input frequency but also applies to operation with crystals.
(4) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
(5) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
•
•
•
•
•
•
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(6) When XT1BYPASS is set, XT1 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this data sheet.
(7) Maximum frequency of operation of the entire device cannot be exceeded.
(8) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
•
•
•
•
For XT1DRIVEx = 0, CL,eff ≤ 6 pF
For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF
For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF
For XT1DRIVEx = 3, CL,eff ≥ 6 pF
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8.17 Crystal Oscillator, XT2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(2) (5)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 4 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 0, TA = 25°C
200
fOSC = 12 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 1, TA = 25°C
260
325
450
XT2 oscillator crystal current
consumption
IDVCC,XT2
3 V
µA
fOSC = 20 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 2, TA = 25°C
fOSC = 32 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 3, TA = 25°C
XT2 oscillator crystal
frequency, mode 0
fXT2,HF0
fXT2,HF1
fXT2,HF2
fXT2,HF3
XT2DRIVEx = 0, XT2BYPASS = 0(7)
XT2DRIVEx = 1, XT2BYPASS = 0(7)
XT2DRIVEx = 2, XT2BYPASS = 0(7)
XT2DRIVEx = 3, XT2BYPASS = 0(7)
4
8
8
MHz
XT2 oscillator crystal
frequency, mode 1
16 MHz
24 MHz
32 MHz
XT2 oscillator crystal
frequency, mode 2
16
24
XT2 oscillator crystal
frequency, mode 3
XT2 oscillator logic-level
square-wave input
frequency
fXT2,HF,SW
XT2BYPASS = 1(6) (7)
0.7
32 MHz
XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 6 MHz, CL,eff = 15 pF, TA = 25°C
450
320
200
200
0.5
XT2DRIVEx = 1, XT2BYPASS = 0,
fXT2,HF1 = 12 MHz, CL,eff = 15 pF, TA = 25°C
Oscillation allowance for
HF crystals(8)
OAHF
3 V
Ω
XT2DRIVEx = 2, XT2BYPASS = 0,
fXT2,HF2 = 20 MHz, CL,eff = 15 pF, TA = 25°C
XT2DRIVEx = 3, XT2BYPASS = 0,
fXT2,HF3 = 32 MHz, CL,eff = 15 pF, TA = 25°C
fOSC = 6 MHz, XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C, CL,eff = 15 pF
tSTART,HF
Start-up time
3 V
ms
pF
fOSC = 20 MHz, XT2BYPASS = 0, XT2DRIVEx = 3,
TA = 25°C, CL,eff = 15 pF
0.3
Integrated effective load
CL,eff
1
capacitance, HF mode(1) (2)
Duty cycle
Measured at ACLK, fXT2,HF2 = 20 MHz
40%
30
50%
60%
300 kHz
fFault,HF
Oscillator fault frequency(4) XT2BYPASS = 1(3)
(1) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the
effective load capacitance should always match the specification of the used crystal.
(2) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(3) Measured with logic-level input frequency but also applies to operation with crystals.
(4) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
(5) To improve EMI on the XT2 oscillator the following guidelines should be observed.
•
•
•
•
•
•
Keep the traces between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(6) When XT2BYPASS is set, the XT2 circuit is automatically powered down.
(7) Maximum frequency of operation of the entire device cannot be exceeded.
(8) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
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8.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLO frequency
VLO frequency temperature drift
TEST CONDITIONS
VCC
MIN
TYP
9.4
0.5
4
MAX UNIT
14 kHz
%/°C
fVLO
Measured at ACLK
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
6
dfVLO/dT
Measured at ACLK(1)
Measured at ACLK(2)
Measured at ACLK
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
%/V
40%
50%
60%
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
8.19 Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
REFO oscillator current
consumption
IREFO
TA = 25°C
1.8 V to 3.6 V
3
µA
REFO frequency calibrated
Measured at ACLK
Full temperature range
TA = 25°C
1.8 V to 3.6 V
1.8 V to 3.6 V
3 V
32768
Hz
±3.5%
fREFO
REFO absolute tolerance
calibrated
±1.5%
dfREFO/dT
REFO frequency temperature drift Measured at ACLK(1)
1.8 V to 3.6 V
0.01
1.0
%/°C
REFO frequency supply voltage
Measured at ACLK(2)
drift
dfREFO/dVCC
1.8 V to 3.6 V
%/V
Duty cycle
Measured at ACLK
40%/60% duty cycle
1.8 V to 3.6 V
1.8 V to 3.6 V
40%
50%
25
60%
µs
tSTART
REFO start-up time
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
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8.20 DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DCORSELx = 0, DCOx = 0, MODx = 0
DCORSELx = 0, DCOx = 31, MODx = 0
DCORSELx = 1, DCOx = 0, MODx = 0
DCORSELx = 1, DCOx = 31, MODx = 0
DCORSELx = 2, DCOx = 0, MODx = 0
DCORSELx = 2, DCOx = 31, MODx = 0
DCORSELx = 3, DCOx = 0, MODx = 0
DCORSELx = 3, DCOx = 31, MODx = 0
DCORSELx = 4, DCOx = 0, MODx = 0
DCORSELx = 4, DCOx = 31, MODx = 0
DCORSELx = 5, DCOx = 0, MODx = 0
DCORSELx = 5, DCOx = 31, MODx = 0
DCORSELx = 6, DCOx = 0, MODx = 0
DCORSELx = 6, DCOx = 31, MODx = 0
DCORSELx = 7, DCOx = 0, MODx = 0
DCORSELx = 7, DCOx = 31, MODx = 0
MIN
0.07
0.70
0.15
1.47
0.32
3.17
0.64
6.07
1.3
TYP
MAX UNIT
0.20 MHz
1.70 MHz
0.36 MHz
3.45 MHz
0.75 MHz
7.38 MHz
1.51 MHz
14.0 MHz
3.2 MHz
fDCO(0,0)
fDCO(0,31)
fDCO(1,0)
fDCO(1,31)
fDCO(2,0)
fDCO(2,31)
fDCO(3,0)
fDCO(3,31)
fDCO(4,0)
fDCO(4,31)
fDCO(5,0)
fDCO(5,31)
fDCO(6,0)
fDCO(6,31)
fDCO(7,0)
fDCO(7,31)
DCO frequency (0, 0)(1)
DCO frequency (0, 31)(1)
DCO frequency (1, 0)(1)
DCO frequency (1, 31)(1)
DCO frequency (2, 0)(1)
DCO frequency (2, 31)(1)
DCO frequency (3, 0)(1)
DCO frequency (3, 31)(1)
DCO frequency (4, 0)(1)
DCO frequency (4, 31)(1)
DCO frequency (5, 0)(1)
DCO frequency (5, 31)(1)
DCO frequency (6, 0)(1)
DCO frequency (6, 31)(1)
DCO frequency (7, 0)(1)
DCO frequency (7, 31)(1)
12.3
2.5
28.2 MHz
6.0 MHz
23.7
4.6
54.1 MHz
10.7 MHz
88.0 MHz
19.6 MHz
135 MHz
39.0
8.5
60
Frequency step between range
DCORSEL and DCORSEL + 1
SDCORSEL
SDCO
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
1.2
2.3 ratio
Frequency step between tap DCO
and DCO + 1
1.02
40%
1.12 ratio
Duty cycle
Measured at SMCLK
fDCO = 1 MHz
50%
0.1
60%
%/°C
%/V
dfDCO/dT
DCO frequency temperature drift
dfDCO/dVCC DCO frequency voltage drift
fDCO = 1 MHz
1.9
(1) When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the
range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31
(DCOx = 31). This ensures that the target DCO frequency resides within the range selected. If the actual fDCO frequency for the
selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the selected range is at its
minimum or maximum tap setting.
100
VCC = 3.0 V
TA = 25°C
10
DCOx = 31
1
DCOx = 0
0.1
0
1
2
3
4
5
6
7
DCORSEL
Figure 8-10. Typical DCO Frequency
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8.21 PMM, Brownout Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
| dDVCC/dt | < 3 V/s
| dDVCC/dt | < 3 V/s
MIN
TYP
MAX UNIT
V(DVCC_BOR_IT–)
V(DVCC_BOR_IT+)
V(DVCC_BOR_hys)
tRESET
BORH on voltage, DVCC falling level
BORH off voltage, DVCC rising level
BORH hysteresis
1.45
1.50
250
V
V
0.80
50
2
1.30
mV
µs
Pulse duration required at RST/NMI pin to accept a reset
8.22 PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Core voltage, active mode,
PMMCOREV = 3
VCORE3(AM)
VCORE2(AM)
VCORE1(AM)
VCORE0(AM)
VCORE3(LPM)
VCORE2(LPM)
VCORE1(LPM)
VCORE0(LPM)
2.4 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 21 mA
1.90
V
Core voltage, active mode,
PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 21 mA
2 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 17 mA
1.8 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 13 mA
2.4 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
2.2 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
2 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
1.8 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
1.80
1.60
1.40
1.94
1.84
1.64
1.44
V
V
V
V
V
V
V
Core voltage, active mode,
PMMCOREV = 1
Core voltage, active mode,
PMMCOREV = 0
Core voltage, low-current mode,
PMMCOREV = 3
Core voltage, low-current mode,
PMMCOREV = 2
Core voltage, low-current mode,
PMMCOREV = 1
Core voltage, low-current mode,
PMMCOREV = 0
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8.23 PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SVSHE = 0, DVCC = 3.6 V
0
nA
I(SVSH)
SVS current consumption
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
SVSHE = 1, SVSHRVL = 0
200
2.0
µA
1.59
1.79
1.98
2.10
1.62
1.88
2.07
2.20
2.32
2.56
2.85
2.85
1.64
1.84
2.04
2.16
1.74
1.94
2.14
2.26
2.40
2.70
3.00
3.00
2.5
1.69
SVSHE = 1, SVSHRVL = 1
1.91
V
V(SVSH_IT–)
SVSH on voltage level(1)
SVSHE = 1, SVSHRVL = 2
2.11
SVSHE = 1, SVSHRVL = 3
2.23
1.81
2.01
2.21
SVSHE = 1, SVSMHRRL = 0
SVSHE = 1, SVSMHRRL = 1
SVSHE = 1, SVSMHRRL = 2
SVSHE = 1, SVSMHRRL = 3
2.33
V
V(SVSH_IT+)
SVSH off voltage level(1)
SVSHE = 1, SVSMHRRL = 4
2.48
SVSHE = 1, SVSMHRRL = 5
2.84
3.15
3.15
SVSHE = 1, SVSMHRRL = 6
SVSHE = 1, SVSMHRRL = 7
SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1
SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0
SVSHE = 0→1, SVSHFP = 1
SVSHE = 0→1, SVSHFP = 0
tpd(SVSH)
SVSH propagation delay
µs
µs
20
12.5
100
t(SVSH)
SVSH on or off delay time
DVCC rise time
dVDVCC/dt
0
1000
V/s
(1) The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and usage.
8.24 PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SVMHE = 0, DVCC = 3.6 V
0
nA
I(SVMH)
SVMH current consumption
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
SVMHE = 1, SVSMHRRL = 0
200
2.0
µA
1.86
1.65
1.85
2.02
2.18
2.32
2.56
2.85
2.85
1.74
1.94
2.14
2.26
2.40
2.70
3.00
3.00
3.75
2.5
SVMHE = 1, SVSMHRRL = 1
2.02
SVMHE = 1, SVSMHRRL = 2
2.22
SVMHE = 1, SVSMHRRL = 3
2.35
V(SVMH) SVMH on or off voltage level(1)
SVMHE = 1, SVSMHRRL = 4
2.48
2.84
3.15
3.15
V
SVMHE = 1, SVSMHRRL = 5
SVMHE = 1, SVSMHRRL = 6
SVMHE = 1, SVSMHRRL = 7
SVMHE = 1, SVMHOVPE = 1
SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1
SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0
SVMHE = 0→1, SVMHFP = 1
tpd(SVMH) SVMH propagation delay
µs
µs
20
12.5
100
t(SVMH)
SVMH on or off delay time
SVMHE = 0→1, SVMHFP = 0
(1) The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and usage.
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8.25 PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SVSLE = 0, PMMCOREV = 2
0
nA
µA
µs
I(SVSL)
SVSL current consumption
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
SVSLE = 0→1, SVSLFP = 1
200
2.0
2.5
20
tpd(SVSL) SVSL propagation delay
12.5
100
t(SVSL)
SVSL on or off delay time
µs
SVSLE = 0→1, SVSLFP = 0
8.26 PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SVMLE = 0, PMMCOREV = 2
0
nA
µA
µs
I(SVML)
SVML current consumption
SVMLE = 1, PMMCOREV = 2, SVMLFP = 0
SVMLE = 1, PMMCOREV = 2, SVMLFP = 1
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
SVMLE = 0→1, SVMLFP = 1
200
2.0
2.5
20
tpd(SVML) SVML propagation delay
12.5
100
t(SVML)
SVML on or off delay time
µs
SVMLE = 0→1, SVMLFP = 0
8.27 Wake-up Times From Low-Power Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
3
6.5
SVSLFP = 1, fMCLK ≥ 4.0 MHz
Wake-up time from LPM2, LPM3, or
LPM4 to active mode(1)
tWAKE-UP-FAST
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
4
8.0
µs
SVSLFP = 1, 1 MHz < fMCLK < 4.0 MHz
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 0
Wake-up time from LPM2, LPM3, or
LPM4 to active mode(2) (3)
tWAKE-UP-SLOW
150
165
Wake-up time from LPM3.5 or LPM4.5
to active mode(4)
tWAKE-UP LPM5
tWAKE-UP-RESET
2
2
3
3
ms
ms
Wake-up time from RST or BOR event
to active mode(4)
(1) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the
performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in
full performance mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode
Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx
Family User's Guide.
(2) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the
performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in
normal mode (low current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode
Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx
Family User's Guide.
(3) The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by
the performance mode settings as for LPM2, LPM3, and LPM4.
(4) This value represents the time from the wake-up event to the reset vector execution.
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8.28 Timer_A – Timers TA0, TA1, and TA2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK or ACLK,
fTA
Timer_A input clock frequency
External: TACLK,
1.8 V, 3 V
20 MHz
Duty cycle = 50% ±10%
All capture inputs, Minimum pulse duration
required for capture
tTA,cap
Timer_A capture timing
1.8 V, 3 V
20
ns
8.29 Timer_B – Timer TB0
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK or ACLK,
fTB
Timer_B input clock frequency
External: TBCLK,
1.8 V, 3 V
20 MHz
Duty cycle = 50% ±10%
All capture inputs, Minimum pulse duration
required for capture
tTB,cap
Timer_B capture timing
1.8 V, 3 V
20
ns
8.30 Battery Backup
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
TA = –40°C
0.43
0.52
VBAT = 1.7 V,
DVCC not connected,
RTC running
TA = 25°C
TA = 60°C
TA = 85°C
TA = –40°C
TA = 25°C
TA = 60°C
TA = 85°C
TA = –40°C
TA = 25°C
TA = 60°C
TA = 85°C
General
0.58
0.66
0.50
VBAT = 2.2 V,
DVCC not connected,
RTC running
0.59
Current into VBAT terminal if no
primary battery is connected
IVBAT
µA
0.64
0.72
0.68
VBAT = 3 V,
DVCC not connected,
RTC running
0.75
0.79
0.87
VSVSH_IT-
SVSHRL = 0
SVSHRL = 1
SVSHRL = 2
SVSHRL = 3
1.59
1.79
1.98
2.10
1.69
VSWITCH
Switch-over level (VCC to VBAT) CVCC = 4.7 µF
1.91
2.11
2.23
V
On-resistance of switch between
VBAT = 1.8 V
RON_VBAT
0 V
0.35
1
kΩ
V
VBAT and VBAK
1.8 V
3 V
0.6
1.0
1.2
±5%
±5%
±5%
VBAT to ADC input channel 12:
VBAT divided, VBAT3 ≈ VBAT/3
VBAT3
3.6 V
tSample,
VBAT to ADC: Sampling time
required if VBAT3 selected
ADC12ON = 1,
Error of conversion result ≤ 2 LSB
1000
2.65
ns
V
VBAT3
VCHVx
Charger end voltage
CHVx = 2
CHCx = 1
CHCx = 2
CHCx = 3
2.7
2.9
5.2
RCHARGE
Charge limiting resistor
10.2
20
kΩ
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8.31 USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK or ACLK,
External: UCLK
fUSCI
USCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ±10%
BITCLK clock frequency
(equals baud rate in MBaud)
fBITCLK
1
MHz
ns
2.2 V
3 V
50
50
600
600
tτ
UART receive deglitch time(1)
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To make sure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
8.32 USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 8-11 and )
PARAMETERFigure 8-12
TEST CONDITIONS
VCC
MIN
MAX UNIT
SMCLK or ACLK,
fUSCI
USCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ±10%
PMMCOREV = 0
1.8 V
3 V
55
38
30
25
0
tSU,MI
SOMI input data setup time
SOMI input data hold time
SIMO output data valid time(2)
SIMO output data hold time(3)
ns
2.4 V
3 V
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
1.8 V
3 V
0
tHD,MI
ns
2.4 V
3 V
0
0
1.8 V
3 V
20
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 0
18
ns
16
tVALID,MO
2.4 V
3 V
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 3
15
1.8 V
3 V
–10
–8
CL = 20 pF, PMMCOREV = 0
CL = 20 pF, PMMCOREV = 3
tHD,MO
ns
2.4 V
3 V
–10
–8
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)
)
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 8-11 and Figure 8-12.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure
8-11 and Figure 8-12.
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
SIMO
tHD,MO
tVALID,MO
Figure 8-11. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLO/HI
tLO/HI
tHD,MI
tSU,MI
SOMI
SIMO
tHD,MO
tVALID,MO
Figure 8-12. SPI Master Mode, CKPH = 1
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8.33 USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 8-13 and Figure 8-14)
PARAMETER
TEST CONDITIONS
VCC
1.8 V
3 V
MIN
11
8
MAX UNIT
PMMCOREV = 0
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
tSU,SI
STE lead time, STE low to clock
ns
2.4 V
3 V
7
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
6
1.8 V
3 V
1
1
STE lag time, last clock to STE high
ns
2.4 V
3 V
1
1
1.8 V
3 V
66
50
ns
36
STE access time, STE low to SOMI data out
2.4 V
3 V
30
30
1.8 V
3 V
30
ns
30
STE disable time, STE high to SOMI high
impedance
2.4 V
3 V
30
1.8 V
3 V
5
5
2
2
5
5
5
5
SIMO input data setup time
SIMO input data hold time
SOMI output data valid time(2)
SOMI output data hold time(3)
ns
2.4 V
3 V
1.8 V
3 V
tHD,SI
ns
2.4 V
3 V
1.8 V
3 V
76
UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 0
60
ns
44
tVALID,SO
2.4 V
3 V
UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 3
40
1.8 V
3 V
12
12
12
12
CL = 20 pF, PMMCOREV = 0
CL = 20 pF, PMMCOREV = 3
tHD,SO
ns
2.4 V
3 V
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)
)
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 8-13 and Figure 8-14.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure
8-13 and Figure 8-14.
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tSU,SI
tLO/HI
tLO/HI
tHD,SI
SIMO
SOMI
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
Figure 8-13. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
SOMI
tHD,MO
tVALID,SO
tSTE,ACC
tSTE,DIS
Figure 8-14. SPI Slave Mode, CKPH = 1
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8.34 USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see
Figure 8-15)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK or ACLK,
External: UCLK
fUSCI
USCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ±10%
fSCL
SCL clock frequency
2.2 V, 3 V
2.2 V, 3 V
0
4.0
0.6
4.7
0.6
0
400 kHz
µs
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
2.2 V, 3 V
µs
tHD,DAT
tSU,DAT
Data hold time
Data setup time
2.2 V, 3 V
2.2 V, 3 V
ns
ns
250
4.0
0.6
50
fSCL ≤ 100 kHz
fSCL > 100 kHz
tSU,STO
Setup time for STOP
2.2 V, 3 V
µs
2.2 V
3 V
600
ns
600
tSP
Pulse duration of spikes suppressed by input filter
50
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
SCL
tLOW
tHIGH
tSP
tSU,DAT
tSU,STO
tHD,DAT
Figure 8-15. I2C Mode Timing
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8.35 LCD_B Operating Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX UNIT
Supply voltage range, charge LCDCPEN = 1, 0000 < VLCDx ≤ 1111
VCC,LCD_B,CP en,3.6
VCC,LCD_B,CP en,3.3
VCC,LCD_B,int. bias
VCC,LCD_B,ext. bias
2.2
3.6
3.6
3.6
3.6
V
V
V
V
pump enabled, VLCD ≤ 3.6 V
(charge pump enabled, VLCD ≤ 3.6 V)
Supply voltage range, charge LCDCPEN = 1, 0000 < VLCDx ≤ 1100
2.0
2.4
2.4
pump enabled, VLCD ≤ 3.3 V
(charge pump enabled, VLCD ≤ 3.3 V)
LCDCPEN = 0, VLCDEXT = 0
Supply voltage range, internal
biasing, charge pump disabled
Supply voltage range, external
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 0
LCDCPEN = 0, VLCDEXT = 1
Supply voltage range, external
LCD voltage, internal or
external biasing, charge pump
disabled
VCC,LCD_B,VLCDEXT
2.0
2.4
3.6
3.6
V
V
External LCD voltage at
LCDCAP/R33, internal or
external biasing, charge pump
disabled
VLCDCAP/R33
LCDCPEN = 0, VLCDEXT = 1
Capacitor on LCDCAP when
charge pump enabled
LCDCPEN = 1, VLCDx > 0000 (charge
pump enabled)
CLCDCAP
fFrame
4.7
32
10
µF
Hz
fLCD = 2 × mux × fFRAME with mux = 1
(static), 2, 3, 4
LCD frame frequency range
0
100
fACLK,in
CPanel
ACLK input frequency range
Panel capacitance
30
40
kHz
pF
100-Hz frame frequency
10000
VCC
0.2
+
VR33
Analog input voltage at R33
Analog input voltage at R23
LCDCPEN = 0, VLCDEXT = 1
2.4
V
V
VR03 + 2/3
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR23,1/3bias
VR13
× (VR33
–
VR33
VR03
)
VR03 + 1/3
× (VR33
VR03
Analog input voltage at R13
with 1/3 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR13,1/3bias
VR03
–
)
VR23
V
V
VR03 + 1/2
× (VR33
VR03
Analog input voltage at R13
with 1/2 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 1
VR13,1/2bias
VR03
–
VR33
)
VR03
Analog input voltage at R03
R0EXT = 1
VSS
2.4
V
V
Voltage difference between
VLCD and R03
VCC
0.2
+
VLCD-VR03
LCDCPEN = 0, R0EXT = 1
External LCD reference
voltage applied at
LCDREF/R13
VLCDREF/R13
VLCDREFx = 01
0.8
1.2
1.5
V
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8.36 LCD_B Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VLCDx = 0000, VLCDEXT = 0
LCDCPEN = 1, VLCDx = 0001
LCDCPEN = 1, VLCDx = 0010
LCDCPEN = 1, VLCDx = 0011
LCDCPEN = 1, VLCDx = 0100
LCDCPEN = 1, VLCDx = 0101
LCDCPEN = 1, VLCDx = 0110
LCDCPEN = 1, VLCDx = 0111
LCDCPEN = 1, VLCDx = 1000
LCDCPEN = 1, VLCDx = 1001
LCDCPEN = 1, VLCDx = 1010
LCDCPEN = 1, VLCDx = 1011
LCDCPEN = 1, VLCDx = 1100
LCDCPEN = 1, VLCDx = 1101
LCDCPEN = 1, VLCDx = 1110
LCDCPEN = 1, VLCDx = 1111
VCC
MIN
TYP
VCC
MAX UNIT
2.4 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2.2 V to 3.6 V
2.2 V to 3.6 V
2.2 V to 3.6 V
2.59
2.66
2.72
2.79
2.85
2.92
2.98
3.05
3.10
3.17
3.24
3.30
3.36
3.42
3.48
VLCD
LCD voltage
V
3.6
µA
Peak supply currents due to
charge pump activities
ICC,Peak,CP
tLCD,CP,on
ICP,Load
LCDCPEN = 1, VLCDx = 1111
2.2 V
2.2 V
2.2 V
2.2 V
2.2 V
400
100
Time to charge CLCD when
discharged
CLCD = 4.7 µF, LCDCPEN = 0→1,
VLCDx = 1111
500
ms
µA
kΩ
kΩ
Maximum charge pump load
current
LCDCPEN = 1, VLCDx = 1111
50
LCD driver output impedance,
segment lines
LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA
RLCD,Seg
RLCD,COM
10
10
LCD driver output impedance,
common lines
LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA
8.37 12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(2)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.2
0
TYP
MAX UNIT
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
AVCC
Analog supply voltage
3.6
V
V(Ax)
Analog input voltage range(3) All ADC12 analog input pins Ax
AVCC
200
V
2.2 V
3 V
150
150
Operating supply current into
fADC12CLK = 5.0 MHz(1)
AVCC terminal(4)
IADC12_A
µA
250
Only one terminal Ax can be selected at one
time
CI
RI
Input capacitance
2.2 V
20
25
pF
Ω
Input MUX ON resistance
0 V ≤ VIN ≤ V(AVCC)
10
200
1900
(1) ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0
(2) The leakage current is specified by the digital I/O input leakage.
(3) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If the
reference voltage is supplied by an external source or if the internal voltage is used and REFOUT = 1, then decoupling capacitors are
required. See Section 8.43 and Section 8.44.
(4) The internal reference supply current is not included in current consumption parameter IADC12
.
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8.38 12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
For specified performance of ADC12 linearity
parameters using an external reference
voltage or AVCC as reference(1)
0.45
4.8
5.0
fADC12CLK
ADC conversion clock
For specified performance of ADC12 linearity 2.2 V, 3 V
parameters using the internal reference(2)
MHz
4.0
0.45
0.45
4.2
2.4
2.4
4.8
For specified performance of ADC12 linearity
parameters using the internal reference(3)
2.7
Internal ADC12
oscillator(5)
fADC12OSC
tCONVERT
tSample
ADC12DIV = 0, fADC12CLK = fADC12OSC
2.2 V, 3 V
2.2 V, 3 V
5.4 MHz
REFON = 0, Internal oscillator,
ADC12OSC used for ADC conversion clock
2.4
3.1
µs
Conversion time
Sampling time
External fADC12CLK from ACLK, MCLK or
SMCLK, ADC12SSEL ≠ 0
13 ×
1 / fADC12CLK
RS = 400 Ω, RI = 200 Ω, CI = 20 pF,
τ = [RS + RI] × CI
2.2 V, 3 V
1000
ns
(4)
(1) REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0,
SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the
specified performance of the ADC12 linearity is ensured with fADC12CLK maximum of 5.0 MHz.
(2) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1
(3) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when
using the ADC12OSC divided by 2.
(4) Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance
(5) The ADC12OSC is sourced directly from MODOSC inside the UCS.
8.39 12-Bit ADC, Linearity Parameters Using an External Reference Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Integral linearity error(2)
Differential linearity error(2)
Offset error(3)
TEST CONDITIONS
1.4 V ≤ dVREF ≤ 1.6 V(1)
1.6 V < dVREF (1)
See (1)
VCC
MIN
TYP
MAX UNIT
±2
LSB
±1.7
EI
2.2 V, 3 V
ED
EO
EG
ET
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
±1 LSB
dVREF ≤ 2.2 V(1)
dVREF > 2.2 V(1)
See (1)
±3
±1.5
±1
±5.6
LSB
±3.5
Gain error(3)
±2.5 LSB
dVREF ≤ 2.2 V(1)
dVREF > 2.2 V(1)
±3.5
±2
±7.1
LSB
±5
Total unadjusted error
(1) The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = VR+ – VR–. VR+ < AVCC. VR–
>
AVSS. Unless otherwise mentioned dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω and two decoupling
capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current. Also see the MSP430F5xx and
MSP430F6xx Family User's Guide.
(2) Parameters are derived using the histogram method.
(3) Parameters are derived using a best fit curve.
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8.40 12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Integral linearity error(2)
Differential linearity error(2)
Offset error(3)
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
±2.0 LSB
±1 LSB
±2 LSB
±4 LSB
±5 LSB
EI
See (1)
See (1)
See (1)
See (1)
See (1)
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
ED
EO
EG
ET
±1
±2
±2
Gain error(3)
Total unadjusted error
(1) AVCC as reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 0.
(2) Parameters are derived using the histogram method.
(3) Parameters are derived using a best fit curve.
8.41 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
VCC
MIN
TYP
MAX UNIT
ADC12SR = 0, REFOUT = 1
fADC12CLK ≤ 4.0 MHz
fADC12CLK ≤ 2.7 MHz
fADC12CLK ≤ 4.0 MHz
fADC12CLK ≤ 2.7 MHz
fADC12CLK ≤ 2.7 MHz
fADC12CLK ≤ 4.0 MHz
fADC12CLK ≤ 2.7 MHz
fADC12CLK ≤ 4.0 MHz
fADC12CLK ≤ 2.7 MHz
fADC12CLK ≤ 4.0 MHz
fADC12CLK ≤ 2.7 MHz
±2.0
LSB
±2.5
Integral
EI
2.2 V, 3 V
linearity error(2)
ADC12SR = 0, REFOUT = 0
ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 0
ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 0
ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 0
ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 0
–1
–1
+1.5
Differential
ED
2.2 V, 3 V
±1 LSB
+2.5
linearity error(2)
±2
±2
±1
±4
LSB
±4
EO
EG
ET
Offset error(3)
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
±2.5 LSB
±1%(4) VREF
±5 LSB
Gain error(3)
±2
Total unadjusted error
±1%(4) VREF
(1) The external reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 1. dVREF = VR+ – VR–
.
(2) Parameters are derived using the histogram method.
(3) Parameters are derived using a best fit curve.
(4) The gain error and the total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In
this mode, the reference voltage used by the ADC12_A is not available on a pin.
8.42 12-Bit ADC, Temperature Sensor and Built-In VMID
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
VCC
2.2 V
3 V
MIN
TYP
MAX UNIT
Temperature sensor voltage(2)
(see Figure 8-16)
680
VSENSOR
ADC12ON = 1, INCH = 0Ah, TA = 0°C
mV
680
TCSENSOR
tSENSOR(sample)
Temperature coefficient of sensor ADC12ON = 1, INCH = 0Ah
2.2 V, 3V
2.2 V
3 V
2.25(2)
mV/°C
µs
30
30
Sample time required if
channel 10 is selected(3)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
2.2 V
3 V
1.06
1.46
1.1
1.5
1.14
V
1.54
ADC12ON = 1, INCH = 0Bh,
VMID ≈ 0.5 × VAVCC
VMID
AVCC divider at channel 11
Sample time required if
channel 11 is selected(4)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
tVMID(sample)
2.2 V, 3 V
1000
ns
(1) The temperature sensor is provided by the REF module. See the REF module parametric, IREF+, regarding the current consumption of
the temperature sensor.
(2) The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor. The TLV structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference
voltage levels. The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature,°C) + VSENSOR, where TCSENSOR and
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VSENSOR can be computed from the calibration values for higher accuracy. Also see the MSP430F5xx and MSP430F6xx Family User's
Guide.
(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
.
(4) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
1000
950
900
850
800
750
700
650
600
550
500
-40 -30 -20 -10
0 10 20 30 40 50 60 70 80
Ambient Temperature (°C)
Figure 8-16. Typical Temperature Sensor Voltage
8.43 REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Positive external reference
voltage input
(2)
VeREF+
VeREF+ > VREF–/VeREF–
1.4
AVCC
1.2
V
V
V
Negative external reference
voltage input
(3)
(4)
VREF–/VeREF–
VeREF+ > VREF–/VeREF–
0
(VeREF+
VREF–/VeREF–
–
Differential external reference
voltage input
VeREF+ > VREF–/VeREF–
1.4
AVCC
)
1.4 V ≤ VeREF+ ≤ VAVCC, VeREF– = 0 V,
fADC12CLK = 5 MHz, ADC12SHTx = 1h,
Conversion rate 200 ksps
2.2 V, 3 V
2.2 V, 3 V
–26
26
IVeREF+, IVREF–/
Static input current
µA
VeREF–
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC12CLK = 5 MHz, ADC12SHTx = 8h,
Conversion rate 20 ksps
–1.2
10
+1.2
Capacitance at VREF+ or
VREF- terminal(5)
CVREF+/-
µF
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is
also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_A. Also see the MSP430F5xx and MSP430F6xx Family User's Guide.
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8.44 REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
REFVSEL = {2} for 2.5 V,
REFON = REFOUT = 1, IVREF+ = 0 A
3 V
2.5
±1%
Positive built-in
reference voltage
output
REFVSEL = {1} for 2 V,
REFON = REFOUT = 1, IVREF+ = 0 A
VREF+
3 V
2.0
1.5
±1%
±1%
V
V
REFVSEL = {0} for 1.5 V,
REFON = REFOUT = 1, IVREF+ = 0 A
2.2 V, 3 V
AVCC minimum
voltage, Positive
built-in reference
active
REFVSEL = {0} for 1.5 V
REFVSEL = {1} for 2 V
REFVSEL = {2} for 2.5 V
2.2
2.3
2.8
AVCC(min)
ADC12SR = 1(8)
REFON = 1, REFOUT = 0, REFBURST = 0
,
70
0.45
210
100
0.75
310
1.7
µA
mA
µA
ADC12SR = 1(8)
REFON = 1, REFOUT = 1, REFBURST = 0
,
Operating supply
current into AVCC
terminal (2) (7)
IREF+
3 V
ADC12SR = 0(8)
REFON = 1, REFOUT = 0, REFBURST = 0
,
ADC12SR = 0(8)
,
0.95
mA
REFON = 1, REFOUT = 1, REFBURST = 0
REFVSEL = {0, 1, 2},
IVREF+ = +10 µA or –1000 µA,
AVCC = AVCC(min) for each reference level,
REFVSEL = {0, 1, 2}, REFON = REFOUT = 1
Load-current
regulation, VREF+
terminal(3)
IL(VREF+)
1500
2500 µV/mA
Capacitance at
VREF+ terminal
REFON = REFOUT = 1(6)
,
0 mA ≤ IVREF+ ≤ IVREF+(max)
CVREF+
2.2 V, 3 V
2.2 V, 3 V
20
100
pF
Temperature
IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ –1 mA
TCREF+
coefficient of built-in
REFOUT = 0
REFOUT = 1
20
20
120
1
ppm/ °C
reference(4)
Temperature
IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ –1 mA
TCREF+
coefficient of built-in
2.2 V, 3 V
50 ppm/ °C
reference(4)
AVCC = AVCC(min) to AVCC(max), TA = 25°C,
REFVSEL = {0, 1, 2}, REFON = 1,
REFOUT = 0 or 1
Power supply
rejection ratio (DC)
PSRR_DC
PSRR_AC
300
µV/V
AVCC = AVCC(min) to AVCC(max), TA = 25°C,
REFVSEL = {0, 1, 2}, REFON = 1,
REFOUT = 0 or 1
Power supply
rejection ratio (AC)
mV/V
AVCC = AVCC(min) to AVCC(max)
,
REFVSEL = {0, 1, 2}, REFOUT = 0,
REFON = 0 → 1
75
75
Settling time of
tSETTLE
µs
reference voltage(5)
AVCC = AVCC(min) to AVCC(max)
,
CVREF = CVREF(max), REFVSEL = {0, 1, 2},
REFOUT = 1, REFON = 0 → 1
(1) The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers,
one smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal and is
used as the reference for the conversion and uses the larger buffer. When REFOUT = 0, the reference is only used as the reference
for the conversion and uses the smaller buffer.
(2) The internal reference current is supplied from the AVCC terminal. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current
contribution of the larger buffer without external load.
(3) Contribution only due to the reference and buffer including package. This does not include resistance due to PCB trace or other
causes.
(4) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
(5) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load when REFOUT = 1.
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(6) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_A. Also see the MSP430F5xx and MSP430F6xx Family User's Guide.
(7) The temperature sensor is provided by the REF module. Its current is supplied from the AVCC terminal and is equivalent to IREF+ with
REFON = 1 and REFOUT = 0.
(8) For devices without the ADC12, the parametric with ADC12SR = 0 are applicable.
8.45 12-Bit DAC, Supply Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
AVCC
Analog supply voltage
AVCC = DVCC, AVSS = DVSS = 0 V
2.20
3.60
110
V
DAC12AMPx = 2, DAC12IR = 0, DAC12IOG = 1
DAC12_xDAT = 0800h
VeREF+ = VREF+ = 1.5 V
3 V
65
65
DAC12AMPx = 2, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = VREF+ = AVCC
110
300
Supply current, single
DAC channel(1) (2)
IDD
µA
DAC12AMPx = 5, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = VREF+ = AVCC
2.2 V, 3 V
250
750
DAC12AMPx = 7, DAC12IR = 1,
DAC12_xDAT = 0800h,
1000
VeREF+ = VREF+ = AVCC
DAC12_xDAT = 800h, VeREF+ = 1.5 V,
ΔAVCC = 100 mV
2.2 V
3 V
70
70
Power supply rejection
ratio(3) (4)
PSRR
dB
DAC12_xDAT = 800h, VeREF+ = 1.5 V or 2.5 V,
ΔAVCC = 100 mV
(1) No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
(2) Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input
specifications.
(3) PSRR = 20 log (ΔAVCC / ΔVDAC12_xOUT
(4) The internal reference is not used.
)
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8.46 12-Bit DAC, Linearity Specifications
See Figure 8-17, over recommended ranges of supply voltage and operating free-air temperature (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP MAX UNIT
Resolution
12-bit monotonic
12
bits
VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1
VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1
VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1
VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1
2.2 V
3 V
±2
±2
±4
±4
±1
±1
INL
Integral nonlinearity(1)
LSB
2.2 V
3 V
±0.4
±0.4
DNL
Differential nonlinearity(1)
LSB
VeREF+ = 1.5 V,
DAC12AMPx = 7,
DAC12IR = 1
2.2 V
3 V
±21
±21
Without calibration(1) (2)
VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1
EO
Offset voltage
mV
VeREF+ = 1.5 V,
DAC12AMPx = 7,
DAC12IR = 1
2.2 V
±1.5
±1.5
With calibration(1) (2)
VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1
3 V
Offset error temperature
coefficient(1)
dE(O)/dT
With calibration
2.2 V, 3 V
±10
10
µV/°C
%FSR
VeREF+ = 1.5 V
VeREF+ = 2.5 V
2.2 V
3 V
±2.5
±2.5
EG
Gain error
Gain temperature
coefficient(1)
ppm of
FSR/°C
dE(G)/dT
2.2 V, 3 V
DAC12AMPx = 2
165
66
Time for offset
calibration(3)
tOffset_Cal
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
2.2 V, 3 V
ms
16.5
(1) Parameters calculated from the best-fit curve from 0x0F to 0xFFF. The best-fit curve method is used to deliver coefficients "a" and "b"
of the first-order equation: y = a + bx. VDAC12_xOUT = EO + (1 + EG) × (VeREF+/4095) × DAC12_xDAT, DAC12IR = 1.
(2) The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
(3) The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx
= {0, 1}. TI recommends configuring the DAC12 module before initiating calibration. Port activity during calibration may affect accuracy
and is not recommended.
DAC VOUT
DAC Output
VR+
RLoad = ¥
Ideal transfer
function
AVCC
2
Offset Error
Positive
Gain Error
CLoad = 100 pF
Negative
DAC Code
Figure 8-17. Linearity Test Load Conditions and Gain/Offset Definition
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8.47 12-Bit DAC, Output Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
No load, VeREF+ = AVCC, DAC12_xDAT = 0h,
DAC12IR = 1, DAC12AMPx = 7
0
0.005
No load, VeREF+ = AVCC
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
,
AVCC
0.05
–
AVCC
Output voltage
VO
range(1) (see Figure
8-18)
2.2 V, 3 V
V
RLoad = 3 kΩ, VeREF+ = AVCC
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
,
0
0.1
RLoad = 3 kΩ, VeREF+ = AVCC
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
,
AVCC
0.13
–
AVCC
Maximum DAC12
load capacitance
CL(DAC12)
2.2 V, 3 V
2.2 V, 3 V
100
pF
DAC12AMPx = 2, DAC12_xDAT = 0FFFh,
VO/P(DAC12) > AVCC – 0.3
–1
Maximum DAC12
load current
IL(DAC12)
mA
DAC12AMPx = 2, DAC12_xDAT = 0h,
VO/P(DAC12) < 0.3 V
1
250
250
6
RLoad = 3 kΩ, VO/P(DAC12) < 0.3 V,
DAC12AMPx = 2, DAC12_xDAT = 0h
150
150
Output resistance
(see Figure 8-18)
RLoad = 3 kΩ, VO/P(DAC12) > AVCC – 0.3 V,
DAC12_xDAT = 0FFFh
RO/P(DAC12)
2.2 V, 3 V
Ω
RLoad = 3 kΩ,
0.3 V ≤ VO/P(DAC12) ≤ AVCC – 0.3 V
(1) Data is valid after the offset calibration of the output amplifier.
RO/P(DAC12_x)
Max
RLoad
ILoad
AVCC
DAC12
2
CLoad = 100 pF
O/P(DAC12_x)
Min
0.3
AVCC – 0.3 V
VOUT
AVCC
Figure 8-18. DAC12_x Output Resistance Tests
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8.48 12-Bit DAC, Reference Input Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
AVCC
+
DAC12IR = 0(1) (2)
AVCC/3
0.2
VeREF+
Reference input voltage range
2.2 V, 3 V
V
AVCC
+
DAC12IR = 1(3) (4)
AVCC
0.2
DAC12_0 IR = DAC12_1 IR = 0
DAC12_0 IR = 1, DAC12_1 IR = 0
DAC12_0 IR = 0, DAC12_1 IR = 1
20
MΩ
52
52
Ri(VREF+)
Ri(VeREF+)
,
Reference input resistance
2.2 V, 3 V
kΩ
DAC12_0 IR = DAC12_1 IR = 1,
26
DAC12_0 SREFx = DAC12_1 SREFx(5)
(1) For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
(2) The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / [3 × (1 + EG)].
(3) For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
(4) The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / (1 + EG).
(5) When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
8.49 12-Bit DAC, Dynamic Specifications
VREF = VCC, DAC12IR = 1 (see Figure 8-19 and Figure 8-20), over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP MAX UNIT
DAC12AMPx = 0 → {2, 3, 4}
60
15
120
30
DAC12_xDAT = 800h,
ErrorV(O) < ±0.5 LSB(1)
(see Figure 8-19)
tON
DAC12 on time
DAC12AMPx = 0 → {5, 6}
DAC12AMPx = 0 → 7
DAC12AMPx = 2
2.2 V, 3 V
µs
µs
µs
6
12
100
40
200
80
DAC12_xDAT =
80h → F7Fh → 80h
tS(FS)
tS(C-C)
SR
Settling time, full scale
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
DAC12AMPx = 2
2.2 V, 3 V
2.2 V, 3 V
15
30
5
DAC12_xDAT =
3F8h → 408h → 3F8h,
BF8h → C08h → BF8h
Settling time, code to
code
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
DAC12AMPx = 2
2
1
0.05
0.35
1.50
0.35
1.10
5.20
DAC12_xDAT =
Slew rate
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
2.2 V, 3 V
2.2 V, 3 V
V/µs
nV-s
80h → F7Fh → 80h(2)
DAC12_xDAT =
800h → 7FFh → 800h
Glitch energy
DAC12AMPx = 7
35
(1) RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 8-19.
(2) Slew rate applies to output voltage steps ≥200 mV.
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Conversion 1
Conversion 2
1/2 LꢀS
Conversion 3
VOUT
DAC Output
Glitch
Energy
RLoad = 3 kW
ILoad
AVCC
2
1/2 LꢀS
CLoad = 100 pF
RO/P(DAC12.x)
tsettleLH
tsettleHL
Figure 8-19. Settling Time and Glitch Energy Testing
Conversion 1
Conversion 2
Conversion 3
VOUT
90%
90%
10%
10%
tSRLH
tSRHL
Figure 8-20. Slew Rate Testing
8.50 12-Bit DAC, Dynamic Specifications (Continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
TA = 25°C
40
3-dB bandwidth,
VDC = 1.5 V,
VAC = 0.1 VPP
(see Figure 8-21)
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
TA = 25°C
BW–3dB
2.2 V, 3 V
180
550
kHz
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
TA = 25°C
DAC12_0DAT = 800h, No load,
DAC12_1DAT = 80h ↔ F7Fh, RLoad = 3 kΩ,
fDAC12_1OUT = 10 kHz at 50/50 duty cycle,
TA = 25°C
–80
–80
Channel-to-channel
crosstalk(1)
(see Figure 8-22)
2.2 V, 3 V
dB
DAC12_0DAT = 80h ↔ F7Fh, RLoad = 3 kΩ,
DAC12_1DAT = 800h, No load,
fDAC12_0OUT = 10 kHz at 50/50 duty cycle,
TA = 25°C
(1) RLoad = 3 kΩ, CLoad = 100 pF
RLoad = 3 kW
ILoad
VeREF+
AVCC
2
DAC12_x
DACx
AC
DC
CLoad = 100 pF
Figure 8-21. Test Conditions for 3-dB Bandwidth Specification
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RLoad
ILoad
AVCC
2
DAC12_xDAT
VOUT
080h
080h
F7Fh
080h
F7Fh
DAC12_0
DAC12_1
DAC0
CLoad = 100 pF
RLoad
VREF+
VDAC12_yOUT
ILoad
VDAC12_xOUT
AVCC
2
1/fToggle
DAC1
CLoad = 100 pF
Figure 8-22. Crosstalk Test Conditions
8.51 Comparator_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
VCC
Supply voltage
1.8
3.6
40
50
65
30
0.5
V
1.8 V
2.2 V
CBPWRMD = 00
30
40
Comparator operating supply
IAVCC_COMP current into AVCC terminal,
Excludes reference resistor ladder
3 V
µA
CBPWRMD = 01
CBPWRMD = 10
2.2 V, 3 V
2.2 V, 3 V
10
0.1
Quiescent current of local
IAVCC_REF
reference voltage amplifier into
AVCC terminal
CBREFACC = 1, CBREFLx = 01
22
µA
VIC
Common mode input range
0
VCC – 1
±20
V
CBPWRMD = 00
VOFFSET
CIN
Input offset voltage
mV
CBPWRMD = 01 or 10
±10
Input capacitance
5
3
pF
kΩ
On (switch closed)
4
RSIN
Series input resistance
Off (switch open)
50
MΩ
CBPWRMD = 00, CBF = 0
450
600
50
ns
µs
tPD
Propagation delay, response time CBPWRMD = 01, CBF = 0
CBPWRMD = 10, CBF = 0
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 00
0.35
0.6
1.0
1.8
0.6
1.0
1.8
3.4
1
1.0
1.8
3.4
6.5
2
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 01
tPD,filter
Propagation delay with filter active
µs
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 10
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 11
CBON = 0 to CBON = 1
CBPWRMD = 00 or 01
tEN_CMP
Comparator enable time
µs
CBON = 0 to CBON = 1
CBPWRMD = 10
100
tEN_REF
Resistor reference enable time
Reference voltage for a given tap
CBON = 0 to CBON = 1
0.3
1.5
µs
V
VIN ×
VIN ×
VIN ×
VIN = reference into resistor
ladder (n = 0 to 31)
VCB_REF
(n + 0.5) / (n + 1) / 3 (n + 1.5) /
32 32
2
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8.52 Ports PU.0 and PU.1
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
High-level output voltage
Low-level output voltage
High-level input voltage
Low-level input voltage
TEST CONDITIONS
VUSB = 3.3 V ±10%, IOH = –25 mA
VUSB = 3.3 V ±10%, IOL = 25 mA
VUSB = 3.3 V ±10%
MIN
MAX
UNIT
VOH
VOL
VIH
VIL
2.4
V
V
V
V
0.4
2.0
VUSB = 3.3 V ±10%
0.8
8.53 USB Output Ports DP and DM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
D+, D- single ended
D+, D- single ended
D+, D- impedance
TEST CONDITIONS
MIN
2.8
0
MAX
3.6
0.3
44
UNIT
V
VOH
USB 2.0 load conditions
VOL
USB 2.0 load conditions
V
Z(DRV)
Including external series resistor of 27 Ω
28
Ω
Full speed, differential, CL = 50 pF,
10%/90%, Rpu on D+
tRISE
tFALL
Rise time
Fall time
4
4
20
20
ns
ns
Full speed, differential, CL = 50 pF,
10%/90%, Rpu on D+
8.54 USB Input Ports DP and DM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Differential input common mode range
Input impedance
TEST CONDITIONS
MIN
MAX
UNIT
V
V(CM)
Z(IN)
VCRS
VIL
0.8
2.5
300
1.3
kΩ
V
Crossover voltage
2.0
0.8
Static SE input logic low level
Static SE input logic high level
Differential input voltage
V
VIH
2.0
V
VDI
0.2
V
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8.55 USB-PWR (USB Power System)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VLAUNCH
VBUS
VBUS detection threshold
3.75
5.5
V
V
USB bus voltage
Normal operation
3.76
VUSB
USB LDO output voltage
3.3
1.8
±9%
V
V18
Internal USB voltage(1)
V
IUSB_EXT
IDET
Maximum external current from VUSB terminal(2)
USB LDO current overload detection(3)
USB LDO is on
12
mA
mA
60
100
USB LDO is on,
USB PLL disabled
ISUSPEND
Operating supply current into VBUS terminal.(4)
250
µA
CBUS
CUSB
C18
VBUS terminal recommended capacitance
VUSB terminal recommended capacitance
V18 terminal recommended capacitance
4.7
220
220
µF
nF
nF
Within 2%,
recommended capacitances
tENABLE
RPUR
Settling time VUSB and V18
2
ms
Ω
Pullup resistance of PUR terminal(5)
70
110
150
(1) This voltage is for internal use only. No external DC loading should be applied.
(2) This represents additional current that can be supplied to the application from the VUSB terminal beyond the needs of the USB
operation.
(3) A current overload will be detected when the total current supplied from the USB LDO, including IUSB_EXT, exceeds this value.
(4) Does not include current contribution of Rpu and Rpd as outlined in the USB specification.
(5) This value, in series with an external resistor between PUR and D+, produces the Rpu as outlined in the USB specification.
8.56 USB-PLL (USB Phase Locked Loop)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN
TYP
MAX UNIT
IPLL
Operating supply current
PLL frequency
7
mA
MHz
MHz
ms
fPLL
48
fUPD
tLOCK
tJitter
PLL reference frequency
PLL lock time
1.5
3
2
PLL jitter
1000
ps
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8.57 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TJ
MIN
TYP
MAX UNIT
DVCC(PGM/ERASE) Program and erase supply voltage
1.8
3.6
5
V
mA
IPGM
Average supply current from DVCC during program
3
6
6
IERASE
Average supply current from DVCC during erase
Average supply current from DVCC during mass erase or bank erase
Cumulative program time(1)
19
19
16
mA
IMERASE, IBANK
tCPT
mA
ms
Program and erase endurance
104
100
64
105
cycles
years
µs
tRetention
tWord
Data retention duration
25°C
Word or byte program time(2)
85
65
tBlock, 0
Block program time for first byte or word(2)
49
µs
Block program time for each additional byte or word, except for last byte
or word(2)
tBlock, 1–(N–1)
37
49
µs
tBlock, N
Block program time for last byte or word(2)
55
23
73
32
µs
tSeg Erase
Erase time for segment, mass erase, and bank erase when available(2)
ms
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4.MGR1 = 1)
fMCLK,MGR
0
1
MHz
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word write, individual byte write, and block write modes.
(2) These values are hardwired into the state machine of the flash controller.
8.58 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
Spy-Bi-Wire input frequency
MIN
TYP
MAX UNIT
fSBW
2.2 V, 3 V
0
20 MHz
tSBW,Low
tSBW, En
tSBW,Rst
Spy-Bi-Wire low clock pulse duration
2.2 V, 3 V
0.025
15
1
µs
µs
µs
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)(1)
2.2 V, 3 V
Spy-Bi-Wire return to normal operation time
15
0
100
5
2.2 V
3 V
fTCK
TCK input frequency for 4-wire JTAG(2)
Internal pulldown resistance on TEST
MHz
kΩ
0
10
80
Rinternal
2.2 V, 3 V
45
60
(1) Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
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9 Detailed Description
9.1 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,
other than program-flow instructions, are performed as register operations in conjunction with seven addressing
modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are
general-purpose registers (see Figure 9-1).
Peripherals are connected to the CPU using data, address, and control buses. The peripherals can be managed
with all instructions.
Program Counter
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
Figure 9-1. Integrated CPU Registers
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9.2 Instruction Set
The instruction set consists of the original 51 instructions with three formats and seven address modes and
additional instructions for the expanded address range. Each instruction can operate on word and byte data.
Table 9-1 lists examples of the three types of instruction formats. Table 9-2 lists the address modes.
Table 9-1. Instruction Word Formats
INSTRUCTION WORD FORMAT
Dual operands, source-destination
EXAMPLE
ADD R4,R5
CALL R8
JNE
OPERATION
R4 + R5 → R5
Single operands, destination only
PC → (TOS), R8 → PC
Jump-on-equal bit = 0
Relative jump, unconditional or conditional
Table 9-2. Address Mode Descriptions
ADDRESS MODE
Register
S(1)
+
D(1)
+
SYNTAX
EXAMPLE
OPERATION
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
+
+
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV &MEM, &TCDAT
MOV @Rn,Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
M(R10) → M(Tab+R6)
Symbolic (PC relative)
Absolute
+
+
+
+
Indirect
+
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
M(R10) → R11
R10 + 2 → R10
Indirect auto-increment
Immediate
+
+
MOV @Rn+,Rm
MOV #X,TONI
#45 → M(TONI)
(1) S = source, D = destination
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9.3 Operating Modes
The MCUs have one active mode and seven software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
Software can configure the following operating modes:
•
Active mode (AM)
– All clocks are active
•
Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
Low-power mode 1 (LPM1)
•
•
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO remains enabled
– ACLK remains active
•
•
Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– ACLK remains active
Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– Crystal oscillator is stopped
– Complete data retention
•
•
Low-power mode 3.5 (LPM3.5)
– Internal regulator disabled
– No data retention
– RTC enabled and clocked by low-frequency oscillator
– Wake-up input from RST/NMI, RTC_B, P1, P2, P3, and P4
Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No data retention
– Wake-up input from RST/NMI, P1, P2, P3, and P4
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9.4 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table
9-3). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 9-3. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
System Reset
Power up, External Reset
Watchdog time-out, key violation
Flash memory key violation
WDTIFG, KEYV (SYSRSTIV)(1) (3)
Reset
0FFFEh
0FFFCh
0FFFAh
63, highest
System NMI
PMM
Vacant memory access
JTAG mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
SVMLVLRIFG, SVMHVLRIFG, VMAIFG,
JMBINIFG, JMBOUTIFG (SYSSNIV)(1)
(Non)maskable
(Non)maskable
62
61
User NMI
NMI
Oscillator fault
NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV)
(1) (3)
Flash memory access violation
Comp_B
Comparator B interrupt flags (CBIV)(1) (2)
TB0CCR0 CCIFG0 (2)
Maskable
Maskable
0FFF8h
0FFF6h
60
59
Timer TB0
TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
TB0IFG (TB0IV)(1) (2)
Timer TB0
Maskable
0FFF4h
58
Watchdog interval timer mode
USCI_A0 receive or transmit
USCI_B0 receive or transmit
ADC12_A
WDTIFG
Maskable
Maskable
Maskable
Maskable
Maskable
0FFF2h
0FFF0h
0FFEEh
0FFECh
0FFEAh
57
56
55
54
53
UCA0RXIFG, UCA0TXIFG (UCA0IV)(1) (2)
UCB0RXIFG, UCB0TXIFG (UCB0IV)(1) (2)
ADC12IFG0 to ADC12IFG15 (ADC12IV)(1) (2)
TA0CCR0 CCIFG0(2)
Timer TA0
TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0IFG (TA0IV)(1) (2)
Timer TA0
Maskable
Maskable
0FFE8h
0FFE6h
52
51
USB_UBM(5)
LDO-PWR (7)
USB interrupts (USBIV)(1) (2)
LDOOFFIFG, LDOONIFG, LDOOVLIFG
DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG,
DMA4IFG, DMA5IFG (DMAIV)(1) (2)
DMA
Maskable
Maskable
Maskable
0FFE4h
0FFE2h
0FFE0h
50
49
48
Timer TA1
Timer TA1
TA1CCR0 CCIFG0(2)
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG (TA1IV)(1) (2)
I/O Port P1
USCI_A1 receive or transmit
USCI_B1 receive or transmit
I/O port P2
P1IFG.0 to P1IFG.7 (P1IV)(1) (2)
UCA1RXIFG, UCA1TXIFG (UCA1IV)(1) (2)
UCB1RXIFG, UCB1TXIFG (UCB1IV)(1) (2)
P2IFG.0 to P2IFG.7 (P2IV)(1) (2)
Maskable
Maskable
Maskable
Maskable
Maskable
0FFDEh
0FFDCh
0FFDAh
0FFD8h
0FFD6h
47
46
45
44
43
LCD_B(6)
LCD_B Interrupt Flags (LCDBIV)(1)
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RTC_B
Maskable
0FFD4h
42
RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV)(1) (2)
DAC12_A
Timer TA2
DAC12_0IFG, DAC12_1IFG(1) (2)
TA2CCR0 CCIFG0(2)
Maskable
Maskable
0FFD2h
0FFD0h
41
40
TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
TA2IFG (TA2IV)(1) (2)
Timer TA2
Maskable
0FFCEh
39
I/O port P3
P3IFG.0 to P3IFG.7 (P3IV)(1) (2)
P4IFG.0 to P4IFG.7 (P4IV)(1) (2)
Maskable
Maskable
0FFCCh
0FFCAh
0FFC8h
0FFC6h
38
37
36
35
I/O Port P4
USCI_A2 receive or transmit
USCI_B2 receive or transmit
UCA2RXIFG, UCA2TXIFG (UCA2IV)(1) (2)
UCB2RXIFG, UCB2TXIFG (UCB2IV)(1) (2)
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Table 9-3. Interrupt Sources, Flags, and Vectors (continued)
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
0FFC4h
⋮
34
Reserved
Reserved(4)
⋮
0FF80h
0, lowest
(1) Multiple source flags
(2) Interrupt flags are in the module.
(3) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it.
(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To
maintain compatibility with other devices, TI recommends reserving these locations.
(5) Only on devices with peripheral module USB (MSP430F665x and MSP430F565x)
(6) Only on devices with peripheral module LCD_B (MSP430F665x and MSP430F645x), otherwise reserved (MSP430F535x and
MSP430F565x)
(7) Only on devices with peripheral module LDO-PWR (MSP430F535x and MSP430F645x)
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9.5 Memory Organization
Table 9-4 summarizes the memory map of all device variants.
Table 9-4. Memory Organization
MSP430F6458
MSP430F5358
MSP430F6459
MSP430F5359
MSP430F6658
MSP430F5658
MSP430F6659
MSP430F5659
(1)
Memory (flash)
Total Size
384KB
512KB
384KB
512KB
Main: interrupt vector
00FFFFh to 00FF80h 00FFFFh to 00FF80h
00FFFFh to 00FF80h
00FFFFh to 00FF80h
128KB
N/A
128KB
087FFFh to 068000h
Bank 3
Bank 2
N/A
087FFFh to 068000h
128KB
128KB
128KB
067FFFh to 048000h
128KB
067FFFh-48000h
067FFFh to 048000h
067FFFh-48000h
Main: code memory
128KB
128KB
128KB
047FFFh to 028000h
128KB
047FFFh to 028000h
Bank 1
047FFFh to 028000h 047FFFh to 028000h
128KB 128KB
027FFFh to 008000h 027FFFh to 008000h
1KB 1KB
006FFFh to 006C00h 006FFFh to 006C00h
16KB 16KB
128KB
027FFFh to 008000h
128KB
027FFFh to 008000h
Bank 0
MID support
software (ROM)
1KB
1KB
Total Size
Sector 3
Sector 2
Sector 1
006FFFh to 006C00h
006FFFh to 006C00h
16KB
0FBFFFh to 0F8000h
16KB
0FBFFFh to 0F8000h
0FBFFFh to 0F8000h 0FBFFFh to 0F8000h
16KB
N/A
16KB
0F7FFFh to 0F4000h
N/A
N/A
0F7FFFh to 0F4000h
16KB
N/A
16KB
0F3FFFh to 0F0000h
RAM
0F3FFFh to 0F0000h
16KB
0063FFh to 002400h
Sector 0 (mirrored at address
range
16KB
16KB
0063FFh to 002400h
(mirrored at address range (mirrored at address range
0FFFFFh to 0FC000h)
16KB
0063FFh to 002400h
0063FFh to 002400h
(mirrored at address
range
0FFFFFh to 0FC000h)
0FFFFFh to 0FC000h) 0FFFFFh to 0FC000h)
2KB 2KB
0023FFh to 001C00h 0023FFh to 001C00h
RAM(3)
Sector 7
Sector 7
Info A
Info B
Info C
Info D
BSL 3
BSL 2
BSL 1
BSL 0
Size
N/A
N/A
2KB
2KB
USB RAM(2)
N/A
N/A
0023FFh to 001C00h
0023FFh to 001C00h
128 bytes
0019FFh to 001980h
128 bytes
0019FFh to 001980h
128 bytes
0019FFh to 001980h
128 bytes
0019FFh to 001980h
128 bytes
00197Fh to 001900h
128 bytes
00197Fh to 001900h
128 bytes
00197Fh to 001900h
128 bytes
00197Fh to 001900h
Information memory
(flash)
128 bytes
0018FFh to 001880h
128 bytes
0018FFh to 001880h
128 bytes
0018FFh to 001880h
128 bytes
0018FFh to 001880h
128 bytes
00187Fh to 001800h
128 bytes
00187Fh to 001800h
128 bytes
00187Fh to 001800h
128 bytes
00187Fh to 001800h
512 bytes
0017FFh to 001600h
512 bytes
0017FFh to 001600h
512 bytes
0017FFh to 001600h
512 bytes
0017FFh to 001600h
512 bytes
0015FFh to 001400h
512 bytes
0015FFh to 001400h
512 bytes
0015FFh to 001400h
512 bytes
0015FFh to 001400h
Bootloader (BSL)
memory (flash)
512 bytes
0013FFh to 001200h
512 bytes
0013FFh to 001200h
512 bytes
0013FFh to 001200h
512 bytes
0013FFh to 001200h
512 bytes
0011FFh to 001000h
512 bytes
0011FFh to 001000h
512 bytes
0011FFh to 001000h
512 bytes
0011FFh to 001000h
4KB
4KB
4KB
4KB
Peripherals
000FFFh to 000000h 000FFFh to 000000h
000FFFh to 000000h
000FFFh to 000000h
(1) N/A = Not available
(2) Only available on F6659, F6658, F5659, F5658 devices. USB RAM can be used as general-purpose RAM when not used for USB
operation.
(3) Only available on F6459, F6458, F5359, F5358 devices.
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9.6 Bootloader (BSL)
The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the
device memory by the BSL is protected by an user-defined password. For complete description of the features of
the BSL and its implementation, see the MSP430 Flash Device Bootloader (BSL) User's Guide.
9.6.1 USB BSL
The devices MSP430F565x and MSP430F665x come preprogrammed with the USB BSL. Use of the USB BSL
requires external access to six pins (see Table 9-5). In addition to these pins, the application must support
external components necessary for normal USB operation; for example, the proper crystal on XT2IN and
XT2OUT or proper decoupling.
Table 9-5. USB BSL Pin Requirements and
Functions
DEVICE SIGNAL
RST/NMI/SBWTDIO
PU.0/DP
BSL FUNCTION
Entry sequence signal
USB data terminal DP
USB data terminal DM
USB pullup resistor terminal
USB bus power supply
USB ground supply
PU.1/DM
PUR
VBUS
VSSU
Note
The default USB BSL evaluates the logic level of the PUR pin after a BOR reset. If it is pulled high
externally, then the BSL is invoked. Therefore, unless the application is invoking the BSL, it is
important to keep PUR pulled low after a BOR reset, even if BSL or USB is never used. TI
recommends applying a 1-MΩ resistor to ground.
9.6.2 UART BSL
All devices without a USB module (MSP430F535x and MSP430F645x) come preprogrammed with the UART
BSL. A UART BSL is also available for devices with USB module that can be programmed by the user into the
BSL memory by replacing the preprogrammed, factory supplied, USB BSL. Use of the UART BSL requires
external access to six pins (see Table 9-6).
Table 9-6. UART BSL Pin Requirements and
Functions
DEVICE SIGNAL
BSL FUNCTION
Entry sequence signal
Entry sequence signal
Data transmit
RST/NMI/SBWTDIO
TEST/SBWTCK
P1.1
P1.2
VCC
VSS
Data receive
Power supply
Ground supply
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9.7 JTAG Operation
9.7.1 JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. Table 9-7 lists the JTAG pin requirements. For further details on
interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For a
complete description of the features of the BSL and its implementation, see MSP430 Programming With the
JTAG Interface.
Table 9-7. JTAG Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
JTAG clock input
JTAG state control
JTAG data input, TCLK input
JTAG data output
Enable JTAG pins
External reset
PJ.3/TCK
IN
IN
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
IN
OUT
IN
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
IN
Power supply
VSS
Ground supply
9.7.2 Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. Spy-
Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table 9-8 lists the
Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and device
programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the
JTAG interface and its implementation, see MSP430 Programming With the JTAG Interface.
Table 9-8. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
DIRECTION
FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input and output
Power supply
IN
IN, OUT
VSS
Ground supply
9.8 Flash Memory
The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:
•
Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also
called information memory.
•
•
•
Segment A can be locked separately.
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9.9 Memory Integrity Detection (MID)
The MID is an add-on to the flash memory controller. MID provides additional functionality over the regular flash
operation methods. The main purpose of the MID function is to gain higher reliability of flash content and overall
system integrity in harsh environments and in application areas that require such features. The on-chip MID
ROM contains the factory-programmed MID support software. This software package provides several software
functions that allow an application to use all of the features of the MID.
The MID functionality can be enabled for different flash memory ranges. These memory ranges are selectable by
the cw0 parameter of the MID function MidEnable() (see Table 9-9).
Table 9-9. Address Range Coverage of cw0 Parameter of MidEnable() Function
MSP430F6659
MSP430F6459
MSP430F5659
MSP430F5359
MSP430F6658
MSP430F6458
MSP430F5658
MSP430F5358
BITS OF cw0 PARAMETER
cw0.15
cw0.14
cw0.13
cw0.12
cw0.11
cw0.10
cw0.9
cw0.8
cw0.7
cw0.6
cw0.5
cw0.4
cw0.3
cw0.2
cw0.1
cw0.0
087FFFh to 080000h
07FFFFh to 078000h
077FFFh to 070000h
06FFFFh to 068000h
067FFFh to 060000h
05FFFFh to 058000h
057FFFh to 050000h
04FFFFh to 048000h
047FFFh to 040000h
03FFFFh to 038000h
037FFFh to 030000h
02FFFFh to 028000h
027FFFh to 020000h
01FFFFh to 018000h
017FFFh to 010000h
00FFFFh to 008000h
N/A
N/A
N/A
N/A
067FFFh to 060000h
05FFFFh to 058000h
057FFFh to 050000h
04FFFFh to 048000h
047FFFh to 040000h
03FFFFh to 038000h
037FFFh to 030000h
02FFFFh to 028000h
027FFFh to 020000h
01FFFFh to 018000h
017FFFh to 010000h
00FFFFh to 008000h
9.10 RAM
The RAM is made up of n sectors. Each sector can be completely powered down to save leakage; however, all
data are lost. Features of the RAM include:
•
•
•
•
RAM has n sectors. The size of a sector can be found in Section 9.5.
Each sector 0 to n can be complete disabled; however, data retention is lost.
Each sector 0 to n automatically enters low-power retention mode when possible.
For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.
9.11 Backup RAM
The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during
operation from a backup supply if the battery backup system module is implemented.
There are 8 bytes of backup RAM available. It can be word-wise accessed by the control registers BAKMEM0,
BAKMEM1, BAKMEM2, and BAKMEM3.
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9.12 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be managed
using all instructions. For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's
Guide.
9.12.1 Digital I/O
Nine 8-bit I/O ports are implemented: P1 through P9 are complete, and port PJ contains four individual I/O ports.
•
•
•
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Programmable pullup or pulldown on all ports.
Programmable drive strength on all ports.
Edge-selectable interrupt input capability for all the eight bits of ports P1, P2, P3, and P4.
Read and write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PD).
9.12.2 Port Mapping Controller
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2. Table
9-10 lists the available mappings, and Table 9-11 lists the default settings.
Table 9-10. Port Mapping Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
0
PM_NONE
None
DVSS
PM_CBOUT
–
Comparator_B output
1
2
PM_TB0CLK
Timer TB0 clock input
–
PM_ADC12CLK
PM_DMAE0
–
ADC12CLK
–
DMAE0 Input
–
PM_SVMOUT
SVM output
3
Timer TB0 high impedance input
TB0OUTH
PM_TB0OUTH
–
4
5
PM_TB0CCR0B
PM_TB0CCR1B
PM_TB0CCR2B
PM_TB0CCR3B
PM_TB0CCR4B
PM_TB0CCR5B
PM_TB0CCR6B
PM_UCA0RXD
PM_UCA0SOMI
PM_UCA0TXD
PM_UCA0SIMO
PM_UCA0CLK
PM_UCB0STE
PM_UCB0SOMI
PM_UCB0SCL
PM_UCB0SIMO
PM_UCB0SDA
PM_UCB0CLK
PM_UCA0STE
PM_MCLK
Timer TB0 CCR0 capture input CCI0B
Timer TB0 CCR1 capture input CCI1B
Timer TB0 CCR2 capture input CCI2B
Timer TB0 CCR3 capture input CCI3B
Timer TB0 CCR4 capture input CCI4B
Timer TB0 CCR5 capture input CCI5B
Timer TB0 CCR6 capture input CCI6B
Timer TB0: TB0.0 compare output Out0
Timer TB0: TB0.1 compare output Out1
Timer TB0: TB0.2 compare output Out2
Timer TB0: TB0.3 compare output Out3
Timer TB0: TB0.4 compare output Out4
Timer TB0: TB0.5 compare output Out5
Timer TB0: TB0.6 compare output Out6
6
7
8
9
10
USCI_A0 UART RXD (Direction controlled by USCI – input)
11
12
13
14
15
USCI_A0 SPI slave out master in (direction controlled by USCI)
USCI_A0 UART TXD (Direction controlled by USCI – output)
USCI_A0 SPI slave in master out (direction controlled by USCI)
USCI_A0 clock input/output (direction controlled by USCI)
USCI_B0 SPI slave transmit enable (direction controlled by USCI – input)
USCI_B0 SPI slave out master in (direction controlled by USCI)
USCI_B0 I2C clock (open drain and direction controlled by USCI)
USCI_B0 SPI slave in master out (direction controlled by USCI)
USCI_B0 I2C data (open drain and direction controlled by USCI)
USCI_B0 clock input/output (direction controlled by USCI)
16
17
USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)
–
MCLK
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Table 9-10. Port Mapping Mnemonics and Functions (continued)
VALUE
18
PxMAPy MNEMONIC
INPUT PIN FUNCTION
Reserved for test purposes. Do not use this setting.
Reserved for test purposes. Do not use this setting.
OUTPUT PIN FUNCTION
Reserved
19
Reserved
20-30
Reserved
None
DVSS
Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents
when applying analog signals
31 (0FFh)(1)
PM_ANALOG
(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide, and the upper bits are
ignored, which results in a read value of 31.
Table 9-11. Default Mapping
PIN
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
USCI_B0 SPI slave transmit enable (direction controlled by USCI – input),
USCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0STE,
PM_UCA0CLK
P2.0/P2MAP0
USCI_B0 SPI slave in master out (direction controlled by USCI),
USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0SIMO,
PM_UCB0SDA
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
USCI_B0 SPI slave out master in (direction controlled by USCI),
USCI_B0 I2C clock (open drain and direction controlled by USCI)
PM_UCB0SOMI,
PM_UCB0SCL
USCI_B0 clock input/output (direction controlled by USCI),
PM_UCB0CLK,
PM_UCA0STE
USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)
USCI_A0 UART TXD (direction controlled by USCI – output),
USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCA0TXD,
PM_UCA0SIMO
USCI_A0 UART RXD (direction controlled by USCI – input),
USCI_A0 SPI slave out master in (direction controlled by USCI)
PM_UCA0RXD,
PM_UCA0SOMI
P2.6/P2MAP6/ R03
PM_NONE
PM_NONE
–
–
DVSS
DVSS
P2.7/P2MAP7/LCDREF/R13
9.12.3 Oscillator and System Clock
The clock system is supported by the Unified Clock System (UCS) module that includes support for a 32-kHz
watch crystal oscillator (in XT1 LF mode; XT1 HF mode is not supported), an internal very-low-power low-
frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal digitally
controlled oscillator (DCO), and a high-frequency crystal oscillator (XT2). The UCS module is designed to meet
the requirements of both low system cost and low power consumption. The UCS module features digital
frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency
to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turnon clock source
and stabilizes in 3 µs (typical). The UCS module provides the following clock signals:
•
Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the
internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally-
controlled oscillator DCO.
•
•
•
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources available to
ACLK.
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources available to ACLK.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
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9.12.4 Power-Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor
(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power-on and power-off. The SVS
and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply
voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not
automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.
9.12.5 Hardware Multiplier (MPY)
The multiplication operation is supported by a dedicated peripheral module. The module performs operations
with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication as well as signed
and unsigned multiply-and-accumulate operations.
9.12.6 Real-Time Clock (RTC_B)
The RTC_B module can be configured for real-time clock (RTC) or calendar mode providing seconds, minutes,
hours, day of week, day of month, month, and year. Calendar mode integrates an internal calendar which
compensates for months with less than 31 days and includes leap year correction. The RTC_B also supports
flexible alarm functions and offset-calibration hardware. The implementation on this device supports operation in
LPM3.5 mode and operation from a backup supply.
Using the MSP430 RTC_B Module With Battery Backup Supply describes how to use the RTC_B with battery
backup supply functionality to retain the time and keep the RTC counting through loss of main power supply, as
well as how to handle correct reinitialization when the main power supply is restored.
9.12.7 Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
9.12.8 System Module (SYS)
The SYS module handles many of the system functions within the device. These include power-on reset and
power-up clear handling, NMI source selection and management, reset interrupt vector generators, bootloader
entry mechanisms, and configuration management (device descriptors). SYS also includes a data exchange
mechanism using JTAG called a JTAG mailbox that can be used in the application. Table 9-12 lists the SYS
module interrupt vector registers.
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Table 9-12. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER
INTERRUPT EVENT
No interrupt pending
Brownout (BOR)
RST/NMI (BOR)
PMMSWBOR (BOR)
LPM3.5 or LPM4.5 wakeup (BOR)
Security violation (BOR)
SVSL (POR)
WORD ADDRESS
OFFSET
00h
PRIORITY
02h
Highest
04h
06h
08h
0Ah
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
SVMH_OVP (POR)
PMMSWPOR (POR)
WDT time-out (PUC)
WDT key violation (PUC)
KEYV flash key violation (PUC)
Reserved
10h
SYSRSTIV, System Reset
019Eh
12h
14h
16h
18h
1Ah
1Ch
Peripheral area fetch (PUC)
PMM key violation (PUC)
Reserved
1Eh
20h
22h to 3Eh
00h
Lowest
Highest
No interrupt pending
SVMLIFG
02h
SVMHIFG
04h
DLYLIFG
06h
DLYHIFG
08h
SYSSNIV, System NMI
VMAIFG
019Ch
0Ah
JMBINIFG
0Ch
JMBOUTIFG
0Eh
SVMLVLRIFG
10h
SVMHVLRIFG
Reserved
12h
14h to 1Eh
00h
Lowest
Highest
No interrupt pending
NMIIFG
02h
OFIFG
04h
SYSUNIV, User NMI
019Ah
0198h
ACCVIFG
06h
BUSIFG
08h
Reserved
0Ah to 1Eh
00h
Lowest
Highest
No interrupt pending
USB wait state time-out
Reserved
02h
SYSBERRIV, Bus Error
04h
MID error
06h
Reserved
08h to 1Eh
Lowest
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9.12.9 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM.
Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces
system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move
data to or from a peripheral.
The USB timestamp generator also uses the channel 0, 1, and 2 DMA trigger assignments described in Table
9-13. The USB timestamp generator is available only on devices with the USB module (MSP430F565x and
MSP430F665x).
Table 9-13. DMA Trigger Assignments
CHANNEL
TRIGGE
R(1)
0
1
2
3
4
5
0
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA2CCR2 CCIFG
TBCCR0 CCIFG
TBCCR2 CCIFG
Reserved
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved
Reserved
UCA2RXIFG
UCA2TXIFG
UCB2RXIFG
UCB2TXIFG
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB1RXIFG
UCB1TXIFG
ADC12IFGx
DAC12_0IFG
DAC12_1IFG
USB FNRXD (2)
USB ready (2)
MPY ready
DMA5IFG
DMA0IFG
DMA1IFG
DMA2IFG
DMAE0
DMA3IFG
DMA4IFG
(1) Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers do not
cause any DMA trigger event when selected.
(2) Only on devices with peripheral module USB (MSP430F565x and MSP430F665x), otherwise
reserved (MSP430F535x and MSP430F645x).
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9.12.10 Universal Serial Communication Interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3- or 4-pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions,
A and B.
The USCI_An module provides support for SPI (3- or 4-pin), UART, enhanced UART, or IrDA.
The USCI_Bn module provides support for SPI (3- or 4-pin) or I2C.
These MCUs include three complete USCI modules (n = 0 to 2).
9.12.11 Timer TA0
Timer TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 supports multiple
capture/compares, PWM outputs, and interval timing (see Table 9-14). TA0 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/
compare registers.
Table 9-14. Timer TA0 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
MODULE
BLOCK
PZ
ZCA, ZQW
PZ
ZCA, ZQW
34-P1.0
L5-P1.0
TA0CLK
ACLK
SMCLK
TA0CLK
TA0.0
DVSS
TACLK
ACLK
SMCLK
TACLK
CCI0A
CCI0B
GND
Timer
CCR0
NA
NA
34-P1.0
35-P1.1
L5-P1.0
M5-P1.1
35-P1.1
M5-P1.1
TA0
TA0.0
DVSS
DVCC
VCC
36-P1.2
40-P1.6
J6-P1.2
J7-P1.6
TA0.1
TA0.1
CCI1A
CCI1B
36-P1.2
40-P1.6
J6-P1.2
J7-P1.6
CCR1
TA1
TA0.1
ADC12_A (internal)
ADC12SHSx = {1}
DVSS
GND
DVCC
TA0.2
TA0.2
DVSS
DVCC
TA0.3
DVSS
DVSS
DVCC
TA0.4
DVSS
DVSS
DVCC
VCC
CCI2A
CCI2B
GND
37-P1.3
41-P1.7
H6-P1.3
M7-P1.7
37-P1.3
H6-P1.3
M7-P1.7
41-P1.7
CCR2
CCR3
CCR4
TA2
TA3
TA4
TA0.2
TA0.3
TA0.4
VCC
38-P1.4
39-P1.5
M6-P1.4
L6-P1.5
CCI3A
CCI3B
GND
38-P1.4
M6-P1.4
L6-P1.5
VCC
CCI4A
CCI4B
GND
39-P1.5
VCC
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9.12.12 Timer TA1
Timer TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 supports multiple
capture/compares, PWM outputs, and interval timing (see Table 9-15). TA1 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/
compare registers.
Table 9-15. Timer TA1 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
MODULE
BLOCK
PZ
ZCA, ZQW
PZ
ZCA, ZQW
42-P3.0
L7-P3.0
TA1CLK
ACLK
TACLK
ACLK
SMCLK
TACLK
CCI0A
CCI0B
GND
Timer
CCR0
NA
NA
SMCLK
TA1CLK
TA1.0
42-P3.0
43-P3.1
L7-P3.0
H7-P3.1
43-P3.1
44-P3.2
H7-P3.1
M8-P3.2
DVSS
TA0
TA1.0
DVSS
DVCC
VCC
44-P3.2
45-P3.3
M8-P3.2
L8-P3.3
TA1.1
CCI1A
DAC12_A
DAC12_0, DAC12_1
(internal)
CBOUT
(internal)
CCI1B
CCR1
CCR2
TA1
TA2
TA1.1
TA1.2
DVSS
DVCC
TA1.2
GND
VCC
CCI2A
45-P3.3
L8-P3.3
ACLK
(internal)
CCI2B
DVSS
DVCC
GND
VCC
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9.12.13 Timer TA2
Timer TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA2 supports multiple
capture/compares, PWM outputs, and interval timing (see Table 9-16). TA2 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/
compare registers.
Table 9-16. Timer TA2 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
MODULE
BLOCK
PZ
ZCA, ZQW
PZ
ZCA, ZQW
46-P3.4
J8-P3.4
TA2CLK
ACLK
TACLK
ACLK
SMCLK
TACLK
CCI0A
CCI0B
GND
Timer
CCR0
NA
NA
SMCLK
TA2CLK
TA2.0
46-P3.4
47-P3.5
J8-P3.4
M9-P3.5
47-P3.5
48-P3.6
M9-P3.5
L9-P3.6
DVSS
TA0
TA2.0
DVSS
DVCC
VCC
48-P3.6
49-P3.7
L9-P3.6
TA2.1
CCI1A
CBOUT
(internal)
CCI1B
CCR1
CCR2
TA1
TA2
TA2.1
TA2.2
DVSS
DVCC
TA2.2
GND
VCC
M10-P3.7
CCI2A
49-P3.7
M10-P3.7
ACLK
(internal)
CCI2B
DVSS
DVCC
GND
VCC
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9.12.14 Timer TB0
Timer TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. TB0 supports multiple
capture/compares, PWM outputs, and interval timing (see Table 9-17). TB0 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/
compare registers.
Table 9-17. Timer TB0 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
MODULE
BLOCK
PZ
ZCA, ZQW
PZ
ZCA, ZQW
58-P8.0
J11-P8.0
TB0CLK
TB0CLK
P2MAPx(1)
P2MAPx(1)
ACLK
ACLK
Timer
NA
NA
SMCLK
SMCLK
58-P8.0
J11-P8.0
TB0CLK
TB0CLK
P2MAPx(1)
P2MAPx(1)
50-P4.0
J9-P4.0
TB0.0
TB0.0
CCI0A
CCI0B
50-P4.0
J9-P4.0
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
CCR0
CCR1
TB0
TB1
TB0.0
TB0.1
ADC12 (internal)
ADC12SHSx = {2}
DVSS
GND
DVCC
TB0.1
TB0.1
VCC
51-P4.1
M11-P4.1
CCI1A
CCI1B
51-P4.1
P2MAPx(1)
M11-P4.1
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
ADC12 (internal)
ADC12SHSx = {3}
DVSS
GND
DVCC
TB0.2
TB0.2
VCC
52-P4.2
L10-P4.2
CCI2A
CCI2B
52-P4.2
P2MAPx(1)
L10-P4.2
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
DAC12_A
DAC12_0, DAC12_1
(internal)
CCR2
TB2
TB0.2
DVSS
GND
DVCC
TB0.3
TB0.3
DVSS
DVCC
TB0.4
TB0.4
DVSS
DVCC
TB0.5
TB0.5
DVSS
DVCC
TB0.6
TB0.6
DVSS
DVCC
VCC
CCI3A
CCI3B
GND
53-P4.3
M12-P4.3
53-P4.3
M12-P4.3
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
CCR3
CCR4
CCR5
CCR6
TB3
TB4
TB5
TB6
TB0.3
TB0.4
TB0.5
TB0.6
VCC
54-P4.4
L12-P4.4
CCI4A
CCI4B
GND
54-P4.4
L12-P4.4
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
VCC
55-P4.5
L11-P4.5
CCI5A
CCI5B
GND
55-P4.5
L11-P4.5
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
VCC
56-P4.6
K11-P4.6
CCI6A
CCI6B
GND
56-P4.6
K11-P4.6
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
VCC
(1) Timer functions are selectable through the port mapping controller.
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9.12.15 Comparator_B
The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,
battery voltage supervision, and monitoring of external analog signals.
9.12.16 ADC12_A
The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator, and a 16 word conversion-and-control buffer. The conversion-
and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU
intervention.
9.12.17 DAC12_A
The DAC12_A module is a 12-bit R-ladder voltage-output DAC. The DAC12_A may be used in 8-bit or 12-bit
mode, and may be used in conjunction with the DMA controller. When multiple DAC12_A modules are present,
they may be grouped together for synchronous operation.
9.12.18 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used for data
checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
9.12.19 Voltage Reference (REF) Module
The REF module generates all critical reference voltages that can be used by the various analog peripherals in
the device.
9.12.20 LCD_B
The LCD_B driver generates the segment and common signals that are required to drive a liquid crystal display
(LCD). The LCD_B controller has dedicated data memories to hold segment drive information. Common and
segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, and 4-mux LCDs are supported.
The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump. It is
possible to control the level of the LCD voltage, and thus contrast, by software. The module also provides an
automatic blinking capability for individual segments.
The LCD_B module is available only on the MSP430F665x and MSP430F645x devices.
9.12.21 USB Universal Serial Bus
The USB module is a fully integrated USB interface that is compliant with the USB 2.0 specification. The module
supports full-speed operation of control, interrupt, and bulk transfers. The module includes an integrated LDO,
PHY, and PLL. The PLL is highly flexible and supports a wide range of input clock frequencies. When USB RAM
is not used for USB communication, it can be used by the system.
The USB module is available only on the MSP430F665x and MSP430F565x devices.
9.12.22 LDO and PU Port
The integrated 3.3-V power system incorporates an integrated 3.3-V LDO regulator that allows the entire
MSP430 microcontroller to be powered from nominal 5-V LDOI when it is made available for the system.
Alternatively, the power system can supply power only to other components within the system, or it can be
unused altogether.
The Port U Pins (PU.0 and PU.1) function as general-purpose high-current I/O pins. These pins can only be
configured together as either both inputs or both outputs. Port U is supplied by the LDOO rail. If the 3.3-V LDO is
not being used in the system (disabled), the LDOO pin can be supplied externally.
The LDO-PWR module (LDO and PU Port) is available on only the MSP430F645x and MSP430F535x devices.
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9.12.23 Embedded Emulation Module (EEM) (L Version)
The EEM supports real-time in-system debugging. The L version of the EEM has the following features:
•
•
•
•
•
•
•
Eight hardware triggers or breakpoints on memory access
Two hardware triggers or breakpoints on CPU register write access
Up to 10 hardware triggers can be combined to form complex triggers or breakpoints
Two cycle counters
Sequencer
State storage
Clock control on module level
9.12.24 Peripheral File Map
Table 9-18 lists the base register address for each available peripheral.
Table 9-18. Peripherals
MODULE NAME
Special Functions (see Table 9-19)
PMM (see Table 9-20)
BASE ADDRESS
OFFSET ADDRESS RANGE(1)
000h to 01Fh
000h to 010h
000h to 00Fh
000h to 007h
000h to 001h
000h to 001h
000h to 01Fh
000h to 01Fh
000h to 001h
000h to 003h
000h to 007h
000h to 01Fh
000h to 01Fh
000h to 00Bh
000h to 00Bh
000h to 00Bh
000h to 01Fh
000h to 02Eh
000h to 02Eh
000h to 02Eh
000h to 02Eh
000h to 01Fh
000h to 01Fh
000h to 02Fh
000h to 00Fh
000h to 00Ah
000h to 00Ah
000h to 00Ah
000h to 00Ah
000h to 00Ah
000h to 00Ah
000h to 01Fh
000h to 01Fh
0100h
0120h
0140h
0150h
0158h
015Ch
0160h
0180h
01B0h
01C0h
01D0h
0200h
0220h
0240h
0260h
0280h
0320h
0340h
0380h
03C0h
0400h
0480h
04A0h
04C0h
0500h
0510h
0520h
0530h
0540h
0550h
0560h
05C0h
05E0h
Flash Control (see Table 9-21)
CRC16 (see Table 9-22)
RAM Control (see Table 9-23)
Watchdog (see Table 9-24)
UCS (see Table 9-25)
SYS (see Table 9-26)
Shared Reference (see Table 9-27)
Port Mapping Control (see Table 9-28)
Port Mapping Port P2 (see Table 9-28)
Port P1, P2 (see Table 9-29)
Port P3, P4 (see Table 9-30)
Port P5, P6 (see Table 9-31)
Port P7, P8 (see Table 9-32)
Port P9 (see Table 9-33)
Port PJ (see Table 9-34)
Timer TA0 (see Table 9-35)
Timer TA1 (see Table 9-36)
Timer TB0 (see Table 9-37)
Timer TA2 (see Table 9-38)
Battery Backup (see Table 9-39)
RTC_B (see Table 9-40)
32-Bit Hardware Multiplier (see Table 9-41)
DMA General Control (see Table 9-42)
DMA Channel 0 (see Table 9-42)
DMA Channel 1 (see Table 9-42)
DMA Channel 2 (see Table 9-42)
DMA Channel 3 (see Table 9-42)
DMA Channel 4 (see Table 9-42)
DMA Channel 5 (see Table 9-42)
USCI_A0 (see Table 9-43)
USCI_B0 (see Table 9-44)
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Table 9-18. Peripherals (continued)
MODULE NAME
USCI_A1 (see Table 9-45)
USCI_B1 (see Table 9-46)
USCI_A2 (see Table 9-47)
USCI_B2 (see Table 9-48)
ADC12_A (see Table 9-49)
DAC12_A (see Table 9-50)
Comparator_B (see Table 9-51)
USB configuration (see Table 9-52) (2)
USB control (see Table 9-53) (2)
BASE ADDRESS
OFFSET ADDRESS RANGE(1)
000h to 01Fh
0600h
0620h
0640h
0660h
0700h
0780h
08C0h
0900h
0920h
0900h
0A00h
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 03Fh
000h to 01Fh
000h to 00Fh
000h to 014h
000h to 01Fh
LDO-PWR; LDO and Port U configuration (see Table 9-54) (3)
LCD_B control (see Table 9-55) (4)
000h to 014h
000h to 05Fh
(1) For a detailed description of the individual control register offset addresses, see the MSP430F5xx and MSP430F6xx Family User's
Guide.
(2) Only on devices with peripheral module USB.
(3) Only on devices with peripheral module LDO-PWR.
(4) Only on devices with peripheral module LCD_B.
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Table 9-19. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SFR interrupt enable
SFR interrupt flag
SFRIE1
00h
02h
04h
SFRIFG1
SFRRPCR
SFR reset pin control
Table 9-20. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
PMMCTL0
PMMCTL1
SVSMHCTL
SVSMLCTL
PMMIFG
OFFSET
00h
PMM control 0
PMM control 1
02h
SVS high-side control
SVS low-side control
PMM interrupt flags
PMM interrupt enable
PMM power mode 5 control
04h
06h
0Ch
0Eh
PMMIE
PM5CTL0
10h
Table 9-21. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
Flash control 1
Flash control 3
Flash control 4
FCTL1
FCTL3
04h
FCTL4
06h
Table 9-22. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
CRC data input
CRC result
CRC16DI
CRC16INIRES
04h
Table 9-23. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RAM control 0
RCCTL0
00h
Table 9-24. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
REGISTER
OFFSET
Watchdog timer control
WDTCTL
00h
Table 9-25. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
UCSCTL0
UCSCTL1
UCSCTL2
UCSCTL3
UCSCTL4
UCSCTL5
UCSCTL6
UCSCTL7
UCSCTL8
OFFSET
00h
UCS control 0
UCS control 1
UCS control 2
UCS control 3
UCS control 4
UCS control 5
UCS control 6
UCS control 7
UCS control 8
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
Table 9-26. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
System control
SYSCTL
Bootloader configuration area
SYSBSLC
02h
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Table 9-26. SYS Registers (Base Address: 0180h) (continued)
REGISTER DESCRIPTION
REGISTER
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSBERRIV
SYSUNIV
OFFSET
06h
JTAG mailbox control
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
Bus error vector generator
User NMI vector generator
08h
0Ah
0Ch
0Eh
18h
1Ah
System NMI vector generator
Reset vector generator
SYSSNIV
1Ch
1Eh
SYSRSTIV
Table 9-27. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Shared reference control
REFCTL
00h
Table 9-28. Port Mapping Registers
(Base Address of Port Mapping Control: 01C0h, Port P4: 01D0h)
REGISTER DESCRIPTION
REGISTER
PMAPPWD
PMAPCTL
P2MAP0
P2MAP1
P2MAP2
P2MAP3
P2MAP4
P2MAP5
P2MAP6
P2MAP7
OFFSET
00h
Port mapping password
Port mapping control
Port P2.0 mapping
Port P2.1 mapping
Port P2.2 mapping
Port P2.3 mapping
Port P2.4 mapping
Port P2.5 mapping
Port P2.6 mapping
Port P2.7 mapping
02h
00h
01h
02h
03h
04h
05h
06h
07h
Table 9-29. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
Port P1 input
P1IN
Port P1 output
P1OUT
P1DIR
P1REN
P1DS
02h
Port P1 direction
04h
Port P1 resistor enable
Port P1 drive strength
Port P1 selection
06h
08h
P1SEL
P1IV
0Ah
0Eh
18h
Port P1 interrupt vector word
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
P1IES
P1IE
1Ah
1Ch
01h
P1IFG
P2IN
Port P2 output
P2OUT
P2DIR
P2REN
P2DS
03h
Port P2 direction
05h
Port P2 resistor enable
Port P2 drive strength
Port P2 selection
07h
09h
P2SEL
0Bh
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Table 9-29. Port P1, P2 Registers (Base Address: 0200h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P2 interrupt vector word
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
P2IV
1Eh
19h
1Bh
1Dh
P2IES
P2IE
P2IFG
Table 9-30. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
02h
04h
06h
08h
0Ah
0Eh
18h
1Ah
1Ch
01h
03h
05h
07h
09h
0Bh
1Eh
19h
1Bh
1Dh
Port P3 input
P3IN
Port P3 output
P3OUT
P3DIR
P3REN
P3DS
Port P3 direction
Port P3 resistor enable
Port P3 drive strength
Port P3 selection
P3SEL
P3IV
Port P3 interrupt vector word
Port P3 interrupt edge select
Port P3 interrupt enable
Port P3 interrupt flag
Port P4 input
P3IES
P3IE
P3IFG
P4IN
Port P4 output
P4OUT
P4DIR
P4REN
P4DS
Port P4 direction
Port P4 resistor enable
Port P4 drive strength
Port P4 selection
P4SEL
P4IV
Port P4 interrupt vector word
Port P4 interrupt edge select
Port P4 interrupt enable
Port P4 interrupt flag
P4IES
P4IE
P4IFG
Table 9-31. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
Port P5 input
P5IN
Port P5 output
P5OUT
P5DIR
P5REN
P5DS
02h
Port P5 direction
Port P5 resistor enable
Port P5 drive strength
Port P5 selection
Port P6 input
04h
06h
08h
P5SEL
P6IN
0Ah
01h
Port P6 output
P6OUT
P6DIR
P6REN
P6DS
03h
Port P6 direction
Port P6 resistor enable
Port P6 drive strength
Port P6 selection
05h
07h
09h
P6SEL
0Bh
Table 9-32. Port P7, P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
Port P7 input
P7IN
Port P7 output
P7OUT
02h
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Table 9-32. Port P7, P8 Registers (Base Address: 0260h) (continued)
REGISTER DESCRIPTION
REGISTER
P7DIR
P7REN
P7DS
OFFSET
04h
Port P7 direction
Port P7 resistor enable
Port P7 drive strength
Port P7 selection
Port P8 input
06h
08h
P7SEL
P8IN
0Ah
01h
Port P8 output
P8OUT
P8DIR
P8REN
P8DS
03h
Port P8 direction
05h
Port P8 resistor enable
Port P8 drive strength
Port P8 selection
07h
09h
P8SEL
0Bh
Table 9-33. Port P9 Register (Base Address: 0280h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
Port P9 input
P9IN
Port P9 output
P9OUT
P9DIR
P9REN
P9DS
02h
Port P9 direction
Port P9 resistor enable
Port P9 drive strength
Port P9 selection
04h
06h
08h
P9SEL
0Ah
Table 9-34. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
Port PJ input
PJIN
Port PJ output
PJOUT
PJDIR
02h
Port PJ direction
Port PJ resistor enable
Port PJ drive strength
04h
PJREN
PJDS
06h
08h
Table 9-35. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
TA0 control
TA0CTL
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Capture/compare control 3
Capture/compare control 4
TA0 counter
TA0CCTL0
TA0CCTL1
TA0CCTL2
TA0CCTL3
TA0CCTL4
TA0R
02h
04h
06h
08h
0Ah
10h
Capture/compare 0
Capture/compare 1
Capture/compare 2
Capture/compare 3
Capture/compare 4
TA0 expansion 0
TA0CCR0
TA0CCR1
TA0CCR2
TA0CCR3
TA0CCR4
TA0EX0
12h
14h
16h
18h
1Ah
20h
TA0 interrupt vector
TA0IV
2Eh
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Table 9-36. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA1 control
TA1CTL
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA1 counter
TA1CCTL0
TA1CCTL1
TA1CCTL2
TA1R
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA1 expansion 0
TA1CCR0
TA1CCR1
TA1CCR2
TA1EX0
TA1 interrupt vector
TA1IV
Table 9-37. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Eh
TB0 control
TB0CTL
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Capture/compare control 3
Capture/compare control 4
Capture/compare control 5
Capture/compare control 6
TB0 counter
TB0CCTL0
TB0CCTL1
TB0CCTL2
TB0CCTL3
TB0CCTL4
TB0CCTL5
TB0CCTL6
TB0R
Capture/compare 0
TB0CCR0
TB0CCR1
TB0CCR2
TB0CCR3
TB0CCR4
TB0CCR5
TB0CCR6
TB0EX0
Capture/compare 1
Capture/compare 2
Capture/compare 3
Capture/compare 4
Capture/compare 5
Capture/compare 6
TB0 expansion 0
TB0 interrupt vector
TB0IV
Table 9-38. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
TA2 control
TA2CTL
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA2 counter
TA2CCTL0
TA2CCTL1
TA2CCTL2
TA2R
02h
04h
06h
10h
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA2 expansion 0
TA2CCR0
TA2CCR1
TA2CCR2
TA2EX0
12h
14h
16h
20h
TA2 interrupt vector
TA2IV
2Eh
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Table 9-39. Battery Backup Registers (Base Address: 0480h)
REGISTER DESCRIPTION
REGISTER
BAKMEM0
BAKMEM1
BAKMEM2
BAKMEM3
BAKCTL
OFFSET
00h
Battery backup memory 0
Battery backup memory 1
Battery backup memory 2
Battery backup memory 3
Battery backup control
Battery charger control
02h
04h
06h
1Ch
BAKCHCTL
1Eh
Table 9-40. Real-Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
RTCCTL0
RTCCTL1
RTCCTL2
RTCCTL3
RTCPS0CTL
RTCPS1CTL
RTCPS0
OFFSET
00h
01h
02h
03h
08h
0Ah
0Ch
0Dh
0Eh
10h
11h
RTC control 0
RTC control 1
RTC control 2
RTC control 3
RTC prescaler 0 control
RTC prescaler 1 control
RTC prescaler 0
RTC prescaler 1
RTC interrupt vector word
RTC seconds
RTCPS1
RTCIV
RTCSEC
RTC minutes
RTCMIN
RTC hours
RTCHOUR
RTCDOW
RTCDAY
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Eh
RTC day of week
RTC days
RTC month
RTCMON
RTCYEARL
RTCYEARH
RTCAMIN
RTCAHOUR
RTCADOW
RTCADAY
BIN2BCD
BCD2BIN
RTC year low
RTC year high
RTC alarm minutes
RTC alarm hours
RTC alarm day of week
RTC alarm days
Binary-to-BCD conversion
BCD-to-binary conversion
Table 9-41. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
16-bit operand 1 – multiply
MPY
16-bit operand 1 – signed multiply
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
MPYS
02h
MAC
04h
MACS
06h
OP2
08h
16 × 16 result low word
RESLO
RESHI
SUMEXT
MPY32L
MPY32H
MPYS32L
0Ah
0Ch
0Eh
10h
16 × 16 result high word
16 × 16 sum extension
32-bit operand 1 – multiply low word
32-bit operand 1 – multiply high word
32-bit operand 1 – signed multiply low word
12h
14h
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Table 9-41. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h) (continued)
REGISTER DESCRIPTION
REGISTER
MPYS32H
MAC32L
MAC32H
MACS32L
MACS32H
OP2L
OFFSET
32-bit operand 1 – signed multiply high word
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
32-bit operand 1 – multiply accumulate low word
32-bit operand 1 – multiply accumulate high word
32-bit operand 1 – signed multiply accumulate low word
32-bit operand 1 – signed multiply accumulate high word
32-bit operand 2 – low word
32-bit operand 2 – high word
OP2H
32 × 32 result 0 – least significant word
32 × 32 result 1
RES0
RES1
32 × 32 result 2
RES2
32 × 32 result 3 – most significant word
MPY32 control 0
RES3
MPY32CTL0
Table 9-42. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA
Channel 4: 0550h, DMA Channel 5: 0560h)
REGISTER DESCRIPTION
REGISTER
DMACTL0
DMACTL1
DMACTL2
DMACTL3
DMACTL4
DMAIV
OFFSET
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
DMA general control: DMA module control 0
DMA general control: DMA module control 1
DMA general control: DMA module control 2
DMA general control: DMA module control 3
DMA general control: DMA module control 4
DMA general control: DMA interrupt vector
DMA channel 0 control
DMA0CTL
DMA0SAL
DMA0SAH
DMA0DAL
DMA0DAH
DMA0SZ
DMA channel 0 source address low
DMA channel 0 source address high
DMA channel 0 destination address low
DMA channel 0 destination address high
DMA channel 0 transfer size
DMA channel 1 control
DMA1CTL
DMA1SAL
DMA1SAH
DMA1DAL
DMA1DAH
DMA1SZ
DMA channel 1 source address low
DMA channel 1 source address high
DMA channel 1 destination address low
DMA channel 1 destination address high
DMA channel 1 transfer size
DMA channel 2 control
DMA2CTL
DMA2SAL
DMA2SAH
DMA2DAL
DMA2DAH
DMA2SZ
DMA channel 2 source address low
DMA channel 2 source address high
DMA channel 2 destination address low
DMA channel 2 destination address high
DMA channel 2 transfer size
DMA channel 3 control
DMA3CTL
DMA3SAL
DMA3SAH
DMA3DAL
DMA3DAH
DMA channel 3 source address low
DMA channel 3 source address high
DMA channel 3 destination address low
DMA channel 3 destination address high
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Table 9-42. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA
Channel 4: 0550h, DMA Channel 5: 0560h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
0Ah
00h
DMA channel 3 transfer size
DMA channel 4 control
DMA3SZ
DMA4CTL
DMA4SAL
DMA4SAH
DMA4DAL
DMA4DAH
DMA4SZ
DMA channel 4 source address low
DMA channel 4 source address high
DMA channel 4 destination address low
DMA channel 4 destination address high
DMA channel 4 transfer size
02h
04h
06h
08h
0Ah
00h
DMA channel 5 control
DMA5CTL
DMA5SAL
DMA5SAH
DMA5DAL
DMA5DAH
DMA5SZ
DMA channel 5 source address low
DMA channel 5 source address high
DMA channel 5 destination address low
DMA channel 5 destination address high
DMA channel 5 transfer size
02h
04h
06h
08h
0Ah
Table 9-43. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
UCA0CTL0
UCA0CTL1
UCA0BR0
OFFSET
00h
USCI control 0
USCI control 1
01h
USCI baud rate 0
06h
USCI baud rate 1
UCA0BR1
07h
USCI modulation control
USCI status
UCA0MCTL
UCA0STAT
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
UCA0IRTCTL
UCA0IRRCTL
UCA0IE
08h
0Ah
0Ch
0Eh
10h
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
12h
13h
1Ch
1Dh
1Eh
UCA0IFG
UCA0IV
Table 9-44. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
REGISTER
UCB0CTL0
UCB0CTL1
UCB0BR0
OFFSET
00h
USCI synchronous control 0
USCI synchronous control 1
USCI synchronous bit rate 0
USCI synchronous bit rate 1
USCI synchronous status
01h
06h
UCB0BR1
07h
UCB0STAT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA
UCB0I2CSA
UCB0IE
0Ah
0Ch
0Eh
10h
USCI synchronous receive buffer
USCI synchronous transmit buffer
USCI I2C own address
USCI I2C slave address
USCI interrupt enable
12h
1Ch
1Dh
USCI interrupt flags
UCB0IFG
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Table 9-44. USCI_B0 Registers (Base Address: 05E0h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI interrupt vector word
UCB0IV
1Eh
Table 9-45. USCI_A1 Registers (Base Address: 0600h)
REGISTER DESCRIPTION
REGISTER
UCA1CTL0
UCA1CTL1
UCA1BR0
OFFSET
00h
USCI control 0
USCI control 1
01h
USCI baud rate 0
06h
USCI baud rate 1
UCA1BR1
07h
USCI modulation control
USCI status
UCA1MCTL
UCA1STAT
UCA1RXBUF
UCA1TXBUF
UCA1ABCTL
UCA1IRTCTL
UCA1IRRCTL
UCA1IE
08h
0Ah
0Ch
0Eh
10h
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
12h
13h
1Ch
1Dh
1Eh
UCA1IFG
UCA1IV
Table 9-46. USCI_B1 Registers (Base Address: 0620h)
REGISTER DESCRIPTION
REGISTER
UCB1CTL0
UCB1CTL1
UCB1BR0
UCB1BR1
UCB1STAT
UCB1RXBUF
UCB1TXBUF
UCB1I2COA
UCB1I2CSA
UCB1IE
OFFSET
00h
USCI synchronous control 0
USCI synchronous control 1
USCI synchronous bit rate 0
USCI synchronous bit rate 1
USCI synchronous status
01h
06h
07h
0Ah
0Ch
0Eh
10h
USCI synchronous receive buffer
USCI synchronous transmit buffer
USCI I2C own address
USCI I2C slave address
USCI interrupt enable
12h
1Ch
1Dh
1Eh
USCI interrupt flags
UCB1IFG
USCI interrupt vector word
UCB1IV
Table 9-47. USCI_A2 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
UCA2CTL0
UCA2CTL1
UCA2BR0
OFFSET
00h
USCI control 0
USCI control 1
01h
USCI baud rate 0
USCI baud rate 1
USCI modulation control
USCI status
06h
UCA2BR1
07h
UCA2MCTL
UCA2STAT
UCA2RXBUF
UCA2TXBUF
UCA2ABCTL
UCA2IRTCTL
UCA2IRRCTL
08h
0Ah
0Ch
0Eh
10h
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
12h
13h
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Table 9-47. USCI_A2 Registers (Base Address: 0640h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
1Ch
USCI interrupt enable
USCI interrupt flags
UCA2IE
UCA2IFG
UCA2IV
1Dh
USCI interrupt vector word
1Eh
Table 9-48. USCI_B2 Registers (Base Address: 0660h)
REGISTER DESCRIPTION
REGISTER
UCB2CTL0
UCB2CTL1
UCB2BR0
UCB2BR1
UCB2STAT
UCB2RXBUF
UCB2TXBUF
UCB2I2COA
UCB2I2CSA
UCB2IE
OFFSET
00h
USCI synchronous control 0
USCI synchronous control 1
USCI synchronous bit rate 0
USCI synchronous bit rate 1
USCI synchronous status
01h
06h
07h
0Ah
0Ch
0Eh
10h
USCI synchronous receive buffer
USCI synchronous transmit buffer
USCI I2C own address
USCI I2C slave address
USCI interrupt enable
12h
1Ch
1Dh
1Eh
USCI interrupt flags
UCB2IFG
USCI interrupt vector word
UCB2IV
Table 9-49. ADC12_A Registers (Base Address: 0700h)
REGISTER DESCRIPTION
REGISTER
ADC12CTL0
ADC12CTL1
ADC12CTL2
ADC12IFG
OFFSET
00h
02h
04h
0Ah
0Ch
0Eh
10h
11h
ADC12 control 0
ADC12 control 1
ADC12 control 2
Interrupt flag
Interrupt enable
ADC12IE
Interrupt vector word
ADC memory control 0
ADC memory control 1
ADC memory control 2
ADC memory control 3
ADC memory control 4
ADC memory control 5
ADC memory control 6
ADC memory control 7
ADC memory control 8
ADC memory control 9
ADC memory control 10
ADC memory control 11
ADC memory control 12
ADC memory control 13
ADC memory control 14
ADC memory control 15
Conversion memory 0
Conversion memory 1
Conversion memory 2
ADC12IV
ADC12MCTL0
ADC12MCTL1
ADC12MCTL2
ADC12MCTL3
ADC12MCTL4
ADC12MCTL5
ADC12MCTL6
ADC12MCTL7
ADC12MCTL8
ADC12MCTL9
ADC12MCTL10
ADC12MCTL11
ADC12MCTL12
ADC12MCTL13
ADC12MCTL14
ADC12MCTL15
ADC12MEM0
ADC12MEM1
ADC12MEM2
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
22h
24h
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Table 9-49. ADC12_A Registers (Base Address: 0700h) (continued)
REGISTER DESCRIPTION
REGISTER
ADC12MEM3
ADC12MEM4
ADC12MEM5
ADC12MEM6
ADC12MEM7
ADC12MEM8
ADC12MEM9
ADC12MEM10
ADC12MEM11
ADC12MEM12
ADC12MEM13
ADC12MEM14
ADC12MEM15
OFFSET
Conversion memory 3
Conversion memory 4
Conversion memory 5
Conversion memory 6
Conversion memory 7
Conversion memory 8
Conversion memory 9
Conversion memory 10
Conversion memory 11
Conversion memory 12
Conversion memory 13
Conversion memory 14
Conversion memory 15
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
36h
38h
3Ah
3Ch
3Eh
Table 9-50. DAC12_A Registers (Base Address: 0780h)
REGISTER DESCRIPTION
REGISTER
DAC12_0CTL0
DAC12_0CTL1
DAC12_0DAT
OFFSET
00h
DAC12_A channel 0 control 0
DAC12_A channel 0 control 1
DAC12_A channel 0 data
02h
04h
DAC12_A channel 0 calibration control
DAC12_A channel 0 calibration data
DAC12_A channel 1 control 0
DAC12_A channel 1 control 1
DAC12_A channel 1 data
DAC12_0CALCTL
DAC12_0CALDAT
DAC12_1CTL0
DAC12_1CTL1
DAC12_1DAT
06h
08h
10h
12h
14h
DAC12_A channel 1 calibration control
DAC12_A channel 1 calibration data
DAC12_A interrupt vector word
DAC12_1CALCTL
DAC12_1CALDAT
DAC12IV
16h
18h
1Eh
Table 9-51. Comparator_B Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
CBCTL0
CBCTL1
CBCTL2
CBCTL3
CBINT
OFFSET
00h
Comp_B control 0
Comp_B control 1
Comp_B control 2
Comp_B control 3
Comp_B interrupt
02h
04h
06h
0Ch
Comp_B interrupt vector word
CBIV
0Eh
Table 9-52. USB Configuration Registers (Base Address: 0900h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
USB key/ID
USBKEYID
USB module configuration
USB PHY control
USBCNF
02h
USBPHYCTL
USBPWRCTL
USBPWRVSR
USBPLLCTL
USBPLLDIV
04h
USB power control
USB power voltage setting
USB PLL control
08h
0Ah
10h
USB PLL divider
12h
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Table 9-52. USB Configuration Registers (Base Address: 0900h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
USB PLL interrupts
USBPLLIR
14h
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Table 9-53. USB Control Registers (Base Address: 0920h)
REGISTER DESCRIPTION
REGISTER
USBIEPCNF_0
USBIEPCNT_0
USBOEPCNFG_0
USBOEPCNT_0
USBIEPIE
OFFSET
Input endpoint_0 configuration
00h
01h
02h
03h
0Eh
0Fh
10h
11h
12h
16h
18h
1Ah
1Ch
1Dh
1Eh
1Fh
Input endpoint_0 byte count
Output endpoint_0 configuration
Output endpoint _0 byte count
Input endpoint interrupt enables
Output endpoint interrupt enables
Input endpoint interrupt flags
Output endpoint interrupt flags
USB interrupt vector
USBOEPIE
USBIEPIFG
USBOEPIFG
USBIV
USB maintenance
USBMAINT
USBTSREG
USBFN
Timestamp
USB frame number
USB control
USBCTL
USB interrupt enables
USB interrupt flags
USBIE
USBIFG
Function address
USBFUNADR
Table 9-54. LDO and Port U Configuration Registers (Base Address: 0900h)
REGISTER DESCRIPTION
REGISTER
LDOKEYID
PUCTL
OFFSET
00h
LDO key/ID
PU port control
LDO power control
04h
LDOPWRCTL
08h
Table 9-55. LCD_B Registers (Base Address: 0A00h)
REGISTER DESCRIPTION
REGISTER
LCDBCTL0
LCDBCTL1
LCDBBLKCTL
LCDBMEMCTL
LCDBVCTL
LCDBPCTL0
LCDBPCTL1
LCDBPCTL2
LCDBCTL0
LCDBIV
OFFSET
000h
002h
004h
006h
008h
00Ah
00Ch
00Eh
012h
01Eh
020h
021h
⋮
LCD_B control 0
LCD_B control 1
LCD_B blinking control
LCD_B memory control
LCD_B voltage control
LCD_B port control 0
LCD_B port control 1
LCD_B port control 2
LCD_B charge pump control
LCD_B interrupt vector word
LCD_B memory 1
LCDM1
LCD_B memory 2
LCDM2
⋮
⋮
LCD_B memory 22
LCD_B blinking memory 1
LCD_B blinking memory 2
⋮
LCDM22
035h
040h
041h
⋮
LCDBM1
LCDBM2
⋮
LCD_B blinking memory 22
LCDBM22
055h
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9.13 Input/Output Diagrams
9.13.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
Figure 9-2 shows the port diagram. Table 9-56 summarizes selection of the pin functions.
Pad Logic
S32...S39
LCDS32...LCDS39
P1REN.x
DVSS
DVCC
0
1
1
P1DIR.x
0
1
Direction
0: Input
1: Output
P1OUT.x
0
1
Module X OUT
P1.0/TA0CLK/ACLK/S39
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.3/TA0.2/S36
P1.4/TA0.3/S35
P1.5/TA0.4/S34
P1.6/TA0.1/S33
P1.7/TA0.2/S32
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
Bus
Keeper
EN
D
Module X IN
P1IRQ.x
P1IE.x
EN
Q
P1IFG.x
Set
P1SEL.x
P1IES.x
Interrupt
Edge
Select
Figure 9-2. Port P1 (P1.0 to P1.7) Diagram
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Table 9-56. Port P1 (P1.0 to P1.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
LCDS32...
LCDS39
P1DIR.x
P1SEL.x
P1.0 (I/O)
I: 0; O: 1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
Timer TA0.TA0CLK
0
P1.0/TA0CLK/ACLK/
S39
0
ACLK
1
S39
X
P1.1 (I/O)
I: 0; O: 1
Timer TA0.CCI0A capture input
Timer TA0.0 output
S38
0
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.3/TA0.2/S36
P1.4/TA0.3/S35
P1.5/TA0.4/S34
P1.6/TA0.1/S33
1
2
3
4
5
6
7
1
X
P1.2 (I/O)
I: 0; O: 1
Timer TA0.CCI1A capture input
Timer TA0.1 output
S37
0
1
X
P1.3 (I/O)
I: 0; O: 1
Timer TA0.CCI2A capture input
Timer TA0.2 output
S36
0
1
X
P1.4 (I/O)
I: 0; O: 1
Timer TA0.CCI3A capture input
Timer TA0.3 output
S35
0
1
X
P1.5 (I/O)
I: 0; O: 1
Timer TA0.CCI4A capture input
Timer TA0.4 output
S34
0
1
X
P1.6 (I/O)
I: 0; O: 1
Timer TA0.CCI1B capture input
Timer TA0.1 output
S33
0
1
X
P1.7 (I/O)
I: 0; O: 1
Timer TA0.CCI2B capture input
Timer TA0.2 output
S32
0
1
X
P1.7/TA0.2/S32
(1) X = Don't care
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9.13.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
Figure 9-3 shows the port diagram. Table 9-57 summarizes selection of the pin functions.
Pad Logic
To LCD_B
From LCD_B
P2REN.x
DVSS
DVCC
0
1
1
P2DIR.x
0
1
Direction
0: Input
1: Output
From Port Mapping
P2OUT.x
0
1
From Port Mapping
P2.0/P2MAP0
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2.4/P2MAP4
P2.5/P2MAP5
P2IN.x
P2.6/P2MAP6/R03
P2.7/P2MAP7/LCDREF/R13
From Port Mapping
EN
D
To Port Mapping
P2IRQ.x
P2IE.x
EN
Q
P2IFG.x
Set
P2SEL.x
P2IES.x
Interrupt
Edge
Select
Figure 9-3. Port P2 (P2.0 to P2.7) Diagram
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Table 9-57. Port P2 (P2.0 to P2.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P2.x)
P2.0/P2MAP0
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
x
0
1
2
3
4
5
FUNCTION
P2DIR.x
P2SEL.x
P2MAPx
P2.0 (I/O)
I: 0; O: 1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
1
Mapped secondary digital function
P2.1 (I/O)
X
≤ 19
I: 0; O: 1
Mapped secondary digital function
P2.2 (I/O)
X
≤ 19
I: 0; O: 1
Mapped secondary digital function
P2.3 (I/O)
X
≤ 19
I: 0; O: 1
Mapped secondary digital function
P2.4 (I/O)
X
≤ 19
I: 0; O: 1
Mapped secondary digital function
P2.5 (I/O
X
≤ 19
I: 0; O: 1
Mapped secondary digital function
P2.6 (I/O)
X
≤ 19
I: 0; O: 1
P2.6/P2MAP6/R03
6 Mapped secondary digital function
X
≤ 19
= 31
R03
X
P2.7 (I/O)
I: 0; O: 1
P2.7/P2MAP7/
LCDREF/R13
7 Mapped secondary digital function
LCDREF/R13
X
X
≤ 19
= 31
(1) X = Don't care
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9.13.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
Figure 9-4 shows the port diagram. Table 9-58 summarizes selection of the pin functions.
Pad Logic
S24...S31
LCDS24...LCDS31
P3REN.x
DVSS
DVCC
0
1
1
P3DIR.x
0
1
Direction
0: Input
1: Output
P3OUT.x
0
1
Module X OUT
P3.0/TA1CLK/CBOUT/S31
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
P3.3/TA1.2/S28
P3.4/TA2CLK/SMCLK/S27
P3.5/TA2.0/S26
P3.6/TA2.1/S25
Bus
Keeper
EN
D
P3.7/TA2.2/S24
Module X IN
P3IRQ.x
P3IE.x
EN
Q
P3IFG.x
Set
P3SEL.x
P3IES.x
Interrupt
Edge
Select
Figure 9-4. Port P3 (P3.0 to P3.7) Diagram
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Table 9-58. Port P3 (P3.0 to P3.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P3.x)
x
FUNCTION
LCDS24...
LCDS31
P3DIR.x
P3SEL.x
P3.0 (I/O)
I: 0; O: 1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
0
1
Timer TA1.TA1CLK
0
P3.0/TA1CLK/
CBOUT/S31
0
CBOUT
1
S31
X
P3.1 (I/O)
I: 0; O: 1
Timer TA1.CCI0A capture input
0
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P3.3/TA1.2/S28
1
2
3
4
5
6
7
Timer TA1.0 output
1
S30
X
P3.2 (I/O)
I: 0; O: 1
Timer TA1.CCI1A capture input
0
Timer TA1.1 output
1
S29
X
P3.3 (I/O)
I: 0; O: 1
Timer TA1.CCI2A capture input
0
Timer TA1.2 output
1
S28
X
P3.4 (I/O)
I: 0; O: 1
Timer TA2.TA2CLK
0
P3.4/TA2CLK/
SMCLK/S27
SMCLK
1
S27
X
P3.5 (I/O)
I: 0; O: 1
Timer TA2.CCI0A capture input
Timer TA2.0 output
S26
0
P3.5/TA2.0/S26
P3.6/TA2.1/S25
1
X
P3.6 (I/O)
I: 0; O: 1
Timer TA2.CCI1A capture input
Timer TA2.1 output
S25
0
1
X
P3.7 (I/O)
I: 0; O: 1
Timer TA2.CCI2A capture input
Timer TA2.2 output
S24
0
1
X
P3.7/TA2.2/S24
(1) X = Don't care
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9.13.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
Figure 9-5 shows the port diagram. Table 9-59 summarizes selection of the pin functions.
Pad Logic
S16...S23
LCDS16...LCDS23
P4REN.x
DVSS
DVCC
0
1
1
P4DIR.x
0
1
Direction
0: Input
1: Output
P4OUT.x
0
1
Module X OUT
P4.0/TB0.0/S23
P4.1/TB0.1/S22
P4.2/TB0.2/S21
P4.3/TB0.3/S20
P4.4/TB0.4/S19
P4.5/TB0.5/S18
P4DS.x
0: Low drive
1: High drive
P4SEL.x
P4IN.x
P4.6/TB0.6/S17
P4.7/TB0OUTH/SVMOUT/S16
Bus
Keeper
EN
D
Module X IN
P4IRQ.x
P4IE.x
EN
Q
P4IFG.x
Set
P4SEL.x
P4IES.x
Interrupt
Edge
Select
Figure 9-5. Port P4 (P4.0 to P4.7) Diagram
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Table 9-59. Port P4 (P4.0 to P4.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P4.x)
x
FUNCTION
LCDS16...
LCDS23
P4DIR.x
P4SEL.x
P4.0 (I/O)
I: 0; O: 1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
Timer TB0.CCI0A capture input
Timer TB0.0 output(2)
S23
0
P4.0/TB0.0/S23
0
1
X
P4.1 (I/O)
I: 0; O: 1
Timer TB0.CCI1A capture input
Timer TB0.1 output(2)
S22
0
P4.1/TB0.1/S22
P4.2/TB0.2/S21
P4.3/TB0.3/S20
P4.4/TB0.4/S19
P4.5/TB0.5/S18
P4.6/TB0.6/S17
1
2
3
4
5
6
7
1
X
P4.2 (I/O)
I: 0; O: 1
Timer TB0.CCI2A capture input
Timer TB0.2 output(2)
S21
0
1
X
P4.3 (I/O)
I: 0; O: 1
Timer TB0.CCI3A capture input
Timer TB0.3 output(2)
S20
0
1
X
P4.4 (I/O)
I: 0; O: 1
Timer TB0.CCI4A capture input
Timer TB0.4 output(2)
S19
0
1
X
P4.5 (I/O)
I: 0; O: 1
Timer TB0.CCI5A capture input
Timer TB0.5 output(2)
S18
0
1
X
P4.6 (I/O)
I: 0; O: 1
Timer TB0.CCI6A capture input
Timer TB0.6 output(2)
S17
0
1
X
P4.7 (I/O)
I: 0; O: 1
Timer TB0.TB0OUTH
SVMOUT
0
1
X
P4.7/TB0OUTH/
SVMOUT/S16
S16
(1) X = Don't care
(2) Setting TB0OUTH causes all Timer_B configured outputs to be set to high impedance.
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9.13.5 Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
Figure 9-6 shows the port diagram. Table 9-60 summarizes selection of the pin functions.
Pad Logic
To/From
Reference
P5REN.x
DVSS
DVCC
0
1
1
P5DIR.x
0
1
P5OUT.x
0
1
Module X OUT
P5.0/VREF+/VeREF+
P5.1/VREF–/VeREF–
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
EN
D
Module X IN
Figure 9-6. Port P5 (P5.0 and P5.1) Diagram
Table 9-60. Port P5 (P5.0 and P5.1) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL.x
REFOUT
P5.0 (I/O)(2)
VeREF+(3)
VREF+(4)
I: 0; O: 1
0
1
1
0
1
1
X
0
1
X
0
1
P5.0/VREF+/VeREF+
0
X
X
P5.1 (I/O)(2)
VeREF–(5)
VREF–(6)
I: 0; O: 1
P5.1/VREF–/VeREF–
1
X
X
(1) X = Don't care
(2) Default condition
(3) Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A, Comparator_B, or
DAC12_A.
(4) Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. The ADC12_A, VREF+ reference is available at the pin.
(5) Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A, Comparator_B, or
DAC12_A.
(6) Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. The ADC12_A, VREF– reference is available at the pin.
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9.13.6 Port P5 (P5.2 to P5.7) Input/Output With Schmitt Trigger
Figure 9-7 shows the port diagram. Table 9-61 summarizes selection of the pin functions.
Pad Logic
S40...S42
LCDS40...LCDS42
P5REN.x
DVSS
DVCC
0
1
1
P5DIR.x
0
1
Direction
0: Input
1: Output
P5OUT.x
0
1
Module X OUT
P5.2/R23
P5DS.x
0: Low drive
1: High drive
P5.3/COM1/S42
P5.4/COM2/S41
P5.5/COM3/S40
P5.6/ADC12CLK/DMAE0
P5.7/RTCCLK
P5SEL.x
P5IN.x
Bus
Keeper
EN
D
Module X IN
Figure 9-7. Port P5 (P5.2 to P5.7) Diagram
Table 9-61. Port P5 (P5.2 to P5.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
LCDS40...
LCDS42
P5DIR.x
P5SEL.x
P5.2 (I/O)
R23
I: 0; O: 1
0
1
0
1
0
0
1
0
0
1
0
0
1
1
0
N/A
N/A
0
P5.2/R23
2
X
P5.3 (I/O)
COM1
I: 0; O: 1
P5.3/COM1/S42
P5.4/COM2/S41
P5.5/COM3/S40
3
4
5
X
X
S42
X
1
P5.4 (I/O)
COM2
I: 0; O: 1
0
X
X
S41
X
1
P5.5 (I/O)
COM3
I: 0; O: 1
0
X
X
S40
X
1
P5.6 (I/O)
ADC12CLK
DMAE0
P5.7 (I/O)
I: 0; O: 1
N/A
N/A
N/A
N/A
P5.6/ADC12CLK/DMAE0
P5.7/RTCCLK
6
7
1
0
I: 0; O: 1
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Table 9-61. Port P5 (P5.2 to P5.7) Pin Functions (continued)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
LCDS40...
LCDS42
P5DIR.x
P5SEL.x
RTCCLK
1
1
N/A
(1) X = Don't care
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9.13.7 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
Figure 9-8 shows the port diagram. Table 9-62 summarizes selection of the pin functions.
Pad Logic
To ADC12
INCHx = y
0
1
2
Dvss
0 if DAC12AMPx=0
1 if DAC12AMPx=1
2 if DAC12AMPx>1
From DAC12_A
To Comparator_B
From Comparator_B
CBPD.x
DAC12AMPx>0
DAC12OPS
P6REN.x
DVSS
DVCC
0
1
1
P6DIR.x
P6OUT.x
P6.0/CB0/A0
P6.1/CB1/A1
P6.2/CB2/A2
P6.3/CB3/A3
P6.4/CB4/A4
P6.5/CB5/A5
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
P6.6/CB6/A6/DAC0
P6.7/CB7/A7/DAC1
Bus
Keeper
Figure 9-8. Port P6 (P6.0 to P6.7) Diagram
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Table 9-62. Port P6 (P6.0 to P6.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P6.x)
x
FUNCTION
P6DIR.x
P6SEL.x
CBPD.x
DAC12OPS
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
X
DAC12AMPx
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
P6.0 (I/O)
CB0
I: 0; O: 1
0
X
1
0
X
1
0
X
1
0
X
1
0
X
1
0
X
1
0
X
1
X
0
X
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
X
0
1
X
X
P6.0/CB0/A0
P6.1/CB1/A1
P6.2/CB2/A2
P6.3/CB3/A3
P6.4/CB4/A4
P6.5/CB5/A5
0
X
A0(2) (3)
P6.1 (I/O)
CB1
X
I: 0; O: 1
1
2
3
4
5
X
A1(2) (3)
P6.2 (I/O)
CB2
X
I: 0; O: 1
X
A2(2) (3)
P6.3 (I/O)
CB3
X
I: 0; O: 1
X
A3(2) (3)
P6.4 (I/O)
CB4
X
I: 0; O: 1
X
A4(2) (3)
P6.5 (I/O)
CB5
X
I: 0; O: 1
X
A5(2) (3)
P6.6 (I/O)
CB6
X
I: 0; O: 1
X
X
0
P6.6/CB6/A6/DAC0
6
7
A6(2) (3)
X
X
0
DAC0
X
0
>1
P6.7 (I/O)
CB7
I: 0; O: 1
X
0
X
X
X
X
0
P6.7/CB7/A7/DAC1
(1) X = Don't care
A7(2) (3)
X
0
DAC1
0
>1
(2) Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
(3) The ADC12_A channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
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9.13.8 Port P7 (P7.2) Input/Output With Schmitt Trigger
Figure 9-9 shows the port diagram. Table 9-63 summarizes selection of the pin functions.
Pad Logic
To XT2
P7REN.2
DVSS
DVCC
0
1
1
P7DIR.2
P7OUT.2
0
1
P7.2/XT2IN
P7DS.2
0: Low drive
1: High drive
P7SEL.2
P7IN.2
Bus
Keeper
Figure 9-9. Port P7 (P7.2) Diagram
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9.13.9 Port P7 (P7.3) Input/Output With Schmitt Trigger
Figure 9-10 shows the port diagram. Table 9-63 summarizes selection of the pin functions.
Pad Logic
To XT2
P7REN.3
DVSS
DVCC
0
1
1
P7DIR.3
0
1
P7OUT.3
P7SEL.2
P7.3/XT2OUT
P7DS.3
0: Low drive
1: High drive
XT2BYPASS
P7SEL.3
P7IN.3
Bus
Keeper
Figure 9-10. Port P7 (P7.3) Diagram
Table 9-63. Port P7 (P7.2 and P7.3) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P7.x)
x
FUNCTION
P7DIR.x
P7SEL.2
P7SEL.3
XT2BYPASS
P7.2 (I/O)
I: 0; O: 1
0
1
1
0
1
1
X
X
X
0
X
0
1
X
0
1
P7.2/XT2IN
2
XT2IN crystal mode(2)
XT2IN bypass mode(2)
P7.3 (I/O)
X
X
I: 0; O: 1
P7.3/XT2OUT
3
XT2OUT crystal mode(3)
P7.3 (I/O)(3)
X
X
X
0
(1) X = Don't care
(2) Setting P7SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P7.2 is configured for crystal
mode or bypass mode.
(3) Setting P7SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.3 can be used as
general-purpose I/O.
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9.13.10 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
Figure 9-11 shows the port diagram. Table 9-64 summarizes selection of the pin functions.
0
Pad Logic
DVSS
1
2
0 if DAC12AMPx = 0
1 if DAC12AMPx = 1
2 if DAC12AMPx > 1
From DAC12_A
To ADC12
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
DAC12AMPx>0
DAC12OPS
P7REN.x
P7SEL.x
P7DIR.x
DVSS
DVCC
0
1
1
P7OUT.x
P7.4/CB8/A12
P7.5/CB9/A13
P7.6/CB10/A14/DAC0
P7.7/CB11/A15/DAC1
P7DS.x
0: Low drive
1: High drive
P7IN.x
Bus
Keeper
Figure 9-11. Port P7 (P7.4 to P7.7) Diagram
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Table 9-64. Port P7 (P7.4 to P7.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P7.x)
x
FUNCTION
P7DIR.x
P7SEL.x
CBPD.x
DAC12OPS
DAC12AMPx
P7.4 (I/O)
I: 0; O: 1
0
X
1
0
X
1
0
X
1
X
0
1
X
0
1
X
0
1
X
0
1
X
X
0
X
X
N/A
N/A
N/A
N/A
N/A
N/A
X
N/A
N/A
N/A
N/A
N/A
N/A
0
P7.4/CB8/A12
P7.5/CB9/A13
4
Comparator_B input CB8
A12(2) (3)
X
X
P7.5 (I/O)
I: 0; O: 1
5
6
7
Comparator_B input CB9
A13(2) (3)
X
X
P7.6 (I/O)
I: 0; O: 1
Comparator_B input CB10
A14(2) (3)
X
X
0
P7.6/CB10/A14/DAC0
X
X
0
DAC12_A output DAC0
X
1
>1
0
P7.7 (I/O)
I: 0; O: 1
X
P7.7/CB11/A15/DAC1
(1) X = Don't care
A15(2) (3)
X
X
X
0
DAC12_A output DAC1
1
>1
(2) Setting the P7SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
(3) The ADC12_A channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
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9.13.11 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
Figure 9-12 shows the port diagram. Table 9-65 summarizes selection of the pin functions.
Pad Logic
S8...S15
LCDS8...LCDS15
P8REN.x
DVSS
DVCC
0
1
1
P8DIR.x
0
1
Direction
0: Input
1: Output
From module
0
1
P8OUT.x
Module X OUT
P8.0/TB0CLK/S15
P8DS.x
0: Low drive
1: High drive
P8.1/UCB1STE/UCA1CLK/S14
P8.2/UCA1TXD/UCA1SIMO/S13
P8.3/UCA1RXD/UCA1SOMI/S12
P8.4/UCB1CLK/UCA1STE/S11
P8.5/UCB1SIMO//UCB1SDA/S10
P8.6/UCB1SOMI/UCB1SCL/S9
P8.7/S8
P8SEL.x
P8IN.x
Bus
Keeper
EN
D
Module X IN
Figure 9-12. Port P8 (P8.0 to P8.7) Diagram
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Table 9-65. Port P8 (P8.0 to P8.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P9.x)
x
FUNCTION
LCDS8...
LCDS15
P8DIR.x
P8SEL.x
P8.0 (I/O)
I: 0; O: 1
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
X
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
P8.0/TB0CLK/S15
0
Timer TB0.TB0CLK clock input
0
S15
X
P8.1 (I/O)
I: 0; O: 1
P8.1/UCB1STE/UCA1CLK/S14
P8.2/UCA1TXD/UCA1SIMO/S13
P8.3/UCA1RXD/UCA1SOMI/S12
P8.4/UCB1CLK/UCA1STE/S11
P8.5/UCB1SIMO/UCB1SDA/S10
P8.6/UCB1SOMI/UCB1SCL/S9
1
2
3
4
5
UCB1STE/UCA1CLK
X
S14
X
P8.2 (I/O)
I: 0; O: 1
UCA1TXD/UCA1SIMO
X
S13
X
P8.3 (I/O)
I: 0; O: 1
UCA1RXD/UCA1SOMI
X
S12
X
P8.4 (I/O)
I: 0; O: 1
UCB1CLK/UCA1STE
X
S11
X
P8.5 (I/O)
I: 0; O: 1
UCB1SIMO/UCB1SDA
X
S10
X
P8.6 (I/O)
I: 0; O: 1
6
7
UCB1SOMI/UCB1SCL
X
S9
X
I: 0; O: 1
X
P8.7 (I/O)
S8
P8.7/S8
(1) X = Don't care
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9.13.12 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
Figure 9-13 shows the port diagram. Table 9-66 summarizes selection of the pin functions.
Pad Logic
S0...S7
LCDS0...LCDS7
P9REN.x
DVSS
DVCC
0
1
1
P9DIR.x
0
1
Direction
0: Input
1: Output
From module
0
1
P9OUT.x
Module X OUT
P9.0/S7
P9DS.x
0: Low drive
1: High drive
P9.1/UCB2STE/UCA2CLK/S6
P9.2/UCA2TXD/UCA2SIMO/S5
P9.3/UCA2RXD/UCA2SOMI/S4
P9.4/UCB2CLK/UCA2STE/S3
P9.5/UCB2SIMO//UCB2SDA/S2
P9.6/UCB2SOMI/UCB2SCL/S1
P9.7/S0
P9SEL.x
P9IN.x
Bus
Keeper
EN
D
Module X IN
Figure 9-13. Port P9 (P9.0 to P9.7) Diagram
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Table 9-66. Port P9 (P9.0 to P9.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P9.x)
x
FUNCTION
LCDS0...
LCDS7
P9DIR.x
P9SEL.x
P9.0 (I/O)
S7
I: 0; O: 1
0
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
X
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
P9.0/S7
0
X
P9.1 (I/O)
I: 0; O: 1
P9.1/UCB2STE/UCA2CLK/S6
1
2
3
4
5
UCB2STE/UCA2CLK
X
S6
X
P9.2 (I/O)
I: 0; O: 1
P9.2/UCA2TXD/UCA2SIMO/S5
P9.3/UCA2RXD/UCA2SOMI/S4
P9.4/UCB2CLK/UCA2STE/S3
P9.5/UCB2SIMO/UCB2SDA/S2
P9.6/UCB2SOMI/UCB2SCLK/S1
UCA2TXD/UCA2SIMO
X
S5
X
P9.3 (I/O)
I: 0; O: 1
UCA2RXD/UCA2SOMI
X
S4
X
P9.4 (I/O)
I: 0; O: 1
UCB2CLK/UCA2STE
X
S3
X
P9.5 (I/O)
I: 0; O: 1
UCB2SIMO/UCB2SDA
X
S2
X
P9.6 (I/O)
I: 0; O: 1
6
7
UCB2SOMI/UCB2SCLK
X
S1
X
I: 0; O: 1
X
P9.7 (I/O)
S0
P9.7/S0
(1) X = Don't care
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9.13.13 Port PU (PU.0/DP, PU.1/DM, PUR) USB Ports (F665x, F565x)
Figure 9-14 shows the port diagram. Table 9-67 and Table 9-68 summarize selection of the pin functions.
PUSEL
VUSB
VSSU
Pad Logic
PUOPE
0
1
USB output enable
PUOUT0
0
1
PU.0/DP
USB DP output
PUIN0
USB DP input
PUIPE
PUIN1
USB DM input
PUOUT1
0
1
PU.1/DM
USB DM output
VUSB
VSSU
Pad Logic
PUREN
PUR
“1”
PUSEL
PURIN
Figure 9-14. Port PU (PU.0 and PU.1) Diagram (F665x, F565x)
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Table 9-67. Port PU (PU.0, PU.1) Functions (F665x, F565x)
PUSEL
PUIPE
PUOPE
PUOUT1
PUOUT0
PU.1/DM
Output low
Output low
Output high
Output high
Input enabled
Hi-Z
PU.0/DP
Output low
Output high
Output low
Output high
Input enabled
Hi-Z
PORT U FUNCTION
Outputs enabled
0
0
0
0
0
0
1
0
0
0
0
1
0
X
1
1
1
1
0
0
X
0
0
1
1
X
X
X
0
1
0
1
X
X
X
Outputs enabled
Outputs enabled
Outputs enabled
Inputs enabled
Outputs and inputs disabled
Direction set by USB module
DM
DP
Table 9-68. Port PU (PUR) Input Functions (F665x,
F565x)
CONTROL BITS
FUNCTION
PUSEL
PUREN
Input disabled
Pullup disabled
0
0
Input disabled
Pullup enabled
0
1
1
1
0
1
Input enabled
Pullup disabled
Input enabled
Pullup enabled
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9.13.14 Port PU (PU.0 and PU.1) Ports (F645x, F535x)
Figure 9-15 shows the port diagram. Table 9-69 summarizes selection of the pin functions.
LDOO
VSSU
Pad Logic
PUOPE
PU.0
PUOUT0
PUIN0
PUIPE
PUIN1
PUOUT1
PU.1
Figure 9-15. Port PU (PU.0 and PU.1) Diagram (F645x, F535x)
Table 9-69. Port PU (PU.0 and PU.1) Functions (F645x, F535x)
PUIPE(1)
PUOPE
PUOUT1
PUOUT0
PU.1
PU.0
PORT U FUNCTION
0
0
0
0
1
0
1
1
1
1
0
0
0
0
1
1
X
X
0
1
0
1
X
X
Output low
Output low
Output high
Output high
Input enabled
Hi-Z
Output low
Output high
Output low
Output high
Input enabled
Hi-Z
Outputs enabled
Outputs enabled
Outputs enabled
Outputs enabled
Inputs enabled
Outputs and inputs disabled
(1) PU.1 and PU.0 inputs and outputs are supplied from LDOO. LDOO can be generated by the device using the integrated 3.3-V LDO
when enabled. LDOO can also be supplied externally when the 3.3-V LDO is not being used and is disabled.
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9.13.15 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
Figure 9-16 shows the port diagram. Table 9-70 summarizes selection of the pin functions.
Pad Logic
PJREN.0
0
1
DVSS
DVCC
1
PJDIR.0
DVCC
0
1
PJOUT.0
0
1
From JTAG
PJ.0/TDO
PJDS.0
0: Low drive
1: High drive
From JTAG
PJIN.0
EN
D
Figure 9-16. Port PJ (PJ.0) Diagram
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9.13.16 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or
Output
Figure 9-17 shows the port diagram. Table 9-70 summarizes selection of the pin functions.
Pad Logic
PJREN.x
0
1
DVSS
DVCC
1
PJDIR.x
DVSS
0
1
PJOUT.x
0
1
From JTAG
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
PJDS.x
0: Low drive
1: High drive
From JTAG
PJIN.x
EN
D
To JTAG
Figure 9-17. Port PJ (PJ.1 to PJ.3) Diagram
Table 9-70. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS
OR SIGNALS(1)
PIN NAME (PJ.x)
x
FUNCTION
PJDIR.x
I: 0; O: 1
X
PJ.0 (I/O)(2)
PJ.0/TDO
0
1
2
3
TDO(3)
PJ.1 (I/O)(2)
TDI/TCLK(3) (4)
PJ.2 (I/O)(2)
TMS(3) (4)
I: 0; O: 1
X
PJ.1/TDI/TCLK
PJ.2/TMS
I: 0; O: 1
X
PJ.3 (I/O)(2)
TCK(3) (4)
I: 0; O: 1
X
PJ.3/TCK
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.
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9.14 Device Descriptors
Table 9-71 lists the contents of the device descriptor tag-length-value (TLV) structure for each device type.
Table 9-71. Device Descriptor Table
VALUE
SIZE
(bytes)
DESCRIPTION(1)
Info length
ADDRESS
F6659
06h
F6658
06h
F6459
06h
F6458
06h
F5659
06h
F5658
06h
F5359
06h
F5358
06h
01A00h
01A01h
01A02h
01A04h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Eh
01A10h
01A12h
01A14h
01A15h
01A16h
01A18h
1
1
2
2
1
1
1
1
4
2
2
2
1
1
2
2
CRC length
CRC value
06h
06h
06h
06h
06h
06h
06h
06h
Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit
Info Block
Device ID
812Bh
10h
812Ch
10h
812Dh
10h
812Eh
10h
8130h
10h
8131h
10h
8132h
10h
8133h
10h
Hardware revision
Firmware revision
Die record tag
Die record length
Lot/wafer ID
10h
10h
10h
10h
10h
10h
10h
10h
08h
08h
08h
08h
08h
08h
08h
08h
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit
Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit
Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit
Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit
Die Record
Die X position
Die Y position
Test results
ADC12 calibration tag
ADC12 calibration length
ADC gain factor
ADC offset
11h
10h
11h
10h
11h
10h
11h
10h
11h
10h
11h
10h
11h
10h
11h
10h
Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit
Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit
ADC 1.5-V reference
temperature sensor 30°C
01A1Ah
01A1Ch
01A1Eh
01A20h
01A22h
01A24h
2
2
2
2
2
2
Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit
Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit
Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit
Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit
Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit
Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit
ADC 1.5-V reference
temperature sensor 85°C
ADC12
Calibration
ADC 2.0-V reference
temperature sensor 30°C
ADC 2.0-V reference
temperature sensor 85°C
ADC 2.5-V reference
temperature sensor 30°C
ADC 2.5-V reference
temperature sensor 85°C
REF calibration tag
REF calibration length
01A26h
01A27h
01A28h
01A2Ah
01A2Ch
1
1
2
2
2
12h
06h
12h
06h
12h
06h
12h
06h
12h
06h
12h
06h
12h
06h
12h
06h
REF
Calibration
REF 1.5-V reference factor
REF 2.0-V reference factor
REF 2.5-V reference factor
Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit
Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit
Per unit Per unit Per unit Per unit Per unit Per unit Per unit Per unit
(1) N/A = Not applicable
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10 Device and Documentation Support
10.1 Getting Started and Next Steps
For more information on the MSP430™ family of devices and the tools and libraries that are available to help with
your development, visit the MSP430 ultra-low-power sensing and measurement MCUs overview.
10.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP
MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These
prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully
qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated
fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.
TI recommends that these devices not be used in any production system because their expected end-use failure
rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature
range, package type, and distribution format. Figure 10-1 provides a legend for reading the complete device
name.
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MSP 430 F 5 438 A I PM T -EP
Processor Family
MCU Platform
Device Type
Series
Feature Set
Optional: Additional Features
Optional: Tape and Reel
Packaging
Optional: Temperature Range
Optional: Revision
Processor Family
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
MCU Platform
Device Type
430 = MSP430 low-power microcontroller platform
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash
L = No nonvolatile memory
Specialized Application
AFE = Analog front end
BQ = Contactless power
CG = ROM medical
FE = Flash energy meter
FG = Flash medical
FW = Flash electronic flow meter
Series
1 = Up to 8 MHz
2 = Up to 16 MHz
3 = Legacy
4 = Up to 16 MHz with LCD driver
5 = Up to 25 MHz
6 = Up to 25 MHz with LCD driver
0 = Low-voltage series
Feature Set
Various levels of integration within a series
Updated version of the base part number
Optional: Revision
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small reel
R = Large reel
No markings = Tube or tray
Optional: Additional Features -EP = Enhanced product (–40°C to 105°C)
-HT = Extreme temperature parts (–55°C to 150°C)
-Q1 = Automotive Q100 qualified
Figure 10-1. Device Nomenclature
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10.3 Tools and Software
All MSP microcontrollers are supported by a wide variety of software and hardware development tools. Tools are
available from TI and various third parties. See them all at MSP430 ultra-low-power MCUs – Design &
development.
Table 10-1 lists the debug features of the MSP430F665x, MSP430F645x, MSP430F565x, and MSP430F535x
MCUs. See the Code Composer Studio IDE for MSP430 MCUs User's Guide for details on the available
features.
Table 10-1. Hardware Debug Features
BREAK-
POINTS
(N)
RANGE
BREAK-
POINTS
LPMx.5
DEBUGGING
SUPPORT
MSP430
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
CLOCK
CONTROL SEQUENCER
STATE
TRACE
BUFFER
MSP430Xv2
Yes
Yes
8
Yes
Yes
Yes
Yes
Yes
Design Kits and Evaluation Modules
MSP-TS430PZ100USB - 100-pin Target Development Board for MSP430F5x and MSP430F6x MCUs
The MSP-TS430PZ100USB is a stand-alone 100-pin ZIF socket target board used to program and debug the
MSP430 MCU in-system through the JTAG interface or the Spy Bi-Wire (2-wire JTAG) protocol.
100-pin Target Development Board and MSP-FET Programmer Bundle for MSP430F5x and MSP430F6x MCUs
The MSP-TS430PZ100USB is a stand-alone 100-pin ZIF socket target board used to program and debug the
MSP430 MCU in-system through the JTAG interface or the Spy Bi-Wire (2-wire JTAG) protocol. The MSP-FET is
a powerful flash emulation tool to quickly begin application development on the MSP430 MCU. It includes USB
debugging interface used to program and debug the MSP430 in-system through the JTAG interface or the pin
saving Spy Bi-Wire (2-wire JTAG) protocol.
MSP430F5529 USB LaunchPad Evaluation Kit
Develop low power, PC-connected applications with integrated Full-speed USB 2.0 (HID/MSC/CDC). The MSP-
EXP430F5529LP LaunchPad is an inexpensive, simple microcontroller development kit for the MSP430F5529
USB microcontroller. It’s an easy way to start developing on the MSP430 MCU, with an on-board emulation for
programming and debugging, as well as buttons and LEDs for simple user interface.
Software
MSP430Ware™ Software
MSP430Ware software is a collection of code examples, data sheets, and other design resources for all
MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 MCU design resources, MSP430Ware software also includes a high-level API called MSP Driver
Library. This library makes it easy to program MSP430 hardware. MSP430Ware software is available as a
component of CCS or as a stand-alone package.
MSP430F665x, MSP430F565x Code Examples
C code examples that configure each of the integrated peripherals for various application needs.
MSP Driver Library
Driver Library's abstracted API keeps you above the bits and bytes of the MSP430 hardware by providing easy-
to-use function calls. Thorough documentation is delivered through a helpful API Guide, which includes details
on each function call and the recognized parameters. Developers can use Driver Library functions to write
complete projects with minimal overhead.
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MSP EnergyTrace™ Technology
EnergyTrace technology for MSP430 microcontrollers is an energy-based code analysis tool that measures and
displays the application's energy profile and helps to optimize it for ultra-low-power consumption.
ULP (Ultra-Low Power) Advisor
ULP Advisor™ software is a tool for guiding developers to write more efficient code to fully utilize the unique
ultra-low power features of MSP and MSP432 microcontrollers. Aimed at both experienced and new
microcontroller developers, ULP Advisor checks your code against a thorough ULP checklist to squeeze every
last nano amp out of your application. At build time, ULP Advisor will provide notifications and remarks to
highlight areas of your code that can be further optimized for lower power.
IEC 60730 Software Package
The IEC 60730 MSP430 software package was developed to be useful in assisting customers in complying with
IEC 60730-1:2010 (Automatic Electrical Controls for Household and Similar Use – Part 1: General
Requirements) for up to Class B products, which includes home appliances, arc detectors, power converters,
power tools, e-bikes, and many others. The IEC 60730 MSP430 software package can be embedded in
customer applications running on MSP430s to help simplify the customer’s certification efforts of functional
safety-compliant consumer devices to IEC 60730-1:2010 Class B.
Fixed Point Math Library for MSP
The MSP IQmath and Qmath Libraries are a collection of highly optimized and high-precision mathematical
functions for C programmers to seamlessly port a floating-point algorithm into fixed-point code on MSP430 and
MSP432 devices. These routines are typically used in computationally intensive real-time applications where
optimal execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and Qmath
libraries, it is possible to achieve execution speeds considerably faster and energy consumption considerably
lower than equivalent code written using floating-point math.
Floating Point Math Library for MSP430
Continuing to innovate in the low power and low cost microcontroller space, TI brings you MSPMATHLIB.
Leveraging the intelligent peripherals of our devices, this floating point math library of scalar functions brings you
up to 26x better performance. Mathlib is easy to integrate into your designs. This library is free and is integrated
in both Code Composer Studio and IAR IDEs. Read the user’s guide for an in depth look at the math library and
relevant benchmarks.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports all MSP microcontroller
devices. Code Composer Studio comprises a suite of embedded software utilities used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking you through
each step of the application development flow. Familiar utilities and interfaces allow users to get started faster
than ever before. Code Composer Studio combines the advantages of the Eclipse software framework with
advanced embedded debug capabilities from TI resulting in a compelling feature-rich development environment
for embedded developers. When using CCS with an MSP MCU, a unique and powerful set of plugins and
embedded software utilities are made available to fully leverage the MSP microcontroller.
Command-Line Programmer
MSP Flasher is an open-source shell-based interface for programming MSP microcontrollers through a FET
programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can download binary
files (.txt or .hex) files directly to the MSP microcontroller without an IDE.
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MSP MCU Programmer and Debugger
The MSP-FET is a powerful emulation development tool – often called a debug probe – which allows users to
quickly begin application development on MSP low-power microcontrollers (MCU). Creating MCU software
usually requires downloading the resulting binary program to the MSP device for validation and debugging. The
MSP-FET provides a debug communication pathway between a host computer and the target MSP.
Furthermore, the MSP-FET also provides a Backchannel UART connection between the computer's USB
interface and the MSP UART. This affords the MSP programmer a convenient method for communicating serially
between the MSP and a terminal running on the computer. It also supports loading programs (often called
firmware) to the MSP target using the BSL (bootloader) through the UART and I2C communication protocols.
MSP-GANG Production Programmer
The MSP Gang Programmer is an MSP430 or MSP432 device programmer that can program up to eight
identical MSP430 or MSP432 Flash or FRAM devices at the same time. The MSP Gang Programmer connects
to a host PC using a standard RS-232 or USB connection and provides flexible programming options that allow
the user to fully customize the process. The MSP Gang Programmer is provided with an expansion board, called
the Gang Splitter, that implements the interconnections between the MSP Gang Programmer and multiple target
devices. Eight cables are provided that connect the expansion board to eight target devices (through JTAG or
Spy-Bi-Wire connectors). The programming can be done with a PC or as a stand-alone device. A PC-side
graphical user interface is also available and is DLL-based.
10.4 Documentation Support
The following documents describe the MSP430F665x, MSP430F645x, MSP430F565x, and MSP430F535x
MCUs. Copies of these documents are available on the Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for your
device on ti.com (for links to the product folders, see Section 10.5). In the upper right corner, click the "Alert me"
button. This registers you to receive a weekly digest of product information that has changed (if any). For change
details, check the revision history of any revised document.
Errata
MSP430F6659 Device Erratasheet
Describes the known exceptions to the functional specifications for all silicon revisions of this device.
MSP430F6658 Device Erratasheet
Describes the known exceptions to the functional specifications for all silicon revisions of this device.
MSP430F6459 Device Erratasheet
Describes the known exceptions to the functional specifications for all silicon revisions of this device.
MSP430F6458 Device Erratasheet
Describes the known exceptions to the functional specifications for all silicon revisions of this device.
MSP430F5659 Device Erratasheet
Describes the known exceptions to the functional specifications for all silicon revisions of this device.
MSP430F5658 Device Erratasheet
Describes the known exceptions to the functional specifications for all silicon revisions of this device.
MSP430F5359 Device Erratasheet
Describes the known exceptions to the functional specifications for all silicon revisions of this device.
MSP430F5358 Device Erratasheet
Describes the known exceptions to the functional specifications for all silicon revisions of this device.
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User's Guides
MSP430F5xx and MSP430F6xx Family User's Guide
Detailed information on the modules and peripherals available in this device family.
MSP430 Flash Devices Bootloader (BSL) User's Guide
The MSP430 bootloader (BSL) lets users communicate with embedded memory in the MSP430 microcontroller
during the prototyping phase, final production, and in service. Both the programmable memory (flash memory)
and the data memory (RAM) can be modified as required. Do not confuse the bootloader with the bootstrap
loader programs found in some digital signal processors (DSPs) that automatically load program code (and data)
from external memory to the internal memory of the DSP.
MSP430 Programming With the JTAG Interface
This document describes the functions that are required to erase, program, and verify the memory module of the
MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition,
it describes how to program the JTAG access security fuse that is available on all MSP430 devices. This
document describes device access using both the standard 4-wire JTAG interface and the 2-wire JTAG
interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide
This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the
program development tool for the MSP430 ultra-low-power microcontroller. Both available interface types, the
parallel port interface and the USB interface, are described.
Application Reports
MSP430 32-kHz Crystal Oscillators
Selection of the right crystal, correct load circuit, and proper board layout are important for a stable crystal
oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the
correct crystal for ultra-low-power operation. In addition, hints and examples for correct board layout are given.
The document also contains detailed information on the possible oscillator tests to ensure stable oscillator
operation in mass production.
MSP430 System-Level ESD Considerations
System-level ESD has become increasingly demanding as silicon technology scales to lower voltages and the
need for designing cost-effective and ultra-low-power components. This application report addresses ESD topics
to help board designers and OEMs understand and design robust system-level designs. A few real-world
system-level ESD protection design examples and their results are discussed.
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MSP430F5659, MSP430F5658, MSP430F5359, MSP430F5358
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10.5 Related Links
Table 10-2 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 10-2. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
MSP430F6659
MSP430F6658
MSP430F6459
MSP430F6458
MSP430F5659
MSP430F5658
MSP430F5359
MSP430F5358
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
10.6 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com,
you can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
10.7 Trademarks
MicroStar Junior™, MSP430™, MSP430Ware™, EnergyTrace™, ULP Advisor™, Code Composer Studio™, and
E2E™ are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
10.8 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.9 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as
defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.
10.10 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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SLAS700E – OCTOBER 2012 – REVISED SEPTEMBER 2020
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Sep-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430F5358IPZ
MSP430F5358IPZR
MSP430F5358IZCAR
MSP430F5358IZCAT
MSP430F5358IZQWR
ACTIVE
LQFP
LQFP
PZ
100
100
113
113
113
90
Green (RoHS
& no Sb/Br)
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
F5358
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PZ
1000
2500
250
Green (RoHS
& no Sb/Br)
NIPDAU
SNAGCU
SNAGCU
SNAGCU
F5358
F5358
F5358
F5358
NFBGA
NFBGA
ZCA
ZCA
ZQW
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
BGA
MICROSTAR
JUNIOR
2500
Green (RoHS
& no Sb/Br)
MSP430F5358IZQWT
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
F5358
MSP430F5359IPZ
MSP430F5359IPZR
MSP430F5359IZCAR
MSP430F5359IZCAT
MSP430F5359IZQWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
PZ
PZ
100
100
113
113
113
90
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
SNAGCU
SNAGCU
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
F5359
F5359
F5359
F5359
F5359
LQFP
1000
2500
250
Green (RoHS
& no Sb/Br)
NFBGA
NFBGA
ZCA
ZCA
ZQW
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
BGA
MICROSTAR
JUNIOR
2500
Green (RoHS
& no Sb/Br)
MSP430F5359IZQWT
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
F5359
MSP430F5658IPZ
MSP430F5658IPZR
ACTIVE
ACTIVE
LQFP
PZ
PZ
100
100
90
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
F5658
F5658
LQFP
1000
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Sep-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430F5658IZQWR
MSP430F5658IZQWT
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
F5658
ACTIVE
BGA
ZQW
250
Green (RoHS
& no Sb/Br)
SNAGCU
-40 to 85
F5658
MICROSTAR
JUNIOR
MSP430F5659IPZ
MSP430F5659IPZR
MSP430F5659IZCAR
MSP430F5659IZCAT
MSP430F5659IZQWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
PZ
PZ
100
100
113
113
113
90
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
SNAGCU
SNAGCU
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
F5659
F5659
F5659
F5659
F5659
LQFP
1000
2500
250
Green (RoHS
& no Sb/Br)
NFBGA
NFBGA
ZCA
ZCA
ZQW
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
BGA
MICROSTAR
JUNIOR
2500
Green (RoHS
& no Sb/Br)
MSP430F5659IZQWT
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
F5659
MSP430F6458IPZ
MSP430F6459IPZ
MSP430F6459IPZR
MSP430F6459IZQWT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
PZ
PZ
100
100
100
113
90
90
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
F6458
F6459
F6459
F6459
Green (RoHS
& no Sb/Br)
PZ
1000
250
Green (RoHS
& no Sb/Br)
BGA
MICROSTAR
JUNIOR
ZQW
Green (RoHS
& no Sb/Br)
MSP430F6658IPZ
MSP430F6659IPZ
MSP430F6659IPZR
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
PZ
PZ
PZ
100
100
100
90
90
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
F6658
F6659
F6659
Green (RoHS
& no Sb/Br)
1000
Green (RoHS
& no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
14-Sep-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
250
(1)
(2)
(3)
(4/5)
(6)
MSP430F6659IZCAR
MSP430F6659IZCAT
MSP430F6659IZQWR
ACTIVE
NFBGA
NFBGA
ZCA
113
113
113
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
F6659
ACTIVE
ACTIVE
ZCA
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
F6659
F6659
BGA
ZQW
2500
Green (RoHS
& no Sb/Br)
MICROSTAR
JUNIOR
MSP430F6659IZQWT
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
F6659
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
14-Sep-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Sep-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430F5358IPZR
MSP430F5358IZCAR
MSP430F5358IZCAT
LQFP
NFBGA
NFBGA
PZ
100
113
113
113
1000
2500
250
330.0
330.0
180.0
330.0
24.4
16.4
16.4
16.4
17.0
7.3
7.3
7.3
17.0
7.3
7.3
7.3
2.1
1.5
1.5
1.5
20.0
12.0
12.0
12.0
24.0
16.0
16.0
16.0
Q2
Q1
Q1
Q1
ZCA
ZCA
ZQW
MSP430F5358IZQWR BGA MI
2500
CROSTA
R JUNI
OR
MSP430F5358IZQWT BGA MI
ZQW
113
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
CROSTA
R JUNI
OR
MSP430F5359IPZR
MSP430F5359IZCAR
MSP430F5359IZCAT
LQFP
NFBGA
NFBGA
PZ
100
113
113
113
1000
2500
250
330.0
330.0
180.0
330.0
24.4
16.4
16.4
16.4
17.0
7.3
7.3
7.3
17.0
7.3
7.3
7.3
2.1
1.5
1.5
1.5
20.0
12.0
12.0
12.0
24.0
16.0
16.0
16.0
Q2
Q1
Q1
Q1
ZCA
ZCA
ZQW
MSP430F5359IZQWR BGA MI
2500
CROSTA
R JUNI
OR
MSP430F5359IZQWT BGA MI
ZQW
113
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
CROSTA
R JUNI
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Sep-2020
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OR
MSP430F5658IPZR
LQFP
PZ
100
113
1000
2500
330.0
330.0
24.4
16.4
17.0
7.3
17.0
7.3
2.1
1.5
20.0
12.0
24.0
16.0
Q2
Q1
MSP430F5658IZQWR BGA MI
ZQW
CROSTA
R JUNI
OR
MSP430F5658IZQWT BGA MI
ZQW
113
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
CROSTA
R JUNI
OR
MSP430F5659IPZR
MSP430F5659IZCAR
MSP430F5659IZCAT
LQFP
NFBGA
NFBGA
PZ
100
113
113
113
1000
2500
250
330.0
330.0
180.0
330.0
24.4
16.4
16.4
16.4
17.0
7.3
7.3
7.3
17.0
7.3
7.3
7.3
2.1
1.5
1.5
1.5
20.0
12.0
12.0
12.0
24.0
16.0
16.0
16.0
Q2
Q1
Q1
Q1
ZCA
ZCA
ZQW
MSP430F5659IZQWR BGA MI
2500
CROSTA
R JUNI
OR
MSP430F5659IZQWT BGA MI
ZQW
113
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
CROSTA
R JUNI
OR
MSP430F6459IPZR
LQFP
PZ
100
113
1000
250
330.0
180.0
24.4
16.4
17.0
7.3
17.0
7.3
2.1
1.5
20.0
12.0
24.0
16.0
Q2
Q1
MSP430F6459IZQWT BGA MI
ZQW
CROSTA
R JUNI
OR
MSP430F6659IPZR
MSP430F6659IZCAR
MSP430F6659IZCAT
LQFP
NFBGA
NFBGA
PZ
100
113
113
113
1000
2500
250
330.0
330.0
180.0
330.0
24.4
16.4
16.4
16.4
17.0
7.3
7.3
7.3
17.0
7.3
7.3
7.3
2.1
1.5
1.5
1.5
20.0
12.0
12.0
12.0
24.0
16.0
16.0
16.0
Q2
Q1
Q1
Q1
ZCA
ZCA
ZQW
MSP430F6659IZQWR BGA MI
2500
CROSTA
R JUNI
OR
MSP430F6659IZQWT BGA MI
ZQW
113
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
CROSTA
R JUNI
OR
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Sep-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430F5358IPZR
MSP430F5358IZCAR
MSP430F5358IZCAT
LQFP
NFBGA
NFBGA
PZ
100
113
113
113
1000
2500
250
350.0
350.0
213.0
350.0
350.0
350.0
191.0
350.0
43.0
43.0
55.0
43.0
ZCA
ZCA
ZQW
MSP430F5358IZQWR BGA MICROSTAR
JUNIOR
2500
MSP430F5358IZQWT BGA MICROSTAR
JUNIOR
ZQW
113
250
213.0
191.0
55.0
MSP430F5359IPZR
MSP430F5359IZCAR
MSP430F5359IZCAT
LQFP
NFBGA
NFBGA
PZ
100
113
113
113
1000
2500
250
350.0
350.0
213.0
350.0
350.0
350.0
191.0
350.0
43.0
43.0
55.0
43.0
ZCA
ZCA
ZQW
MSP430F5359IZQWR BGA MICROSTAR
JUNIOR
2500
MSP430F5359IZQWT BGA MICROSTAR
JUNIOR
ZQW
113
250
213.0
191.0
55.0
MSP430F5658IPZR
LQFP
PZ
100
113
1000
2500
350.0
350.0
350.0
350.0
43.0
43.0
MSP430F5658IZQWR BGA MICROSTAR
JUNIOR
ZQW
MSP430F5658IZQWT BGA MICROSTAR
JUNIOR
ZQW
113
250
213.0
191.0
55.0
MSP430F5659IPZR
MSP430F5659IZCAR
MSP430F5659IZCAT
LQFP
NFBGA
NFBGA
PZ
100
113
113
1000
2500
250
350.0
350.0
213.0
350.0
350.0
191.0
43.0
43.0
55.0
ZCA
ZCA
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Sep-2020
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430F5659IZQWR BGA MICROSTAR
JUNIOR
ZQW
113
2500
350.0
350.0
43.0
MSP430F5659IZQWT BGA MICROSTAR
JUNIOR
ZQW
113
250
213.0
191.0
55.0
MSP430F6459IPZR
LQFP
PZ
100
113
1000
250
350.0
213.0
350.0
191.0
43.0
55.0
MSP430F6459IZQWT BGA MICROSTAR
JUNIOR
ZQW
MSP430F6659IPZR
MSP430F6659IZCAR
MSP430F6659IZCAT
LQFP
NFBGA
NFBGA
PZ
100
113
113
113
1000
2500
250
350.0
350.0
213.0
350.0
350.0
350.0
191.0
350.0
43.0
43.0
55.0
43.0
ZCA
ZCA
ZQW
MSP430F6659IZQWR BGA MICROSTAR
JUNIOR
2500
MSP430F6659IZQWT BGA MICROSTAR
JUNIOR
ZQW
113
250
213.0
191.0
55.0
Pack Materials-Page 4
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
M
0,08
51
50
76
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
0,25
16,20
SQ
0,05 MIN
0°–7°
15,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OUTLINE
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
ZCA0113A
A
7.1
6.9
B
BALL A1 CORNER
7.1
6.9
1 MAX
C
SEATING PLANE
0.08 C
0.25
0.15
BALL TYP
5.5
TYP
(0.75) TYP
SYMM
M
L
K
J
(0.75) TYP
H
G
F
E
D
C
SYMM
5.5
TYP
0.35
0.25
113X Ø
B
A
0.15
0.05
C
C
A B
1
2
3
4
5
6
7
8
9 10 11 12
0.5 TYP
0.5 TYP
4225149/A 08/2019
NanoFree is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
ZCA0113A
(0.5) TYP
(0.5) TYP
1
2
3
4
5
6
7
8
9
10 11 12
A
B
C
D
E
F
113X (Ø0.25)
SYMM
G
H
J
K
L
M
SYMM
LAND PATTERN EXAMPLE
SCALE: 10X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
EXPOSED
METAL
(Ø 0.25)
METAL
(Ø 0.25)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225149/A 08/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments
Literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
ZCA0113A
(0.5) TYP
(0.5) TYP
1
2
3
4
5
6
7
8
9
10 11 12
A
B
C
D
E
F
(R0.05)
SYMM
G
H
J
METAL TYP
113X ( 0.25)
K
L
M
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
SCALE: 10X
4225149/A 08/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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