MSP430F6735AIPZ [TI]
具有 3 个 Σ-Δ ADC、LCD、实时时钟、128KB 闪存和 4KB RAM 的单相位计量 SoC | PZ | 100 | -40 to 85;
| 型号： | MSP430F6735AIPZ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 3 个 Σ-Δ ADC、LCD、实时时钟、128KB 闪存和 4KB RAM 的单相位计量 SoC | PZ | 100 | -40 to 85 时钟 CD 闪存 |
| 文件： | 总163页 (文件大小：2487K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
MSP430F673xA、MSP430F672xA 混合信号微控制器
1 器件概述
1.1 特性
1
寄存器
• 增强型通用串行通信接口 (eUSCI)
– eUSCI_A0、eUSCI_A1 和 eUSCI_A2
• 低电源电压范围：
3.6V 到低至 1.8V
• 超低功耗
– 激活模式 (AM)：
所有系统时钟激活
– 增强型通用异步收发器 (UART) 支持自动波特
率检测
在 8MHz、3.0V 且闪存程序执行时为
265µA/MHz（典型值）
在 8MHz、3.0V 且 RAM 程序执行时为
140µA/MHz（典型值）
– IrDA 编码和解码
– 同步串行外设接口 (SPI)
– eUSCI_B0
– 支持多个从器件寻址的 I2C
– 同步串行外设接口 (SPI)
– 待机模式 (LPM3)：
含晶体的实时时钟 (RTC)、看门狗、电源监视器
可用、完全 RAM 保持、快速唤醒：
2.2V 时为 1.7µA，3.0V 时为 2.5µA（典型值）
• 具有晶振偏移校准和温度补偿功能的受密码保护的
RTC
• 用于备用子系统的独立电压电源
– 32kHz 低频振荡器 (XT1)
– 实时时钟
– 关闭模式 (LPM4)：
完全 RAM 保持、电源监视器可用、快速唤醒：
3.0V 时为 1.6µA（典型值）
– 关断 RTC 模式 (LPM3.5)：
关断模式，RTC（采用晶振）工作：
3.0V 时为 1.24µA（典型值）
– 备用存储器（4 × 16 位）
• 三个具有差分可编程增益放大器 (PGA) 输入的 24
位 Σ-Δ 模数转换器 (ADC)
• 具有 8 路复用模式下高达 320 段对比度控制 的集成
LCD 驱动器
• 硬件乘法器支持 32 位运算
• 10位 200ksps ADC
– 内部基准
– 关断模式 (LPM4.5)：
3.0V 时为 0.78µA（典型值）
• 在 3μs（典型值）内从待机模式唤醒
• 16 位精简指令集计算机 (RISC) 架构，扩展内存，
高达 25MHz 的系统时钟
• 灵活的电源管理系统
– 内置可编程的低压降稳压器 (LDO)
– 电源电压监视、监控、和临时限电
– 由多达 2 个辅助电源供电的系统运行
• 单一时钟系统
– 采样和保持、自动扫描特性
– 多达 6 个外部通道和 2 个内部通道，包括温度传
感器
• 3 通道内部直接内存访问 (DMA)
• 串行板上编程，无需外部编程电压
• 器件比较 汇总了可用的产品系列成员
• 采用 100 引脚和 80 引脚 LQFP 封装
• 单相电子电表开发工具（另请参阅 工具与软件）
– 针对频率稳定的锁相环 (FLL) 控制环路
– 低功耗低频内部时钟源 (VLO)
– 低频修整内部基准源 (REFO)
– 32kHz 晶体 (XT1)
– EVM430-F6736 - 用于计量的 MSP430F6736
• 一个具有 3 个捕捉/比较寄存器的 16 位定时器
• 3 个 16 位定时器，每个定时器具有 2 个捕捉/比较
EVM
– 适用于 MSP430™ MCU 的能量测量设计中心
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASE46
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
1.2 应用
•
•
单相电子式电度表
能量监控
•
公用事业仪表计量
1.3 说明
TI MSP 系列超低功耗微控制器种类繁多，各成员器件配备不同的外设集以满足各类应用的 需求。此架构与
多种低功耗模式配合使用，是延长便携式测量应用电池寿命的最优 选择。该器件 具有 一个强大的 16 位精
简指令集 (RISC) CPU，使用 16 位寄存器以及常数发生器，以便获得最高编码效率。DCO 可使器件在不到
3µs（典型值）的时间内从低功耗模式唤醒至激活模式。
MSP430F673xA 和 MSP430F672xA 微控制器具有高性能 24 位 Σ-Δ ADC（MSP430F673xA 中有 3 个
ADC，MSP430F672xA 中有 2 个 ADC）、1 个 10 位 ADC、4 个 eUSCI（3 个 eUSCI_A 模块和 1 个
eUSCI_B 模块）、4 个 16 位计时器、1 个硬件乘法器、1 个 DMA 模块、1 个具有报警功能的 RTC 模块、
1 个具有集成对比度控制功能的 LCD 驱动器以及 1 个辅助电源系统；100 引脚器件的 I/O 引脚多达 72 个，
而 80 引脚器件的 I/O 引脚多达 52 个。
要获得完整的模块说明，请参阅《MSP430F5xx 和 MSP430F6xx 系列用户指南》
器件信息(1)
封装
器件型号
MSP430F6736AIPZ
MSP430F6736AIPN
封装尺寸(2)
14mm x 14mm
12mm x 12mm
LQFP (100)
LQFP (80)
(1) 要获得最新的产品、封装和订购信息，请参见封装选项附录（节 9），或者访问德州仪器 (TI) 网站
www.ti.com.cn。
(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参见机械数据（节 9）。
2
器件概述
版权 © 2015–2018, Texas Instruments Incorporated
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
1.4 功能框图
图 1-1 给出了所有采用 PZ 封装的器件型号的功能框图。
PB
PC
PA
PD
PE
P9.x
DVCC DVSS AVCC AVSS
AUX1 AUX2 AUX3
XIN
XOUT
RST/NMI
P3.x
P4.x
P5.x P6.x
P7.x P8.x
P1.x P2.x
(32 kHz)
ACLK
I/O Ports
P1, P2
2×8 I/Os
Interrupt,
Wakeup
I/O Ports
P3, P4
2×8 I/Os
I/O Ports
P5, P6
2×8 I/Os
I/O Ports
P7, P8
2×8 I/Os
I/O Ports
P9
1×4 I/O
SYS
Unified
Clock
System
8KB
4KB
2KB
1KB
128KB
96KB
64KB
32KB
16KB
Watchdog
CRC16
MPY32
SMCLK
Port
Mapping
Controller
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
MCLK
PD
1×16 I/Os
PE
1×4 I/O
RAM
Flash
CPUXV2
and
Working
Registers
(25 MHz)
EEM
(S: 3+1)
PMM
Auxiliary
Supplies
eUSCI_A0
eUSCI_A1
eUSCI_A2
TA1
TA2
TA3
LCD_C
ADC10_A
REF
SD24_B
eUSCI_B0
(SPI, I2C)
TA0
DMA
JTAG,
SBW
Interface
RTC_C
8-mux
Up to 320
Segments
3 Channel
10 Bit
200 ksps
Reference
1.5 V, 2.0 V,
2.5 V
3 Channel
2 Channel
LDO
SVM, SVS
BOR
(UART,
IrDA,SPI)
Timer_A
2 CC
Registers
Timer_A
3 CC
Registers
Port PJ
Copyright © 2016, Texas Instruments Incorporated
图 1-1. 功能框图 - MSP430F673xAIPZ 和 MSP430F672xAIPZ
图 1-2 给出了所有采用 PN 封装的器件型号的功能框图。
PB
PC
PA
DVCC DVSS AVCC AVSS
AUX1 AUX2 AUX3
XIN
XOUT
RST/NMI
P3.x
P4.x
P5.x P6.x
P1.x P2.x
(32 kHz)
ACLK
I/O Ports
P1, P2
2×8 I/Os
Interrupt,
Wakeup
I/O Ports
P3, P4
2×8 I/Os
I/O Ports
P5, P6
2×8 I/Os
SYS
Watchdog
Unified
Clock
System
8KB
4KB
2KB
1KB
128KB
96KB
64KB
32KB
16KB
DMA
CRC16
MPY32
SMCLK
3 Channel
Port
Mapping
Controller
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
MCLK
RAM
Flash
CPUXV2
and
Working
Registers
(25 MHz)
EEM
(S: 3+1)
TA1
TA2
TA3
PMM
Auxiliary
Supplies
eUSCI_A0
eUSCI_A1
eUSCI_A2
LCD_C
ADC10_A
REF
SD24_B
TA0
eUSCI_B0
(SPI, I2C)
JTAG,
SBW
Interface
RTC_C
8 mux
Up to 320
Segments
10 Bit
200 ksps
Reference
1.5 V, 2.0 V,
2.5 V
3 Channel
2 Channel
Timer_A
3 CC
Registers
Timer_A
2 CC
Registers
LDO
SVM, SVS
BOR
(UART,
IrDA, SPI)
Port PJ
Copyright © 2016, Texas Instruments Incorporated
图 1-2. 功能框图 - MSP430F673xAIPN 和 MSP430F672xAIPN
版权 © 2015–2018, Texas Instruments Incorporated
器件概述
3
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
内容
1
器件概述.................................................... 1
1.1 特性 ................................................... 1
1.2 应用 ................................................... 2
1.3 说明 ................................................... 2
1.4 功能框图 .............................................. 3
修订历史记录............................................... 5
Device Comparison ..................................... 6
3.1 Related Products ..................................... 7
Terminal Configuration and Functions.............. 8
4.1 Pin Diagrams ......................................... 8
4.2 Pin Attributes ........................................ 12
4.3 Signal Descriptions.................................. 22
4.4 Pin Multiplexing ..................................... 33
4.5 Buffer Type.......................................... 33
4.6 Connection of Unused Pins ......................... 33
Specifications ........................................... 34
5.1 Absolute Maximum Ratings ........................ 34
5.2 ESD Ratings ........................................ 34
5.3 Recommended Operating Conditions............... 34
6.1 Overview ............................................ 75
6.2 CPU ................................................. 75
6.3 Instruction Set....................................... 76
6.4 Operating Modes.................................... 77
6.5 Interrupt Vector Addresses.......................... 78
6.6 Bootloader (BSL).................................... 79
6.7 JTAG Operation ..................................... 79
6.8 Flash Memory ....................................... 80
6.9 RAM ................................................. 80
6.10 Backup RAM ........................................ 80
6.11 Peripherals .......................................... 81
6.12 Input/Output Diagrams .............................. 91
6.13 Device Descriptors (TLV) .......................... 123
6.14 Memory ............................................ 125
6.15 Identification........................................ 140
Applications, Implementation, and Layout ...... 141
器件和文档支持......................................... 142
8.1 入门和后续步骤 .................................... 142
8.2 Device Nomenclature.............................. 142
8.3 工具与软件 ......................................... 144
8.4 文档支持 ........................................... 146
8.5 相关链接 ........................................... 148
8.6 社区资源 ........................................... 148
8.7 商标 ................................................ 148
8.8 静电放电警告....................................... 149
8.9 Export Control Notice .............................. 149
8.10 Glossary............................................ 149
机械、封装和可订购信息 .............................. 149
2
3
4
5
7
8
5.4
5.5
5.6
Active Mode Supply Current Into VCC Excluding
External Current..................................... 36
Low-Power Mode Supply Currents (Into VCC
)
Excluding External Current.......................... 37
Low-Power Mode With LCD Supply Currents (Into
VCC) Excluding External Current.................... 38
5.7 Thermal Resistance Characteristics ................ 39
5.8 Timing and Switching Characteristics............... 40
Detailed Description ................................... 75
6
9
4
内容
版权 © 2015–2018, Texas Instruments Incorporated
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
2 修订历史记录
Changes from February 25, 2015 to October 3, 2018
Page
•
•
•
•
•
在以下位置添加了指向开发工具和设计中心的链接：特性....................................................................... 1
Added Section 3.1, Related Products ............................................................................................. 7
Added Section 4.5, Buffer Type ................................................................................................... 33
Added typical conditions statements at the beginning of Section 5, Specifications ........................................ 34
Added SD24_B input pins and AUXVCCx pins to exception list on "Voltage applied to pins" parameter, and
added SD24_B input pin limits in "Diode current at pins" parameter in Section 5.1, Absolute Maximum Ratings..... 34
Added Section 5.7, Thermal Resistance Characteristics ...................................................................... 39
Corrected nonvolatile memory type (changed "FRAM" to "flash") in 节 5.8.1, Power Supply Sequencing ............. 40
Updated notes (1) and (2) and added note (3) in Table 5-1, Wake-up Times From Low-Power Modes and Reset .. 40
Changed the MIN value of the V(DVCC_BOR_hys) parameter from 60 mV to 50 mV in Table 5-12, PMM, Brownout
Reset (BOR) ......................................................................................................................... 50
Replaced fFrame parameter with fLCD, fFRAME,4mux, and fFRAME,8mux parameters in Table 5-33, LCD_C Operating
Conditions ............................................................................................................................ 62
Removed ADC10DIV from the formula for the TYP value in the second row for tCONVERT in Table 5-44, 10-Bit
ADC, Timing Parameters, because fADC10CLK is after division ................................................................. 71
Updated Test Conditions for all parameters in Table 5-45, 10-Bit ADC, Linearity Parameters: changed from
"(VeREF+ – VeREF–)min ≤ (VeREF+ – VeREF–)" to "1.4 V ≤ (VeREF+ – VeREF–)" in all cases....................................... 72
Added "CVeREF+ = 20 pF" to EI Test Conditions.................................................................................. 72
Changed all instances of "bootloader" to "bootloader" ......................................................................... 79
Corrected spelling of NMIIFG in 表 6-9, System Module Interrupt Vector Registers....................................... 85
Corrected port number in title of 表 6-21, Port P2 (P2.0 and P2.1) Pin Functions (MSP430F67xxAIPZ Only)......... 96
将先前的开发工具支持部分替换为节 8.3工具与软件 .......................................................................... 144
更改了格式并在节 8.4文档支持 中添加了内容 ................................................................................. 146
•
•
•
•
•
•
•
•
•
•
•
•
•
Copyright © 2015–2018, Texas Instruments Incorporated
修订历史记录
5
Submit Documentation Feedback
Product Folder Links: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A
MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
3 Device Comparison
Table 3-1 summarizes the available family members.
Table 3-1. Device Comparison(1) (2)
eUSCI_A:
UART, IrDA,
SPI
eUSCI_B:
SPI, I2C
FLASH
(KB)
SRAM
(KB)
SD24_B
CONVERTERS
ADC10_A
CHANNELS
DEVICE
Timer_A(3)
I/Os
PACKAGE
MSP430F6736AIPZ
MSP430F6735AIPZ
MSP430F6734AIPZ
MSP430F6733AIPZ
MSP430F6731AIPZ
MSP430F6730AIPZ
MSP430F6726AIPZ
MSP430F6725AIPZ
MSP430F6724AIPZ
MSP430F6723AIPZ
MSP430F6721AIPZ
MSP430F6720AIPZ
MSP430F6736AIPN
MSP430F6735AIPN
MSP430F6734AIPN
MSP430F6733AIPN
MSP430F6731AIPN
MSP430F6730AIPN
MSP430F6726AIPN
MSP430F6725AIPN
MSP430F6724AIPN
MSP430F6723AIPN
MSP430F6721AIPN
MSP430F6720AIPN
128
128
96
8
4
4
4
2
1
8
4
4
4
2
1
8
4
4
4
2
1
8
4
4
4
2
1
3
3
3
3
3
3
2
2
2
2
2
2
3
3
3
3
3
3
2
2
2
2
2
2
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
3 ext, 2 int
3 ext, 2 int
3 ext, 2 int
3 ext, 2 int
3 ext, 2 int
3 ext, 2 int
3 ext, 2 int
3 ext, 2 int
3 ext, 2 int
3 ext, 2 int
3 ext, 2 int
3 ext, 2 int
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
72
72
72
72
72
72
72
72
72
72
72
72
52
52
52
52
52
52
52
52
52
52
52
52
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
80 PN
80 PN
80 PN
80 PN
80 PN
80 PN
80 PN
80 PN
80 PN
80 PN
80 PN
80 PN
64
32
16
128
128
96
64
32
16
128
128
96
64
32
16
128
128
96
64
32
16
(1) For the most current package and ordering information, see the Package Option Addendum in 节 9, or see the TI website at
www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
6
Device Comparison
Copyright © 2015–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A
MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
3.1 Related Products
For information about other devices in this family of products or related products, see the following links.
Products for TI Microcontrollers TI's low-power and high-performance MCUs, with wired and wireless
connectivity options, are optimized for a broad range of applications.
Products for MSP430 Ultra-Low-Power Microcontrollers One platform. One ecosystem. Endless
possibilities. Enabling the connected world with innovations in ultra-low-power
microcontrollers with advanced peripherals for precise sensing and measurement.
Companion Products for MSP430F6736A Review products that are frequently purchased or used with
this product.
Reference Designs for MSP430F6736A The TI Designs Reference Design Library is a robust reference
design library that spans analog, embedded processor, and connectivity. Created by TI
experts to help you jump start your system design, all TI Designs include schematic or block
diagrams, BOMs, and design files to speed your time to market.
Copyright © 2015–2018, Texas Instruments Incorporated
Device Comparison
7
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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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4 Terminal Configuration and Functions
4.1 Pin Diagrams
Figure 4-1 shows the pinout for the 100-pin PZ package. See Table 4-1 for differences between the
MSP430F673xA and MSP430F672xA devices in this package.
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
SD0P0
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DVSS
SD0N0
2
DVSYS
SD1P0
3
P6.0/S19
SD1N0
4
P5.7/S20
SD2P0
5
P5.6/S21
SD2N0
6
P5.5/S22
VREF
7
P5.4/S23
AVSS
8
P5.3/S24
AVCC
9
P5.2/S25
VASYS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P5.1/S26
P9.1/A5
P5.0/S27
P9.2/A4
P4.7/S28
P9.3/A3
P4.6/S29
P1.0/PM_TA0.0/VeREF-/A2
P4.5/S30
P1.1/PM_TA0.1/VeREF+/A1
P4.4/S31
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0
P4.3/S32
P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03
P4.2/S33
AUXVCC2
AUXVCC1
VDSYS
DVCC
P4.1/S34
P4.0/S35
P3.7/PM_SD2DIO/S36
P3.6/PM_SD1DIO/S37
P3.5/PM_SD0DIO/S38
P3.4/PM_SDCLK/S39
P3.3/PM_TA0.2
P3.2/PM_TACLK/PM_RTCCLK
DVSS
VCORE
XIN
XOUT
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NOTE: The secondary digital functions on Ports P1, P2, and P3 are fully mappable. This pinout shows the default mapping.
See 节 6.11.6 for details.
NOTE: The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
CAUTION: The LCDCAP/R33 pin must be connected to DVSS if not used.
Figure 4-1. 100-Pin PZ Package (Top View)
8
Terminal Configuration and Functions
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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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Table 4-1. Pinout Differences Between MSP430F673xAIPZ and
MSP430F672xAIPZ(1)
PIN NAME
PIN NUMBER
MSP430F673xAIPZ
MSP430F672xAIPZ
SD0P0
1
2
SD0P0
SD0N0
SD0N0
3
SD1P0
SD1P0
4
SD1N0
SD1N0
5
SD2P0
NC
6
SD2N0
NC
7
VREF
VREF
53
54
55
56
P3.4/PM_SDCLK/S39
P3.5/PM_SD0DIO/S38
P3.6/PM_SD1DIO/S37
P3.7/PM_SD2DIO/S36
P3.4/PM_SDCLK/S39
P3.5/PM_SD0DIO/S38
P3.6/PM_SD1DIO/S37
P3.7/PM_NONE/S36
(1) Signal names that differ between devices are indicated by italic typeface.
Copyright © 2015–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
9
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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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Figure 4-2 shows the pinout for the 80-pin PN package. See Table 4-2 for differences between the
MSP430F673xA and MSP430F672xA devices in this package.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
SD0P0
1
2
60 DVSS
SD0N0
59 DVSYS
SD1P0
3
58 P5.1/S14
SD1N0
4
57 P5.0/S15
SD2P0
5
56 P4.7/S16
SD2N0
6
55 P4.6/S17
VREF
7
54 P4.5/S18
AVSS
8
53 P4.4/S19
AVCC
9
52 P4.3/S20
VASYS
10
11
12
13
14
15
16
17
18
19
20
51 P4.2/S21
P1.0/PM_TA0.0/VeREF-/A2
50 P4.1/S22
P1.1/PM_TA0.1/VeREF+/A1
49 P4.0/S23
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0
48 P3.7/PM_SD2DIO/S24
47 P3.6/PM_SD1DIO/S25
46 P3.5/PM_SD0DIO/S26
45 P3.4/PM_SDCLK/S27
44 P3.3/PM_TA0.2/S28
43 P3.2/PM_TACLK/PM_RTCCLK/S29
42 P3.1/PM_TA2.1/S30/BSL_RX
41 P3.0/PM_TA2.0/S31/BSL_TX
P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03
AUXVCC2
AUXVCC1
VDSYS
DVCC
DVSS
VCORE
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NOTE: The secondary digital functions on Ports P1, P2, and P3 are fully mappable. This pinout shows the default mapping.
See 节 6.11.6 for details.
NOTE: The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
CAUTION: The LCDCAP/R33 pin must be connected to DVSS if not used.
Figure 4-2. 80-Pin PN Package (Top View)
10
Terminal Configuration and Functions
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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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Table 4-2. Pinout Differences Between MSP430F673xAIPN and
MSP430F672xAIPN(1)
PIN NAME
PIN NUMBER
MSP430F673xAIPN
MSP430F672xAIPN
SD0P0
1
2
SD0P0
SD0N0
SD0N0
3
SD1P0
SD1P0
4
SD1N0
SD1N0
5
SD2P0
NC
6
SD2N0
NC
7
VREF
VREF
45
46
47
48
P3.4/PM_SDCLK/S27
P3.5/PM_SD0DIO/S26
P3.6/PM_SD1DIO/S25
P3.7/PM_SD2DIO/S24
P3.4/PM_SDCLK/S27
P3.5/PM_SD0DIO/S26
P3.6/PM_SD1DIO/S25
P3.7/PM_NONE/S24
(1) Signal names that differ between devices are indicated by italic typeface.
Copyright © 2015–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
11
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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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4.2 Pin Attributes
Table 4-3 lists the pin attributes for all device variants in the PZ package. For the PN package, see
Table 4-4.
Table 4-3. Pin Attributes, PZ Package
RESET STATE AFTER
(1) (2)
(3)
(4)
PIN NO.
SIGNAL NAME
SIGNAL TYPE
BUFFER TYPE
POWER SOURCE
(5)
BOR
1
2
SD0P0
SD0N0
SD1P0
SD1N0
SD2P0
SD2N0
VREF
I
I
Analog
Analog
AVCC
AVCC
AVCC
AVCC
AVCC
AVCC
–
OFF
OFF
OFF
OFF
OFF
OFF
OFF
N/A
N/A
N/A
OFF
–
3
I
Analog
4
I
Analog
5
I
Analog
6
I
Analog
7
I
Analog
8
AVSS
P
P
P
I/O
I
Power
–
9
AVCC
Power
–
10
VASYS
P9.1
Power
–
LVCMOS
Analog
DVCC
AVCC
DVCC
AVCC
DVCC
AVCC
DVCC
DVCC
–
11
12
13
A5
P9.2
I/O
I
LVCMOS
Analog
OFF
–
A4
P9.3
I/O
I
LVCMOS
Analog
OFF
–
A3
P1.0
I/O
I/O
I
LVCMOS
LVCMOS
Power
OFF
–
PM_TA0.0
VeREF-
A2
14
15
16
17
N/A
–
I
Analog
AVCC
DVCC
DVCC
–
P1.1
I/O
I/O
I
LVCMOS
LVCMOS
Power
OFF
–
PM_TA0.1
VeREF+
A1
N/A
–
I
Analog
AVCC
DVCC
DVCC
DVCC
AVCC
DVCC
DVCC
DVCC
AVCC
–
P1.2
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
PM_UCA0RXD
PM_UCA0SOMI
A0
I/O
I
–
–
P1.3
I/O
O
I/O
I/O
P
P
P
P
P
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
PM_UCA0TXD
PM_UCA0SIMO
R03
–
–
18
19
20
21
22
AUXVCC2
AUXVCC1
VDSYS
DVCC
Power
N/A
N/A
N/A
N/A
N/A
Power
–
Power
–
Power
–
DVSS
Power
–
(1) For each multiplexed pin, the signal that is listed first in this table is the default after reset.
(2) To determine the pin mux encodings for each pin, refer to 节 6.12, Input/Output Diagrams.
(3) Signal Types: I = Input, O = Output, I/O = Input or Output.
(4) Buffer Types: LVCMOS, Analog, or Power (see Table 4-7, Buffer Type)
(5) Reset States:
OFF = High-impedance input with pullup or pulldown disabled (if available)
N/A = Not applicable
12
Terminal Configuration and Functions
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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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PIN NO.
Table 4-3. Pin Attributes, PZ Package (continued)
RESET STATE AFTER
(1) (2)
(3)
(4)
SIGNAL NAME
SIGNAL TYPE
BUFFER TYPE
POWER SOURCE
(5)
BOR
23
24
25
26
VCORE
XIN
P
I
Power
–
N/A
LVCMOS
LVCMOS
Power
DVCC
DVCC
–
OFF
OFF
N/A
OFF
–
XOUT
O
AUXVCC3
P1.4
P
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
AVCC
AVCC
DVCC
DVCC
DVCC
AVCC
AVCC
AVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
PM_UCA1RXD
PM_UCA1SOMI
LCDREF
R13
27
28
I/O
I
–
–
I/O
I/O
O
Analog
–
P1.5
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
PM_UCA1TXD
PM_UCA1SIMO
R23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
–
–
LCDCAP
R33
Analog
OFF
–
29
30
31
Analog
P8.4
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
OFF
–
TA1.0
P8.5
OFF
–
TA1.1
32
33
34
35
COM0
OFF
OFF
OFF
OFF
OFF
–
COM1
O
COM2
O
COM3
O
P1.6
I/O
I/O
O
36
37
PM_UCA0CLK
COM4
–
P1.7
I/O
I/O
O
OFF
–
PM_UCB0CLK
COM5
–
P2.0
I/O
I/O
I/O
O
OFF
–
PM_UCB0SOMI
PM_UCB0SCL
COM6
38
39
–
–
P2.1
I/O
I/O
I/O
O
OFF
–
PM_UCB0SIMO
PM_UCB0SDA
COM7
–
–
P8.6
I/O
I/O
I/O
I/O
I/O
I
OFF
–
40
41
TA2.0
P8.7
OFF
–
TA2.1
P9.0
OFF
–
42
43
TACLK
RTCCLK
P2.2
O
–
I/O
I
OFF
–
PM_UCA2RXD
PM_UCA2SOMI
I/O
–
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Terminal Configuration and Functions
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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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Table 4-3. Pin Attributes, PZ Package (continued)
RESET STATE AFTER
(1) (2)
(3)
(4)
PIN NO.
SIGNAL NAME
P2.3
SIGNAL TYPE
BUFFER TYPE
POWER SOURCE
(5)
BOR
I/O
O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
AVCC
DVCC
DVCC
AVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
OFF
–
44
PM_UCA2TXD
PM_UCA2SIMO
P2.4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
–
OFF
–
45
46
47
48
PM_UCA1CLK
P2.5
OFF
–
PM_UCA2CLK
P2.6
OFF
–
PM_TA1.0
P2.7
OFF
–
PM_TA1.1
P3.0
OFF
–
49
50
PM_TA2.0
BSL_TX
P3.1
–
I/O
I/O
I
OFF
–
PM_TA2.1
BSL_RX
P3.2
–
I/O
I
OFF
–
51
52
53
PM_TACLK
PM_RTCCLK
P3.3
O
–
I/O
I/O
I/O
I/O
O
OFF
–
PM_TA0.2
P3.4
OFF
–
PM_SDCLK
S39
–
P3.5
I/O
I/O
O
OFF
–
54
55
56
PM_SD0DIO
S38
LVCMOS
LVCMOS
Analog
–
P3.6
I/O
I/O
O
OFF
–
PM_SD1DIO
S37
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
–
P3.7
I/O
I/O
O
OFF
–
PM_SD2DIO
S36
–
P4.0
I/O
O
OFF
–
57
58
59
60
61
62
S35
P4.1
I/O
O
OFF
–
S34
P4.2
I/O
O
OFF
–
S33
P4.3
I/O
O
OFF
–
S32
P4.4
I/O
O
OFF
–
S31
P4.5
I/O
O
OFF
–
S30
14
Terminal Configuration and Functions
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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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Table 4-3. Pin Attributes, PZ Package (continued)
RESET STATE AFTER
(1) (2)
(3)
(4)
PIN NO.
SIGNAL NAME
P4.6
SIGNAL TYPE
BUFFER TYPE
POWER SOURCE
(5)
BOR
I/O
O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Power
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
–
OFF
63
S29
P4.7
S28
P5.0
S27
P5.1
S26
P5.2
S25
P5.3
S24
P5.4
S23
P5.5
S22
P5.6
S21
P5.7
S20
P6.0
S19
DVSYS
DVSS
P6.1
S18
P6.2
S17
P6.3
S16
P6.4
S15
P6.5
S14
P6.6
S13
P6.7
S12
P7.0
S11
P7.1
S10
P7.2
S9
–
I/O
O
OFF
–
64
65
66
67
68
69
70
71
72
73
I/O
O
OFF
–
I/O
O
OFF
–
I/O
O
OFF
–
I/O
O
OFF
–
I/O
O
OFF
–
I/O
O
OFF
–
I/O
O
OFF
–
I/O
O
OFF
–
I/O
O
OFF
–
74
75
P
N/A
N/A
OFF
–
P
Power
–
I/O
O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
76
77
78
79
80
81
82
83
84
85
86
I/O
O
OFF
–
I/O
O
OFF
–
I/O
O
OFF
–
I/O
O
OFF
–
I/O
O
OFF
–
I/O
O
OFF
–
I/O
O
OFF
–
I/O
O
OFF
–
I/O
O
OFF
–
P7.3
S8
I/O
O
OFF
–
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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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Table 4-3. Pin Attributes, PZ Package (continued)
RESET STATE AFTER
(1) (2)
(3)
(4)
PIN NO.
SIGNAL NAME
P7.4
SIGNAL TYPE
BUFFER TYPE
POWER SOURCE
(5)
BOR
I/O
O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
OFF
–
87
S7
P7.5
S6
I/O
O
OFF
–
88
89
90
91
92
93
94
95
P7.6
S5
I/O
O
OFF
–
P7.7
S4
I/O
O
OFF
–
P8.0
S3
I/O
O
OFF
–
P8.1
S2
I/O
O
OFF
–
P8.2
S1
I/O
O
OFF
–
P8.3
S0
I/O
O
OFF
–
TEST
SBWTCK
PJ.0
SMCLK
TDO
PJ.1
MCLK
TDI
I
OFF
–
I
I/O
O
OFF
–
96
97
O
–
I/O
O
OFF
–
I
–
TCLK
PJ.2
ADC10CLK
TMS
PJ.3
ACLK
TCK
RST
NMI
I
–
I/O
O
OFF
–
98
99
I
–
I/O
O
OFF
–
I
–
I
PU
–
100
I
SBWTDIO
I/O
–
16
Terminal Configuration and Functions
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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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Table 4-4 lists the pin attributes for all device variants in the PN package. For the PZ package, see
Table 4-3.
Table 4-4. Pin Attributes, PN Package
(1)
SIGNAL NAME
RESET STATE AFTER
(3)
(4)
PIN NO.
SIGNAL TYPE
BUFFER TYPE
POWER SOURCE
(2)
(5)
BOR
1
2
SD0P0
SD0N0
SD1P0
SD1N0
SD2P0
SD2N0
VREF
I
I
Analog
Analog
Analog
Analog
Analog
Analog
Power
AVCC
AVCC
AVCC
AVCC
AVCC
AVCC
–
OFF
OFF
OFF
OFF
OFF
OFF
N/A
N/A
N/A
N/A
OFF
–
3
I
4
I
5
I
6
I
7
I
8
AVSS
P
P
P
I/O
I/O
I
Power
–
9
AVCC
Power
–
10
VASYS
P1.0
Power
–
LVCMOS
LVCMOS
Power
DVCC
DVCC
–
PM_TA0.0
VeREF-
A2
11
12
13
14
–
I
Analog
LVCMOS
LVCMOS
Power
AVCC
DVCC
DVCC
–
–
P1.1
I/O
I/O
I
OFF
–
PM_TA0.1
VeREF+
A1
–
I
Analog
LVCMOS
LVCMOS
LVCMOS
Analog
LVCMOS
LVCMOS
LVCMOS
Analog
Power
AVCC
DVCC
DVCC
DVCC
AVCC
DVCC
DVCC
DVCC
AVCC
–
–
P1.2
I/O
I
OFF
–
PM_UCA0RXD
PM_UCA0SOMI
A0
I/O
I
–
–
P1.3
I/O
O
I/O
I/O
P
P
P
P
P
P
I
OFF
–
PM_UCA0TXD
PM_UCA0SIMO
R03
–
–
15
16
17
18
19
20
21
22
23
AUXVCC2
AUXVCC1
VDSYS
DVCC
N/A
N/A
N/A
N/A
N/A
N/A
OFF
OFF
N/A
Power
–
Power
–
Power
–
DVSS
Power
–
VCORE
XIN
Power
–
LVCMOS
LVCMOS
Power
DVCC
DVCC
–
XOUT
O
P
AUXVCC3
(1) For each multiplexed pin, the signal that is listed first in this table is the default after reset.
(2) To determine the pin mux encodings for each pin, refer to 节 6.12, Input/Output Diagrams.
(3) Signal Types: I = Input, O = Output, I/O = Input or Output.
(4) Buffer Types: LVCMOS, Analog, or Power (see Table 4-7, Buffer Type)
(5) Reset States:
OFF = High-impedance input with pullup or pulldown disabled (if available)
N/A = Not applicable
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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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Table 4-4. Pin Attributes, PN Package (continued)
(1)
SIGNAL NAME
RESET STATE AFTER
(3)
(4)
PIN NO.
SIGNAL TYPE
BUFFER TYPE
POWER SOURCE
(2)
(5)
BOR
P1.4
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
AVCC
AVCC
DVCC
DVCC
DVCC
AVCC
AVCC
AVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
OFF
–
PM_UCA1RXD
PM_UCA1SOMI
LCDREF
R13
24
I/O
I
–
–
I/O
I/O
O
Analog
–
P1.5
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
PM_UCA1TXD
PM_UCA1SIMO
R23
25
26
I/O
I/O
I/O
I/O
O
–
–
LCDCAP
R33
Analog
OFF
OFF
OFF
OFF
OFF
OFF
OFF
–
Analog
27
28
29
30
COM0
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
COM1
O
COM2
O
COM3
O
P1.6
I/O
I/O
O
31
32
PM_UCA0CLK
COM4
–
P1.7
I/O
I/O
O
OFF
–
PM_UCB0CLK
COM5
–
P2.0
I/O
I/O
I/O
O
OFF
–
PM_UCB0SOMI
PM_UCB0SCL
COM6
33
34
–
–
S39
O
–
P2.1
I/O
I/O
I/O
O
OFF
–
PM_UCB0SIMO
PM_UCB0SDA
COM7
–
–
S38
O
–
P2.2
I/O
I
OFF
–
PM_UCA2RXD
PM_UCA2SOMI
S37
35
36
I/O
O
–
–
P2.3
I/O
O
OFF
–
PM_UCA2TXD
PM_UCA2SIMO
S36
I/O
O
–
–
P2.4
I/O
I/O
O
OFF
–
37
38
PM_UCA1CLK
S35
–
P2.5
I/O
I/O
O
OFF
–
PM_UCA2CLK
S34
–
18
Terminal Configuration and Functions
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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
Table 4-4. Pin Attributes, PN Package (continued)
(1)
SIGNAL NAME
RESET STATE AFTER
(3)
(4)
PIN NO.
SIGNAL TYPE
BUFFER TYPE
POWER SOURCE
(2)
(5)
BOR
P2.6
I/O
I/O
O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
OFF
39
PM_TA1.0
S33
–
–
P2.7
I/O
I/O
O
OFF
–
40
41
PM_TA1.1
S32
–
P3.0
I/O
I/O
O
OFF
–
PM_TA2.0
S31
–
BSL_TX
P3.1
O
–
I/O
I/O
O
OFF
–
PM_TA2.1
S30
42
43
–
BSL_RX
P3.2
I
–
I/O
I
OFF
–
PM_TACLK
PM_RTCCLK
S29
O
–
O
–
P3.3
I/O
I/O
O
OFF
–
44
45
46
47
48
PM_TA0.2
S28
–
P3.4
I/O
I/O
O
OFF
–
PM_SDCLK
S27
–
P3.5
I/O
I/O
O
OFF
–
PM_SD0DIO
S26
–
P3.6
I/O
I/O
O
OFF
–
PM_SD1DIO
S25
–
P3.7
I/O
I/O
O
OFF
–
PM_SD2DIO
S24
–
P4.0
I/O
O
OFF
–
49
50
51
52
53
54
55
S23
P4.1
I/O
O
OFF
–
S22
P4.2
I/O
O
OFF
–
S21
P4.3
I/O
O
OFF
–
S20
P4.4
I/O
O
OFF
–
S19
P4.5
I/O
O
OFF
–
S18
P4.6
I/O
O
OFF
–
S17
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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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Table 4-4. Pin Attributes, PN Package (continued)
(1)
SIGNAL NAME
RESET STATE AFTER
(3)
(4)
PIN NO.
SIGNAL TYPE
BUFFER TYPE
POWER SOURCE
(2)
(5)
BOR
P4.7
S16
P5.0
S15
P5.1
S14
DVSYS
DVSS
P5.2
S13
P5.3
S12
P5.4
S11
P5.5
S10
P5.6
S9
I/O
O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Power
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
–
OFF
–
56
I/O
O
OFF
–
57
58
I/O
O
OFF
–
59
60
P
N/A
N/A
OFF
–
P
Power
–
I/O
O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
I/O
O
OFF
–
I/O
O
OFF
–
I/O
O
OFF
–
I/O
O
OFF
–
P5.7
S8
I/O
O
OFF
–
P6.0
S7
I/O
O
OFF
–
P6.1
S6
I/O
O
OFF
–
P6.2
S5
I/O
O
OFF
–
P6.3
S4
I/O
O
OFF
–
P6.4
S3
I/O
O
OFF
–
P6.5
S2
I/O
O
OFF
–
P6.6
S1
I/O
O
OFF
–
P6.7
S0
I/O
O
OFF
–
TEST
I
OFF
–
SBWTCK
PJ.0
I
I/O
O
OFF
–
76
77
SMCLK
TDO
O
–
PJ.1
I/O
O
OFF
–
MCLK
TDI
I
–
TCLK
I
–
20
Terminal Configuration and Functions
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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
Table 4-4. Pin Attributes, PN Package (continued)
(1)
SIGNAL NAME
RESET STATE AFTER
(3)
(4)
PIN NO.
SIGNAL TYPE
BUFFER TYPE
POWER SOURCE
(2)
(5)
BOR
PJ.2
I/O
O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
OFF
78
ADC10CLK
TMS
–
–
I
PJ.3
I/O
O
OFF
–
79
80
ACLK
TCK
I
–
RST
I/O
I
PU
–
NMI
SBWTDIO
I/O
–
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Terminal Configuration and Functions
21
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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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4.3 Signal Descriptions
Table 4-5 describes the signals for all device variants in the PZ package. See Table 4-6 for signal
descriptions in the PN package.
Table 4-5. Signal Descriptions, PZ Package
SIGNAL
TYPE
FUNCTION
SIGNAL NAME
A0
PIN NO.
DESCRIPTION
16
15
14
13
12
11
98
I
I
Analog input A0 for 10-bit ADC
A1
Analog input A1 for 10-bit ADC
Analog input A2 for 10-bit ADC
Analog input A3 for 10-bit ADC
Analog input A4 for 10-bit ADC
Analog input A5 for 10-bit ADC
ADC10_A clock output
A2
I
A3
I
A4
I
ADC10
A5
I
ADC10CLK
O
Positive terminal for the ADC reference voltage for an external applied
reference voltage
VeREF+
VeREF-
15
14
I
I
Negative terminal for the ADC reference voltage for an external applied
reference voltage
BSL_RX
BSL_TX
ACLK
50
49
99
97
51
42
96
24
25
95
100
99
97
97
96
95
98
I
O
O
O
O
O
O
I
Bootloader data receive
Bootloader data transmit
ACLK clock output
BSL
MCLK
MCLK clock output
PM_RTCCLK
RTCCLK
SMCLK
XIN
Default mapping: RTCCLK clock output
RTCCLK clock output
Clock
SMCLK clock output
Input terminal for crystal oscillator
Output terminal for crystal oscillator
Spy-Bi-Wire input clock
Spy-Bi-Wire data input/output
Test clock
XOUT
O
I
SBWTCK
SBWTDIO
TCK
I/O
I
TCLK
I
Test clock input
Debug
TDI
I
Test data input
TDO
O
I
Test data output
TEST
Test mode pin – select digital I/O on JTAG pins
Test mode select
TMS
I
General-purpose digital I/O with port interrupt and mappable secondary
function
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
14
15
16
17
27
28
36
37
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O with port interrupt and mappable secondary
function
General-purpose digital I/O with port interrupt and mappable secondary
function
General-purpose digital I/O with port interrupt and mappable secondary
function
GPIO
General-purpose digital I/O with port interrupt and mappable secondary
function
General-purpose digital I/O with port interrupt and mappable secondary
function
General-purpose digital I/O with port interrupt and mappable secondary
function
General-purpose digital I/O with port interrupt and mappable secondary
function
22
Terminal Configuration and Functions
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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
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FUNCTION
Table 4-5. Signal Descriptions, PZ Package (continued)
SIGNAL
TYPE
SIGNAL NAME
P2.0
PIN NO.
38
DESCRIPTION
General-purpose digital I/O with port interrupt and mappable secondary
function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.1
39
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.2
43
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.3
44
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.4
45
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.5
46
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.6
47
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.7
48
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
76
77
78
79
80
81
82
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O with mappable secondary function
General-purpose digital I/O with mappable secondary function
General-purpose digital I/O with mappable secondary function
General-purpose digital I/O with mappable secondary function
General-purpose digital I/O with mappable secondary function
General-purpose digital I/O with mappable secondary function
General-purpose digital I/O with mappable secondary function
General-purpose digital I/O with mappable secondary function
General-purpose digital I/O
GPIO
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
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Terminal Configuration and Functions
23
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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
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Table 4-5. Signal Descriptions, PZ Package (continued)
SIGNAL
TYPE
FUNCTION
SIGNAL NAME
PIN NO.
DESCRIPTION
P7.0
83
84
85
86
87
88
89
90
91
92
93
94
30
31
40
41
42
11
12
13
96
97
98
99
38
39
32
33
34
35
36
37
38
39
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
P8.0
P8.1
P8.2
P8.3
GPIO
P8.4
P8.5
P8.6
P8.7
P9.0
P9.1
P9.2
P9.3
PJ.0
PJ.1
PJ.2
PJ.3
PM_UCB0SCL
PM_UCB0SDA
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
Default mapping: eUSCI_B0 I2C clock
Default mapping: eUSCI_B0 I2C data
I2C
LCD common output COM0 for LCD backplane
LCD common output COM1 for LCD backplane
LCD common output COM2 for LCD backplane
LCD common output COM3 for LCD backplane
LCD common output COM4 for LCD backplane
LCD common output COM5 for LCD backplane
LCD common output COM6 for LCD backplane
LCD common output COM7 for LCD backplane
O
O
O
O
O
O
O
LCD
LCD capacitor connection
CAUTION: This pin must be connected to DVSS if not used.
LCDCAP
29
I/O
LCDREF
R03
27
17
27
28
I
External reference voltage input for regulated LCD voltage
Input/output port of lowest analog LCD voltage (V5)
I/O
I/O
I/O
R13
Input/output port of third most positive analog LCD voltage (V3 or V4)
Input/output port of second most positive analog LCD voltage (V2)
R23
Input/output port of most positive analog LCD voltage (V1)
CAUTION: This pin must be connected to DVSS if not used.
R33
29
I/O
24
Terminal Configuration and Functions
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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
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FUNCTION
Table 4-5. Signal Descriptions, PZ Package (continued)
SIGNAL
TYPE
SIGNAL NAME
PIN NO.
DESCRIPTION
S0
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
LCD segment output S0
LCD segment output S1
LCD segment output S2
LCD segment output S3
LCD segment output S4
LCD segment output S5
LCD segment output S6
LCD segment output S7
LCD segment output S8
LCD segment output S9
LCD segment output S10
LCD segment output S11
LCD segment output S12
LCD segment output S13
LCD segment output S14
LCD segment output S15
LCD segment output S16
LCD segment output S17
LCD segment output S18
LCD segment output S19
LCD segment output S20
LCD segment output S21
LCD segment output S22
LCD segment output S23
LCD segment output S24
LCD segment output S25
LCD segment output S26
LCD segment output S27
LCD segment output S28
LCD segment output S29
LCD segment output S30
LCD segment output S31
LCD segment output S32
LCD segment output S33
LCD segment output S34
LCD segment output S35
LCD segment output S36
LCD segment output S37
LCD segment output S38
LCD segment output S39
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
LCD
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Terminal Configuration and Functions
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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
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Table 4-5. Signal Descriptions, PZ Package (continued)
SIGNAL
TYPE
FUNCTION
SIGNAL NAME
PIN NO.
DESCRIPTION
AUXVCC1
AUXVCC2
AUXVCC3
AVCC
19
18
26
9
P
P
P
P
P
P
Auxiliary power supply AUXVCC1
Auxiliary power supply AUXVCC2
Auxiliary power supply AUXVCC3 for back up subsystem
Analog power supply
AVSS
8
Analog ground supply
DVCC
21
Digital power supply
22
75
DVSS
P
P
P
Digital ground supply
Power
DVSYS(1)
VASYS
74
Digital power supply for I/Os
Analog power supply selected among AVCC, AUXVCC1, AUXVCC2.
Connect recommended capacitor value of CVSYS (see Table 5-18).
10
Regulated core power supply (internal use only, no external current
loading)
VCORE(2)
VDSYS(1)
23
20
P
P
Digital power supply selected between DVCC, AUXVCC1, AUXVCC2.
Connect recommended capacitor value of CVSYS (see Table 5-18).
PM_SD0DIO
PM_SD1DIO
54
55
I/O
I/O
Default mapping: SD24_B converter 0 bit stream data input/output
Default mapping: SD24_B converter 1 bit stream data input/output
Default mapping: SD24_B converter 2 bit stream data input/output (not
available on F672xA devices)
PM_SD2DIO
56
I/O
PM_SDCLK
SD0N0
53
2
I/O
Default mapping: SD24_B bit stream clock input/output
SD24_B negative analog input for converter 0(3)
SD24_B positive analog input for converter 0(3)
SD24_B negative analog input for converter 1(3)
SD24_B positive analog input for converter 1(3)
I
I
I
I
SD0P0
1
SD24
SD1N0
4
SD1P0
3
SD24_B negative analog input for converter 2(3) (not available on F672xA
devices)
SD24_B positive analog input for converter 2(3) (not available on F672xA
devices)
SD2N0
SD2P0
6
5
I
I
VREF
7
36
17
16
45
28
27
46
44
43
37
39
38
100
100
O
SD24_B external reference voltage
PM_UCA0CLK
PM_UCA0SIMO
PM_UCA0SOMI
PM_UCA1CLK
PM_UCA1SIMO
PM_UCA1SOMI
PM_UCA2CLK
PM_UCA2SIMO
PM_UCA2SOMI
PM_UCB0CLK
PM_UCB0SIMO
PM_UCB0SOMI
NMI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Default mapping: eUSCI_A0 clock input/output
Default mapping: eUSCI_A0 SPI slave in/master out
Default mapping: eUSCI_A0 SPI slave out/master in
Default mapping: eUSCI_A1 clock input/output
Default mapping: eUSCI_A1 SPI slave in/master out
Default mapping: eUSCI_A1 SPI slave out/master in
Default mapping: eUSCI_A2 clock input/output
Default mapping: eUSCI_A2 SPI slave in/master out
Default mapping: eUSCI_A2 SPI slave out/master in
Default mapping: eUSCI_B0 clock input/output
Default mapping: eUSCI_B0 SPI slave in/master out
Default mapping: eUSCI_B0 SPI slave out/master in
Nonmaskable interrupt input
SPI
System
RST
I
Reset input active low(4)
(1) The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE
.
(3) TI recommends shorting unused analog input pairs and connect them to analog ground.
(4) When this pin is configured as reset, the internal pullup resistor is enabled by default.
26
Terminal Configuration and Functions
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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
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FUNCTION
Table 4-5. Signal Descriptions, PZ Package (continued)
SIGNAL
TYPE
SIGNAL NAME
PM_TA0.0
PM_TA0.1
PM_TA0.2
PM_TA1.0
PM_TA1.1
PM_TA2.0
PM_TA2.1
PIN NO.
14
DESCRIPTION
Default mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0
output
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Default mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1
output
15
Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2
output
52
Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0
output
47
Default mapping: Timer TA1 capture CCR1: CCI1A input, compare: Out1
output
48
Timer_A
Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0
output
49
Default mapping: Timer TA2 capture CCR1: CCI1A input, compare: Out1
output
50
PM_TACLK
TA1.0
51
30
31
40
41
42
16
17
27
28
43
44
I
I/O
I/O
I/O
I/O
I
Default mapping: Timer clock input TACLK for TA0, TA1, TA2, TA3
Timer TA1 CCR0 capture: CCI0A input, compare: Out0 output
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output
Timer TA2 CCR0 capture: CCI0A input, compare: Out0 output
Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output
Timer clock input TACLK for TA0, TA1, TA2, TA3
TA1.1
TA2.0
TA2.1
TACLK
PM_UCA0RXD
PM_UCA0TXD
PM_UCA1RXD
PM_UCA1TXD
PM_UCA2RXD
PM_UCA2TXD
I
Default mapping: eUSCI_A0 UART receive data
O
I
Default mapping: eUSCI_A0 UART transmit data
Default mapping: eUSCI_A1 UART receive data
UART
O
I
Default mapping: eUSCI_A1 UART transmit data
Default mapping: eUSCI_A2 UART receive data
O
Default mapping: eUSCI_A2 UART transmit data
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Terminal Configuration and Functions
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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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Table 4-6 describes the signals for all device variants in the PN package. See Table 4-5 for signal
descriptions in the PZ package.
Table 4-6. Signal Descriptions, PN Package
SIGNAL
FUNCTION
SIGNAL NAME
A0
PIN NO.
DESCRIPTION
TYPE(1)
13
12
11
78
I
I
Analog input A0 for 10-bit ADC
A1
Analog input A1 for 10-bit ADC
Analog input A2 for 10-bit ADC
ADC10_A clock output
A2
I
ADC10CLK
O
ADC10
Positive terminal for the ADC reference voltage for an external
applied reference voltage
VeREF+
VeREF-
12
11
I
I
Negative terminal for the ADC reference voltage for an external
applied reference voltage
BSL_RX
BSL_TX
ACLK
42
41
79
77
43
76
21
22
75
80
79
77
77
76
75
78
I
O
O
O
O
O
I
Bootloader data receive
Bootloader data transmit
ACLK clock output
BSL
MCLK
PM_RTCCLK
SMCLK
XIN
MCLK clock output
Default mapping: RTCCLK clock output
SMCLK clock output
Clock
Input terminal for crystal oscillator
Output terminal for crystal oscillator
Spy-Bi-Wire input clock
Spy-Bi-Wire data input/output
Test clock
XOUT
SBWTCK
SBWTDIO
TCK
O
I
I/O
I
TCLK
I
Test clock input
Debug
TDI
I
Test data input
TDO
O
I
Test data output
TEST
Test mode pin – select digital I/O on JTAG pins
Test mode select
TMS
I
General-purpose digital I/O with port interrupt and mappable
secondary function
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
11
12
13
14
24
25
31
32
33
34
35
36
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O with port interrupt and mappable
secondary function
General-purpose digital I/O with port interrupt and mappable
secondary function
General-purpose digital I/O with port interrupt and mappable
secondary function
General-purpose digital I/O with port interrupt and mappable
secondary function
General-purpose digital I/O with port interrupt and mappable
secondary function
GPIO
General-purpose digital I/O with port interrupt and mappable
secondary function
General-purpose digital I/O with port interrupt and mappable
secondary function
General-purpose digital I/O with port interrupt and mappable
secondary function
General-purpose digital I/O with port interrupt and mappable
secondary function
General-purpose digital I/O with port interrupt and mappable
secondary function
General-purpose digital I/O with port interrupt and mappable
secondary function
(1) I = input, O = output
28 Terminal Configuration and Functions
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FUNCTION
Table 4-6. Signal Descriptions, PN Package (continued)
SIGNAL
TYPE(1)
SIGNAL NAME
P2.4
PIN NO.
37
DESCRIPTION
General-purpose digital I/O with port interrupt and mappable
secondary function
I/O
I/O
I/O
I/O
General-purpose digital I/O with port interrupt and mappable
secondary function
P2.5
P2.6
P2.7
38
General-purpose digital I/O with port interrupt and mappable
secondary function
39
General-purpose digital I/O with port interrupt and mappable
secondary function
40
P3.0
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
69
70
71
72
73
74
76
77
78
79
33
34
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O with mappable secondary function
General-purpose digital I/O with mappable secondary function
General-purpose digital I/O with mappable secondary function
General-purpose digital I/O with mappable secondary function
General-purpose digital I/O with mappable secondary function
General-purpose digital I/O with mappable secondary function
General-purpose digital I/O with mappable secondary function
General-purpose digital I/O with mappable secondary function
General-purpose digital I/O
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
General-purpose digital I/O
P4.2
General-purpose digital I/O
P4.3
General-purpose digital I/O
P4.4
General-purpose digital I/O
P4.5
General-purpose digital I/O
P4.6
General-purpose digital I/O
GPIO
P4.7
General-purpose digital I/O
P5.0
General-purpose digital I/O
P5.1
General-purpose digital I/O
P5.2
General-purpose digital I/O
P5.3
General-purpose digital I/O
P5.4
General-purpose digital I/O
P5.5
General-purpose digital I/O
P5.6
General-purpose digital I/O
P5.7
General-purpose digital I/O
P6.0
General-purpose digital I/O
P6.1
General-purpose digital I/O
P6.2
General-purpose digital I/O
P6.3
General-purpose digital I/O
P6.4
General-purpose digital I/O
P6.5
General-purpose digital I/O
P6.6
General-purpose digital I/O
P6.7
General-purpose digital I/O
PJ.0
General-purpose digital I/O
PJ.1
General-purpose digital I/O
PJ.2
General-purpose digital I/O
PJ.3
General-purpose digital I/O
PM_UCB0SCL
PM_UCB0SDA
Default mapping: eUSCI_B0 I2C clock
Default mapping: eUSCI_B0 I2C data
I2C
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Table 4-6. Signal Descriptions, PN Package (continued)
SIGNAL
TYPE(1)
FUNCTION
SIGNAL NAME
PIN NO.
DESCRIPTION
COM0
27
28
29
30
31
32
33
34
O
O
O
O
O
O
O
O
LCD common output COM0 for LCD backplane
LCD common output COM1 for LCD backplane
LCD common output COM2 for LCD backplane
LCD common output COM3 for LCD backplane
LCD common output COM4 for LCD backplane
LCD common output COM5 for LCD backplane
LCD common output COM6 for LCD backplane
LCD common output COM7 for LCD backplane
LCD capacitor connection
COM1
COM2
COM3
COM4
COM5
COM6
COM7
LCDCAP
26
I/O
CAUTION: This pin must be connected to DVSS if not used.
External reference voltage input for regulated LCD voltage
Input/output port of lowest analog LCD voltage (V5)
LCDREF
R03
24
14
I
I/O
Input/output port of third most positive analog LCD voltage (V3 or
V4)
R13
R23
R33
24
25
26
I/O
I/O
I/O
Input/output port of second most positive analog LCD voltage (V2)
Input/output port of most positive analog LCD voltage (V1)
CAUTION: This pin must be connected to DVSS if not used.
S0
74
73
72
71
70
69
68
67
66
65
64
63
62
61
58
57
56
55
54
53
52
51
50
49
48
47
46
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
LCD segment output S0
LCD segment output S1
LCD segment output S2
LCD segment output S3
LCD segment output S4
LCD segment output S5
LCD segment output S6
LCD segment output S7
LCD segment output S8
LCD segment output S9
LCD segment output S10
LCD segment output S11
LCD segment output S12
LCD segment output S13
LCD segment output S14
LCD segment output S15
LCD segment output S16
LCD segment output S17
LCD segment output S18
LCD segment output S19
LCD segment output S20
LCD segment output S21
LCD segment output S22
LCD segment output S23
LCD segment output S24
LCD segment output S25
LCD segment output S26
S1
S2
S3
S4
LCD
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
30
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FUNCTION
Table 4-6. Signal Descriptions, PN Package (continued)
SIGNAL
TYPE(1)
SIGNAL NAME
PIN NO.
DESCRIPTION
S27
45
44
43
42
41
40
39
38
37
36
35
34
33
16
15
23
9
O
O
O
O
O
O
O
O
O
O
O
O
O
P
P
P
P
P
P
P
P
P
LCD segment output S27
LCD segment output S28
LCD segment output S29
LCD segment output S30
LCD segment output S31
LCD segment output S32
LCD segment output S33
LCD segment output S34
LCD segment output S35
LCD segment output S36
LCD segment output S37
LCD segment output S38
LCD segment output S39
S28
S29
S30
S31
S32
LCD
S33
S34
S35
S36
S37
S38
S39
AUXVCC1
AUXVCC2
AUXVCC3
AVCC
AVSS
DVCC
DVSS
DVSS
DVSYS(2)
Auxiliary power supply AUXVCC1
Auxiliary power supply AUXVCC2
Auxiliary power supply AUXVCC3 for backup subsystem
Analog power supply
8
Analog ground supply
18
19
60
59
Digital power supply
Digital ground supply
Digital ground supply
Power
Digital power supply for I/Os
Analog power supply selected between AVCC, AUXVCC1,
AUXVCC2. Connect recommended capacitor value of CVSYS (see
Table 5-18).
VASYS
10
20
17
P
P
P
Regulated core power supply (internal use only, no external current
loading)
VCORE(3)
VDSYS(2)
Digital power supply selected between DVCC, AUXVCC1,
AUXVCC2. Connect recommended capacitor value of CVSYS (see
Table 5-18).
PM_SD0DIO
PM_SD1DIO
46
47
I/O
I/O
Default mapping: SD24_B converter 0 bit stream data input/output
Default mapping: SD24_B converter 1 bit stream data input/output
Default mapping: SD24_B converter 2 bit stream data input/output
(not available on F672xA devices)
PM_SD2DIO
48
I/O
PM_SDCLK
SD0N0
45
2
I/O
Default mapping: SD24_B bit stream clock input/output
SD24_B negative analog input for converter 0(4)
SD24_B positive analog input for converter 0(4)
SD24_B negative analog input for converter 1(4)
SD24_B positive analog input for converter 1(4)
I
I
I
I
SD0P0
1
SD24
SD1N0
4
SD1P0
3
SD24_B negative analog input for converter 2(4) (not available on
F672xA devices)
SD2N0
6
I
SD24_B positive analog input for converter 2(4) (not available on
F672xA devices)
SD2P0
VREF
5
7
I
I
SD24_B external reference voltage
(2) The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
(3) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE
.
(4) TI recommends shorting unused analog input pairs and connect them to analog ground.
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Table 4-6. Signal Descriptions, PN Package (continued)
SIGNAL
TYPE(1)
FUNCTION
SIGNAL NAME
PIN NO.
DESCRIPTION
PM_UCA0CLK
PM_UCA0SIMO
PM_UCA0SOMI
PM_UCA1CLK
PM_UCA1SIMO
PM_UCA1SOMI
PM_UCA2CLK
PM_UCA2SIMO
PM_UCA2SOMI
PM_UCB0CLK
PM_UCB0SIMO
PM_UCB0SOMI
NMI
31
14
13
37
25
24
38
36
35
32
34
33
80
80
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Default mapping: eUSCI_A0 clock input/output
Default mapping: eUSCI_A0 SPI slave in/master out
Default mapping: eUSCI_A0 SPI slave out/master in
Default mapping: eUSCI_A1 clock input/output
Default mapping: eUSCI_A1 SPI slave in/master out
Default mapping: eUSCI_A1 SPI slave out/master in
Default mapping: eUSCI_A2 clock input/output
Default mapping: eUSCI_A2 SPI slave in/master out
Default mapping: eUSCI_A2 SPI slave out/master in
Default mapping: eUSCI_B0 clock input/output
Default mapping: eUSCI_B0 SPI slave in/master out
Default mapping: eUSCI_B0 SPI slave out/master in
Nonmaskable interrupt input
SPI
System
RST
I/O
Reset input active low(5)
Default mapping: Timer TA0 CCR0 capture: CCI0A input, compare:
Out0 output
PM_TA0.0
PM_TA0.1
PM_TA0.2
PM_TA1.0
PM_TA1.1
PM_TA2.0
PM_TA2.1
11
12
44
39
40
41
42
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Default mapping: Timer TA0 CCR1 capture: CCI1A input, compare:
Out1 output
Default mapping: Timer TA0 capture CCR2: CCI2A input, compare:
Out2 output
Default mapping: Timer TA1 capture CCR0: CCI0A input, compare:
Out0 output
Timer_A
Default mapping: Timer TA1 capture CCR1: CCI1A input, compare:
Out1 output
Default mapping: Timer TA2 capture CCR0: CCI0A input, compare:
Out0 output
Default mapping: Timer TA2 capture CCR1: CCI1A input, compare:
Out1 output
PM_TACLK
43
13
14
24
25
35
36
I
I
Default mapping: Timer clock input TACLK for TA0, TA1, TA2, TA3
Default mapping: eUSCI_A0 UART receive data
Default mapping: eUSCI_A0 UART transmit data
Default mapping: eUSCI_A1 UART receive data
Default mapping: eUSCI_A1 UART transmit data
Default mapping: eUSCI_A2 UART receive data
Default mapping: eUSCI_A2 UART transmit data
PM_UCA0RXD
PM_UCA0TXD
PM_UCA1RXD
PM_UCA1TXD
PM_UCA2RXD
PM_UCA2TXD
O
I
UART
O
I
O
(5) When this pin is configured as reset, the internal pullup resistor is enabled by default.
32
Terminal Configuration and Functions
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4.4 Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and schematics of the
multiplexed ports, see 节 6.12.
4.5 Buffer Type
Table 4-7 describes the buffer types that are referenced in Table 4-3 and Table 4-4.
Table 4-7. Buffer Type
NOMINAL
PU OR PD
STRENGTH
(µA)
OUTPUT
DRIVE
STRENGTH
(mA)
BUFFER TYPE
(STANDARD)
NOMINAL
VOLTAGE
OTHER
CHARACTERISTICS
HYSTERESIS
PU OR PD
See 节 5.8.4
Digital I/O Ports Digital I/O Ports
See 节 5.8.4
LVCMOS
3.0 V
Y
Programmable
See analog modules in
Section 5, Specifications,
for details.
Analog
Power
3.0 V
3.0 V
N
N/A
N/A
N/A
N/A
N/A
N/A
Y with SVS on
4.6 Connection of Unused Pins
Table 4-8 lists the correct termination of unused pins.
Table 4-8. Connection of Unused Pins(1)
PIN
POTENTIAL
COMMENT
AVCC
AVSS
DVCC
DVSS
Switched to port function, output direction (PxDIR.n = 1). Px.y represents port x and bit y
of port x (for example, P1.0, P1.1, P2.2, PJ.0, PJ.1)
Px.y
XIN
Open
DVSS
For dedicated XIN pins only. XIN pins with shared GPIO functions should be
programmed to GPIO and follow Px.y recommendations.
For dedicated XOUT pins only. XOUT pins with shared GPIO functions should be
programmed to GPIO and follow Px.y recommendations.
XOUT
Open
DVSS
LCDCAP
RST/NMI
DVCC or VCC
47-kΩ pullup or internal pullup selected with 10-nF (2.2-nF) pulldown(2)
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK
The JTAG pins are shared with general-purpose I/O function (PJ.x). If not being used,
these should be switched to port function, output direction (PJDIR.n = 1). When used as
JTAG pins, these pins should remain open.
Open
TEST
Open
This pin always has an internal pulldown enabled.
(1) Any unused pin with a secondary function that is shared with a general-purpose I/O must follow the Px.y unused pin connection
guidelines.
(2) The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG
mode with TI tools such as FET interfaces or GANG programmers.
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5 Specifications
All graphs in this section are for typical conditions, unless otherwise noted.
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Voltage applied at DVCC to DVSS
Voltage applied to pins(2)
–0.3
4.1
V
All pins except VCORE(3), SD24_B input pins (SDxN0, SDxP0)(4)
AUXVCC1, AUXVCC2, and AUXVCC3(5)
,
–0.3
VCC + 0.3
V
All pins except SD24_B input pins (SDxN0, SDxP0)
SD0N0, SD0P0, SD1N0, SD1P0, SD2N0, SD2P0(6)
±2
2
Diode current at pins
mA
Maximum junction temperature, TJ
95
°C
°C
(7)
Storage temperature, Tstg
–55
105
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS = VDVSS = VAVSS
.
(3) VCORE is for internal device use only. No external DC loading or voltage should be applied.
(4) See Table 5-35 for SD24_B specifications.
(5) See Table 5-18 for AUX specifications.
(6) A protection diode is connected to VCC for the SD24_B input pins. No protection diode is connected to VSS
.
(7) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD) Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3 Recommended Operating Conditions
MIN NOM
MAX UNIT
PMMCOREVx = 0
1.8
2.0
2.2
2.4
0
3.6
PMMCOREVx = 0, 1
PMMCOREVx = 0, 1, 2
PMMCOREVx = 0, 1, 2, 3
3.6
V
Supply voltage during program execution and flash
programming. V(AVCC) = V(DVCC) = VCC
VCC
(1) (2)
3.6
3.6
V
VSS
TA
Supply voltage V(AVSS) = V(DVSS) = VSS
Operating free-air temperature
I version
I version
–40
–40
470
85
85
°C
°C
nF
TJ
Operating junction temperature
Recommended capacitor at VCORE(3)
CVCORE
CDVCC
CVCORE
/
Capacitor ratio of DVCC to VCORE
10
(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between V(AVCC) and V(DVCC) can
be tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Table 5-14 threshold parameters for
the exact values and further details.
(3) A capacitor tolerance of ±20% or better is required.
34
Specifications
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Recommended Operating Conditions (continued)
MIN NOM
MAX UNIT
PMMCOREVx = 0,
1.8 V ≤ VCC ≤ 3.6 V
(default condition)
0
8.0
PMMCOREVx = 1,
2.0 V ≤ VCC ≤ 3.6 V
Processor frequency (maximum MCLK frequency)(4) (5)
(see Figure 5-1)
0
0
0
12.0
MHz
fSYSTEM
PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V
20.0
25.0
PMMCOREVx = 3,
2.4 V ≤ VCC ≤ 3.6 V
Maximum load current that can be drawn from DVCC for core and IO
(ILOAD = ICORE + IIO
ILOAD, DVCCD
ILOAD, AUX1D
ILOAD, AUX2D
ILOAD, AVCCA
ILOAD, AUX1A
ILOAD, AUX2A
20
20
20
10
5
mA
mA
mA
mA
mA
mA
)
Maximum load current that can be drawn from AUXVCC1 for core and IO
(ILOAD = ICORE + IIO
)
Maximum load current that can be drawn from AUXVCC2 for core and IO
(ILOAD = ICORE + IIO
)
Maximum load current that can be drawn from AVCC for analog modules
(ILOAD = IModules
)
Maximum load current that can be drawn from AUXVCC1 for analog modules
(ILOAD = IModules
)
Maximum load current that can be drawn from AUXVCC2 for analog modules
(ILOAD = IModules
5
)
(4) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(5) Modules may have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.
25
3
20
2, 3
2
12
8
1, 2
1, 2, 3
1
0
0, 1
0, 1, 2
0, 1, 2, 3
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
The numbers within the fields denote the supported PMMCOREVx settings.
Figure 5-1. Maximum System Frequency
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Specifications
35
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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
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5.4 Active Mode Supply Current Into VCC Excluding External Current
(2) (3)
over recommended operating free-air temperature (unless otherwise noted)(1)
FREQUENCY (fDCO = fMCLK = fSMCLK
8 MHz 12 MHz 20 MHz
TYP
)
EXECUTION
MEMORY
PARAMETER
VCC
PMMCOREVx
1 MHz
TYP
25 MHz
UNIT
MAX
MAX
TYP
MAX
TYP
MAX
TYP
8.65
4.70
MAX
9.54
5.30
0
1
2
3
0
1
2
3
0.32
0.36
0.39
0.42
0.20
0.22
0.24
0.26
0.36
2.10
2.39
2.65
2.82
1.10
1.30
1.45
1.55
2.30
3.54
3.94
4.20
3.90
(4)
IAM, Flash
Flash
3.0 V
mA
6.54
6.96
7.23
0.22
1.22
1.90
2.15
2.30
2.10
(5)
IAM, RAM
RAM
3.0 V
mA
3.55
3.80
4.0
(1) All inputs are tied to 0 or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Characterized with program executing typical data processing.
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.
(4) Active mode supply current when program executes in flash at a nominal supply voltage of 3 V.
(5) Active mode supply current when program executes in RAM at a nominal supply voltage of 3 V.
36
Specifications
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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
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5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(2)
TEMPERATURE (TA)
PARAMETER
VCC
PMMCOREVx
–40°C
TYP
25°C
TYP
60°C
TYP
85°C
UNIT
MAX
MAX
87
99
9
MAX
TYP
84
MAX
96
2.2 V
3.0 V
2.2 V
3.0 V
0
3
0
3
0
1
2
0
1
2
3
0
1
2
3
0
1
2
3
75
85
78
89
81
93
(4)
(4)
ILPM0,1MHz
Low-power mode 0(3)
Low-power mode 2(5)
µA
µA
98
110
17
5.9
6.9
1.4
1.5
1.7
2.2
2.3
2.5
2.5
1.4
1.5
1.6
1.6
1.3
1.4
1.4
1.4
0.65
1.16
0.70
6.2
7.4
1.7
1.9
2.0
2.5
2.7
2.9
2.9
1.7
1.8
1.9
1.9
1.6
1.6
1.7
1.7
0.80
1.24
0.78
6.9
8.4
2.5
2.7
2.9
3.3
3.5
3.7
3.7
2.4
2.5
2.7
2.7
2.3
2.4
2.5
2.5
0.90
1.43
0.90
9.4
11
ILPM2
10
19
4.9
5.2
5.5
5.5
5.8
6.1
6.1
4.5
4.7
4.9
5.0
4.4
4.5
4.8
4.8
1.30
1.87
1.20
Low-power mode 3, crystal
ILPM3,XT1LF
2.2 V
µA
µA
(4)
mode(6)
3.1
12.7
Low-power mode 3, crystal
ILPM3,XT1LF
3.0 V
(4)
mode(6)
3.5
2.2
14.0
11.5
Low-power mode 3,
ILPM3,VLO
3.0 V
3.0 V
µA
µA
VLO mode(7)
(4)
2.4
2.0
12.7
11.1
(4)
ILPM4
Low-power mode 4(8)
2.2
12.2
2.2 V
3.0 V
3.0 V
Low-power mode 3.5, RTC
active on AUXVCC3(9)
ILPM3.5
ILPM4.5
µA
µA
2.05
1.05
2.71
1.85
Low-power mode 4.5(10)
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
(4) Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML)
disabled. High-side monitor (SVMH) disabled. RAM retention enabled.
(5) Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. ACLK = low-frequency crystal operation (XTS = 0,
XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCO setting
= 1-MHz operation, DCO bias generator enabled.
(6) Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. ACLK = low-frequency crystal operation (XTS = 0,
XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
(7) Current for watchdog timer clocked by ACLK included. RTC is disabled (RTCHOLD=1). ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
(9) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC active on AUXVCC3 supply
(10) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 0 Hz, PMMREGOFF = 1
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MSP430F6720A
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5.6 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
(2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
TEMPERATURE (TA)
PARAMETER
VCC
PMMCOREVx
–40°C
TYP MAX
25°C
TYP
60°C
TYP
85°C
TYP
UNIT
MAX
MAX
MAX
Low-power mode 3
(LPM3) current, LCD 4-
mux mode, internal
biasing, charge pump
disabled(3) (4)
0
1
2.4
2.5
2.9
3.1
3.6
3.8
4.0
5.8
6.0
12.2
ILPM3
LCD,
int. bias
2.2 V
µA
2
2.6
3.3
3.9
3.9
4.2
6.3
13.4
13.3
0
1
2
3
0
1
2
0
1
2
3
2.8
2.9
3.1
3.1
3.2
3.4
3.6
3.6
3.8
3.9
4.0
4.0
4.1
4.2
4.2
4.1
4.3
4.5
4.5
6.4
6.7
7.0
7.0
Low-power mode 3
(LPM3) current, LCD 4-
mux mode, internal
biasing, charge pump
disabled(3) (4)
ILPM3
LCD,
int. bias
3.0 V
2.2 V
3.0 V
µA
µA
4.5
14.7
Low-power mode 3
(LPM3) current, LCD 4-
mux mode, internal
biasing, charge pump
enabled(3) (5)
ILPM3
LCD,CP
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. ACLK = low-frequency crystal operation (XTS = 0,
XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for brownout and high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML)
disabled. High-side monitor (SVMH) disabled. RAM retention enabled.
(4) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2, ... = 0 and odd segments S1, S3, ... = 1. No LCD panel load.
(5) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump
enabled), VLCDx = 1000 (VLCD = 3 V, typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2, ... = 0 and odd segments S1, S3, ... = 1. No LCD panel load.
38
Specifications
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MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
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5.7 Thermal Resistance Characteristics
THERMAL METRIC(1) (2)
VALUE
46.3
45.6
11.5
11.0
N/A(3)
N/A
UNIT
LQFP 80 (PN)
LQFP 100 (PZ)
LQFP 80 (PN)
LQFP 100 (PZ)
LQFP 80 (PN)
LQFP 100 (PZ)
LQFP 80 (PN)
LQFP 100 (PZ)
LQFP 80 (PN)
LQFP 100 (PZ)
LQFP 80 (PN)
LQFP 100 (PZ)
RθJA
Junction-to-ambient thermal resistance, still air
°C/W
RθJC(TOP)
RθJC(BOTTOM)
RθJB
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (bottom) thermal resistance
Junction-to-board thermal resistance
21.9
23.4
0.5
ΨJT
Junction-to-package-top thermal characterization parameter
Junction-to-board thermal characterization parameter
0.4
21.6
23.0
ΨJB
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(3) N/A = not applicable
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Specifications
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MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
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5.8 Timing and Switching Characteristics
5.8.1 Power Supply Sequencing
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up,
power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the
limits specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the
device including erroneous writes to RAM and flash.
5.8.2 Reset Timing
Table 5-1 lists the device wake-up times.
Table 5-1. Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
f
MCLK ≥ 4 MHz
3
5
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1
Wake-up time from LPM2, LPM3,
or LPM4 to active mode(1)
tWAKE-UP-FAST
µs
µs
1 MHz < fMCLK
4 MHz
<
4
6
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 0
Wake-up time from LPM2, LPM3,
or LPM4 to active mode(2)(3)
tWAKE-UP-SLOW
150
160
Wake-up time from LPM4.5 to
active mode(4)
tWAKE-UP-LPM4.5
tWAKE-UP-RESET
2
2
3
3
ms
ms
Wake-up time from RST or BOR
event to active mode(4)
(1) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in full performance
mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in
the Power Management Module and Supply Voltage Supervisor chapter of the MSP430x5xx and MSP430x6xx Family User's Guide.
(2) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in normal mode (low
current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in the
Power Management Module and Supply Voltage Supervisor chapter of the MSP430x5xx and MSP430x6xx Family User's Guide.
(3) The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by the
performance mode settings as for LPM2, LPM3, and LPM4.
(4) This value represents the time from the wake-up event to the reset vector execution.
40
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5.8.3 Clock Specifications
Table 5-2 lists the characteristics of the crystal oscillator in low-frequency mode.
Table 5-2. Crystal Oscillator, XT1, Low-Frequency Mode(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 1, TA = 25°C
0.075
Differential XT1 oscillator
crystal current consumption
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
ΔIDVCC.LF
3.0 V
0.170
0.290
32768
µA
from lowest drive setting, LF XT1DRIVEx = 2, TA = 25°C
mode
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 3, TA = 25°C
XT1 oscillator crystal
frequency, LF mode
fXT1,LF0
XTS = 0, XT1BYPASS = 0
Hz
XT1 oscillator logic-level
(3)
fXT1,LF,SW
square-wave input frequency, XTS = 0, XT1BYPASS = 1(2)
LF mode
10 32.768
50 kHz
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
210
300
Oscillation allowance for
LF crystals(4)
OALF
kΩ
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, XCAPx = 0(6)
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
XTS = 0, XCAPx = 3
1
5.5
Integrated effective load
capacitance, LF mode(5)
CL,eff
pF
8.5
12.0
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
Duty cycle, LF mode
30%
10
70%
Oscillator fault frequency,
LF mode(7)
fFault,LF
XTS = 0(8)
10000
Hz
ms
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 0, TA = 25°C, CL,eff = 6 pF
1000
500
tSTART,LF
Start-up time, LF mode
3.0 V
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 3, TA = 25°C, CL,eff = 12 pF
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
•
•
•
•
•
•
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-Trigger Inputs section of this data sheet.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
•
•
•
•
For XT1DRIVEx = 0, CL,eff ≤ 6 pF
For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF
For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF
For XT1DRIVEx = 3, CL,eff ≥ 6 pF
(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.
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Table 5-3 lists the characteristics of the VLO.
Table 5-3. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLO frequency
VLO frequency temperature drift
TEST CONDITIONS
VCC
MIN
TYP
9.4
0.5
4
MAX UNIT
15 kHz
%/°C
fVLO
Measured at ACLK
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
6
dfVLO/dT
Measured at ACLK(1)
Measured at ACLK(2)
Measured at ACLK
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
%/V
30%
70%
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Table 5-4 lists the characteristics of the REFO.
Table 5-4. Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
3
MAX UNIT
REFO oscillator current
consumption
IREFO
TA = 25°C
1.8 V to 3.6 V
µA
REFO frequency calibrated
Measured at ACLK
Full temperature range
TA = 25°C
1.8 V to 3.6 V
1.8 V to 3.6 V
3 V
32768
Hz
±3.5%
±1.5%
%/°C
fREFO
REFO absolute tolerance calibrated
REFO frequency temperature drift
dfREFO/dVCC REFO frequency supply voltage drift Measured at ACLK(2)
dfREFO/dT
Measured at ACLK(1)
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
0.01
1.0
%/V
Duty cycle
Measured at ACLK
40%/60% duty cycle
40%
50%
25
60%
tSTART
REFO start-up time
µs
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
42
Specifications
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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
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Table 5-5 lists the DCO frequencies.
Table 5-5. DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-2)
PARAMETER
TEST CONDITIONS
DCORSELx = 0, DCOx = 0, MODx = 0
DCORSELx = 0, DCOx = 31, MODx = 0
DCORSELx = 1, DCOx = 0, MODx = 0
DCORSELx = 1, DCOx = 31, MODx = 0
DCORSELx = 2, DCOx = 0, MODx = 0
DCORSELx = 2, DCOx = 31, MODx = 0
DCORSELx = 3, DCOx = 0, MODx = 0
DCORSELx = 3, DCOx = 31, MODx = 0
DCORSELx = 4, DCOx = 0, MODx = 0
DCORSELx = 4, DCOx = 31, MODx = 0
DCORSELx = 5, DCOx = 0, MODx = 0
DCORSELx = 5, DCOx = 31, MODx = 0
DCORSELx = 6, DCOx = 0, MODx = 0
DCORSELx = 6, DCOx = 31, MODx = 0
DCORSELx = 7, DCOx = 0, MODx = 0
DCORSELx = 7, DCOx = 31, MODx = 0
MIN
0.07
0.70
0.15
1.47
0.32
3.17
0.64
6.07
1.3
TYP
MAX UNIT
0.20 MHz
1.70 MHz
0.36 MHz
3.45 MHz
0.75 MHz
7.38 MHz
1.51 MHz
14.0 MHz
3.2 MHz
fDCO(0,0)
fDCO(0,31)
fDCO(1,0)
fDCO(1,31)
fDCO(2,0)
fDCO(2,31)
fDCO(3,0)
fDCO(3,31)
fDCO(4,0)
fDCO(4,31)
fDCO(5,0)
fDCO(5,31)
fDCO(6,0)
fDCO(6,31)
fDCO(7,0)
fDCO(7,31)
DCO frequency (0, 0)(1)
DCO frequency (0, 31)(1)
DCO frequency (1, 0)(1)
DCO frequency (1, 31)(1)
DCO frequency (2, 0)(1)
DCO frequency (2, 31)(1)
DCO frequency (3, 0)(1)
DCO frequency (3, 31)(1)
DCO frequency (4, 0)(1)
DCO frequency (4, 31)(1)
DCO frequency (5, 0)(1)
DCO frequency (5, 31)(1)
DCO frequency (6, 0)(1)
DCO frequency (6, 31)(1)
DCO frequency (7, 0)(1)
DCO frequency (7, 31)(1)
12.3
2.5
28.2 MHz
6.0 MHz
23.7
4.6
54.1 MHz
10.7 MHz
88.0 MHz
19.6 MHz
135 MHz
39.0
8.5
60
Frequency step between range
DCORSEL and DCORSEL + 1
SDCORSEL
SDCO
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
1.2
2.3 ratio
Frequency step between tap
DCO and DCO + 1
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
Measured at SMCLK
1.02
40%
1.12 ratio
Duty cycle
50%
0.1
60%
%/°C
%/V
dfDCO/dT
DCO frequency temperature drift fDCO = 1 MHz
DCO frequency voltage drift fDCO = 1 MHz
dfDCO/dVCORE
1.9
(1) When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the
range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31
(DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual
fDCOfrequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the
selected range is at its minimum or maximum tap setting.
100
VCC = 3.0 V
TA = 25°C
10
DCOx = 31
1
DCOx = 0
0.1
0
1
2
3
4
5
6
7
DCORSEL
Figure 5-2. Typical DCO Frequency
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Specifications
43
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5.8.4 Digital I/O Ports
Table 5-6 lists the characteristics of the GPIOs.
Table 5-6. Schmitt-Trigger Inputs, General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.8 V
3 V
MIN
0.80
1.50
0.45
0.75
0.3
TYP
MAX UNIT
1.40
V
VIT+
VIT–
Vhys
Positive-going input threshold voltage
2.10
1.8 V
3 V
1.00
V
Negative-going input threshold voltage
1.65
1.8 V
3 V
0.85
V
Input voltage hysteresis (VIT+ – VIT–
)
0.4
1.0
For pullup: VIN = VSS
For pulldown: VIN = VCC
RPull
CI
Pullup or pulldown resistor(1)
Input capacitance
20
35
5
50
kΩ
VIN = VSS or VCC
pF
(1) Also applies to RST pin when pullup or pulldown resistor is enabled.
Table 5-7 lists the characteristics of the P1 and P2 inputs.
Table 5-7. Inputs, Ports P1 and P2(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Port P1, P2: P1.x to P2.x, External trigger pulse duration
to set interrupt flag
t(int)
External interrupt timing(2)
2.2 V, 3 V
20
ns
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It might be set by trigger signals
shorter than t(int)
.
Table 5-8 lists the leakage currents of the GPIOs.
Table 5-8. Leakage Current, General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1) (2)
VCC
MIN
MAX UNIT
±50 nA
Ilkg(Px.y)
High-impedance leakage current
See
1.8 V, 3 V
(1) The leakage current is measured with VSSor VCC applied to the corresponding pins, unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
44
Specifications
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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
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Table 5-9 lists the output characteristics of the GPIOs in full drive strength mode. Also see Figure 5-3
through Figure 5-6.
Table 5-9. Outputs, General-Purpose I/O (Full Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA(1)
VCC
MIN
VCC – 0.25
VCC – 0.60
VCC – 0.25
VCC – 0.60
MAX UNIT
VCC
1.8 V
I(OHmax) = –10 mA(1)
I(OHmax) = –5 mA(1)
I(OHmax) = –15 mA(1)
I(OLmax) = 3 mA(2)
I(OLmax) = 10 mA(3)
I(OLmax) = 5 mA(2)
I(OLmax) = 15 mA(3)
VCC
VOH
High-level output voltage
V
VCC
3 V
1.8 V
3 V
VCC
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
VSS VSS + 0.60
VOL
Low-level output voltage
V
(1) The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified.
See Section 5.3 for more details.
(2) The maximum total current, I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified.
(3) The maximum total current, I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified.
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Specifications
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MSP430F6720A
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5.8.4.1 Typical Characteristics, General-Purpose I/O (Full Drive Strength)
0
0
-10
-20
-30
-40
-50
-60
-5
-10
-15
-20
-25
TA = 85°C
TA = 25°C
TA = 85°C
TA = 25°C
0.5
0
0.2
0.4
VOH – High-Level Output Voltage – V
Full Drive Strength
0.6
0.8
1
1.2
1.4
1.6
1.8
0
1
1.5
2
2.5
3
VOH – High-Level Output Voltage – V
VCC = 3 V Full Drive Strength
VCC = 1.8 V
Figure 5-3. High-Level Output Current vs High-Level Output
Voltage
Figure 5-4. High-Level Output Current vs High-Level Output
Voltage
25
60
50
20
TA = 25°C
TA = 25°C
TA = 85°C
TA = 85°C
40
15
30
20
10
0
10
5
0
0
0.2
0.4
VOL – Low-Level Output Voltage – V
Full Drive Strength
0.6
0.8
1
1.2
1.4
1.6
1.8
0
0.5
1
1.5
VOL – Low-Level Output Voltage – V
Full Drive Strength
2
2.5
3
VCC = 1.8 V
VCC = 3 V
Figure 5-5. Low-Level Output Current vs Low-Level Output
Voltage
Figure 5-6. Low-Level Output Current vs Low-Level Output
Voltage
46
Specifications
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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
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Table 5-10 lists the output characteristics of the GPIOs in reduced drive strength mode. Also see Figure 5-
7 through Figure 5-10.
Table 5-10. Outputs, General-Purpose I/O (Reduced Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA(2)
VCC
MIN
VCC – 0.25
VCC – 0.60
VCC – 0.25
VCC – 0.60
MAX UNIT
VCC
1.8 V
I(OHmax) = –3 mA(2)
I(OHmax) = –2 mA(2)
I(OHmax) = –6 mA(2)
I(OLmax) = 1 mA(3)
I(OLmax) = 3 mA(4)
I(OLmax) = 2 mA(3)
I(OLmax) = 6 mA(4)
VCC
VOH
High-level output voltage
V
VCC
3.0 V
1.8 V
3.0 V
VCC
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
VSS VSS + 0.60
VOL
Low-level output voltage
V
(1) Selecting reduced drive strength may reduce EMI.
(2) The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified.
See Section 5.3 for more details.
(3) The maximum total current, I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified.
(4) The maximum total current, I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage drop specified.
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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
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5.8.4.2 Typical Characteristics, General-Purpose I/O (Reduced Drive Strength)
0
-1
-2
-3
-4
-5
-6
-7
-8
0
-5
-10
-15
-20
-25
TA = 85°C
TA = 85°C
TA = 25°C
TA = 25°C
0.4
0
0.2
0.6
0.8
1
1.2
1.4
1.6
1.8
0
0.5
1
1.5
VOH – High-Level Output Voltage – V
Reduced Drive Strength
2
2.5
3
VOH – High-Level Output Voltage – V
VCC = 1.8 V Reduced Drive Strength
VCC = 3 V
Figure 5-7. High-Level Output Current vs High-Level Output
Voltage
Figure 5-8. High-Level Output Current vs High-Level Output
Voltage
8
7
20
18
TA = 25°C
16
TA = 25°C
6
TA = 85°C
14
TA = 85°C
5
12
10
8
4
3
2
1
0
6
4
2
0
0
0.2
0.4
VOL – Low-Level Output Voltage – V
Reduced Drive Strength
0.6
0.8
1
1.2
1.4
1.6
1.8
0
0.5
1
1.5
VOL – Low-Level Output Voltage – V
Reduced Drive Strength
2
2.5
3
VCC = 1.8 V
VCC = 3 V
Figure 5-9. Low-Level Output Current vs Low-Level Output
Voltage
Figure 5-10. Low-Level Output Current vs Low-Level Output
Voltage
48
Specifications
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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
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Table 5-11 lists the output frequencies of the GPIOs.
Table 5-11. Output Frequency, General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
VCC = 1.8 V,
PMMCOREVx = 0
16
fPx.y
Port output frequency (with load)
See(1) (2)
MHz
25
VCC = 3 V,
PMMCOREVx = 3
VCC = 1.8 V,
PMMCOREVx = 0
16
ACLK, SMCLK, MCLK,
CL = 20 pF(2)
fPort_CLK
Clock output frequency
MHz
25
VCC = 3 V,
PMMCOREVx = 3
(1) A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS
.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
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5.8.5 Power-Management Module (PMM)
Table 5-12 lists the characteristics of the BOR.
Table 5-12. PMM, Brownout Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
| dDVCC/dt | < 3 V/s
| dDVCC/dt | < 3 V/s
MIN
TYP
MAX UNIT
V(DVCC_BOR_IT–)
V(DVCC_BOR_IT+)
V(DVCC_BOR_hys)
BORH on voltage, DVCC falling level
BORH off voltage, DVCC rising level
BORH hysteresis
1.45
1.50
250
V
V
0.80
50
1.30
mV
Pulse duration required at RST/NMI pin to
accept a reset
(1)
tRESET
2
µs
(1) Pulse shorter than 2 µs might trigger reset.
Table 5-13 lists the characteristics of the PMM core voltage.
Table 5-13. PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
2.4 V ≤ DVCC ≤ 3.6 V
2.2 V ≤ DVCC ≤ 3.6 V
2.0 V ≤ DVCC ≤ 3.6 V
1.8 V ≤ DVCC ≤ 3.6 V
2.4 V ≤ DVCC ≤ 3.6 V
2.2 V ≤ DVCC ≤ 3.6 V
2.0 V ≤ DVCC ≤ 3.6 V
1.8 V ≤ DVCC ≤ 3.6 V
MIN
TYP
1.93
1.83
1.62
1.42
1.96
1.94
1.74
1.54
MAX UNIT
VCORE3(AM)
VCORE2(AM)
VCORE1(AM)
VCORE0(AM)
VCORE3(LPM)
VCORE2(LPM)
VCORE1(LPM)
VCORE0(LPM)
Core voltage, active mode, PMMCOREV = 3
Core voltage, active mode, PMMCOREV = 2
Core voltage, active mode, PMMCOREV = 1
Core voltage, active mode, PMMCOREV = 0
Core voltage, low-current mode, PMMCOREV = 3
Core voltage, low-current mode, PMMCOREV = 2
Core voltage, low-current mode, PMMCOREV = 1
Core voltage, low-current mode, PMMCOREV = 0
V
V
V
V
V
V
V
V
50
Specifications
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Table 5-14 lists the characteristics of the high-side SVS.
Table 5-14. PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SVSHE = 0, DVCC = 3.6 V
MIN
TYP
0
MAX UNIT
nA
I(SVSH)
SVS current consumption
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
SVSHE = 1, SVSHRVL = 0
200
1.5
µA
1.60
1.77
1.97
2.09
1.68
1.89
2.08
2.21
2.35
2.65
2.96
2.96
1.65
1.84
2.04
2.16
1.74
1.95
2.14
2.27
2.41
2.72
3.04
3.04
2.5
1.70
SVSHE = 1, SVSHRVL = 1
1.90
V
V(SVSH_IT–)
SVSH on voltage level(1)
SVSHE = 1, SVSHRVL = 2
2.10
SVSHE = 1, SVSHRVL = 3
2.23
1.80
2.01
2.21
SVSHE = 1, SVSMHRRL = 0
SVSHE = 1, SVSMHRRL = 1
SVSHE = 1, SVSMHRRL = 2
SVSHE = 1, SVSMHRRL = 3
2.34
V
V(SVSH_IT+)
SVSH off voltage level(1)
SVSHE = 1, SVSMHRRL = 4
2.49
SVSHE = 1, SVSMHRRL = 5
2.80
3.13
3.13
SVSHE = 1, SVSMHRRL = 6
SVSHE = 1, SVSMHRRL = 7
SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1
SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0
SVSHE = 0 → 1, SVSHFP = 1
SVSHE = 0 → 1, SVSHFP = 0
tpd(SVSH)
SVSH propagation delay
µs
µs
20
12.5
100
t(SVSH)
SVSH on or off delay time
DVCC rise time
dVDVCC/dt
0
1000
V/s
(1) The SVSH settings available depend on the VCORE (PMMCOREVx) setting. Please refer to the Power Management Module and Supply
Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide on recommended settings and use.
Table 5-15 lists the characteristics of the high-side SVM.
Table 5-15. PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SVMHE = 0, DVCC = 3.6 V
MIN
TYP
0
MAX UNIT
nA
I(SVMH)
SVMH current consumption
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
SVMHE = 1, SVSMHRRL = 0
200
1.5
µA
1.80
1.68
1.89
2.08
2.21
2.35
2.65
2.96
2.96
1.74
1.95
2.14
2.27
2.41
2.72
3.04
3.04
3.79
2.5
SVMHE = 1, SVSMHRRL = 1
2.01
SVMHE = 1, SVSMHRRL = 2
2.21
SVMHE = 1, SVSMHRRL = 3
2.34
V(SVMH)
SVMH on or off voltage level(1)
SVMHE = 1, SVSMHRRL = 4
2.49
2.80
3.13
3.13
V
SVMHE = 1, SVSMHRRL = 5
SVMHE = 1, SVSMHRRL = 6
SVMHE = 1, SVSMHRRL = 7
SVMHE = 1, SVMHOVPE = 1
SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1
SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0
SVMHE = 0 → 1, SVMHFP = 1
SVMHE = 0 → 1, SVMHFP = 0
tpd(SVMH) SVMH propagation delay
µs
µs
20
12.5
100
t(SVMH)
SVMH on or off delay time
(1) The SVMH settings available depend on the VCORE (PMMCOREVx) setting. Refer to the Power Management Module and Supply
Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide on recommended settings and use.
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Table 5-16 lists the characteristics of the low-side SVS.
Table 5-16. PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SVSLE = 0, PMMCOREV = 2
MIN
TYP
0
MAX UNIT
nA
µA
µs
I(SVSL)
SVSL current consumption
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
SVSLE = 0 → 1, SVSLFP = 1
200
1.5
2.5
20
tpd(SVSL)
SVSL propagation delay
SVSL on or off delay time
12.5
100
t(SVSL)
µs
SVSLE = 0 → 1, SVSLFP = 0
Table 5-17 lists the characteristics of the low-side SVM.
Table 5-17. PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SVMLE = 0, PMMCOREV = 2
MIN
TYP
0
MAX UNIT
nA
µA
µs
I(SVML)
SVML current consumption
SVMLE = 1, PMMCOREV = 2, SVMLFP = 0
SVMLE = 1, PMMCOREV = 2, SVMLFP = 1
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
SVMLE = 0 → 1, SVMLFP = 1
200
1.5
2.5
20
tpd(SVML) SVML propagation delay
12.5
100
t(SVML)
SVML on or off delay time
µs
SVMLE = 0 → 1, SVMLFP = 0
52
Specifications
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5.8.6 Auxiliary Supplies Module
Table 5-18 lists the recommended operating conditions of the auxiliary supplies.
Table 5-18. Auxiliary Supplies, Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM
1.8
MAX UNIT
VCC
Supply voltage for all supplies at pins DVCC, AVCC, AUX1, AUX2, AUX3
PMMCOREVx = 0
3.6
3.6
3.6
3.6
3.6
V
1.8
PMMCOREVx = 1
PMMCOREVx = 2
PMMCOREVx = 3
2.0
Digital system supply voltage range,
VDSYS = VCC – RON × ILOAD
VDSYS
V
2.2
2.4
VASYS
CVCC
CAUX1/2
CVSYS
CVCORE
CAUX3
Analog system supply voltage range, VASYS = VCC - RON × ILOAD
Refer to modules
V
,
Recommended capacitor at pins DVCC, AVCC, AUX1, AUX2
4.7
µF
Recommended capacitor at pins VDSYS and VASYS
Recommended capacitance at pin VCORE
Recommended capacitor at pin AUX3
4.7
0.47
0.47
µF
µF
µF
Table 5-19 lists the current consumption of AUX3.
Table 5-19. Auxiliary Supplies, AUX3 (Backup Subsystem) Currents
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA
MIN
MAX UNIT
25°C
85°C
25°C
85°C
0.83
µA
RTC and 32-kHz oscillator in
backup subsystem enabled
IAUX3,RTCon
AUX3 current with RTC enabled
3 V
0.95
110
nA
RTC and 32-kHz oscillator in
backup subsystem disabled
IAUX3,RTCoff
AUX3 current with RTC disabled
3 V
165
Table 5-20 lists the characteristics of the auxiliary supply monitor.
Table 5-20. Auxiliary Supplies, Auxiliary Supply Monitor
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
LOCKAUX = 0, AUXMRx = 0,
Average supply current for
monitoring circuitry drawn from
VDSYS (also see Figure 5-11)
AUX0MD = 0, AUX1MD = 0, AUX2MD = 1,
VDSYS = DVCC, VASYS = AVCC,
Current measured at VDSYS pin
ICC,Monitor
3 V
0.70
µA
LOCKAUX = 0, AUXMRx = 0,
AUX0MD = 0, AUX1MD = 0, AUX2MD = 1,
VDSYS = DVCC, VASYS = AVCC,
AUXVCC1 = 3 V,
Average current drawn from
monitored supply during
measurement cycle (also see
Figure 5-12)
IMeas,Monitor
0.11
µA
Current measured at AUXVCC1 pin
AUXLVLx = 0
AUXLVLx = 1
AUXLVLx = 2
AUXLVLx = 3
AUXLVLx = 4
AUXLVLx = 5
AUXLVLx = 6
AUXLVLx = 7
1.67
1.87
2.06
2.19
2.33
2.63
2.91
2.91
1.74
1.95
2.14
2.27
2.41
2.72
3.02
3.02
1.80
2.01
2.21
2.33
2.48
2.79
3.10
3.10
VMonitor
Auxiliary supply threshold level
V
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0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VDSYS Voltage – V
Figure 5-11. VDSYS Voltage vs ICC,Monitor
120
100
80
60
40
20
0
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
AUXVCC1 Voltage – V
Figure 5-12. AUXVCC1 Voltage vs IMeas,Monitor
Table 5-21 lists the AUX switch ON resistance characteristics.
Table 5-21. Auxiliary Supplies, Switch ON-Resistance
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
ON-resistance of switch between DVCC
and VDSYS
RON,DVCC
RON,DAUX1
RON,DAUX2
RON,AVCC
RON,AAUX1
RON,AAUX2
ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA
5
5
Ω
ON-resistance of switch between AUX1
and VDSYS
ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA
ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA
ILOAD = IModules = 10 mA
Ω
Ω
Ω
Ω
Ω
ON-resistance of switch between AUX2
and VDSYS
5
ON-resistance of switch between AVCC
and VASYS
5
ON-resistance of switch between AUX1
and VASYS
ILOAD = IModules = 5 mA
20
20
ON-resistance of switch between AUX2
and VASYS
ILOAD = IModules = 5 mA
54
Specifications
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Table 5-22 lists the switching times of the auxiliary supplies.
Table 5-22. Auxiliary Supplies, Switching Time
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
MAX
100
UNIT
ns
tSwitch
Time from occurrence of trigger (SVM or software) to "new" supply connected to system supplies
tRecover "Recovery time" after a switch over takes place; during this time, no further switching takes place
200
450
µs
Table 5-23 lists the leakage characteristics of the auxiliary supplies switch.
Table 5-23. Auxiliary Supplies, Switch Leakage
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Current into DVCC, AVCC, AUX1 or AUX2 if not
selected
ISW,Lkg
IVmax
Per supply (but not the highest supply)
50
100
730
nA
nA
Current drawn from highest supply
450
Table 5-24 lists the characteristics of the auxiliary supplies to the ADC.
Table 5-24. Auxiliary Supplies, Auxiliary Supplies to ADC10_A
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
0.58
0.98
1.18
TYP
0.60
1.00
1.20
MAX UNIT
1.8 V
3.0 V
3.6 V
0.62
Supply voltage divider
V3 = VSupply / 3
V3
1.02
1.22
18
V
AUXADCRx = 0
AUXADCRx = 1
AUXADCRx = 2
RV3
Load resistance
1.5
kΩ
ns
0.6
AUXADCRx = 0
AUXADCRx = 1
AUXADCRx = 2
1000
1000
1000
AUXADC = 1, ADC10ON = 1,
INCH = 0Ch,
Error of conversion result ≤ 1 LSB
Sampling time required if
V3 selected
tSample,V3
Table 5-25 lists the characteristics of the charge-limiting resistor.
Table 5-25. Auxiliary Supplies, Charge-Limiting Resistor
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
CHCx = 1
VCC
3 V
3 V
3 V
MIN
TYP
MAX UNIT
5
RCHARGE
Charge limiting resistor
CHCx = 2
CHCx = 3
10
20
kΩ
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5.8.7 Timer_A Module
Table 5-26 lists the characteristics of the Timer_A.
Table 5-26. Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
fTA
Timer_A input clock frequency
External: TACLK
1.8 V, 3 V
25 MHz
Duty cycle = 50% ± 10%
All capture inputs, Minimum pulse
duration required for capture
tTA,cap
Timer_A capture timing
1.8 V, 3 V
20
ns
5.8.8 eUSCI Module
Table 5-27 lists the supported clock frequencies of the eUSCI in UART mode.
Table 5-27. eUSCI (UART Mode) Clock Frequency
PARAMETER
eUSCI input clock frequency
fBITCLK BITCLK clock frequency (equals baud rate in MBaud)
TEST CONDITIONS
MIN
MAX UNIT
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
feUSCI
fSYSTEM
MHz
MHz
5
Table 5-28 lists the switching characteristics of the eUSCI in UART mode.
Table 5-28. eUSCI (UART Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UCGLITx = 0
VCC
MIN
10
TYP
15
MAX UNIT
25
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
30
50
85
ns
tt
UART receive deglitch time(1)
2 V, 3 V
50
80
150
70
120
200
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
56
Specifications
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Table 5-29 lists the supported clock frequencies of the eUSCI in SPI master mode.
Table 5-29. eUSCI (SPI Master Mode) Clock Frequency
PARAMETER
TEST CONDITIONS
Internal: SMCLK or ACLK,
Duty cycle = 50% ±10%
MIN
MAX UNIT
feUSCI
eUSCI input clock frequency
fSYSTEM
MHz
Table 5-30 lists the switching characteristics of the eUSCI in SPI master mode.
Table 5-30. eUSCI (SPI Master Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V
MIN
150
150
200
200
MAX UNIT
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
tSTE,LEAD
STE lead time, STE active to clock
ns
STE lag time, Last clock to STE
inactive
tSTE,LAG
ns
50
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
3 V
30
ns
50
STE access time, STE active to
SIMO data out
tSTE,ACC
2 V
3 V
30
40
2 V
3 V
25
ns
40
STE disable time, STE inactive to
SIMO high impedance
tSTE,DIS
2 V
3 V
25
2 V
50
30
0
tSU,MI
SOMI input data setup time
SOMI input data hold time
SIMO output data valid time(2)
SIMO output data hold time(3)
ns
3 V
2 V
tHD,MI
ns
3 V
0
2 V
9
tVALID,MO
UCLK edge to SIMO valid, CL = 20 pF
CL = 20 pF
ns
5
3 V
2 V
0
0
tHD,MO
ns
3 V
(1) fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)
)
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-13 and Figure 5-14.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-
13 and Figure 5-14.
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UCMODEx = 01
tSTE,LEAD
tSTE,LAG
STE
UCMODEx = 10
CKPL = 0
1/fUCxCLK
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
SIMO
tSTE,ACC
tVALID,MO
tSTE,DIS
Figure 5-13. BadDriveBacuSPI Master Mode, CKPH = 0
UCMODEx = 01
STE
UCMODEx = 10
tSTE,LEAD
tSTE,LAG
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
SIMO
tSTE,ACC
tVALID,MO
tSTE,DIS
Figure 5-14. SPI Master Mode, CKPH = 1
58
Specifications
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MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
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Table 5-31 lists the switching characteristics of the eUSCI in SPI slave mode.
Table 5-31. eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
4
MAX UNIT
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
tSTE,LEAD STE lead time, STE active to clock
ns
3
0
tSTE,LAG
tSTE,ACC
tSTE,DIS
tSU,SI
STE lag time, Last clock to STE inactive
ns
0
46
ns
24
STE access time, STE active to SOMI data out
38
ns
25
STE disable time, STE inactive to SOMI high
impedance
2
1
2
2
SIMO input data setup time
SIMO input data hold time
ns
ns
tHD,SI
55
ns
32
UCLK edge to SOMI valid,
CL = 20 pF
tVALID,SO SOMI output data valid time(2)
SOMI output data hold time(3)
24
16
tHD,SO
CL = 20 pF
ns
(1) fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)
)
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 5-13 and Figure 5-14.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in
Figure 5-15 and Figure 5-16.
UCMODEx = 01
tSTE,LEAD
tSTE,LAG
STE
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tSU,SIMO
tHD,SIMO
tLOW/HIGH
tLOW/HIGH
SIMO
tACC
tVALID,SOMI
tDIS
SOMI
Figure 5-15. SPI Slave Mode, CKPH = 0
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MSP430F6720A
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UCMODEx = 01
tSTE,LEAD
tSTE,LAG
STE
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tACC
tDIS
tVALID,SO
SOMI
Figure 5-16. SPI Slave Mode, CKPH = 1
60
Specifications
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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
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Table 5-32 lists the characteristics of the eUSCI in I2C mode.
Table 5-32. eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-17)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP
MAX UNIT
Internal: SMCLK, ACLK
External: UCLK
feUSCI
eUSCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ±10%
fSCL
SCL clock frequency
2 V, 3 V
2 V, 3 V
0
5.1
1.5
5.1
1.4
0.4
5.0
1.3
5.2
1.7
75
400 kHz
µs
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
tHD,STA
Hold time (repeated) START
tSU,STA
tHD,DAT
tSU,DAT
Setup time for a repeated START
Data hold time
2 V, 3 V
µs
µs
µs
2 V, 3 V
2 V, 3 V
2 V, 3 V
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
UCGLITx = 0
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
UCCLTOx = 1
UCCLTOx = 2
UCCLTOx = 3
Data setup time
tSU,STO
Setup time for STOP
2 V, 3 V
µs
220
35
120
ns
tSP
Pulse duration of spikes suppressed by input filter
2 V, 3 V
30
60
20
35
30
tTIMEOUT Clock low time-out
2 V, 3 V
33
ms
37
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
SCL
tLOW
tHIGH
tSP
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-17. I2C Mode Timing
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MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
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5.8.9 LCD Controller
Table 5-33 lists the operating conditions of the LCD.
Table 5-33. LCD_C Operating Conditions
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
Supply voltage range, charge
pump enabled, VLCD ≤ 3.6 V
LCDCPEN = 1, 0000 < VLCDx ≤ 1111
(charge pump enabled, VLCD ≤ 3.6 V)
VCC,LCD_C,CP en,3.6
VCC,LCD_C,CP en,3.3
VCC,LCD_C,int. bias
VCC,LCD_C,ext. bias
2.2
3.6
3.6
3.6
3.6
V
V
V
V
Supply voltage range, charge
pump enabled, VLCD ≤ 3.3 V
LCDCPEN = 1, 0000 < VLCDx ≤ 1100
(charge pump enabled, VLCD ≤ 3.3 V)
2.0
2.4
2.4
Supply voltage range, internal
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 0
LCDCPEN = 0, VLCDEXT = 0
Supply voltage range, external
biasing, charge pump disabled
Supply voltage range, external
LCD voltage, internal or external
biasing, charge pump disabled
VCC,LCD_C,VLCDEXT
LCDCPEN = 0, VLCDEXT = 1
2.0
2.4
3.6
3.6
V
V
External LCD voltage at
LCDCAP/R33, internal or external LCDCPEN = 0, VLCDEXT = 1
biasing, charge pump disabled
VLCDCAP/R33
Capacitor on LCDCAP when
charge pump enabled
LCDCPEN = 1, VLCDx > 0000
(charge pump enabled)
CLCDCAP
fLCD
fFRAME,4mux
fFRAME,8mux
4.7
10
1024
128
64
µF
Hz
Hz
Hz
fFRAME = 1/(2 × mux) × fLCD
with mux = 1 (static) to 8
LCD frequency range
0
fFRAME,4mux(MAX) = 1/(2 × 4) ×
fLCD(MAX) = 1/(2 × 4) × 1024 Hz
LCD frame frequency range
LCD frame frequency range
fFRAME,8mux(MAX) = 1/(2 × 4) ×
fLCD(MAX) = 1/(2 × 8) × 1024 Hz
fACLK,in
CPanel
ACLK input frequency range
Panel capacitance
30
32
40 kHz
100-Hz frame frequency
10000
VCC
pF
+
VR33
Analog input voltage at R33
LCDCPEN = 0, VLCDEXT = 1
2.4
V
0.2
VR03 + 2/3 ×
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR23,1/3bias
Analog input voltage at R23
VR13
(VR33
–
VR33
V
V
V
VR03
)
VR03 + 1/3 ×
(VR33
VR03
Analog input voltage at R13 with
1/3 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR13,1/3bias
VR03
–
)
VR23
VR03 + 1/2 ×
(VR33
VR03
Analog input voltage at R13 with
1/2 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 1
VR13,1/2bias
VR03
–
VR33
)
VR03
Analog input voltage at R03
R0EXT = 1
VSS
2.4
V
V
Voltage difference between VLCD
and R03
VCC
0.2
+
VLCD-VR03
LCDCPEN = 0, R0EXT = 1
External LCD reference voltage
applied at LCDREF/R13
VLCDREF/R13
VLCDREFx = 01
0.8
1.2
1.5
V
62
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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
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Table 5-34 lists the characteristics of the LCD.
Table 5-34. LCD_C Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
VCC
MAX UNIT
VLCDx = 0000, VLCDEXT = 0
LCDCPEN = 1, VLCDx = 0001
LCDCPEN = 1, VLCDx = 0010
LCDCPEN = 1, VLCDx = 0011
LCDCPEN = 1, VLCDx = 0100
LCDCPEN = 1, VLCDx = 0101
LCDCPEN = 1, VLCDx = 0110
LCDCPEN = 1, VLCDx = 0111
LCDCPEN = 1, VLCDx = 1000
LCDCPEN = 1, VLCDx = 1001
LCDCPEN = 1, VLCDx = 1010
LCDCPEN = 1, VLCDx = 1011
LCDCPEN = 1, VLCDx = 1100
LCDCPEN = 1, VLCDx = 1101
LCDCPEN = 1, VLCDx = 1110
LCDCPEN = 1, VLCDx = 1111
2.4 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2.2 V to 3.6 V
2.2 V to 3.6 V
2.2 V to 3.6 V
2.2 V
2.58
2.64
2.71
2.78
2.83
2.90
2.96
3.02
3.07
3.14
3.21
3.27
3.32
3.38
3.44
VLCD
LCD voltage
V
3.6
µA
Peak supply currents due to
charge pump activities
ICC,Peak,CP
tLCD,CP,on
ICP,Load
LCDCPEN = 1, VLCDx = 1111
400
150
Time to charge CLCD when
discharged
CLCD = 4.7µF, LCDCPEN = 0→1,
VLCDx = 1111
2.2 V
2.2 V
2.2 V
2.2 V
500
ms
µA
kΩ
kΩ
Maximum charge pump load
current
LCDCPEN = 1, VLCDx = 1111
50
LCD driver output impedance,
segment lines
LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA
RLCD,Seg
RLCD,COM
10
10
LCD driver output impedance,
common lines
LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA
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MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
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5.8.10 SD24_B Module
Table 5-35 lists the power supply and recommended operating conditions of the SD24_B.
Table 5-35. SD24_B Power Supply and Recommended Operating Conditions
MIN
2.4
TYP
MAX UNIT
3.6
2.3 MHz
AVCC Analog supply voltage
AVCC = DVCC, AVSS = DVSS = 0 V
V
fSD
VI
Modulator clock frequency(1)
Absolute input voltage range
Common-mode input voltage range
0.03
AVSS – 1
AVSS – 1
–VREF/GAIN
±910
AVCC
V
V
VIC
AVCC
VID,FS Differential full-scale input voltage
VID = VI,A+ – VI,A–
SD24GAINx = 1
SD24GAINx = 2
SD24GAINx = 4
+VREF/GAIN
±920
±460
±230
±115
±58
±455
±227
SD24GAINx = 8
SD24REFS = 1
±113
mV
nF
Differential input voltage for specified
VID
performance(2)
SD24GAINx = 16
±57
SD24GAINx = 32
SD24GAINx = 64
±28
±29
±14 ±14.5
SD24GAINx = 128
±7
±7.2
100
CREF
VREF load capacitance(3)
SD24REFS = 1
(1) Modulator clock frequency: MIN = 32.768 kHz – 10% ≈ 30 kHz. MAX = 32.768 kHz × 64 + 10% ≈ 2.3 MHz
(2) The full-scale range (FSR) is defined by VFS+ = +VREF/GAIN and VFS– = –VREF/GAIN: FSR = VFS+ – VFS– = 2 × VREF / GAIN. If VREF is
sourced externally, the analog input range should not exceed 80% of VFS+ or VFS–; that is, VID = 0.8 VFS– to 0.8 VFS+. If VREF is sourced
internally, the given VID ranges apply.
(3) There is no capacitance required on VREF. However, a capacitance of 100 nF is recommended to reduce any reference voltage noise.
Table 5-36 lists the analog input characteristics of the SD24_B.
(1)
Table 5-36. SD24_B Analog Input
PARAMETER
TEST CONDITIONS
SD24GAINx = 1
VCC
MIN
TYP
5
MAX UNIT
SD24GAINx = 2
5
SD24GAINx = 4
5
CI
Input capacitance
pF
SD24GAINx = 8
5
SD24GAINx = 16
SD24GAINx = 32, 64, 128
5
5
SD24GAINx = 1
SD24GAINx = 8
SD24GAINx = 32
SD24GAINx = 1
SD24GAINx = 8
SD24GAINx = 32
3 V
3 V
3 V
3 V
3 V
3 V
200
200
200
400
400
400
Input impedance
(Pin A+ or A- to AVSS
ZI
fSD24 = 1 MHz
fSD24 = 1 MHz
kΩ
kΩ
)
300
300
Differential input impedance
(Pin A+ to pin A-)
ZID
(1) All parameters pertain to each SD24_B converter.
64
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MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
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1600
1400
1200
1000
800
600
400
200
0
-200
-1
-0.5
0
0.5
1
1.5
2
2.5
3
Input Voltage – V
Figure 5-18. Input Leakage Current vs Input Voltage
(Modulator OFF)
Table 5-37 lists the supply current of the SD24_B.
Table 5-37. SD24_B Supply Currents
PARAMETER
TEST CONDITIONS
SD24GAIN: 1
VCC
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
MIN
TYP
600
600
600
700
700
775
775
775
750
825
900
MAX UNIT
675
675
675
SD24GAIN: 2
SD24GAIN: 4
SD24GAIN: 8
SD24GAIN: 16
SD24GAIN: 32
SD24GAIN: 64
SD24GAIN: 128
SD24GAIN: 1
SD24GAIN: 8
SD24GAIN: 32
750
µA
Analog plus digital supply current per
converter (reference not included)
fSD24 = 1 MHz,
SD24OSR = 256
ISD,256
750
850
850
850
800
Analog plus digital supply current per
converter (reference not included)
fSD24 = 2 MHz,
SD24OSR = 512
ISD,512
900
µA
1000
Table 5-38 lists the performance characteristics of the SD24_B.
Table 5-38. SD24_B Performance
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER
TEST CONDITIONS
VCC
MIN
–0.01
–0.01
–0.01
TYP
MAX UNIT
SD24GAIN: 1
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
0.01
Integral nonlinearity, end-
point fit
% of
FSR
INL
SD24GAIN: 8
SD24GAIN: 32
SD24GAIN: 1
SD24GAIN: 2
SD24GAIN: 4
SD24GAIN: 8
SD24GAIN: 16
SD24GAIN: 32
SD24GAIN: 64
0.01
0.01
1
2
4
8
Gnom
Nominal gain
16
31.7
63.4
SD24GAIN: 128
126.8
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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
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Table 5-38. SD24_B Performance (continued)
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER
TEST CONDITIONS
VCC
3 V
3 V
3 V
MIN
–1%
–2%
–2%
TYP
MAX UNIT
+1%
SD24GAIN: 1, with external reference (1.2 V)
SD24GAIN: 8, with external reference (1.2 V)
SD24GAIN: 32, with external reference (1.2 V)
EG
Gain error(1)
+2%
+2%
Gain error temperature
coefficient(2), internal
reference
ppm/
ΔEG/ΔT
ΔEG/ΔVCC
SD24GAIN: 1, 8, or 32 (with internal reference)
3 V
50
°C
SD24GAIN: 1
0.15
0.15
0.4
(3)
Gain error vs VCC
SD24GAIN: 8
%/V
SD24GAIN: 32
SD24GAIN: 1 (with Vdiff = 0 V)
SD24GAIN: 8
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
2.3
EOS[V]
Offset error(4)
Offset error(4)
0.73
0.18
0.2
mV
SD24GAIN: 32
SD24GAIN: 1 (with Vdiff = 0 V)
SD24GAIN: 8
–0.2
–0.5
–0.5
EOS[FS]
0.5 % FS
0.5
SD24GAIN: 32
SD24GAIN: 1
1
0.15
0.1
Offset error temperature
coefficient(5)
ΔEOS/ΔT
ΔEOS/ΔVCC
CMRR,DC
SD24GAIN: 8
µV/°C
µV/V
dB
SD24GAIN: 32
SD24GAIN: 1
600
(6)
Offset error vs VCC
SD24GAIN: 8
100
SD24GAIN: 32
SD24GAIN: 1
50
3 V
3 V
3 V
–110
–110
–110
Common-mode rejection at
DC(7)
SD24GAIN: 8
SD24GAIN: 32
(1) The gain error EG specifies the deviation of the actual gain Gact from the nominal gain Gnom: EG = (Gact – Gnom)/Gnom. It covers process,
temperature and supply voltage variations.
(2) The gain error temperature coefficient ΔEG / ΔT specifies the variation of the gain error EG over temperature (EG(T) = (Gact(T) –
Gnom)/Gnom) using the box method (that is, MIN and MAX values):
ΔEG/ ΔT = (MAX(EG(T)) – MIN(EG(T) ) / (MAX(T) – MIN(T)) = (MAX(Gact(T)) – MIN(Gact(T)) / Gnom / (MAX(T) – MIN(T))
with T ranging from –40°C to +85°C.
(3) The gain error vs VCC coefficient ΔEG/ ΔVCC specifies the variation of the gain error EG over supply voltage (EG(VCC) = (Gact(VCC) –
Gnom)/Gnom) using the box method (that is, MIN and MAX values):
ΔEG/ ΔVCC = (MAX(EG(VCC)) – MIN(EG(VCC) ) / (MAX(VCC) – MIN(VCC)) = (MAX(Gact(VCC)) – MIN(Gact(VCC)) / Gnom / (MAX(VCC) –
MIN(VCC))
with VCC ranging from 2.4 V to 3.6 V.
(4) The offset error EOS is measured with shorted inputs in 2s-complement mode with +100% FS = VREF / G and –100% FS = –VREF / G.
Conversion between EOS [FS] and EOS [V] is as follows: EOS [FS] = EOS [V]×G/VREF; EOS [V] = EOS [FS]×VREF/G.
(5) The offset error temperature coefficient ΔEOS / ΔT specifies the variation of the offset error EOS over temperature using the box method
(that is, MIN and MAX values):
ΔEOS / ΔT = (MAX(EOS(T)) – MIN(EOS(T) ) / (MAX(T) – MIN(T))
with T ranging from –40°C to +85°C.
(6) The offset error vs VCC ΔEOS / ΔVCC specifies the variation of the offset error EOS over supply voltage using the box method (that is,
MIN and MAX values):
ΔEOS / ΔVCC = (MAX(EOS(VCC)) – MIN(EOS(VCC) ) / (MAX(VCC) – MIN(VCC))
with VCC ranging from 2.4 V to 3.6 V.
(7) The DC CMRR specifies the change in the measured differential input voltage value when the common-mode voltage varies:
DC CMRR = –20log(ΔMAX/FSR) with ΔMAX being the difference between the minium value and the maximum value measured when
sweeping the common-mode voltage (for example, calculating with 16-bit FSR = 65536, a maximum change by 1 LSB results in
–20log(1/65536) ≈ –96 dB) .
The DC CMRR is measured with both inputs connected to the common-mode voltage (that is, no differential input signal is applied), and
the common-mode voltage is swept from –1 V to VCC
.
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Table 5-38. SD24_B Performance (continued)
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER
TEST CONDITIONS
VCC
3 V
3 V
3 V
MIN
TYP
–110
–110
–110
MAX UNIT
SD24GAIN: 1, fCM = 50 Hz, VCM = 930 mV
SD24GAIN: 8, fCM = 50 Hz, VCM = 120 mV
SD24GAIN: 32, fCM = 50 Hz, VCM = 30 mV
Common-mode rejection at
50 Hz(8)
CMRR,50Hz
dB
SD24GAIN: 1,
VCC = 3 V + 50 mV × sin(2π × fVcc × t),
fVcc = 50 Hz
–61
–77
–79
–61
–77
–79
SD24GAIN: 8,
VCC = 3 V + 50 mV × sin(2π × fVcc × t),
fVcc = 50 Hz
AC power supply rejection
ratio, external reference(9)
AC PSRR,ext
dB
SD24GAIN: 32,
VCC = 3 V + 50 mV × sin(2π × fVcc × t),
fVcc = 50 Hz
SD24GAIN: 1,
VCC = 3 V + 50 mV × sin(2π × fVcc × t),
fVcc = 50 Hz
SD24GAIN: 8,
VCC = 3 V + 50 mV × sin(2π × fVcc × t),
fVcc = 50 Hz
AC power supply rejection
ratio, internal reference(9)
AC PSRR,int
dB
SD24GAIN: 32,
VCC = 3 V + 50 mV × sin(2π × fVcc × t),
fVcc = 50 Hz
Crosstalk source: SD24GAIN: 1,
Sine wave with maximum possible Vpp,
fIN = 50 Hz or 100 Hz,
3 V
3 V
3 V
–120
–115
–100
Converter under test: SD24GAIN: 1
Crosstalk source: SD24GAIN: 1,
Sine wave with maximum possible Vpp,
fIN = 50 Hz or 100 Hz,
Crosstalk between
converters(10)
XT
dB
Converter under test: SD24GAIN: 8
Crosstalk source: SD24GAIN: 1,
Sine wave with maximum possible Vpp,
fIN = 50 Hz or 100 Hz,
Converter under test: SD24GAIN: 32
(8) The AC CMRR is the difference between a hypothetical signal with the amplitude and frequency of the applied common-mode ripple
applied to the inputs of the ADC and the actual common-mode signal spur visible in the FFT spectrum:
AC CMRR = Error Spur [dBFS] – 20log(VCM / 1.2 V / G) [dBFS] with a common-mode signal of VCM × sin(2π × fCM × t) applied to the
analog inputs.
The AC CMRR is measured with the both inputs connected to the common-mode signal (that is, no differential input signal is applied).
With the specified typical values the error spur is within the noise floor (as specified by the SINAD values).
(9) The AC PSRR is the difference between a hypothetical signal with the amplitude and frequency of the applied supply voltage ripple
applied to the inputs of the ADC and the actual supply ripple spur visible in the FFT spectrum:
AC PSRR = Error Spur [dBFS] – 20log(50 mV / 1.2 V / G) [dBFS] with a signal of 50 mV × sin(2π × fVcc × t) added to VCC
The AC PSRR is measured with the inputs grounded (that is, no analog input signal is applied).
With the specified typical values the error spur is within the noise floor (as specified by the SINAD values).
SD24GAIN: 1 → Hypothetical signal: 20log(50 mV / 1.2 V / 1) = –27.6 dBFS
.
SD24GAIN: 8 → Hypothetical signal: 20log(50 mV / 1.2 V / 8) = –9.5 dBFS
SD24GAIN: 32 → Hypothetical signal: 20log(50 mV / 1.2 V / 32) = 2.5 dBFS
(10) The crosstalk (XT) is specified as the tone level of the signal applied to the crosstalk source seen in the spectrum of the converter under
test. It is measured with the inputs of the converter under test being grounded.
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Table 5-39 lists the AC performance characteristics of the SD24_B.
Table 5-39. SD24_B AC Performance
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER
TEST CONDITIONS
SD24GAIN: 1
VCC
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
MIN
TYP
87
MAX UNIT
85
SD24GAIN: 2
SD24GAIN: 4
SD24GAIN: 8
SD24GAIN: 16
SD24GAIN: 32
SD24GAIN: 64
SD24GAIN: 128
SD24GAIN: 1
SD24GAIN: 8
SD24GAIN: 32
86
85
82
73
84
SINAD Signal-to-noise + distortion ratio
fIN = 50 Hz(1)
dB
80
74
68
62
100
90
THD
Total harmonic distortion
fIN = 50 Hz(1)
dB
80
(1) The following voltages were applied to the SD24_B inputs:
VI,A+(t) = 0 V + VPP / 2 × sin(2π × fIN × t)
VI,A-(t) = 0 V – VPP / 2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VI,A+(t) – VI,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24_B recommended operating conditions).
Table 5-40 lists the AC performance characteristics of the SD24_B.
Table 5-40. SD24_B AC Performance
fSD24 = 2 MHz, SD24OSRx = 512, SD24REFS = 1
PARAMETER
TEST CONDITIONS
SD24GAIN: 1
VCC
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
MIN
TYP
87
86
85
84
81
76
71
65
MAX UNIT
SD24GAIN: 2
SD24GAIN: 4
SD24GAIN: 8
SD24GAIN: 16
SD24GAIN: 32
SD24GAIN: 64
SD24GAIN: 128
SINAD Signal-to-noise + distortion ratio
fIN = 50 Hz(1)
dB
(1) The following voltages were applied to the SD24_B inputs:
VI,A+(t) = 0 V + VPP / 2 × sin(2π × fIN × t)
VI,A-(t) = 0 V – VPP / 2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VI,A+(t) – VI,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24_B recommended operating conditions).
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Table 5-41 lists the AC performance characteristics of the SD24_B.
Table 5-41. SD24_B AC Performance
fSD24 = 32 kHz, SD24OSRx = 512, SD24REFS = 1
PARAMETER
TEST CONDITIONS
VCC
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
MIN
TYP
89
85
84
86
80
76
67
61
MAX UNIT
SD24GAIN: 1
SD24GAIN: 2
SD24GAIN: 4
SD24GAIN: 8
SD24GAIN: 16
SD24GAIN: 32
SD24GAIN: 64
SD24GAIN: 128
SINAD Signal-to-noise + distortion ratio
fIN = 12 Hz(1)
dB
(1) The following voltages were applied to the SD24_B inputs:
VI,A+(t) = 0 V + VPP / 2 × sin(2π × fIN × t)
VI,A-(t) = 0 V – VPP / 2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VI,A+(t) – VI,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24_B recommended operating conditions).
95
90
85
80
75
70
65
60
55
32
64
128
256
512
1024
SD24OSRx
Figure 5-19. SINAD vs OSR
(fSD24 = 1 MHz, SD24REFS = 1, SD24GAIN = 1)
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90
85
80
75
70
65
60
0.1
0.2
0.3
0.4
0.5
Vpp/Vref/Gain
0.6
0.7
0.8
0.9
1
Figure 5-20. SINAD vs VPP
Table 5-42 lists the external reference input requirements of the SD24_B.
Table 5-42. SD24_B External Reference Input
ensure correct input voltage range according to VREF
PARAMETER
Input voltage
TEST CONDITIONS
SD24REFS = 0
SD24REFS = 0
VCC
3 V
3 V
MIN
TYP
1.20
MAX UNIT
VREF(I)
IREF(I)
1.0
1.5
50
V
Input current
nA
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5.8.11 ADC10_A Module
Table 5-43 lists the input requirements of the ADC.
Table 5-43. 10-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
1.8
0
TYP
MAX UNIT
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
AVCC
V(Ax)
Analog supply voltage
3.6
V
V
Analog input voltage range(1) All ADC10_A pins
AVCC
105
Operating supply current into fADC10CLK = 5 MHz, ADC10ON =1, REFON = 0,
AVCC terminal, REF module SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
and reference buffer off
2.2 V
3 V
70
80
115
ADC10SREF = 00
Operating supply current into fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 1,
AVCC terminal, REF module SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
3 V
3 V
130
108
74
185
on, reference buffer on
ADC10SREF = 01
IADC10_A
µA
Operating supply current into fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
AVCC terminal, REF module SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
160
105
off, reference buffer on
ADC10SREF = 10, VEREF = 2.5 V
Operating supply current into fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
AVCC terminal, REF module SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
3 V
off, reference buffer off
ADC10SREF = 11, VEREF = 2.5 V
Only one terminal Ax can be selected at one time
from the pad to the ADC10_A capacitor array
including wiring and pad.
CI
RI
Input capacitance
2.2 V
3.5
pF
AVCC > 2 V, 0 V ≤ VAx ≤ AVCC
36
96
Input MUX ON resistance
kΩ
1.8 V < AVCC < 2 V, 0 V ≤ VAx ≤ AVCC
(1) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The external
reference voltage requires decoupling capacitors. Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to
decouple the dynamic current required for an external reference source if it is used for the ADC10_A. Also see the MSP430x5xx and
MSP430x6xx Family User's Guide.
Table 5-44 lists the timing parameters of the ADC.
Table 5-44. 10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
For specified performance of ADC10_A
linearity parameters
fADC10CLK
fADC10OSC
2.2 V, 3 V
0.45
5
5.5 MHz
Internal ADC10_A
oscillator(1)
ADC10DIV = 0, fADC10CLK = fADC10OSC
2.2 V, 3 V
2.2 V, 3 V
4.4
2.4
5.0
5.6 MHz
REFON = 0, Internal oscillator, 12
ADC10CLK cycles, 10-bit mode
fADC10OSC = 4 MHz to 5 MHz
3.0
µs
tCONVERT
Conversion time
External fADC10CLK from ACLK, MCLK or
12 ×
SMCLK, ADC10SSEL ≠ 0
1 / fADC10CLK
Turnon settling time of
the ADC
(2)
tADC10ON
tSample
See
100
ns
µs
RS = 1000 Ω, RI = 96 kΩ, CI = 3.5 pF(3)
RS = 1000 Ω, RI = 36 kΩ, CI = 3.5 pF(3)
1.8 V
3 V
3
1
Sampling time
(1) The ADC10OSC is sourced directly from MODOSC inside the UCS.
(2) The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
(3) Approximately 8 Tau (t) are needed to get an error of less than ±0.5 LSB
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Table 5-45 lists the linearity parameters of the ADC.
Table 5-45. 10-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
1.4 V ≤ (VeREF+ – VeREF–) ≤ 1.6 V, CVeREF+ = 20 pF
1.6 V < (VeREF+ – VeREF–) ≤ VAVCC, CVeREF+ = 20 pF
±1.0
LSB
±1.0
Integral
linearity error
EI
2.2 V, 3 V
Differential
linearity error
ED
EO
EG
ET
1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
±1.0 LSB
±1.0 LSB
±1.0 LSB
±2.0 LSB
1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF
Internal impedance of source RS < 100 Ω
Offset error
Gain error
1.4 V ≤ (VeREF+ – VeREF–),
CVeREF+ = 20 pF, ADC10SREFx = 11b
Total unadjusted
error
1.4 V ≤ (VeREF+ – VeREF–),
CVeREF+ = 20 pF, ADC10SREFx = 11b
±1.0
Table 5-46 lists the characteristics of the external reference for the ADC.
Table 5-46. 10-Bit ADC, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Positive external reference
voltage input
(2)
VeREF+
VeREF+ > VeREF–
1.4
AVCC
1.2
V
V
V
Negative external
reference voltage input
(3)
(4)
VeREF–
VeREF+ > VeREF–
VeREF+ > VeREF–
0
(VeREF+
–
Differential external
reference voltage input
1.4
AVCC
VeREF–
)
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHz, ADC10SHTx = 0x0001,
Conversion rate 200 ksps
2.2 V, 3 V
2.2 V, 3 V
±8.5
±26
±1
µA
IVeREF+
IVeREF–
,
Static input current
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHz, ADC10SHTX = 0x1000,
Conversion rate 20 ksps
µA
µF
Capacitance at VeREF+
or VeREF- terminal
(5)
CVeREF+/-
See
10
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VeREF to decouple the dynamic current required for an external
reference source if it is used for the ADC10_A. Also see the MSP430x5xx and MSP430x6xx Family User's Guide .
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5.8.12 REF Module
Table 5-47 lists the characteristics of the built-in reference.
Table 5-47. REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
REFVSEL = {2} for 2.5 V, REFON = 1
REFVSEL = {1} for 2.0 V, REFON = 1
REFVSEL = {0} for 1.5 V, REFON = 1
REFVSEL = {0} for 1.5 V
VCC
3 V
MIN
2.47
1.95
1.46
1.8
TYP
2.51
1.99
1.50
MAX UNIT
2.55
Positive built-in reference
voltage
VREF+
3 V
2.03
1.54
V
V
2.2 V, 3 V
AVCC minimum voltage,
Positive built-in reference
active
AVCC(min)
REFVSEL = {1} for 2.0 V
2.2
REFVSEL = {2} for 2.5 V
2.7
fADC10CLK = 5 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {2} for 2.5 V
23
21
30
27
fADC10CLK = 5 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {1} for 2.0 V
Operating supply current
into AVCC terminal(1)
IREF+
3 V
µA
fADC10CLK = 5 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {0} for 1.5 V
19
10
25
50
Temperature coefficient of
built-in reference(2)
ppm/
°C
TCREF+
ISENSOR
REFVSEL = {0, 1, 2}, REFON = 1
2.2 V
3 V
145
170
780
780
1.1
220
245
Operating supply current
into AVCC terminal
REFON = 1, ADC10ON = 1,
INCH = 0Ah, TA = 30°C
µA
mV
V
2.2 V
3 V
REFON = 1, ADC10ON = 1,
INCH = 0Ah, TA = 30°C
(3)
VSENSOR
See
2.2 V
3 V
1.08
1.48
1.12
1.52
ADC10ON = 1, INCH = 0Bh,
VMID
tSENSOR(sample)
tVMID(sample)
AVCC divider at channel 11
VMID ≈ 0.5 × VAVCC
1.5
Sample time required if
channel 10 is selected(4)
REFON = 1, ADC10ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
30
1
µs
µs
Sample time required if
channel 11 is selected(5)
ADC10ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
AVCC = AVCC(min) to AVCC(max),
TA = 25°C,
REFVSEL = {0, 1, 2}, REFON = 1
Power supply rejection ratio
(DC)
PSRR_DC
PSRR_AC
120
300 µV/V
AVCC = AVCC(min) to AVCC(max),
TA = 25°C, f = 1 kHz, ΔVpp = 100 mV,
REFVSEL = {0, 1, 2}, REFON = 1
Power supply rejection ratio
(AC)
1
mV/V
µs
Settling time of reference
voltage(6)
AVCC = AVCC(min) to AVCC(max),
REFVSEL = {0, 1, 2}, REFON = 0 → 1
tSETTLE
VSD24REF
tON
75
SD24_B internal reference
voltage
SD24REFS = 1
3 V
3 V
1.137 1.151 1.165
200
V
SD24_B internal reference
turnon time(7)
SD24REFS = 0→1, CREF = 100 nF
µs
(1) The internal reference current is supplied by terminal AVCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
(2) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
(3) The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
(4) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
(5) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
(6) The condition is that the error in a conversion started after tREFON is ≤ 1 LSB.
.
(7) The condition is that SD24_B conversion started after tON should ensure specified SINAD values for the selected Gain, OSR, and fSD24
.
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Specifications
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5.8.13 Flash
Table 5-48 lists the characteristics of the flash memory.
Table 5-48. Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TJ
MIN
TYP
MAX UNIT
DVCC(PGM/ERASE) Program and erase supply voltage
1.8
3.6
5
V
mA
IPGM
Average supply current from DVCC during program
3
6
6
IERASE
Average supply current from DVCC during erase
Average supply current from DVCC during mass erase or bank erase
Cumulative program time(1)
11
11
16
mA
IMERASE, IBANK
tCPT
mA
ms
Program and erase endurance
104
100
64
105
cycles
years
µs
tRetention
tWord
Data retention duration
Word or byte program time(2)
Block program time for first byte or word(2)
25°C
85
65
tBlock, 0
49
µs
Block program time for each additional byte or word, except for last byte
or word(2)
Block program time for last byte or word(2)
tBlock, 1–(N–1)
tBlock, N
37
55
23
49
73
32
µs
µs
Erase time for segment erase, mass erase, and bank erase when
available(2)
tErase
ms
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
fMCLK,MGR
0
1
MHz
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
modes: individual word or byte write and block write.
(2) These values are hardwired into the state machine of the flash controller.
5.8.14 Emulation and Debug
Table 5-49 lists the characteristics of the JTAG and Spy-Bi-Wire interface.
Table 5-49. JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Spy-Bi-Wire input frequency
VCC
MIN
0
TYP
MAX UNIT
fSBW
2.2 V, 3 V
2.2 V, 3 V
20
15
MHz
µs
tSBW,Low
Spy-Bi-Wire low clock pulse duration
0.025
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge)(1)
tSBW, En
tSBW,Rst
2.2 V, 3 V
1
µs
µs
Spy-Bi-Wire return to normal operation time
TCK input frequency for 4-wire JTAG(2)
Internal pulldown resistance on TEST
15
0
100
5
2.2 V
3 V
fTCK
MHz
0
10
80
Rinternal
2.2 V, 3 V
45
60
kΩ
(1) Tools that access the Spy-Bi-Wire interface must wait for the minimum tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
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6 Detailed Description
6.1 Overview
The MSP430F673xA and MSP430F673xA microcontrollers feature three high-performance 24-bit sigma-
delta ADCs, a 10-bit ADC, four enhanced universal serial communication interfaces (three eUSCI_A
modules and one eUSCI_B module), four 16-bit timers, a hardware multiplier, a DMA module, an RTC
module with alarm capabilities, a segment LCD driver with integrated contrast control, an auxiliary supply
system, and up to 72 I/O pins in the 100-pin devices and 52 I/O pins in the 80-pin devices.
6.2 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are
dedicated as program counter, stack pointer, status register, and constant generator, respectively. The
remaining registers are general-purpose registers (see 图 6-1).
Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be
managed with all instructions.
Program Counter
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
图 6-1. Integrated CPU Registers
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6.3 Instruction Set
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data. 表 6-1 lists examples of the three types of instruction formats. 表 6-2 lists the address modes.
表 6-1. Instruction Word Formats
INSTRUCTION WORD FORMAT
Dual operands, source-destination
EXAMPLE
ADD R4,R5
OPERATION
R4 + R5 → R5
Single operands, destination only
CALL R8
JNE
PC → (TOS), R8 → PC
Relative jump, conditional or unconditional
Jump-on-equal bit = 0
表 6-2. Address Mode Descriptions
ADDRESS MODE
Register
S(1)
+
D(1)
+
SYNTAX
MOV Rs,Rd
EXAMPLE
OPERATION
R10 → R11
MOV R10,R11
Indexed
+
+
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV & MEM, & TCDAT
MOV @Rn,Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
M(R10) → M(Tab+R6)
Symbolic (PC relative)
Absolute
+
+
+
+
Indirect
+
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
M(R10) → R11
R10 + 2 → R10
Indirect autoincrement
+
+
MOV @Rn+,Rm
MOV #X,TONI
Immediate
#45 → M(TONI)
(1) S = source, D = destination
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6.4 Operating Modes
The MSP430F673xA and MSP430F673xA microcontrollers have one active mode and seven software-
selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-
power modes, service the request, and restore back to the low-power mode on return from the interrupt
program.
Software can configure the following operating modes:
•
Active mode (AM)
All clocks are active
Low-power mode 0 (LPM0)
–
•
–
–
–
CPU is disabled
ACLK and SMCLK remain active, MCLK is disabled
FLL loop control remains active
•
•
Low-power mode 1 (LPM1)
–
–
–
CPU is disabled
FLL loop control is disabled
ACLK and SMCLK remain active, MCLK is disabled
Low-power mode 2 (LPM2)
–
–
–
–
CPU is disabled
MCLK and FLL loop control and DCOCLK are disabled
DC generator of the DCO remains enabled
ACLK remains active
•
•
Low-power mode 3 (LPM3)
–
–
–
–
CPU is disabled
MCLK, FLL loop control, and DCOCLK are disabled
DC generator of the DCO is disabled
ACLK remains active
Low-power mode 4 (LPM4)
–
–
–
–
–
–
CPU is disabled
ACLK is disabled
MCLK, FLL loop control, and DCOCLK are disabled
DC generator of the DCO is disabled
Crystal oscillator is stopped
Complete data retention
•
•
Low-power mode 3.5 (LPM3.5)
–
–
–
–
–
Internal regulator disabled
No RAM retention, Backup RAM retained
I/O pad state retention
RTC clocked by low-frequency oscillator
Wake-up input from RST/NMI, RTC_C events, Ports P1 and P2
Low-power mode 4.5 (LPM4.5)
–
–
–
–
–
Internal regulator disabled
No RAM retention, Backup RAM retained
RTC is disabled
I/O pad state retention
Wake-up input from RST/NMI, Ports P1 and P2
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6.5 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see 表
6-3). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
表 6-3. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
System Reset
Power-Up
External Reset
(2)
WDTIFG, KEYV (SYSRSTIV)(1)
Reset
0FFFEh
0FFFCh
63, highest
Watchdog Time-out, Key Violation
Flash Memory Key Violation
System NMI
PMM
Vacant Memory Access
JTAG Mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
(Non)maskable
62
(1) (3)
JMBOUTIFG (SYSSNIV)
User NMI
NMI
Oscillator Fault
NMIIFG, OFIFG, ACCVIFG, AUXSWNMIFG
(SYSUNIV)(1) (3)
(Non)maskable
Maskable
0FFFAh
0FFF8h
61
60
Flash Memory Access Violation
Supply Switch
Watchdog Timer_A Interval Timer
Mode
WDTIFG
eUSCI_A0 Receive or Transmit
eUSCI_B0 Receive or Transmit
UCA0RXIFG, UCA0TXIFG (UCA0IV)(1) (4)
UCB0RXIFG, UCB0TXIFG (UCB0IV)(1) (4)
Maskable
Maskable
0FFF6h
0FFF4h
59
58
ADC10IFG0, ADC10INIFG, ADC10LOIFG,
ADC10HIIFG, ADC10TOVIFG, ADC10OVIFG
(ADC10IV)(1) (4)
ADC10_A
Maskable
0FFF2h
57
SD24_B
SD24_B Interrupt Flags (SD24IV)(1) (4)
TA0CCR0 CCIFG0(4)
Maskable
Maskable
0FFF0h
0FFEEh
56
55
Timer TA0
TA0CCR1 CCIFG1, TA0CCR2 CCIFG2,
TA0IFG (TA0IV)(1) (4)
Timer TA0
Maskable
0FFECh
54
eUSCI_A1 Receive or Transmit
eUSCI_A2 Receive or Transmit
Auxiliary Supplies
DMA
UCA1RXIFG, UCA1TXIFG (UCA1IV)(1) (4)
UCA2RXIFG, UCA2TXIFG (UCA2IV)(1) (4)
Auxiliary Supplies Interrupt Flags (AUXIV)(1) (4)
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1) (4)
TA1CCR0 CCIFG0(4)
Maskable
Maskable
Maskable
Maskable
Maskable
0FFEAh
0FFE8h
0FFE6h
0FFE4h
0FFE2h
53
52
51
50
49
Timer TA1
TA1CCR1 CCIFG1,
TA1IFG (TA1IV)(1) (4)
Timer TA1
Maskable
0FFE0h
48
I/O Port P1
Timer TA2
P1IFG.0 to P1IFG.7 (P1IV)(1) (4)
TA2CCR0 CCIFG0(4)
Maskable
Maskable
0FFDEh
0FFDCh
47
46
TA2CCR1 CCIFG1,
TA2IFG (TA2IV)(1) (4)
Timer TA2
Maskable
0FFDAh
45
I/O Port P2
Timer TA3
P2IFG.0 to P2IFG.7 (P2IV)(1) (4)
TA3CCR0 CCIFG0(4)
Maskable
Maskable
0FFD8h
0FFD6h
44
43
TA3CCR1 CCIFG1,
TA3IFG (TA3IV)(1) (4)
LCD_C Interrupt Flags (LCDCIV)(1) (4)
Timer TA3
LCD_C
Maskable
Maskable
Maskable
0FFD4h
0FFD2h
0FFD0h
42
41
40
RTCOFIFG, RTCRDYIFG, RTCTEVIFG,
RTC_C
RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV)(1) (4)
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(3) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(4) Interrupt flags are located in the module.
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表 6-3. Interrupt Sources, Flags, and Vectors (continued)
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
0FFCEh
⋮
39
Reserved
Reserved(5)
⋮
0FF80h
0, lowest
(5) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, TI recommends reserving these locations.
6.6 Bootloader (BSL)
The BSL lets users program the flash memory or RAM using various serial interfaces. Access to the
device memory through the BSL is protected by an user-defined password. BSL entry requires a specific
entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For complete description of the
features of the BSL and its implementation, see the MSP430™ Flash Device Bootloader (BSL) User's
Guide. 表 6-4 lists the BSL pin requirements.
表 6-4. UART BSL Pin Requirements and Functions
DEVICE SIGNAL
RST/NMI/SBWTDIO
TEST/SBWTCK
P3.0
BSL FUNCTION
Entry sequence signal
Entry sequence signal
Data transmit
P3.1
Data receive
DVCC
Power supply
DVSS
Ground supply
6.7 JTAG Operation
6.7.1 JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. 表 6-5 lists the JTAG pin requirements. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools
User's Guide and MSP430 Programming With the JTAG Interface.
表 6-5. JTAG Pin Requirements and Functions
DEVICE SIGNAL
PJ.3/ACLK/TCK
PJ.2/ADC10CLK/TMS
PJ.1/MCLK/TDI/TCLK
PJ.0/SMCLK/TDO
TEST/SBWTCK
RST/NMI/SBWTDIO
DVCC
DIRECTION
FUNCTION
JTAG clock input
JTAG state control
JTAG data input/TCLK input
JTAG data output
Enable JTAG pins
External reset
IN
IN
IN
OUT
IN
IN
Power supply
DVSS
Ground supply
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6.7.2 Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two-wire Spy-Bi-Wire
interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers.
表 6-6 lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to development
tools and device programmers, see the MSP430 Hardware Tools User's Guide and MSP430 Programming
With the JTAG Interface.
表 6-6. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
DVCC
DIRECTION
IN
FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input/output
Power supply
IN, OUT
DVSS
Ground supply
6.8 Flash Memory
The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system
by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory.
Features of the flash memory include:
•
Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
•
•
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are
also called information memory.
•
Segment A can be locked separately.
6.9 RAM
The RAM is made up of n sectors. Each sector can be completely powered down to save leakage;
however, all data are lost. Features of the RAM include:
•
•
•
RAM has n sectors of 2 kbytes each.
Each sector 0 to n can be completely disabled; however, data retention is lost.
Each sector 0 to n automatically enters low-power retention mode when possible.
6.10 Backup RAM
The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5. This
backup RAM is part of the Backup subsystem that operates on dedicated power supply AUXVCC3. 8
bytes of backup RAM are available in this device. The backup RAM can be word-wise accessed through
the registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3. The backup RAM registers cannot be
accessed by the CPU when the high-side SVS is disabled by software.
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6.11 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. The peripherals can be
handled using all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx
Family User's Guide.
6.11.1 Oscillator and System Clock
The Unified Clock System (UCS) module includes support for a 32768-Hz watch crystal oscillator, an
internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator
(REFO), and an integrated internal digitally controlled oscillator (DCO). The UCS module is designed to
meet the requirements of both low system cost and low power consumption. The UCS module features
digital frequency-locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the
DCO frequency to a programmable multiple of the selected FLL reference frequency. The internal DCO
provides a fast turn-on clock source and stabilizes in 3 µs (typical). The UCS module provides the
following clock signals:
•
•
•
•
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, the internal low-frequency oscillator
(VLO), or the trimmed low-frequency oscillator (REFO).
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources made available to ACLK.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
6.11.2 Power-Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and
contains programmable output levels to provide for power optimization. The PMM also includes supply
voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection.
The brownout circuit is implemented to provide the proper internal reset signal to the device during power-
on and power-off. The SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level
and supports both supply voltage supervision (the device is automatically reset) and supply voltage
monitoring (the device is not automatically reset). SVS and SVM are available on the primary supply and
the core supply.
6.11.3 Auxiliary Supply System
The auxiliary supply system provides the possibility to operate the device from auxiliary supplies when the
primary supply fails.There are two auxililary supplies (AUXVCC1 and AUXVCC2) are supported. This
module supports automatic and manual switching from primary supply to auxiliary suppllies while
maintaining full functionality. It allows threshold based monitoring of primary and auxiliary supplies. The
device can be started from primary supply or AUXVCC1, whichever is higher. Auxiliary supply system
enables internal monitoring of voltage levels on primary and auxiliary supplies using ADC10_A. Also this
module implements simple charger for backup supplies.
6.11.4 Backup Subsystem
The Backup subsystem operates on a dedicated power supply AUXVCC3. This subsystem includes low-
frequency oscillator (XT1), RTC module, and backup RAM. The functionality of the Backup subsystem is
retained during LPM3.5. The Backup subsystem module registers cannot be accessed by CPU when the
high-side SVS is disabled by the user. It is necessary to keep the high-side SVS enabled with SVSHMD =
1 and SVSMHACE = 0 to turn off the low-frequency oscillator (XT1) in LPM4.
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Detailed Description
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MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
6.11.5 Digital I/O
Up to nine 8-bit I/O ports are implemented. For 100-pin options, Ports P1 to P8 are complete, and P9 is
reduced to 4-bit I/O. For 80-pin options, Ports P1 to P6 are complete, and P7 to P9 are completely
removed. Port PJ contains four individual I/O pins, common to all devices. All I/O bits are individually
programmable.
•
•
•
•
Any combination of input, output and interrupt conditions is possible.
Pullup or pulldown on all ports is programmable.
Programmable drive strength on all ports.
Edge-selectable interrupt and LPM3.5, LPM4.5 wake-up input capability available for all bits of ports
P1 and P2.
•
•
Read and write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PE).
6.11.6 Port Mapping Controller
The port mapping controller allows flexible and reconfigurable mapping of digital functions to P1, P2, and
P3 (see 表 6-7). 表 6-8 lists the default settings for all pins that support port mapping.
表 6-7. Port Mapping Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
PM_NONE
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
0
None
DVSS
PM_UCA0RXD
PM_UCA0SOMI
PM_UCA0TXD
PM_UCA0SIMO
PM_UCA0CLK
PM_UCA0STE
PM_UCA1RXD
PM_UCA1SOMI
PM_UCA1TXD
PM_UCA1SIMO
PM_UCA1CLK
PM_UCA1STE
PM_UCA2RXD
PM_UCA2SOMI
PM_UCA2TXD
PM_ UCA2SIMO
PM_UCA2CLK
PM_UCA2STE
PM_UCB0SIMO
PM_UCB0SDA
PM_UCB0SOMI
PM_UCB0SCL
PM_UCB0CLK
PM_UCB0STE
PM_TA0.0
eUSCI_A0 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A0 UART TXD (direction controlled by eUSCI – Output)
eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A0 clock input/output (direction controlled by eUSCI)
eUSCI_A0 SPI slave transmit enable (direction controlled by eUSCI)
eUSCI_A1 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A1 UART TXD (direction controlled by eUSCI – Output)
eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A1 clock input/output (direction controlled by eUSCI)
eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)
eUSCI_A2 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A2 UART TXD (direction controlled by eUSCI – Output)
eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A2 clock input/output (direction controlled by eUSCI)
eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)
eUSCI_B0 SPI slave in master out (direction controlled by eUSCI)
eUSCI_B0 I2C data (open drain and direction controlled by eUSCI)
eUSCI_B0 SPI slave out master in (direction controlled by eUSCI)
eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI)
eUSCI_B0 clock input/output (direction controlled by eUSCI)
eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
TA0 CCR0 capture input CCI0A
TA0 CCR1 capture input CCI1A
TA0 CCR2 capture input CCI2A
TA1 CCR0 capture input CCI0A
TA1 CCR1 capture input CCI1A
TA0 CCR0 compare output Out0
TA0 CCR1 compare output Out1
TA0 CCR2 compare output Out2
TA1 CCR0 compare output Out0
TA1 CCR1 compare output Out1
PM_TA0.1
PM_TA0.2
PM_TA1.0
PM_TA1.1
82
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MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
表 6-7. Port Mapping Mnemonics and Functions (continued)
VALUE
22
PxMAPy MNEMONIC
PM_TA2.0
INPUT PIN FUNCTION
TA2 CCR0 capture input CCI0A
OUTPUT PIN FUNCTION
TA2 CCR0 compare output Out0
TA2 CCR1 compare output Out1
TA3 CCR0 compare output Out0
TA3 CCR1 compare output Out1
23
PM_TA2.1
PM_TA3.0
PM_TA3.1
TA2 CCR1 capture input CCI1A
TA3 CCR0 capture input CCI0A
TA3 CCR1 capture input CCI1A
24
25
Timer_A clock input to
TA0, TA1, TA2, TA3
PM_TACLK
None
26
PM_RTCCLK
PM_SDCLK
PM_SD0DIO
PM_SD1DIO
PM_SD2DIO
None
RTC_C clock output
27
28
29
30
SD24_B bit stream clock input/output (direction controlled by SD24_B)
SD24_B converter 0 bit stream data input/output (direction controlled by SD24_B)
SD24_B converter 1 bit stream data input/output (direction controlled by SD24_B)
SD24_B converter 2 bit stream data input/output (direction controlled by SD24_B)
Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents
when applying analog signals.
(1)
31 (0FFh)
PM_ANALOG
(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide, and the upper bits are
ignored, which results in a read value of 31.
表 6-8. Default Mapping
PIN NAME
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
PZ
PN
P1.0/PM_TA0.0/
VeREF-/A2
P1.0/PM_TA0.0/
VeREF-/A2
PM_TA0.0
PM_TA0.1
TA0 CCR0 capture input CCI0A
TA0 CCR1 capture input CCI1A
TA0 CCR0 compare output Out0
TA0 CCR1 compare output Out1
P1.1/PM_TA0.1/
VeREF+/A1
P1.1/PM_TA0.1/
VeREF+/A1
eUSCI_A0 UART RXD
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0
PM_UCA0RXD,
PM_UCA0SOMI
(direction controlled by eUSCI – input),
eUSCI_A0 SPI slave out master in
(direction controlled by eUSCI)
eUSCI_A0 UART TXD
(direction controlled by eUSCI – output),
eUSCI_A0 SPI slave in master out
(direction controlled by eUSCI)
P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03
P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03
PM_UCA0TXD,
PM_UCA0SIMO
eUSCI_A1 UART RXD
(direction controlled by eUSCI – input),
eUSCI_A1 SPI slave out master in
(direction controlled by eUSCI)
P1.4/PM_UCA1RXD/
PM_UCA1SOMI/
LCDREF/R13
P1.4/PM_UCA1RXD/
PM_UCA1SOMI/
LCDREF/R13
PM_UCA1RXD,
PM_UCA1SOMI
eUSCI_A1 UART TXD
(direction controlled by eUSCI – output),
eUSCI_A1 SPI slave in master out
(direction controlled by eUSCI)
P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23
P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23
PM_UCA1TXD,
PM_UCA1SIMO
P1.6/PM_UCA0CLK/
COM4
P1.6/PM_UCA0CLK/
COM4
PM_UCA0CLK
PM_UCB0CLK
eUSCI_A0 clock input/output (direction controlled by eUSCI)
eUSCI_B0 clock input/output (direction controlled by eUSCI)
P1.7/PM_UCB0CLK/
COM5
P1.7/PM_UCB0CLK/
COM5
eUSCI_B0 SPI slave out master in
(direction controlled by eUSCI),
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6/S39
PM_UCB0SOMI,
PM_UCB0SCL
eUSCI_B0 I2C clock
(open drain and direction controlled by eUSCI)
eUSCI_B0 SPI slave in master out
(direction controlled by eUSCI),
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7/S38
PM_UCB0SIMO,
PM_UCB0SDA
eUSCI_B0 I2C data
(open drain and direction controlled by eUSCI)
eUSCI_A2 UART RXD
(direction controlled by eUSCI – input),
eUSCI_A2 SPI slave out master in
(direction controlled by eUSCI)
P2.2/PM_UCA2RXD/
PM_UCA2SOMI
P2.2/PM_UCA2RXD/
PM_UCA2SOMI/S37
PM_UCA2RXD,
PM_UCA2SOMI
eUSCI_A2 UART TXD
(direction controlled by eUSCI – output),
eUSCI_A2 SPI slave in master out
(direction controlled by eUSCI)
P2.3/PM_UCA2TXD/
PM_UCA2SIMO
P2.3/PM_UCA2TXD/
PM_UCA2SIMO/S36
PM_UCA2TXD,
PM_UCA2SIMO
P2.4/PM_UCA1CLK
P2.4/PM_UCA1CLK/S35
PM_UCA1CLK
eUSCI_A1 clock input/output (direction controlled by eUSCI)
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MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
表 6-8. Default Mapping (continued)
PIN NAME
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
PZ
P2.5/PM_UCA2CLK
P2.6/PM_TA1.0
P2.7/PM_TA1.1
P3.0/PM_TA2.0
P3.1/PM_TA2.1
PN
P2.5/PM_UCA2CLK/S34
P2.6/PM_TA1.0/S33
P2.7/PM_TA1.1/S32
P3.0/PM_TA2.0/S31
P3.1/PM_TA2.1/S30
PM_UCA2CLK
PM_TA1.0
PM_TA1.1
PM_TA2.0
PM_TA2.1
eUSCI_A2 clock input/output (direction controlled by eUSCI)
TA1 CCR0 capture input CCI0A
TA1 CCR1 capture input CCI1A
TA2 CCR0 capture input CCI0A
TA2 CCR1 capture input CCI1A
TA1 CCR0 compare output Out0
TA1 CCR1 compare output Out1
TA2 CCR0 compare output Out0
TA2 CCR1 compare output Out1
P3.2/PM_TACLK/
PM_RTCCLK
P3.2/PM_TACLK/
PM_RTCCLK/S29
PM_TACLK,
PM_RTCCLK
Timer_A clock input to
TA0, TA1, TA2, TA3
RTC_C clock output
P3.3/PM_TA0.2
P3.3/PM_TA0.2/S28
P3.4/PM_SDCLK/S27
PM_TA0.2
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
SD24_B bit stream clock input/output
(direction controlled by SD24_B)
P3.4/PM_SDCLK/S39
PM_SDCLK
SD24_B converter 0 bit stream data input/output
(direction controlled by SD24_B)
P3.5/PM_SD0DIO/S38
P3.6/PM_SD1DIO/S37
P3.7/PM_SD2DIO/S36
P3.5/PM_SD0DIO/S26
P3.6/PM_SD1DIO/S25
P3.7/PM_SD2DIO/S24
PM_SD0DIO
PM_SD1DIO
PM_SD2DIO
SD24_B converter 1 bit stream data input/output
(direction controlled by SD24_B)
SD24_B converter 2 bit stream data input/output
(direction controlled by SD24_B)
6.11.7 System Module (SYS)
The SYS module handles many of the system functions within the device. These include power-on reset
(POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector
generators (see 表 6-9), bootloader entry mechanisms, and configuration management (device
descriptors). It also includes a data exchange mechanism through JTAG called a JTAG mailbox that can
be used in the application.
表 6-9. System Module Interrupt Vector Registers
WORD
ADDRESS
INTERRUPT VECTOR REGISTER
INTERRUPT EVENT
OFFSET
PRIORITY
No interrupt pending
Brownout (BOR)
00h
02h
Highest
RST/NMI (POR)
04h
DoBOR (BOR)
06h
Wakeup from LPMx.5 (BOR)
Security violation (BOR)
SVSL (POR)
08h
0Ah
0Ch
0Eh
SVSH (POR)
SVML_OVP (POR)
SVMH_OVP (POR)
DoPOR (POR)
10h
SYSRSTIV, System Reset
019Eh
12h
14h
WDT time-out (PUC)
WDT key violation (PUC)
KEYV flash key violation (PUC)
Reserved
16h
18h
1Ah
1Ch
1Eh
Peripheral area fetch (PUC)
PMM key violation (PUC)
Reserved
20h
22h to 3Eh
Lowest
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MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
表 6-9. System Module Interrupt Vector Registers (continued)
WORD
ADDRESS
INTERRUPT VECTOR REGISTER
INTERRUPT EVENT
OFFSET
PRIORITY
No interrupt pending
SVMLIFG
00h
02h
Highest
SVMHIFG
DLYLIFG
04h
06h
DLYHIFG
08h
SYSSNIV, System NMI
VMAIFG
019Ch
0Ah
JMBINIFG
JMBOUTIFG
VLRLIFG
0Ch
0Eh
10h
VLRHIFG
12h
Reserved
14h to 1Eh
00h
Lowest
Highest
No interrupt pending
NMIIFG
02h
OFIFG
04h
SYSUNIV, User NMI
019Ah
ACCVIFG
06h
AUXSWNMIFG
Reserved
08h
0Ah to 1Eh
Lowest
6.11.8 Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart after a software
problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function
is not needed in an application, the timer can be configured as an interval timer and can generate
interrupts at selected time intervals.
6.11.9 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC10_A conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral. 表 6-10 lists the available DMA triggers.
表 6-10. DMA Trigger Assignments(1)
CHANNEL
TRIGGER
0
1
2
0
1
2
3
4
5
6
7
8
9
DMAREQ
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
Reserved
TA2CCR0 CCIFG
Reserved
TA3CCR0 CCIFG
Reserved
Reserved
(1) Reserved DMA triggers may be used by other devices in the family.
Reserved DMA triggers do not cause any DMA trigger event when
selected.
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MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
表 6-10. DMA Trigger Assignments(1) (continued)
CHANNEL
TRIGGER
0
1
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved
Reserved
Reserved
SD24IFG
Reserved
Reserved
UCA0RXIFG
UCA0TXIFG
UCA1RXIFG
UCA1TXIFG
UCA2RXIFG
UCA2TXIFG
UCB0RXIFG0
UCB0TXIFG0
ADC10IFG0
Reserved
Reserved
Reserved
Reserved
MPY ready
DMA0IFG
Reserved
DMA2IFG
DMA1IFG
6.11.10 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
6.11.11 Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication
as well as signed and unsigned multiply-and-accumulate operations.
6.11.12 Enhanced Universal Serial Communication Interface (eUSCI)
The eUSCI module is used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3- or 4-pin) and I2C, and asynchronous communication protocols
such as UART, enhanced UART with automatic baud-rate detection, and IrDA.
The eUSCI_An module supports for SPI (3- or 4-pin), UART, enhanced UART, or IrDA.
The eUSCI_Bn module supports for SPI (3- or 4-pin) or I2C.
Three eUSCI_A and one eUSCI_B module are implemented.
6.11.13 ADC10_A
The ADC10_A module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit
SAR core, sample select control, reference generator, and a conversion results buffer. A window
comparator with a lower and upper limit allows CPU independent result monitoring with three window
comparator interrupt flags.
86
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MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
6.11.14 SD24_B
The SD24_B module integrates up to three independent 24-bit sigma-delta analog-to-digital converters.
Each converter is designed with a fully differential analog input pair and programmable gain amplifier input
stage. The converters are based on second-order over-sampling sigma-delta modulators and digital
decimation filters. The decimation filters are comb-type filters with selectable oversampling ratios of up to
1024.
6.11.15 TA0
TA0 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA0 can support
multiple capture/compares, PWM outputs, and interval timing (see 表 6-11). TA0 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
表 6-11. TA0 Signal Connections
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
DEVICE INPUT SIGNAL
MODULE INPUT NAME
MODULE BLOCK
PM_TACLK
ACLK (internal)
SMCLK (internal)
PM_TACLK
PM_TA0.0
DVSS
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
NA
NA
PM_TA0.0
CCR0
CCR1
CCR2
TA0
DVSS
DVCC
VCC
PM_TA0.1
CCI1A
PM_TA0.1
ADC10_A (internal)
ADC10SHSx = {1}
ACLK (internal)
DVSS
CCI1B
GND
TA1
TA2
SD24_B (internal)
SD24SCSx = {1}
DVCC
PM_TA0.2
DVSS
VCC
CCI2A
CCI2B
GND
PM_TA0.2
DVSS
DVCC
VCC
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MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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6.11.16 TA1
TA1 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA1 can support multiple
capture/compares, PWM outputs, and interval timing (see 表 6-12). TA1 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
表 6-12. TA1 Signal Connections
DEVICE OUTPUT
MODULE OUTPUT
SIGNAL
PZ
DEVICE INPUT SIGNAL
MODULE INPUT NAME
MODULE BLOCK
SIGNAL
PM_TACLK
ACLK (internal)
SMCLK (internal)
PM_TACLK
PM_TA1.0
DVSS
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
NA
NA
PM_TA1.0
CCR0
CCR1
TA0
TA1
DVSS
DVCC
VCC
PM_TA1.1
ACLK (internal)
DVSS
CCI1A
CCI1B
GND
PM_TA1.1
DVCC
VCC
6.11.17 TA2
TA2 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA2 can support multiple
capture/compares, PWM outputs, and interval timing (see 表 6-13). TA2 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
表 6-13. TA2 Signal Connections
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
DEVICE INPUT SIGNAL
MODULE INPUT NAME
MODULE BLOCK
PM_TACLK
ACLK (internal)
SMCLK (internal)
PM_TACLK
PM_TA2.0
DVSS
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
NA
NA
PM_TA2.0
CCR0
CCR1
TA0
DVSS
DVCC
VCC
PM_TA2.1
CCI1A
PM_TA2.1
SD24_B (internal)
SD24SCSx = {2}
ACLK (internal)
CCI1B
TA1
DVSS
DVCC
GND
VCC
88
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
6.11.18 TA3
TA3 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA3 can support multiple
capture/compares, PWM outputs, and interval timing (see 表 6-14). TA3 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
表 6-14. TA3 Signal Connections
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
DEVICE INPUT SIGNAL
MODULE INPUT NAME
MODULE BLOCK
PM_TACLK
ACLK (internal)
SMCLK (internal)
PM_TACLK
TACLK
ACLK
Timer
NA
SMCLK
INCLK
CCI0A
PM_TA3.0
PM_TA3.0
ADC10_A (internal)
ADC10SHSx = {2}
DVSS
CCI0B
CCR0
CCR1
TA0
DVSS
DVCC
GND
VCC
PM_TA3.1
CCI1A
PM_TA3.1
SD24_B (internal)
SD24SCSx = {3}
ACLK (internal)
CCI1B
TA1
DVSS
DVCC
GND
VCC
6.11.19 SD24_B Triggers
表 6-15 lists the input trigger connections to SD24_B converters from Timer_A modules and the output
trigger pulse connection from SD24_B to ADC10_A.
表 6-15. SD24_B Input/Output Trigger Connections
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
DEVICE INPUT SIGNAL MODULE INPUT SIGNAL
MODULE BLOCK
SD24_B
TA0.1 (internal)
ADC10_A (internal)
ADC10SHSx = {3}
Trigger Pulse
SD24SCSx = {1}
SD24_B
TA2.1 (internal)
SD24_B
SD24SCSx = {2}
SD24_B
TA3.1 (internal)
SD24SCSx = {3}
6.11.20 ADC10_A Triggers
表 6-16 lists the input trigger connections to ADC10_A from Timer_A modules and SD24_B.
表 6-16. ADC10_A Input Trigger Connections
DEVICE INPUT SIGNAL
MODULE INPUT SIGNAL
MODULE BLOCK
ADC10_A
ADC10SHSx = {1}
TA0.1 (internal)
ADC10_A
ADC10_A
TA3.0 (internal)
ADC10SHSx = {2}
版权 © 2015–2018, Texas Instruments Incorporated
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
6.11.21 Real-Time Clock (RTC_C)
The RTC_C module can be configured for real-time clock or calendar mode that provides seconds, hours,
day of week, day of month, month, and year. The RTC_C control and configuration registers are
password-protected to ensure clock integrity against runaway code. Calendar mode integrates an internal
calendar that compensates for months with less than 31 days and includes leap year correction. The
RTC_C also supports flexible alarm functions, offset calibration, and temperature compensation. The
RTC_C on this device operates on dedicated AUXVCC3 supply and supports operation in LPM3.5.
6.11.22 Reference (REF) ModuleVoltage Reference
The REF is responsible for generation of all critical reference voltages that can be used by the various
analog peripherals in the device. These include the ADC10_A, LCD_C, and SD24_B modules.
6.11.23 LCD_C
The LCD_C driver generates the segment and common signals required to drive a segment liquid crystal
display (LCD). The LCD_C controller has dedicated data memories to hold segment drive information.
Common and segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, 4-mux, up to
8-mux LCDs are supported. The module can provide a LCD voltage independent of the supply voltage
with its integrated charge pump. It is possible to control the level of the LCD voltage, and thus contrast, by
software. The module also provides an automatic blinking capability for individual segments in static, 2-
mux, 3-mux, and 4-mux modes.
6.11.24 Embedded Emulation Module (EEM) (S Version)
The EEM supports real-time in-system debugging. The S version of the EEM has the following features:
•
•
•
•
•
Three hardware triggers or breakpoints on memory access
One hardware trigger or breakpoint on CPU register write access
Up to four hardware triggers can be combined to form complex triggers or breakpoints
One cycle counter
Clock control on module level
90
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
6.12 Input/Output Diagrams
6.12.1 Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ and
MSP430F67xxAIPN)
图 6-2 shows the port diagram. 表 6-17 summarizes the selection of the pin functions.
Pad Logic
to/from Reference
To ADC10_A
INCHx = y
P1REN.x
P1MAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
1
P1DIR.x
0
1
Direction
0: Input
1: Output
from Port Mapping
P1OUT.x
0
1
from Port Mapping
P1.0/PM_TA0.0/VeREF-/A2
P1.1/PM_TA0.1/VeREF+/A1
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
Bus
Keeper
EN
D
to Port Mapping
P1IRQ.x
P1IE.x
EN
Set
Q
P1IFG.x
P1SEL.x
P1IES.x
Interrupt
Edge
Select
图 6-2. Port P1 (P1.0 and P1.1) Diagram (MSP430F67xxAIPZ and MSP430F67xxAIPN)
版权 © 2015–2018, Texas Instruments Incorporated
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
表 6-17. Port P1 (P1.0 and P1.1) Pin Functions (MSP430F67xxAIPZ and MSP430F67xxAIPN)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
P1MAPx
X
P1.0 (I/O)
I: 0; O: 1
0
1
1
1
0
1
1
1
TA0.CCI0A
0
default
default
= 31
P1.0/PM_TA0.0/
VeREF-/A2
0
TA0.TA0
1
VeREF-/A2(2)
P1.1 (I/O)
X
I: 0; O: 1
X
TA0.CCI1A
TA0.TA1
VeREF+/A1(2)
0
1
X
default
default
= 31
P1.1/PM_TA0.1/
VeREF+/A1
1
(1) X = Don't care
(2) Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger.
92
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
6.12.2 Port P1 (P1.2) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ and
MSP430F67xxAIPN)
图 6-3 shows the port diagram. 表 6-18 summarizes the selection of the pin functions.
Pad Logic
To ADC10_A
INCHx = y
P1REN.x
P1MAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
1
P1DIR.x
0
1
Direction
0: Input
1: Output
from Port Mapping
P1OUT.x
0
1
from Port Mapping
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
Bus
Keeper
EN
D
to Port Mapping
P1IRQ.x
P1IE.x
EN
Set
Q
P1IFG.x
P1SEL.x
P1IES.x
Interrupt
Edge
Select
图 6-3. Port P1 (P1.2) Diagram (MSP430F67xxAIPZ and MSP430F67xxAIPN)
表 6-18. Port P1 (P1.2) Pin Functions (MSP430F67xxAIPZ and MSP430F67xxAIPN)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
P1MAPx
P1.2 (I/O)
I: 0; O: 1
0
1
1
X
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0
2
UCA0RXD/UCA0SOMI
A0(2)
X
X
default
= 31
(1) X = Don't care
(2) Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger.
版权 © 2015–2018, Texas Instruments Incorporated
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
6.12.3 Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ and
MSP430F67xxAIPN)
图 6-4 shows the port diagram. 表 6-19 summarizes the selection of the pin functions.
to LCD_C
Pad Logic
P1REN.x
P1MAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
1
P1DIR.x
0
1
Direction
0: Input
1: Output
from Port Mapping
P1OUT.x
0
1
from Port Mapping
P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03
P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13
P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
Bus
Keeper
EN
D
to Port Mapping
P1IRQ.x
P1IE.x
EN
Set
Q
P1IFG.x
P1SEL.x
P1IES.x
Interrupt
Edge
Select
图 6-4. Port P1 (P1.3 to P1.5) Diagram (MSP430F67xxAIPZ and MSP430F67xxAIPN)
表 6-19. Port P1 (P1.3 to P1.5) Pin Functions (MSP430F67xxAIPZ and MSP430F67xxAIPN)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
P1MAPx
X
P1.3 (I/O)
I: 0; O: 1
0
1
1
0
1
1
0
1
1
P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03
3
UCA0TXD/UCA0SIMO
R03(2)
X
default
= 31
X
X
P1.4 (I/O)
I: 0; O: 1
P1.4/PM_UCA1RXD/
PM_UCA1SOMI/
LCDREF/R13
4
5
UCA1RXD/UCA1SOMI
LCDREF/R13(2)
P1.5 (I/O)
X
default
= 31
X
X
I: 0; O: 1
P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23
UCA1TXD/UCA1SIMO
R23(2)
X
X
default
= 31
(1) X = Don't care
(2) Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger.
94
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
6.12.4 Port P1 (P1.6 and P1.7) (MSP430F67xxAIPZ and MSP430F67xxAIPN) and
Port P2 (P2.0 and P2.1) (MSP430F67xxAIPZ Only) Input/Output With Schmitt Trigger
图 6-5 shows the port diagram. 表 6-20 and 表 6-21 summarize the selection of the pin functions.
COM4 to COM7
from LCD_C
Pad Logic
PyREN.x
PyMAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
1
PyDIR.x
0
1
Direction
0: Input
1: Output
from Port Mapping
PyOUT.x
0
1
from Port Mapping
P1.6/PM_UCA0CLK/COM4
P1.7/PM_UCB0CLK/COM5
P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7
PyDS.x
0: Low drive
1: High drive
PySEL.x
PyIN.x
Bus
Keeper
EN
D
to Port Mapping
PyIRQ.x
PyIE.x
EN
Set
Q
PyIFG.x
PySEL.x
PyIES.x
Interrupt
Edge
Select
图 6-5. Port P1 (P1.6 and P1.7) (MSP430F67xxAIPZ and MSP430F67xxAIPN), Port P2 (P2.0 and P2.1)
(MSP430F67xxAIPZ Only) Diagram
版权 © 2015–2018, Texas Instruments Incorporated
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
表 6-20. Port P1 (P1.6 and P1.7) Pin Functions (MSP430F67xxAIPZ and MSP430F67xxAIPN)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
COM4, COM5
Enable Signal
P1DIR.x
P1SEL.x
P1MAPx
P1.6 (I/O)
UCA0CLK
I: 0; O: 1
X
0
1
X
0
0
default
P1.6/PM_UCA0CLK/COM4
6
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
COM4
X
I: 0; O: 1
X
X
0
1
X
X
1
0
0
P1.7 (I/O)
UCB0CLK
default
P1.7/PM_UCB0CLK/COM5
(1) X = Don't care
7
Output driver and input Schmitt
trigger disabled
X
X
1
= 31
X
0
1
COM5
X
表 6-21. Port P2 (P2.0 and P2.1) Pin Functions (MSP430F67xxAIPZ Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
COM6, COM7
Enable Signal
P2DIR.x
P2SEL.x
P2MAPx
P2.0 (I/O)
I: 0; O: 1
X
0
1
X
0
0
UCB0SOMI/UCB0SCL
default
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
COM6
X
I: 0; O: 1
X
X
0
1
X
X
1
0
0
P2.1 (I/O)
UCB0SIMO/UCB0SDA
default
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7
1
Output driver and input Schmitt
trigger disabled
X
X
1
= 31
X
0
1
COM7
X
(1) X = Don't care
96
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
6.12.5 Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
图 6-6 shows the port diagram. 表 6-22 summarizes the selection of the pin functions.
Pad Logic
P2REN.x
P2MAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
1
P2DIR.x
0
1
Direction
0: Input
1: Output
from Port Mapping
P2OUT.x
0
1
from Port Mapping
P2.2/PM_UCA2RXD/PM_UCA2SOMI
P2.3/PM_UCA2TXD/PM_UCA2SIMO
P2.4/PM_UCA1CLK
P2.5/PM_UCA2CLK
P2.6/PM_TA1.0
P2.7/PM_TA1.1
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
Bus
Keeper
EN
D
to Port Mapping
P2IRQ.x
P2IE.x
EN
Set
Q
P2IFG.x
P2SEL.x
P2IES.x
Interrupt
Edge
Select
图 6-6. Port P2 (P2.2 to P2.7) Diagram (MSP430F67xxAIPZ Only)
版权 © 2015–2018, Texas Instruments Incorporated
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
表 6-22. Port P2 (P2.2 to P2.7) Pin Functions (MSP430F67xxAIPZ Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL.x
P2MAPx
X
P2.2 (I/O)
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
0
1
1
1
P2.2/PM_UCA2RXD/
PM_UCA2SOMI
2
3
4
5
UCA2RXD/UCA2SOMI
X
default
= 31
X
Output driver and input Schmitt trigger disabled
X
P2.3 (I/O)
I: 0; O: 1
P2.3/PM_UCA2TXD/
PM_UCA2SIMO
UCA2TXD/UCA2SIMO
X
default
= 31
X
Output driver and input Schmitt trigger disabled
X
P2.4 (I/O)
I: 0; O: 1
P2.4/PM_UCA1CLK
P2.5/PM_UCA2CLK
UCA1CLK
X
default
= 31
X
Output driver and input Schmitt trigger disabled
X
P2.5 (I/O)
I: 0; O: 1
UCA2CLK
X
default
= 31
X
Output driver and input Schmitt trigger disabled
X
P2.6 (I/O)
I: 0; O: 1
TA1.CC10A
0
default
default
= 31
X
P2.6/PM_TA1.0
6
7
TA1.TA0
1
Output driver and input Schmitt trigger disabled
X
P2.7 (I/O)
I: 0; O: 1
TA1.CCI1A
0
1
X
default
default
= 31
P2.7/PM_TA1.1
TA1.TA1
Output driver and input Schmitt trigger disabled
(1) X = Don't care
98
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
6.12.6 Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
图 6-7 shows the port diagram. 表 6-23 summarizes the selection of the pin functions.
Pad Logic
P3REN.x
P3MAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
1
P3DIR.x
0
1
Direction
0: Input
1: Output
from Port Mapping
P3OUT.x
0
1
from Port Mapping
P3.0/PM_TA2.0
P3.1/PM_TA2.1
P3.2/PM_TACLK/PM_RTCCLK
P3.3/PM_TA0.2
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
Bus
Keeper
EN
D
to Port Mapping
图 6-7. Port P3 (P3.0 to P3.3) Diagram (MSP430F67xxAIPZ Only)
表 6-23. Port P3 (P3.0 to P3.3) Pin Functions (MSP430F67xxAIPZ Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x
P3SEL.x
P3MAPx
P3.0 (I/O)
TA2.CC10A
TA2.TA0
I: 0; O: 1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
X
0
default
default
= 31
P3.0/PM_TA2.0
0
1
Output driver and input Schmitt trigger disabled
X
P3.1 (I/O)
I: 0; O: 1
X
TA2.CCI1A
0
default
default
= 31
P3.1/PM_TA2.1
1
2
3
TA2.TA1
1
Output driver and input Schmitt trigger disabled
X
P3.2 (I/O)
I: 0; O: 1
X
TACLK
0
default
default
= 31
P3.2/PM_TACLK/
PM_RTCCLK
RTCCLK
1
Output driver and input Schmitt trigger disabled
X
P3.3 (I/O)
I: 0; O: 1
X
TA0.CCI2A
0
1
X
default
default
= 31
P3.3/PM_TA0.2
TA0.TA2
Output driver and input Schmitt trigger disabled
(1) X = Don't care
版权 © 2015–2018, Texas Instruments Incorporated
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
6.12.7 Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
图 6-8 shows the port diagram. 表 6-24 summarizes the selection of the pin functions.
S39 to S37
LCDS39 to LCDS37
Pad Logic
P3REN.x
P3MAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
1
P3DIR.x
0
1
Direction
0: Input
1: Output
from Port Mapping
P3OUT.x
0
1
from Port Mapping
P3.4/PM_SDCLK/S39
P3.5/PM_SD0DIO/S38
P3.6/PM_SD1DIO/S37
P3.7/PM_SD2DIO/S36
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
Bus
Keeper
EN
D
to Port Mapping
图 6-8. Port P3 (P3.4 to P3.7) Diagram (MSP430F67xxAIPZ Only)
100
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
表 6-24. Port P3 (P3.4 to P3.7) Pin Functions (MSP430F67xxAIPZ Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P3.x)
x
FUNCTION
LCDS39...
LCDS36
P3DIR.x
P3SEL.x
P3MAPx
P3.4 (I/O)
SDCLK
I: 0; O: 1
X
0
1
X
0
0
default
P3.4/PM_SDCLK/S39
P3.5/PM_SD0DIO/S38
P3.6/PM_SD1DIO/S37
4
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S39
X
I: 0; O: 1
X
X
0
1
X
X
1
0
0
P3.5 (I/O)
SD0DIO
default
5
6
7
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S38
X
I: 0; O: 1
X
X
0
1
X
X
1
0
0
P3.6 (I/O)
SD1DIO
default
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S37
X
I: 0; O: 1
X
X
0
1
X
X
1
0
0
P3.7 (I/O)
SD2DIO
default
P3.7/PM_SD2DIO/S36
(1) X = Don't care
Output driver and input Schmitt
trigger disabled
X
X
1
= 31
X
0
1
S36
X
版权 © 2015–2018, Texas Instruments Incorporated
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
6.12.8 Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7), Port P7 (P7.0 to
P7.7), Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
图 6-9 shows the port diagram. 表 6-25 through 表 6-29 summarize the selection of the pin functions.
Sz
LCDSz
Pad Logic
PyREN.x
DVSS
DVCC
0
1
1
PyDIR.x
0
1
Direction
0: Input
1: Output
PyOUT.x
DVSS
0
1
Py.x/Sz
PyDS.x
0: Low drive
1: High drive
PySEL.x
PyIN.x
Bus
Keeper
EN
D
Not Used
图 6-9. Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7), Port P7 (P7.0 to P7.7), Port P8
(P8.0 to P8.3) Diagram (MSP430F67xxAIPZ Only)
102
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
表 6-25. Port P4 (P4.0 to P4.7) Pin Functions (MSP430F67xxAIPZ Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P4.x)
x
FUNCTION
LCDS35...
LCDS28
P4DIR.x
P4SEL.x
P4.0 (I/O)
N/A
I: 0; O: 1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
P4.0/S35
P4.1/S34
P4.2/S33
P4.3/S32
P4.4/S31
P4.5/S30
P4.6/S29
0
DVSS
S35
1
X
P4.1 (I/O)
N/A
I: 0; O: 1
0
1
2
3
4
5
6
7
DVSS
S34
1
X
P4.2 (I/O)
N/A
I: 0; O: 1
0
DVSS
S33
1
X
P4.3 (I/O)
N/A
I: 0; O: 1
0
DVSS
S32
1
X
P4.4 (I/O)
N/A
I: 0; O: 1
0
DVSS
S31
1
X
P4.5 (I/O)
N/A
I: 0; O: 1
0
DVSS
S30
1
X
P4.6 (I/O)
N/A
I: 0; O: 1
0
DVSS
S29
1
X
P4.7 (I/O)
N/A
I: 0; O: 1
0
1
X
P4.7/S28
DVSS
S28
(1) X = Don't care
版权 © 2015–2018, Texas Instruments Incorporated
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
表 6-26. Port P5 (P5.0 to P5.7) Pin Functions (MSP430F67xxAIPZ Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
LCDS27...
LCDS20
P5DIR.x
P5SEL.x
P5.0 (I/O)
N/A
I: 0; O: 1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
P5.0/S27
0
1
2
3
4
5
6
7
DVSS
S27
1
X
P5.1 (I/O)
N/A
I: 0; O: 1
0
P5.1/S26
P5.2/S25
P5.3/S24
P5.4/S23
P5.5/S22
P5.6/S21
DVSS
S26
1
X
P5.2 (I/O)
N/A
I: 0; O: 1
0
DVSS
S25
1
X
P5.3 (I/O)
N/A
I: 0; O: 1
0
DVSS
S24
1
X
P5.4 (I/O)
N/A
I: 0; O: 1
0
DVSS
S23
1
X
P5.5 (I/O)
N/A
I: 0; O: 1
0
DVSS
S22
1
X
P5.6 (I/O)
N/A
I: 0; O: 1
0
DVSS
S21
1
X
P5.7 (I/O)
N/A
I: 0; O: 1
0
1
X
P5.7/S20
DVSS
S20
(1) X = Don't care
104
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
表 6-27. Port P6 (P6.0 to P6.7) Pin Functions (MSP430F67xxAIPZ Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P6.x)
x
FUNCTION
LCDS19...
LCDS12
P6DIR.x
P6SEL.x
P6.0 (I/O)
N/A
I: 0; O: 1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
P6.0/S19
P6.1/S18
P6.2/S17
P6.3/S16
P6.4/S15
P6.5/S14
P6.6/S13
0
DVSS
S19
1
X
P6.1 (I/O)
N/A
I: 0; O: 1
0
1
2
3
4
5
6
7
DVSS
S18
1
X
P6.2 (I/O)
N/A
I: 0; O: 1
0
DVSS
S17
1
X
P6.3 (I/O)
N/A
I: 0; O: 1
0
DVSS
S16
1
X
P6.4 (I/O)
N/A
I: 0; O: 1
0
DVSS
S15
1
X
P6.5 (I/O)
N/A
I: 0; O: 1
0
DVSS
S14
1
X
P6.6 (I/O)
N/A
I: 0; O: 1
0
DVSS
S13
1
X
P6.7 (I/O)
N/A
I: 0; O: 1
0
1
X
P6.7/S12
DVSS
S12
(1) X = Don't care
版权 © 2015–2018, Texas Instruments Incorporated
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
表 6-28. Port P7 (P7.0 to P7.7) Pin Functions (MSP430F67xxAIPZ Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P7.x)
x
FUNCTION
LCDS11...
LCDS4
P7DIR.x
P7SEL.x
P7.0 (I/O)
N/A
I: 0; O: 1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
P7.0/S11
0
1
2
3
4
5
6
7
DVSS
S11
1
X
P7.1 (I/O)
N/A
I: 0; O: 1
0
P7.1/S10
P7.2/S9
P7.3/S8
P7.4/S7
P7.5/S6
P7.6/S5
DVSS
S10
1
X
P7.2 (I/O)
N/A
I: 0; O: 1
0
DVSS
S9
1
X
P7.3 (I/O)
N/A
I: 0; O: 1
0
DVSS
S8
1
X
P7.4 (I/O)
N/A
I: 0; O: 1
0
DVSS
S7
1
X
P7.5 (I/O)
N/A
I: 0; O: 1
0
DVSS
S6
1
X
P7.6 (I/O)
N/A
I: 0; O: 1
0
DVSS
S5
1
X
P7.7 (I/O)
N/A
I: 0; O: 1
0
1
X
P7.7/S4
DVSS
S4
(1) X = Don't care
106
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
表 6-29. Port P8 (P8.0 to P8.3) Pin Functions (MSP430F67xxAIPZ Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P8.x)
x
FUNCTION
LCDS3...
LCDS0
P8DIR.x
P8SEL.x
P8.0 (I/O)
N/A
I: 0; O: 1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
P8.0/S3
P8.1/S2
P8.2/S1
0
DVSS
S3
1
X
P8.1 (I/O)
N/A
I: 0; O: 1
0
1
2
3
DVSS
S2
1
X
P8.2 (I/O)
N/A
I: 0; O: 1
0
DVSS
S1
1
X
P8.3 (I/O)
N/A
I: 0; O: 1
0
1
X
P8.3/S0
DVSS
S0
(1) X = Don't care
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
6.12.9 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
图 6-10 shows the port diagram. 表 6-30 summarizes the selection of the pin functions.
Pad Logic
P8REN.x
DVSS
DVCC
0
1
1
P8DIR.x
0
1
Direction
0: Input
1: Output
P8OUT.x
0
1
Module X OUT
P8.4/TA1.0
P8.5/TA1.1
P8.6/TA2.0
P8.7/TA2.1
P8DS.x
0: Low drive
1: High drive
P8SEL.x
P8IN.x
EN
D
Module X IN
图 6-10. Port P8 (P8.4 to P8.7) Diagram (MSP430F67xxAIPZ Only)
表 6-30. Port P8 (P8.4 to P8.7) Pin Functions (MSP430F67xxAIPZ Only)
CONTROL BITS OR SIGNALS
PIN NAME (P8.x)
x
FUNCTION
P8DIR.x
P8SEL.x
P8.4 (I/O)
TA1.CCI0A
TA1.TA0
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
P8.4/TA1.0
4
0
1
P8.5 (I/O)
TA1.CCI1A
TA1.TA1
I: 0; O: 1
P8.5/TA1.1
P8.6/TA2.0
P8.7/TA2.1
5
6
7
0
1
P8.6 (I/O)
TA2.CCI0A
TA2.TA0
I: 0; O: 1
0
1
P8.7 (I/O)
TA2.CCI1A
TA2.TA1
I: 0; O: 1
0
1
108
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
6.12.10 Port P9 (P9.0) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
图 6-11 shows the port diagram. 表 6-31 summarizes the selection of the pin functions.
Pad Logic
P9REN.x
DVSS
DVCC
0
1
1
P9DIR.x
0
1
Direction
0: Input
1: Output
P9OUT.x
0
1
Module X OUT
P9.0/TACLK/RTCCLK
P9DS.x
0: Low drive
1: High drive
P9SEL.x
P9IN.x
EN
D
Module X IN
图 6-11. Port P9 (P9.0) Diagram (MSP430F67xxAIPZ Only)
表 6-31. Port P9 (P9.0) Pin Functions (MSP430F67xxAIPZ Only)
CONTROL BITS OR SIGNALS
PIN NAME (P9.x)
x
FUNCTION
P9DIR.x
P9SEL.x
P9.0 (I/O)
TACLK
I: 0; O: 1
0
1
1
P9.0/TACLK/RTCCLK
0
0
1
RTCCLK
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
6.12.11 Port P9 (P9.1 to P9.3) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
图 6-12 shows the port diagram. 表 6-32 summarizes the selection of the pin functions.
Pad Logic
To ADC10
INCHx = y
P9REN.x
DVSS
DVCC
0
1
1
P9DIR.x
P9OUT.x
P9.1/A5
P9.2/A4
P9.3/A3
P9DS.x
0: Low drive
1: High drive
P9SEL.x
P9IN.x
Bus
Keeper
图 6-12. Port P9 (P9.1 to P9.3) Diagram (MSP430F67xxAIPZ Only)
表 6-32. Port P9 (P9.1 to P9.3) Pin Functions (MSP430F67xxAIPZ Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P9.x)
x
1
2
3
FUNCTION
P9DIR.x
I: 0; O: 1
X
P9SEL.x
P9.1 (I/O)
A5(2)
0
1
0
1
0
1
P9.1/A5
P9.2 (I/O)
A4(2)
I: 0; O: 1
X
P9.2/A4
P9.3 (I/O)
A3(2)
I: 0; O: 1
X
P9.3/A3
(1) X = Don't care
(2) Setting P9SEL.x bit disables the output driver and the input Schmitt trigger.
110
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
6.12.12 Port P2 (P2.0 and P2.1) Input/Output With Schmitt Trigger (MSP430F67xxAIPN Only)
图 6-13 shows the port diagram. 表 6-33 summarizes the selection of the pin functions.
S39, S38
LCDS39, LCDS38
COM6, COM7
from LCD_C
Pad Logic
P2REN.x
P2MAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
1
P2DIR.x
0
1
Direction
0: Input
1: Output
from Port Mapping
P2OUT.x
0
1
from Port Mapping
P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6/S39
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7/S38
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
Bus
Keeper
EN
D
to Port Mapping
P2IRQ.x
P2IE.x
EN
Set
Q
P2IFG.x
P2SEL.x
P2IES.x
Interrupt
Edge
Select
图 6-13. Port P2 (P2.0 and P2.1) Diagram (MSP430F67xxAIPN Only)
版权 © 2015–2018, Texas Instruments Incorporated
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
表 6-33. Port P2 (P2.0 and P2.1) Pin Functions (MSP430F67xxAIPN Only)
CONTROL BITS OR SIGNALS(1)
COM6,
COM7
Enable
Signal
PIN NAME (P2.x)
x
FUNCTION
LCDS39,
LCDS38
P2DIR.x
P2SEL.x
P2MAPx
P2.0 (I/O)
I: 0; O: 1
X
0
1
X
0
0
0
0
UCB0SOMI/UCB0SCL
default
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6/
S39
Output driver and input
Schmitt trigger disabled
0
X
1
= 31
0
0
COM6
X
X
X
0
1
X
X
X
1
0
0
1
0
0
0
S39
X
I: 0; O: 1
X
P2.1 (I/O)
X
UCB0SIMO/UCB0SDA
default
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7/
S38
Output driver and input
Schmitt trigger disabled
1
X
1
= 31
0
0
COM7
S38
X
X
X
X
X
X
X
1
1
0
(1) X = Don't care
112
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
6.12.13 Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPN Only)
图 6-14 shows the port diagram. 表 6-34 summarizes the selection of the pin functions.
S37...S32
LCDS37...LCDS32
Pad Logic
P2REN.x
P2MAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
1
P2DIR.x
0
1
Direction
0: Input
1: Output
from Port Mapping
P2OUT.x
0
1
from Port Mapping
P2.2/PM_UCA2RXD/PM_UCA2SOMI/S37
P2.3/PM_UCA2TXD/PM_UCA2SIMO/S36
P2.4/PM_UCA1CLK/S35
P2.5/PM_UCA2CLK/S34
P2.6/PM_TA1.0/S33
P2.7/PM_TA1.1/S32
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
Bus
Keeper
EN
D
to Port Mapping
P2IRQ.x
P2IE.x
EN
Set
Q
P2IFG.x
P2SEL.x
P2IES.x
Interrupt
Edge
Select
图 6-14. Port P2 (P2.2 to P2.7) Diagram (MSP430F67xxAIPN Only)
版权 © 2015–2018, Texas Instruments Incorporated
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
表 6-34. Port P2 (P2.2 to P2.7) Pin Functions (MSP430F67xxAIPN Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
LCDS37...
LCDS32
P2DIR.x
P2SEL.x
P2MAPx
P2.2 (I/O)
I: 0; O: 1
X
0
1
X
0
0
UCA2RXD/UCA2SOMI
default
P2.2/PM_UCA2RXD/
PM_UCA2SOMI/S37
2
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S37
X
I: 0; O: 1
X
X
0
1
X
X
1
0
0
P2.3 (I/O)
UCA2TXD/UCA2SIMO
default
P2.3/PM_UCA2TXD/
PM_UCA2SIMO/S36
3
4
5
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S36
X
I: 0; O: 1
X
X
0
1
X
X
1
0
0
P2.4 (I/O)
UCA1CLK
default
P2.4/PM_UCA1CLK/S35
P2.5/PM_UCA2CLK/S34
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S35
X
I: 0; O: 1
X
X
0
1
X
X
1
0
0
P2.5 (I/O)
UCA2CLK
default
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S34
X
X
0
1
1
X
1
0
0
0
P2.6 (I/O)
TA1.CCI0A
TA1.TA0
I: 0; O: 1
X
0
1
default
default
P2.6/PM_TA1.0/S33
6
7
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S33
X
X
0
1
1
X
1
0
0
0
P2.7 (I/O)
TA1.CCI1A
TA1.TA1
I: 0; O: 1
X
0
1
default
default
P2.7/PM_TA1.1/S32
(1) X = Don't care
Output driver and input Schmitt
trigger disabled
X
X
1
= 31
X
0
1
S32
X
114
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
6.12.14 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPN Only)
图 6-15 shows the port diagram. 表 6-35 summarizes the selection of the pin functions.
S31 to S24
LCDS31 to LCDS24
Pad Logic
P3REN.x
P3MAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
1
P3DIR.x
0
1
Direction
0: Input
1: Output
from Port Mapping
P3OUT.x
0
1
from Port Mapping
P3.0/PM_TA2.0/S31
P3.1/PM_TA2.1/S30
P3.2/PM_TACLK/PM_RTCCLK/S29
P3.3/PM_TA0.2/S28
P3.4/PM_SDCLK/S27
P3.5/PM_SD0DIO/S26
P3.6/PM_SD1DIO/S25
P3.7/PM_SD2DIO/S24
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
Bus
Keeper
EN
D
to Port Mapping
图 6-15. Port P3 (P3.0 to P3.7) Diagram (MSP430F67xxAIPN Only)
版权 © 2015–2018, Texas Instruments Incorporated
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
表 6-35. Port P3 (P3.0 to P3.7) Pin Functions (MSP430F67xxAIPN Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P3.x)
x
FUNCTION
LCDS31...
LCDS24
P3DIR.x
P3SEL.x
P3MAPx
P3.0 (I/O)
I: 0; O: 1
0
1
1
X
0
0
0
TA2.CCI0A
TA2.TA0
0
1
default
default
P3.0/PM_TA2.0/S31
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S31
X
X
0
1
1
X
1
0
0
0
P3.1 (I/O)
TA2.CCI1A
TA2.TA1
I: 0; O: 1
X
0
1
default
default
P3.1/PM_TA2.1/S30
1
2
3
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S30
X
X
0
1
1
X
1
0
0
0
P3.2 (I/O)
TACLK
RTCCLK
I: 0; O: 1
X
0
1
default
default
P3.2/PM_TACLK/
PM_RTCCLK/S29
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S29
X
X
0
1
1
X
1
0
0
0
P3.3 (I/O)
TA0.CCI2A
TA0.TA2
I: 0; O: 1
X
0
1
default
default
P3.3/PM_TA0.2/S28
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S28
X
I: 0; O: 1
X
X
0
1
X
X
1
0
0
P3.4 (I/O)
SDCLK
default
P3.4/PM_SDCLK/S27
P3.5/PM_SD0DIO/S26
P3.6/PM_SD1DIO/S25
4
5
6
7
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S27
X
I: 0; O: 1
X
X
0
1
X
X
1
0
0
P3.5 (I/O)
SD0DIO
default
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S26
X
I: 0; O: 1
X
X
0
1
X
X
1
0
0
P3.6 (I/O)
SD1DIO
default
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S25
X
I: 0; O: 1
X
X
0
1
X
X
1
0
0
P3.7 (I/O)
SD2DIO
default
P3.7/PM_SD2DIO/S24
(1) X = Don't care
Output driver and input Schmitt
trigger disabled
X
X
1
= 31
X
0
1
S24
X
116
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
6.12.15 Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7) Input/Output
With Schmitt Trigger (MSP430F67xxAIPN Only)
图 6-16 shows the port diagram. 表 6-36 through 表 6-38 summarize the selection of the pin functions.
Sz
LCDSz
Pad Logic
PyREN.x
DVSS
DVCC
0
1
1
PyDIR.x
0
1
Direction
0: Input
1: Output
PyOUT.x
DVSS
0
1
Py.x/Sz
PyDS.x
0: Low drive
1: High drive
PySEL.x
PyIN.x
Bus
Keeper
EN
D
Not Used
图 6-16. Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7) Diagram (MSP430F67xxAIPN
Only)
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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表 6-36. Port P4 (P4.0 to P4.7) Pin Functions (MSP430F67xxAIPN Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P4.x)
x
FUNCTION
LCDS23...
LCDS16
P4DIR.x
P4SEL.x
P4.0 (I/O)
N/A
I: 0; O: 1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
P4.0/S23
0
1
2
3
4
5
6
7
DVSS
S23
1
X
P4.1 (I/O)
N/A
I: 0; O: 1
0
P4.1/S22
P4.2/S21
P4.3/S20
P4.4/S19
P4.5/S18
P4.6/S17
DVSS
S22
1
X
P4.2 (I/O)
N/A
I: 0; O: 1
0
DVSS
S21
1
X
P4.3 (I/O)
N/A
I: 0; O: 1
0
DVSS
S20
1
X
P4.4 (I/O)
N/A
I: 0; O: 1
0
DVSS
S19
1
X
P4.5 (I/O)
N/A
I: 0; O: 1
0
DVSS
S18
1
X
P4.6 (I/O)
N/A
I: 0; O: 1
0
DVSS
S17
1
X
P4.7 (I/O)
N/A
I: 0; O: 1
0
1
X
P4.7/S16
DVSS
S16
(1) X = Don't care
118
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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表 6-37. Port P5 (P5.0 to P5.7) Pin Functions (MSP430F67xxAIPN Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
LCDS15...
LCDS8
P5DIR.x
P5SEL.x
P5.0 (I/O)
N/A
I: 0; O: 1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
P5.0/S15
P5.1/S14
P5.2/S13
P5.3/S12
P5.4/S11
P5.5/S10
P5.6/S9
0
DVSS
S15
1
X
P5.1 (I/O)
N/A
I: 0; O: 1
0
1
2
3
4
5
6
7
DVSS
S14
1
X
P5.2 (I/O)
N/A
I: 0; O: 1
0
DVSS
S13
1
X
P5.3 (I/O)
N/A
I: 0; O: 1
0
DVSS
S12
1
X
P5.4 (I/O)
N/A
I: 0; O: 1
0
DVSS
S11
1
X
P5.5 (I/O)
N/A
I: 0; O: 1
0
DVSS
S10
1
X
P5.6 (I/O)
N/A
I: 0; O: 1
0
DVSS
S9
1
X
P5.7 (I/O)
N/A
I: 0; O: 1
0
1
X
P5.7/S8
DVSS
S8
(1) X = Don't care
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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表 6-38. Port P6 (P6.0 to P6.7) Pin Functions (MSP430F67xxAIPN Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P6.x)
x
FUNCTION
LCDS7...
LCDS0
P6DIR.x
P6SEL.x
P6.0 (I/O)
N/A
I: 0; O: 1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
P6.0/S7
0
1
2
3
4
5
6
7
DVSS
S7
1
X
P6.1 (I/O)
N/A
I: 0; O: 1
0
P6.1/S6
P6.2/S5
P6.3/S4
P6.4/S3
P6.5/S2
P6.6/S1
DVSS
S6
1
X
P6.2 (I/O)
N/A
I: 0; O: 1
0
DVSS
S5
1
X
P6.3 (I/O)
N/A
I: 0; O: 1
0
DVSS
S4
1
X
P6.4 (I/O)
N/A
I: 0; O: 1
0
DVSS
S3
1
X
P6.5 (I/O)
N/A
I: 0; O: 1
0
DVSS
S2
1
X
P6.6 (I/O)
N/A
I: 0; O: 1
0
DVSS
S1
1
X
P6.7 (I/O)
N/A
I: 0; O: 1
0
1
X
P6.7/S0
DVSS
S0
(1) X = Don't care
120
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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6.12.16 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
图 6-17 shows the port diagram. 表 6-39 summarizes the selection of the pin functions.
Pad Logic
PJREN.x
0
1
DVSS
DVCC
1
PJDIR.x
DVCC
0
1
PJOUT.x
00
01
10
11
From JTAG
SMCLK
PJ.0/SMCLK/TDO
PJDS.0
0: Low drive
1: High drive
PJSEL.x
From JTAG
PJIN.x
Bus
Holder
EN
D
图 6-17. Port PJ (PJ.0) Diagram
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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6.12.17 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt
Trigger or Output
图 6-18 shows the port diagram. 表 6-39 summarizes the selection of the pin functions.
Pad Logic
PJREN.x
DVSS
DVCC
0
1
1
PJDIR.x
DVSS
0
1
PJOUT.x
00
From JTAG
01
10
11
PJ.1/MCLK/TDI/TCLK
PJ.2/ADC10CLK/TMS
PJ.3/ACLK/TCK
PJDS.x
0: Low drive
1: High drive
MCLK/ADC10CLK/ACLK
PJSEL.x
From JTAG
PJIN.x
Bus
Holder
EN
D
To JTAG
图 6-18. Port PJ (PJ.1 to PJ.3) Diagram
表 6-39. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS OR SIGNALS(1)
JTAG
PIN NAME (PJ.x)
x
FUNCTION
PJDIR.x
PJSEL.x
Mode
Signal
PJ.0 (I/O)(2)
SMCLK
TDO(3)
I: 0; O: 1
0
1
X
0
1
X
0
1
X
0
1
X
0
0
1
0
0
1
0
0
1
0
0
1
PJ.0/SMCLK/TDO
PJ.1/MCLK/TDI/TCLK
PJ.2/ADC10CLK/TMS
PJ.3/ACLK/TCK
0
1
2
3
1
X
PJ.1 (I/O)(2)
I: 0; O: 1
MCLK
1
(3) (4)
TDI/TCLK
X
PJ.2 (I/O)(2)
I: 0; O: 1
ADC10CLK
1
(3) (4)
TMS
X
PJ.3 (I/O)(2)
I: 0; O: 1
ACLK
1
(3) (4)
TCK
X
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
122
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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6.13 Device Descriptors (TLV)
表 6-40 and 表 6-41 list the complete contents of the device descriptor tag-length-value (TLV) structure for
each device type.
表 6-40. MSP430F673xA Device Descriptors
VALUE
SIZE
(bytes)
DESCRIPTION
Info length
ADDRESS
F6736A
06h
F6735A
06h
F6734A
06h
F6733A
06h
F6731A
06h
F6730A
06h
01A00h
01A01h
01A02h
01A04h
01A05h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Eh
01A10h
01A12h
01A14h
01A15h
01A16h
01A18h
1
1
2
1
1
1
1
1
1
4
2
2
2
1
1
2
2
CRC length
CRC value
06h
06h
06h
06h
06h
06h
Per unit
86h
Per unit
85h
Per unit
84h
Per unit
83h
Per unit
81h
Per unit
80h
Info Block
Device ID
Device ID
82h
82h
82h
82h
82h
82h
Hardware revision
Firmware revision
Die record tag
Die record length
Lot/wafer ID
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Die Record
Die X position
Die Y position
Test results
ADC10 calibration tag
ADC10 calibration length
ADC gain factor
ADC offset
10h
10h
10h
10h
10h
10h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 30°C
01A1Ah
01A1Ch
01A1Eh
01A20h
01A22h
01A24h
2
2
2
2
2
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 85°C
ADC10
Calibration
ADC 2.0-V reference
Temperature sensor 30°C
ADC 2.0-V reference
Temperature sensor 85°C
ADC 2.5-V reference
Temperature sensor 30°C
ADC 2.5-V reference
Temperature sensor 85°C
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
表 6-41. MSP430F672xA Device Descriptors
VALUE
F6724A
SIZE
(bytes)
DESCRIPTION
Info length
ADDRESS
F6726A
06h
F6725A
06h
F6723A
06h
F6721A
06h
F6720A
06h
01A00h
01A01h
01A02h
01A04h
01A05h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Eh
01A10h
01A12h
01A14h
01A15h
01A16h
01A18h
1
1
2
1
1
1
1
1
1
4
2
2
2
1
1
2
2
06h
06h
CRC length
CRC value
06h
06h
06h
06h
06h
Per unit
7Ch
Per unit
7Bh
Per unit
7Ah
Per unit
79h
Per unit
77h
Per unit
76h
Info Block
Device ID
Device ID
82h
82h
82h
82h
82h
82h
Hardware revision
Firmware revision
Die record tag
Die record length
Lot/wafer ID
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Die Record
Die X position
Die Y position
Test results
ADC10 calibration tag
ADC10 calibration length
ADC gain factor
ADC offset
10h
10h
10h
10h
10h
10h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 30°C
01A1Ah
01A1Ch
01A1Eh
01A20h
01A22h
01A24h
2
2
2
2
2
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 85°C
ADC10
Calibration
ADC 2.0-V reference
Temperature sensor 30°C
ADC 2.0-V reference
Temperature sensor 85°C
ADC 2.5-V reference
Temperature sensor 30°C
ADC 2.5-V reference
Temperature sensor 85°C
124
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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6.14 Memory
6.14.1 Memory Organization
表 6-42 and 表 6-43 summarize the memory map for all device variants.
表 6-42. Memory Organization
MSP430F6730A
MSP430F6720A
MSP430F6731A
MSP430F6721A
MSP430F6733A
MSP430F6723A
Main Memory
(flash)
Total Size
16KB
32KB
64KB
Main: Interrupt
vector
00FFFFh–00FF80h
00FFFFh–00FF80h
00FFFFh–00FF80h
Main: code
memory
Bank 3
Bank 2
Bank 1
Not available
Not available
Not available
Not available
Not available
Not available
Not available
16KB
00FFFFh–00C000h
32KB
013FFFh–00C000h
16KB
00FFFFh–00C000h
16KB
00BFFFh–008000h
32KB
00BFFFh–004000h
Bank 0
RAM
Total Size
Sector 3
Sector 2
1KB
2KB
4KB
Not available
Not available
Not available
Not available
Not available
Not available
2KB
Sector 1
Sector 0
Info A
Not available
Not available
002BFFh–002400h
1KB
2KB
2KB
001FFFh–001C00h
0023FFh–001C00h
0023FFh–001C00h
128 B
0019FFh–001980h
128 B
0019FFh–001980h
128 B
0019FFh–001980h
128 B
00197Fh–001900h
128 B
00197Fh–001900h
128 B
00197Fh–001900h
Info B
Information
memory (flash)
128 B
0018FFh–001880h
128 B
0018FFh–001880h
128 B
0018FFh–001880h
Info C
Info D
BSL 3
BSL 2
BSL 1
BSL 0
128 B
00187Fh–001800h
128 B
00187Fh–001800h
128 B
00187Fh–001800h
512 B
0017FFh–001600h
512 B
0017FFh–001600h
512 B
0017FFh–001600h
512 B
0015FFh–001400h
512 B
0015FFh–001400h
512 B
0015FFh–001400h
Bootloader (BSL)
memory (flash)
512 B
0013FFh–001200h
512 B
0013FFh–001200h
512 B
0013FFh–001200h
512 B
0011FFh–001000h
512 B
0011FFh–001000h
512 B
0011FFh–001000h
4 KB
000FFFh–0h
4 KB
000FFFh–0h
4 KB
000FFFh–0h
Peripherals
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
表 6-43. Memory Organization
MSP430F6734A
MSP430F6724A
MSP430F6735A
MSP430F6725A
MSP430F6736A
MSP430F6726A
Total
Size
Main Memory (flash)
Main: Interrupt vector
Main: code memory
96KB
128KB
128KB
00FFFFh–00FF80h
Not available
00FFFFh–00FF80h
00FFFFh–00FF80h
32KB
023FFFh–01C000h
32KB
023FFFh–01C000h
Bank 3
Bank 2
Bank 1
Bank 0
32KB
01BFFFh–014000h
32KB
01BFFFh–014000h
32KB
01BFFFh–014000h
32KB
013FFFh–00C000h
32KB
013FFFh–00C000h
32KB
013FFFh–00C000h
32KB
00BFFFh–004000h
32KB
00BFFFh–004000h
32KB
00BFFFh–004000h
Total
Size
RAM
4KB
4KB
8KB
2KB
Sector 3
Sector 2
Sector 1
Sector 0
Info A
Not available
Not available
Not available
Not available
003BFFh–003400h
2KB
0033FFh–002C00h
2KB
2KB
2KB
002BFFh–002400h
002BFFh–002400h
002BFFh–002400h
2KB
2KB
2KB
0023FFh–001C00h
0023FFh–001C00h
0023FFh–001C00h
128 B
0019FFh–001980h
128 B
0019FFh–001980h
128 B
0019FFh–001980h
128 B
00197Fh–001900h
128 B
00197Fh–001900h
128 B
00197Fh–001900h
Info B
Information memory
(flash)
128 B
0018FFh–001880h
128 B
0018FFh–001880h
128 B
0018FFh–001880h
Info C
128 B
00187Fh–001800h
128 B
00187Fh–001800h
128 B
00187Fh–001800h
Info D
512 B
0017FFh–001600h
512 B
0017FFh–001600h
512 B
0017FFh–001600h
BSL 3
512 B
0015FFh–001400h
512 B
0015FFh–001400h
512 B
0015FFh–001400h
BSL 2
Bootloader (BSL)
memory (flash)
512 B
0013FFh–001200h
512 B
0013FFh–001200h
512 B
0013FFh–001200h
BSL 1
512 B
0011FFh–001000h
512 B
0011FFh–001000h
512 B
0011FFh–001000h
BSL 0
4 KB
000FFFh–0h
4 KB
000FFFh–0h
4 KB
000FFFh–0h
Peripherals
126
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
6.14.2 Peripheral File Map
表 6-44 lists the available modules with the base address and the offset range for each. 表 6-45 through
表 6-82 list all of the available registers for each module.
表 6-44. Peripheral File Map
OFFSET ADDRESS
MODULE NAME
BASE ADDRESS
RANGE
Special Functions (see 表 6-45)
PMM (see 表 6-46)
0100h
0120h
0140h
0150h
0158h
015Ch
0160h
0180h
01B0h
01C0h
01C8h
01D0h
01D8h
0200h
0220h
0240h
000h–01Fh
000h–01Fh
000h–00Fh
000h–007h
000h–001h
000h–001h
000h–01Fh
000h–01Fh
000h–001h
000h–007h
000h–007h
000h–007h
000h–007h
000h–01Fh
000h–00Bh
000h–00Bh
Flash Control (see 表 6-47)
CRC16 (see 表 6-48)
RAM Control (see 表 6-49)
Watchdog (see 表 6-50)
UCS (see 表 6-51)
SYS (see 表 6-52)
Shared Reference (see 表 6-53)
Port Mapping Control (see 表 6-54)
Port Mapping Port P1 (see 表 6-55)
Port Mapping Port P2 (see 表 6-56)
Port Mapping Port P3 (see 表 6-57)
Port P1, P2 (see 表 6-58)
Port P3, P4 (see 表 6-59)
Port P5, P6 (see 表 6-60)
Port P7, P8 (see 表 6-61)
(Port P7, P8 not available in MSP430F67xxAIPN)
0260h
000h–00Bh
Port P9 (Port P9 not available in
MSP430F67xxAIPN)
(see 表 6-62)
0280h
000h–00Bh
Port PJ (refer to表 6-63)
Timer TA0 (see 表 6-64)
0320h
0340h
0380h
0400h
0440h
0480h
04A0h
04C0h
0500h
0500h
0500h
0500h
05C0h
05E0h
0600h
0640h
0740h
0800h
09E0h
0A00h
000h–01Fh
000h–03Fh
000h–03Fh
000h–03Fh
000h–03Fh
000h–00Fh
000h–01Fh
000h–02Fh
000h–00Fh
010h–01Fh
020h–02Fh
030h–03Fh
000h–01Fh
000h–01Fh
000h–01Fh
000h–02Fh
000h–01Fh
000h–06Fh
000h–01Fh
000h–05Fh
Timer TA1 (see 表 6-65)
Timer TA2 (see 表 6-66)
Timer TA3 (see 表 6-67)
Backup Memory (see 表 6-68)
RTC_C (see 表 6-69)
32-Bit Hardware Multiplier (see 表 6-70)
DMA General Control (see 表 6-71)
DMA Channel 0 (see 表 6-72)
DMA Channel 1 (see 表 6-73)
DMA Channel 2 (see 表 6-74)
eUSCI_A0 (see 表 6-75)
eUSCI_A1 (see 表 6-76)
eUSCI_A2 (see 表 6-77)
eUSCI_B0 (see 表 6-78)
ADC10_A (see 表 6-79)
SD24_B (see 表 6-80)
Auxiliary Supply (see 表 6-74)
LCD_C (see 表 6-82)
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
表 6-45. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
SFRIE1
OFFSET
SFR interrupt enable
SFR interrupt flag
00h
02h
04h
SFRIFG1
SFR reset pin control
SFRRPCR
表 6-46. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PMM control 0
PMMCTL0
PMMCTL1
SVSMHCTL
SVSMLCTL
PMMIFG
00h
02h
04h
06h
0Ch
0Eh
10h
PMM control 1
SVS high-side control
SVS low-side control
PMM interrupt flags
PMM interrupt enable
PMM power mode 5 control 0
PMMIE
PM5CTL0
表 6-47. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Flash control 1
Flash control 3
Flash control 4
FCTL1
FCTL3
FCTL4
00h
04h
06h
表 6-48. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
CRC16DI
OFFSET
CRC data input
00h
02h
04h
06h
CRC data input reverse byte
CRC result
CRC16DIRB
CRCINIRES
CRCRESR
CRC result reverse byte
表 6-49. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
REGISTER
RCCTL0
OFFSET
OFFSET
OFFSET
RAM control 0
00h
00h
表 6-50. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
REGISTER
WDTCTL
Watchdog timer control
表 6-51. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
UCS control 0
UCS control 1
UCS control 2
UCS control 3
UCS control 4
UCS control 5
UCS control 6
UCS control 7
UCSCTL0
UCSCTL1
UCSCTL2
UCSCTL3
UCSCTL4
UCSCTL5
UCSCTL6
UCSCTL7
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
128
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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表 6-51. UCS Registers (Base Address: 0160h) (continued)
REGISTER DESCRIPTION
REGISTER
UCSCTL8
OFFSET
OFFSET
UCS control 8
10h
表 6-52. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
System control
SYSCTL
00h
02h
06h
08h
0Ah
0Ch
0Eh
18h
1Ah
1Ch
1Eh
Bootloader configuration area
JTAG mailbox control
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
Bus error vector generator
User NMI vector generator
System NMI vector generator
Reset vector generator
SYSBSLC
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSBERRIV
SYSUNIV
SYSSNIV
SYSRSTIV
表 6-53. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
REGISTER
REFCTL
OFFSET
OFFSET
Shared reference control
00h
表 6-54. Port Mapping Controller (Base Address: 01C0h)
REGISTER DESCRIPTION
REGISTER
PMAPPWD
PMAPCTL
Port mapping password
Port mapping control
00h
02h
表 6-55. Port Mapping for Port P1 (Base Address: 01C8h)
REGISTER DESCRIPTION
REGISTER
P1MAP0
OFFSET
Port P1.0 mapping
Port P1.1 mapping
Port P1.2 mapping
Port P1.3 mapping
Port P1.4 mapping
Port P1.5 mapping
Port P1.6 mapping
Port P1.7 mapping
00h
01h
02h
03h
04h
05h
06h
07h
P1MAP1
P1MAP2
P1MAP3
P1MAP4
P1MAP5
P1MAP6
P1MAP7
表 6-56. Port Mapping for Port P2 (Base Address: 01D0h)
REGISTER DESCRIPTION
REGISTER
P2MAP0
OFFSET
Port P2.0 mapping
Port P2.1 mapping
Port P2.2 mapping
Port P2.3 mapping
Port P2.4 mapping
Port P2.5 mapping
Port P2.6 mapping
Port P2.7 mapping
00h
01h
02h
03h
04h
05h
06h
07h
P2MAP2
P2MAP2
P2MAP3
P2MAP4
P2MAP5
P2MAP6
P2MAP7
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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表 6-57. Port Mapping for Port P3 (Base Address: 01D8h)
REGISTER DESCRIPTION
REGISTER
P3MAP0
OFFSET
Port P3.0 mapping
Port P3.1 mapping
Port P3.2 mapping
Port P3.3 mapping
Port P3.4 mapping
Port P3.5 mapping
Port P3.6 mapping
Port P3.7 mapping
00h
01h
02h
03h
04h
05h
06h
07h
P3MAP3
P3MAP2
P3MAP3
P3MAP4
P3MAP5
P3MAP6
P3MAP7
表 6-58. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
02h
04h
06h
08h
0Ah
0Eh
18h
1Ah
1Ch
01h
03h
05h
07h
09h
0Bh
1Eh
19h
1Bh
1Dh
Port P1 output
P1OUT
P1DIR
P1REN
P1DS
P1SEL
P1IV
Port P1 direction
Port P1 resistor enable
Port P1 drive strength
Port P1 selection
Port P1 interrupt vector word
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
P1IES
P1IE
P1IFG
P2IN
Port P2 output
P2OUT
P2DIR
P2REN
P2DS
P2SEL
P2IV
Port P2 direction
Port P2 resistor enable
Port P2 drive strength
Port P2 selection
Port P2 interrupt vector word
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
P2IES
P2IE
P2IFG
表 6-59. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
02h
04h
06h
08h
0Ah
01h
03h
05h
07h
09h
0Bh
Port P3 output
P3OUT
P3DIR
P3REN
P3DS
Port P3 direction
Port P3 resistor enable
Port P3 drive strength
Port P3 selection
Port P4 input
P3SEL
P4IN
Port P4 output
P4OUT
P4DIR
P4REN
P4DS
Port P4 direction
Port P4 resistor enable
Port P4 drive strength
Port P4 selection
P4SEL
130
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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表 6-60. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
02h
04h
06h
08h
0Ah
01h
03h
05h
07h
09h
0Bh
Port P5 output
P5OUT
P5DIR
P5REN
P5DS
Port P5 direction
Port P5 resistor enable
Port P5 drive strength
Port P5 selection
Port P6 input
P5SEL
P6IN
Port P6 output
P6OUT
P6DIR
P6REN
P6DS
Port P6 direction
Port P6 resistor enable
Port P6 drive strength
Port P6 selection
P6SEL
表 6-61. Port P7, P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 input
P7IN
00h
02h
04h
06h
08h
0Ah
01h
03h
05h
07h
09h
0Bh
Port P7 output
P7OUT
P7DIR
P7REN
P7DS
Port P7 direction
Port P7 resistor enable
Port P7 drive strength
Port P7 selection
Port P8 input
P7SEL
P8IN
Port P8 output
P8OUT
P8DIR
P8REN
P8DS
Port P8 direction
Port P8 resistor enable
Port P8 drive strength
Port P8 selection
P8SEL
表 6-62. Port P9 Registers (Base Address: 0280h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P9 input
P9IN
00h
02h
04h
06h
08h
0Ah
Port P9 output
P9OUT
P9DIR
P9REN
P9DS
Port P9 direction
Port P9 resistor enable
Port P9 drive strength
Port P9 selection
P9SEL
表 6-63. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
02h
04h
06h
08h
0Ah
Port PJ output
PJOUT
PJDIR
PJREN
PJDS
Port PJ direction
Port PJ resistor enable
Port PJ drive strength
Port PJ selection
PJSEL
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
表 6-64. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0 control
TA0CTL
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA0 counter
TA0CCTL0
TA0CCTL1
TA0CCTL2
TA0R
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA0 expansion 0
TA0CCR0
TA0CCR1
TA0CCR2
TA0EX0
TA0 interrupt vector
TA0IV
表 6-65. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
OFFSET
OFFSET
TA1 control
TA1CTL
TA1CCTL0
TA1CCTL1
TA1R
00h
02h
04h
10h
12h
14h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
TA1 counter
Capture/compare 0
Capture/compare 1
TA1 expansion 0
TA1CCR0
TA1CCR1
TA1EX0
TA1IV
TA1 interrupt vector
表 6-66. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
TA2 control
TA2CTL
TA2CCTL0
TA2CCTL1
TA2R
00h
02h
04h
10h
12h
14h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
TA2 counter
Capture/compare 0
Capture/compare 1
TA2 expansion 0
TA2CCR0
TA2CCR1
TA2EX0
TA2IV
TA2 interrupt vector
表 6-67. TA3 Registers (Base Address: 0440h)
REGISTER DESCRIPTION
REGISTER
TA3 control
TA3CTL
TA3CCTL0
TA3CCTL1
TA3R
00h
02h
04h
10h
12h
14h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
TA3 counter
Capture/compare 0
Capture/compare 1
TA3 expansion 0
TA3CCR0
TA3CCR1
TA3EX0
TA3IV
TA3 interrupt vector
132
Detailed Description
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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表 6-68. Backup Memory Registers (Base Address: 0480h)
REGISTER DESCRIPTION
REGISTER
BAKMEM0
OFFSET
Backup memory 0
Backup memory 1
Backup memory 2
Backup memory 3
00h
02h
04h
06h
BAKMEM1
BAKMEM2
BAKMEM3
表 6-69. RTC_C Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
RTCCTL0
OFFSET
RTC control 0
00h
01h
02h
03h
04h
06h
08h
0Ah
0Ch
0Dh
0Eh
10h
11h
12h
13h
14h
15h
16h
18h
19h
1Ah
1Bh
1Ch
1Eh
RTC password
RTCPWD
RTCCTL1
RTCCTL3
RTCOCAL
RTCTCMP
RTCPS0CTL
RTCPS1CTL
RTCPS0
RTC control 1
RTC control 3
RTC offset calibration
RTC temperature compensation
RTC prescaler 0 control
RTC prescaler 1 control
RTC prescaler 0
RTC prescaler 1
RTC interrupt vector word
RTC seconds
RTCPS1
RTCIV
RTCSEC
RTC minutes
RTCMIN
RTC hours
RTCHOUR
RTCDOW
RTCDAY
RTC day of week
RTC days
RTC month
RTCMON
RTCYEAR
RTCAMIN
RTCAHOUR
RTCADOW
RTCADAY
BIN2BCD
BCD2BIN
RTC year
RTC alarm minutes
RTC alarm hours
RTC alarm day of week
RTC alarm days
Binary-to-BCD conversion
BCD-to-binary conversion
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MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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表 6-70. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
16-bit operand 1 – signed multiply
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
MPYS
MAC
MACS
OP2
16 × 16 result low word
RESLO
RESHI
16 × 16 result high word
16 × 16 sum extension
SUMEXT
MPY32L
MPY32H
MPYS32L
MPYS32H
MAC32L
MAC32H
MACS32L
MACS32H
OP2L
32-bit operand 1 – multiply low word
32-bit operand 1 – multiply high word
32-bit operand 1 – signed multiply low word
32-bit operand 1 – signed multiply high word
32-bit operand 1 – multiply accumulate low word
32-bit operand 1 – multiply accumulate high word
32-bit operand 1 – signed multiply accumulate low word
32-bit operand 1 – signed multiply accumulate high word
32-bit operand 2 – low word
32-bit operand 2 – high word
OP2H
32 × 32 result 0 – least significant word
32 × 32 result 1
RES0
RES1
32 × 32 result 2
RES2
32 × 32 result 3 – most significant word
MPY32 control 0
RES3
MPY32CTL0
表 6-71. DMA General Control Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
DMACTL0
OFFSET
DMA module control 0
DMA module control 1
DMA module control 2
DMA module control 3
DMA module control 4
DMA interrupt vector
00h
02h
04h
06h
08h
0Eh
DMACTL1
DMACTL2
DMACTL3
DMACTL4
DMAIV
表 6-72. DMA Channel 0 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
DMA0CTL
OFFSET
DMA channel 0 control
10h
12h
14h
16h
18h
1Ah
DMA channel 0 source address low
DMA channel 0 source address high
DMA channel 0 destination address low
DMA channel 0 destination address high
DMA channel 0 transfer size
DMA0SAL
DMA0SAH
DMA0DAL
DMA0DAH
DMA0SZ
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MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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表 6-73. DMA Channel 1 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
DMA1CTL
OFFSET
OFFSET
OFFSET
DMA channel 1 control
20h
22h
24h
26h
28h
2Ah
DMA channel 1 source address low
DMA channel 1 source address high
DMA channel 1 destination address low
DMA channel 1 destination address high
DMA channel 1 transfer size
DMA1SAL
DMA1SAH
DMA1DAL
DMA1DAH
DMA1SZ
表 6-74. DMA Channel 2 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
DMA2CTL
DMA channel 2 control
30h
32h
34h
36h
38h
3Ah
DMA channel 2 source address low
DMA channel 2 source address high
DMA channel 2 destination address low
DMA channel 2 destination address high
DMA channel 2 transfer size
DMA2SAL
DMA2SAH
DMA2DAL
DMA2DAH
DMA2SZ
表 6-75. eUSCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
UCA0CTLW0
eUSCI_A control word 0
eUSCI _A control word 1
eUSCI_A baud rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
UCA0CTLW1
UCA0BR0
eUSCI_A baud rate 1
UCA0BR1
eUSCI_A modulation control
eUSCI_A status
UCA0MCTLW
UCA0STAT
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
UCA0IRTCTL
UCA0IRRCTL
UCA0IE
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
UCA0IFG
UCA0IV
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MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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表 6-76. eUSCI_A1 Registers (Base Address:05E0h)
REGISTER DESCRIPTION
REGISTER
UCA1CTLW0
OFFSET
eUSCI_A control word 0
eUSCI _A control word 1
eUSCI_A baud rate 0
eUSCI_A baud rate 1
eUSCI_A modulation control
eUSCI_A status
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
UCA1CTLW1
UCA1BR0
UCA1BR1
UCA1MCTLW
UCA1STAT
UCA1RXBUF
UCA1TXBUF
UCA1ABCTL
UCA1IRTCTL
UCA1IRRCTL
UCA1IE
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
UCA1IFG
eUSCI_A interrupt vector word
UCA1IV
表 6-77. eUSCI_A2 Registers (Base Address:0600h)
REGISTER DESCRIPTION
REGISTER
UCA2CTLW0
OFFSET
eUSCI_A control word 0
eUSCI _A control word 1
eUSCI_A baud rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
UCA2CTLW1
UCA2BR0
eUSCI_A baud rate 1
UCA2BR1
eUSCI_A modulation control
eUSCI_A status
UCA2MCTLW
UCA2STAT
UCA2RXBUF
UCA2TXBUF
UCA2ABCTL
UCA2IRTCTL
UCA2IRRCTL
UCA2IE
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
UCA2IFG
UCA2IV
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MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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表 6-78. eUSCI_B0 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_B control word 0
eUSCI_B control word 1
eUSCI_B bit rate 0
UCB0CTLW0
UCB0CTLW1
UCB0BR0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Ah
2Ch
2Eh
eUSCI_B bit rate 1
UCB0BR1
eUSCI_B status word
UCB0STATW
UCB0TBCNT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA0
UCB0I2COA1
UCB0I2COA2
UCB0I2COA3
UCB0ADDRX
UCB0ADDMASK
UCB0I2CSA
UCB0IE
eUSCI_B byte counter threshold
eUSCI_B receive buffer
eUSCI_B transmit buffer
eUSCI_B I2C own address 0
eUSCI_B I2C own address 1
eUSCI_B I2C own address 2
eUSCI_B I2C own address 3
eUSCI_B received address
eUSCI_B address mask
eUSCI I2C slave address
eUSCI interrupt enable
eUSCI interrupt flags
UCB0IFG
eUSCI interrupt vector word
UCB0IV
表 6-79. ADC10_A Registers (Base Address: 0740h)
REGISTER DESCRIPTION
REGISTER
ADC10CTL0
OFFSET
ADC10_A control 0
00h
02h
04h
06h
08h
0Ah
12h
1Ah
1Ch
1Eh
ADC10_A control 1
ADC10CTL1
ADC10CTL2
ADC10LO
ADC10_A control 2
ADC10_A window comparator low threshold
ADC10_A window comparator high threshold
ADC10_A memory control 0
ADC10_A conversion memory
ADC10_A interrupt enable
ADC10_A interrupt flags
ADC10HI
ADC10MCTL0
ADC10MCTL0
ADC10IE
ADC10IGH
ADC10IV
ADC10_A interrupt vector word
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MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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表 6-80. SD24_B Registers (Base Address: 0800h)
REGISTER DESCRIPTION
REGISTER
SD24BCTL0
OFFSET
SD24_B control 0
00h
02h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
50h
52h
54h
56h
58h
5Ah
SD24_B control 1
SD24BCTL1
SD24BIFG
SD24_B interrupt flag
SD24_B interrupt enable
SD24_B interrupt vector
SD24_B converter 0 control
SD24BIE
SD24BIV
SD24BCCTL0
SD24BINCTL0
SD24BOSR0
SD24BPRE0
SD24BCCTL1
SD24BINCTL1
SD24BOSR1
SD24BPRE1
SD24BCCTL2
SD24BINCTL2
SD24BOSR2
SD24BPRE2
SD24BMEML0
SD24BMEMH0
SD24BMEML1
SD24BMEMH1
SD24BMEML2
SD24BMEMH2
SD24_B converter 0 input control
SD24_B converter 0 OSR control
SD24_B converter 0 preload
SD24_B converter 1 control
SD24_B converter 1 input control
SD24_B converter 1 OSR control
SD24_B converter 1 preload
SD24_B converter 2 control
SD24_B converter 2 input control
SD24_B converter 2 OSR control
SD24_B converter 2 preload
SD24_B converter 0 conversion memory low word
SD24_B converter 0 conversion memory high word
SD24_B converter 1 conversion memory low word
SD24_B converter 1 conversion memory high word
SD24_B converter 2 conversion memory low word
SD24_B converter 2 conversion memory high word
表 6-81. Auxiliary Supplies Registers (Base Address: 09E0h)
REGISTER DESCRIPTION
REGISTER
AUXCTL0
OFFSET
Auxiliary supply control 0
Auxiliary supply control 1
Auxiliary supply control 2
AUX2 charger control
AUX3 charger control
AUX ADC control
00h
02h
04h
12h
14h
16h
1Ah
1Ch
1Eh
AUXCTL1
AUXCTL2
AUX2CHCTL
AUX3CHCTL
AUXADCCTL
AUXIFG
AUX interrupt flag
AUX interrupt enable
AUX interrupt vector word
AUXIE
AUXIV
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MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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表 6-82. LCD_C Registers (Base Address: 0A00h)
REGISTER DESCRIPTION
REGISTER
LCDCCTL0
OFFSET
LCD_C control 0
000h
002h
004h
006h
008h
00Ah
00Ch
00Eh
012h
01Eh
LCD_C control 1
LCDCCTL1
LCDCBLKCTL
LCDCMEMCTL
LCDCVCTL
LCDCPCTL0
LCDCPCTL1
LCDCPCTL2
LCDCCPCTL
LCDCIV
LCD_C blinking control
LCD_C memory control
LCD_C voltage control
LCD_C port control 0
LCD_C port control 1
LCD_C port control 2
LCD_C charge pump control
LCD_C interrupt vector
Static and 2 to 4 mux modes
LCD_C memory 1
LCD_C memory 2
⋮
LCDM1
LCDM2
⋮
020h
021h
⋮
LCD_C memory 20
LCD_C blinking memory 1
LCD_C blinking memory 2
⋮
LCDM20
LCDBM1
LCDBM2
⋮
033h
040h
041h
⋮
LCD_C blinking memory 20
5 to 8 mux modes
LCD_C memory 1
LCD_C memory 2
⋮
LCDBM20
053h
LCDM1
LCDM2
⋮
020h
021h
⋮
LCD_C memory 40
LCDM40
047h
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MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
6.15 Identification
6.15.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings. For links to all of the errata sheets for the devices
in this data sheet, see 节 8.4.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Hardware Revision" entries in 节 6.13.
6.15.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings. For links to all of the errata sheets for the devices in this data
sheet, see 节 8.4.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Device ID" entries in 节 6.13.
6.15.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
detail in the MSP430 Programming With the JTAG Interface.
140
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MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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7 Applications, Implementation, and Layout
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
The following resources provide application guidelines and best practices when designing with the
MSP430F673xA and MSP430F672xA.
Implementation of a Single-Phase Electronic Watt-Hour Meter Using the MSP430F6736(A)
This application report describes the implementation of a single-phase electronic electricity meter using
the Texas Instruments MSP430F673x(A) metering processor. It also includes the necessary information
with regard to metrology software and hardware procedures for this single-chip implementation.
High-Accuracy Single-Phase Electricity Meter With Tamper Detection
This design, featuring the MSP430F6736(A) device, implements a highly-integrated single-chip electricity
metering (e-meter) solution. Hardware and software design files are provided to enable calculation of
various parameters for single phase energy measurement, such as RMS current and voltage, active and
reactive power and energies, power factor, and frequency.
Features
•
•
Low-power single-phase e-metering implementation
Calculate parameters such as RMS current and voltage, active and reactive power and energies,
power factor and frequency
•
•
•
Based on the highly-integrated MSP430F67xx(A) family of metering-focused MCU SoCs
Segment LCD is also implemented in this design
RF modules can also be added to this design to enable unique connectivity solutions.
版权 © 2015–2018, Texas Instruments Incorporated
Applications, Implementation, and Layout
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MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
8 器件和文档支持
8.1 入门和后续步骤
要获得有助于您开发工作的 MSP430™系列器件、工具和库的更多相关信息，请访问 入门 页面。
8.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS.
These prefixes represent evolutionary stages of product development from engineering prototypes (XMS)
through fully qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical
specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production
devices. TI recommends that these devices not be used in any production system because their expected
end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
temperature range, package type, and distribution format. 图 8-1 provides a legend for reading the
complete device name.
142
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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MSP 430 F 5 438 A I ZQW T -EP
Processor Family
MCU Platform
Device Type
Series
Feature Set
Optional: Additional Features
Optional: Tape and Reel
Packaging
Optional: Temperature Range
Optional: A = Revision
Processor Family
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
MCU Platform
Device Type
430 = MSP430 low-power microcontroller platform
Memory Type
C = ROM
Specialized Application
AFE = Analog Front End
BQ = Contactless Power
CG = ROM Medical
F = Flash
FR = FRAM
G = Flash or FRAM (Value Line)
L = No Nonvolatile Memory
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
Series
1 = Up to 8 MHz
5 = Up to 25 MHz
6 = Up to 25 MHz with LCD
0 = Low-Voltage Series
2 = Up to 16 MHz
3 = Legacy
4 = Up to 16 MHz with LCD
Feature Set
Various levels of integration within a series
N/A
Optional: A = Revision
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small reel
R = Large reel
No markings = Tube or tray
Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C)
-HT = Extreme Temperature Parts (–55°C to 150°C)
-Q1 = Automotive Q100 Qualified
图 8-1. Device Nomenclature
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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8.3 工具与软件
所有 MSP 微控制器均受多种软件和硬件开发工具的支持。相关工具由 TI 以及多家第三方供应商提供。请参
阅《MSP430 超低功耗 MCU – 工具与软件》了解所有工具。
表 8-1 列出 了 MSP430F673xA 和 MSP430F672xA MCU 的调试特性。关于可用特性的详细信息，请参见
《适用于 MSP430 的 Code Composer Studio 用户指南 》。
表 8-1. 硬件调试 特性
四线制
JTAG
两线制
JTAG
断点
(N)
状态序列发生
器
LPMx.5 调试支
持
MSP430 架构
范围断点
有
时钟控制
是
跟踪缓冲器
否
MSP430Xv2
有
有
3
否
否
设计套件与评估模块
MSP-TS430PZ100B - 适用于 MSP430F6x MCU 的 100 引脚目标开发板 MSP-TS430PZ100B 是一款独立
的 100 引脚 ZIF 插座目标板，用于通过 JTAG 接口或 Spy-Bi-Wire（两线制 JTAG）协议在系
统内对 MSP430 MCU 进行编程和调试。
适用于 MSP430F6x MCU 的 100 引脚目标开发板和 MSP-FET 编程器捆绑包 MSP-FET 是一款强大的闪
存仿真工具，可在 MSP430 MCU 上快速开始应用开发。它包含 USB 调试接口，用于通过
JTAG 接口或节省引脚的 Spy-Bi-Wire（两线制 JTAG）协议在系统内对 MSP430 进行编程和
调试。
EVM430-F6736 - 用于计量的 MSP430F6736 EVM EVM430-F6736 是一个基于 MSP430F6736 器件的单
相电表评估模块。该电表不仅可连接至主电力线，而且还具备电压和电流输入，以及可用于防
篡改设置的第三连接系统。
软件
MSP430Ware™ 软件 MSP430Ware 软件集合了所有 MSP430 器件的代码示例、数据表以及其他设计资
源，打包提供给用户。除了提供已有 MSP430 设计资源的完整集合外，MSP430Ware 软件还
包含名为 MSP 驱动程序库的高级 API。借助该库可以轻松地对 MSP430 硬件进行编程。
MSP430Ware 软件以 CCS 组件或独立软件包两种形式提供。
适用于 MSP430 MCU 的能量测量设计中心
能量测量设计中心是一款快速开发工具，它使用
TI
MSP430i20xx 和 MSP430F67xx 基于闪存的微控制器 (MCU) 实现能量测量。它包含能够在各
种电源监控和能量测量应用（包括智能电网和楼宇自动化）中简化开发和加快设计的图形用户
界面 (GUI)、文档、 软件库和示例。使用该设计中心，您无需编写任何代码即可配置、校准并
查看结果。
MSP 驱动程序库 MSP 驱动程序库的抽象 API 提供易用的函数调用，无需直接操纵 MSP430 硬件的位与字
节。完整的文档通过具有帮助意义的 API 指南交付，其中包括有关每个函数调用和经过验证的
参数的详细信息。开发人员可使用驱动程序库函数以尽可能低的费用编写全部项目。
IEC60730 软件包 IEC60730 MSP430 软件包经过专门开发，用于协助客户达到 IEC 60730-1:2010（家用
及类似用途的自动化电气控制 - 第 1 部分：一般要求）B 类产品的要求。其中涵盖家用电器、
电弧检测器、电源转换器、电动工具、电动自行车及其他诸多产品。IEC60730 MSP430 软件
包可以嵌入在 MSP430 MCU 中 运行的客户应用， 从而帮助客户简化其消费类器件在功能安
全方面遵循 IEC 60730-1:2010 B 类规范的认证工作。
MSP430F673xA、MSP430F672xA 代码示例 根据不同应用需求配置各集成外设的每个 MSP 器件均具备
相应的 C 代码示例。
144
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产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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电容式触摸软件库 可在 MSP430 MCU 启用电容触控功能的免费 C 代码库。MSP430 MCU 库版本 采用 多
种电容触控实现方法，包括 RO 和 RC 方法。
MSP EnergyTrace™ 技术 适用于 MSP430 微控制器的 EnergyTrace 技术是基于电能的代码分析工具，适
用于测量和显示应用的电能系统配置并帮助优化应用以实现超低功耗。
ULP（超低功耗）Advisor ULP Advisor™软件是一款辅助工具，旨在指导开发人员编写更为高效的代码，
从而充分利用 MSP430 和 MSP432 微控制器 独特 功能。ULP Advisor 的目标人群是微控制器
的资深开发者和开发新手，可以根据详尽的 ULP 检验表检查代码，以便最大限度地减少应用
程序的能耗。在编译时，ULP Advisor 会提供通知和备注以突出显示代码中可以进一步优化的
区域，进而实现更低功耗。
适用于 MSP 的定点数学库 MSP IQmath 和 Qmath 库是为 C 语言开发者提供的一套经过高度优化的高精
度数学运算函数集合，能够将浮点算法无缝嵌入 MSP430 和 MSP432 器件的定点代码中。这
些例程通常用于计算密集型实时 应用， 而优化的执行速度、高精度以及超低能耗通常是影响
这些实时应用的关键因素。与使用浮点数学算法编写的同等代码相比，使用 IQmath 和 Qmath
库可以大幅提高执行速度并显著降低能耗。
适用于 MSP430 的浮点数学运算库
TI
在低功耗和低成本微控制器领域锐意创新，为您提供
MSPMATHLIB。此标量函数的浮点数学运算库，能够充分利用器件的智能外设，使速度最高
达到标准 MSP430 数学函数的 26 倍。Mathlib 能够轻松集成到您的设计中。该运算库免费使
用并集成在 Code Composer Studio IDE 和 IAR Embedded Workbench IDE 中。
开发工具
适用于 MSP 微控制器的 Code Composer Studio™ 集成开发环境 Code Composer Studio (CCS) 集成开
发环境 (IDE) 支持所有 MSP 微控制器器件。CCS 包含一整套用于开发和调试嵌入式 应用的
工具。它包含了优化的 C/C++ 编译器、源代码编辑器、项目构建环境、调试器、描述器以及
其他多种 功能。
命令行编程器 MSP Flasher 是一款基于 shell 的开源接口，可使用 JTAG 或 Spy-Bi-Wire (SBW) 通信通过
FET 编程器或 eZ430 对 MSP 微控制器进行编程。MSP Flasher 可用于将二进制文件（.txt 或
.hex 文件）直接下载到 MSP 微控制器，而无需使用 IDE。
MSP MCU 编程器和调试器 MSP-FET 是一款强大的仿真开发工具（通常称为调试探针），可帮助用户在
MSP 低功耗微控制器 (MCU) 中快速开发应用。创建 MCU 软件通常需要将生成的二进制程序
下载到 MSP 器件中，从而进行验证和调试。
MSP-GANG 生产编程器 MSP Gang 编程器是一款 MSP430 或 MSP432 器件编程器，可同时对多达八个
完全相同的 MSP430 或 MSP432 闪存或 FRAM 器件进行编程。MSP Gang 编程器可使用标
准的 RS-232 或 USB 连接与主机 PC 相连并提供灵活的编程选项，允许用户完全自定义流
程。
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145
提交文档反馈意见
产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
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8.4 文档支持
以下文档对 MSP430F673xA 和 MSP430F672xA MCU 进行了介绍。www.ti.com.cn 网站上提供了这些文档
的副本。
接收文档更新通知
要接收文档更新通知（包括器件勘误表），请转至 ti.com.cn 上相关器件的产品文件夹（请参阅节 8.5提供的
链接）。请单击右上角的“通知我”按钮。点击注册后，即可收到产品信息更改每周摘要（如有）。有关更改
的详细信息，请查阅已修订文档的修订历史记录。
勘误
《MSP430F6736A 器件勘误表》 说明了功能技术规格的已知例外情况。
《MSP430F6735A 器件勘误表》 说明了功能技术规格的已知例外情况。
《MSP430F6734A 器件勘误表》 说明了功能技术规格的已知例外情况。
《MSP430F6733A 器件勘误表》 说明了功能技术规格的已知例外情况。
《MSP430F6731A 器件勘误表》 说明了功能技术规格的已知例外情况。
《MSP430F6730A 器件勘误表》 说明了功能技术规格的已知例外情况。
《MSP430F6726A 器件勘误表》 说明了功能技术规格的已知例外情况。
《MSP430F6725A 器件勘误表》 说明了功能技术规格的已知例外情况。
《MSP430F6724A 器件勘误表》 说明了功能技术规格的已知例外情况。
《MSP430F6723A 器件勘误表》 说明了功能技术规格的已知例外情况。
《MSP430F6721A 器件勘误表》 说明了功能技术规格的已知例外情况。
《MSP430F6720A 器件勘误表》 说明了功能技术规格的已知例外情况。
用户指南
《MSP430x5xx 和 MSP430x6xx 系列用户指南》 详细介绍了该器件系列提供的模块和外设。
《MSP430™ 闪存器件引导加载程序 (BSL) 用户指南》 MSP430 引导加载程序 (BSL) 允许用户在原型设
计、投产和维护等各阶段与 MSP430 微控制器中的嵌入式存储器进行通信。可编程存储器
（闪存）和数据存储器 (RAM) 可根据相关要求进行变更。不要将此处的引导加载程序与某些
数字信号处理器 (DSP) 中将外部存储器中的程序代码（和数据）自动加载到 DSP 内部存储器
的引导装载程序混为一谈。
《通过 JTAG 接口对 MSP430 进行编程》
此文档介绍了使用 JTAG 通信端口擦除、编程和验证基于
MSP430 闪存和 FRAM 的微控制器系列的存储器模块所需的功能。此外，该文档还介绍了如
何编程所有 MSP430 器件上均具备的 JTAG 访问安全保险丝。此文档介绍了使用标准四线制
JTAG 接口和两线制 JTAG 接口（也称为 Spy-Bi-Wire (SBW)）的器件访问。
《MSP430 硬件工具用户指南》 此手册介绍了 TI MSP-FET430 闪存仿真工具 (FET) 的硬件。FET 是针对
MSP430
超低功耗微控制器的程序开发工具。文中对提供的接口类型，即并行端口接口和
USB 接口进行了说明。
146
器件和文档支持
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提交文档反馈意见
产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
应用报告
《使用 MSP430F6736(A) 实施单相电子电表》
该应用报告介绍了如何使用德州仪器
MSP430F673x(A) 计量处理器实现单相电子电表。它还包含有关此单芯片实现的计量软件和硬
件程序的必要信息。
(TI)
《MSP430F67xx 与 MSP430F67xxA 器件之间的差异》 该应用报告介绍了 MSP430F67xxA 器件在非 A
MSP430F67xx 器件基础上实现的增强功能。该应用报告介绍了在 MSP430F67xxA 中修复的
MSP430F67xx 勘误表以及向 MSP430F67xxA 器件 添加的 其他功能。此外，还比较了计量结
果，以进一步展示 MSP430F67xxA 器件中实现的更改不会影响计量性能。
《MSP430 32kHz 晶体振荡器》 对于稳定的晶体振荡器，选择合适的晶振、正确的负载电路和适当的电路
板布局布线至关重要。该应用报告总结了晶体振荡器的功能，介绍了用于选择合适的晶体以实
现 MSP430 超低功耗运行的参数。此外，还给出了正确电路板布局的提示和示例。此外，为
了确保振荡器在大规模生产后能够稳定运行，还可能需要进行一些振荡器测试，该文档中提供
了有关这些测试的详细信息。
《MSP430 系统级 ESD 注意事项》
随着硅晶技术向更低电压方向发展以及设计具有成本效益的超低功耗
组件的需求的出现，系统级 ESD 要求变得越来越苛刻。该应用报告介绍了三个不同的 ESD 主
题，旨在帮助电路板设计人员和 OEM 理解并设计出稳健耐用的系统级设计。
《使用 MSP430 和段式 LCD 进行设计》 从智能电表，到电子货架标签 (ESL)，再到医疗设备，各式各样
的应用 都需要使用段式液晶显示屏 (LCD) 为用户 提供相关信息。部分 MSP430™ 微控制器系
列内置低功耗 LCD 驱动电路，MSP430 MCU 借此能够直接控制段式 LCD 玻璃。本应用手册
可帮助您理解段式 LCD 的工作原理、MSP430 MCU 系列各种 LCD 模块的不同特性， 并提供
了 LCD 硬件布线技巧、编写高效易用的 LCD 驱动软件的相关指导以及 具有不同 LCD 特性的
MSP430 器件的 产品组合概述， 旨在协助您进行器件选型。
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147
提交文档反馈意见
产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
8.5 相关链接
表 8-2 列出了快速访问链接。类别包括技术文档、支持与社区资源、工具与软件，以及申请样片或购买产品
的快速链接。
表 8-2. 相关链接
器件
产品文件夹
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技术文档
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工具与软件
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支持和社区
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MSP430F6736A
MSP430F6735A
MSP430F6734A
MSP430F6733A
MSP430F6731A
MSP430F6730A
MSP430F6726A
MSP430F6725A
MSP430F6724A
MSP430F6723A
MSP430F6721A
MSP430F6720A
8.6 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术
规范，并且不一定反映 TI 的观点；请参见 TI 的 《使用条款》。
TI E2E™ 社区
TI 的工程师交流 (E2E) 社区. 此社区的创建目的是为了促进工程师之间协作。在 e2e.ti.com 中，您可以提
问、共享知识、拓展思路，在同领域工程师的帮助下解决问题。
TI 嵌入式处理器维基网页
德州仪器 (TI) 嵌入式处理器维基网页。此网站的建立是为了帮助开发人员熟悉德州仪器 (TI) 的嵌入式处理
器，并且也为了促进与这些器件相关的硬件和软件的总体知识的创新和增长。
8.7 商标
MSP430, MSP430Ware, EnergyTrace, ULP Advisor, 适用于 MSP 微控制器的 Code Composer Studio,
E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
148
器件和文档支持
版权 © 2015–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
ZHCSDG4A –FEBRUARY 2015–REVISED OCTOBER 2018
www.ti.com.cn
8.8 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
8.9 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
8.10 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
9 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通
知，且不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015–2018, Texas Instruments Incorporated
机械、封装和可订购信息
149
提交文档反馈意见
产品主页链接: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A
MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430F6720AIPN
MSP430F6720AIPNR
MSP430F6720AIPZ
MSP430F6720AIPZR
MSP430F6721AIPN
MSP430F6721AIPNR
MSP430F6721AIPZ
MSP430F6721AIPZR
MSP430F6723AIPN
MSP430F6723AIPNR
MSP430F6723AIPZ
MSP430F6723AIPZR
MSP430F6724AIPN
MSP430F6724AIPNR
MSP430F6724AIPZ
MSP430F6724AIPZR
MSP430F6725AIPN
MSP430F6725AIPNR
MSP430F6725AIPZ
MSP430F6725AIPZR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
PN
PN
PZ
PZ
PN
PN
PZ
PZ
PN
PN
PZ
PZ
PN
PN
PZ
PZ
PN
PN
PZ
PZ
80
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
F6720A
1000 RoHS & Green
90 RoHS & Green
1000 RoHS & Green
119 RoHS & Green
1000 RoHS & Green
90 RoHS & Green
1000 RoHS & Green
119 RoHS & Green
1000 RoHS & Green
90 RoHS & Green
1000 RoHS & Green
119 RoHS & Green
1000 RoHS & Green
90 RoHS & Green
1000 RoHS & Green
119 RoHS & Green
1000 RoHS & Green
90 RoHS & Green
1000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
F6720A
F6720A
F6720A
F6721A
F6721A
F6721A
F6721A
F6723A
F6723A
F6723A
F6723A
F6724A
F6724A
F6724A
F6724A
F6725A
F6725A
F6725A
F6725A
100
100
80
80
100
100
80
80
100
100
80
80
100
100
80
80
100
100
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430F6726AIPN
MSP430F6726AIPNR
MSP430F6726AIPZ
MSP430F6726AIPZR
MSP430F6730AIPN
MSP430F6730AIPNR
MSP430F6730AIPZ
MSP430F6730AIPZR
MSP430F6731AIPN
MSP430F6731AIPNR
MSP430F6731AIPZ
MSP430F6731AIPZR
MSP430F6733AIPN
MSP430F6733AIPNR
MSP430F6733AIPZ
MSP430F6733AIPZR
MSP430F6734AIPN
MSP430F6734AIPNR
MSP430F6734AIPZ
MSP430F6734AIPZR
MSP430F6735AIPN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
PN
PN
PZ
PZ
PN
PN
PZ
PZ
PN
PN
PZ
PZ
PN
PN
PZ
PZ
PN
PN
PZ
PZ
PN
80
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
F6726A
1000 RoHS & Green
90 RoHS & Green
1000 RoHS & Green
119 RoHS & Green
1000 RoHS & Green
90 RoHS & Green
1000 RoHS & Green
119 RoHS & Green
1000 RoHS & Green
90 RoHS & Green
1000 RoHS & Green
119 RoHS & Green
1000 RoHS & Green
90 RoHS & Green
1000 RoHS & Green
119 RoHS & Green
1000 RoHS & Green
90 RoHS & Green
1000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
F6726A
F6726A
F6726A
F6730A
F6730A
F6730A
F6730A
F6731A
F6731A
F6731A
F6731A
F6733A
F6733A
F6733A
F6733A
F6734A
F6734A
F6734A
F6734A
F6735A
100
100
80
80
100
100
80
80
100
100
80
80
100
100
80
80
100
100
80
119
RoHS & Green
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430F6735AIPNR
MSP430F6735AIPZ
MSP430F6735AIPZR
MSP430F6736AIPN
MSP430F6736AIPNR
MSP430F6736AIPZ
MSP430F6736AIPZR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
PN
PZ
PZ
PN
PN
PZ
PZ
80
100
100
80
1000 RoHS & Green
90 RoHS & Green
1000 RoHS & Green
119 RoHS & Green
1000 RoHS & Green
90 RoHS & Green
1000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
F6735A
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
F6735A
F6735A
F6736A
F6736A
F6736A
F6736A
80
100
100
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Nov-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430F6720AIPNR
MSP430F6720AIPZR
MSP430F6721AIPNR
MSP430F6723AIPNR
MSP430F6724AIPNR
MSP430F6724AIPZR
MSP430F6725AIPNR
MSP430F6725AIPZR
MSP430F6726AIPNR
MSP430F6726AIPZR
MSP430F6730AIPZR
MSP430F6731AIPNR
MSP430F6731AIPZR
MSP430F6733AIPNR
MSP430F6733AIPZR
MSP430F6734AIPNR
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
PN
PZ
PN
PN
PN
PZ
PN
PZ
PN
PZ
PZ
PN
PZ
PN
PZ
PN
80
100
80
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
24.4
24.4
24.4
24.4
24.4
24.4
24.4
24.4
24.4
24.4
24.4
24.4
24.4
24.4
24.4
24.4
15.0
17.0
15.0
15.0
15.0
17.0
15.0
17.0
15.0
17.0
17.0
15.0
17.0
15.0
17.0
15.0
15.0
17.0
15.0
15.0
15.0
17.0
15.0
17.0
15.0
17.0
17.0
15.0
17.0
15.0
17.0
15.0
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
80
80
100
80
100
80
100
100
80
100
80
100
80
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Nov-2022
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430F6735AIPNR
MSP430F6736AIPNR
MSP430F6736AIPZR
LQFP
LQFP
LQFP
PN
PN
PZ
80
80
1000
1000
1000
330.0
330.0
330.0
24.4
24.4
24.4
15.0
15.0
17.0
15.0
15.0
17.0
2.1
2.1
2.1
20.0
20.0
20.0
24.0
24.0
24.0
Q2
Q2
Q2
100
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Nov-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430F6720AIPNR
MSP430F6720AIPZR
MSP430F6721AIPNR
MSP430F6723AIPNR
MSP430F6724AIPNR
MSP430F6724AIPZR
MSP430F6725AIPNR
MSP430F6725AIPZR
MSP430F6726AIPNR
MSP430F6726AIPZR
MSP430F6730AIPZR
MSP430F6731AIPNR
MSP430F6731AIPZR
MSP430F6733AIPNR
MSP430F6733AIPZR
MSP430F6734AIPNR
MSP430F6735AIPNR
MSP430F6736AIPNR
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
PN
PZ
PN
PN
PN
PZ
PN
PZ
PN
PZ
PZ
PN
PZ
PN
PZ
PN
PN
PN
80
100
80
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
350.0
350.0
350.0
350.0
350.0
350.0
350.0
367.0
367.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
367.0
367.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
45.0
45.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
80
80
100
80
100
80
100
100
80
100
80
100
80
80
80
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Nov-2022
Device
MSP430F6736AIPZR
Package Type Package Drawing Pins
LQFP PZ 100
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
1000
Pack Materials-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Nov-2022
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
MSP430F6720AIPN
MSP430F6721AIPZ
MSP430F6731AIPZ
MSP430F6733AIPN
MSP430F6735AIPZ
MSP430F6736AIPZ
PN
PZ
PZ
PN
PZ
PZ
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
80
100
100
80
119
90
7 x 17
6 x 15
6 x 15
7 x 17
6 x 15
6 x 15
150
150
150
150
150
150
315 135.9 7620 17.9
315 135.9 7620 20.3
315 135.9 7620 20.3
315 135.9 7620 17.9
315 135.9 7620 20.3
315 135.9 7620 20.3
14.3 13.95
15.4 15.45
15.4 15.45
14.3 13.95
15.4 15.45
15.4 15.45
90
119
90
100
100
90
Pack Materials-Page 5
PACKAGE OUTLINE
PN0080A
LQFP - 1.6 mm max height
SCALE 1.250
PLASTIC QUAD FLATPACK
12.2
11.8
B
PIN 1 ID
A
80
61
1
60
12.2
11.8
14.2
TYP
13.8
20
41
40
21
76X 0.5
0.27
80X
0.17
4X 9.5
0.08
C A B
1.6 MAX
C
(0.13) TYP
SEATING PLANE
0.08
SEE DETAIL A
0.25
GAGE PLANE
(1.4)
0.05 MIN
0.75
0.45
0 -7
DETAIL
SCALE: 14
A
DETAIL A
TYPICAL
4215166/A 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MS-026.
www.ti.com
EXAMPLE BOARD LAYOUT
PN0080A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
80
61
80X (1.5)
1
60
80X (0.3)
SYMM
(13.4)
76X (0.5)
(R0.05) TYP
20
41
21
40
(13.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
0.05 MAX
ALL AROUND
EXPOSED METAL
METAL
0.05 MIN
ALL AROUND
EXPOSED METAL
SOLDER MASK
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4215166/A 08/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
6. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).
www.ti.com
EXAMPLE STENCIL DESIGN
PN0080A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
80
61
80X (1.5)
1
60
80X (0.3)
SYMM
(13.4)
76X (0.5)
(R0.05) TYP
20
41
21
40
(13.4)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:6X
4215166/A 08/2022
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
M
0,08
51
50
76
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
0,25
16,20
SQ
0,05 MIN
0°–7°
15,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
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