MSP430F6775AIPZR [TI]
具有 7 个 Σ-Δ ADC、LCD、实时时钟、AES、128KB 闪存和 16KB RAM 的多相位计量 SoC | PZ | 100 | -40 to 85;
| 型号： | MSP430F6775AIPZR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 7 个 Σ-Δ ADC、LCD、实时时钟、AES、128KB 闪存和 16KB RAM 的多相位计量 SoC | PZ | 100 | -40 to 85 时钟 CD 闪存 |
| 文件： | 总181页 (文件大小：2797K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
MSP430F677xA、MSP430F676xA、MSP430F674xA 多相仪表计量片
上系统 (SoC)
1 器件概述
1.1 特性
1
• 相位电流在超过 2000:1 的动态范围内精度 < 0.1%
• 高集成度数字
• 符合或者超过美国国家标准学会 (ANSI) C12.20 和
国际电工委员会 (IEC) 62053 标准
• 支持诸如电流变压器、罗式线圈或分流器等多种传
感器
– 3 通道直接存储器存取 (DMA) 控制器
– 用于加密的集成硬件 AES-128 模块
– 16 位循环冗余校验 (CRC) 模块
– 4 个 16 位计时器，共有 9 个捕捉/比较寄存器
• 6 个增强型通用串行通信接口 (eUSCI)
– eUSCI_A0、eUSCI_A1、eUSCI_A2 和
eUSCI_A3 支持 UART、IrDA 和 SPI
– eUSCI_B0、eUSCI_B1 支持 SPI 和 I2C
• 超低功耗
• 针对高达 3 相位加上中线相位的电源管理
• 为校准提供有源能量和无功能量的专用脉冲输出引
脚
• 每相位或累加相位的四象限测量
• 精确的相位角测量
• 针对电流变压器的数字相位校正
• 温度补偿电能测量
• 使用单一校准的 40Hz 至 70Hz 线路频率范围
• 支持自动切换的灵活电源选项
• AC 主电源故障期间，显示运行在极低功耗
下：LMP3 时 为 3µA
• 具有高达 320 段对比度控制的 LCD 驱动器
• 具有篡改检测、晶振偏移校准和温度补偿功能的受
密码保护的实时时钟 (RTC)
• 集成安全模块以支持防篡改和加密
• 用于智能仪表实施的多个通信接口
• 高性能模拟
– 多个低功耗模式
– 待机模式 (LPM3)：3V 时为 2.1µA，
在不到 5µs 的时间内唤醒
– RTC 模式 (LPM3.5)：3V 时为 0.34µA
– 关断模式 (LPM4.5)：3V 时为 0.18µA
• CPU
– 具有 32 位复用器的高性能 25MHz CPU
– 宽输入电源电压范围：
3.6V 到低至 1.8V
• 存储器
– 高达 512KB 的单周期闪存
– 高达 32KB 支持单周期访问的 RAM
• 封装选项
– 具有 90 个 I/O 引脚的 128 引脚薄型方形扁平
(LQFP)(PEU) 封装
– 具有 62 个 I/O 引脚的 100 引脚 LQFP (PZ) 封装
• 开发工具（另请参阅 工具与软件）
– 多达 7 个支持差分输入和可变增益的独立 24 位
Σ-Δ ADC
– 具有 6 个外部通道和 2 个内部通道的 10 位
200ksps SAR ADC，包括电源和温度传感器测量
– 适用于具有 24 位 Σ-Δ ADC 的 MSP430 MCU 的
电能测量设计中心 (MSP-EM-DESIGN-CENTER)
– 用于计量的三相电子电表 (EVM430-F6779)
– 目标开发板 (MSP‑TS430PEU128)
1.2 应用
•
•
三相电子电表
•
能量监控
公用事业仪表计量
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLAS982
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
1.3 说明
MSP430F67xxA 多相位计量 SoC 是功能强大的高度集成解决方案，这些解决方案使用很少的外部组件即可
提供高精度计量并实现低系统成本。MSP430F67xxA 微控制器 (MCU) 系列是 MSP430™计量和监测 MCU
产品系列的一部分，该产品系列专用于电能测量和功率监控 应用 （包括智能电网和楼宇自动化）。
MSP430F67xxA MCU具有多达 7 个独立的 24 位 Σ-Δ ADC，可提供优于 0.1% 的精度。MSP430F67xxA 器
件集成了高性能 MSP430 CPU 和 32 位乘法器，可执行所有计量计算。系列产品成员包括高达 512KB 的闪
存、32KB 的 RAM 以及一个最高支持 320 段的 LCD 控制器。
MSP430F67xxA 具有超低功耗，可以最大程度地减小系统电源，从而降低总成本。低待机功率需要最低的
电能存储，并且能够在主电源发生故障时更长时间地保留关键数据。
MSP430F67xxA MCU 系列由广泛的软件和硬件生态系统提供支持。德州仪器 (TI) 电能测量设计中心
(EMDC) 可以通过快速配置电能测量软件库、自动生成代码、执行校准和查看结果来简化开发并加快设计。
MSP430F67xxA MCU 执行电能测量软件库，该软件库计算所有相关电能和功率结果。开发套件包括
EVM430-F6779 三相电表评估板和 MSP-TS430PEU128 128 引脚目标开发板。还提供工业标准开发工具与
软件平台，以在全球范围内加快符合所有 ANSI 和 IEC 标准的仪表的开发。
有关完整的模块说明，请参阅《MSP430F5xx 和 MSP430F6xx 系列用户指南》
器件信息(1)
封装
器件型号
MSP430F6779AIPEU
MSP430F6779AIPZ
封装尺寸(2)
20mm × 14mm
14mm x 14mm
LQFP (128)
LQFP (100)
(1) 要获得最新的产品、封装和订购信息，请参见封装选项附录（节 9），或者访问德州仪器 (TI) 网站
www.ti.com.cn。
(2) 此处显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参见机械数据（节 9）。
2
器件概述
版权 © 2014–2018, Texas Instruments Incorporated
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
1.4 应用图
图 1-1 显示了典型应用图。
TOTAL
kWh
Load
Sx, COMx
Phase C
Phase B
VCC
RST
VSS
Phase A
MSP430F677xA
R33
Px.x
LCDCAP
Neutral
+
Status LEDs
ΣΔ Modulator
CT
IA
IB
IC
–
+
Px.y
ΣΔ Modulator
CT
–
Pulse LEDs
+
ΣΔ Modulator
CT
–
XIN
+
32768 Hz
ΣΔ Modulator
CT
Ineutral
–
XOUT
USCIA0
USCIA1
USCIA2
USCIA3
USCIB0
USCIB1
VA
AFE
+
UART or SPI
UART or SPI
UART or SPI
UART or SPI
I2C or SPI
ΣΔ Modulator
–
VB
+
ΣΔ Modulator
–
VC
VN
+
ΣΔ Modulator
–
I2C or SPI
Vref
Neutral
Phase B
Phase C
Phase A
Source From Utility
Copyright © 2016, Texas Instruments Incorporated
图 1-1. 使用 MSP430F677xA 的 3 相 4 线制星形连接
版权 © 2014–2018, Texas Instruments Incorporated
器件概述
3
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
内容
1
器件概述.................................................... 1
1.1 特性 ................................................... 1
1.2 应用 ................................................... 1
1.3 说明 ................................................... 2
1.4 应用图 ................................................ 3
修订历史记录............................................... 5
Device Comparison ..................................... 6
3.1 Related Products ..................................... 7
Terminal Configuration and Functions.............. 8
4.1 Pin Diagrams ......................................... 8
4.2 Signal Descriptions.................................. 12
4.3 Pin Multiplexing ..................................... 25
4.4 Connection of Unused Pins ......................... 25
Specifications ........................................... 26
5.1 Absolute Maximum Ratings......................... 26
5.2 ESD Ratings ........................................ 26
5.3 Recommended Operating Conditions............... 26
5.17 ADC10_A............................................ 60
5.18 REF.................................................. 62
5.19 Comparator_B....................................... 63
5.20 Flash ................................................ 64
5.21 Emulation and Debug ............................... 64
Detailed Description ................................... 65
6.1 Overview ............................................ 65
6.2 Functional Block Diagrams.......................... 66
6.3 CPU (Link to User's Guide) ......................... 67
6.4 Instruction Set....................................... 68
6.5 Operating Modes.................................... 69
6.6 Interrupt Vector Addresses.......................... 70
6.7 Special Function Registers (SFRs) ................. 71
6.8 Bootloader (BSL).................................... 72
6.9 JTAG Operation ..................................... 73
6.10 Memory.............................................. 74
6.11 Peripherals .......................................... 77
6.12 Input/Output Diagrams............................. 103
6.13 Device Descriptors (TLV) .......................... 158
6.14 Identification........................................ 161
Applications, Implementation, and Layout ...... 162
器件和文档支持......................................... 163
8.1 入门和后续步骤 .................................... 163
8.2 Device Nomenclature.............................. 163
8.3 工具与软件 ......................................... 165
8.4 文档支持 ........................................... 167
8.5 相关链接 ........................................... 169
8.6 社区资源 ........................................... 169
8.7 商标 ................................................ 169
8.8 静电放电警告....................................... 169
8.9 Glossary............................................ 169
机械、封装和可订购信息 .............................. 170
2
3
6
4
5
5.4
5.5
5.6
Active Mode Supply Current Into VCC Excluding
External Current..................................... 28
Low-Power Mode Supply Currents (Into VCC
)
Excluding External Current.......................... 29
Low-Power Mode With LCD Supply Currents (Into
7
8
VCC) Excluding External Current.................... 30
5.7 Thermal Resistance Characteristics ................ 31
5.8 Timing and Switching Characteristics............... 32
5.9 Digital I/Os........................................... 36
5.10 Power-Management Module (PMM) ................ 40
5.11 Auxiliary Supplies ................................... 42
5.12 Timer_A ............................................. 45
5.13 eUSCI ............................................... 45
5.14 RTC Tamper Detect Pin ............................ 51
5.15 LCD_C .............................................. 52
5.16 SD24_B ............................................. 54
9
4
内容
版权 © 2014–2018, Texas Instruments Incorporated
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
2 修订历史记录
Changes from May 29, 2014 to September 28, 2018
Page
•
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•
更新了节 1.1特性 ..................................................................................................................... 1
更新了节 1.3说明 ..................................................................................................................... 2
Added Section 3.1, Related Products ............................................................................................. 7
Corrected the port number (P4.2) on pin 61 in Figure 4-2, 100-Pin PZ Package (Top View) ............................ 10
Added note to P1.3/ADC10CLK/A3 (pin 8) in Table 4-3, Terminal Functions – PEU Package........................... 12
Added typical conditions statements at the beginning of Section 5, Specifications ........................................ 26
Added SD24_B input pins and AUXVCCx pins to exception list on "Voltage applied to pins" parameter, and
added SD24_B input pin limits in "Diode current at pins" parameter in Section 5.1, Absolute Maximum Ratings..... 26
Added Section 5.2, ESD Ratings.................................................................................................. 26
Added Section 5.7, Thermal Resistance Characteristics ...................................................................... 31
Updated notes (1) and (2) and added note (3) in Table 5-1, Wake-up Times From Low-Power Modes and Reset .. 32
Changed the TYP value of the CL,eff parameter with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF
in Table 5-2, Crystal Oscillator, XT1, Low-Frequency Mode .................................................................. 33
Corrected bit name in Test Conditions of RCHARGE parameter (changed CHCx to AUXCHCx) in Table 5-25,
Auxiliary Supplies, Charge Limiting Resistor .................................................................................... 44
Replaced fFrame parameter with fLCD, fFRAME,4mux, and fFRAME,8mux parameters in Table 5-37, LCD_C, Operating
Conditions ............................................................................................................................ 52
On the VID,FS parameter in Table 5-39, SD24_B Power Supply and Recommended Operating Conditions:
Changed the MIN value from "VREF/GAIN" to "–VREF/GAIN"; Removed "Unipolar mode" test condition (mode is
not supported) ....................................................................................................................... 54
Removed ADC10DIV from the formula for the TYP value in the second row of the tCONVERT parameter in Table 5-
48, 10-Bit ADC, Switching Characteristics, because ADC10CLK is after division.......................................... 60
Changed Test Conditions for all parameters in Table 5-49, 10-Bit ADC Linearity Parameters: Removed "VREF–";
•
•
•
•
•
•
•
•
•
Changed from "(VeREF+ – VeREF–)min ≤ (VeREF+ – VeREF–)" to "1.4 V ≤ (VeREF+ – VeREF–)"; Changed from "CVREF+
=
20 pF" to "CVeREF+ = 20 pF"; Added "CVeREF+ = 20 pF" to EI; Added "ADC10SREFx = 11b" to ET and EG .............. 61
Changed from "VREF–/VeREF–" to "VeREF–" in Test Conditions for VeREF+, VeREF–, and (VeREF+ – VeREF–) parameters
in Table 5-50, 10-Bit ADC, External Reference ................................................................................. 61
Changed the MIN value of AVCC(min) with Test Conditions of "REFVSEL = {0} for 1.5 V" from 2.2 V to 1.8 V in
Table 5-51, REF Built-In Reference .............................................................................................. 62
Changed the MAX value of the tEN_CMP parameter with Test Conditions of "CBPWRMD = 10" from 50 µs to
100 µs in Table 5-52, Comparator_B............................................................................................. 63
Corrected the name of the RTC module (changed from RTC_CE to RTC_C) in Figure 6-1, Functional Block
Diagram – PEU Package........................................................................................................... 66
Corrected the name of the RTC module (changed from RTC_CE to RTC_C) in Figure 6-2, Functional Block
Diagram – PZ Package............................................................................................................. 66
Throughout document, changed all instances of "bootstrap loader" to "bootloader"....................................... 72
Corrected spelling of NMIIFG in Table 6-13, System Module Interrupt Vector Registers ................................. 80
Deleted mention of counter mode in Section 6.11.22, Real-Time Clock (RTC_C) (feature is not supported in this
device) ................................................................................................................................ 85
已将先前的“开发工具支持”部分替换为“节 8.3、工具与软件” ................................................................ 165
更改了格式并在节 8.4文档支持 中添加了内容 ................................................................................. 167
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•
•
•
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•
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•
Copyright © 2014–2018, Texas Instruments Incorporated
修订历史记录
5
Submit Documentation Feedback
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
3 Device Comparison
Table 3-1 summarizes the available family members.
Table 3-1. Device Comparison(1)(2)
eUSCI
CHANNEL
A:
UART, IrDA,
SPI
FLASH
(KB)
SRAM
(KB)
SD24_B
CONVERTERS
ADC10_A
CHANNELS
Timer_A(3)
I/Os
PACKAGE
CHANNEL
B:
SPI, I2C
DEVICE
MSP430F6779AIPEU
MSP430F6778AIPEU
MSP430F6777AIPEU
MSP430F6776AIPEU
MSP430F6775AIPEU
MSP430F6769AIPEU
MSP430F6768AIPEU
MSP430F6767AIPEU
MSP430F6766AIPEU
MSP430F6765AIPEU
MSP430F6749AIPEU
MSP430F6748AIPEU
MSP430F6747AIPEU
MSP430F6746AIPEU
MSP430F6745AIPEU
MSP430F6779AIPZ
MSP430F6778AIPZ
MSP430F6777AIPZ
MSP430F6776AIPZ
MSP430F6775AIPZ
MSP430F6769AIPZ
MSP430F6768AIPZ
MSP430F6767AIPZ
MSP430F6766AIPZ
MSP430F6765AIPZ
MSP430F6749AIPZ
MSP430F6748AIPZ
MSP430F6747AIPZ
MSP430F6746AIPZ
MSP430F6745AIPZ
512
512
256
256
128
512
512
256
256
128
512
512
256
256
128
512
512
256
256
128
512
512
256
256
128
512
512
256
256
128
32
16
32
16
16
32
16
32
16
16
32
16
32
16
16
32
16
32
16
16
32
16
32
16
16
32
16
32
16
16
7
7
7
7
7
6
6
6
6
6
4
4
4
4
4
7
7
7
7
7
6
6
6
6
6
4
4
4
4
4
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
(1) For the most current package and ordering information, see the Package Option Addendum in 节 9, or see the TI website at
www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
6
Device Comparison
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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3.1 Related Products
For information about other devices in this family of products or related products, see the following links.
Products for TI Microcontrollers TI's low-power and high-performance MCUs, with wired and wireless
connectivity options, are optimized for a broad range of applications.
Products for MSP430 Ultra-Low-Power Microcontrollers One platform. One ecosystem. Endless
possibilities. Enabling the connected world with innovations in ultra-low-power
microcontrollers with advanced peripherals for precise sensing and measurement.
Companion Products for MSP430F6779A Review products that are frequently purchased or used with
this product.
Reference Designs for MSP430F6779A The TI Designs Reference Design Library is a robust reference
design library that spans analog, embedded processor, and connectivity. Created by TI
experts to help you jump start your system design, all TI Designs include schematic or block
diagrams, BOMs, and design files to speed your time to market.
Copyright © 2014–2018, Texas Instruments Incorporated
Device Comparison
7
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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4 Terminal Configuration and Functions
4.1 Pin Diagrams
Figure 4-1 shows the pinout for the 128-pin PEU package. Table 4-1 summarizes the differences in the
pinout among the device variants.
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
XIN
XOUT
1
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
RST/NMI/SBWTDIO
PJ.3/TCK
2
AUXVCC3
3
PJ.2/TMS
RTCCAP1
4
PJ.1/TDI/TCLK
PJ.0/TDO
RTCCAP0
5
P1.5/SMCLK/CB0/A5
P1.4/MCLK/CB1/A4
P1.3/ADC10CLK/A3
P1.2/ACLK/A2
6
TEST/SBWTCK
P2.3/PM_TA1.0
P2.2/PM_TA0.2
P2.1/PM_TA0.1/BSL_RX
P2.0/PM_TA0.0/BSL_TX
P11.5/TACLK/RTCCLK
P11.4/CBOUT
P11.3/TA2.1
P11.2/TA1.1
P11.1/TA3.1/CB3
P11.0/S0
7
8
9
P1.1/TA2.1/VeREF+/A1
P1.0/TA1.1/VeREF-/A0
P2.4/PM_TA2.0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
P2.5/PM_UCB0SOMI/PM_UCB0SCL
P2.6/PM_UCB0SIMO/PM_UCB0SDA
P2.7/PM_UCB0CLK
P3.0/PM_UCA0RXD/PM_UCA0SOMI
P3.1/PM_UCA0TXD/PM_UCA0SIMO
P3.2/PM_UCA0CLK
P3.3/PM_UCA1CLK
P3.4/PM_UCA1RXD/PM_UCA1SOMI
P3.5/PM_UCA1TXD/PM_UCA1SIMO
COM0
P10.7/S1
P10.6/S2
P10.5/S3
P10.4/S4
P10.3/S5
P10.2/S6
COM1
P10.1/S7
P1.6/COM2
P10.0/S8
P1.7/COM3
P9.7/S9
P5.0/COM4
P9.6/S10
P5.1/COM5
P9.5/S11
P5.2/COM6
P9.4/S12
P5.3/COM7
P9.3/S13
LCDCAP/R33
P9.2/S14
P5.4/SDCLK/R23
P9.1/S15
P5.5/SD0DIO/LCDREF/R13
P5.6/SD1DIO/R03
P9.0/S16
DVSS2
P5.7/SD2DIO/CB2
VDSYS2
P6.0/SD3DIO
P8.7/S17
P3.6/PM_UCA2RXD/PM_UCA2SOMI
P3.7/PM_UCA2TXD/PM_UCA2SIMO
P4.0/PM_UCA2CLK
P8.6/S18
P8.5/S19
P8.4/S20
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
A. The secondary digital functions on Ports P2, P3, and P4 are fully mappable. This pinout shows only the default
mapping. See Section 6.11.6 for details.
B. The pair of pins VDSYS1 and VDSYS2, VASYS1 and VASYS2 must be connected externally on board for proper
device operation.
C. CAUTION: The LCDCAP/R33 pin must be connected to DVSS if it is not used.
Figure 4-1. 128-Pin PEU Package (Top View)
8
Terminal Configuration and Functions
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 4-1. Pinout Differences for PEU Package, F677xA, F676xA, and F674xA
PIN NAME
PIN
NUMBER
MSP430F677xAIPEU
P6.1/SD4DIO/S39
P6.2/SD5DIO/S38
P6.3/SD6DIO/S37
VREF
MSP430F676xAIPEU
P6.1/SD4DIO/S39
P6.2/SD5DIO/S38
P6.3/S37
VREF
MSP430F674xAIPEU
46
P6.1/S39
P6.2/S38
P6.3/S37
VREF
NC
47
48
113
114
115
116
117
118
119
SD4P0
SD4P0
SD4N0
SD4N0
NC
SD5P0
SD5P0
NC
SD5N0
SD5NO
NC
SD6P0
NC
NC
SD6N0
NC
NC
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Terminal Configuration and Functions
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Figure 4-2 shows the pinout for the 100-pin PZ package. Table 4-2 summarizes the differences in the
pinout among the device variants.
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
SD0P0
SD0N0
SD1P0
SD1N0
SD2P0
SD2N0
SD3P0
SD3N0
VASYS2
AVSS2
VREF
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDSYS2
2
P5.7/SD6DIO/S17
3
P5.6/SD5DIO/S18
4
P5.5/SD4DIO/S19
5
P5.4/SD3DIO/S20
6
P5.3/SD2DIO/S21
7
P5.2/SD1DIO/S22
8
P5.1/SD0DIO/S23
9
P5.0/SDCLK/S24
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P4.7/PM_TA3.0/S25
P4.6/PM_UCB1CLK/S26
SD4P0
SD4N0
SD5P0
SD5N0
SD6P0
SD6N0
AVSS1
AVCC
P4.5/PM_UCB1SIMO/PM_UCB1SDA/S27
P4.4/PM_UCB1SOMI/PM_UCB1SCL/S28
P4.3/PM_UCA3CLK/S29
P4.2/PM_UCA3TXD/PM_UCA3SIMO/S30
P4.1/PM_UCA3RXD/PM_UCA3SOMI/S31
P4.0/PM_UCA2CLK/S32
P3.7/PM_UCA2TXD/PM_UCA2SIMO/S33
P3.6/PM_UCA2RXD/PM_UCA2SOMI/S34
P3.5/PM_UCA1TXD/PM_UCA1SIMO/S35
P3.4/PM_UCA1RXD/PM_UCA1SOMI/S36
P3.3/PM_UCA1CLK/S37
VASYS1
AUXVCC2
AUXVCC1
VDSYS1
DVCC
P3.2/PM_UCA0CLK/S38
P3.1/PM_UCA0TXD/PM_UCA0SIMO/S39
P3.0/PM_UCA0RXD/PM_UCA0SOMI
DVSS1
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A. The secondary digital functions on Ports P2, P3, and P4 are fully mappable. This pinout shows only the default
mapping. See Section 6.11.6 for details.
B. The pair of pins VDSYS1 and VDSYS2, VASYS1 and VASYS2 must be connected externally on board for proper
device operation.
C. CAUTION: The LCDCAP/R33 pin must be connected to DVSS if it is not used.
Figure 4-2. 100-Pin PZ Package (Top View)
10
Terminal Configuration and Functions
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 4-2. Pinout Differences for PZ Package, F677xA, F676xA, and F674xA
PIN NAME
PIN
NUMBER
MSP430F677xAIPZ
VREF
MSP430F676xAIPZ
VREF
MSP430F674xAIPZ
11
12
13
14
15
16
17
72
73
74
VREF
NC
SD4P0
SD4P0
SD4N0
SD4N0
NC
SD5P0
SD5P0
NC
SD5N0
SD5NO
NC
SD6P0
NC
NC
SD6N0
NC
NC
P5.5/SD4DIO/S19
P5.6/SD5DIO/S18
P5.7/SD6DIO/S17
P5.5/SD4DIO/S19
P5.6/SD5DIO/S18
P5.7/S17
P5.5/S19
P5.6/S18
P5.7/S17
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Terminal Configuration and Functions
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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4.2 Signal Descriptions
Table 4-3 describes the signals for devices in the PEU package. See Table 4-4 for the signals in the PZ
package.
Table 4-3. Terminal Functions – PEU Package
TERMINAL
NO. I/O(1)
PEU
DESCRIPTION
NAME
XIN
1
2
3
4
5
I/O Input terminal for crystal oscillator
I/O Output terminal for crystal oscillator
XOUT
AUXVCC3
RTCCAP1
RTCCAP0
Auxiliary power supply AUXVCC3 for backup subsystem
External time capture pin 1 for RTC_C
External time capture pin 0 for RTC_C
General-purpose digital I/O with port interrupt
SMCLK clock output
I
I
P1.5/SMCLK/CB0/A5
P1.4/MCLK/CB1/A4
6
7
I/O
I/O
Comparator_B input CB0
Analog input A5 for 10-bit ADC
General-purpose digital I/O with port interrupt
MCLK clock output
Comparator_B input CB1
Analog input A4 for 10-bit ADC
General-purpose digital I/O with port interrupt
P1.3/ADC10CLK/A3(2)
P1.2/ACLK/A2
8
9
I/O ADC10_A clock output
Analog input A3 for 10-bit ADC
General-purpose digital I/O with port interrupt
I/O ACLK clock output
Analog input A2 for 10-bit ADC
General-purpose digital I/O with port interrupt
Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output
P1.1/TA2.1/VeREF+/A1
10
11
I/O
Positive terminal for the ADC reference voltage for an external applied reference voltage
Analog input A1 for 10-bit ADC
General-purpose digital I/O with port interrupt
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output
P1.0/TA1.1/VeREF-/A0
P2.4/PM_TA2.0
I/O
Negative terminal for the ADC reference voltage for an external applied reference voltage
Analog input A0 for 10-bit ADC
General-purpose digital I/O with port interrupt and mappable secondary function
12
13
I/O
Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0 output
General-purpose digital I/O with port interrupt and mappable secondary function
I/O Default mapping: eUSCI_B0 SPI slave out master in
Default mapping: eUSCI_B0 I2C clock
P2.5/PM_UCB0SOMI/
PM_UCB0SCL
General-purpose digital I/O with port interrupt and mappable secondary function
I/O Default mapping: eUSCI_B0 SPI slave in master out
Default mapping: eUSCI_B0 I2C data
P2.6/PM_UCB0SIMO/
PM_UCB0SDA
14
15
General-purpose digital I/O with port interrupt and mappable secondary function
P2.7/PM_UCB0CLK
I/O
Default mapping: eUSCI_B0 clock input/output
(1) I = input, O = output
(2) Before enabling the analog function (A3), pull this pin low by setting the port function to output low or to input with the internal pulldown
resistor enabled.
12
Terminal Configuration and Functions
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 4-3. Terminal Functions – PEU Package (continued)
TERMINAL
NO. I/O(1)
PEU
DESCRIPTION
NAME
General-purpose digital I/O with mappable secondary function
P3.0/PM_UCA0RXD/
PM_UCA0SOMI
16
17
I/O Default mapping: eUSCI_A0 UART receive data
Default mapping: eUSCI_A0 SPI slave out master in
General-purpose digital I/O with mappable secondary function
I/O Default mapping: eUSCI_A0 UART transmit data
Default mapping: eUSCI_A0 SPI slave in master out
P3.1/PM_UCA0TXD/
PM_UCA0SIMO
General-purpose digital I/O with mappable secondary function
P3.2/PM_UCA0CLK
P3.3/PM_UCA1CLK
18
19
I/O
Default mapping: eUSCI_A0 clock input/output
General-purpose digital I/O with mappable secondary function
I/O
Default mapping: eUSCI_A1 clock input/output
General-purpose digital I/O with mappable secondary function
I/O Default mapping: eUSCI_A1 UART receive data
Default mapping: eUSCI_A1 SPI slave out master in
General-purpose digital I/O with mappable secondary function
I/O Default mapping: eUSCI_A1 UART transmit data
Default mapping: eUSCI_A1 SPI slave in master out
P3.4/PM_UCA1RXD/
PM_UCA1SOMI
20
21
P3.5/PM_UCA1TXD/
PM_UCA1SIMO
COM0
COM1
22
23
O
O
LCD common output COM0 for LCD backplane
LCD common output COM1 for LCD backplane
General-purpose digital I/O with port interrupt
LCD common output COM2 for LCD backplane
General-purpose digital I/O with port interrupt
LCD common output COM3 for LCD backplane
General-purpose digital I/O
P1.6/COM2
P1.7/COM3
P5.0/COM4
P5.1/COM5
P5.2/COM6
P5.3/COM7
24
25
26
27
28
29
I/O
I/O
I/O
I/O
I/O
I/O
LCD common output COM4 for LCD backplane
General-purpose digital I/O
LCD common output COM5 for LCD backplane
General-purpose digital I/O
LCD common output COM6 for LCD backplane
General-purpose digital I/O
LCD common output COM7 for LCD backplane
LCD capacitor connection
LCDCAP/R33
30
31
I/O Input/output port of most positive analog LCD voltage (V1)
CAUTION: This pin must be connected to DVSS if not used.
General-purpose digital I/O
P5.4/SDCLK/R23
I/O SD24_B bit-stream clock input/output
Input/Output port of second most positive analog LCD voltage (V2)
General-purpose digital I/O
SD24_B converter 0 bit-stream data input/output
P5.5/SD0DIO/
LCDREF/R13
32
33
I/O
External reference voltage input for regulated LCD voltage
Input/output port of third most positive analog LCD voltage (V3 or V4)
General-purpose digital I/O
P5.6/SD1DIO/R03
I/O SD24_B converter 1 bit-stream data input/output
Input/output port of lowest analog LCD voltage (V5)
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 4-3. Terminal Functions – PEU Package (continued)
TERMINAL
NO. I/O(1)
PEU
DESCRIPTION
NAME
P5.7/SD2DIO/CB2
P6.0/SD3DIO
General-purpose digital I/O
34
35
36
I/O SD24_B converter 2 bit-stream data input/output
Comparator_B input CB2
General-purpose digital I/O
I/O
SD24_B converter 3 bit-stream data input/output
General-purpose digital I/O with mappable secondary function
I/O Default mapping: eUSCI_A2 UART receive data
Default mapping: eUSCI_A2 SPI slave out master in
General-purpose digital I/O with mappable secondary function
I/O Default mapping: eUSCI_A2 UART transmit data
Default mapping: eUSCI_A2 SPI slave in master out
P3.6/PM_UCA2RXD/
PM_UCA2SOMI
P3.7/PM_UCA2TXD/
PM_UCA2SIMO
37
38
39
General-purpose digital I/O with mappable secondary function
P4.0/PM_UCA2CLK
I/O
Default mapping: eUSCI_A2 clock input/output
General-purpose digital I/O with mappable secondary function
I/O Default mapping: eUSCI_A3 UART receive data
Default mapping: eUSCI_A3 SPI slave out master in
General-purpose digital I/O with mappable secondary function
I/O Default mapping: eUSCI_A3 UART transmit data
Default mapping: eUSCI_A3 SPI slave in master out
P4.1/PM_UCA3RXD/
PM_UCA3SOMI
P4.2/PM_UCA3TXD/
PM_UCA3SIMO
40
41
42
General-purpose digital I/O with mappable secondary function
P4.3/PM_UCA3CLK
I/O
Default mapping: eUSCI_A3 clock input/output
General-purpose digital I/O with mappable secondary function
I/O Default mapping: eUSCI_B1 SPI slave out, master in
Default mapping: eUSCI_B1 I2C clock
P4.4/PM_UCB1SOMI/
PM_UCB1SCL
General-purpose digital I/O with mappable secondary function
I/O Default mapping: eUSCI_B1 SPI slave in, master out
Default mapping: eUSCI_B1 I2C data
P4.5/PM_UCB1SIMO/
PM_UCB1SDA
43
General-purpose digital I/O with mappable secondary function
P4.6/PM_UCB1CLK
P4.7/PM_TA3.0
44
45
I/O
Default mapping: eUSCI_B1 clock input/output
General-purpose digital I/O with mappable secondary function
I/O
Default mapping: Timer TA3 capture CCR0: CCI0A input, compare: Out0 output
General-purpose digital I/O
P6.1/SD4DIO/S39
P6.2/SD5DIO/S38
P6.3/SD6DIO/S37
46
47
48
I/O SD24_B converter 4 bit-stream data input/output (not available in F674xA devices)
LCD segment output S39
General-purpose digital I/O
I/O SD24_B converter 5 bit-stream data input/output (not available in F674xA devices)
LCD segment output S38
General-purpose digital I/O
I/O SD24_B converter 6 bit-stream data input/output (not available in F676xA, F674xA devices)
LCD segment output S37
General-purpose digital I/O
I/O
P6.4/S36
P6.5/S35
49
50
LCD segment output S36
General-purpose digital I/O
I/O
LCD segment output S35
14
Terminal Configuration and Functions
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 4-3. Terminal Functions – PEU Package (continued)
TERMINAL
NAME
NO. I/O(1)
PEU
DESCRIPTION
General-purpose digital I/O
LCD segment output S34
General-purpose digital I/O
LCD segment output S33
General-purpose digital I/O
LCD segment output S32
General-purpose digital I/O
LCD segment output S31
General-purpose digital I/O
LCD segment output S30
General-purpose digital I/O
LCD segment output S29
General-purpose digital I/O
LCD segment output S28
General-purpose digital I/O
LCD segment output S27
General-purpose digital I/O
LCD segment output S26
General-purpose digital I/O
LCD segment output S25
General-purpose digital I/O
LCD segment output S24
General-purpose digital I/O
LCD segment output S23
General-purpose digital I/O
LCD segment output S22
General-purpose digital I/O
LCD segment output S21
General-purpose digital I/O
LCD segment output S20
General-purpose digital I/O
LCD segment output S19
General-purpose digital I/O
LCD segment output S18
General-purpose digital I/O
LCD segment output S17
Digital power supply for I/Os
Digital ground supply
P6.6/S34
P6.7/S33
P7.0/S32
P7.1/S31
P7.2/S30
P7.3/S29
P7.4/S28
P7.5/S27
P7.6/S26
P7.7/S25
P8.0/S24
P8.1/S23
P8.2/S22
P8.3/S21
P8.4/S20
P8.5/S19
P8.6/S18
P8.7/S17
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDSYS2(3)
DVSS2
69
70
General-purpose digital I/O
LCD segment output S16
General-purpose digital I/O
LCD segment output S15
General-purpose digital I/O
LCD segment output S14
P9.0/S16
P9.1/S15
P9.2/S14
71
72
73
I/O
I/O
I/O
(3) The pins VDSYS1 and VDSYS2 must be connected externally on board for proper device operation.
Terminal Configuration and Functions
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 4-3. Terminal Functions – PEU Package (continued)
TERMINAL
NO. I/O(1)
PEU
DESCRIPTION
NAME
General-purpose digital I/O
LCD segment output S13
General-purpose digital I/O
LCD segment output S12
General-purpose digital I/O
LCD segment output S11
General-purpose digital I/O
LCD segment output S10
General-purpose digital I/O
LCD segment output S9
General-purpose digital I/O
LCD segment output S8
General-purpose digital I/O
LCD segment output S7
General-purpose digital I/O
LCD segment output S6
General-purpose digital I/O
LCD segment output S5
General-purpose digital I/O
LCD segment output S4
General-purpose digital I/O
LCD segment output S3
General-purpose digital I/O
LCD segment output S2
General-purpose digital I/O
LCD segment output S1
General-purpose digital I/O
LCD segment output S0
General-purpose digital I/O
P9.3/S13
P9.4/S12
P9.5/S11
P9.6/S10
P9.7/S9
74
75
76
77
78
79
80
81
82
83
84
85
86
87
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P10.0/S8
P10.1/S7
P10.2/S6
P10.3/S5
P10.4/S4
P10.5/S3
P10.6/S2
P10.7/S1
P11.0/S0
P11.1/TA3.1/CB3
88
I/O Timer TA3 capture CCR1: CCI1A input, compare: Out1 output
Comparator_B input CB3
General-purpose digital I/O
P11.2/TA1.1
P11.3/TA2.1
P11.4/CBOUT
89
90
91
I/O
Timer TA1 capture CCR1: CCI1A input, compare: Out1 output
General-purpose digital I/O
I/O
Timer TA2 capture CCR1: CCI1A input, compare: Out1 output
General-purpose digital I/O
I/O
Comparator_B output
General-purpose digital I/O
P11.5/TACLK/RTCCLK
P2.0/PM_TA0.0/BSL_TX
92
93
I/O Timer clock input TACLK for TA0, TA1, TA2, TA3
RTCCLK clock output
General-purpose digital I/O with port interrupt and mappable secondary function
I/O Default mapping: Timer TA0 capture CCR0: CCI0A input, compare: Out0 output
Bootloader: Data transmit
16
Terminal Configuration and Functions
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 4-3. Terminal Functions – PEU Package (continued)
TERMINAL
NO. I/O(1)
PEU
DESCRIPTION
NAME
General-purpose digital I/O with port interrupt and mappable secondary function
P2.1/PM_TA0.1/BSL_RX
94
I/O Default mapping: Timer TA0 capture CCR1: CCI1A input, compare: Out1 output
Bootloader: Data receive
General-purpose digital I/O with port interrupt and mappable secondary function
P2.2/PM_TA0.2
P2.3/PM_TA1.0
TEST/SBWTCK
PJ.0/TDO
95
96
97
98
I/O
Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2 output
General-purpose digital I/O port interrupt and with mappable secondary function
I/O
Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0 output
Test mode pin – select digital I/O on JTAG pins
I
Spy-Bi-Wire input clock
General-purpose digital I/O
I/O
Test data output
General-purpose digital I/O
I/O Test data input
PJ.1/TDI/TCLK
99
Test clock input
General-purpose digital I/O
PJ.2/TMS
PJ.3/TCK
100
101
I/O
Test mode select
General-purpose digital I/O
I/O
Test clock
Reset input, active-low(4)
I/O Nonmaskable interrupt input
Spy-By-Wire data input/output
RST/NMI/SBWTDIO
102
SD0P0
SD0N0
SD1P0
SD1N0
SD2P0
SD2N0
SD3P0
SD3N0
103
104
105
106
107
108
109
110
I
I
I
I
I
I
I
I
SD24_B positive analog input for converter 0(5)
SD24_B negative analog input for converter 0(5)
SD24_B positive analog input for converter 1(5)
SD24_B negative analog input for converter 1(5)
SD24_B positive analog input for converter 2(5)
SD24_B negative analog input for converter 2(5)
SD24_B positive analog input for converter 3(5)
SD24_B negative analog input for converter 3(4)
Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended
VASYS2
111
capacitor value of CVSYS
.
AVSS2
VREF
112
113
114
115
116
117
118
119
120
121
Analog ground supply
I
I
I
I
I
I
I
SD24_B external reference voltage
SD4P0
SD4N0
SD5P0
SD5N0
SD6P0
SD6N0
AVSS1
AVCC
SD24_B positive analog input for converter 4(5) (not available on F674xA devices)
SD24_B negative analog input for converter 4(5) (not available on F674xA devices)
SD24_B positive analog input for converter 5(5) (not available on F674xA devices)
SD24_B negative analog input for converter 5(5) (not available on F674xA devices)
SD24_B positive analog input for converter 6(5) (not available on F676xA, F674xA devices)
SD24_B negative analog input for converter 6(5) (not available on F676xA, F674xA devices)
Analog ground supply
Analog power supply
Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended
VASYS1
122
123
capacitor value of CVSYS
.
AUXVCC2
Auxiliary power supply AUXVCC2
(4) When this pin is configured as reset, the internal pullup resistor is enabled by default.
(5) TI recommends shorting unused analog input pairs and connecting them to analog ground.
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Terminal Configuration and Functions
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 4-3. Terminal Functions – PEU Package (continued)
TERMINAL
NO. I/O(1)
PEU
DESCRIPTION
NAME
AUXVCC1
VDSYS1(3)
124
Auxiliary power supply AUXVCC1
Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect recommended
125
capacitor value of CVSYS
Digital power supply
Digital ground supply
.
DVCC
126
127
128
DVSS1
VCORE(6)
Regulated core power supply (internal use only, no external current loading)
(6) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE
.
18
Terminal Configuration and Functions
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 4-4 describes the signals for devices in the PZ package. See Table 4-3 for the signals in the PEU
package.
Table 4-4. Terminal Functions – PZ Package
TERMINAL
NO. I/O(1)
PZ
DESCRIPTION
SD24_B positive analog input for converter 0(2)
SD24_B negative analog input for converter 0(2)
SD24_B positive analog input for converter 1(2)
SD24_B negative analog input for converter 1(2)
SD24_B positive analog input for converter 2(2)
SD24_B negative analog input for converter 2(2)
SD24_B positive analog input for converter 3(2)
NAME
SD0P0
SD0N0
SD1P0
SD1N0
SD2P0
SD2N0
SD3P0
SD3N0
1
2
3
4
5
6
7
8
I
I
I
I
I
I
I
I
SD24_B negative analog input for converter 3(2)
Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended
VASYS2
9
capacitor value of CVSYS
.
AVSS2
VREF
10
11
12
13
14
15
16
17
18
19
Analog ground supply
I
I
I
I
I
I
I
SD24_B external reference voltage
SD4P0
SD4N0
SD5P0
SD5N0
SD6P0
SD6N0
AVSS1
AVCC
SD24_B positive analog input for converter 4(2) (not available on F674x devices)
SD24_B negative analog input for converter 4(2) (not available on F674xA devices)
SD24_B positive analog input for converter 5(2) (not available on F674xA devices)
SD24_B negative analog input for converter 5(2) (not available on F674xA devices)
SD24_B positive analog input for converter 6(2) (not available on F676xA, F674xA devices)
SD24_B negative analog input for converter 6(2) (not available on F676xA, F674xA devices)
Analog ground supply
Analog power supply
Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended
capacitor value of CVSYS
VASYS1
20
AUXVCC2
AUXVCC1
21
22
Auxiliary power supply AUXVCC2
Auxiliary power supply AUXVCC1
Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect recommended
(3)
VDSYS1
23
capacitor value of CVSYS
Digital power supply
Digital ground supply
.
DVCC
DVSS1
VCORE
XIN
24
25
26
27
28
29
30
31
(4)
Regulated core power supply (internal use only, no external current loading)
I/O Input terminal for crystal oscillator
XOUT
I/O Output terminal for crystal oscillator
AUXVCC3
RTCCAP1
RTCCAP0
Auxiliary power supply AUXVCC3 for backup subsystem
I
I
External time capture pin 1 for RTC_C
External time capture pin 0 for RTC_C
General-purpose digital I/O with port interrupt
SMCLK clock output
P1.5/SMCLK/CB0/A5
32
I/O
Comparator_B input CB0
Analog input A5 for 10-bit ADC
(1) I = input, O = output
(2) TI recommends shorting unused analog input pairs and connecting them to analog ground.
(3) The pins VDSYS1 and VDSYS2 must be connected externally on board for proper device operation.
(4) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE
.
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Terminal Configuration and Functions
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 4-4. Terminal Functions – PZ Package (continued)
TERMINAL
NO. I/O(1)
PZ
DESCRIPTION
NAME
General-purpose digital I/O with port interrupt
MCLK clock output
P1.4/MCLK/CB1/A4
33
I/O
Comparator_B input CB1
Analog input A4 for 10-bit ADC
General-purpose digital I/O with port interrupt
P1.3/ADC10CLK/A3
P1.2/ACLK/A2
34
35
I/O ADC10_A clock output
Analog input A3 for 10-bit ADC
General-purpose digital I/O with port interrupt
I/O ACLK clock output
Analog input A2 for 10-bit ADC
General-purpose digital I/O with port interrupt
Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output
I/O Comparator_B Output
P1.1/TA2.1/CBOUT/
VeREF+/A1
36
Positive terminal for the ADC reference voltage for an external applied reference voltage
Analog input A1 for 10-bit ADC
General-purpose digital I/O with port interrupt
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output
Negative terminal for the ADC reference voltage for an external applied reference voltage
Analog input A0 for 10-bit ADC
P1.0/TA1.1/VeREF-/A0
37
I/O
COM0
COM1
38
39
I/O LCD common output COM0 for LCD backplane
I/O LCD common output COM1 for LCD backplane
General-purpose digital I/O with port interrupt
I/O
P1.6/COM2
P1.7/COM3
40
41
LCD common output COM2 for LCD backplane
General-purpose digital I/O with port interrupt
I/O
LCD common output COM3 for LCD backplane
General-purpose digital I/O with port interrupt and mappable secondary function
Default Mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
P2.0/PM_TA0.0/
BSL_TX/COM4
42
43
I/O
Bootloader: Data transmit
LCD common output COM4 for LCD backplane
General-purpose digital I/O with port interrupt and mappable secondary function
Default Mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
P2.1/PM_TA0.1/
BSL_RX/COM5
I/O
Bootloader: Data receive
LCD common output COM5 for LCD backplane
General-purpose digital I/O with port interrupt and mappable secondary function
I/O Default Mapping: Timer TA0 CCR0 capture: CCI2A input, compare: Out2 output
LCD common output COM6 for LCD backplane
P2.2/PM_TA0.2/COM6
P2.3/PM_TA1.0/COM7
LCDCAP/R33
44
45
46
47
General-purpose digital I/O with port interrupt and mappable secondary function
I/O Default Mapping: Timer TA1 CCR0 capture: CCI0A input, compare: Out0 output
LCD common output COM7 for LCD backplane
LCD capacitor connection
I/O Input/output port of most positive analog LCD voltage (V1)
CAUTION: This pin must be connected to DVSS if not used.
General-purpose digital I/O with port interrupt and mappable secondary function
I/O Default Mapping: Timer TA2 CCR0 capture: CCI0A input, compare: Out0 output
Input/output port of second most positive analog LCD voltage (V2)
P2.4/PM_TA2.0/R23
20
Terminal Configuration and Functions
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 4-4. Terminal Functions – PZ Package (continued)
TERMINAL
NO. I/O(1)
PZ
DESCRIPTION
NAME
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_B0 SPI slave out, master in
I/O Default mapping: eUSCI_B0 I2C clock
P2.5/PM_UCB0SOMI/
PM_UCB0SCL/LCDREF/
R13
48
49
External reference voltage input for regulated LCD voltage
Input/output port of third most positive analog LCD voltage (V3 or V4)
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_B0 SPI slave in, master out
Default mapping: eUSCI_B0 I2C data
P2.6/PM_UCB0SIMO/
PM_UCB0SDA/R03
I/O
Input/output port of lowest analog LCD voltage (V5)
General-purpose digital I/O with port interrupt and mappable secondary function
I/O Default mapping: eUSCI_B0 clock input/output
Comparator_B input CB2
P2.7/PM_UCB0CLK/CB2
50
51
General-purpose digital I/O with mappable secondary function
I/O Default mapping: eUSCI_A0 UART receive data
Default mapping: eUSCI_A0 SPI slave out, master in
General-purpose digital I/O with mappable secondary function
P3.0/PM_UCA0RXD/
PM_UCA0SOMI
Default mapping: eUSCI_A0 UART transmit data
P3.1/PM_UCA0TXD/
PM_UCA0SIMO/S39
52
I/O
Default mapping: eUSCI_A0 SPI slave in, master out
LCD segment output S39
General-purpose digital I/O with mappable secondary function
I/O Default mapping: eUSCI_A0 clock input/output
LCD segment output S38
P3.2/PM_UCA0CLK/S38
P3.3/PM_UCA1CLK/S37
53
54
General-purpose digital I/O with mappable secondary function
I/O Default mapping: eUSCI_A1 clock input/output
LCD segment output S37
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A1 UART receive data
I/O
P3.4/PM_UCA1RXD/
PM_UCA1SOMI/S36
55
56
57
Default mapping: eUSCI_A1 SPI slave out, master in
LCD segment output S36
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A1 UART transmit data
P3.5/PM_UCA1TXD/
PM_UCA1SIMO/S35
I/O
Default mapping: eUSCI_A1 SPI slave in, master out
LCD segment output S35
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A2 UART receive data
I/O
P3.6/PM_UCA2RXD/
PM_UCA2SOMI/S34
Default mapping: eUSCI_A2 SPI slave out, master in
LCD segment output S34
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A2 UART transmit data
P3.7/PM_UCA2TXD/
PM_UCA2SIMO/S33
58
59
I/O
Default mapping: eUSCI_A2 SPI slave in, master out
LCD segment output S33
General-purpose digital I/O with mappable secondary function
I/O Default mapping: eUSCI_A2 clock input/output
LCD segment output S32
P4.0/PM_UCA2CLK/S32
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Terminal Configuration and Functions
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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Table 4-4. Terminal Functions – PZ Package (continued)
TERMINAL
NO. I/O(1)
PZ
DESCRIPTION
NAME
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A3 UART receive data
Default mapping: eUSCI_A3 SPI slave out, master in
LCD segment output S31
P4.1/PM_UCA3RXD/
PM_UCA3SOMI/S31
60
I/O
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A3 UART transmit data
Default mapping: eUSCI_A3 SPI slave in, master out
LCD segment output S30
P4.2/PM_UCA3TXD/
PM_UCA3SIMO/S30
61
62
63
General-purpose digital I/O with mappable secondary function
P4.3/PM_UCA3CLK/S29
I/O Default mapping: eUSCI_A3 clock input/output
LCD segment output S29
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_B1 SPI slave out, master in
Default mapping: eUSCI_B1 I2C clock
P4.4/PM_UCB1SOMI/
PM_UCB1SCL/S28
I/O
LCD segment output S28
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_B1 SPI slave in, master out
Default mapping: eUSCI_B1 I2C data
P4.5/PM_UCB1SIMO/
PM_UCB1SDA/S27
64
I/O
LCD segment output S27
General-purpose digital I/O with mappable secondary function
I/O Default mapping: eUSCI_B1 clock input/output
LCD segment output S26
P4.6/PM_UCB1CLK/S26
P4.7/PM_TA3.0/S25
P5.0/SDCLK/S24
65
66
67
68
69
70
71
General-purpose digital I/O with mappable secondary function
I/O Default Mapping: Timer TA3 CCR0 capture: CCI0A input, compare: Out0 output
LCD segment output S25
General-purpose digital I/O
I/O SD24_B bit-stream clock input/output
LCD segment output S24
General-purpose digital I/O
P5.1/PM_SD0DIO/S23
P5.2/PM_SD1DIO/S22
P5.3/PM_SD2DIO/S21
P5.4/PM_SD3DIO/S20
I/O Default mapping: SD24_B converter 0 bit-stream data input/output
LCD segment output S23
General-purpose digital I/O
I/O Default mapping: SD24_B converter 1 bit-stream data input/output
LCD segment output S22
General-purpose digital I/O
I/O Default mapping: SD24_B converter 2 bit-stream data input/output
LCD segment output S21
General-purpose digital I/O
I/O Default mapping: SD24_B converter 3 bit-stream data input/output
LCD segment output S20
General-purpose digital I/O
Default mapping: SD24_B converter 4 bit-stream data input/output (not available on F674xA
devices)
P5.5/PM_SD4DIO/S19
72
I/O
LCD segment output S19
22
Terminal Configuration and Functions
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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Table 4-4. Terminal Functions – PZ Package (continued)
TERMINAL
NO. I/O(1)
PZ
DESCRIPTION
NAME
General-purpose digital I/O
Default mapping: SD24_B converter 5 bit-stream data input/output (not available on F674xA
devices)
P5.6/PM_SD5DIO/S18
73
74
I/O
I/O
LCD segment output S18
General-purpose digital I/O
Default mapping: SD24_B converter 6 bit-stream data input/output (not available on F676xA or
F674xA devices)
P5.7/PM_SD6DIO/S17
LCD segment output S17
Digital power supply for I/Os
Digital ground supply
VDSYS2(3)
DVSS2
75
76
General-purpose digital I/O
LCD segment output S16
General-purpose digital I/O
LCD segment output S15
General-purpose digital I/O
LCD segment output S14
General-purpose digital I/O
LCD segment output S13
General-purpose digital I/O
LCD segment output S12
General-purpose digital I/O
LCD segment output S11
General-purpose digital I/O
LCD segment output S10
General-purpose digital I/O
LCD segment output S9
General-purpose digital I/O
LCD segment output S8
General-purpose digital I/O
LCD segment output S7
General-purpose digital I/O
LCD segment output S6
General-purpose digital I/O
LCD segment output S5
General-purpose digital I/O
LCD segment output S4
General-purpose digital I/O
LCD segment output S3
General-purpose digital I/O
LCD segment output S2
General-purpose digital I/O
LCD segment output S1
General-purpose digital I/O
LCD segment output S0
P6.0/S16
P6.1/S15
P6.2/S14
P6.3/S13
P6.4/S12
P6.5/S11
P6.6/S10
P6.7/S9
P7.0/S8
P7.1/S7
P7.2/S6
P7.3/S5
P7.4/S4
P7.5/S3
P7.6/S2
P7.7/S1
P8.0/S0
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
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Terminal Configuration and Functions
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
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Table 4-4. Terminal Functions – PZ Package (continued)
TERMINAL
NO. I/O(1)
PZ
DESCRIPTION
NAME
General-purpose digital I/O
Timer clock input TACLK for TA0, TA1, TA2, TA3
RTCCLK clock output
P8.1/TACLK/RTCCLK/CB3
94
I/O
Comparator_B input CB3
Test mode pin – select digital I/O on JTAG pins
Spy-By-Wire input clock
TEST/SBWTCK
PJ.0/TDO
95
96
97
98
99
I
General-purpose digital I/O
Test data output
I/O
I/O
I/O
I/O
General-purpose digital I/O
Test data input or Test clock input
General-purpose digital I/O
Test mode select
PJ.1/TDI/TCLK
PJ.2/TMS
General-purpose digital I/O
Test clock
PJ.3/TCK
Reset input active low(5)
RST/NMI/SBWTDIO
100
I/O Nonmaskable interrupt input
Spy-By-Wire data input/output
(5) When this pin is configured as reset, the internal pullup resistor is enabled by default.
24
Terminal Configuration and Functions
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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4.3 Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and schematics of the
multiplexed ports, see Section 6.12.
4.4 Connection of Unused Pins
Table 4-5 lists the correct termination of unused pins.
Table 4-5. Connection of Unused Pins(1)
PIN
POTENTIAL
DVCC
COMMENT
AVCC
AVSS
DVSS
Switched to port function, output direction (PxDIR.n = 1). Px.y represents port x and bit y
of port x (for example, P1.0, P1.1, P2.2, PJ.0, PJ.1)
Px.y
XIN
Open
DVSS
Open
For dedicated XIN pins only. XIN pins with shared GPIO functions should be
programmed to GPIO and follow Px.y recommendations.
For dedicated XOUT pins only. XOUT pins with shared GPIO functions should be
programmed to GPIO and follow Px.y recommendations.
XOUT
LCDCAP
RST/NMI
DVSS
DVCC or VCC
47-kΩ pullup or internal pullup selected with 10-nF (2.2 nF) pulldown(2)
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK
The JTAG pins are shared with general-purpose I/O function (PJ.x). If not being used,
these should be switched to port function, output direction (PJDIR.n = 1). When used as
JTAG pins, these pins should remain open.
Open
Open
TEST
This pin always has an internal pulldown enabled.
(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.y unused pin connection
guidelines.
(2) The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG
mode with TI tools such as FET interfaces or GANG programmers.
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Terminal Configuration and Functions
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
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5 Specifications
All graphs in this section are for typical conditions, unless otherwise noted.
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Voltage applied at DVCC to DVSS
Voltage applied to pins(2)
–0.3
4.1
V
All pins except VCORE(3), SD24_B input pins (SDxN0, SDxP0)(4)
AUXVCC1, AUXVCC2, and AUXVCC3(5)
,
–0.3
VCC + 0.3
V
All pins except SD24_B input pins (SDxN0, SDxP0)
±2
2
Diode current at pins
mA
SD0N0, SD0P0, SD1N0, SD1P0, SD2N0, SD2P0, SD3N0, SD3P0,
SD4N0, SD4P0, SD5N0, SD5P0, SD6N0, SD6P0(6)
Maximum junction temperature, TJ
95
°C
°C
(7)
Storage temperature, Tstg
–55
105
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS = VDVSS = VAVSS
.
(3) VCORE is for internal device use only. No external DC loading or voltage should be applied.
(4) See Table 5-39 for SD24_B specifications.
(5) See Table 5-18 for AUX specifications.
(6) A protection diode is connected to VCC for the SD24_B input pins. No protection diode is connected to VSS
.
(7) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3 Recommended Operating Conditions
MIN NOM
MAX UNIT
PMMCOREVx = 0
1.8
2.0
2.2
2.4
0
3.6
PMMCOREVx = 0, 1
PMMCOREVx = 0, 1,3 2
PMMCOREVx = 0, 1, 2, 3
3.6
V
Supply voltage during program execution and flash
VCC
(1)(2)
programming (VAVCC = VDVCC = VCC
)
3.6
3.6
V
VSS
TA
Supply voltage VAVSS = VDVSS = VSS
Operating free-air temperature
I version
I version
–40
–40
470
85
85
°C
°C
nF
TJ
Operating junction temperature
Recommended capacitor at VCORE
CVCORE
CDVCC
CVCORE
/
Capacitor ratio of DVCC to VCORE
10
(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between V(AVCC) and V(DVCC) can be
tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Table 5-14 threshold parameters for
the exact values and further details.
26
Specifications
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MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
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Recommended Operating Conditions (continued)
MIN NOM
MAX UNIT
PMMCOREVx = 0,
1.8 V ≤ VCC ≤ 3.6 V
(default condition)
0
8.0
PMMCOREVx = 1,
2 V ≤ VCC ≤ 3.6 V
Processor frequency (maximum MCLK frequency)(3) (4)
(see Figure 5-1)
0
0
0
12.0
MHz
fSYSTEM
PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V
20.0
25.0
PMMCOREVx = 3,
2.4 V ≤ VCC ≤ 3.6 V
Maximum load current that can be drawn from DVCC for core and IO
(ILOAD = ICORE + IIO
ILOAD, DVCCD
ILOAD, AUX1D
ILOAD, AUX2D
ILOAD, AVCCA
ILOAD, AUX1A
20
20
20
10
5
mA
mA
mA
mA
mA
)
Maximum load current that can be drawn from AUXVCC1 for core and IO
(ILOAD = ICORE + IIO
)
Maximum load current that can be drawn from AUXVCC2 for core and IO
(ILOAD = ICORE + IIO
)
Maximum load current that can be drawn from AVCC for analog modules
(ILOAD = IModules
)
Maximum load current that can be drawn from AUXVCC1 for analog modules
(ILOAD = IModules
)
Maximum load current that can be drawn from AUXVCC2 for analog modules
(ILOAD = IModules
ILOAD, AUX2A
PINT
5
mA
W
)
Internal power dissipation
VCC x I(DVCC)
(VCC – VIOH) x IIOH
VIOL x IIOL
+
PIO
I/O power dissipation of the I/O pins powered by DVCC
Maximum allowed power dissipation, PMAX > PIO + PINT
W
PMAX
(TJ – TA) / θJA
W
(3) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
(4) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
25
3
20
2, 3
2
12
8
1, 2
1, 2, 3
1
0
0, 1
0, 1, 2
0, 1, 2, 3
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
The numbers within the fields denote the supported PMMCOREVx settings.
Figure 5-1. Maximum System Frequency
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Specifications
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MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
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5.4 Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted)(1)(2)(3)
FREQUENCY (fDCO = fMCLK = fSMCLK
)
EXECUTION
MEMORY
PMMCOREV
x
PARAMETER
VCC
1 MHz
8 MHz
12 MHz
20 MHz
TYP
25 MHz
UNIT
TYP MAX
TYP MAX
TYP MAX
MAX
TYP
8.67
4.44
MAX
0
1
2
3
0
1
2
3
0.32
0.35
0.39
0.41
0.19
0.21
0.23
0.24
0.50
2.08
2.35
2.68
2.83
1.04
1.20
1.38
1.47
2.84
3.50
3.99
4.22
4.76
(4)
IAM, Flash
Flash
RAM
3 V
mA
6.61
6.98
8.3
11.75
1.77
2.04
2.18
(5)
IAM, RAM
3 V
mA
3.35
3.58
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1 V-T1K crystal with a load capacitance of 12.5 pF. The internal and external
load capacitance are chosen to closely match the required 12.5 pF.
(3) Characterized with program executing typical data processing.
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.
(4) Active mode supply current when program executes in flash at a nominal supply voltage of 3.0 V.
(5) Active mode supply current when program executes in RAM at a nominal supply voltage of 3.0 V.
28
Specifications
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
TEMPERATURE (TA)
PARAMETER
VCC
PMMCOREVx
–40°C
TYP
25°C
TYP
85°C
TYP
UNIT
MAX
MAX
105
18
MAX
130
30
2.2 V
3 V
0
3
0
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
70
81
75
87
86
100
12.5
13.8
7.8
8.3
8.6
8.6
8.5
9.0
9.3
9.3
7.5
7.9
8.2
8.2
7.4
7.8
7.9
8.0
1.4
1.8
1.2
ILPM0,1MHz
Low-power mode 0(3) (4)
Low-power mode 2(5) (4)
µA
µA
2.2 V
3 V
5.9
6.7
1.50
1.65
1.80
1.84
2.0
2.1
2.3
2.3
1.3
1.3
1.4
1.4
1.2
1.2
1.3
1.3
0.7
1.0
0.6
6.5
7.3
2.0
2.2
2.4
2.4
2.5
2.7
2.9
2.9
1.7
1.8
1.9
1.9
1.6
1.7
1.7
1.7
0.9
1.2
0.7
ILPM2
Low-power mode 3, crystal
mode(6) (4)
ILPM3,XT1LF
ILPM3,XT1LF
ILPM3,VLO
ILPM4
2.2 V
3 V
µA
µA
µA
µA
Low-power mode 3, crystal
mode(6) (4)
25
25.0
23.0
Low-power mode 3,
VLO mode(7) (4)
3 V
Low-power mode 4(8) (4)
3 V
2.2 V
3 V
Low-power mode 3.5, RTC
active on AUXVCC3(9)
ILPM3.5
ILPM4.5
µA
µA
1.5
1.0
3.0
2.0
Low-power mode 4.5(10)
3 V
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1 V-T1K crystal with a load capacitance of 12.5 pF. The internal and external
load capacitance are chosen to closely match the required 12.5 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
(4) Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML)
disabled. High-side monitor (SVMH) disabled. RAM retention enabled.
(5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCO setting
= 1-MHz operation, DCO bias generator enabled.
(6) Current for watchdog timer and RTC clocked by low-frequency clock included. ACLK = low frequency crystal operation (XTS = 0,
XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
(7) Current for watchdog timer and RTC clocked by low-frequency clock included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
(9) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC active on AUXVCC3 supply
(10) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 0 Hz, PMMREGOFF = 1
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Specifications
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5.6 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
TEMPERATURE (TA)
PARAMETER
VCC
PMMCOREVx
–40°C
TYP
25°C
TYP
85°C
TYP
UNIT
MAX
MAX
6.0
MAX
25.0
25.0
0
1
2
3
0
1
2
3
0
1
2
0
1
2
3
2.5
2.6
2.8
2.8
2.9
3.1
3.2
3.3
2.2
2.3
2.5
2.6
2.8
2.9
3.0
3.1
3.3
3.5
3.5
3.5
3.7
4.0
4.0
2.8
3.0
3.2
3.2
3.4
3.6
3.7
9.1
9.5
ILPM3
LCD,
ext. bias
Low-power mode 3 (LPM3)
current, LCD 4-mux mode,
external biasing(3) (4)
3 V
µA
9.9
10.0
9.7
Low-power mode 3 (LPM3)
current, LCD 4-mux mode,
internal biasing, charge
pump disabled(3) (5)
ILPM3
LCD,
int. bias
10.1
10.5
10.5
8.8
3 V
2.2 V
3 V
µA
µA
µA
5.5
9.1
Low-power mode 3 (LPM3)
current, LCD 4-mux mode,
internal biasing, charge
pump enabled(3) (6)
9.5
ILPM3
LCD,CP
9.3
9.7
10.1
10.2
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1 V-T1K crystal with a load capacitance of 12.5 pF. The internal and external
load capacitance are chosen to closely match the required 12.5 pF.
(3) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for brownout and high-side supervisor (SVSH) in normal mode included. Low-side supervisor (SVSL) and low-side monitor
(SVML) disabled. High-side monitor (SVMH) disabled. RAM retention enabled.
(4) LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Current through external resistors not included (voltage levels are supplied by test equipment).
Even segments (S0, S2, ...) = 0, and odd segments (S1, S3, ...) = 1. No LCD panel load.
(5) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments (S0, S2, ...) = 0, and odd segments (S1, S3, ...) = 1. No LCD panel load.
(6) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump
enabled), VLCDx = 1000 (VLCD = 3 V typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments (S0, S2, ...) = 0, and odd segments (S1, S3, ...) = 1. No LCD panel load.
30
Specifications
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5.7 Thermal Resistance Characteristics
THERMAL METRIC(1) (2)
VALUE
44.4
42.9
10.5
9.3
UNIT
LQFP 128 (PEU)
LQFP 100 (PZ)
LQFP 128 (PEU)
LQFP 100 (PZ)
LQFP 128 (PEU)
LQFP 100 (PZ)
LQFP 128 (PEU)
LQFP 100 (PZ)
LQFP 128 (PEU)
LQFP 100 (PZ)
LQFP 128 (PEU)
LQFP 100 (PZ)
RθJA
Junction-to-ambient thermal resistance, still air
°C/W
RθJC(TOP)
RθJC(BOTTOM)
RθJB
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
N/A(3)
Junction-to-case (bottom) thermal resistance
Junction-to-board thermal resistance
N/A
23.1
20.6
0.4
ΨJT
Junction-to-package-top thermal characterization parameter
Junction-to-board thermal characterization parameter
0.3
22.8
20.3
ΨJB
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(3) N/A = not applicable
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Specifications
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5.8 Timing and Switching Characteristics
5.8.1 Reset Timing
Table 5-1 lists the device wake-up times.
Table 5-1. Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Wake-up time from LPM2,
LPM3, or LPM4 to active
mode(1)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1
f
MCLK ≥ 4.0 MHz
5
tWAKE-UP-FAST
µs
fMCLK < 4.0 MHz
10
Wake-up time from LPM2,
LPM3, or LPM4 to active
mode(2)(3)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 0
tWAKE-UP-SLOW
150
165
µs
Wake-up time from LPM4.5
to active mode(4)
tWAKE-UP-LPM4.5
tWAKE-UP-RESET
2
2
3
3
ms
ms
Wake-up time from RST or
BOR event to active mode(4)
(1) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in full performance
mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in
the Power Management Module and Supply Voltage Supervisor chapter of the MSP430x5xx and MSP430x6xx Family User's Guide.
(2) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in normal mode (low
current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in the
Power Management Module and Supply Voltage Supervisor chapter of the MSP430x5xx and MSP430x6xx Family User's Guide.
(3) The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by the
performance mode settings as for LPM2, LPM3, and LPM4.
(4) This value represents the time from the wake-up event to the reset vector execution.
32
Specifications
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5.8.2 Clock Specifications
Table 5-2 lists the characteristics of the crystal oscillator in low-frequency mode.
Table 5-2. Crystal Oscillator, XT1, Low-Frequency Mode(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 1, TA = 25°C
0.075
Differential XT1 oscillator
crystal current consumption
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
ΔIDVCC.LF
3 V
0.170
0.290
32768
µA
from lowest drive setting, LF XT1DRIVEx = 2, TA = 25°C
mode
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 3, TA = 25°C
XT1 oscillator crystal
frequency, LF mode
fXT1,LF0
XTS = 0, XT1BYPASS = 0
Hz
XT1 oscillator logic-level
(3)
fXT1,LF,SW
square-wave input frequency, XTS = 0, XT1BYPASS = 1(2)
LF mode
10 32.768
50 kHz
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
210
300
Oscillation allowance for
LF crystals(4)
OALF
kΩ
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, XCAPx = 0(6)
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
XTS = 0, XCAPx = 3
1
5.5
Integrated effective load
capacitance, LF mode(5)
CL,eff
pF
8.5
12.0
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
Duty cycle, LF mode
30%
10
70%
Oscillator fault frequency,
LF mode(7)
fFault,LF
XTS = 0(8)
10000
Hz
ms
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 0, TA = 25°C, CL,eff = 6 pF
1000
500
tSTART,LF
Start-up time, LF mode
3 V
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 3, TA = 25°C, CL,eff = 12 pF
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
•
•
•
•
•
•
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this data sheet.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
•
•
•
•
For XT1DRIVEx = 0, CL,eff ≤ 6 pF.
For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF.
For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF.
For XT1DRIVEx = 3, CL,eff ≥ 6 pF.
(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the
effective load capacitance should always match the specification of the used crystal.
(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.
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Specifications
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Table 5-3 lists the characteristics of the VLO.
Table 5-3. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLO frequency
VLO frequency temperature drift
TEST CONDITIONS
Measured at ACLK
VCC
MIN
TYP
9.6
0.5
4
MAX UNIT
15 kHz
%/°C
fVLO
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
6
dfVLO/dT
Measured at ACLK
Measured at ACLK
Measured at ACLK
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
%/V
40%
50%
60%
Table 5-4 lists the characteristics of the REFO.
Table 5-4. Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
3
MAX UNIT
µA
IREFO
REFO oscillator current consumption TA = 25°C
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
3 V
REFO frequency calibrated
Measured at ACLK
32768
Hz
fREFO
Full temperature range
TA = 25°C
–3.5%
–1.5%
+3.5%
+1.5%
%/°C
%/V
REFO absolute tolerance calibrated
dfREFO/dT
REFO frequency temperature drift
REFO frequency supply voltage drift
Duty cycle
Measured at ACLK
Measured at ACLK
Measured at ACLK
40%/60% duty cycle
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
0.01
1.0
dfREFO/dVCC
40%
50%
25
60%
tSTART
REFO start-up time
µs
34
Specifications
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Table 5-5 lists the frequency characteristics of the DCO.
Table 5-5. DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-2)
PARAMETER
TEST CONDITIONS
DCORSELx = 0, DCOx = 0, MODx = 0
DCORSELx = 0, DCOx = 31, MODx = 0
DCORSELx = 1, DCOx = 0, MODx = 0
DCORSELx = 1, DCOx = 31, MODx = 0
DCORSELx = 2, DCOx = 0, MODx = 0
DCORSELx = 2, DCOx = 31, MODx = 0
DCORSELx = 3, DCOx = 0, MODx = 0
DCORSELx = 3, DCOx = 31, MODx = 0
DCORSELx = 4, DCOx = 0, MODx = 0
DCORSELx = 4, DCOx = 31, MODx = 0
DCORSELx = 5, DCOx = 0, MODx = 0
DCORSELx = 5, DCOx = 31, MODx = 0
DCORSELx = 6, DCOx = 0, MODx = 0
DCORSELx = 6, DCOx = 31, MODx = 0
DCORSELx = 7, DCOx = 0, MODx = 0
DCORSELx = 7, DCOx = 31, MODx = 0
MIN
0.07
0.70
0.15
1.47
0.32
3.17
0.64
6.07
1.3
TYP
MAX UNIT
0.20 MHz
1.70 MHz
0.36 MHz
3.45 MHz
0.75 MHz
7.38 MHz
1.51 MHz
14.0 MHz
3.2 MHz
fDCO(0,0)
fDCO(0,31)
fDCO(1,0)
fDCO(1,31)
fDCO(2,0)
fDCO(2,31)
fDCO(3,0)
fDCO(3,31)
fDCO(4,0)
fDCO(4,31)
fDCO(5,0)
fDCO(5,31)
fDCO(6,0)
fDCO(6,31)
fDCO(7,0)
fDCO(7,31)
DCO frequency (0, 0)(1)
DCO frequency (0, 31)(1)
DCO frequency (1, 0)(1)
DCO frequency (1, 31)(1)
DCO frequency (2, 0)(1)
DCO frequency (2, 31)(1)
DCO frequency (3, 0)(1)
DCO frequency (3, 31)(1)
DCO frequency (4, 0)(1)
DCO frequency (4, 31)(1)
DCO frequency (5, 0)(1)
DCO frequency (5, 31)(1)
DCO frequency (6, 0)(1)
DCO frequency (6, 31)(1)
DCO frequency (7, 0)(1)
DCO frequency (7, 31)(1)
12.3
2.5
28.2 MHz
6.0 MHz
23.7
4.6
54.1 MHz
10.7 MHz
88.0 MHz
19.6 MHz
135 MHz
39.0
8.5
60
Frequency step between range
DCORSEL and DCORSEL + 1
SDCORSEL
SDCO
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
1.2
2.3 ratio
Frequency step between tap
DCO and DCO + 1
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
Measured at SMCLK
1.02
40%
1.12 ratio
Duty cycle
50%
0.1
60%
%/°C
%/V
dfDCO/dT
DCO frequency temperature drift fDCO = 1 MHz
DCO frequency voltage drift fDCO = 1 MHz
dfDCO/dVCORE
1.9
(1) When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the
range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap
31 (DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual
fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the
selected range is at its minimum or maximum tap setting.
100
VCC = 3.0 V
TA = 25°C
10
DCOx = 31
1
DCOx = 0
0.1
0
1
2
3
4
5
6
7
DCORSEL
Figure 5-2. Typical DCO Frequency
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Specifications
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5.9 Digital I/Os
Table 5-6 lists the input characteristics of the Schmitt-trigger GPIOs.
Table 5-6. Schmitt-Trigger Inputs – General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.8 V
3 V
MIN
0.80
1.50
0.45
0.75
0.3
TYP
MAX UNIT
1.40
V
VIT+
VIT–
Vhys
Positive-going input threshold voltage
2.10
1.8 V
3 V
1.00
V
Negative-going input threshold voltage
1.65
1.8 V
3 V
0.85
V
Input voltage hysteresis (VIT+ – VIT–
)
0.4
1.0
For pullup: VIN = VSS
For pulldown: VIN = VCC
,
RPull
CI
Pullup or pulldown resistor
Input capacitance
20
35
5
50
kΩ
VIN = VSS or VCC
pF
Table 5-7 lists the input characteristics of the GPIOs.
Table 5-7. Inputs – Ports P1 and P2(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Port P1, P2: P1.x to P2.x, External trigger pulse duration
to set interrupt flag
t(int)
External interrupt timing(2)
2.2 V, 3 V
20
ns
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int)
.
Table 5-8 lists the leakage characteristics of the GPIOs.
Table 5-8. Leakage Current – General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
+50 nA
(1)(2)
Ilkg(Px.y)
High-impedance leakage current
1.8 V, 3 V
–50
(1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
36
Specifications
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Table 5-9 lists the output characteristics of the GPIOs in full drive strength mode.
Table 5-9. Outputs – General-Purpose I/O (Full Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Section 5.9.2)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA(1)
VCC
MIN
1.55
1.20
2.75
2.40
0.00
0.00
0.00
0.00
MAX UNIT
1.80
1.8 V
I(OHmax) = –10 mA(1)
I(OHmax) = –5 mA(1)
I(OHmax) = –15 mA(1)
I(OLmax) = 3 mA(2)
I(OLmax) = 10 mA(3)
I(OLmax) = 5 mA(2)
I(OLmax) = 15 mA(3)
1.80
V
VOH
High-level output voltage
3.00
3 V
1.8 V
3 V
3.00
0.25
0.60
V
VOL
Low-level output voltage
0.25
0.60
(1) The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified.
See Section 5.3 for more details.
(2) The maximum total current, I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified.
(3) The maximum total current, I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified.
Table 5-10 lists the output characteristics of the GPIOs in reduced drive strength mode.
Table 5-10. Outputs – General-Purpose I/O (Reduced Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (see
Section 5.9.1)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA(2)
VCC
MIN
1.55
1.20
2.75
2.40
0.00
0.00
0.00
0.00
MAX UNIT
1.80
1.8 V
I(OHmax) = –3 mA(2)
I(OHmax) = –2 mA(2)
I(OHmax) = –6 mA(2)
I(OLmax) = 1 mA(3)
I(OLmax) = 3 mA(4)
I(OLmax) = 2 mA(3)
I(OLmax) = 6 mA(4)
1.80
V
VOH
High-level output voltage
3.00
3 V
1.8 V
3 V
3.00
0.25
0.60
V
VOL
Low-level output voltage
0.25
0.60
(1) Selecting reduced drive strength may reduce EMI.
(2) The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified.
See Section 5.3 for more details.
(3) The maximum total current, I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified.
(4) The maximum total current, I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage drop specified.
Table 5-11 lists the output frequency of the GPIOs.
Table 5-11. Output Frequency – General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
VCC = 1.8 V,
PMMCOREVx = 0
16
(1) (2)
fPx.y
Port output frequency (with load)
See
MHz
25
VCC = 3 V,
PMMCOREVx = 3
VCC = 1.8 V,
PMMCOREVx = 0
ACLK
16
SMCLK
MCLK
fPort_CLK
Clock output frequency
MHz
25
VCC = 3 V,
PMMCOREVx = 3
CL = 20 pF(2)
(1) A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS
.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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Specifications
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5.9.1 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
20
8
7
6
5
4
3
2
1
0
18
16
14
12
10
8
TA = 25°C
TA = 25°C
TA = 85°C
TA = 85°C
6
4
2
0
0
0.5
1
1.5
2
2.5
3
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
VCC = 3 V
Reduced drive strength
VCC = 1.8 V
Reduced drive strength
Figure 5-3. Typical Low-Level Output Current vs
Low-Level Output Voltage
Figure 5-4. Typical Low-Level Output Current vs
Low-Level Output Voltage
0
-5
0
-1
-2
-3
-4
-5
-6
-7
-8
-10
-15
-20
-25
TA = 85°C
TA = 25°C
TA = 85°C
TA = 25°C
0
0.5
1
1.5
2
2.5
3
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
VCC = 3 V
Reduced drive strength
VCC = 1.8 V
Reduced drive strength
Figure 5-5. Typical High-Level Output Current vs
High-Level Output Voltage
Figure 5-6. Typical High-Level Output Current vs
High-Level Output Voltage
38
Specifications
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5.9.2 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
60
50
40
30
20
10
0
25
20
15
10
5
TA = 25°C
TA = 25°C
TA = 85°C
TA = 85°C
0
0
0.5
1
1.5
2
2.5
3
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
VCC = 3 V
Full drive strength
VCC = 1.8 V
Full drive strength
Figure 5-7. Typical Low-Level Output Current vs
Low-Level Output Voltage
Figure 5-8. Typical Low-Level Output Current vs
Low-Level Output Voltage
0
-10
-20
-30
-40
-50
-60
0
-5
-10
-15
-20
-25
TA = 85°C
TA = 25°C
TA = 85°C
TA = 25°C
0
0.5
1
1.5
2
2.5
3
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
VCC = 3 V
Full drive strength
VCC = 1.8 V
Full drive strength
Figure 5-9. Typical High-Level Output Current vs
High-Level Output Voltage
Figure 5-10. Typical High-Level Output Current vs
High-Level Output Voltage
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5.10 Power-Management Module (PMM)
Table 5-12 lists the characteristics of the BOR.
Table 5-12. PMM, Brownout Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
| dDVCC/dt | < 3 V/s
| dDVCC/dt | < 3 V/s
MIN
TYP
MAX UNIT
V(DVCC_BOR_IT–)
V(DVCC_BOR_IT+)
V(DVCC_BOR_hys)
tRESET
BORH on voltage, DVCC falling level
BORH off voltage, DVCC rising level
BORH hysteresis
1.45
1.50
250
V
V
0.80
50
2
1.20
mV
µs
Pulse duration required at RST/NMI pin to accept a reset
Table 5-13 lists the core voltage characteristics of the PMM.
Table 5-13. PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
2.4 V ≤ DVCC ≤ 3.6 V
2.2 V ≤ DVCC ≤ 3.6 V
2 V ≤ DVCC ≤ 3.6 V
1.8 V ≤ DVCC ≤ 3.6 V
2.4 V ≤ DVCC ≤ 3.6 V
2.2 V ≤ DVCC ≤ 3.6 V
2 V ≤ DVCC ≤ 3.6 V
1.8 V ≤ DVCC ≤ 3.6 V
MIN
TYP
1.91
1.81
1.61
1.41
1.94
1.92
1.73
1.52
MAX UNIT
VCORE3(AM)
VCORE2(AM)
VCORE1(AM)
VCORE0(AM)
VCORE3(LPM)
VCORE2(LPM)
VCORE1(LPM)
VCORE0(LPM)
Core voltage, active mode, PMMCOREV = 3
Core voltage, active mode, PMMCOREV = 2
Core voltage, active mode, PMMCOREV = 1
Core voltage, active mode, PMMCOREV = 0
Core voltage, low-current mode, PMMCOREV = 3
Core voltage, low-current mode, PMMCOREV = 2
Core voltage, low-current mode, PMMCOREV = 1
Core voltage, low-current mode, PMMCOREV = 0
V
V
V
V
V
V
V
V
Table 5-14 lists the characteristics of the high-side SVS.
Table 5-14. PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SVSHE = 0, DVCC = 3.6 V
MIN
TYP
0
MAX UNIT
nA
I(SVSH)
SVS current consumption
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
SVSHE = 1, SVSHRVL = 0
200
1.5
µA
1.60
1.77
1.93
2.09
1.65
1.85
2.05
2.15
2.30
2.57
2.90
2.90
1.65
1.84
2.00
2.16
1.75
1.95
2.15
2.25
2.40
2.70
3.05
3.05
2.5
1.75
SVSHE = 1, SVSHRVL = 1
1.95
V
V(SVSH_IT–)
SVSH on voltage level
SVSHE = 1, SVSHRVL = 2
2.12
SVSHE = 1, SVSHRVL = 3
2.29
1.85
2.05
2.25
SVSHE = 1, SVSMHRRL = 0
SVSHE = 1, SVSMHRRL = 1
SVSHE = 1, SVSMHRRL = 2
SVSHE = 1, SVSMHRRL = 3
2.35
V
V(SVSH_IT+)
SVSH off voltage level
SVSHE = 1, SVSMHRRL = 4
2.55
SVSHE = 1, SVSMHRRL = 5
2.83
3.20
3.20
SVSHE = 1, SVSMHRRL = 6
SVSHE = 1, SVSMHRRL = 7
SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1
SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0
SVSHE = 0 → 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1
SVSHE = 0 → 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0
tpd(SVSH)
SVSH propagation delay
µs
µs
20
12.5
100
t(SVSH)
SVSH on or off delay time
DVCC rise time
dVDVCC/dt
0
1000
V/s
40
Specifications
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Table 5-15 lists the characteristics of the high-side SVM.
Table 5-15. PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SVMHE = 0, DVCC = 3.6 V
MIN
TYP
0
MAX UNIT
nA
I(SVMH)
SVMH current consumption
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
SVMHE = 1, SVSMHRRL = 0
200
1.5
µA
1.83
1.63
1.83
2.03
2.13
2.28
2.55
2.88
2.88
1.73
1.93
2.13
2.23
2.40
2.70
3.02
3.02
3.77
2.5
SVMHE = 1, SVSMHRRL = 1
2.03
SVMHE = 1, SVSMHRRL = 2
2.23
SVMHE = 1, SVSMHRRL = 3
2.33
V(SVMH)
SVMH on or off voltage level(1)
SVMHE = 1, SVSMHRRL = 4
2.53
2.81
3.18
3.18
V
SVMHE = 1, SVSMHRRL = 5
SVMHE = 1, SVSMHRRL = 6
SVMHE = 1, SVSMHRRL = 7
SVMHE = 1, SVMHOVPE = 1
SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1
SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0
tpd(SVMH) SVMH propagation delay
µs
µs
20
SVMHE = 0 → 1, dVDVCC/dt = 10 mV/µs,
SVMHFP = 1
12.5
100
t(SVMH)
SVMH on or off delay time
SVMHE = 0 → 1, dVDVCC/dt = 1 mV/µs,
SVMHFP = 0
(1) The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide on recommended settings and use.
Table 5-16 lists the characteristics of the low-side SVS.
Table 5-16. PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SVSLE = 0, PMMCOREV = 2
MIN
TYP
0
MAX UNIT
nA
µA
µs
I(SVSL)
SVSL current consumption
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
200
1.5
2.5
20
tpd(SVSL)
SVSL propagation delay
SVSL on or off delay time
SVSLE = 0 → 1, dVCORE/dt = 10 mV/µs,
SVSLFP = 1
12.5
100
t(SVSL)
µs
SVSLE = 0 → 1, dVCORE/dt = 1 mV/µs,
SVSLFP = 0
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MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 5-17 lists the characteristics of the low-side SVM.
Table 5-17. PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SVMLE = 0, PMMCOREV = 2
MIN
TYP
0
MAX UNIT
nA
µA
µs
I(SVML)
SVML current consumption
SVMLE = 1, PMMCOREV = 2, SVMLFP = 0
200
1.5
2.5
20
SVMLE = 1, PMMCOREV = 2, SVMLFP = 1
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
SVMLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
SVMLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
tpd(SVML)
SVML propagation delay
SVML on or off delay time
12.5
100
t(SVML)
µs
5.11 Auxiliary Supplies
Table 5-18 lists the recommended operating conditions of the auxiliary supplies.
Table 5-18. Auxiliary Supplies, Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX UNIT
Supply voltage range for all supplies at pins DVCC, AVCC, AUXVCC1, AUXVCC2,
AUXVCC3
VCC
1.8
3.6
V
V
V
PMMCOREVx = 0
1.8
2.0
2.2
2.4
3.6
3.6
3.6
3.6
PMMCOREVx = 1
PMMCOREVx = 2
PMMCOREVx = 3
Digital system supply voltage range,
VDSYS = VCC – RON × ILOAD
VDSYS
See module
specifications
VASYS
Analog system supply voltage range, VASYS = VCC – RON × ILOAD
TA
Ambient temperature range
–40
85
°C
°C
TA,HTOL
Ambient temperature during HTOL (module should be functional during HTOL)
150
CVCC,CAUX
1/2
Recommended capacitor at pins DVCC, AVCC, AUXVCC1, AUXVCC2
4.7
µF
CVSYS
Recommended capacitor at pins VDSYS1, VDSYS2 and VASYS1, VASYS2
Recommended capacitance at pin VCORE
4.7
0.47
0.47
µF
µF
µF
CVCORE
CAUX3
Recommended capacitor at pin AUXVCC3
Table 5-19 lists the current consumption of the backup subsystem.
Table 5-19. Auxiliary Supplies, AUXVCC3 (Backup Subsystem) Currents
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA
MIN
MAX UNIT
25°C
85°C
25°C
85°C
0.86
µA
AUXVCC3 current with RTC
enabled
RTC and 32-kHz oscillator in
backup subsystem enabled
IAUX3,RTCon
3 V
1.2
120
nA
AUXVCC3 current with RTC
disabled
RTC and 32-kHz oscillator in
backup subsystem disabled
IAUX3,RTCoff
3 V
220
42
Specifications
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 5-20 lists the characteristics of the auxiliary supply monitor.
Table 5-20. Auxiliary Supplies, Auxiliary Supply Monitor
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Average supply
LOCKAUX = 0, AUXMRx = 0
current for monitoring AUX0MD = 0, AUX1MD = 0, AUX2MD = 1,
ICC,Monitor
1.10
0.13
µA
µA
circuitry drawn from
VDSYS
VDSYS = DVCC, VASYS = AVCC,
Current measured at VDSYS
Average current
LOCKAUX = 0, AUXMRx = 0
drawn from monitored AUX0MD = 0, AUX1MD = 0, AUX2MD = 1,
IMeas,Montior
supply during
measurement cycle
VDSYS = DVCC, VASYS = AVCC,
Current measured at AUXVCC1
VSVMH
VSVMH
VSVMH
(SVSMHRRLx
= AUXLVLx)
(SVSMHRRL (SVSMHRRL
x =
AUXLVLx)
x =
AUXLVLx)
General
X – 5%
1.65
1.85
2.05
2.15
2.30
2.57
2.90
2.90
X + 5%
1.85
2.05
2.25
2.35
2.55
2.83
3.20
3.20
AUXLVLx = 0
AUXLVLx = 1
AUXLVLx = 2
AUXLVLx = 3
AUXLVLx = 4
AUXLVLx = 5
AUXLVLx = 6
AUXLVLx = 7
1.75
1.95
2.15
2.25
2.40
2.70
3.00
3.00
Auxiliary supply
threshold level (same
as high-side SVM)
VMonitor
V
Table 5-21 lists the ON-resistance characteristics of the switches.
Table 5-21. Auxiliary Supplies, Switch ON-Resistance
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
ON-resistance of switch between DVCC and
VDSYS
RON,DVCC
RON,DAUX1
RON,DAUX2
RON,AVCC
RON,AAUX1
RON,AAUX2
ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA
5
5
Ω
Ω
Ω
Ω
Ω
Ω
ON-resistance of switch between AUXVCC1
and VDSYS
ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA
ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA
ILOAD = IModules = 10 mA
ON-resistance of switch between AUXVCC2
and VDSYS
5
ON-resistance of switch between AVCC and
VASYS
5
ON-resistance of switch between AUXVCC1
and VASYS
ILOAD = IModules = 5 mA
20
20
ON-resistance of switch between AUXVCC2
and VASYS
ILOAD = IModules = 5 mA
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MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 5-22 lists the switching times of the auxiliary supplies.
Table 5-22. Auxiliary Supplies, Switching Time
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
MAX UNIT
tSwitch
Time from occurrence of trigger (SVM or software) to "new" supply connected to system supplies
"Recovery time" after a switch over takes place. During this time, another switch cannot occur.
100
480
ns
µs
tRecover
170
Table 5-23 lists the leakage characteristics of the switch.
Table 5-23. Auxiliary Supplies, Switch Leakage
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Current into DVCC, AVCC, AUXVCC1, or
AUXVCC2 if not selected
ISW,Lkg
IVmax
Per supply (but not the highest supply)
75
250
700
nA
nA
Current drawn from highest supply
500
Table 5-24 lists the characteristics of the auxiliary supplies to the ADC.
Table 5-24. Auxiliary Supplies, Auxiliary Supplies to ADC10_A
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.8 V
3 V
MIN
0.57
0.95
1.14
TYP MAX
UNIT
0.6
1.0
1.2
0.63
1.05
1.26
15
Supply voltage divider
V3 = VSupply / 3
V3
V
3.6 V
AUXADCRx = 0
AUXADCRx = 1
AUXADCRx = 2
RV3
Load resistance
1.5
kΩ
0.6
AUXADCRx = 0
AUXADCRx = 1
AUXADCRx = 2
1000
1000
1000
Error of conversion
result ≤ 1 LSB
tSample,V3 Sampling time required if V3 is selected
ns
Table 5-25 lists the characteristics of the charge limiting resistor.
Table 5-25. Auxiliary Supplies, Charge Limiting Resistor
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
AUXCHCx = 1
VCC
MIN
TYP
MAX UNIT
5
RCHARGE Charge limiting resistor
AUXCHCx = 2
AUXCHCx = 3
3 V
10
20
kΩ
44
Specifications
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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5.12 Timer_A
Table 5-26 lists the characteristics of the Timer_A.
Table 5-26. Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK or ACLK,
External: TACLK,
fTA
Timer_A input clock frequency
1.8 V, 3 V
25 MHz
Duty cycle = 50% ±10%
All capture inputs, Minimum pulse
duration required for capture
tTA,cap
Timer_A capture timing
1.8 V, 3 V
20
ns
5.13 eUSCI
Table 5-27 lists the supported clock frequencies of the eUSCI in UART mode.
Table 5-27. eUSCI (UART Mode) Clock Frequency
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
Internal: SMCLK or ACLK,
feUSCI
eUSCI input clock frequency
External: UCLK,
Duty cycle = 50% ±10%
fSYSTEM
MHz
MHz
BITCLK clock frequency
(equals baud rate in MBaud)
fBITCLK
5
Table 5-28 lists the switching characteristics of the eUSCI in UART mode.
Table 5-28. eUSCI (UART Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UCGLITx = 0
VCC
MIN
10
TYP
15
MAX UNIT
25
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
30
50
85
ns
tt
UART receive deglitch time(1)
2 V, 3 V
50
80
150
70
120
200
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To make sure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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Table 5-29 lists the supported clock frequencies of the eUSCI in SPI master mode.
Table 5-29. eUSCI (SPI Master Mode) Clock Frequency
PARAMETER
TEST CONDITIONS
Internal: SMCLK or ACLK,
Duty cycle = 50% ±10%
MIN
MAX UNIT
feUSCI
eUSCI input clock frequency
fSYSTEM
MHz
Table 5-30 lists the switching characteristics of the eUSCI in SPI master mode.
Table 5-30. eUSCI (SPI Master Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
150
150
200
200
MAX UNIT
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
tSTE,LEAD
STE lead time, STE low to clock
2 V, 3 V
ns
tSTE,LAG
STE lag time, Last clock to STE high
2 V, 3 V
ns
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
50
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
30
ns
50
STE access time, STE low to SIMO data
out
tSTE,ACC
30
40
25
ns
40
STE disable time, STE high to SIMO
high impedance
tSTE,DIS
25
50
30
0
tSU,MI
SOMI input data setup time
SOMI input data hold time
SIMO output data valid time(2)
SIMO output data hold time(3)
ns
tHD,MI
ns
0
9
tVALID,MO
UCLK edge to SIMO valid, CL = 20 pF
CL = 20 pF
ns
5
0
0
tHD,MO
ns
(1) fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)
)
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-11 and Figure 5-12.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-
11 and Figure 5-12.
46
Specifications
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MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
SIMO
tVALID,MO
Figure 5-11. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
SIMO
tVALID,MO
Figure 5-12. SPI Master Mode, CKPH = 1
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MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
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Table 5-31 lists the characteristics of the eUSCI in SPI slave mode.
Table 5-31. eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
MIN
4
TYP
MAX UNIT
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
tSU,SI
STE lead time, STE low to clock
ns
3
0
STE lag time, Last clock to STE high
ns
0
46
ns
24
STE access time, STE low to SOMI data out
38
ns
25
STE disable time, STE high to SOMI high
impedance
2
1
2
2
SIMO input data setup time
SIMO input data hold time
SOMI output data valid time(2)
SOMI output data hold time(3)
ns
ns
tHD,SI
55
ns
32
UCLK edge to SOMI valid,
CL = 20 pF
tVALID,SO
24
16
tHD,SO
CL = 20 pF
ns
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)
)
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-13 and Figure 5-14.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13
and Figure 5-14.
48
Specifications
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MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
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UCMODEx = 01
UCMODEx = 10
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tSU,SIMO
tHD,SIMO
tLOW/HIGH
tLOW/HIGH
SIMO
tACC
tVALID,SOMI
tDIS
SOMI
Figure 5-13. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
SOMI
tACC
tDIS
tVALID,SO
Figure 5-14. SPI Slave Mode, CKPH = 1
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MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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Table 5-32 lists the characteristics of the eUSCI in I2C mode.
Table 5-32. eUSCI (I2C Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-15)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK or ACLK,
External: UCLK,
feUSCI
eUSCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ±10%
fSCL
SCL clock frequency
2 V, 3 V
2 V, 3 V
0
5.1
1.5
5.1
1.4
0.4
5.0
1.3
5.2
1.7
75
400 kHz
µs
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
tHD,STA
Hold time (repeated) START
tSU,STA
tHD,DAT
tSU,DAT
Setup time for a repeated START
Data hold time
2 V, 3 V
2 V, 3 V
2 V, 3 V
µs
µs
µs
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
UCGLITx = 0
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
UCCLTOx = 1
UCCLTOx = 2
UCCLTOx = 3
Data setup time
tSU,STO
Setup time for STOP
2 V, 3 V
2 V, 3 V
µs
220
35
120
ns
Pulse duration of spikes suppressed by
input filter
tSP
30
60
20
35
30
33
37
tTIMEOUT
Clock low time-out
2 V, 3 V
ms
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-15. I2C Mode Timing
50
Specifications
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
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MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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5.14 RTC Tamper Detect Pin
Table 5-33 lists the input characteristics of the tamper detect pin.
Table 5-33. Schmitt-Trigger Inputs, RTC Tamper Detect Pin
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
AUXVCC3
1.8 V
3 V
MIN
0.80
1.50
0.45
0.75
0.3
TYP
MAX UNIT
1.40
V
VIT+ Positive-going input threshold voltage
2.10
1.8 V
3 V
1.00
V
VIT– Negative-going input threshold voltage
1.65
1.8 V
3 V
0.85
V
Vhys Input voltage hysteresis (VIT+ – VIT–
RPull Pullup or pulldown resistor
)
0.4
1.0
For pullup: VIN = VSS
For pulldown: VIN = AUXVCC3
20
35
5
50
kΩ
CI
Input capacitance
VIN = VSS or AUXVCC3
pF
Table 5-34 lists the input requirements of the tamper detect pin.
Table 5-34. Inputs, RTC Tamper Detect Pin(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
AUXVCC3
MIN
MAX UNIT
Port P1, P2: P1.x to P2.x, External trigger pulse duration
to set interrupt flag
t(int)
External interrupt timing(2)
2.2 V, 3 V
20
ns
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int)
.
Table 5-35 lists the leakage current of the tamper detect pin.
Table 5-35. Leakage Current, RTC Tamper Detect Pin
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1) (2)
AUXVCC3
MIN
MAX UNIT
+50 nA
Ilkg(Px.y)
High-impedance leakage current
See
1.8 V, 3 V
–50
(1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
Table 5-36 lists the output characteristics of the tamper detect pin.
Table 5-36. Outputs, RTC Tamper Detect Pin
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –100 µA(1)
AUXVCC3
MIN
1.50
1.20
2.70
2.40
0.00
0.00
0.00
0.00
MAX UNIT
1.80
1.8 V
I(OHmax) = –200 µA(1)
I(OHmax) = –100 µA(1)
I(OHmax) = –200 µA(1)
I(OLmax) = 100 µA(2)
I(OLmax) = 200 µA(2)
I(OLmax) = 100 µA(2)
I(OLmax) = 200 µA(2)
1.80
V
VOH
High-level output voltage
3.00
3 V
1.8 V
3 V
3.00
0.25
0.60
V
VOL
Low-level output voltage
0.25
0.60
(1) The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified.
See Section 5.3 for more details.
(2) The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified.
See Section 5.3 for more details.
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5.15 LCD_C
Table 5-37 lists the operating conditions of the LCD controller.
Table 5-37. LCD_C, Operating Conditions
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
Supply voltage range, charge
pump enabled, VLCD ≤ 3.6 V
LCDCPEN = 1, 0000 < VLCDx ≤ 1111
(charge pump enabled, VLCD ≤ 3.6 V)
VCC,LCD_C,CP en,3.6
VCC,LCD_C,CP en,3.3
VCC,LCD_C,int. bias
VCC,LCD_C,ext. bias
2.2
3.6
3.6
3.6
3.6
V
V
V
V
Supply voltage range, charge
pump enabled, VLCD ≤ 3.3 V
LCDCPEN = 1, 0000 < VLCDx ≤ 1100
(charge pump enabled, VLCD ≤ 3.3 V)
2.0
2.4
2.4
Supply voltage range, internal
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 0
LCDCPEN = 0, VLCDEXT = 0
Supply voltage range, external
biasing, charge pump disabled
Supply voltage range, external
LCD voltage, internal or
external biasing, charge pump
disabled
VCC,LCD_C,VLCDEXT
LCDCPEN = 0, VLCDEXT = 1
LCDCPEN = 0, VLCDEXT = 1
2.0
2.4
3.6
3.6
V
V
External LCD voltage at
LCDCAP/R33, internal or
external biasing, charge pump
disabled
VLCDCAP/R33
Capacitor on LCDCAP when
charge pump enabled
LCDCPEN = 1, VLCDx > 0000
(charge pump enabled)
CLCDCAP
fLCD
fFRAME,4mux
fFRAME,8mux
4.7
0
4.7
10
1024
128
64
µF
Hz
Hz
Hz
fFRAME = 1/(2 × mux) × fLCD
with mux = 1 (static) to 8
LCD frequency range
fFRAME,4mux(MAX) = 1/(2 × 4) ×
fLCD(MAX) = 1/(2 × 4) × 1024 Hz
LCD frame frequency range
LCD frame frequency range
fFRAME,8mux(MAX) = 1/(2 × 4) ×
fLCD(MAX) = 1/(2 × 8) × 1024 Hz
fACLK,in
CPanel
VR33
ACLK input frequency range
Panel capacitance
30
32
40
10000
kHz
pF
V
100-Hz frame frequency
Analog input voltage at R33
LCDCPEN = 0, VLCDEXT = 1
2.4
VCC + 0.2
VR03 + 2/3
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR23,1/3bias
VR13,1/3bias
VR13,1/2bias
Analog input voltage at R23
VR13
× (VR33
–
VR33
VR23
VR33
V
V
V
VR03
)
VR03 + 1/3
× (VR33
VR03
Analog input voltage at R13
with 1/3 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR03
–
)
VR03 + 1/2
× (VR33
VR03
Analog input voltage at R13
with 1/2 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 1
VR03
–
)
VR03
Analog input voltage at R03
R03EXT = 1
VSS
2.4
V
V
Voltage difference between
VLCD and R03
VLCD – VR03
LCDCPEN = 0, R03EXT = 1
VCC + 0.2
1.5
External LCD reference voltage
applied at LCDREF/R13
VLCDREF/R13
VLCDREFx = 01
0.8
1.2
V
52
Specifications
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Table 5-38 lists the characteristics of the LCD controller.
Table 5-38. LCD_C, Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VLCDx = 0000, VLCDEXT = 0
LCDCPEN = 1, VLCDx = 0001
LCDCPEN = 1, VLCDx = 0010
LCDCPEN = 1, VLCDx = 0011
LCDCPEN = 1, VLCDx = 0100
LCDCPEN = 1, VLCDx = 0101
LCDCPEN = 1, VLCDx = 0110
LCDCPEN = 1, VLCDx = 0111
LCDCPEN = 1, VLCDx = 1000
LCDCPEN = 1, VLCDx = 1001
LCDCPEN = 1, VLCDx = 1010
LCDCPEN = 1, VLCDx = 1011
LCDCPEN = 1, VLCDx = 1100
LCDCPEN = 1, VLCDx = 1101
LCDCPEN = 1, VLCDx = 1110
LCDCPEN = 1, VLCDx = 1111
VCC
MIN
TYP
VCC
MAX UNIT
2.4 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2.2 V to 3.6 V
2.2 V to 3.6 V
2.2 V to 3.6 V
2.60
2.66
2.72
2.78
2.84
2.90
2.96
3.02
3.08
3.14
3.20
3.26
3.32
3.38
3.50
VLCD
LCD voltage
V
3.72
µA
Peak supply currents due to
charge pump activities
ICC,Peak,CP
tLCD,CP,on
ICP,Load
LCDCPEN = 1, VLCDx = 1111
2.2 V
2.2 V
2.2 V
2.2 V
2.2 V
200
100
Time to charge CLCD when
discharged
CLCD = 4.7 µF, LCDCPEN = 0→1,
VLCDx = 1111
500
ms
µA
kΩ
kΩ
Maximum charge pump load
current
LCDCPEN = 1, VLCDx = 1111
50
LCD driver output
impedance, segment lines
LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA
RLCD,Seg
RLCD,COM
10
10
LCD driver output
impedance, common lines
LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA
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Specifications
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5.16 SD24_B
Table 5-39 lists the operating conditions of the SD24_B.
Table 5-39. SD24_B, Power Supply and Operating Conditions
MIN
2.4
TYP
MAX UNIT
AVCC
TA
Analog supply voltage
AVCC = DVCC, AVSS = DVSS = 0 V
3.6
85
V
°C
MHz
V
Ambient temperature
–40
fSD
Modulator clock frequency
Absolute input voltage
0.03
2.3
VI
AVSS – 1
AVSS – 1
–VREF/GAIN
±900
AVCC
VIC
Common-mode input voltage
Differential full-scale input voltage
AVCC
V
VID,FS
Bipolar mode, VID = VI,A+ – VI,A–
SD24GAINx = 1
+VREF/GAIN
mV
±930
±460
±230
±120
±60
SD24GAINx = 2
±450
SD24GAINx = 4
±225
SD24GAINx = 8
REFON = 1
±112
Differential input voltage for specified
performance(1)
VID
mV
nF
SD24GAINx = 16
±56
SD24GAINx = 32
SD24GAINx = 64
±28
±30
±14
±14
SD24GAINx = 128
±7
±7.25
100
CREF
VREF load capacitance(2)
SD24REFS = 1
(1) The full-scale range (FSR) is defined by VFS+ = +VREF/GAIN and VFS– = –VREF/GAIN: FSR = VFS+ – VFS– = 2 × VREF/GAIN. If VREF is
sourced externally, the analog input range should not exceed 80% of VFS+ or VFS–, that is, VID = 0.8 VFS– to 0.8 VFS+. If VREF is sourced
internally, the given VID ranges apply. MIN values are calculated based on a VREF of 1.125 V. TYP values are calculated based on a
VREF of 1.16 V.
(2) There is no capacitance required on VREF. However, TI recommends using a capacitance of 100 nF to reduce any reference voltage
noise.
Table 5-40 lists the analog input characteristics of the SD24_B.
(1)
Table 5-40. SD24_B, Analog Inputs
Also see Figure 5-16
PARAMETER
TEST CONDITIONS
SD24GAINx = 1
VCC
MIN
TYP
5.0
MAX UNIT
SD24GAINx = 2
5.0
SD24GAINx = 4
5.0
CI
Input capacitance
pF
SD24GAINx = 8
5.0
SD24GAINx = 16
SD24GAINx = 32, 64, 128
5.0
5.0
SD24GAINx = 1
SD24GAINx = 8
SD24GAINx = 32
SD24GAINx = 1
SD24GAINx = 8
SD24GAINx = 32
200
200
200
400
400
400
Input impedance
(pin A+ or A- to AVSS
ZI
fSD24 = 1 MHz
fSD24 = 1 MHz
3 V
3 V
kΩ
kΩ
)
300
300
Differential input impedance
(pin A+ to pin A-)
ZID
(1) All parameters pertain to each SD24_B converter.
54
Specifications
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1600
1400
1200
1000
800
600
400
200
0
-200
-1
-0.5
0
0.5
1
1.5
2
2.5
3
Input Voltage – V
Figure 5-16. Input Leakage Current vs Input Voltage (Modulator OFF)
Table 5-41 lists the supply currents of the SD24_B.
Table 5-41. SD24_B, Supply Currents
PARAMETER
TEST CONDITIONS
SD24GAIN: 1
VCC
MIN
TYP
490
490
490
559
559
627
627
627
600
677
740
MAX UNIT
600
600
600
SD24GAIN: 2
SD24GAIN: 4
Analog plus digital supply
current per converter (reference
not included)
SD24GAIN: 8
SD24GAIN: 16
SD24GAIN: 32
SD24GAIN: 64
SD24GAIN: 128
SD24GAIN: 1
SD24GAIN: 8
SD24GAIN: 32
700
µA
fSD24 = 1 MHz,
SD24OSR = 256
ISD,256
3 V
700
800
800
800
700
Analog plus digital supply
current per converter (reference
not included)
fSD24 = 2 MHz,
SD24OSR = 512
ISD,512
3 V
800
900
µA
Current of internal SD24
No converter is active,
ISD24REFonly
reference and buffers (includes (SD24REFS = 1,
3 V
3 V
147
75
190
110
µA
µA
shared reference)
SD24BCCTLx.SD24SC = 0)
Current of internal SD24
Converter 0 is active,
ISD24REF,Conv0
reference and buffers (includes (SD24REFS = 1,
shared reference)
SD24BCCTL0.SD24SC = 1)
Any converter other than converter 0
is active,
Current of internal SD24
ISD24REF,notConv0
reference and buffers (includes (SD24REFS = 1,
shared reference) SD24BCCTL0.SD24SC = 0,
3 V
137
175
µA
SD24BCCTLx.SD24SC = 1)
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Table 5-42 lists the performance characteristics of the SD24_B.
Table 5-42. SD24_B, Performance
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFON = 1
PARAMETER
TEST CONDITIONS
VCC
MIN
–0.01
–0.01
–0.01
TYP
MAX
+0.01
UNIT
SD24GAIN: 1
SD24GAIN: 8
SD24GAIN: 32
SD24GAIN: 1
SD24GAIN: 2
SD24GAIN: 4
SD24GAIN: 8
SD24GAIN: 16
SD24GAIN: 32
SD24GAIN: 64
Integral nonlinearity, end-
point fit
INL
3 V
+0.01 % of FSR
+0.01
1
2
4
8
Gnom
Nominal gain
3 V
16
32
64
128
SD24GAIN: 128
SD24GAIN: 1, with external reference (1.2 V)
SD24GAIN: 8, with external reference (1.2 V)
SD24GAIN: 32, with external reference (1.2 V)
–1%
–2%
–2%
+1%
+2%
+2%
EG
Gain error(1)
3 V
3 V
3 V
Gain error temperature
coefficient(2), internal
reference
ΔEG/ΔT
ΔEG/ΔT
SD24GAIN: 1, 8, or 32 (with internal reference)
80 ppm/°C
SD24GAIN: 1 (with external reference)
SD24GAIN: 8 (with external reference)
SD24GAIN: 32 (with external reference)
SD24GAIN: 1
15
Gain error temperature
coefficient(2), external
reference
15 ppm/°C
15
0.1
0.1
0.4
(3)
ΔEG/ΔVCC
Gain error vs VCC
SD24GAIN: 8
3 V
3 V
3 V
3 V
%/V
SD24GAIN: 32
SD24GAIN: 1 (with Vdiff = 0 V)
SD24GAIN: 8
2.3
EOS[V]
Offset error(4)
Offset error(4)
1
0.5
mV
SD24GAIN: 32
SD24GAIN: 1 (with Vdiff = 0 V)
SD24GAIN: 8
–0.2
–0.7
–1.4
+0.2
+0.7
+1.4
EOS[FS]
ΔEOS/ΔT
% FS
µV/°C
SD24GAIN: 32
SD24GAIN: 1
2
0.25
0.1
Offset error temperature
coefficient(5)
SD24GAIN: 8
SD24GAIN: 32
(1) The gain error EG specifies the deviation of the actual gain Gact from the nominal gain Gnom: EG = (Gact – Gnom)/Gnom. It covers process,
temperature, and supply voltage variations.
(2) The gain error temperature coefficient ΔEG/ ΔT specifies the variation of the gain error EG over temperature (EG(T) = (Gact(T) –
Gnom)/Gnom) using the box method (that is, minimum and maximum values):
ΔEG/ ΔT = (MAX(EG(T)) – MIN(EG(T) ) / (MAX(T) – MIN(T)) = (MAX(Gact(T)) – MIN(Gact(T)) / Gnom / (MAX(T) – MIN(T))
with T ranging from –40°C to 85°C.
(3) The gain error vs VCC coefficient ΔEG/ ΔVCC specifies the variation of the gain error EG over supply voltage (EG(VCC) = (Gact(VCC) –
Gnom)/Gnom) using the box method (that is, minimum and maximum values):
ΔEG/ ΔVCC = (MAX(EG(VCC)) – MIN(EG(VCC) ) / (MAX(VCC) – MIN(VCC)) = (MAX(Gact(VCC)) – MIN(Gact(VCC)) / Gnom / (MAX(VCC) –
MIN(VCC))
with VCC ranging from 2.4 V to 3.6 V.
(4) The offset error EOS is measured with shorted inputs in 2s-complement mode with +100% FS = VREF/G and –100% FS = –VREF/G.
Conversion between EOS [FS] and EOS [V] is as follows: EOS [FS] = EOS [V] × G/VREF, EOS [V] = EOS [FS] × VREF/G.
(5) The offset error temperature coefficient ΔEOS/ ΔT specifies the variation of the offset error EOS over temperature using the box method
(that is, minimum and maximum values):
ΔEOS/ ΔT = (MAX(EOS(T)) – MIN(EOS(T) ) / (MAX(T) – MIN(T))
with T ranging from –40°C to 85°C.
56
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Table 5-42. SD24_B, Performance (continued)
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFON = 1
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
500
MAX
UNIT
SD24GAIN: 1
(6)
ΔEOS/ΔVCC
CMRR,DC
CMRR,50Hz
Offset error vs VCC
SD24GAIN: 8
SD24GAIN: 32
SD24GAIN: 1
SD24GAIN: 8
SD24GAIN: 32
3 V
125
µV/V
50
–120
–110
–100
–120
–110
–100
Common-mode rejection
at DC(7)
3 V
3 V
dB
dB
SD24GAIN: 1, fCM = 50 Hz, VCM = 930 mV
SD24GAIN: 8, fCM = 50 Hz, VCM = 120 mV
SD24GAIN: 32, fCM = 50 Hz, VCM = 30 mV
Common-mode rejection
at 50 Hz(8)
SD24GAIN: 1, VCC = 3 V + 50 mV × sin(2π × fVCC
× t), fVCC = 50 Hz
–61
–75
–79
–61
–75
–79
AC power supply
SD24GAIN: 8, VCC = 3 V + 50 mV × sin(2π × fVCC
× t), fVCC = 50 Hz
AC PSRR, ext rejection ratio, external
dB
dB
reference(9)
SD24GAIN: 32, VCC = 3 V + 50 mV × sin(2π ×
fVCC × t), fVCC = 50 Hz
SD24GAIN: 1, VCC = 3 V + 50 mV × sin(2π × fVCC
× t), fVCC = 50 Hz
AC power supply
SD24GAIN: 8, VCC = 3 V + 50 mV × sin(2π × fVCC
× t), fVCC = 50 Hz
AC PSRR, int
rejection ratio, internal
reference(9)
SD24GAIN: 32, VCC = 3 V + 50 mV × sin(2π ×
fVCC × t), fVCC = 50 Hz
Crosstalk source: SD24GAIN: 1, Sine-wave with
maximum possible Vpp, fIN = 50 Hz or 100 Hz,
Converter under test: SD24GAIN: 1
–120
–115
–110
Crosstalk source: SD24GAIN: 1, Sine-wave with
maximum possible Vpp, fIN = 50 Hz or 100 Hz,
Converter under test: SD24GAIN: 8
Crosstalk between
converters(10)
XT
3 V
dB
Crosstalk source: SD24GAIN: 1, Sine-wave with
maximum possible Vpp, fIN = 50 Hz or 100 Hz,
Converter under test: SD24GAIN: 32
(6) The offset error vs VCC ΔEOS/ ΔVCC specifies the variation of the offset error EOS over supply voltage using the box method (that is,
minimum and maximum values):
ΔEOS/ ΔVCC = (MAX(EOS(VCC)) – MIN(EOS(VCC) ) / (MAX(VCC) – MIN(VCC))
with VCC ranging from 2.4 V to 3.6 V.
(7) The DC CMRR specifies the change in the measured differential input voltage value when the common-mode voltage varies:
DC CMRR = –20log(ΔMAX/FSR) with ΔMAX being the difference between the minium value and the maximum value measured when
sweeping the common-mode voltage.
The DC CMRR is measured with both inputs connected to the common-mode voltage (that is, no differential input signal is applied), and
the common-mode voltage is swept from –1 V to VCC
.
(8) The AC CMRR is the difference between a hypothetical signal with the amplitude and frequency of the applied common-mode ripple
applied to the inputs of the ADC and the actual common-mode signal spur visible in the FFT spectrum:
AC CMRR = Error Spur [dBFS] – 20log(VCM / 1.2 V / G) [dBFS] with a common-mode signal of VCM × sin(2π × fCM × t) applied to the
analog inputs.
The AC CMRR is measured with the both inputs connected to the common-mode signal; that is, no differential input signal is applied.
With the specified typical values the error spur is within the noise floor (as specified by the SINAD values).
(9) The AC PSRR is the difference between a hypothetical signal with the amplitude and frequency of the applied supply voltage ripple
applied to the inputs of the ADC and the actual supply ripple spur visible in the FFT spectrum:
AC PSRR = Error Spur [dBFS] – 20log(50 mV / 1.2 V / G) [dBFS] with a signal of 50 mV × sin(2π × fVCC × t) added to VCC
The AC PSRR is measured with the inputs grounded; that is, no analog input signal is applied.
With the specified typical values the error spur is within the noise floor (as specified by the SINAD values).
SD24GAIN: 1 → Hypothetical signal: 20log(50 mV / 1.2 V / 1) = –27.6 dBFS
.
SD24GAIN: 8 → Hypothetical signal: 20log(50 mV / 1.2 V / 8) = –9.5 dBFS
SD24GAIN: 32 → Hypothetical signal: 20log(50 mV / 1.2 V / 32) = 2.5 dBFS
(10) The crosstalk XT is specified as the tone level of the signal applied to the crosstalk source seen in the spectrum of the converter under
test. It is measured with the inputs of the converter under test being grounded.
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Table 5-43 lists the AC performance characteristics of the SD24_B.
Table 5-43. SD24_B, AC Performance
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFON = 1
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
86
85
84
83
80
73
67
61
95
90
86
MAX UNIT
SD24GAIN: 1
SD24GAIN: 2
SD24GAIN: 4
SD24GAIN: 8
SD24GAIN: 16
SD24GAIN: 32
SD24GAIN: 64
SD24GAIN: 128
SD24GAIN: 1
SD24GAIN: 8
SD24GAIN: 32
82
81
71
Signal-to-noise + distortion
ratio
SINAD
fIN = 50 Hz(1)
3 V
dB
THD
Total harmonic distortion
fIN = 50 Hz(1)
3 V
dB
(1) The following voltages were applied to the SD24_B inputs: VI,A+(t) = 0 V + VPP / 2 × sin(2π × fIN × t) and VI,A–(t) = 0 V – VPP/2 × sin(2π ×
fIN × t)
resulting in a differential voltage of VID = VI,A+(t) – VI,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24_B recommended operating conditions).
Table 5-44 lists the AC performance characteristics of the SD24_B.
Table 5-44. SD24_B, AC Performance
fSD24 = 2 MHz, SD24OSRx = 512, SD24REFON = 1
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
87
85
84
83
81
76
71
65
MAX UNIT
SD24GAIN: 1
SD24GAIN: 2
SD24GAIN: 4
SD24GAIN: 8
SD24GAIN: 16
SD24GAIN: 32
SD24GAIN: 64
SD24GAIN: 128
Signal-to-noise + distortion
ratio
SINAD
fIN = 50 Hz(1)
3 V
dB
(1) The following voltages were applied to the SD24_B inputs: VI,A+(t) = 0 V + VPP / 2 × sin(2π × fIN × t) and VI,A–(t) = 0 V – VPP/2 × sin(2π ×
fIN × t)
resulting in a differential voltage of VID = VI,A+(t) – VI,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24_B recommended operating conditions).
58
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Table 5-45 lists the AC performance characteristics of the SD24_B.
Table 5-45. SD24_B, AC Performance
fSD24 = 32 kHz, SD24OSRx = 512, SD24REFON = 1 (see Figure 5-17 and Figure 5-18)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
89
85
84
82
80
76
67
61
MAX UNIT
SD24GAIN: 1
SD24GAIN: 2
SD24GAIN: 4
SD24GAIN: 8
SD24GAIN: 16
SD24GAIN: 32
SD24GAIN: 64
SD24GAIN: 128
Signal-to-noise + distortion
ratio
SINAD
fIN = 50 Hz(1)
3 V
dB
(1) The following voltages were applied to the SD24_B inputs: VI,A+(t) = 0 V + VPP / 2 × sin(2π × fIN × t) and VI,A–(t) = 0 V – VPP/2 × sin(2π ×
fIN × t)
resulting in a differential voltage of VID = VI,A+(t) – VI,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24_B recommended operating conditions).
110.0
100.0
90.0
80.0
70.0
60.0
50.0
100.0
80.0
60.0
40.0
20.0
0.0
Theoretical limit
(second order)
10
100
1000
0
0.2
0.4
0.6
0.8
1
Vpp – Vref/Gain
OSR
Figure 5-17. SINAD vs OSR
(fSD24 = 1 MHz, SD24REFON = 1, SD24GAIN = 1)
Figure 5-18. SINAD vs VPP
Table 5-46 lists the external reference requirements of the SD24_B.
Table 5-46. SD24_B External Reference Input
ensure correct input voltage range according to VREF
PARAMETER
Input voltage
Input current
TEST CONDITIONS
SD24REFS = 0
VCC
3 V
3 V
MIN
TYP
MAX UNIT
VREF(I)
IREF(I)
1.0
1.20
1.5
50
V
SD24REFS = 0
nA
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5.17 ADC10_A
Table 5-47 lists the input requirements of the ADC.
Table 5-47. 10-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
1.8
0
TYP
MAX UNIT
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
AVCC
V(Ax)
Analog supply voltage
3.6
V
V
Analog input voltage range(1) All ADC10_A pins
AVCC
100
Operating supply current into fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
AVCC terminal, REF module SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
and reference buffer off
2.2 V
3 V
68
78
110
ADC10SREF = 00
Operating supply current into fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 1,
AVCC terminal, REF module SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
3 V
3 V
124
105
72
180
on, reference buffer on
ADC10SREF = 01
IADC10_A
µA
Operating supply current into fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
AVCC terminal, REF module SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
160
110
off, reference buffer on
ADC10SREF = 10, VEREF = 2.5 V
Operating supply current into fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
AVCC terminal, REF module SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
3 V
off, reference buffer off
ADC10SREF = 11, VEREF = 2.5 V
Only one terminal Ax can be selected at one time
from the pad to the ADC10_A capacitor array
including wiring and pad
CI
RI
Input capacitance
2.2 V
3.5
pF
AVCC > 2.0 V, 0 V ≤ VAx ≤ AVCC
36
96
Input MUX ON resistance
kΩ
1.8 V < AVCC < 2.0 V, 0 V ≤ VAx ≤ AVCC
(1) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The external
reference voltage requires decoupling capacitors. Connect two decoupling capacitors, 10 µF and 100 nF, to VREF to decouple the
dynamic current required for an external reference source if it is used for the ADC10_A. Also see the MSP430x5xx and MSP430x6xx
Family User's Guide.
Table 5-48 lists the switching characteristics of the ADC.
Table 5-48. 10-Bit ADC, Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
For specified performance of ADC10_A
linearity parameters
fADC10CLK
fADC10OSC
2.2 V, 3 V
0.45
5
5.5 MHz
Internal ADC10_A
oscillator(1)
ADC10DIV = 0, fADC10CLK = fADC10OSC
2.2 V, 3 V
2.2 V, 3 V
4.4
2.4
4.9
5.6 MHz
REFON = 0, Internal oscillator,
12 ADC10CLK cycles, 10-bit mode,
fADC10OSC = 4 MHz to 5 MHz
3.0
µs
tCONVERT
Conversion time
External fADC10CLK from ACLK, MCLK, or
12 ×
SMCLK, ADC10SSEL ≠ 0
1 / fADC10CLK
Turn-on settling time of
the ADC
(2)
tADC10ON
tSample
See
100
ns
µs
RS = 1000 Ω, RI = 96 kΩ, CI = 3.5 pF(3)
RS = 1000 Ω, RI = 36 kΩ, CI = 3.5 pF(3)
1.8 V
3 V
3
1
Sampling time
(1) The ADC10OSC is sourced directly from MODOSC inside the UCS.
(2) The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
(3) Approximately 8 Tau (τ) are needed to get an error of less than ±0.5 LSB
60
Specifications
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Table 5-49 lists the linearity parameters of the ADC.
Table 5-49. 10-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
–1.0
–1.0
–1.0
MAX UNIT
1.4 V ≤ (VeREF+ – VeREF–) ≤ 1.6 V, CVeREF+ = 20 pF
1.6 V < (VeREF+ – VeREF–) ≤ VAVCC, CVeREF+ = 20 pF
1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF
+1.0
LSB
+1.0
EI
Integral linearity error
2.2 V, 3 V
ED Differential linearity error
EO Offset error
2.2 V, 3 V
2.2 V, 3 V
+1.0
LSB
1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF
Internal impedance of source RS < 100 Ω
–1.0
–1.0
–2.0
+1.0
LSB
1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF,
ADC10SREFx = 11b
EG Gain error
2.2 V, 3 V
2.2 V, 3 V
+1.0
+2.0
LSB
LSB
1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF,
ADC10SREFx = 11b
ET Total unadjusted error
Table 5-50 lists the requirement for the ADC external reference.
Table 5-50. 10-Bit ADC, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Positive external reference
voltage input
(2)
VeREF+
VeREF+ > VeREF–
1.4
AVCC
1.2
V
V
V
Negative external reference
voltage input
(3)
(4)
VeREF–
VeREF+ > VeREF–
VeREF+ > VeREF–
0
(VeREF+
–
Differential external reference
voltage input
1.4
AVCC
VeREF–
)
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHz, ADC10SHTx = 0x0001,
Conversion rate 200 ksps
–26
+26
+1
IVeREF+
IVeREF–
,
Static input current
2.2 V, 3 V
µA
µF
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHZ, ADC10SHTX = 0x1000,
Conversion rate 20 ksps
–1
10
(5)
CVREF+
Capacitance at VREF+ terminal See
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5) Connect two decoupling capacitors, 10 µF and 100 nF, to VREF to decouple the dynamic current required for an external reference
source if it is used for the ADC10_A. Also see the MSP430x5xx and MSP430x6xx Family User's Guide.
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5.18 REF
Table 5-51 lists the characteristics of the REF.
Table 5-51. REF Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
REFVSEL = {2} for 2.5 V, REFON = 1
REFVSEL = {1} for 2 V, REFON = 1
REFVSEL = {0} for 1.5 V, REFON = 1
REFVSEL = {0} for 1.5 V
VCC
MIN
2.47
1.96
1.48
1.8
TYP
2.51
1.99
1.5
MAX UNIT
2.55
3 V
Positive built-in reference
voltage
VREF+
2.02
1.52
V
V
2.2 V, 3 V
AVCC minimum voltage,
Positive built-in reference
active
AVCC(min)
REFVSEL = {1} for 2 V
2.2
REFVSEL = {2} for 2.5 V
2.7
fADC10CLK = 5.0 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {2} for 2.5 V
18
24
21
21
fADC10CLK = 5.0 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {1} for 2 V
Operating supply current into
AVCC terminal(1)
IREF+
3 V
16.1
µA
fADC10CLK = 5.0 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {0} for 1.5 V
14.4
< 18
Temperature coefficient of
built-in reference(2)
IVREF+ = 0 A,
REFVSEL = {0, 1, 2}, REFON = 1
TCREF+
ISENSOR
50 ppm/ °C
2.2 V
3 V
17
17
22
µA
22
Operating supply current into REFON = 0, INCH = 0Ah,
AVCC terminal(3)
ADC10ON = N/A, TA = 30°C
2.2 V
3 V
770
770
1.1
1.5
(4)
VSENSOR
See
ADC10ON = 1, INCH = 0Ah, TA = 30°C
ADC10ON = 1, INCH = 0Bh,
mV
2.2 V
3 V
1.06
1.46
1.14
1.54
VMID
tSENSOR(sample)
tVMID(sample)
AVCC divider at channel 11
V
VMID ≈ 0.5 × VAVCC
Sample time required if
channel 10 is selected(5)
ADC10ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
30
1
µs
µs
Sample time required if
channel 11 is selected(6)
ADC10ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
AVCC = AVCC (min) to AVCC(max)
TA = 25°C,
,
Power supply rejection ratio
(DC)
PSRR_DC
PSRR_AC
120
µV/V
REFVSEL = {0, 1, 2}, REFON = 1
AVCC = AVCC (min) to AVCC(max)
,
Power supply rejection ratio
(AC)
TA = 25°C, f = 1 kHz, ΔVpp = 100 mV,
REFVSEL = {0, 1, 2}, REFON = 1
6.4
75
mV/V
Settling time of reference
voltage(7)
AVCC = AVCC (min) to AVCC(max),
REFVSEL = {0, 1, 2}, REFON = 0 → 1
tSETTLE
VSD24REF
tON
µs
V
SD24_B internal reference
voltage
SD24REFS = 1
3 V
3 V
1.151 1.1623 1.174
200
SD24_B internal reference
turnon time
SD24REFS = 0→1, CREF = 100 nF
µs
(1) The internal reference current is supplied from the AVCC terminal. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an analog-to-digital conversion.
(2) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
(3) The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is already included in IREF+
.
(4) The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
(5) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
(6) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
(7) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
.
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5.19 Comparator_B
Table 5-52 lists the characteristics of the comparator.
Table 5-52. Comparator_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
VCC
Supply voltage
1.8
3.6
40
V
1.8 V
2.2 V
3 V
Comparator operating
supply current into
AVCC, excludes
CBPWRMD = 00, CBON = 1, CBRSx = 00
22
32
50
IAVCC_COMP
65
µA
CBPWRMD = 01, CBON = 1, CBRSx = 00
CBPWRMD = 10, CBON = 1, CBRSx = 00
10
30
reference resistor ladder
2.2 V, 3 V
0.2
0.85
CBREFACC = 1, CBREFLx = 01,
CBRSx = 10, REFON = 0, CBON = 0
Quiescent current of
resistor ladder into
AVCC, includes REF
module current
10
33
22
40
IAVCC_REF
2.2 V, 3 V
µA
CBREFACC = 0, CBREFLx = 01,
CBRSx = 10, REFON = 0, CBON = 0
Common-mode input
range
VIC
VOFFSET
CIN
0
VCC – 1
V
CBPWRMD = 00
–20
–20
20
20
Input offset voltage
Input capacitance
mV
CBPWRMD = 01 or 10
5
3
pF
kΩ
On (switch closed)
4
RSIN
Series input resistance
Off (switch open)
50
MΩ
CBPWRMD = 00, CBF = 0
CBPWRMD = 01, CBF = 0
CBPWRMD = 10, CBF = 0
450
600
50
ns
µs
Propagation delay,
response time
tPD
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 00
0.30
0.5
0.6
1.0
1.8
3.4
1
1.5
1.8
3.4
6.5
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 01
Propagation delay with
filter active
tPD,filter
µs
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 10
0.8
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 11
1.5
CBON = 0 to CBON = 1,
CBPWRMD = 00 or 01
2
100
1.5
tEN_CMP
Comparator enable time
µs
µs
CBON = 0 to CBON = 1, CBPWRMD = 10
Resistor reference
enable time
tEN_REF
TCREF
CBON = 0 to CBON = 1
1.0
Temperature coefficient
reference
ppm/
°C
50
VIN × VIN ×
(n + (n + 1)
VIN ×
(n +
Reference voltage for a
given tap
VIN = reference into resistor ladder,
n = 0 to 31
VCB_REF
V
1.5) / 32
/ 32 0.5) / 32
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Specifications
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MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
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5.20 Flash
Table 5-53 lists the characteristics of the flash memory.
Table 5-53. Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TJ
MIN
TYP
MAX UNIT
DVCC(PGM/ERASE)
IPGM
Program and erase supply voltage
1.8
3.6
5
V
Average supply current from DVCC during program
Average supply current from DVCC during erase
3
6
mA
mA
IERASE
15
IMERASE
IBANK
,
Average supply current from DVCC during mass erase or bank
erase
Cumulative program time(1)
6
15
16
mA
tCPT
ms
cycles
years
µs
Program and erase endurance
Data retention duration
Word or byte program time(2)
Block program time for first byte or word(2)
104
100
64
105
tRetention
tWord
25°C
85
65
tBlock, 0
49
µs
Block program time for each additional byte or word, except for
last byte or word(2)
Block program time for last byte or word(2)
tBlock, 1–(N–1)
tBlock, N
37
55
23
49
73
32
µs
µs
Erase time for segment erase, mass erase, and bank erase when
available(2)
tErase
ms
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
fMCLK,MGR
0
1
MHz
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word or byte write and block write modes.
(2) These values are hardwired into the state machine of the flash controller.
5.21 Emulation and Debug
Table 5-54 lists the characteristics of the JTAG and SBW interface.
Table 5-54. JTAG and Spy-Bi-Wire (SBW) Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Spy-Bi-Wire input frequency
VCC
MIN
0
TYP
MAX UNIT
fSBW
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
20
15
1
MHz
µs
tSBW,Low
tSBW, En
tSBW,Rst
Spy-Bi-Wire low clock pulse duration
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)(1)
0.025
µs
Spy-Bi-Wire return to normal operation time
15
0
100
5
µs
2.2 V
3 V
MHz
MHz
kΩ
fTCK
TCK input frequency for 4-wire JTAG(2)
Internal pulldown resistance on TEST
0
10
80
Rinternal
2.2 V, 3 V
45
60
(1) Tools that access the Spy-Bi-Wire interface must wait for the minimum tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
64
Specifications
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
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6 Detailed Description
6.1 Overview
The TI MSP430F67xxA family of polyphase metering SoCs are powerful highly-integrated solutions for
revenue meters that offer accuracy and low system cost with few external components. The
MSP430F67xxA uses the low-power MSP430 CPU with a 32-bit multiplier to perform all energy
calculations, metering applications such as tariff rate management, and communications with AMR and
AMI modules.
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
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6.2 Functional Block Diagrams
Figure 6-1 shows the functional block diagram for the MSP430F677xA, MSP430F676xA, and
MSP430F674xA devices in the PEU package.
PB
PC
PA
PD
PE
P9.x
P10.x
PF
DVCC DVSS AVCC AVSS
AUX1 AUX2 AUX3
XIN
XOUT
RST/NMI
P3.x
P4.x
P11.x
P5.x P6.x
P7.x P8.x
P1.x P2.x
(32 kHz)
ACLK
I/O Ports
P1, P2
2×8 I/Os
Interrupt,
Wakeup
I/O Ports
P3, P4
2×8 I/Os
I/O Ports
P5, P6
2×8 I/Os
I/O Ports
P7, P8
2×8 I/Os
I/O Ports
P9, P10
2×8 I/O
I/O Ports
P11
1×6 I/O
SYS
Unified
Clock
System
32KB
16KB
512KB
256KB
128KB
Watchdog
CRC16
MPY32
AES128
SMCLK
Port
Mapping
Controller
RAM
Flash
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
MCLK
PD
1×16 I/Os
PE
1×16 I/O
PF
1×6 I/O
CPUXV2
and
Working
Registers
(25 MHz)
EEM
(S: 8+2)
PMM
Auxiliary
Supplies
eUSCI_A0
eUSCI_A1
eUSCI_A2
eUSCI_A3
TA0
TA1
TA2
TA3
LCD_C
ADC10_A
REF
SD24_B
eUSCI_B0
eUSCI_B1
COMP_B
DMA
JTAG.
SBW
Interface
RTC_C
Timer_A
3 CC
Registers
(External
Voltage
Monitoring)
8-Mux
Up to 320
Segments
3 Channel
10 Bit
200 ksps
Reference
1.5 V, 2.0 V,
2.5 V
7 Channel
6 Channel
4 Channel
LDO,
SVM, SVS,
BOR
Timer_A
2 CC
Registers
(UART,
IrDA,SPI)
(SPI, I2C)
Port PJ
Copyright © 2016, Texas Instruments Incorporated
Figure 6-1. Functional Block Diagram – PEU Package
Figure 6-2 shows the functional block diagram for the MSP430F677xA, MSP430F676xA, and
MSP430F674xA devices in the PZ package.
PB
PC
PA
PD
DVCC DVSS AVCC AVSS
AUX1 AUX2 AUX3
XIN
XOUT
RST/NMI
P3.x
P4.x
P5.x P6.x
P7.x P8.x
P1.x P2.x
(32 kHz)
ACLK
I/O Ports
P1, P2
2×8 I/Os
Interrupt,
Wakeup
I/O Ports
P3, P4
2×8 I/Os
I/O Ports
P5, P6
2×8 I/Os
I/O Ports
P7, P8
1×8 I/Os
1×2 I/Os
SYS
Unified
Clock
System
32KB
16KB
512KB
256KB
128KB
Watchdog
CRC16
MPY32
AES128
SMCLK
Port
Mapping
Controller
RAM
Flash
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
MCLK
PD
1×10 I/Os
CPUXV2
and
Working
Registers
(25 MHz)
EEM
(S: 8+2)
PMM
Auxiliary
Supplies
eUSCI_A0
eUSCI_A1
eUSCI_A2
eUSCI_A3
TA0
TA1
TA2
TA3
LCD_C
ADC10_A
REF
SD24_B
eUSCI_B0
eUSCI_B1
COMP_B
DMA
JTAG,
SBW
Interface
RTC_C
Timer_A
3 CC
Registers
(External
Voltage
Monitoring)
8-Mux
Up to 320
Segments
3 Channel
10 Bit
200 ksps
Reference
1.5 V, 2.0 V,
2.5 V
7 Channel
6 Channel
4 Channel
LDO,
SVM, SVS,
BOR
Timer_A
2 CC
Registers
(UART,
IrDA,SPI)
(SPI, I2C)
Port PJ
Copyright © 2016, Texas Instruments Incorporated
Figure 6-2. Functional Block Diagram – PZ Package
66
Detailed Description
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
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6.3 CPU (Link to User's Guide)
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are
dedicated as program counter, stack pointer, status register, and constant generator, respectively. The
remaining registers are general-purpose registers (see Figure 6-3).
Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be
managed with all instructions.
Program Counter
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
Figure 6-3. CPU Registers
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Detailed Description
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MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
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6.4 Instruction Set
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data. Table 6-1 lists examples of the three types of instruction formats. Table 6-2 lists the address
modes.
Table 6-1. Instruction Word Formats
INSTRUCTION WORD FORMAT
Dual operands, source and destination
Single operands, destination only
EXAMPLE
ADD R4,R5
CALL R8
JNE
OPERATION
R4 + R5 → R5
PC → (TOS), R8 → PC
Jump-on-equal bit = 0
Relative jump, conditional or unconditional
Table 6-2. Address Mode Descriptions
ADDRESS MODE
Register
S(1)
✓
D(1)
SYNTAX
MOV Rs,Rd
EXAMPLE
OPERATION
✓
✓
✓
✓
MOV R10,R11
R10 → R11
Indexed
✓
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV & MEM, & TCDAT
MOV @Rn,Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
M(R10) → M(Tab+R6)
Symbolic (PC relative)
Absolute
✓
✓
Indirect
✓
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
M(R10) → R11
R10 + 2 → R10
Indirect autoincrement
✓
✓
MOV @Rn+,Rm
MOV #X,TONI
Immediate
#45 → M(TONI)
(1) S = source, D = destination
68
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
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6.5 Operating Modes
These microcontrollers have one active mode and six software-selectable low-power modes of operation.
An interrupt event can wake up the device from any of the five low-power modes, service the request, and
restore back to the low-power mode on return from the interrupt program.
Software can configure the following operating modes:
•
Active mode (AM)
All clocks are active
Low-power mode 0 (LPM0)
–
•
–
–
–
CPU is disabled
ACLK and SMCLK remain active, MCLK is disabled
FLL loop control remains active
•
•
Low-power mode 1 (LPM1)
–
–
–
CPU is disabled
FLL loop control is disabled
ACLK and SMCLK remain active, MCLK is disabled
Low-power mode 2 (LPM2)
–
–
–
–
CPU is disabled
MCLK and FLL loop control and DCOCLK are disabled
DC generator of the DCO remains enabled
ACLK remains active
•
•
Low-power mode 3 (LPM3)
–
–
–
–
CPU is disabled
MCLK, FLL loop control, and DCOCLK are disabled
DC generator of the DCO is disabled
ACLK remains active
Low-power mode 4 (LPM4)
–
–
–
–
–
–
CPU is disabled
ACLK is disabled
MCLK, FLL loop control, and DCOCLK are disabled
DC generator of the DCO is disabled
Crystal oscillator is stopped
Complete data retention
•
•
Low-power mode 3.5 (LPM3.5)
–
–
–
–
–
Internal regulator disabled
No RAM retention, backup RAM retained
I/O pad state retention
RTC clocked by low-frequency oscillator
Wake-up input from RST/NMI, RTC_C events, port P1, or port P2
Low-power mode 4.5 (LPM4.5)
–
–
–
–
–
Internal regulator disabled
No RAM retention, backup RAM retained
RTC is disabled
I/O pad state retention
Wake-up input from RST/NMI, port P1, or port P2
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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6.6 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see
Table 6-3). The vector contains the 16-bit address of the appropriate interrupt-handler instruction
sequence.
Table 6-3. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
System Reset
Power up
External reset
(2)
WDTIFG, KEYV (SYSRSTIV)(1)
Reset
0FFFEh
0FFFCh
63, highest
Watchdog time-out, key violation
Flash memory key violation
System NMI
PMM
Vacant memory access
JTAG mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBINIFG,
(Non)maskable
62
(1) (3)
JMBOUTIFG (SYSSNIV)
User NMI
NMI
Oscillator fault
NMIIFG, OFIFG, ACCVIFG, AUXSWGIFG
(SYSUNIV)(1) (3)
(Non)maskable
Maskable
0FFFAh
0FFF8h
61
60
Flash memory access violation
Supply switched
Watchdog Timer_A interval timer
mode
WDTIFG
eUSCI_A0 receive or transmit
eUSCI_B0 receive or transmit
UCA0RXIFG, UCA0TXIFG (UCA0IV)(1) (4)
UCB0RXIFG, UCB0TXIFG (UCB0IV)(1) (4)
Maskable
Maskable
0FFF6h
0FFF4h
59
58
ADC10IFG0, ADC10INIFG, ADC10LOIFG,
ADC10HIIFG, ADC10TOVIFG, ADC10OVIFG
(ADC10IV)(1) (4)
ADC10_A
Maskable
0FFF2h
57
SD24_B
SD24_B Interrupt Flags (SD24IV)(1) (4)
TA0CCR0 CCIFG0(4)
Maskable
Maskable
0FFF0h
0FFEEh
56
55
Timer TA0
TA0CCR1 CCIFG1, TA0CCR2 CCIFG2,
TA0IFG (TA0IV)(1) (4)
Timer TA0
Maskable
0FFECh
54
eUSCI_A1 receive or transmit
eUSCI_A2 receive or transmit
UCA1RXIFG, UCA1TXIFG (UCA1IV)(1) (4)
UCA2RXIFG, UCA2TXIFG (UCA2IV)(1) (4)
Maskable
Maskable
0FFEAh
0FFE8h
53
52
AUXSWGIFG, AUXIFG0, AUXIFG1, AUXIFG2
(AUXIV)(1) (4)
Auxiliary supplies
Maskable
0FFE6h
51
DMA
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1) (4)
TA1CCR0 CCIFG0(4)
Maskable
Maskable
0FFE4h
0FFE2h
50
49
Timer TA1
TA1CCR1 CCIFG1,
TA1IFG (TA1IV)(1) (4)
Timer TA1
Maskable
0FFE0h
48
eUSCI_A3 receive or transmit
eUSCI_B1 receive or transmit
I/O port P1
UCA3RXIFG, UCA3TXIFG (UCA3IV)(1) (4)
UCB1RXIFG, UCB1TXIFG (UCB1IV)(1) (4)
P1IFG.0 to P1IFG.7 (P1IV)(1) (4)
TA2CCR0 CCIFG0(4)
Maskable
Maskable
Maskable
Maskable
0FFDEh
0FFDCh
0FFDAh
0FFD8h
47
46
45
44
Timer TA2
TA2CCR1 CCIFG1,
TA2IFG (TA2IV)(1) (4)
Timer TA2
Maskable
0FFD6h
43
I/O port P2
Timer TA3
P2IFG.0 to P2IFG.7 (P2IV)(1) (4)
TA3CCR0 CCIFG0(4)
Maskable
Maskable
0FFD4h
0FFD2h
42
41
TA3CCR1 CCIFG1,
TA3IFG (TA3IV)(1) (4)
LCD_C Interrupt Flags (LCDCIV)(1) (4)
Timer TA3
LCD_C
Maskable
Maskable
0FFD0h
0FFCEh
40
39
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(3) (Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it.
(4) Interrupt flags are in the module.
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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Table 6-3. Interrupt Sources, Flags, and Vectors (continued)
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
RTCOFIFG, RTCRDYIFG, RTCTEVIFG,
RTC_C
Maskable
0FFCCh
38
RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV)(1) (4)
(1)
Comparator_B
AES
Comparator_B Interrupt Flags (CBIV)
Maskable
Maskable
0FFCAh
0FFC8h
0FFC6h
⋮
37
AESRDYIFG
36
35
Reserved
Reserved(5)
⋮
0FF80h
0, lowest
(5) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, TI recommends reserving these locations.
6.7 Special Function Registers (SFRs)
The SFRs are in the lowest address space and can be accessed in word or byte formats.
Legend
rw
Bit can be read and written.
rw-0, rw-1
rw-(0), rw-(1)
rw-[0], rw-[1]
–
Bit can be read and written. It is reset or set by PUC.
Bit can be read and written. It is reset or set by POR.
Bit can be read and written. It is reset or set by BOR.
SFR bit is not present in device.
Figure 6-4. Interrupt Enable 1 Register
15
–
14
–
13
–
12
–
11
–
10
–
9
8
–
AUXSWNMIE
rw-0
7
6
5
4
3
2
–
1
0
JMBOUTIE
rw-0
JMBINIE
rw-0
ACCVIE
rw-0
NMIIE
rw-0
VMAIE
rw-0
OFIE
rw-0
WDTIE
rw-0
Table 6-4. Interrupt Enable 1 Register Description
Bit
9
Field
AUXSWNMIE
Type
RW
RW
RW
RW
RW
RW
RW
Reset
0h
Description
Supply switched nonmaskable interrupt enable
JTAG mailbox output interrupt enable
JTAG mailbox input interrupt enable
Flash access violation interrupt enable
Nonmaskable interrupt enable
7
JMBOUTIE
JMBINIE
ACCVIE
NMIIE
0h
6
0h
5
0h
4
0h
3
VMAIE
0h
Vacant memory access interrupt enable
Oscillator fault interrupt enable
1
OFIE
0h
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if
watchdog timer is configured as a general-purpose timer.
0
WDTIE
RW
0h
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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Figure 6-5. Interrupt Flag 1 Register
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
6
5
–
4
3
2
–
1
0
JMBOUTIFG
rw-[0]
JMBINIFG
rw-[0]
NMIIFG
rw-0
VMAIFG
rw-0
OFIFG
rw-0
WDTIFG
rw-0
Table 6-5. Interrupt Flag 1 Register Description
Bit
7
Field
JMBOUTIFG
Type
RW
RW
RW
RW
RW
Reset
0h
Description
Set on JTAG mailbox output register ready for next message
Set on JTAG mailbox input message
Set by RST/NMI pin
6
JMBINIFG
NMIIFG
VMAIFG
OFIFG
0h
4
0h
3
0h
Set on vacant memory access
1
0h
Flag set on oscillator fault
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
0
WDTIFG
RW
0h
6.8 Bootloader (BSL)
The BSL enables users to program the flash memory or RAM using various serial interfaces.Table 6-6
lists the BSL interface pin requirements. Access to the device memory by the BSL is protected by an user-
defined password. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and
TEST/SBWTCK pins. For a complete description of the features of the BSL and its implementation, see
the MSP430™ Flash Device Bootloader (BSL) User's Guide.
Table 6-6. UART BSL Pin Requirements and Functions
DEVICE SIGNAL
RST/NMI/SBWTDIO
TEST/SBWTCK
P2.0
BSL FUNCTION
Entry sequence signal
Entry sequence signal
Data transmit
P2.1
Data receive
DVCC
Power supply
DVSS
Ground supply
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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6.9 JTAG Operation
6.9.1 JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. Table 6-7 lists the JTAG interface pin requirements.
For further details on interfacing to development tools and device programmers, see the MSP430
Hardware Tools User's Guide. For a complete description of the features of the JTAG interface and its
implementation, see MSP430 Programming With the JTAG Interface.
Table 6-7. JTAG Pin Requirements and Functions
DEVICE SIGNAL
PJ.3/TCK
DIRECTION
FUNCTION
JTAG clock input
JTAG state control
JTAG data input, TCLK input
JTAG data output
Enable JTAG pins
External reset
IN
IN
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
IN
OUT
IN
TEST/SBWTCK
RST/NMI/SBWTDIO
DVCC
IN
Power supply
DVSS
Ground supply
6.9.2 Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the 2-wire Spy-Bi-Wire interface.
Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table 6-8
lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the
features of the JTAG interface and its implementation, see MSP430 Programming With the JTAG
Interface.
Table 6-8. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
DVCC
DIRECTION
IN
FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input and output
Power supply
IN, OUT
DVSS
Ground supply
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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6.10 Memory
6.10.1 Memory Organization
Table 6-9 summarizes the memory map of the MSP430F67x9A, MSP430F67x8A, and MSP430F67x7A
devices.
Table 6-9. Memory Organization – MSP430F67x9A, MSP430F67x8A, and MSP430F67x7A
MSP430F6779A
MSP430F6769A
MSP430F6749A
MSP430F6778A
MSP430F6768A
MSP430F6748A
MSP430F6777A
MSP430F6767A
MSP430F6747A
Main memory (flash)
Main: interrupt vector
Total Size
512KB
512KB
256KB
00FFFFh to 00FF80h
00FFFFh to 00FF80h
00FFFFh to 00FF80h
128KB
08BFFFh to 06C000h
128KB
08BFFFh to 06C000h
Main: code memory
Bank 3
Bank 2
Bank 1
Not available
Not available
128KB
06BFFFh to 04C000h
128KB
06BFFFh to 04C000h
128KB
04BFFFh to 02C000h
128KB
04BFFFh to 02C000h
128KB
04BFFFh to 02C000h
128KB
02BFFFh to 00C000h
128KB
02BFFFh to 00C000h
128KB
02BFFFh to 00C000h
Bank 0
Total Size
Sector 7
RAM
32KB
16KB
32KB
4KB
4KB
Not available
009BFFh to 008C00h
009BFFh to 008C00h
4KB
4KB
Sector 6
Sector 5
Sector 4
Sector 3
Sector 2
Sector 1
Sector 0
Not available
Not available
Not available
008BFFh to 007C00h
008BFFh to 007C00h
4KB
4KB
007BFFh to 006C00h
007BFFh to 006C00h
4KB
4KB
006BFFh to 005C00h
006BFFh to 005C00h
4KB
4KB
4KB
005BFFh to 004C00h
005BFFh to 004C00h
005BFFh to 004C00h
4KB
4KB
4KB
004BFFh to 003C00h
004BFFh to 003C00h
004BFFh to 003C00h
4KB
4KB
4KB
003BFFh to 002C00h
003BFFh to 002C00h
003BFFh to 002C00h
4KB
4KB
4KB
002BFFh to 001C00h
002BFFh to 001C00h
002BFFh to 001C00h
128 B
128 B
128 B
001AFFh to 001A80h
001AFFh to 001A80h
001AFFh to 001A80h
Device descriptor
128 B
128 B
128 B
001A7Fh to 001A00h
001A7Fh to 001A00h
001A7Fh to 001A00h
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
Info A
Info B
Info C
Info D
BSL 3
BSL 2
BSL 1
BSL 0
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
Information memory (flash)
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
Bootloader (BSL) memory
(flash)
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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Table 6-9. Memory Organization – MSP430F67x9A, MSP430F67x8A, and MSP430F67x7A (continued)
MSP430F6779A
MSP430F6769A
MSP430F6749A
MSP430F6778A
MSP430F6768A
MSP430F6748A
MSP430F6777A
MSP430F6767A
MSP430F6747A
4KB
000FFFh to 0h
4KB
000FFFh to 0h
4KB
000FFFh to 0h
Peripherals
Table 6-10 summarizes the memory map of the MSP430F67x6A and MSP430F67x5A devices.
Table 6-10. Memory Organization – MSP430F67x6A and MSP430F67x5A
MSP430F6776A
MSP430F6766A
MSP430F6746A
MSP430F6775A
MSP430F6765A
MSP430F6745A
Main memory (flash)
Main: interrupt vector
Total Size
256KB
00FFFFh to 00FF80h
Not available
128KB
00FFFFh to 00FF80h
Not available
Bank 3
Bank 2
Not available
Not available
128KB
04BFFFh to 02C000h
Main: code memory
Bank 1
Bank 0
Not available
128KB
02BFFFh to 00C000h
128KB
02BFFFh to 00C000h
Total Size
Sector 7
Sector 6
Sector 5
Sector 4
16KB
16KB
Not available
Not available
Not available
Not available
Not available
Not available
Not available
Not available
4KB
4KB
Sector 3
Sector 2
Sector 1
Sector 0
RAM
005BFFh to 004C00h
005BFFh to 004C00h
4KB
4KB
004BFFh to 003C00h
004BFFh to 003C00h
4KB
4KB
003BFFh to 002C00h
003BFFh to 002C00h
4KB
4KB
002BFFh to 001C00h
002BFFh to 001C00h
128 B
128 B
001AFFh to 001A80h
001AFFh to 001A80h
Device descriptor
128 B
128 B
001A7Fh to 001A00h
001A7Fh to 001A00h
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
Info A
Info B
Info C
Info D
BSL 3
BSL 2
BSL 1
BSL 0
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
Information memory (flash)
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
Bootloader (BSL) memory
(flash)
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
4KB
000FFFh to 0h
4KB
000FFFh to 0h
Peripherals
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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6.10.2 Flash Memory (Link to User's Guide)
The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system
by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory.
Features of the flash memory include:
•
Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
•
•
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are
also called information memory.
•
Segment A can be locked separately.
6.10.3 RAM (Link to User's Guide)
The RAM is made up of n sectors. Each sector can be completely powered down to save leakage;
however, all data are lost in the sector that is powered down. Features of the RAM include:
•
•
•
RAM has n sectors of 4KB each.
Each sector 0 to n can be completely disabled; however, data retention is lost in the disabled sector.
Each sector 0 to n automatically enters low-power retention mode when possible.
6.10.4 Backup RAM (Link to User's Guide)
The backup RAM provides a limited number of bytes of RAM that are retained during LPM3.5. This
backup RAM is part of the backup subsystem that operates on dedicated power supply AUXVCC3. Eight
bytes of backup RAM are available in this device. The backup RAM can be word-wise accessed using the
registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3. The backup RAM registers cannot be
accessed by CPU when the high-side SVS is disabled by the user application.
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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6.11 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
controlled using all instructions. For complete module descriptions, see the MSP430x5xx and
MSP430x6xx Family User's Guide.
6.11.1 Oscillator and System Clock (Link to User's Guide)
The Unified Clock System (UCS) module includes support for a 32768-Hz watch crystal oscillator, an
internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator
(REFO), and an integrated internal digitally controlled oscillator (DCO). The UCS module is designed to
meet the requirements of both low system cost and low power consumption. The UCS module features
digital frequency-locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the
DCO frequency to a programmable multiple of the selected FLL reference frequency. The internal DCO
provides a fast turnon clock source and stabilizes in less than 5 µs. The UCS module provides the
following clock signals:
•
•
•
•
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, the internal low-frequency oscillator
(VLO), or the trimmed low-frequency oscillator (REFO).
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources made available to ACLK.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
6.11.2 Power-Management Module (PMM) (Link to User's Guide)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and
contains programmable output levels to provide for power optimization. The PMM also includes supply
voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection.
The brownout circuit is implemented to provide the proper internal reset signal to the device during power
on and power off. The SVS and SVM circuitry detects if the supply voltage drops below a user-selectable
level and supports both supply voltage supervision (the device is automatically reset) and supply voltage
monitoring (the device is not automatically reset). SVS and SVM circuitry is available on the primary
supply and core supply.
6.11.3 Auxiliary-Supply System (Link to User's Guide)
The auxiliary supply system provides the option to operate the device from auxiliary supplies when the
primary supply fails. There are two auxiliary supplies (AUXVCC1 and AUXVCC2) supported in
MSP430F67xx. This module supports automatic and manual switching from primary supply to auxiliary
supplies while maintaining full functionality. The auxiliary supply system allows threshold-based monitoring
of primary and auxiliary supplies. The device can be started from primary supply or AUXVCC1, whichever
is higher. Auxiliary supply system enables internal monitoring of voltage levels on primary and auxiliary
supplies using ADC10_A. This module also implements a simple charger for backup capacitors.
6.11.4 Backup Subsystem
The backup subsystem operates on a dedicated power supply AUXVCC3. This subsystem includes low-
frequency oscillator, real-time clock module, and backup RAM. The functionality of the backup subsystem
is retained during LPM3.5. The backup subsystem module registers cannot be accessed by CPU when
the high-side SVS is disabled by user.
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
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6.11.5 Digital I/O (Link to User's Guide)
Up to eleven 8-bit I/O ports are implemented. For 128-pin options, ports P1 to P10 are complete, and port
P11 is 6 bits wide. For 100-pin options, ports P1 to P7 are complete, port P8 is 2 bits wide, and ports P9,
P10, and P11 are completely removed. Port PJ contains four individual I/O pins, common to all devices.
All I/O bits are individually programmable.
•
•
•
•
Any combination of input, output, and interrupt conditions is possible.
Programmable pullup or pulldown on all ports.
Programmable drive strength on all ports.
Edge-selectable interrupt and LPM3.5, LPM4.5 wake-up input capability available for all bits of ports
P1 and P2.
•
•
Read-write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise (P1 to P11) or word-wise in pairs (PA to PF).
6.11.6 Port Mapping Controller (Link to User's Guide)
The port mapping controller allows flexible and reconfigurable mapping of digital functions to ports P2, P3,
and P4 (see Table 6-11). Table 6-12 lists the default settings for all pins that support port mapping.
Table 6-11. Port Mapping Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
PM_NONE
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
0
None
DVSS
PM_UCA0RXD
PM_UCA0SOMI
PM_UCA0TXD
PM_UCA0SIMO
PM_UCA0CLK
PM_UCA0STE
PM_UCA1RXD
PM_UCA1SOMI
PM_UCA1TXD
PM_UCA1SIMO
PM_UCA1CLK
PM_UCA1STE
PM_UCA2RXD
PM_UCA2SOMI
PM_UCA2TXD
PM_ UCA2SIMO
PM_UCA2CLK
PM_UCA2STE
PM_UCA3RXD
PM_UCA3SOMI
PM_UCA3TXD
PM_ UCA3SIMO
PM_UCA3CLK
PM_UCA3STE
PM_UCB0SIMO
PM_UCB0SDA
PM_UCB0SOMI
PM_UCB0SCL
PM_UCB0CLK
PM_UCB0STE
eUSCI_A0 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A0 UART TXD (direction controlled by eUSCI – Output)
eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A0 clock input/output (direction controlled by eUSCI)
eUSCI_A0 SPI slave transmit enable (direction controlled by eUSCI)
eUSCI_A1 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A1 UART TXD (direction controlled by eUSCI – Output)
eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A1 clock input/output (direction controlled by eUSCI)
eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)
eUSCI_A2 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A2 UART TXD (direction controlled by eUSCI – Output)
eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A2 clock input/output (direction controlled by eUSCI)
eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)
eUSCI_A3 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A3 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A3 UART TXD (direction controlled by eUSCI – Output)
eUSCI_A3 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A3 clock input/output (direction controlled by eUSCI)
eUSCI_A3 SPI slave transmit enable (direction controlled by eUSCI)
eUSCI_B0 SPI slave in master out (direction controlled by eUSCI)
eUSCI_B0 I2C data (open drain and direction controlled by eUSCI)
eUSCI_B0 SPI slave out master in (direction controlled by eUSCI)
eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI)
eUSCI_B0 clock input/output (direction controlled by eUSCI)
eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
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Table 6-11. Port Mapping Mnemonics and Functions (continued)
VALUE
PxMAPy MNEMONIC
PM_UCB1SIMO
PM_UCB1SDA
PM_UCB1SOMI
PM_UCB1SCL
PM_UCB1CLK
PM_UCB1STE
PM_TA0.0
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
eUSCI_B1 SPI slave in master out (direction controlled by eUSCI)
eUSCI_B1 I2C data (open drain and direction controlled by eUSCI)
eUSCI_B1 SPI slave out master in (direction controlled by eUSCI)
eUSCI_B1 I2C clock (open drain and direction controlled by eUSCI)
eUSCI_B1 clock input/output (direction controlled by eUSCI)
eUSCI_B1 SPI slave transmit enable (direction controlled by eUSCI)
21
22
23
24
25
26
27
28
29
30
TA0 CCR0 capture input CCI0A
TA0 CCR1 capture input CCI1A
TA0 CCR2 capture input CCI2A
TA1 CCR0 capture input CCI0A
TA2 CCR0 capture input CCI0A
TA3 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
TA0 CCR1 compare output Out1
TA0 CCR2 compare output Out2
TA1 CCR0 compare output Out0
TA2 CCR0 compare output Out0
TA3 CCR0 compare output Out0
PM_TA0.1
PM_TA0.2
PM_TA1.0
PM_TA2.0
PM_TA3.0
Disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals.
(1)
31 (0FFh)
PM_ANALOG
(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide, and the upper bits are
ignored, which results in a read value of 31.
Table 6-12. Default Port Mapping
PIN NAME
PxMAPy
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
MNEMONIC
PEU
P2.0/PM_TA0.0
P2.1/PM_TA0.1
P2.2/PM_TA0.2
P2.3/PM_TA1.0
P2.4/PM_TA2.0
PZ
P2.0/PM_TA0.0/COM4
P2.1/PM_TA0.1/COM5
P2.2/PM_TA0.2/COM6
P2.3/PM_TA1.0/COM7
P1.1/PM_TA2.0/R23
PM_TA0.0
PM_TA0.1
PM_TA0.2
PM_TA1.0
PM_TA2.0
TA0 CCR0 capture input CCI0A
TA0 CCR1 capture input CCI1A
TA0 CCR2 capture input CCI2A
TA1 CCR0 capture input CCI0A
TA2 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
TA0 CCR1 compare output Out1
TA0 CCR2 compare output Out2
TA1 CCR0 compare output Out0
TA2 CCR0 compare output Out0
P2.5/PM_UCB0SOMI/
PM_UCB0SCL
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/R13
PM_UCB0SOMI/
PM_UCB0SCL
eUSCI_B0 SPI slave out master in (direction controlled by eUSCI),
eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI)
P2.6/PM_UCB0SIMO/
PM_UCB0SDA
P2.6/PM_UCB0SIMO/
PM_UCB0SDA/R03
PM_UCB0SIMO/
PM_UCB0SDA
eUSCI_B0 SPI slave in master out (direction controlled by eUSCI),
eUSCI_B0 I2C data (open drain and direction controlled by eUSCI)
P2.7/PM_UCB0CLK
P2.7/PM_UCB0CLK/CB2
PM_UCB0CLK
eUSCI_B0 clock input/output (direction controlled by eUSCI)
P3.0/PM_UCA0RXD/
PM_UCA0SOMI
P3.0/PM_UCA0RXD/
PM_UCA0SOMI
PM_UCA0RXD/
PM_UCA0SOMI
eUSCI_A0 UART RXD (direction controlled by eUSCI – input),
eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)
P3.1/PM_UCA0TXD/
PM_UCA0SIMO
P3.1/PM_UCA0TXD/
PM_UCA0SIMO/S39
PM_UCA0TXD/
PM_UCA0SIMO
eUSCI_A0 UART TXD (direction controlled by eUSCI – output),
eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)
P3.2/PM_UCA0CLK
P3.3/PM_UCA1CLK
P3.2/PM_UCA0CLK/S38
P3.3/PM_UCA1CLK/S37
PM_UCA0CLK
PM_UCA1CLK
eUSCI_A0 clock input/output (direction controlled by eUSCI)
eUSCI_A1 clock input/output (direction controlled by eUSCI)
P3.4/PM_UCA1RXD/
PM_UCA1SOMI/
P3.4/PM_UCA1RXD/
PM_UCA1SOMI/S36
PM_UCA1RXD/
PM_UCA1SOMI
eUSCI_A1 UART RXD (direction controlled by eUSCI – input),
eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
P3.5/PM_UCA1TXD/
PM_UCA1SIMO
P3.5/PM_UCA1TXD/
PM_UCA1SIMO/S35
PM_UCA1TXD/
PM_UCA1SIMO
eUSCI_A1 UART TXD (direction controlled by eUSCI – output),
eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
P3.6/PM_UCA2RXD/
PM_UCA2SOMI/
P3.6/PM_UCA2RXD/
PM_UCA2SOMI/S34
PM_UCA2RXD/
PM_UCA2SOMI
eUSCI_A2 UART RXD (direction controlled by eUSCI – input),
eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
P3.7/PM_UCA2TXD/
PM_UCA2SIMO
P3.7/PM_UCA2TXD/
PM_UCA2SIMO/S33
PM_UCA2TXD/
PM_UCA2SIMO
eUSCI_A2 UART TXD (direction controlled by eUSCI – output),
eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
P4.0/PM_UCA2CLK
P4.0/PM_UCA2CLK/S32
PM_UCA2CLK
eUSCI_A2 clock input/output (direction controlled by eUSCI)
P4.1/PM_UCA3RXD/
PM_UCA3SOMI/
P4.1/PM_UCA3RXD/
PM_UCA3SOMI/S31
PM_UCA3RXD/
PM_UCA3SOMI
eUSCI_A3 UART RXD (direction controlled by eUSCI – input),
eUSCI_A3 SPI slave out master in (direction controlled by eUSCI)
P4.2/PM_UCA3TXD/
PM_UCA3SIMO
P4.2/PM_UCA3TXD/
PM_UCA3SIMO/S30
PM_UCA3TXD/
PM_UCA3SIMO
eUSCI_A3 UART TXD (direction controlled by eUSCI – output),
eUSCI_A3 SPI slave in master out (direction controlled by eUSCI)
P4.3/PM_UCA3CLK
P4.3/PM_UCA3CLK/S29
PM_UCA3CLK
eUSCI_A3 clock input/output (direction controlled by eUSCI)
P4.4/PM_UCB1SOMI/
PM_UCB1SCL
P4.4/PM_UCB1SOMI/
PM_UCB1SCL/S28
PM_UCB1SOMI/
PM_UCB1SCL
eUSCI_B1 SPI slave out master in (direction controlled by eUSCI),
eUSCI_B1 I2C clock (open drain and direction controlled by eUSCI)
P4.5/PM_UCB1SIMO/
PM_UCB1SDA
P4.5/PM_UCB1SIMO/
PM_UCB1SDA/S27
PM_UCB1SIMO/
PM_UCB1SDA
eUSCI_B1 SPI slave in master out (direction controlled by eUSCI),
eUSCI_B1 I2C data (open drain and direction controlled by eUSCI)
P4.6/PM_UCB1CLK
P4.7/PM_TA3.0
P4.6/PM_UCB1CLK/S26
P4.7/PM_TA3.0/S25
PM_UCB1CLK
PM_TA3.0
eUSCI_B1 clock input/output (direction controlled by eUSCI)
TA3 CCR0 capture input CCI0A
TA3 CCR0 compare output Out0
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6.11.7 System Module (SYS) (Link to User's Guide)
The SYS module handles many of the system functions within the device. These include power-on reset
(POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector
generators, bootloader entry mechanisms, and configuration management (device descriptors). The SYS
module also includes a data exchange mechanism using JTAG called a JTAG mailbox that can be used in
the application. Table 6-13 lists the SYS module interrupt vector registers.
Table 6-13. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER
ADDRESS
INTERRUPT EVENT
No interrupt pending
Brownout (BOR)
RST/NMI (POR)
DoBOR (BOR)
Wake up from LPMx.5
Security violation (BOR)
SVSL (POR)
VALUE
00h
PRIORITY
02h
Highest
04h
06h
08h
0Ah
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
SVMH_OVP (POR)
DoPOR (POR)
WDT time-out (PUC)
WDT key violation (PUC)
KEYV flash key violation (PUC)
Reserved
10h
SYSRSTIV, System Reset
019Eh
12h
14h
16h
18h
1Ah
1Ch
Peripheral area fetch (PUC)
PMM key violation (PUC)
Reserved
1Eh
20h
22h to 3Eh
00h
Lowest
Highest
No interrupt pending
SVMLIFG
02h
SVMHIFG
04h
DLYLIFG
06h
DLYHIFG
08h
SYSSNIV, System NMI
019Ch
VMAIFG
0Ah
JMBINIFG
0Ch
JMBOUTIFG
0Eh
VLRLIFG
10h
VLRHIFG
12h
Reserved
14h to 1Eh
00h
Lowest
Highest
No interrupt pending
NMIIFG
02h
OFIFG
04h
SYSUNIV, User NMI
019Ah
ACCVIFG
06h
AUXSWGIFG
08h
Reserved
0Ah to 1Eh
Lowest
6.11.8 Watchdog Timer (WDT_A) (Link to User's Guide)
The primary function of the WDT_A is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not
needed in an application, the timer can be configured as an interval timer and can generate interrupts at
selected time intervals.
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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6.11.9 DMA Controller (Link to User's Guide)
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC10_A conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral. Table 6-14 lists the available DMA triggers.
Table 6-14. DMA Trigger Assignments(1)
CHANNEL
TRIGGER
0
1
2
0
DMAREQ
DMAREQ
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
Reserved
2
3
4
5
TA2CCR0 CCIFG
Reserved
TA2CCR0 CCIFG
Reserved
TA2CCR0 CCIFG
Reserved
6
7
TA3CCR0 CCIFG
Reserved
TA3CCR0 CCIFG
Reserved
TA3CCR0 CCIFG
Reserved
8
9
Reserved
Reserved
Reserved
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SD24IFG
SD24IFG
SD24IFG
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
UCA0RXIFG
UCA0TXIFG
UCA1RXIFG
UCA1TXIFG
UCA2RXIFG
UCA2TXIFG
UCB0RXIFG0
UCB0TXIFG0
ADC10IFG0
UCA3RXIFG
UCA3TXIFG
UCB1RXIFG0
UCB1TXIFG0
MPY ready
UCA0RXIFG
UCA0TXIFG
UCA1RXIFG
UCA1TXIFG
UCA2RXIFG
UCA2TXIFG
UCB0RXIFG0
UCB0TXIFG0
ADC10IFG0
UCA3RXIFG
UCA3TXIFG
UCB1RXIFG0
UCB1TXIFG0
MPY ready
UCA0RXIFG
UCA0TXIFG
UCA1RXIFG
UCA1TXIFG
UCA2RXIFG
UCA2TXIFG
UCB0RXIFG0
UCB0TXIFG0
ADC10IFG0
UCA3RXIFG
UCA3TXIFG
UCB1RXIFG0
UCB1TXIFG0
MPY ready
DMA2IFG
DMA0IFG
DMA1IFG
Reserved
Reserved
Reserved
(1) Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers do not
cause any DMA trigger event when selected.
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
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6.11.10 CRC16 (Link to User's Guide)
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
6.11.11 Hardware Multiplier (Link to User's Guide)
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication
as well as signed and unsigned multiply-and-accumulate operations.
6.11.12 AES128 Accelerator (Link to User's Guide)
The AES accelerator module performs encryption and decryption of 128-bit data with 128-bit keys
according to the Advanced Encryption Standard (AES) (FIPS PUB 197) in hardware.
6.11.13 Enhanced Universal Serial Communication Interface (eUSCI) (Links to User's
Guide: UART Mode, SPI Mode, I2C Mode)
The eUSCI module is used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3- or 4-pin) and I2C, and asynchronous communication protocols
such as UART, enhanced UART with automatic baud-rate detection, and IrDA.
The eUSCI_An module provides support for SPI (3- or 4-pin), UART, enhanced UART, and IrDA.
The eUSCI_Bn module provides support for SPI (3- or 4-pin) and I2C.
Four eUSCI_A and two eUSCI_B module are implemented in the MSP430F67xxA MCUs.
6.11.14 ADC10_A (Link to User's Guide)
The ADC10_A module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit
SAR core, sample select control, reference generator and a conversion results buffer. A window
comparator with a lower and upper limit allows CPU independent result monitoring with three window
comparator interrupt flags.
6.11.15 SD24_B (Link to User's Guide)
The SD24_B module integrates up to seven independent 24-bit sigma-delta ADCs. Each converter is
designed with a fully differential analog input pair and programmable gain amplifier input stage. Also the
converters are based on second-order oversampling sigma-delta modulators and digital decimation filters.
The decimation filters are comb filters with selectable oversampling ratios of up to 1024.
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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6.11.16 TA0 (Link to User's Guide)
TA0 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA0 can support
multiple capture/compares, PWM outputs, and interval timing (see Table 6-15). TA0 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
Table 6-15. TA0 Signal Connections
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE OUTPUT
SIGNAL
MODULE BLOCK
DEVICE OUTPUT SIGNAL
PM_TACLK
ACLK (internal)
SMCLK (internal)
PM_TACLK
PM_TA0.0
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
NA
NA
PM_TA0.0
CBOUT (internal)
DVSS
CCR0
CCR1
CCR2
TA0
DVCC
VCC
PM_TA0.1
CCI1A
PM_TA0.1
ADC10_A (internal)
ADC10SHSx = 001b
ACLK (internal)
DVSS
CCI1B
GND
TA1
TA2
SD24_B (internal)
SD24CHx.SD24SCSx = 001b
DVCC
PM_TA0.2
DVSS
VCC
CCI2A
CCI2B
GND
PM_TA0.2
DVSS
DVCC
VCC
6.11.17 TA1 (Link to User's Guide)
TA1 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers (see Table 6-16). TA1
can support multiple capture/compares, PWM outputs, and interval timing. TA1 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
Table 6-16. TA1 Signal Connections
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
DEVICE INPUT SIGNAL
MODULE INPUT NAME
MODULE BLOCK
PM_TACLK
ACLK (internal)
SMCLK (internal)
PM_TACLK
PM_TA1.0
CBOUT (internal)
DVSS
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
NA
TA0
TA1
NA
PM_TA1.0
CCR0
CCR1
DVCC
VCC
PM_TA1.1
ACLK (internal)
DVSS
CCI1A
CCI1B
GND
PM_TA1.1
DVCC
VCC
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6.11.18 TA2 (Link to User's Guide)
TA2 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA2 can support multiple
capture/compares, PWM outputs, and interval timing (see Table 6-17). TA2 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-17. TA2 Signal Connections
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE OUTPUT
SIGNAL
MODULE BLOCK
DEVICE OUTPUT SIGNAL
PM_TACLK
ACLK (internal)
SMCLK (internal)
PM_TACLK
PM_TA2.0
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
NA
NA
PM_TA2.0
CBOUT (internal)
DVSS
CCR0
CCR1
TA0
DVCC
VCC
PM_TA2.1
CCI1A
PM_TA2.1
SD24_B (internal)
SD24CHx.SD24SCSx = 010b
ACLK (internal)
CCI1B
TA1
DVSS
DVCC
GND
VCC
6.11.19 TA3 (Link to User's Guide)
TA3 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA3 can support multiple
capture/compares, PWM outputs, and interval timing (see Table 6-18). TA3 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-18. TA3 Signal Connections
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE OUTPUT
SIGNAL
MODULE BLOCK
DEVICE OUTPUT SIGNAL
PM_TACLK
ACLK (internal)
SMCLK (internal)
PM_TACLK
TACLK
ACLK
Timer
NA
SMCLK
INCLK
CCI0A
PM_TA3.0
PM_TA3.0
ADC10_A (internal)
ADC10SHSx = 010b
CBOUT (internal)
CCI0B
CCR0
CCR1
TA0
DVSS
DVCC
GND
VCC
PM_TA3.1
CCI1A
PM_TA3.1
SD24_B (internal)
SD24CHx.SD24SCSx = 011b
ACLK (internal)
CCI1B
TA1
DVSS
DVCC
GND
VCC
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
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6.11.20 SD24_B Triggers
Table 6-19 lists the input trigger connections to SD24_B converters from Timer_A modules and output
trigger pulse connection from SD24_B to ADC10_A.
Table 6-19. SD24_B Input/Output Trigger Connections
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
DEVICE INPUT SIGNAL
TA0.1 (internal)
MODULE INPUT SIGNAL
MODULE BLOCK
SD24_B
SD24CHx.SD24SCSx = 001b
ADC10_A (internal)
ADC10SHSx = 011b
Trigger Pulse
SD24_B
SD24CHx.SD24SCSx = 010b
TA2.1 (internal)
SD24_B
SD24_B
SD24CHx.SD24SCSx = 011b
TA3.1 (internal)
6.11.21 ADC10_A Triggers
Table 6-20 lists the input trigger connections to ADC10_A from Timer_A modules and SD24_B.
Table 6-20. ADC10_A Input Trigger Connections
DEVICE INPUT SIGNAL
MODULE INPUT SIGNAL
MODULE BLOCK
ADC10_A
ADC10SHSx = 001b
TA0.1 (internal)
ADC10_A
ADC10SHSx = 010b
TA3.0 (internal)
ADC10_A
SD24_B
ADC10_A
trigger pulse (internal)
ADC10SHSx = 011b
6.11.22 Real-Time Clock (RTC_C) (Link to User's Guide)
The RTC_C module can be configured for calendar mode providing seconds, hours, day of week, day of
month, month, and year. The RTC_C control and configuration registers are password protected to ensure
clock integrity against runaway code. Calendar mode integrates an internal calendar that compensates for
months with less than 31 days and includes leap year correction. The RTC_C also supports flexible alarm
functions, offset calibration, temperature compensation, and time capture on two external events. The
RTC_C on this device operates on dedicated AUXVCC3 supply and supports operation in LPM3.5.
6.11.23 Reference (REF) Module Voltage Reference (Link to User's Guide)
The REF module generates all of the critical reference voltages that can be used by the various analog
peripherals in the device. The analog peripherals include the ADC10_A, LCD_C, and SD24_B modules.
6.11.24 LCD_C (Link to User's Guide)
The LCD_C driver generates the segment and common signals required to drive a liquid crystal display
(LCD). The LCD_C controller has dedicated data memories to hold segment drive information. Common
and segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, 4-mux, up to 8-mux
LCDs are supported. The module can provide a LCD voltage independent of the supply voltage with its
integrated charge pump. It is possible to control the level of the LCD voltage, and thus contrast, by
software. The module also provides an automatic blinking capability for individual segments in static, 2-
mux, 3-mux, and 4-mux modes.
6.11.25 Comparator_B (Link to User's Guide)
The primary function of the Comparator_B module is to support precision slope analog-to-digital
conversions, battery voltage supervision, and monitoring of external analog signals.
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MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
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6.11.26 Embedded Emulation Module (EEM) (Link to User's Guide)
The EEM supports real-time in-system debugging. The L version of the EEM has the following features:
•
•
•
•
•
•
•
Eight hardware triggers or breakpoints on memory access
Two hardware triggers or breakpoints on CPU register write access
Up to 10 hardware triggers that can be combined to form complex triggers or breakpoints
Two cycle counters
Sequencer
State storage
Clock control on module level
6.11.27 Peripheral File Map
Table 6-21 shows the base address for the registers of each supported peripheral. Table 6-22 through
Table 6-64 show the offset addresses for each register. For complete description of these registers, see
the MSP430x5xx and MSP430x6xx Family User's Guide.
Table 6-21. Peripherals
OFFSET ADDRESS
MODULE NAME
BASE ADDRESS
RANGE
Special Functions (see Table 6-22)
PMM (see Table 6-23)
0100h
0120h
0140h
0150h
0158h
015Ch
0160h
0180h
01B0h
01C0h
01D0h
01D8h
01E0h
0200h
0220h
0240h
0260h
000h to 01Fh
000h to 01Fh
000h to 00Fh
000h to 007h
000h to 001h
000h to 001h
000h to 01Fh
000h to 01Fh
000h to 001h
000h to 007h
000h to 007h
000h to 007h
000h to 007h
000h to 01Fh
000h to 00Bh
000h to 00Bh
000h to 00Bh
Flash Control (see Table 6-24)
CRC16 (see Table 6-25)
RAM Control (see Table 6-26)
Watchdog (see Table 6-27)
UCS (see Table 6-28)
SYS (see Table 6-29)
Shared Reference (see Table 6-30)
Port Mapping Control (see Table 6-31)
Port Mapping Port P2 (see Table 6-32)
Port Mapping Port P3 (see Table 6-33)
Port Mapping Port P4 (see Table 6-34)
Port P1, P2 (see Table 6-35)
Port P3, P4 (see Table 6-36)
Port P5, P6 (see Table 6-37)
Port P7, P8 (see Table 6-38)
Port P9, P10 (see Table 6-39)
(Ports P9 and P10 not available in PZ package)
0280h
02A0h
000h to 00Bh
000h to 00Bh
Port P11 (see Table 6-40)
(Port P11 not available in PZ package)
Port PJ (see Table 6-41)
Timer TA0 (see Table 6-42)
0320h
0340h
0380h
0400h
0440h
0480h
04C0h
0500h
0500h
0500h
000h to 01Fh
000h to 03Fh
000h to 03Fh
000h to 03Fh
000h to 03Fh
000h to 00Fh
000h to 02Fh
000h to 00Fh
010h to 01Fh
020h to 02Fh
Timer TA1 (see Table 6-43)
Timer TA2 (see Table 6-44)
Timer TA3 (see Table 6-45)
Backup Memory (see Table 6-46)
32-Bit Hardware Multiplier (see Table 6-48)
DMA General Control (see Table 6-49)
DMA Channel 0 (see Table 6-50)
DMA Channel 1 (see Table 6-51)
86
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MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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Table 6-21. Peripherals (continued)
OFFSET ADDRESS
MODULE NAME
BASE ADDRESS
RANGE
DMA Channel 2 (see Table 6-52)
RTC_C (see Table 6-47)
0500h
0C80h
05C0h
05E0h
0600h
0620h
0640h
0680h
0740h
0800h
08C0h
09C0h
09E0h
0A00h
030h to 03Fh
000h to 03Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 02Fh
000h to 02Fh
000h to 01Fh
000h to 06Fh
000h to 00Fh
000h to 00Fh
000h to 01Fh
000h to 05Fh
eUSCI_A0 (see Table 6-53)
eUSCI_A1 (see Table 6-54)
eUSCI_A2 (see Table 6-55)
eUSCI_A3 (see Table 6-56)
eUSCI_B0 (see Table 6-57)
eUSCI_B1 ( see Table 6-58 )
ADC10_A (see Table 6-59)
SD24_B (see Table 6-60)
Comparator_B (see Table 6-61 )
AES Accelerator (see Table 6-62)
Auxiliary Supply (see Table 6-63)
LCD_C (see Table 6-64)
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
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Table 6-22. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
SFRIE1
OFFSET
SFR interrupt enable
SFR interrupt flag
00h
02h
04h
SFRIFG1
SFR reset pin control
SFRRPCR
Table 6-23. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
PMMCTL0
OFFSET
PMM control 0
00h
02h
04h
06h
0Ch
0Eh
10h
PMM control 1
PMMCTL1
SVSMHCTL
SVSMLCTL
PMMIFG
SVS high-side control
SVS low-side control
PMM interrupt flags
PMM interrupt enable
PMM power mode 5 control 0
PMMIE
PM5CTL0
Table 6-24. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Flash control 1
Flash control 3
Flash control 4
FCTL1
FCTL3
FCTL4
00h
04h
06h
Table 6-25. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
CRC16DI
OFFSET
CRC data input
CRC result
00h
04h
CRCINIRES
Table 6-26. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
REGISTER
RCCTL0
OFFSET
OFFSET
OFFSET
RAM control 0
00h
00h
Table 6-27. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
REGISTER
WDTCTL
Watchdog timer control
Table 6-28. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
UCSCTL0
UCS control 0
UCS control 1
UCS control 2
UCS control 3
UCS control 4
UCS control 5
UCS control 6
UCS control 7
UCS control 8
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
UCSCTL1
UCSCTL2
UCSCTL3
UCSCTL4
UCSCTL5
UCSCTL6
UCSCTL7
UCSCTL8
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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Table 6-29. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
SYSCTL
OFFSET
System control
00h
02h
06h
08h
0Ah
0Ch
0Eh
18h
1Ah
1Ch
1Eh
Bootloader configuration area
JTAG mailbox control
SYSBSLC
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSBERRIV
SYSUNIV
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
Bus Error vector generator
User NMI vector generator
System NMI vector generator
Reset vector generator
SYSSNIV
SYSRSTIV
Table 6-30. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
REGISTER
REFCTL
OFFSET
OFFSET
Shared reference control
00h
Table 6-31. Port Mapping Controller (Base Address: 01C0h)
REGISTER DESCRIPTION
REGISTER
PMAPPWD
PMAPCTL
Port mapping password
Port mapping control
00h
02h
Table 6-32. Port Mapping for Port P2 (Base Address: 01D0h)
REGISTER DESCRIPTION
REGISTER
P2MAP0
OFFSET
Port P2.0 mapping
Port P2.1 mapping
Port P2.2 mapping
Port P2.3 mapping
Port P2.4 mapping
Port P2.5 mapping
Port P2.6 mapping
Port P2.7 mapping
00h
01h
02h
03h
04h
05h
06h
07h
P2MAP1
P2MAP2
P2MAP3
P2MAP4
P2MAP5
P2MAP6
P2MAP7
Table 6-33. Port Mapping for Port P3 (Base Address: 01D8h)
REGISTER DESCRIPTION
REGISTER
P3MAP0
OFFSET
Port P3.0 mapping
Port P3.1 mapping
Port P3.2 mapping
Port P3.3 mapping
Port P3.4 mapping
Port P3.5 mapping
Port P3.6 mapping
Port P3.7 mapping
00h
01h
02h
03h
04h
05h
06h
07h
P3MAP1
P3MAP2
P3MAP3
P3MAP4
P3MAP5
P3MAP6
P3MAP7
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MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
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Table 6-34. Port Mapping for Port P4 (Base Address: 01E0h)
REGISTER DESCRIPTION
REGISTER
P4MAP0
OFFSET
Port P4.0 mapping
Port P4.1 mapping
Port P4.2 mapping
Port P4.3 mapping
Port P4.4 mapping
Port P4.5 mapping
Port P4.6 mapping
Port P4.7 mapping
00h
01h
02h
03h
04h
05h
06h
07h
P4MAP1
P4MAP2
P4MAP3
P4MAP4
P4MAP5
P4MAP6
P4MAP7
Table 6-35. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
18h
1Ah
1Ch
01h
03h
05h
07h
09h
0Bh
0Dh
1Eh
19h
1Bh
1Dh
Port P1 output
P1OUT
P1DIR
P1REN
P1DS
Port P1 direction
Port P1 resistor enable
Port P1 drive strength
Port P1 selection 0
P1SEL0
P1SEL1
P1IV
Port P1 selection 1
Port P1 interrupt vector word
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
P1IES
P1IE
P1IFG
P2IN
Port P2 output
P2OUT
P2DIR
P2REN
P2DS
Port P2 direction
Port P2 resistor enable
Port P2 drive strength
Port P2 selection 0
Port P2 selection 1(1)
Port P2 interrupt vector word
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
P2SEL0
P2SEL1
P2IV
P2IES
P2IE
P2IFG
(1) P2SEL1 is an empty control register to be consistent with P1SEL1 in 16-bit access.
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MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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Table 6-36. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
02h
04h
06h
08h
0Ah
01h
03h
05h
07h
09h
0Bh
Port P3 output
P3OUT
P3DIR
P3REN
P3DS
Port P3 direction
Port P3 resistor enable
Port P3 drive strength
Port P3 selection 0
Port P4 input
P3SEL0
P4IN
Port P4 output
P4OUT
P4DIR
P4REN
P4DS
Port P4 direction
Port P4 resistor enable
Port P4 drive strength
Port P4 selection 0
P4SEL0
Table 6-37. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
02h
04h
06h
08h
0Ah
0Ch
01h
03h
05h
07h
09h
0Bh
0Dh
Port P5 output
P5OUT
P5DIR
P5REN
P5DS
Port P5 direction
Port P5 resistor enable
Port P5 drive strength
Port P5 selection 0
Port P5 selection 1
Port P6 input
P5SEL0
P5SEL1
P6IN
Port P6 output
P6OUT
P6DIR
P6REN
P6DS
Port P6 direction
Port P6 resistor enable
Port P6 drive strength
Port P6 selection 0
Port P6 selection 1(1)
P6SEL0
P6SEL1
(1) P6SEL1 is an empty control register to be consistent with P5SEL1 in 16-bit access.
Table 6-38. Port P7, P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 input
P7IN
00h
02h
04h
06h
08h
0Ah
01h
03h
05h
07h
09h
0Bh
Port P7 output
P7OUT
P7DIR
P7REN
P7DS
Port P7 direction
Port P7 resistor enable
Port P7 drive strength
Port P7 selection 0
Port P8 input
P7SEL0
P8IN
Port P8 output
P8OUT
P8DIR
P8REN
P8DS
Port P8 direction
Port P8 resistor enable
Port P8 drive strength
Port P8 selection 0
P8SEL0
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 6-39. Port P9, P10 Registers (Base Address: 0280h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P9 input
P9IN
00h
02h
04h
06h
08h
0Ah
01h
03h
05h
07h
09h
0Bh
Port P9 output
P9OUT
P9DIR
P9REN
P9DS
Port P9 direction
Port P9 resistor enable
Port P9 drive strength
Port P9 selection 0
Port P10 input
P9SEL0
P10IN
Port P10 output
P10OUT
P10DIR
P10REN
P10DS
Port P10 direction
Port P10 resistor enable
Port P10 drive strength
Port P10 selection 0
P10SEL0
Table 6-40. Port 11 Registers (Base Address: 02A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
OFFSET
OFFSET
Port P11 input
P11IN
00h
02h
04h
06h
08h
0Ah
Port P11 output
P11OUT
P11DIR
P11REN
P11DS
Port P11 direction
Port P11 resistor enable
Port P11 drive strength
Port P11 selection 0
P11SEL0
Table 6-41. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
Port PJ input
PJIN
00h
02h
04h
06h
08h
0Ah
Port PJ output
PJOUT
PJDIR
PJREN
PJDS
Port PJ direction
Port PJ resistor enable
Port PJ drive strength
Port PJ selection
PJSEL
Table 6-42. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
TA0CTL
TA0 control
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA0 counter
TA0CCTL0
TA0CCTL1
TA0CCTL2
TA0R
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA0 expansion 0
TA0CCR0
TA0CCR1
TA0CCR2
TA0EX0
TA0 interrupt vector
TA0IV
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 6-43. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
TA1CTL
OFFSET
OFFSET
OFFSET
OFFSET
TA1 control
00h
02h
04h
10h
12h
14h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
TA1 counter
TA1CCTL0
TA1CCTL1
TA1R
Capture/compare 0
Capture/compare 1
TA1 expansion 0
TA1CCR0
TA1CCR1
TA1EX0
TA1IV
TA1 interrupt vector
Table 6-44. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
TA2CTL
TA2 control
00h
02h
04h
10h
12h
14h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
TA2 counter
TA2CCTL0
TA2CCTL1
TA2R
Capture/compare 0
Capture/compare 1
TA2 expansion 0
TA2CCR0
TA2CCR1
TA2EX0
TA2IV
TA2 interrupt vector
Table 6-45. TA3 Registers (Base Address: 0440h)
REGISTER DESCRIPTION
REGISTER
TA3CTL
TA3 control
00h
02h
04h
10h
12h
14h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
TA3 counter
TA3CCTL0
TA3CCTL1
TA3R
Capture/compare 0
Capture/compare 1
TA3 expansion 0
TA3CCR0
TA3CCR1
TA3EX0
TA3IV
TA3 interrupt vector
Table 6-46. Backup Memory Registers (Base Address: 0480h)
REGISTER DESCRIPTION
REGISTER
BAKMEM0
Backup memory 0
Backup memory 1
Backup memory 2
Backup memory 3
00h
02h
04h
06h
BAKMEM1
BAKMEM2
BAKMEM3
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 6-47. RTC_C Registers (Base Address: 0C80h)
REGISTER DESCRIPTION
REGISTER
RTCCTL0
OFFSET
RTC control 0
00h
01h
02h
03h
04h
06h
08h
0Ah
0Ch
0Dh
0Eh
10h
11h
12h
13h
14h
15h
16h
18h
19h
1Ah
1Bh
1Ch
1Eh
20h
21h
22h
30h
31h
32h
33h
34h
36h
38h
39h
3Ah
3Bh
3Ch
3Eh
RTC password
RTC control 1
RTCPWD
RTCCTL1
RTC control 3
RTCCTL3
RTC offset calibration
RTCOCAL
RTC temperature compensation
RTC prescaler 0 control
RTC prescaler 1 control
RTC prescaler 0
RTCTCMP
RTCPS0CTL
RTCPS1CTL
RTCPS0
RTC prescaler 1
RTCPS1
RTC interrupt vector word
RTC seconds
RTCIV
RTCSEC
RTC minutes
RTCMIN
RTC hours
RTCHOUR
RTCDOW
RTC day of week
RTC days
RTCDAY
RTC month
RTCMON
RTC year
RTCYEAR
RTC alarm minutes
RTC alarm hours
RTCAMIN
RTCAHOUR
RTCADOW
RTCADAY
RTC alarm day of week
RTC alarm days
Binary-to-BCD conversion
BCD-to-binary conversion
Real-time clock time capture control
Tamper detect pin 0 control
Tamper detect pin 1 control
RTC seconds backup 0
RTC minutes backup 0
RTC hours backup 0
RTC days backup 0
RTC month backup 0
RTC year backup 0
RTC seconds backup 1
RTC minutes backup 1
RTC hours backup 1
RTC days backup 1
RTC month backup 1
RTC year backup 1
BIN2BCD
BCD2BIN
RTCTCCTL
RTCCAP0CTL
RTCCAP1CTL
RTCSECBAK0
RTCMINBAK0
RTCHOURBAK0
RTCDAYBAK0
RTCMONBAK0
RTCYEARBAK0
RTCSECBAK1
RTCMINBAK1
RTCHOURBAK1
RTCDAYBAK1
RTCMONBAK1
RTCYEARBAK1
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 6-48. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
16-bit operand 1 – signed multiply
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
MPYS
MAC
MACS
OP2
16 × 16 result low word
RESLO
RESHI
16 × 16 result high word
16 × 16 sum extension
SUMEXT
MPY32L
MPY32H
MPYS32L
MPYS32H
MAC32L
MAC32H
MACS32L
MACS32H
OP2L
32-bit operand 1 – multiply low word
32-bit operand 1 – multiply high word
32-bit operand 1 – signed multiply low word
32-bit operand 1 – signed multiply high word
32-bit operand 1 – multiply accumulate low word
32-bit operand 1 – multiply accumulate high word
32-bit operand 1 – signed multiply accumulate low word
32-bit operand 1 – signed multiply accumulate high word
32-bit operand 2 – low word
32-bit operand 2 – high word
OP2H
32 × 32 result 0 – least significant word
32 × 32 result 1
RES0
RES1
32 × 32 result 2
RES2
32 × 32 result 3 – most significant word
MPY32 control 0
RES3
MPY32CTL0
Table 6-49. DMA General Control Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
DMACTL0
OFFSET
DMA module control 0
DMA module control 1
DMA module control 2
DMA module control 3
DMA module control 4
DMA interrupt vector
00h
02h
04h
06h
08h
0Eh
DMACTL1
DMACTL2
DMACTL3
DMACTL4
DMAIV
Table 6-50. DMA Channel 0 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
DMA0CTL
OFFSET
DMA channel 0 control
10h
12h
14h
16h
18h
1Ah
DMA channel 0 source address low
DMA channel 0 source address high
DMA channel 0 destination address low
DMA channel 0 destination address high
DMA channel 0 transfer size
DMA0SAL
DMA0SAH
DMA0DAL
DMA0DAH
DMA0SZ
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 6-51. DMA Channel 1 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
DMA1CTL
OFFSET
DMA channel 1 control
20h
22h
24h
26h
28h
2Ah
DMA channel 1 source address low
DMA channel 1 source address high
DMA channel 1 destination address low
DMA channel 1 destination address high
DMA channel 1 transfer size
DMA1SAL
DMA1SAH
DMA1DAL
DMA1DAH
DMA1SZ
Table 6-52. DMA Channel 2 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
DMA2CTL
OFFSET
DMA channel 2 control
30h
32h
34h
36h
38h
3Ah
DMA channel 2 source address low
DMA channel 2 source address high
DMA channel 2 destination address low
DMA channel 2 destination address high
DMA channel 2 transfer size
DMA2SAL
DMA2SAH
DMA2DAL
DMA2DAH
DMA2SZ
Table 6-53. eUSCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
UCA0CTLW0
OFFSET
USCI_A control word 0
USCI _A control word 1
USCI_A baud rate 0
USCI_A baud rate 1
USCI_A modulation control
USCI_A status
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
UCA0CTLW1
UCA0BR0
UCA0BR1
UCA0MCTLW
UCA0STAT
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
UCA0IRTCTL
UCA0IRRCTL
UCA0IE
USCI_A receive buffer
USCI_A transmit buffer
USCI_A LIN control
USCI_A IrDA transmit control
USCI_A IrDA receive control
USCI_A interrupt enable
USCI_A interrupt flags
UCA0IFG
USCI_A interrupt vector word
UCA0IV
96
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 6-54. eUSCI_A1 Registers (Base Address:05E0h)
REGISTER DESCRIPTION
REGISTER
UCA1CTLW0
OFFSET
USCI_A control word 0
USCI _A control word 1
USCI_A baud rate 0
USCI_A baud rate 1
USCI_A modulation control
USCI_A status
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
UCA1CTLW1
UCA1BR0
UCA1BR1
UCA1MCTLW
UCA1STAT
UCA1RXBUF
UCA1TXBUF
UCA1ABCTL
UCA1IRTCTL
UCA1IRRCTL
UCA1IE
USCI_A receive buffer
USCI_A transmit buffer
USCI_A LIN control
USCI_A IrDA transmit control
USCI_A IrDA receive control
USCI_A interrupt enable
USCI_A interrupt flags
UCA1IFG
USCI_A interrupt vector word
UCA1IV
Table 6-55. eUSCI_A2 Registers (Base Address:0600h)
REGISTER DESCRIPTION
REGISTER
UCA2CTLW0
OFFSET
USCI_A control word 0
USCI _A control word 1
USCI_A baud rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
UCA2CTLW1
UCA2BR0
USCI_A baud rate 1
UCA2BR1
USCI_A modulation control
USCI_A status
UCA2MCTLW
UCA2STAT
UCA2RXBUF
UCA2TXBUF
UCA2ABCTL
UCA2IRTCTL
UCA2IRRCTL
UCA2IE
USCI_A receive buffer
USCI_A transmit buffer
USCI_A LIN control
USCI_A IrDA transmit control
USCI_A IrDA receive control
USCI_A interrupt enable
USCI_A interrupt flags
USCI_A interrupt vector word
UCA2IFG
UCA2IV
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 6-56. eUSCI_A3 Registers (Base Address: 0620h)
REGISTER DESCRIPTION
REGISTER
UCA3CTLW0
OFFSET
USCI_A control word 0
USCI _A control word 1
USCI_A baud rate 0
USCI_A baud rate 1
USCI_A modulation control
USCI_A status
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
UCA3CTLW1
UCA3BR0
UCA3BR1
UCA3MCTLW
UCA3STAT
UCA3RXBUF
UCA3TXBUF
UCA3ABCTL
UCA3IRTCTL
UCA3IRRCTL
UCA3IE
USCI_A receive buffer
USCI_A transmit buffer
USCI_A LIN control
USCI_A IrDA transmit control
USCI_A IrDA receive control
USCI_A interrupt enable
USCI_A interrupt flags
UCA3IFG
USCI_A interrupt vector word
UCA3IV
Table 6-57. eUSCI_B0 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
UCB0CTLW0
OFFSET
USCI_B control word 0
USCI_B control word 1
USCI_B bit rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Ah
2Ch
2Eh
UCB0CTLW1
UCB0BR0
USCI_B bit rate 1
UCB0BR1
USCI_B status word
UCB0STATW
UCB0TBCNT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA0
UCB0I2COA1
UCB0I2COA2
UCB0I2COA3
UCB0ADDRX
UCB0ADDMASK
UCB0I2CSA
UCB0IE
USCI_B byte counter threshold
USCI_B receive buffer
USCI_B transmit buffer
USCI_B I2C own address 0
USCI_B I2C own address 1
USCI_B I2C own address 2
USCI_B I2C own address 3
USCI_B received address
USCI_B address mask
USCI I2C slave address
USCI interrupt enable
USCI interrupt flags
UCB0IFG
USCI interrupt vector word
UCB0IV
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 6-58. eUSCI_B1 Registers (Base Address: 0680h)
REGISTER DESCRIPTION
REGISTER
UCB1CTLW0
OFFSET
USCI_B control word 0
USCI_B control word 1
USCI_B bit rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Ah
2Ch
2Eh
UCB1CTLW1
UCB1BR0
USCI_B bit rate 1
UCB1BR1
USCI_B status word
UCB1STATW
UCB1TBCNT
UCB1RXBUF
UCB1TXBUF
UCB1I2COA0
UCB1I2COA1
UCB1I2COA2
UCB1I2COA3
UCB1ADDRX
UCB1ADDMASK
UCB1I2CSA
UCB1IE
USCI_B byte counter threshold
USCI_B receive buffer
USCI_B transmit buffer
USCI_B I2C own address 0
USCI_B I2C own address 1
USCI_B I2C own address 2
USCI_B I2C own address 3
USCI_B received address
USCI_B address mask
USCI I2C slave address
USCI interrupt enable
USCI interrupt flags
UCB1IFG
USCI interrupt vector word
UCB1IV
Table 6-59. ADC10_A Registers (Base Address: 0740h)
REGISTER DESCRIPTION
REGISTER
ADC10CTL0
OFFSET
ADC10_A control 0
00h
02h
04h
06h
08h
0Ah
12h
1Ah
1Ch
1Eh
ADC10_A control 1
ADC10CTL1
ADC10CTL2
ADC10LO
ADC10_A control 2
ADC10_A window comparator low threshold
ADC10_A window comparator high threshold
ADC10_A memory control 0
ADC10_A conversion memory
ADC10_A interrupt enable
ADC10_A interrupt flags
ADC10HI
ADC10MCTL0
ADC10MCTL0
ADC10IE
ADC10IGH
ADC10IV
ADC10_A interrupt vector word
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
Table 6-60. SD24_B Registers (Base Address: 0800h)
REGISTER DESCRIPTION
REGISTER
SD24BCTL0
OFFSET
SD24_B control 0
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
36h
38h
3Ah
3Ch
3Eh
40h
42h
44h
46h
50h
52h
54h
56h
58h
5Ah
5Ch
5Eh
60h
62h
64h
SD24_B control 1
SD24BCTL1
SD24_B trigger control
SD24_B trigger OSR control
SD24_B trigger preload
SD24_B interrupt flag
SD24_B interrupt enable
SD24_B interrupt vector
SD24_B converter 0 control
SD24BTRGCTL
SD24BTRGOSR
SD24BTRGPRE
SD24BIFG
SD24BIE
SD24BIV
SD24BCCTL0
SD24BINCTL0
SD24BOSR0
SD24BPRE0
SD24BCCTL1
SD24BINCTL1
SD24BOSR1
SD24BPRE1
SD24BCCTL2
SD24BINCTL2
SD24BOSR2
SD24BPRE2
SD24BCCTL3
SD24BINCTL3
SD24BOSR3
SD24BPRE3
SD24BCCTL4
SD24BINCTL4
SD24BOSR4
SD24BPRE4
SD24BCCTL5
SD24BINCTL5
SD24BOSR5
SD24BPRE5
SD24BCCTL6
SD24BINCTL6
SD24BOSR6
SD24BPRE6
SD24BMEML0
SD24BMEMH0
SD24BMEML1
SD24BMEMH1
SD24BMEML2
SD24BMEMH2
SD24BMEML3
SD24BMEMH3
SD24BMEML4
SD24BMEMH4
SD24BMEML5
SD24_B converter 0 input control
SD24_B converter 0 OSR control
SD24_B converter 0 preload
SD24_B converter 1 control
SD24_B converter 1 input control
SD24_B converter 1 OSR control
SD24_B converter 1 preload
SD24_B converter 2 control
SD24_B converter 2 input control
SD24_B converter 2 OSR control
SD24_B converter 2 preload
SD24_B converter 3 control
SD24_B converter 3 input control
SD24_B converter 3 OSR control
SD24_B converter 3 preload
SD24_B converter 4 control
SD24_B converter 4 input control
SD24_B converter 4 OSR control
SD24_B converter 4 preload
SD24_B converter 5 control
SD24_B converter 5 Input control
SD24_B converter 5 OSR control
SD24_B converter 5 preload
SD24_B converter 6 control
SD24_B converter 6 Input control
SD24_B converter 6 OSR control
SD24_B converter 6 preload
SD24_B converter 0 conversion memory low word
SD24_B converter 0 conversion memory high word
SD24_B converter 1 conversion memory low word
SD24_B converter 1 conversion memory high word
SD24_B converter 2 conversion memory low word
SD24_B converter 2 conversion memory high word
SD24_B converter 3 conversion memory low word
SD24_B converter 3 conversion memory high word
SD24_B converter 4 conversion memory low word
SD24_B converter 4 conversion memory high word
SD24_B converter 5 conversion memory low word
100
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 6-60. SD24_B Registers (Base Address: 0800h) (continued)
REGISTER DESCRIPTION
REGISTER
SD24BMEMH5
OFFSET
SD24_B converter 5 conversion memory high word
SD24_B converter 6 conversion memory low word
SD24_B converter 6 conversion memory high word
66h
68h
6Ah
SD24BMEML6
SD24BMEMH6
Table 6-61. Comparator_B Register (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
CBCTL0
OFFSET
Comp_B control 0
Comp_B control 1
Comp_B control 2
Comp_B control 3
Comp_B interrupt
00h
02h
04h
06h
0Ch
0Eh
CBCTL1
CBCTL2
CBCTL3
CBINT
Comp_B interrupt vector word
CBIV
Table 6-62. AES Accelerator Registers (Base Address: 09C0h)
REGISTER DESCRIPTION
REGISTER
AESACTL0
OFFSET
AES accelerator control 0
AES accelerator status
AES accelerator key
00h
04h
06h
08h
0Ah
AESASTAT
AESAKEY
AESADIN
AES accelerator data in
AES accelerator data out
AESADOUT
Table 6-63. Auxiliary Supply Registers (Base Address: 09E0h)
REGISTER DESCRIPTION
REGISTER
AUXCTL0
OFFSET
Auxiliary supply control 0
Auxiliary supply control 1
Auxiliary supply control 2
AUX2 charger control
AUX3 charger control
AUX ADC control
00h
02h
04h
12h
14h
16h
1Ah
1Ch
1Eh
AUXCTL1
AUXCTL2
AUX2CHCTL
AUX3CHCTL
AUXADCCTL
AUXIFG
AUX interrupt flag
AUX interrupt enable
AUX interrupt vector word
AUXIE
AUXIV
Copyright © 2014–2018, Texas Instruments Incorporated
Detailed Description
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 6-64. LCD_C Registers (Base Address: 0A00h)
REGISTER DESCRIPTION
REGISTER
LCDCCTL0
OFFSET
LCD_C control 0
000h
002h
004h
006h
008h
00Ah
00Ch
00Eh
012h
01Eh
LCD_C control 1
LCDCCTL1
LCDCBLKCTL
LCDCMEMCTL
LCDCVCTL
LCDCPCTL0
LCDCPCTL1
LCDCPCTL2
LCDCCPCTL
LCDCIV
LCD_C blinking control
LCD_C memory control
LCD_C voltage control
LCD_C port control 0
LCD_C port control 1
LCD_C port control 2
LCD_C charge pump control
LCD_C interrupt vector
Static and 2- to 4-mux modes
LCD_C memory 1
LCD_C memory 2
⋮
LCDM1
LCDM2
⋮
020h
021h
⋮
LCD_C memory 20
LCD_C blinking memory 1
LCD_C blinking memory 2
⋮
LCDM20
LCDBM1
LCDBM2
⋮
033h
040h
041h
⋮
LCD_C blinking memory 20
5- to 8-mux modes
LCD_C memory 1
LCD_C memory 2
⋮
LCDBM20
053h
LCDM1
LCDM2
⋮
020h
021h
⋮
LCD_C memory 40
LCDM40
047h
102
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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6.12 Input/Output Diagrams
6.12.1 Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger (PEU Package Only)
Figure 6-6 shows the port diagram. Table 6-65 summarizes the selection of the pin functions.
A0 to A3
From ADC
P1REN.x
0
DVSS
1
DVCC
P1DIR.x
0
0
0 1
1 0
1 1
P1OUT.x
0
0
From Timer_A,
ACLK, ADC10CLK
0 1
1 0
1 1
DVSS
(MSP430F677xAIPEU only)
P1.0/TA1.1/VeREF-/A0
P1.1/TA2.1/VeREF+/A1
P1.2/ACLK/A2
P1DS.x
P1SEL0.x
P1SEL1.x
P1.3/ADC10CLK/A3
P1IN.x
EN
To Timer_A
P1IE.x
D
Bus
Keeper
P1IRQ.x
P1IFG.x
Q
EN
SET
Interrupt
Edge
Select
P1SEL.x
P1IES.x
Figure 6-6. Port P1 (P1.0 to P1.3) Diagram (PEU Package Only)
Copyright © 2014–2018, Texas Instruments Incorporated
Detailed Description
103
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 6-65. Port P1 (P1.0 to P1.3) Pin Functions (PEU Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.0 (I/O)
TA1.CCI1A
TA1.1
I:0; O:1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
1
1
1
0
0
1
1
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
P1.0/TA1.1/VeREF-/A0
0
N/A
0
DVSS
1
VeREF-/A0
P1.1 (I/O)
TA2.CCI1A
TA2.1
X
I:0; O:1
0
1
P1.1/TA2.1/VeREF+/A1
1
N/A
0
DVSS
1
VeREF+/A1
P1.2 (I/O)
ACLK
X
I:0; O:1
1
P1.2/ACLK/A2
2
3
N/A
0
DVSS
1
A2
X
P1.3 (I/O)
ADC10CLK
N/A
I:0; O:1
1
0
1
X
P1.3/ADC10CLK/A3
(1) X = don't care
DVSS
A3
104
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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6.12.2 Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger (PZ Package Only)
Figure 6-7 shows the port diagram. Table 6-66 summarizes the selection of the pin functions.
A0 to A3
From ADC
P1REN.x
0
DVSS
1
DVCC
P1DIR.x
0
0
0 1
1 0
1 1
P1OUT.x
0
0
From Comparator_B
0 1
1 0
1 1
From Timer_A,
ACLK, ADC10CLK
DVSS
(MSP430F677xAIPZ only)
P1.0/TA1.1/VeREF-/A0
P1.1/TA2.1/CBOUT/VeREF+/A1
P1.2/ACLK/A2
P1DS.x
P1SEL0.x
P1SEL1.x
P1.3/ADC10CLK/A3
P1IN.x
EN
To Timer_A
P1IE.x
D
Bus
Keeper
P1IRQ.x
P1IFG.x
Q
EN
SET
Interrupt
Edge
Select
P1SEL.x
P1IES.x
Figure 6-7. Port P1 (P1.0 to P1.3) Diagram (PZ Package Only)
Copyright © 2014–2018, Texas Instruments Incorporated
Detailed Description
105
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 6-66. Port P1 (P1.0 to P1.3) Pin Functions (PZ Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.0 (I/O)
TA1.CCI1A
TA1.1
I:0; O:1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
1
1
1
0
0
1
1
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
P1.0/TA1.1/VeREF-/A0
0
N/A
0
DVSS
1
VeREF-/A0
P1.1 (I/O)
TA2.CCI1A
TA2.1
X
I:0; O:1
0
1
P1.1/TA2.1/CBOUT/VeREF+/A1
1
N/A
0
CBOUT
VeREF+/A1
P1.2 (I/O)
ACLK
1
X
I:0; O:1
1
P1.2/ACLK/A2
2
3
N/A
0
DVSS
1
A2
X
P1.3 (I/O)
ADC10CLK
N/A
I:0; O:1
1
0
1
X
P1.3/ADC10CLK/A3
(1) X = don't care
DVSS
A3
106
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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6.12.3 Port P1 (P1.4 and P1.5) Input/Output With Schmitt Trigger
Figure 6-8 shows the port diagram. Table 6-67 summarizes the selection of the pin functions.
To Comparator_B
From Comparator_B
CBPD.z
A0 to A3
From ADC
P1REN.x
0
DVSS
1
DVCC
P1DIR.x
0
0
0 1
1 0
1 1
P1OUT.x
0
0
0 1
1 0
1 1
From MCLK, SMCLK
DVSS
P1.4/MCLK/CB1/A4
P1.5/SMCLK/CB0/A5
P1DS.x
P1SEL0.x
P1SEL1.x
P1IN.x
EN
Not used
P1IE.x
D
Bus
Keeper
P1IRQ.x
P1IFG.x
Q
EN
SET
Interrupt
Edge
Select
P1SEL.x
P1IES.x
Figure 6-8. Port P1 (P1.4 and P1.5) Diagram
Copyright © 2014–2018, Texas Instruments Incorporated
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 6-67. Port P1 (P1.4 and P1.5) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
CPBD.z
P1.4 (I/O)
MCLK
N/A
I:0; O:1
0
0
1
1
1
X
0
0
1
1
1
X
0
1
0
0
1
X
0
1
0
0
1
X
0
1
0
0
0
P1.4/MCLK/CB1/A4
4
DVSS
A4
1
0
X
0
CB1
X
1 (z = 1)
P1.5 (I/O)
SMCLK
N/A
I:0; O:1
0
1
0
1
X
X
0
0
P1.5/SMCLK/CB0/A5
(1) X = don't care
5
DVSS
A5
0
0
CB0
1 (z = 0)
108
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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6.12.4 Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
Figure 6-9 shows the port diagram. Table 6-68 summarizes the selection of the pin functions.
COM2 to COM3
From LCD_C
P1REN.x
0
DVSS
1
DVCC
P1DIR.x
0
0
0 1
1 0
1 1
P1OUT.x
DVSS
0
0
0 1
1 0
1 1
P1.6/COM2
P1.7/COM3
P1DS.x
P1SEL0.x
P1SEL1.x
P1IN.x
EN
Not used
P1IE.x
D
Bus
Keeper
P1IRQ.x
P1IFG.x
Q
EN
SET
Interrupt
Edge
Select
P1SEL.x
P1IES.x
Figure 6-9. Port P1 (P1.6 and P1.7) Diagram
Copyright © 2014–2018, Texas Instruments Incorporated
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 6-68. Port P1 (P1.6 and P1.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
COM Enable
P1.6 (I/O)
N/A
I:0; O:1
X
X
X
X
X
X
X
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
P1.6/COM2
6
DVSS
COM2
P1.7 (I/O)
N/A
1
X
I:0; O:1
0
1
X
P1.7/COM3
7
DVSS
COM3
(1) X = don't care
110
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.5 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger (PEU Package Only)
Figure 6-10 shows the port diagram. Table 6-69 summarizes the selection of the pin functions.
P2REN.x
P2MAP.x = PMAP_ANALOG
0
1
DVSS
DVCC
0
1
P2DIR.x
From Port Mapping
0
1
P2OUT.x
From Port Mapping
(MSP430F677xAIPEU only)
P2.0/PM_TA0.0
P2.1/PM_TA0.1
P2.2/PM_TA0.2
P2.3/PM_TA1.0
P2.4/PM_TA2.0
P2DS.x
P2SEL0.x
P2IN.x
P2.5/PM_UCB0SOMI/PM_UCB0SCL
P2.6/PM_UCB0SIMO/PM_UCB0SDA
P2.7/PM_UCB0CLK
EN
To Port Mapping
P2IE.x
D
Bus
Keeper
P2IRQ.x
P2IFG.x
Q
EN
SET
P2SEL.x
P2IES.x
Interrupt
Edge
Select
Figure 6-10. Port P2 (P2.0 to P2.7) Diagram (PEU Package Only)
Copyright © 2014–2018, Texas Instruments Incorporated
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
Table 6-69. Port P2 (P2.0 to P2.7) Pin Functions (PEU Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL0.x
P2MAP.x
X
P2.0 (I/O)
I:0; O:1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
P2.0/PM_TA0.0
0
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
P2.1 (I/O)
X
≤ 30
= 31
X
X
I:0; O:1
P2.1/PM_TA0.1
P2.2/PM_TA0.2
P2.3/PM_TA1.0
P2.4/PM_TA2.0
1
2
3
4
5
6
7
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
P2.2 (I/O)
X
≤ 30
= 31
X
X
I:0; O:1
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
P2.3 (I/O)
X
≤ 30
= 31
X
X
I:0; O:1
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
P2.4 (I/O)
X
≤ 30
= 31
X
X
I:0; O:1
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
P2.5 (I/O)
X
≤ 30
= 31
X
X
I:0; O:1
P2.5/PM_UCB0SOMI/
PM_UCB0SCL
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
P2.6 (I/O)
X
≤ 30
= 31
X
X
I:0; O:1
P2.6/PM_UCB0SIMO/
PM_UCB0SDA
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
P2.7 (I/O)
X
≤ 30
= 31
X
X
I:0; O:1
P2.7/PM_UCB0CLK
(1) X = don't care
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
X
X
≤ 30
= 31
112
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.6 Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger (PZ Package Only)
Figure 6-11 shows the port diagram. Table 6-70 summarizes the selection of the pin functions.
COM4 to COM7
From LCD_C
P2REN.x
0
1
P2MAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
P2DIR.x
From Port Mapping
0
1
P2OUT.x
From Port Mapping
(MSP430F677xAIPZ only)
P2.0/PM_TA0.0/COM4
P2.1/PM_TA0.1/COM5
P2.2/PM_TA0.2/COM6
P2.3/PM_TA1.0/COM7
P2DS.x
P2SEL0.x
P2IN.x
EN
To Port Mapping
P2IE.x
D
Bus
Keeper
P2IRQ.x
Q
EN
P2IFG.x
SET
Interrupt
Edge
Select
P2SEL.x
P2IES.x
Figure 6-11. Port P2 (P2.0 to P2.3) Diagram (PZ Package Only)
Copyright © 2014–2018, Texas Instruments Incorporated
Detailed Description
113
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
Table 6-70. Port P2 (P2.0 to P2.3) Pin Functions (PZ Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
COM
Enable
P2DIR.x
P2SEL0.x
P2MAP.x
P2.0 (I/O)
I:0; O:1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
X
≤ 30
= 31
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
Mapped secondary digital function
X
P2.0/PM_TA0.0/ COM4
0
Output driver and input Schmitt trigger disabled
X
COM4
X
P2.1 (I/O)
I:0; O:1
X
Mapped secondary digital function
X
≤ 30
= 31
X
P2.1/PM_TA0.1/ COM5
P2.2/PM_TA0.2/ COM6
1
2
3
Output driver and input Schmitt trigger disabled
X
COM5
X
P2.2 (I/O)
I:0; O:1
X
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
COM6
X
≤ 30
= 31
X
X
X
P2.3 (I/O)
I:0; O:1
X
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
COM7
X
X
X
≤ 30
= 31
X
P2.3/PM_TA1.0/ COM7
(1) X = don't care
114
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.7 Port P2 (P2.4 to P2.6) Input/Output With Schmitt Trigger (PZ Package Only)
Figure 6-12 shows the port diagram. Table 6-71 summarizes the selection of the pin functions.
P2REN.x
P2MAP.x = PMAP_ANALOG
0
1
DVSS
DVCC
0
1
P2DIR.x
From Port Mapping
0
1
P2OUT.x
From Port Mapping
(MSP430F677xAIPZ only)
P2.4/PM_TA2.0
P2.5/PM_UCB0SOMI/PM_UCB0SCL
P2.6/PM_UCB0SIMO/PM_UCB0SDA
P2DS.x
P2SEL0.x
P2IN.x
EN
To Port Mapping
P2IE.x
D
Bus
Keeper
P2IRQ.x
Q
EN
P2IFG.x
SET
P2SEL.x
P2IES.x
Interrupt
Edge
Select
Figure 6-12. Port P2 (P2.4 to P2.6) Diagram (PZ Package Only)
Table 6-71. Port P2 (P2.4 to P2.6) Pin Functions (PZ Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL0.x
P2MAP.x
P2.4 (I/O)
I:0; O:1
0
1
1
0
1
1
0
1
1
X
P2.4/PM_TA2.0/R23
4
Mapped secondary digital function
X
≤ 30
= 31
X
R23
X
P2.5 (I/O)
I:0; O:1
P2.5/PM_UCB0SOMI/
PM_UCB0SCL/R13
5
6
Mapped secondary digital function
X
≤ 30
= 31
X
R13
X
P2.6 (I/O)
I:0; O:1
P2.6/PM_UCB0SIMO/
PM_UCB0SDA/R03
Mapped secondary digital function
R03
X
X
≤ 30
= 31
(1) X = don't care
Copyright © 2014–2018, Texas Instruments Incorporated
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.8 Port P2 (P2.7) Input/Output With Schmitt Trigger (PZ Package Only)
Figure 6-13 shows the port diagram. Table 6-72 summarizes the selection of the pin functions.
Comparator_B
CBPD.z
P2REN.x
0
1
P2MAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
P2DIR.x
From Port Mapping
0
1
P2OUT.x
From Port Mapping
(MSP430F677xAIPZ only)
P2.7/PM_UCB0CLK/CB2
P2DS.x
P2SEL0.x
P2IN.x
EN
To Port Mapping
P2IE.x
D
Bus
Keeper
P2IRQ.x
P2IFG.x
Q
EN
SET
Interrupt
Edge
Select
P2SEL.x
P2IES.x
Figure 6-13. Port P2 (P2.7) Diagram (PZ Package Only)
Table 6-72. Port P2 (P2.7) Pin Functions (PZ Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL0.x
P2MAP.x
CBPD.z
P2.7 (I/O)
I:0; O:1
0
1
1
X
X
0
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
CB2
X
X
X
≤ 30
= 31
X
0
0
P2.7/PM_UCB0CLK/
CB2
7
1 (z = 2)
(1) X = don't care
116
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.9 Ports P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger (PEU Package Only)
Figure 6-14 shows the port diagram. Table 6-73 summarizes the selection of the pin functions.
P3REN.x
P3MAP.x = PMAP_ANALOG
0
1
DVSS
DVCC
0
1
P3DIR.x
From Port Mapping
0
1
P3OUT.x
From Port Mapping
(MSP430F677xAIPEU only)
P3DS.x
P3SEL0.x
P3IN.x
P3.0/PM_UCA0RXD/PM_UCA0SOMI
P3.1/PM_UCA0TXD/PM_UCA0SIMO
P3.2/PM_UCA0CLK
P3.3/PM_UCA1CLK
P3.4/PM_UCA1RXD/PM_UCA1SOMI
P3.5/PM_UCA1TXD/PM_UCA1SIMO
P3.6/PM_UCA2RXD/PM_UCA2SOMI
P3.7/PM_UCA2TXD/PM_UCA2SIMO
EN
To Port Mapping
D
Bus
Keeper
Figure 6-14. Ports P3 (P3.0 to P3.7) Diagram (PEU Package Only)
Copyright © 2014–2018, Texas Instruments Incorporated
Detailed Description
117
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
Table 6-73. Ports P3 (P3.0 to P3.7) Pin Functions (PEU Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x
P3SEL0.x
P3MAP.x
X
P3.0 (I/O)
I:0; O:1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
P3.0/PM_UCA0RXD/
PM_UCA0SOMI
0
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
P3.1 (I/O)
X
≤ 30
= 31
X
X
I:0; O:1
P3.1/PM_UCA0TXD/
PM_UCA0SIMO
1
2
3
4
5
6
7
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
P3.2 (I/O)
X
≤ 30
= 31
X
X
I:0; O:1
P3.2/PM_UCA0CLK
P3.3/PM_UCA1CLK
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
P3.3 (I/O)
X
≤ 30
= 31
X
X
I:0; O:1
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
P3.4 (I/O)
X
≤ 30
= 31
X
X
I:0; O:1
P3.4/PM_UCA1RXD/
PM_UCA1SOMI
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
P3.5 (I/O)
X
≤ 30
= 31
X
X
I:0; O:1
P3.5/PM_UCA1TXD/
PM_UCA1SIMO
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
P3.6 (I/O)
X
≤ 30
= 31
X
X
I:0; O:1
P3.6/PM_UCA2RXD/
PM_UCA2SOMI
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
P3.7 (I/O)
X
≤ 30
= 31
X
X
I:0; O:1
P3.7/PM_UCA2TXD/
PM_UCA2SIMO
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
X
X
≤ 30
= 31
(1) X = don't care
118
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.10 Ports P3 (P3.0) Input/Output With Schmitt Trigger (PZ Package Only)
Figure 6-15 shows the port diagram. Table 6-74 summarizes the selection of the pin functions.
P3REN.x
P3MAP.x = PMAP_ANALOG
0
1
DVSS
DVCC
0
1
P3DIR.x
From Port Mapping
0
1
P3OUT.x
From Port Mapping
(MSP430F677xAIPZ only)
P3.0/PM_UCA0RXD/PM_UCA0SOMI
P3DS.x
P3SEL0.x
P3IN.x
EN
D
To Port Mapping
Bus
Keeper
Figure 6-15. Ports P3 (P3.0) Diagram (PZ Package Only)
Table 6-74. Ports P3 (P3.0) Pin Functions (PZ Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x
P3SEL0.x
P3MAP.x
X
P3.0 (I/O)
I:0; O:1
0
1
1
P3.0/PM_UCA0RXD/
PM_UCA0SOMI
0
Mapped secondary digital function
X
X
≤ 30
Output driver and input Schmitt trigger disabled
= 31
(1) X = don't care
Copyright © 2014–2018, Texas Instruments Incorporated
Detailed Description
119
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Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.11 Ports P3 (P3.1 to P3.7) Input/Output With Schmitt Trigger (PZ Package Only)
Figure 6-16 shows the port diagram. Table 6-75 summarizes the selection of the pin functions.
S39 to S33
LCDS39 to LCDS33
P3REN.x
0
1
P3MAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
P3DIR.x
From Port Mapping
0
1
P3OUT.x
From Port Mapping
(MSP430F677xAIPZ only)
P3DS.x
P3SEL0.x
P3IN.x
P3.1/PM_UCA0TXD/PM_UCA0SIMO/S39
P3.2/PM_UCA0CLK/S38
P3.3/PM_UCA1CLK/S37
P3.4/PM_UCA1RXD/PM_UCA1SOMI/S36
P3.5/PM_UCA1TXD/PM_UCA1SIMO/S35
P3.6/PM_UCA2RXD/PM_UCA2SOMI/S34
P3.7/PM_UCA2TXD/PM_UCA2SIMO/S33
EN
D
To Port Mapping
Bus
Keeper
Figure 6-16. Ports P3 (P3.1 to P3.7) Diagram (PZ Package Only)
120
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
Table 6-75. Ports P3 (P3.1 to P3.7) Pin Functions (PZ Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P3.x)
x
FUNCTION
LCDS39 to
LCDS33
P3DIR.x
P3SEL0.x
P3MAP.x
P3.1 (I/O)
I:0; O:1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
X
≤ 30
= 31
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
Mapped secondary digital function
X
P3.1/PM_UCA0TXD/
PM_UCA0SIMO/S39
1
Output driver and input Schmitt trigger disabled
X
S39
X
P3.2 (I/O)
I:0; O:1
X
Mapped secondary digital function
X
≤ 30
= 31
X
P3.2/PM_UCA0CLK/
S38
2
3
4
5
6
7
Output driver and input Schmitt trigger disabled
X
S38
X
P3.3 (I/O)
I:0; O:1
X
Mapped secondary digital function
X
≤ 30
= 31
X
P3.3/PM_UCA1CLK/
S37
Output driver and input Schmitt trigger disabled
X
S37
X
P3.4 (I/O)
I:0; O:1
X
Mapped secondary digital function
X
≤ 30
= 31
X
P3.4/PM_UCA1RXD/
PM_UCA1SOMI/S36
Output driver and input Schmitt trigger disabled
X
S36
X
P3.5 (I/O)
I:0; O:1
X
Mapped secondary digital function
X
≤ 30
= 31
X
P3.5/PM_UCA1TXD/
PM_UCA1SIMO/S35
Output driver and input Schmitt trigger disabled
X
S35
X
P3.6 (I/O)
I:0; O:1
X
Mapped secondary digital function
X
≤ 30
= 31
X
P3.6/PM_UCA2RXD/
PM_UCA2SOMI/S34
Output driver and input Schmitt trigger disabled
X
S34
X
P3.7 (I/O)
I:0; O:1
X
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
S33
X
X
X
≤ 30
= 31
X
P3.7/PM_UCA2TXD/
PM_UCA2SIMO/S33
(1) X = don't care
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Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.12 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger (PEU Package Only)
Figure 6-17 shows the port diagram. Table 6-76 summarizes the selection of the pin functions.
P4REN.x
P4MAP.x = PMAP_ANALOG
0
1
DVSS
DVCC
0
1
P4DIR.x
From Port Mapping
0
1
P4OUT.x
From Port Mapping
(MSP430F677xAIPEU only)
P4.0/PM_UCA2CLK
P4.1/PM_UCA3RXD/PM_UCA3SOMI
P4.2/PM_UCA3TXD/PM_UCA3SIMO
P4.3/PM_UCA3CLK
P4.4/PM_UCB1SOMI/PM_UCB1SCL
P4.5/PM_UCB1SIMO/PM_UCB1SDA
P4.6/PM_UCB1CLK
P4DS.x
P4SEL0.x
P4IN.x
P4.7/PM_TA3.0
EN
D
To Port Mapping
Bus
Keeper
Figure 6-17. Port P4 (P4.0 to P4.7) Diagram (PEU Package Only)
122
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
Table 6-76. Port P4 (P4.0 to P4.7) Pin Functions (PEU Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x
P4SEL0.x
P4MAP.x
X
P4.0 (I/O)
I:0; O:1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
P4.0/PM_UCA2CLK
0
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
P4.1 (I/O)
X
≤ 30
= 31
X
X
I:0; O:1
P4.1/PM_UCA3RXD/
PM_UCA3SOMI
1
2
3
4
5
6
7
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
P4.2 (I/O)
X
≤ 30
= 31
X
X
I:0; O:1
P4.2/PM_UCA3TXD/
PM_UCA3SIMO
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
P4.3 (I/O)
X
≤ 30
= 31
X
X
I:0; O:1
P4.3/PM_UCA3CLK
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
P4.4 (I/O)
X
≤ 30
= 31
X
X
I:0; O:1
P4.4/PM_UCB1SOMI/
PM_UCB1SCL
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
P4.5 (I/O)
X
≤ 30
= 31
X
X
I:0; O:1
P4.5/PM_UCB1SIMO/
PM_UCB1SDA
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
P4.6 (I/O)
X
≤ 30
= 31
X
X
I:0; O:1
P4.6/PM_UCB1CLK
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
P4.7 (I/O)
X
≤ 30
= 31
X
X
I:0; O:1
P4.7/PM_TA3.0
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
X
X
≤ 30
= 31
(1) X = don't care
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Detailed Description
123
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.13 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger (PZ Package Only)
Figure 6-18 shows the port diagram. Table 6-77 summarizes the selection of the pin functions.
S32 to S25
LCDS32 to LCDS25
P4REN.x
0
1
P4MAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
P4DIR.x
From Port Mapping
0
1
P4OUT.x
From Port Mapping
(MSP430F677xAIPZ only)
P4.0/PM_UCA2CLK/S32
P4.1/PM_UCA3RXD/PM_UCA3SOMI/S31
P4.2/PM_UCA3TXD/PM_UCA3SIMO/S30
P4.3/PM_UCA3CLK/S29
P4.4/PM_UCB1SOMI/PM_UCB1SCL/S28
P4.5/PM_UCB1SIMO/PM_UCB1SDA/S27
P4.6/PM_UCB1CLK/S26
P4DS.x
P4SEL0.x
P4IN.x
P4.7/PM_TA3.0/S25
EN
D
To Port Mapping
Bus
Keeper
Figure 6-18. Port P4 (P4.0 to P4.7) Diagram (PZ Package Only)
124
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
Table 6-77. Port P4 (P4.0 to P4.7) Pin Functions (PZ Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P4.x)
x
FUNCTION
LCD32 to
LCDS25
P4DIR.x
P4SEL0.x
P4MAP.x
P4.0 (I/O)
I:0; O:1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
X
≤ 30
= 31
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
Mapped secondary digital function
X
P4.0/PM_UCA2CLK/
S32
0
Output driver and input Schmitt trigger disabled
X
S32
X
P4.1 (I/O)
I:0; O:1
X
Mapped secondary digital function
X
≤ 30
= 31
X
P4.1/PM_UCA3RXD/
PM_UCA3SOMI/S31
1
2
3
4
5
6
7
Output driver and input Schmitt trigger disabled
X
S31
X
P4.2 (I/O)
I:0; O:1
X
Mapped secondary digital function
X
≤ 30
= 31
X
P4.2/PM_UCA3TXD/
PM_UCA3SIMO/S30
Output driver and input Schmitt trigger disabled
X
S30
X
P4.3 (I/O)
I:0; O:1
X
Mapped secondary digital function
X
≤ 30
= 31
X
P4.3/PM_UCA3CLK/
S29
Output driver and input Schmitt trigger disabled
X
S29
X
P4.4 (I/O)
I:0; O:1
X
Mapped secondary digital function
X
≤ 30
= 31
X
P4.4/ PM_UCB1SOMI/
PM_UCB1SCL/S28
Output driver and input Schmitt trigger disabled
X
S28
X
P4.5 (I/O)
I:0; O:1
X
Mapped secondary digital function
X
≤ 30
= 31
X
P4.5/ PM_UCB1SIMO/
PM_UCB1SDA/S27
Output driver and input Schmitt trigger disabled
X
S27
X
P4.6 (I/O)
I:0; O:1
X
Mapped secondary digital function
X
≤ 30
= 31
X
P4.6/PM_UCB1CLK/
S26
Output driver and input Schmitt trigger disabled
X
S26
X
P4.7 (I/O)
I:0; O:1
X
Mapped secondary digital function
Output driver and input Schmitt trigger disabled
S25
X
X
X
≤ 30
= 31
X
P4.7/PM_TA3.0/S25
(1) X = don't care
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Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.14 Port P5 (P5.0 to P5.3) Input/Output With Schmitt Trigger (PEU Package Only)
Figure 6-19 shows the port diagram. Table 6-78 summarizes the selection of the pin functions.
COM4 to COM7
From LCD_C
P5REN.x
0
DVSS
1
DVCC
P5DIR.x
0
0
0 1
1 0
1 1
P5OUT.x
DVSS
0
0
0 1
1 0
1 1
(MSP430F677xAIPEU only)
P5.0/COM4
P5.1/COM5
P5DS.x
P5SEL0.x
P5SEL1.x
P5.2/COM6
P5.3/COM7
P5IN.x
EN
D
Not used
Bus
Keeper
Figure 6-19. Port P5 (P5.0 to P5.3) Diagram (PEU Package Only)
126
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
Table 6-78. Port P5 (P5.0 to P5.3) Pin Functions (PEU Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL1.x
P5SEL0.x
COM Enable
P5.0 (I/O)
N/A
I:0; O:1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
P5.0/COM4
P5.1/COM5
P5.2/COM6
0
DVSS
COM4
P5.1 (I/O)
N/A
1
X
I:0; O:1
0
1
2
3
DVSS
COM5
P5.2 (I/O)
N/A
1
X
I:0; O:1
0
DVSS
COM6
P5.3 (I/O)
N/A
1
X
I:0; O:1
0
1
X
P5.3/COM7
DVSS
COM7
(1) X = don't care
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Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.15 Port P5 (P5.4 to P5.6) Input/Output With Schmitt Trigger (PEU Package Only)
Figure 6-20 shows the port diagram. Table 6-79 summarizes the selection of the pin functions.
R23, R13, R03, LCDREF
P5REN.x
0
DVSS
1
DVCC
P5DIR.x
0
0
0 1
1 0
1 1
From SD24_B
P5OUT.x
0
0
0 1
1 0
1 1
From SD24_B
DVSS
(MSP430F677xAIPEU only)
P5.4/SDCLK/R23
P5.5/SD0DIO/LCDREF/R13
P5.6/SD1DIO/R03
P5DS.x
P5SEL0.x
P5SEL1.x
P5IN.x
EN
D
To SD24_B
Bus
Keeper
Figure 6-20. Port P5 (P5.4 to P5.6) Diagram (PEU Package Only)
128
Detailed Description
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Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
Table 6-79. Port P5 (P5.4 to P5.6) Pin Functions (PEU Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL1.x
P5SEL0.x
P5.4 (I/O)
I:0; O:1
0
0
1
1
1
0
0
1
1
1
0
0
1
1
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
Secondary digital function
X
P5.4/SDCLK/R23
4
N/A
0
DVSS
1
R23
X
P5.5 (I/O)
I:0; O:1
Secondary digital function
X
P5.5/SD0DIO/LCDREF/R13
5
6
N/A
0
DVSS
1
LCDREF/R13
X
P5.6 (I/O)
I:0; O:1
Secondary digital function
X
0
1
X
PT.6/SD1DIO/R03
N/A
DVSS
R03
(1) X = don't care
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.16 Port P5 (P5.7) Input/Output With Schmitt Trigger (PEU Package Only)
Figure 6-21 shows the port diagram. Table 6-80 summarizes the selection of the pin functions.
To Comparator_B
CBPD.z
P5REN.x
0
DVSS
1
DVCC
P5DIR.x
0
0
0 1
1 0
1 1
From SD24_B
P5OUT.x
0
0
0 1
1 0
1 1
From SD24_B
(MSP430F677xAIPEU only)
P5.7/SD2DIO/CB2
P5DS.x
P5SEL0.x
P5SEL1.x
P5IN.x
EN
D
To SD24_B
Bus
Keeper
Figure 6-21. Port P5 (P5.7) Diagram (PEU Package Only)
Table 6-80. Port P5 (P5.7) Pin Function (PEU Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL1.x
P5SEL0.x
CBPD.z
P5.7 (I/O)
I:0; O:1
X
X
X
0
1
0
0
P5.7/SD2DIO/CB2
7
Secondary digital function
CB2
X
X
X
1 (z = 2)
(1) X = don't care
130
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.17 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger (PZ Package Only)
Figure 6-22 shows the port diagram. Table 6-81 summarizes the selection of the pin functions.
S24 to S17
LCDS24 to LCDS17
P5REN.x
0
DVSS
1
DVCC
P5DIR.x
0
0
0 1
1 0
1 1
From SD24_B
P5OUT.x
0
0
0 1
1 0
1 1
From SD24_B
(MSP430F677xAIPZ only)
P5.0/SDCLK/S24
P5.1/SD0DIO/S23
P5.2/SD1DIO/S22
P5.3/SD2DIO/S21
P5.4/SD3DIO/S20
P5.5/SD4DIO/S19
P5.6/SD5DIO/S18
P5.7/SD6DIO/S17
P5DS.x
P5SEL0.x
P5SEL1.x
P5IN.x
EN
D
To SD24_B
Bus
Keeper
Figure 6-22. Port P5 (P5.0 to P5.7) Diagram (PZ Package Only)
Copyright © 2014–2018, Texas Instruments Incorporated
Detailed Description
131
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
Table 6-81. Port P5 (P5.0 to P5.7) Pin Function (PZ Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
LCDS24 to
LCDS17
P5DIR.x
P5SEL1.x
P5SEL0.x
P5.0 (I/O)
I:0; O:1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
P5.0/SDCLK/S24
0
Secondary digital function
X
S24
X
P5.1 (I/O)
I:0; O:1
P5.1/SD0DIO/S23
P5.2/SD1DIO/S22
P5.3/SD2DIO/S21
P5.4/SD3DIO/S20
P5.5/SD4DIO/S19
P5.6/SD5DIO/S18
1
2
3
4
5
6
7
Secondary digital function
X
S23
X
P5.2 (I/O)
I:0; O:1
Secondary digital function
X
S22
X
P5.3 (I/O)
I:0; O:1
Secondary digital function
X
S21
X
P5.4 (I/O)
I:0; O:1
Secondary digital function
X
S20
X
P5.5 (I/O)
I:0; O:1
Secondary digital function
X
S19
X
P5.6 (I/O)
I:0; O:1
Secondary digital function
X
S18
X
P5.7 (I/O)
I:0; O:1
P5.7/SD6DIO/S17
Secondary digital function
S17
X
X
(1) X = don't care
132
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.18 Port P6 (P6.0) Input/Output With Schmitt Trigger (PEU Package Only)
Figure 6-23 shows the port diagram. Table 6-82 summarizes the selection of the pin functions.
P6REN.x
0
DVSS
1
DVCC
0
1
P6DIR.x
From SD24_B
0
1
P6OUT.x
From SD24_B
(MSP430F677xAIPEU only)
P6.0/SD3DIO
P6DS.x
P6SEL0.x
P6IN.x
EN
To SD24_B
D
Bus
Keeper
Figure 6-23. Port P6 (P6.0) Diagram (PEU Package Only)
Table 6-82. Port P6 (P6.0) Pin Functions (PEU Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P6.x)
x
FUNCTION
P6DIR.x
I:0; O:1
X
P6SEL0.x
P6.0 (I/O)
0
1
P6.0/SD3DIO
0
Secondary digital function
(1) X = don't care
Copyright © 2014–2018, Texas Instruments Incorporated
Detailed Description
133
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.19 Port P6 (P6.1 to P6.3) Input/Output With Schmitt Trigger (PEU Package Only)
Figure 6-24 shows the port diagram. Table 6-83 summarizes the selection of the pin functions.
S39 to S37
LCDS39 to LCDS37
P6REN.x
0
DVSS
1
DVCC
0
1
P6DIR.x
From SD24_B
0
1
P6OUT.x
From SD24_B
(MSP430F677xAIPEU only)
P6.1/SD4DIO/S39
P6.2/SD5DIO/S38
P6DS.x
P6SEL0.x
P6IN.x
P6.3/SD6DIO/S37
EN
To SD24_B
D
Bus
Keeper
Figure 6-24. Port P6 (P6.1 to P6.3) Diagram (PEU Package Only)
Table 6-83. Port P6 (P6.1 to P6.3) Pin Functions (PEU Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P6.x)
x
FUNCTION
LCD39 to
LCDS37
P6DIR.x
P6SEL0.x
P6.1 (I/O)
I:0; O:1
0
1
X
0
1
X
0
1
X
0
0
1
0
0
1
0
0
1
P6.1/SD4DIO/S39
1
Secondary digital function
X
S39
X
P6.2 (I/O)
I:0; O:1
P6.2/SD5DIO/S38
2
3
Secondary digital function
X
S38
X
P6.3 (I/O)
I:0; O:1
P6.3/SD6DIO/S37
Secondary digital function
S37
X
X
(1) X = don't care
134
Detailed Description
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Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.20 Port P6 (P6.4 to P6.7) Input/Output With Schmitt Trigger (PEU Package Only)
Figure 6-25 shows the port diagram. Table 6-84 summarizes the selection of the pin functions.
S36 to S0
LCDS36 to LCDS0
P6REN.x
0
DVSS
1
DVCC
0
1
P6DIR.x
P6OUT.x
DVSS
0
1
(MSP430F677xAIPEU only)
P6.4/S36
P6.5/S35
P6.6/S34
P6.7/S33
P6DS.x
P6SEL0.x
P6IN.x
EN
D
Not used
Bus
Keeper
Figure 6-25. Port P6 (P6.4 to P6.7) Diagram (PEU Package Only)
Copyright © 2014–2018, Texas Instruments Incorporated
Detailed Description
135
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Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
Table 6-84. Port P6 (P6.4 to P6.7) Pin Functions (PEU Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P6.x)
x
FUNCTION
LCDS36 to
LCDS33
P6DIR.x
P6SEL0.x
P6.4 (I/O)
N/A
I:0; O:1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
P6.4/S36
4
DVSS
S36
1
X
P6.5 (I/O)
N/A
I:0; O:1
0
P6.5/S35
P6.6/S34
5
6
7
DVSS
S35
1
X
P6.6(I/O)
N/A
I:0; O:1
0
DVSS
S34
1
X
P6.7 (I/O)
N/A
I:0; O:1
0
1
X
P6.7/S33
DVSS
S33
(1) X = don't care
136
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.21 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger (PZ Package Only)
Figure 6-26 shows the port diagram. Table 6-85 summarizes the selection of the pin functions.
S16 to S9
LCDS16 to LCDS9
P6REN.x
0
DVSS
1
DVCC
0
1
P6DIR.x
0
1
P6OUT.x
DVSS
(MSP430F677xAIPZ only)
P6.0/S16
P6.1/S15
P6.2/S14
P6.3/S13
P6DS.x
P6SEL0.x
P6IN.x
P6.4/S12
P6.5/S11
P6.6/S10
P6.7/S9
EN
Not used
D
Bus
Keeper
Figure 6-26. Port P6 (P6.0 to P6.7) Diagram (PZ Package Only)
Copyright © 2014–2018, Texas Instruments Incorporated
Detailed Description
137
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Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
Table 6-85. Port P6 (P6.0 to P6.7) Pin Functions (PZ Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P6.x)
x
FUNCTION
LCDS16 to
LCDS9
P6DIR.x
P6SEL0.x
P6.0 (I/O)
N/A
I:0; O:1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
P6.0/S16
0
DVSS
S16
1
X
P6.1 (I/O)
N/A
I:0; O:1
0
P6.1/S15
P6.2/S14
P6.3/S13
P6.4/S12
P6.5/S11
P6.6/S10
1
2
3
4
5
6
7
DVSS
S15
1
X
P6.2 (I/O)
N/A
I:0; O:1
0
DVSS
S14
1
X
P6.3 (I/O)
N/A
I:0; O:1
0
DVSS
S13
1
X
P6.4 (I/O)
N/A
I:0; O:1
0
DVSS
S12
1
X
P6.5 (I/O)
N/A
I:0; O:1
0
DVSS
S11
1
X
P6.6 (I/O)
N/A
I:0; O:1
0
DVSS
S10
1
X
P6.7 (I/O)
N/A
I:0; O:1
0
1
X
P6.7/S9
DVSS
S9
(1) X = don't care
138
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.22 Port P7 (P7.0 to P7.7) Input/Output With Schmitt Trigger (PEU Package Only)
Figure 6-27 shows the port diagram. Table 6-86 summarizes the selection of the pin functions.
S32 to S25
LCDS32 to LCDS25
P7REN.x
0
DVSS
1
DVCC
0
1
P7DIR.x
0
1
P7OUT.x
DVSS
(MSP430F677xAIPEU only)
P7.0/S32
P7.1/S31
P7.2/S30
P7.3/S29
P7DS.x
P7SEL0.x
P7IN.x
P7.4/S28
P7.5/S27
P7.6/S26
P7.7/S25
EN
D
Not used
Bus
Keeper
Figure 6-27. Port P7 (P7.0 to P7.7) Diagram (PEU Package Only)
Copyright © 2014–2018, Texas Instruments Incorporated
Detailed Description
139
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Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
Table 6-86. Port P7 (P7.0 to P7.7) Pin Functions (PEU Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P7.x)
x
FUNCTION
LCDS32 to
LCDS25
P7DIR.x
P7SEL0.x
P7.0 (I/O)
N/A
I:0; O:1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
P7.0/S32
0
DVSS
S32
1
X
P7.1 (I/O)
N/A
I:0; O:1
0
P7.1/S31
P7.2/S30
P7.3/S29
P7.4/S28
P7.5/S27
P7.6/S26
1
2
3
4
5
6
7
DVSS
S31
1
X
P7.2 (I/O)
N/A
I:0; O:1
0
DVSS
S30
1
X
P7.3 (I/O)
N/A
I:0; O:1
0
DVSS
S29
1
X
P7.4 (I/O)
N/A
I:0; O:1
0
DVSS
S28
1
X
P7.5 (I/O)
N/A
I:0; O:1
0
DVSS
S27
1
X
P7.6 (I/O)
N/A
I:0; O:1
0
DVSS
S26
1
X
P7.7 (I/O)
N/A
I:0; O:1
0
1
X
P7.7/S25
DVSS
S25
(1) X = don't care
140
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.23 Port P7 (P7.0 to P7.7) Input/Output With Schmitt Trigger (PZ Package Only)
Figure 6-28 shows the port diagram. Table 6-87 summarizes the selection of the pin functions.
S8 to S1
LCDS8 to LCDS1
P7REN.x
0
DVSS
1
DVCC
0
1
P7DIR.x
0
1
P7OUT.x
DVSS
(MSP430F677xAIPZ only)
P7.0/S8
P7.1/S7
P7.2/S6
P7.3/S5
P7DS.x
P7SEL0.x
P7IN.x
P7.4/S4
P7.5/S3
P7.6/S2
P7.7/S1
EN
D
Not used
Bus
Keeper
Figure 6-28. Port P7 (P7.0 to P7.7) Diagram (PZ Package Only)
Copyright © 2014–2018, Texas Instruments Incorporated
Detailed Description
141
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
Table 6-87. Port P7 (P7.0 to P7.7) Pin Functions (PZ Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P7.x)
x
FUNCTION
LCDS8 to
LCDS1
P7DIR.x
P7SEL0.x
P7.0 (I/O)
N/A
I:0; O:1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
P7.0/S8
0
DVSS
S8
1
X
P7.1 (I/O)
N/A
I:0; O:1
0
P7.1/S7
P7.2/S6
P7.3/S5
P7.4/S4
P7.5/S3
P7.6/S2
1
2
3
4
5
6
7
DVSS
S7
1
X
P7.2 (I/O)
N/A
I:0; O:1
0
DVSS
S6
1
X
P7.3 (I/O)
N/A
I:0; O:1
0
DVSS
S5
1
X
P7.4 (I/O)
N/A
I:0; O:1
0
DVSS
S4
1
X
P7.5 (I/O)
N/A
I:0; O:1
0
DVSS
S3
1
X
P7.6 (I/O)
N/A
I:0; O:1
0
DVSS
S2
1
X
P7.7 (I/O)
N/A
I:0; O:1
0
1
X
P7.7/S1
DVSS
S1
(1) X = don't care
142
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.24 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger (PEU Package Only)
Figure 6-29 shows the port diagram. Table 6-88 summarizes the selection of the pin functions.
S24 to S17
LCDS24 to LCDS17
P8REN.x
0
DVSS
1
DVCC
0
1
P8DIR.x
0
1
P8OUT.x
DVSS
(MSP430F677xAIPEU only)
P8.0/S24
P8.1/S23
P8.2/S22
P8.3/S21
P8DS.x
P8SEL0.x
P8IN.x
P8.4/S20
P8.5/S19
P8.6/S18
P8.7/S17
EN
D
Not used
Bus
Keeper
Figure 6-29. Port P8 (P8.0 to P8.7) Diagram (PEU Package Only)
Copyright © 2014–2018, Texas Instruments Incorporated
Detailed Description
143
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Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
Table 6-88. Port P8 (P8.0 to P8.7) Pin Functions (PEU Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P8.x)
x
FUNCTION
LCDS24 to
LCDS17
P8DIR.x
P8SEL0.x
P8.0 (I/O)
N/A
I:0; O:1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
P8.0/S24
0
DVSS
S24
1
X
P8.1 (I/O)
N/A
I:0; O:1
0
P8.1/S23
P8.2/S22
P8.3/S21
P8.4/S20
P8.5/S19
P8.6/S18
1
2
3
4
5
6
7
DVSS
S23
1
X
P8.2 (I/O)
N/A
I:0; O:1
0
DVSS
S22
1
X
P8.3 (I/O)
N/A
I:0; O:1
0
DVSS
S21
1
X
P8.4 (I/O)
N/A
I:0; O:1
0
DVSS
S20
1
X
P8.5 (I/O)
N/A
I:0; O:1
0
DVSS
S19
1
X
P8.6 (I/O)
N/A
I:0; O:1
0
DVSS
S18
1
X
P8.7 (I/O)
N/A
I:0; O:1
0
1
X
P8.7/S17
DVSS
S17
(1) X = don't care
144
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.25 Port P8 (P8.0) Input/Output With Schmitt Trigger (PZ Package Only)
Figure 6-30 shows the port diagram. Table 6-89 summarizes the selection of the pin functions.
S0
LCDS0
P8REN.x
0
DVSS
1
DVCC
0
1
P8DIR.x
0
1
P8OUT.x
DVSS
(MSP430F677xAIPZ only)
P8.0/S0
P8DS.x
P8SEL0.x
P8IN.x
EN
D
Not used
Bus
Keeper
Figure 6-30. Port P8 (P8.0) Diagram (PZ Package Only)
Table 6-89. Port P8 (P8.0) Pin Functions (PZ Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P8.x)
x
FUNCTION
P8DIR.x
P8SEL0.x
LCDS0
P8.0 (I/O)
N/A
I:0; O:1
0
1
1
X
0
0
0
1
0
1
X
P8.0/S0
0
DVSS
S0
(1) X = don't care
Copyright © 2014–2018, Texas Instruments Incorporated
Detailed Description
145
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Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.26 Port P8 (P8.1) Input/Output With Schmitt Trigger (PZ Package Only)
Figure 6-31 shows the port diagram. Table 6-90 summarizes the selection of the pin functions.
To Comparator_B
CBPD.z
P8REN.x
0
DVSS
1
DVCC
0
1
P8DIR.x
0
1
P8OUT.x
RTCCLK
(MSP430F677xAIPZ only)
P8.1/TACLK/RTCCLK/CB3
P8DS.x
P8SEL0.x
P8IN.x
EN
D
To TACLK
Bus
Keeper
Figure 6-31. Port P8 (P8.1) Diagram (PZ Package Only)
Table 6-90. Port P8 (P8.1) Pin Functions (PZ Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P8.x)
x
FUNCTION
P8DIR.x
P8SEL0.x
CBPD.z
P8.1 (I/O)
TACLK
RTCCLK
CB3
I:0; O:1
0
1
1
X
0
0
1
X
0
0
P8.1/TACLK/RTCCLK/CB3
(1) X = don't care
1
1 (z = 3)
146
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.27 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger (PEU Package Only)
Figure 6-32 shows the port diagram. Table 6-91 summarizes the selection of the pin functions.
S16 to S9
LCDS16 to LCDS9
P9REN.x
0
DVSS
1
DVCC
0
1
P9DIR.x
0
1
P9OUT.x
DVSS
(MSP430F677xAIPEU only)
P9.0/S16
P9.1/S15
P9.2/S14
P9.3/S13
P9DS.x
P9SEL0.x
P9IN.x
P9.4/S12
P9.5/S11
P9.6/S10
P9.7/S9
EN
Not used
D
Bus
Keeper
Figure 6-32. Port P9 (P9.0 to P9.7) Diagram (PEU Package Only)
Copyright © 2014–2018, Texas Instruments Incorporated
Detailed Description
147
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Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
Table 6-91. Port P9 (P9.0 to P9.7) Pin Functions (PEU Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P9.x)
x
FUNCTION
LCDS16 to
LCDS9
P9DIR.x
P9SEL0.x
P9.0 (I/O)
N/A
I:0; O:1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
P9.0/S16
0
DVSS
S16
1
X
P9.1 (I/O)
N/A
I:0; O:1
0
P9.1/S15
P9.2/S14
P9.3/S13
P9.4/S12
P9.5/S11
P9.6/S10
1
2
3
4
5
6
7
DVSS
S15
1
X
P9.2 (I/O)
N/A
I:0; O:1
0
DVSS
S14
1
X
P9.3 (I/O)
N/A
I:0; O:1
0
DVSS
S13
1
X
P9.4 (I/O)
N/A
I:0; O:1
0
DVSS
S12
1
X
P9.5 (I/O)
N/A
I:0; O:1
0
DVSS
S11
1
X
P9.6 (I/O)
N/A
I:0; O:1
0
DVSS
S10
1
X
P9.7 (I/O)
N/A
I:0; O:1
0
1
X
P9.7/S9
DVSS
S9
(1) X = don't care
148
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.28 Port P10 (P10.0 to P10.7) Input/Output With Schmitt Trigger (PEU Package Only)
Figure 6-33 shows the port diagram. Table 6-92 summarizes the selection of the pin functions.
S8 to S1
LCDS8 to LCDS1
P10REN.x
0
DVSS
1
DVCC
0
1
P10DIR.x
0
1
P10OUT.x
DVSS
(MSP430F677xIPEU only)
P10.0/S8
P10.1/S7
P10.2/S6
P10.3/S5
P10DS.x
P10SEL0.x
P10IN.x
P10.4/S4
P10.5/S3
P10.6/S2
P10.7/S1
EN
D
Not used
Bus
Keeper
Figure 6-33. Port P10 (P10.0 to P10.7) Diagram (PEU Package Only)
Copyright © 2014–2018, Texas Instruments Incorporated
Detailed Description
149
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
Table 6-92. Port P10 (P10.0 to P10.7) Pin Functions (PEU Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P10.x)
x
FUNCTION
LCDS8 to
LCDS1
P10DIR.x
P10SEL0.x
P10.0 (I/O)
N/A
I:0; O:1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
P10.0/S8
0
DVSS
S8
1
X
P10.1 (I/O)
N/A
I:0; O:1
0
P10.1/S7
P10.2/S6
P10.3/S5
P10.4/S4
P10.5/S3
P10.6/S2
1
2
3
4
5
6
7
DVSS
S7
1
X
P10.2 (I/O)
N/A
I:0; O:1
0
DVSS
S6
1
X
P10.3 (I/O)
N/A
I:0; O:1
0
DVSS
S5
1
X
P10.4 (I/O)
N/A
I:0; O:1
0
DVSS
S4
1
X
P10.5 (I/O)
N/A
I:0; O:1
0
DVSS
S3
1
X
P10.6 (I/O)
N/A
I:0; O:1
0
DVSS
S2
1
X
P10.7 (I/O)
N/A
I:0; O:1
0
1
X
P10.7/S1
DVSS
S1
(1) X = don't care
150
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
6.12.29 Port P11 (P11.0) Input/Output With Schmitt Trigger (PEU Package Only)
Figure 6-34 shows the port diagram. Table 6-93 summarizes the selection of the pin functions.
S0
LCDS0
P11REN.x
0
DVSS
1
DVCC
0
1
P11DIR.x
0
1
P11OUT.x
DVSS
(MSP430F677xIPEU only)
P11.0/S0
P11DS.x
P11SEL0.x
P11IN.x
EN
D
Not used
Bus
Keeper
Figure 6-34. Port P11 (P11.0) Diagram (PEU Package Only)
Table 6-93. Port P11 (P11.0) Pin Functions (PEU Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P11.x)
x
FUNCTION
P11DIR.x
P11SEL0.x
LCDS0
P11.0 (I/O)
N/A
I:0; O:1
0
1
1
X
0
0
0
1
0
1
X
P11.0/S0
0
DVSS
S0
(1) X = don't care
Copyright © 2014–2018, Texas Instruments Incorporated
Detailed Description
151
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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6.12.30 Port P11 (P11.1) Input/Output With Schmitt Trigger (PEU Package Only)
Figure 6-35 shows the port diagram. Table 6-94 summarizes the selection of the pin functions.
To Comparator_B
CBPD.z
P11REN.x
0
DVSS
1
DVCC
0
1
P11DIR.x
0
1
P11OUT.x
From Timer_A
(MSP430F677xIPEU only)
P11.1/TA3.1/CB3
P11DS.x
P11SEL0.x
P11IN.x
EN
To Timer_A
D
Bus
Keeper
Figure 6-35. Port P11 (P11.1) Diagram (PEU Package Only)
Table 6-94. Port P11 (P11.1) Pin Functions (PEU Package Only)
CONTROL BITS OR SIGNALS(1)
PIN NAME (P11.x)
x
FUNCTION
P11DIR.x
P11SEL0.x
CBPD.z
P11.1 (I/O)
TA3.CCI1A
TA3.1
I:0; O:1
0
1
1
X
0
0
0
1
0
1
X
P11.1/TA3.1/CB3
1
CB3
(1) X = don't care
152
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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6.12.31 Port P11 (P11.2 and P11.3) Input/Output With Schmitt Trigger (PEU Package Only)
Figure 6-36 shows the port diagram. Table 6-95 summarizes the selection of the pin functions.
P11REN.x
0
DVSS
1
DVCC
0
1
P11DIR.x
0
1
P11OUT.x
From Timer_A
(MSP430F677xIPEU only)
P11.2/TA1.1
P11.3/TA2.1
P11DS.x
P11SEL0.x
P11IN.x
EN
To Timer_A
D
Bus
Keeper
Figure 6-36. Port P11 (P11.2 and P11.3) Diagram (PEU Package Only)
Table 6-95. Port P11 (P11.2 and P11.3) Pin Functions (PEU Package Only)
CONTROL BITS OR SIGNALS
PIN NAME (P11.x)
x
FUNCTION
P11DIR.x
P11SEL0.x
P11.2 (I/O)
TA1.CCI1A
TA1.1
I:0; O:1
0
1
1
0
1
1
P11.2/TA1.1
P11.3/TA2.1
2
0
1
P11.3 (I/O)
TA2.CCI1A
TA2.1
I:0; O:1
3
0
1
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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6.12.32 Port P11 (P11.4 and P11.5) Input/Output With Schmitt Trigger (PEU Package Only)
Figure 6-37 shows the port diagram. Table 6-96 summarizes the selection of the pin functions.
P11REN.x
0
DVSS
1
DVCC
0
1
P11DIR.x
0
1
P11OUT.x
From Comparator_B
RTCCLK
(MSP430F677xIPEU only)
P11.4/CBOUT
P11.5/TACLK/RTCCLK
P11DS.x
P11SEL0.x
P11IN.x
EN
To TACLK
D
Bus
Keeper
Figure 6-37. Port P11 (P11.4 and P11.5) Diagram (PEU Package Only)
Table 6-96. Port P11 (P11.4 and P11.5) Pin Functions (PEU Package Only)
CONTROL BITS OR SIGNALS
PIN NAME (P11.x)
x
FUNCTION
P11DIR.x
P11SEL0.x
P11.4 (I/O)
N/A
I:0; O:1
0
1
1
0
1
1
P11.4/CBOUT
4
0
CBOUT
P11.5 (I/O)
TACLK
1
I:0; O:1
P11.5/TACLK/RTCCLK
5
0
1
RTCCLK
154
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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6.12.33 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
Figure 6-38 shows the port diagram. Table 6-97 summarizes the selection of the pin functions.
Pad Logic
PJREN.x
0
1
DVSS
DVCC
1
PJDIR.x
DVCC
0
1
PJOUT.x
00
01
10
11
From JTAG
SMCLK
PJ.0/SMCLK/TDO
PJDS.0
0: Low drive
1: High drive
PJSEL.x
From JTAG
PJIN.x
Bus
Holder
EN
D
Figure 6-38. Port PJ (PJ.0) Diagram
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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6.12.34 Port PJ (PJ.0 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt
Trigger or Output
Figure 6-39 shows the port diagram. Table 6-97 summarizes the selection of the pin functions.
Pad Logic
PJREN.x
DVSS
DVCC
0
1
1
PJDIR.x
DVSS
0
1
PJOUT.x
00
From JTAG
01
10
11
PJ.1/MCLK/TDI/TCLK
PJ.2/ADC10CLK/TMS
PJ.3/ACLK/TCK
PJDS.x
0: Low drive
1: High drive
MCLK/ADC10CLK/ACLK
PJSEL.x
From JTAG
PJIN.x
Bus
Holder
EN
D
To JTAG
Figure 6-39. Port PJ (PJ.1 to PJ.3) Diagram
156
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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Table 6-97. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (PJ.x)
x
FUNCTION
PJDIR.x
PJSEL.x
JTAG MODE
PJ.0 (I/O)(2)
SMCLK
TDO(3)
I: 0; O: 1
0
1
x
0
1
x
0
1
x
0
1
x
0
0
1
0
0
1
0
0
1
0
0
1
PJ.0/SMCLK/TDO
PJ.1/MCLK/TDI/TCLK
PJ.2/ADC10CLK/TMS
PJ.3/ACLK/TCK
0
1
x
PJ.1 (I/O)(2)
I: 0; O: 1
1
2
3
MCLK
1
TDI/TCLK(3)
PJ.2 (I/O)(2)
ADC10CLK
x
(4)
I: 0; O: 1
1
(4)
TMS(3)
x
PJ.3 (I/O)(2)
I: 0; O: 1
ACLK
1
x
(4)
TCK(3)
(1) X = don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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6.13 Device Descriptors (TLV)
Table 6-98 through Table 6-100 list the contents of the device descriptor tag-length-value (TLV) structure
for each device type.
Table 6-98. F677xA Device Descriptor
VALUE
DESCRIPTION
Info length
ADDRESS
SIZE (bytes)
F6779A
06h
F6778A
06h
F6777A
06h
F6776A
06h
F6775A
06h
1A00h
1A01h
1A02h
1A04h
1A06h
1A07h
1A08h
1A09h
1A0Ah
1A0Eh
1A10h
1A12h
1A13h
1A14h
1A15h
1A16h
1A18h
1A1Ah
1A1Ch
1A1Eh
1A20h
1A22h
1A24h
1
1
2
2
1
1
1
1
4
2
2
1
1
1
1
2
2
2
2
2
2
2
2
CRC length
CRC value
06h
06h
06h
06h
06h
Per unit
8224h
Per unit
Per unit
08h
Per unit
8223h
Per unit
Per unit
08h
Per unit
8222h
Per unit
Per unit
08h
Per unit
8221h
Per unit
Per unit
08h
Per unit
8220h
Per unit
Per unit
08h
Info Block
Device ID
Hardware revision
Firmware revision
Die record tag
Die record length
Lot ID
0Ah
0Ah
0Ah
0Ah
0Ah
Per unit
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
Per unit
13h
Die Record
X position
Y position
Test record CP
Test record FT
ADC calibration tag
ADC calibration length
ADC gain factor
ADC offset
10h
10h
10h
10h
10h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 15T30
ADC10
Calibration
ADC 15T85
ADC 20T30
ADC 20T85
ADC 25T30
ADC 25T85
158
Detailed Description
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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Table 6-99. F676xA Device Descriptor
VALUE
DESCRIPTION
Info length
ADDRESS
SIZE (bytes)
F6769A
06h
F6768A
06h
F6767A
06h
F6766A
06h
F6765A
06h
1A00h
1A01h
1A02h
1A04h
1A06h
1A07h
1A08h
1A09h
1A0Ah
1A0Eh
1A10h
1A12h
1A13h
1A14h
1A15h
1A16h
1A18h
1A1Ah
1A1Ch
1A1Eh
1A20h
1A22h
1A24h
1
1
2
2
1
1
1
1
4
2
2
1
1
1
1
2
2
2
2
2
2
2
2
CRC length
CRC value
06h
06h
06h
06h
06h
Per unit
821Fh
Per unit
Per unit
08h
Per unit
821Eh
Per unit
Per unit
08h
Per unit
821Dh
Per unit
Per unit
08h
Per unit
821Ch
Per unit
Per unit
08h
Per unit
821Bh
Per unit
Per unit
08h
Info Block
Device ID
Hardware revision
Firmware revision
Die record tag
Die record length
Lot ID
0Ah
0Ah
0Ah
0Ah
0Ah
Per unit
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
Per unit
13h
Die Record
X position
Y position
Test record CP
Test record FT
ADC calibration tag
ADC calibration length
ADC gain factor
ADC offset
10h
10h
10h
10h
10h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 15T30
ADC10
Calibration
ADC 15T85
ADC 20T30
ADC 20T85
ADC 25T30
ADC 25T85
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
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Table 6-100. F674xA Device Descriptor
VALUE
DESCRIPTION
Info length
ADDRESS
SIZE (bytes)
F6749A
06h
F6748A
06h
F6747A
06h
F6746A
06h
F6745A
06h
1A00h
1A01h
1A02h
1A04h
1A06h
1A07h
1A08h
1A09h
1A0Ah
1A0Eh
1A10h
1A12h
1A13h
1A14h
1A15h
1A16h
1A18h
1A1Ah
1A1Ch
1A1Eh
1A20h
1A22h
1A24h
1
1
2
2
1
1
1
1
4
2
2
1
1
1
1
2
2
2
2
2
2
2
2
CRC length
CRC value
06h
06h
06h
06h
06h
Per unit
821Ah
Per unit
Per unit
08h
Per unit
8219h
Per unit
Per unit
08h
Per unit
8218h
Per unit
Per unit
08h
Per unit
8217h
Per unit
Per unit
08h
Per unit
8216h
Per unit
Per unit
08h
Info Block
Device ID
Hardware revision
Firmware revision
Die record tag
Die record length
Lot ID
0Ah
0Ah
0Ah
0Ah
0Ah
Per unit
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
Per unit
13h
Die Record
X position
Y position
Test record CP
Test record FT
ADC calibration tag
ADC calibration length
ADC gain factor
ADC offset
10h
10h
10h
10h
10h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 15T30
ADC10
Calibration
ADC 15T85
ADC 20T30
ADC 20T85
ADC 25T30
ADC 25T85
160
Detailed Description
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MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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6.14 Identification
6.14.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings. For links to all of the errata sheets for the devices
in this data sheet, see 节 8.4.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Hardware Revision" entries in Section 6.13.
6.14.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings. For links to all of the errata sheets for the devices in this data
sheet, see 节 8.4.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Device ID" entries in Section 6.13.
6.14.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
detail in the MSP430 Programming With the JTAG Interface.
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MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
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7 Applications, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
The following resources provide application guidelines and best practices when designing with the
MSP430F677xA, MSP430F676xA, and MSP430F674xA devices.
Implementation of a 3-Phase Electronic Watt-Hour Meter Using the MSP430F677x(A)
This application report describes the implementation of a 3-phase electronic electricity meter using the
TI MSP430F677x(A) metering processors. This application report includes the necessary information
with regard to metrology software and hardware procedures for this single-chip implementation.
High-Accuracy 3-Phase Electricity Meter With Tamper Detection
The design implements a highly accurate 3-phase electric meter system using the MSP430F6779
smart meter SoC. It exceeds all of the requirements for ANSI C12.20 and IEC-62053 Class 0.2 meters.
The F6779 SoC is the most integrated polyphase e-meter SoC with 512KB of flash. This allows
developers to create a true single-chip smart e-meter with the highest performance and accuracy. In
addition, this EVM has tamper detection capabilities which help the engineer develop methods to
prevent theft of electricity from utilities.
Features
•
•
•
Comprehensive design includes schematics, BOMs, design files, and test reports.
Three-phase electricity meter which exceeds Class 0.2 accuracy requirements from ANSI and IEC
TI Energy Library firmware calculates all energy measurement parameters including active and
reactive power and energy, RMS current and voltage, power factor, and line frequency.
•
•
Add-on communications modules for wireless communications standards such as ZigBee®, Wi-Fi®,
Wireless M-Bus, and IEEE Std 802.15.4g, both 2.4 GHz and sub-1 GHz
Built-in 160-segment display powered from 3-phase line voltage
162
Applications, Implementation, and Layout
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提交文档反馈意见
产品主页链接: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A
MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A
MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
8 器件和文档支持
8.1 入门和后续步骤
有关 MSP430™系列器件以及开发协助工具和库的更多信息，请访问入门页面。
8.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS.
These prefixes represent evolutionary stages of product development from engineering prototypes (XMS)
through fully qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical
specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production
devices. TI recommends that these devices not be used in any production system because their expected
end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
temperature range, package type, and distribution format. 图 8-1 provides a legend for reading the
complete device name.
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产品主页链接: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A
MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A
MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
MSP 430 F 5 438 A I ZQW T -EP
Processor Family
MCU Platform
Device Type
Series
Feature Set
Optional: Additional Features
Optional: Tape and Reel
Packaging
Optional: Temperature Range
Optional: A = Revision
Processor Family
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
MCU Platform
Device Type
430 = MSP430 low-power microcontroller platform
Memory Type
C = ROM
Specialized Application
AFE = Analog Front End
BQ = Contactless Power
CG = ROM Medical
F = Flash
FR = FRAM
G = Flash or FRAM (Value Line)
L = No Nonvolatile Memory
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
Series
1 = Up to 8 MHz
5 = Up to 25 MHz
6 = Up to 25 MHz with LCD
0 = Low-Voltage Series
2 = Up to 16 MHz
3 = Legacy
4 = Up to 16 MHz with LCD
Feature Set
Various levels of integration within a series
N/A
Optional: A = Revision
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small reel
R = Large reel
No markings = Tube or tray
Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C)
-HT = Extreme Temperature Parts (–55°C to 150°C)
-Q1 = Automotive Q100 Qualified
图 8-1. Device Nomenclature
164
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产品主页链接: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A
MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A
MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
8.3 工具与软件
所有 MSP 微控制器均受多种软件和硬件开发工具的支持。相关工具由 TI 以及多家第三方供应商提供。请参
阅《MSP430 超低功耗 MCU – 工具与软件》，了解所有工具。
表 8-1 列出 了 MSP430F677xA、MSP430F676xA 和 MSP430F674xA MCU 的调试功能。关于可用特性的
详细信息，请参见《适用于 MSP430 的 Code Composer Studio 用户指南 》。
表 8-1. 硬件调试 特性
四线制
JTAG
两线制
JTAG
断点
(N)
状态序列发生
器
LPMx.5 调试支
持
MSP430 架构
范围断点
有
时钟控制
是
跟踪缓冲器
否
MSP430Xv2
有
有
3
否
有
设计套件与评估模块
用于计量的三相电子电表 EVM (EVM430-F6779) 该 EVM430-F6779 是一款基于 MSP430F6779A 器件的
三相电表评估板。该电表支持三种电压和三种电流的输入，具有可展示防篡改功能的附加连
接。利用该 EVM，您可以测试新的 F677x、F674x、F676x、F677x1、F674x1、F676x1 系
列并查看高精度结果、实现的宽动态范围以及易于校准性。易于使用的能源库提供了计量软
件，可通过此 EVM 快速启动。此外，该软件还具备可编程功能，可满足所有用户需求。
采用增强型 ESD 保护和篡改检测功能的三相计量参考设计 此设计实现了一个具有增强型 ESD 保护的
ANSI/IEC 0.2 类三相能量计。该设计还 具有 篡改检测功能，以限制通过 ZigBee™ 连接进行
能源盗窃和通信的可行性。使用电表
CC2530EM 附加板。开发人员可以使用配套的家用能源显示设备 TI 设计 (TIDM-LOWEND-
IHD) 来远程显示结果。
SoC
来执行所有计量功能并将有功功率结果发送到
适用于 MSP430F6x MCU 的 128 引脚目标开发板和 MSP-FET 编程器捆绑包 MSP-FET430U128 是一款
强大的闪存仿真工具，可在 MSP430 MCU 上快速开始应用开发。它包含 USB 调试接口，用
于通过 JTAG 接口或节省引脚的 Spy-Bi-Wire（两线制 JTAG）协议在系统内对 MSP430 进行
编程和调试。
软件
MSP430Ware™ 软件 MSP430Ware 软件集合了所有 MSP430 器件的代码示例、数据表以及其他设计资
源，打包提供给用户。除了提供已有 MSP430 设计资源的完整集合外，MSP430Ware 软件还
包含名为 MSP 驱动程序库的高级 API。借助该库可以轻松地对 MSP430 硬件进行编程。
MSP430Ware 软件以 CCS 组件或独立软件包两种形式提供。
适用于 MSP430 MCU 的电能测量设计中心
电能测量设计中心是一款快速开发工具，它使用
TI
MSP430i20xx 和 MSP430F67xx 基于闪存的微控制器 (MCU) 实现电能测量。它包含能够在各
种电源监控和电能测量应用（包括智能电网和楼宇自动化）中简化开发和加快设计的图形用户
界面 (GUI)、文档、 软件库和示例。使用设计中心，您无需编写任何代码即可配置、校准并查
看结果。
MSP 驱动程序库 MSP 驱动程序库的抽象 API 提供易用的函数调用，无需直接操纵 MSP430 硬件的位与字
节。完整的文档通过具有帮助意义的 API 指南交付，其中包括有关每个函数调用和经过验证的
参数的详细信息。开发人员可使用驱动程序库函数以尽可能低的费用编写全部项目。
MSP430F677x(1)A、MSP430F676x(1)A、MSP430F674x(1)A 代码示例 为每个 MSP 器件提供了根据不
同应用需求配置各集成外设的 C 代码示例。
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产品主页链接: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A
MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A
MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
MSP EnergyTrace™ 技术 适用于 MSP430 微控制器的 EnergyTrace 技术是基于电能的代码分析工具，适
用于测量和显示应用的电能系统配置并帮助优化应用以实现超低功耗。
ULP（超低功耗）Advisor ULP Advisor™软件是一款辅助工具，旨在指导开发人员编写更为高效的代码，
从而充分利用 MSP430 和 MSP432 微控制器 独特 功能。ULP Advisor 的目标人群是微控制器
的资深开发者和开发新手，可以根据详尽的 ULP 检验表检查代码，以便最大限度地减少应用
程序的能耗。在编译时，ULP Advisor 会提供通知和备注以突出显示代码中可以进一步优化的
区域，进而实现更低功耗。
适用于 MSP 的定点数学库 MSP IQmath 和 Qmath 库是为 C 语言开发者提供的一套经过高度优化的高精
度数学运算函数集合，能够将浮点算法无缝嵌入 MSP430 和 MSP432 器件的定点代码中。这
些例程通常用于计算密集型实时 应用， 而优化的执行速度、高精度以及超低能耗通常是影响
这些实时应用的关键因素。与使用浮点数学算法编写的同等代码相比，使用 IQmath 和 Qmath
库可以大幅提高执行速度并显著降低能耗。
适用于 MSP430 的浮点数学运算库
TI
在低功耗和低成本微控制器领域锐意创新，为您提供
MSPMATHLIB。此标量函数的浮点数学运算库，能够充分利用器件的智能外设，使速度最高
达到标准 MSP430 数学函数的 26 倍。Mathlib 能够轻松集成到您的设计中。该运算库免费使
用并集成在 Code Composer Studio IDE 和 IAR Embedded Workbench IDE 中。
开发工具
适用于 MSP 微控制器的 Code Composer Studio™ 集成开发环境 Code Composer Studio (CCS) 集成开
发环境 (IDE) 支持所有 MSP 微控制器器件。CCS 包含一整套用于开发和调试嵌入式 应用的
工具。它包含了优化的 C/C++ 编译器、源代码编辑器、项目构建环境、调试器、描述器以及
其他多种 功能。
命令行编程器 MSP Flasher 是一款基于 shell 的开源接口，可使用 JTAG 或 Spy-Bi-Wire (SBW) 通信通过
FET 编程器或 eZ430 对 MSP 微控制器进行编程。MSP Flasher 可用于将二进制文件（.txt 或
.hex 文件）直接下载到 MSP 微控制器，而无需使用 IDE。
MSP MCU 编程器和调试器 MSP-FET 是一款强大的仿真开发工具（通常称为调试探针），可帮助用户在
MSP 低功耗微控制器 (MCU) 中快速开发应用。创建 MCU 软件通常需要将生成的二进制程序
下载到 MSP 器件中，从而进行验证和调试。
MSP-GANG 生产编程器 MSP Gang 编程器是一款 MSP430 或 MSP432 器件编程器，可同时对多达八个
完全相同的 MSP430 或 MSP432 闪存或 FRAM 器件进行编程。MSP Gang 编程器可使用标
准的 RS-232 或 USB 连接与主机 PC 相连并提供灵活的编程选项，允许用户完全自定义流
程。
166
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产品主页链接: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A
MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A
MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
8.4 文档支持
以下文档对 MSP430F677xA、MSP430F676xA 和 MSP430F674xA MCU 进行了介绍。www.ti.com.cn 网站
上提供了这些文档的副本。
接收文档更新通知
要接收文档更新通知（包括芯片勘误表），请转至 ti.com.cn 上您的器件对应的产品文件夹（关于产品文件
夹的链接，请参见节 8.5）。请单击右上角的“通知我”按钮。点击注册后，即可收到产品信息更改每周摘要
（如有）。有关更改的详细信息，请查阅已修订文档的修订历史记录。
勘误
《MSP430F6779A 器件勘误表》 介绍功能规格的已知例外情况。
《MSP430F6778A 器件勘误表》 介绍功能规格的已知例外情况。
《MSP430F6777A 器件勘误表》 介绍功能规格的已知例外情况。
《MSP430F6776A 器件勘误表》 介绍功能规格的已知例外情况。
《MSP430F6775A 器件勘误表》 介绍功能规格的已知例外情况。
《MSP430F6769A 器件勘误表》 介绍功能规格的已知例外情况。
《MSP430F6768A 器件勘误表》 介绍功能规格的已知例外情况。
《MSP430F6767A 器件勘误表》 介绍功能规格的已知例外情况。
《MSP430F6766A 器件勘误表》 介绍功能规格的已知例外情况。
《MSP430F6765A 器件勘误表》 介绍功能规格的已知例外情况。
《MSP430F6749A 器件勘误表》 介绍功能规格的已知例外情况。
《MSP430F6748A 器件勘误表》 介绍功能规格的已知例外情况。
《MSP430F6747A 器件勘误表》 介绍功能规格的已知例外情况。
《MSP430F6746A 器件勘误表》 介绍功能规格的已知例外情况。
《MSP430F6745A 器件勘误表》 介绍功能规格的已知例外情况。
用户指南
《MSP430x5xx 和 MSP430x6xx 系列用户指南》 详细介绍了该器件系列提供的模块和外设。
《MSP430™ 闪存器件引导加载程序 (BSL) 用户指南》 MSP430 引导加载程序 (BSL) 允许用户在原型设
计、投产和维护等各阶段与 MSP430 微控制器中的嵌入式存储器进行通信。可编程存储器
（闪存）和数据存储器 (RAM) 可根据相关要求进行变更。不要将此处的引导加载程序与某些
数字信号处理器 (DSP) 中将外部存储器中的程序代码（和数据）自动加载到 DSP 内部存储器
的引导装载程序混为一谈。
《通过 JTAG 接口对 MSP430 进行编程》
此文档介绍了使用 JTAG 通信端口擦除、编程和验证基于
MSP430 闪存和 FRAM 的微控制器系列的存储器模块所需的功能。此外，该文档还介绍了如
何编程所有 MSP430 器件上均具备的 JTAG 访问安全保险丝。此文档介绍了使用标准四线制
JTAG 接口和两线制 JTAG 接口（也称为 Spy-Bi-Wire (SBW)）的器件访问。
《MSP430 硬件工具用户指南》 此手册介绍了 TI MSP-FET430 闪存仿真工具 (FET) 的硬件。FET 是针对
MSP430
超低功耗微控制器的程序开发工具。文中对提供的接口类型，即并行端口接口和
USB 接口进行了说明。
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产品主页链接: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A
MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A
MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
应用报告
《使用 MSP430F677x(A) 实施三相电子电表》 该应用报告介绍了如何使用 MSP430F677x(A) 计量处理器
实现三相电子电表。该应用报告包含有关此单芯片实现的计量软件、硬件程序的必要信息。
《使用 TI 的 DLMS COSEM 库》 该应用报告详细介绍了如何使用德州仪器 (TI) 为在计量应用中使用 TI 微
控制器的客户 开发的 DLMS COSEM 库。该库作为目标代码提供，具有易于使用的配置文
件。可以通过联系区域销售和营销办事处获得该库。
《MSP430F67xx 与 MSP430F67xxA 器件之间的差异》 该应用报告介绍了非 A MSP430F67xx 器件对
MSP430F67xxA
器件的增强功能。该应用报告介绍了在
MSP430F67xx 勘误表以及向 MSP430F67xxA 器件 添加的 其他功能。此外，还比较了计量结
MSP430F67xxA
中修复的
果，以进一步展示 MSP430F67xxA 器件中实现的更改不会影响计量性能。
《MSP430 32kHz 晶体振荡器》 对于稳定的晶体振荡器，选择合适的晶振、正确的负载电路和适当的电路
板布局布线至关重要。该应用报告总结了晶体振荡器的功能，介绍了用于选择合适的晶体以实
现 MSP430 超低功耗运行的参数。此外，还给出了正确电路板布局的提示和示例。此外，为
了确保振荡器在大规模生产后能够稳定运行，还可能需要进行一些振荡器测试，该文档中提供
了有关这些测试的详细信息。
《MSP430 系统级 ESD 注意事项》
随着硅晶技术向更低电压方向发展以及设计具有成本效益的超低功耗
组件的需求的出现，系统级 ESD 要求变得越来越苛刻。该应用报告介绍了三个不同的 ESD 主
题，旨在帮助电路板设计人员和 OEM 理解并设计出稳健耐用的系统级设计。
《使用 MSP430 和段式 LCD 进行设计》 从智能电表，到电子货架标签 (ESL)，再到医疗设备，各式各样
的应用 都需要使用段式液晶显示屏 (LCD) 为用户 提供相关信息。部分 MSP430™ 微控制器系
列内置低功耗 LCD 驱动电路，MSP430 MCU 借此能够直接控制段式 LCD 玻璃。本应用手册
可帮助您理解段式 LCD 的工作原理、MSP430 MCU 系列各种 LCD 模块的不同特性， 并提供
了 LCD 硬件布线技巧、编写高效易用的 LCD 驱动软件的相关指导以及 具有不同 LCD 特性的
MSP430 器件的 产品组合概述， 旨在协助您进行器件选型。
168
器件和文档支持
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提交文档反馈意见
产品主页链接: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A
MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A
MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
8.5 相关链接
表 8-2 列出了快速访问链接。类别包括技术文档、支持与社区资源、工具与软件，以及申请样片或购买产品
的快速链接。
表 8-2. 相关链接
器件
产品文件夹
请单击此处
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立即订购
技术文档
工具与软件
请单击此处
请单击此处
请单击此处
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请单击此处
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支持和社区
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
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请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
MSP430F6779A
MSP430F6778A
MSP430F6777A
MSP430F6776A
MSP430F6775A
MSP430F6769A
MSP430F6768A
MSP430F6767A
MSP430F6766A
MSP430F6765A
MSP430F6749A
MSP430F6748A
MSP430F6747A
MSP430F6746A
MSP430F6745A
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
8.6 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术
规范，并且不一定反映 TI 的观点；请参见 TI 的 《使用条款》。
TI E2E™ 社区
TI 的工程师交流 (E2E) 社区. 此社区的创建目的是为了促进工程师之间协作。在 e2e.ti.com 中，您可以提
问、共享知识、拓展思路，在同领域工程师的帮助下解决问题。
TI 嵌入式处理器维基网页
德州仪器 (TI) 嵌入式处理器维基网页。此网站的建立是为了帮助开发人员熟悉德州仪器 (TI) 的嵌入式处理
器，并且也为了促进与这些器件相关的硬件和软件的总体知识的创新和增长。
8.7 商标
MSP430, MSP430Ware, EnergyTrace, ULP Advisor, 适用于 MSP 微控制器的 Code Composer Studio,
E2E are trademarks of Texas Instruments.
Wi-Fi is a registered trademark of Wi-Fi Alliance.
ZigBee is a registered trademark of ZigBee Alliance.
8.8 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
8.9 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
版权 © 2014–2018, Texas Instruments Incorporated
器件和文档支持
169
提交文档反馈意见
产品主页链接: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A
MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A
MSP430F6747A MSP430F6746A MSP430F6745A
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A
ZHCSCN8A –MAY 2014–REVISED SEPTEMBER 2018
www.ti.com.cn
9 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通
知，且不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
170
机械、封装和可订购信息
版权 © 2014–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A
MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A
MSP430F6747A MSP430F6746A MSP430F6745A
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430F6745AIPEU
MSP430F6745AIPEUR
MSP430F6745AIPZ
MSP430F6745AIPZR
MSP430F6746AIPEU
MSP430F6746AIPEUR
MSP430F6746AIPZ
MSP430F6746AIPZR
MSP430F6747AIPEU
MSP430F6747AIPEUR
MSP430F6747AIPZ
MSP430F6747AIPZR
MSP430F6748AIPEU
MSP430F6748AIPEUR
MSP430F6748AIPZ
MSP430F6748AIPZR
MSP430F6749AIPEU
MSP430F6749AIPEUR
MSP430F6749AIPZ
MSP430F6749AIPZR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
PEU
PEU
PZ
128
128
100
100
128
128
100
100
128
128
100
100
128
128
100
100
128
128
100
100
72
750
90
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
F6745A
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
F6745A
F6745A
F6745A
F6746A
F6746A
F6746A
F6746A
F6747A
F6747A
F6747A
F6747A
F6748A
F6748A
F6748A
F6748A
F6749A
F6749A
F6749A
F6749A
PZ
1000 RoHS & Green
PEU
PEU
PZ
72
750
90
RoHS & Green
RoHS & Green
RoHS & Green
PZ
1000 RoHS & Green
PEU
PEU
PZ
72
750
90
RoHS & Green
RoHS & Green
RoHS & Green
PZ
1000 RoHS & Green
PEU
PEU
PZ
72
750
90
RoHS & Green
RoHS & Green
RoHS & Green
PZ
1000 RoHS & Green
PEU
PEU
PZ
72
750
90
RoHS & Green
RoHS & Green
RoHS & Green
PZ
1000 RoHS & Green
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430F6765AIPEU
MSP430F6765AIPEUR
MSP430F6765AIPZ
MSP430F6765AIPZR
MSP430F6766AIPEU
MSP430F6766AIPEUR
MSP430F6766AIPZ
MSP430F6766AIPZR
MSP430F6767AIPEU
MSP430F6767AIPEUR
MSP430F6767AIPZ
MSP430F6767AIPZR
MSP430F6768AIPEU
MSP430F6768AIPEUR
MSP430F6768AIPZ
MSP430F6768AIPZR
MSP430F6769AIPEU
MSP430F6769AIPEUR
MSP430F6769AIPZ
MSP430F6769AIPZR
MSP430F6775AIPEU
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
PEU
PEU
PZ
128
128
100
100
128
128
100
100
128
128
100
100
128
128
100
100
128
128
100
100
128
72
750
90
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
F6765A
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
F6765A
F6765A
F6765A
F6766A
F6766A
F6766A
F6766A
F6767A
F6767A
F6767A
F6767A
F6768A
F6768A
F6768A
F6768A
F6769A
F6769A
F6769A
F6769A
F6775A
PZ
1000 RoHS & Green
PEU
PEU
PZ
72
750
90
RoHS & Green
RoHS & Green
RoHS & Green
PZ
1000 RoHS & Green
PEU
PEU
PZ
72
750
90
RoHS & Green
RoHS & Green
RoHS & Green
PZ
1000 RoHS & Green
PEU
PEU
PZ
72
750
90
RoHS & Green
RoHS & Green
RoHS & Green
PZ
1000 RoHS & Green
PEU
PEU
PZ
72
750
90
RoHS & Green
RoHS & Green
RoHS & Green
PZ
1000 RoHS & Green
PEU
72
RoHS & Green
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430F6775AIPEUR
MSP430F6775AIPZ
MSP430F6775AIPZR
MSP430F6776AIPEU
MSP430F6776AIPEUR
MSP430F6776AIPZ
MSP430F6776AIPZR
MSP430F6777AIPEU
MSP430F6777AIPEUR
MSP430F6777AIPZ
MSP430F6777AIPZR
MSP430F6778AIPEU
MSP430F6778AIPEUR
MSP430F6778AIPZ
MSP430F6778AIPZR
MSP430F6779AIPEU
MSP430F6779AIPEUR
MSP430F6779AIPZ
MSP430F6779AIPZR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
PEU
PZ
128
100
100
128
128
100
100
128
128
100
100
128
128
100
100
128
128
100
100
750
90
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
F6775A
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
F6775A
F6775A
F6776A
F6776A
F6776A
F6776A
F6777A
F6777A
F6777A
F6777A
F6778A
F6778A
F6778A
F6778A
F6779A
F6779A
F6779A
F6779A
PZ
1000 RoHS & Green
PEU
PEU
PZ
72
750
90
RoHS & Green
RoHS & Green
RoHS & Green
PZ
1000 RoHS & Green
PEU
PEU
PZ
72
750
90
RoHS & Green
RoHS & Green
RoHS & Green
PZ
1000 RoHS & Green
PEU
PEU
PZ
72
750
90
RoHS & Green
RoHS & Green
RoHS & Green
PZ
1000 RoHS & Green
PEU
PEU
PZ
72
750
90
RoHS & Green
RoHS & Green
RoHS & Green
PZ
1000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430F6745AIPZR
MSP430F6746AIPZR
MSP430F6747AIPZR
MSP430F6748AIPZR
MSP430F6749AIPZR
MSP430F6765AIPZR
MSP430F6766AIPZR
MSP430F6767AIPZR
MSP430F6768AIPZR
MSP430F6769AIPZR
MSP430F6775AIPZR
MSP430F6776AIPZR
MSP430F6777AIPZR
MSP430F6778AIPZR
MSP430F6779AIPZR
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
PZ
PZ
PZ
PZ
PZ
PZ
PZ
PZ
PZ
PZ
PZ
PZ
PZ
PZ
PZ
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
24.4
24.4
24.4
24.4
24.4
24.4
24.4
24.4
24.4
24.4
24.4
24.4
24.4
24.4
24.4
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430F6745AIPZR
MSP430F6746AIPZR
MSP430F6747AIPZR
MSP430F6748AIPZR
MSP430F6749AIPZR
MSP430F6765AIPZR
MSP430F6766AIPZR
MSP430F6767AIPZR
MSP430F6768AIPZR
MSP430F6769AIPZR
MSP430F6775AIPZR
MSP430F6776AIPZR
MSP430F6777AIPZR
MSP430F6778AIPZR
MSP430F6779AIPZR
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
PZ
PZ
PZ
PZ
PZ
PZ
PZ
PZ
PZ
PZ
PZ
PZ
PZ
PZ
PZ
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2022
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
MSP430F6745AIPEU
MSP430F6745AIPZ
MSP430F6746AIPEU
MSP430F6746AIPZ
MSP430F6747AIPEU
MSP430F6747AIPZ
MSP430F6748AIPEU
MSP430F6748AIPZ
MSP430F6749AIPEU
MSP430F6749AIPZ
MSP430F6765AIPEU
MSP430F6765AIPZ
MSP430F6766AIPEU
MSP430F6766AIPZ
MSP430F6767AIPEU
MSP430F6767AIPZ
MSP430F6768AIPEU
PEU
PZ
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
128
100
128
100
128
100
128
100
128
100
128
100
128
100
128
100
128
72
90
72
90
72
90
72
90
72
90
72
90
72
90
72
90
72
6X12
6 x 15
6X12
6 x 15
6X12
6 x 15
6X12
6 x 15
6X12
6 x 15
6X12
6 x 15
6X12
6 x 15
6X12
6 x 15
6X12
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
315 135.9 7620 25.4
315 135.9 7620 20.3
315 135.9 7620 25.4
315 135.9 7620 20.3
315 135.9 7620 25.4
315 135.9 7620 20.3
315 135.9 7620 25.4
315 135.9 7620 20.3
315 135.9 7620 25.4
315 135.9 7620 20.3
315 135.9 7620 25.4
315 135.9 7620 20.3
315 135.9 7620 25.4
315 135.9 7620 20.3
315 135.9 7620 25.4
315 135.9 7620 20.3
315 135.9 7620 25.4
17.8 15.45
15.4 15.45
17.8 15.45
15.4 15.45
17.8 15.45
15.4 15.45
17.8 15.45
15.4 15.45
17.8 15.45
15.4 15.45
17.8 15.45
15.4 15.45
17.8 15.45
15.4 15.45
17.8 15.45
15.4 15.45
17.8 15.45
PEU
PZ
PEU
PZ
PEU
PZ
PEU
PZ
PEU
PZ
PEU
PZ
PEU
PZ
PEU
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2022
Device
Package Package Pins SPQ Unit array
Max
L (mm)
W
K0
P1
CL
CW
Name
Type
matrix temperature
(°C)
(mm) (µm) (mm) (mm) (mm)
MSP430F6768AIPZ
MSP430F6769AIPEU
MSP430F6769AIPZ
MSP430F6775AIPEU
MSP430F6775AIPZ
MSP430F6776AIPEU
MSP430F6776AIPZ
MSP430F6777AIPEU
MSP430F6777AIPZ
MSP430F6778AIPEU
MSP430F6778AIPZ
MSP430F6779AIPEU
MSP430F6779AIPZ
PZ
PEU
PZ
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
100
128
100
128
100
128
100
128
100
128
100
128
100
90
72
90
72
90
72
90
72
90
72
90
72
90
6 x 15
6X12
6 x 15
6X12
6 x 15
6X12
6 x 15
6X12
6 x 15
6X12
6 x 15
6X12
6 x 15
150
150
150
150
150
150
150
150
150
150
150
150
150
315 135.9 7620 20.3
315 135.9 7620 25.4
315 135.9 7620 20.3
315 135.9 7620 25.4
315 135.9 7620 20.3
315 135.9 7620 25.4
315 135.9 7620 20.3
315 135.9 7620 25.4
315 135.9 7620 20.3
315 135.9 7620 25.4
315 135.9 7620 20.3
315 135.9 7620 25.4
315 135.9 7620 20.3
15.4 15.45
17.8 15.45
15.4 15.45
17.8 15.45
15.4 15.45
17.8 15.45
15.4 15.45
17.8 15.45
15.4 15.45
17.8 15.45
15.4 15.45
17.8 15.45
15.4 15.45
PEU
PZ
PEU
PZ
PEU
PZ
PEU
PZ
PEU
PZ
Pack Materials-Page 4
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
M
0,08
51
50
76
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
0,25
16,20
SQ
0,05 MIN
0°–7°
15,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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