MSP430FG461X [TI]
MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器型号: | MSP430FG461X |
厂家: | TEXAS INSTRUMENTS |
描述: | MIXED SIGNAL MICROCONTROLLER |
文件: | 总105页 (文件大小:1856K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
D
D
Low Supply-Voltage Range, 1.8 V to 3.6 V
D
D
Universal Serial Communication Interface
− Enhanced UART supporting
auto-baudrate detection
Ultralow-Power Consumption:
− Active Mode: 350 µA at 1 MHz, 2.2 V
− Standby Mode: 1.1 µA
− Off Mode (RAM Retention): 0.3 µA
Five Power Saving Modes
− IrDA Encoder and Decoder
− Synchronous SPI
TM
− I2C
D
D
D
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
Wake-Up From Standby Mode in less
than 6 µs
16-Bit RISC Architecture, Extended
Memory, 125-ns Instruction Cycle Time
D
D
D
D
Brownout Detector
D
Three Channel Internal DMA
Basic Timer with Real Time Clock Feature
D
12-Bit A/D Converter With Internal
Reference, Sample-and-Hold and Autoscan
Feature
Integrated LCD Driver up to 160 Segments
With Regulated Charge Pump
Family Members Include:
− MSP430FG4616:
92KB+256B Flash Memory,
4KB RAM
D
D
Three Configurable Operational Amplifiers
Dual 12-Bit D/A Converters With
Synchronization
D
D
16-Bit Timer_A With Three
Capture/Compare Registers
− MSP430FG4617:
92KB+256B Flash Memory,
8KB RAM
− MSP430FG4618:
116KB+256B Flash Memory,
8KB RAM
− MSP430FG4619:
120KB+256B Flash Memory,
4KB RAM
16-Bit Timer_B With Seven
Capture/Compare-With-Shadow Registers
D
On-Chip Comparator
D
Supply Voltage Supervisor/Monitor With
Programmable Level Detection
D
Serial Communication Interface (USART1),
Select Asynchronous UART or
Synchronous SPI by Software
D
For Complete Module Descriptions, Refer
to the MSP430x4xx Family User’s Guide
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs.
The MSP430FG461x series are microcontroller configurations with two 16-bit timers, a high performance 12-bit
A/D converter, dual 12-bit D/A converters, three configurable operational amplifiers, one universal serial
communication interface (USCI), one universal synchronous/asynchronous communication interface
(USART), DMA, 80 I/O pins, and a liquid crystal display (LCD) driver with regulated charge pump.
Typical applications for this device include analog and digital sensor systems, digital motor control, remote
controls, thermostats, digital timers, hand-held meters, etc.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢂ
ꢓ
ꢔ
ꢎ
ꢖ
ꢒ
ꢕ
ꢂ
ꢓ
ꢍ
ꢗ
ꢋ
ꢍ
ꢘ
ꢙ
ꢚ
ꢛ
ꢜ
ꢝ
ꢞ
ꢟ
ꢠ
ꢙ
ꢜ
ꢚ
ꢡ
ꢜ
ꢚ
ꢡ
ꢢ
ꢝ
ꢚ
ꢣ
ꢤ
ꢝ
ꢜ
ꢥ
ꢦ
ꢥꢢ ꢣ ꢙ ꢩꢚ ꢤꢧ ꢟ ꢣ ꢢ ꢜꢛ ꢥꢢ ꢨ ꢢ ꢪꢜ ꢤꢞꢢ ꢚꢠꢫ ꢒ ꢧꢟ ꢝꢟ ꢡꢠ ꢢꢝ ꢙꢣ ꢠꢙ ꢡ ꢥꢟ ꢠꢟ ꢟꢚ ꢥ ꢜꢠ ꢧꢢꢝ
ꢡ
ꢠ
ꢣ
ꢙ
ꢚ
ꢠ
ꢧ
ꢢ
ꢛ
ꢜ
ꢝ
ꢞ
ꢟ
ꢠ
ꢙ
ꢨ
ꢢ
ꢜ
ꢝ
Copyright 2006, Texas Instruments Incorporated
ꢣ
ꢤ
ꢢ
ꢡ
ꢙ
ꢛ
ꢙ
ꢡ
ꢟ
ꢠ
ꢙ
ꢜ
ꢚ
ꢣ
ꢟ
ꢝ
ꢢ
ꢥ
ꢢ
ꢣ
ꢙ
ꢩ
ꢚ
ꢩ
ꢜ
ꢟ
ꢪ
ꢣ
ꢫ
ꢕ
ꢢ
ꢊ
ꢟ
ꢣ
ꢋ
ꢚ
ꢣ
ꢠ
ꢝ
ꢦ
ꢞ
ꢢ
ꢚ
ꢡ ꢧꢟ ꢚ ꢩꢢ ꢜꢝ ꢥꢙ ꢣ ꢡ ꢜꢚ ꢠꢙ ꢚꢦꢢ ꢠ ꢧꢢ ꢣ ꢢ ꢤꢝ ꢜꢥ ꢦꢡꢠ ꢣ ꢬ ꢙꢠꢧ ꢜꢦꢠ ꢚꢜꢠ ꢙꢡꢢ ꢫ
ꢠ
ꢣ
ꢝ
ꢢ
ꢣ
ꢢ
ꢝ
ꢨ
ꢢ
ꢣ
ꢠ
ꢧ
ꢢ
ꢝ
ꢙ
ꢩ
ꢧ
ꢠ
ꢠ
ꢜ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
PLASTIC 100-PIN TQFP
(PZ)
MSP430FG4616IPZ
MSP430FG4617IPZ
MSP430FG4618IPZ
MSP430FG4619IPZ
−40°C to 85°C
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
pin designation, MSP430FG461xIPZ
1
75
DV
P2.4/UCA0TXD
P2.5/UCA0RXD
P2.6/CAOUT
CC1
2
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P6.3/A3/OA1O
P6.4/A4/OA1I0
P6.5/A5/OA2O
P6.6/A6/DAC0/OA2I0
P6.7/A7/DAC1/SVSIN
VREF+
3
4
P2.7/ADC12CLK/DMAE0
P3.0/UCB0STE
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK
P3.4/TB3
5
6
7
8
XIN
9
XOUT
VeREF+/DAC0
VREF−/VeREF−
P5.1/S0/A12/DAC1
P5.0/S1/A13/OA1I1
P10.7/S2/A14/OA2I1
P10.6/S3/A15
P10.5/S4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P3.5/TB4
P3.6/TB5
MSP430FG4616IPZ
MSP430FG4617IPZ
MSP430FG4618IPZ
MSP430FG4619IPZ
P3.7/TB6
P4.0/UTXD1
P4.1/URXD1
DV
DV
SS2
CC2
P10.4/S5
LCDCAP/R33
P5.7/R23
P10.3/S6
P10.2/S7
P5.6/LCDREF/R13
P5.5/R03
P10.1/S8
P10.0/S9
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P9.7/S10
P9.6/S11
P9.5/S12
P9.4/S13
P4.2/STE1/S39
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
MSP430FG461x functional block diagram
XIN/ XOUT/
XT2IN XT2OUT
P3.x/P4.x
P5.x/P6.x
P7.x/P8.x
P9.x/P10.x
DVCC 1/2 DVSS1/2
AVCC
AVSS
P1.x/P2.x
2x8
2
2
4x8
4x8/2x16
ACLK
Flash
RAM
Ports
P3/P4
P5/P6
Ports
P7/P8
P9/P10
Oscillators
FLL+
ADC12
12−Bit
DAC12
12−Bit
Ports P 1/P2
OA0, OA1,
OA2
120kB
116 kB
92kB
4kB
8kB
8kB
4kB
Comparator
_A
SMCLK
2x8 I/O
Interrupt
capability
12
Channels
2 Channels
Voltage out
3 Op Amps
4x8 I/O
4x8/2x16 I/O
MCLK
92kB
MAB
8MHz
DMA
CPUX
incl. 16
Controller
Registers
3 Channels
MDB
Enhanced
Emulation
Hardware
Multiplier
Timer_A3
Timer_B7
USCI_A0:
UART,
LCD_A
USART1
Brownout
Protection
Watchdog
WDT+
Basic Timer
&
Real −Time
Clock
JTAG
Interface
3 CC
Registers
7 CC
Registers
Shadow
Reg
IrDA, SPI
MPY ,
MPYS,
MAC,
MACS
160
Segments
1,2,3,4 Mux
UART , SPI
USCI_B0:
SPI, I2C
SVS/SVM
15/16−Bit
RST/NMI
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
MSP430FG461x Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
Digital supply voltage, positive terminal.
NO.
1
DV
CC1
P6.3/A3/OA1O
P6.4/A4/OA1I0
2
I/O General-purpose digital I/O / analog input a3—12-bit ADC / OA1 output
3
I/O General-purpose digital I/O / analog input a4—12-bit ADC / OA1 input multiplexer on
+terminal and −terminal
P6.5/A5/OA2O
4
5
I/O General-purpose digital I/O / analog input a5—12-bit ADC / OA2 output
P6.6/A6/DAC0/OA2I0
I/O General-purpose digital I/O / analog input a6—12-bit ADC / DAC12.0 output / OA2 input
multiplexer on +terminal and −terminal
General-purpose digital I/O / analog input a7—12-bit ADC / DAC12.1 output / analog input
to brownout, supply voltage supervisor
P6.7/A7/DAC1/SVSIN
6
I/O
V
7
8
O
I
Output of positive terminal of the reference voltage in the ADC
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
Output terminal of crystal oscillator XT1
REF+
XIN
XOUT
9
O
Ve /DAC0
REF+
10
I/O Input for an external reference voltage to the ADC / DAC12.0 output
Negative terminal for the ADC’s reference voltage for both sources, the internal reference
voltage, or an external applied reference voltage
V
/Ve
11
12
13
14
I
REF− REF−
General-purpose digital I/O / LCD segment output 0 / analog input a12 − 12−bit ADC /
DAC12.1 output
P5.1/S0/A12/DAC1 (see Note 1)
P5.0/S1/A13/OA1I1 (see Note 1)
P10.7/S2/A14/OA2I1 (see Note 1)
I/O
General-purpose digital I/O / LCD segment output 1 / analog input a13 − 12−bit ADC/OA1
input multiplexer on +terminal and −terminal
I/O
General-purpose digital I/O / LCD segment output 2 / analog input a14 − 12−bit ADC/OA2
input multiplexer on +terminal and −terminal
I/O
P10.6/S3/A15 (see Note 1)
P10.5/S4
P10.4/S5
P10.3/S6
P10.2/S7
P10.1/S8
P10.0/S9
P9.7/S10
P9.6/S11
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
I/O General-purpose digital I/O / LCD segment output 3 / analog input a15 − 12−bit ADC
I/O General-purpose digital I/O / LCD segment output 4
I/O General-purpose digital I/O / LCD segment output 5
I/O General-purpose digital I/O / LCD segment output 6
I/O General-purpose digital I/O / LCD segment output 7
I/O General-purpose digital I/O / LCD segment output 8
I/O General-purpose digital I/O / LCD segment output 9
I/O General-purpose digital I/O / LCD segment output 10
I/O General-purpose digital I/O / LCD segment output 11
I/O General-purpose digital I/O / LCD segment output 12
I/O General-purpose digital I/O / LCD segment output 13
I/O General-purpose digital I/O / LCD segment output 14
I/O General-purpose digital I/O / LCD segment output 15
I/O General-purpose digital I/O / LCD segment output 16
I/O General-purpose digital I/O / LCD segment output 17
I/O General-purpose digital I/O / LCD segment output 18
I/O General-purpose digital I/O / LCD segment output 19
I/O General-purpose digital I/O / LCD segment output 20
I/O General-purpose digital I/O / LCD segment output 21
I/O General-purpose digital I/O / LCD segment output 22
P9.5/S12
P9.4/S13
P9.3/S14
P9.2/S15
P9.1/S16
P9.0/S17
P8.7/S18
P8.6/S19
P8.5/S20
P8.4/S21
P8.3/S22
NOTES: 1. Segments S0 through S3 must be disabled and cannot be used when the LCD charge pump feature is enabled. In addition, when
using segments S0 through S3 with an external LCD voltage supply, V ≤ AV
.
LCD CC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢍ
ꢀ
ꢋ
ꢌ
ꢎ
ꢁ
ꢋ
ꢇ
ꢏ
ꢐ
ꢑ
ꢀ
ꢋ
ꢒ
ꢓ
ꢔ
ꢒ
ꢔ
ꢏ
ꢕ
ꢓ
ꢔꢑ
ꢑꢍ
ꢓ
SLAS508 − APRIL 2006
MSP430FG461x Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
NO.
35
36
37
38
39
40
41
P8.2/S23
P8.1/S24
P8.0/S25
P7.7/S26
P7.6/S27
P7.5/S28
P7.4/S29
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O / LCD segment output 23
General-purpose digital I/O / LCD segment output 24
General-purpose digital I/O / LCD segment output 25
General-purpose digital I/O / LCD segment output 26
General-purpose digital I/O / LCD segment output 27
General-purpose digital I/O / LCD segment output 28
General-purpose digital I/O / LCD segment output 29
General-purpose digital I/O / external clock input—USCI_A0/UART or SPI mode, clock
output—USART1/SPI MODE / LCD segment output 30
P7.3/UCA0CLK/S30
P7.2/UCA0SOMI/S31
P7.1/UCA0SIMO/S32
P7.0/UCA0STE/S33
P4.7/UCA0RXD/S34
P4.6/UCA0TXD/S35
P4.5/UCLK1/S36
42
43
44
45
46
47
48
49
50
51
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O / slave out/master in of USCI_A0/SPI mode / LCD segment output
31
General-purpose digital I/O / slave in/master out of USCI_A0/SPI mode / LCD segment output
32
General-purpose digital I/O / slave transmit enable—USCI_A0/SPI mode / LCD segment output
33
General-purpose digital I/O / receive data in − USCI_A0/UART or IrDA mode / LCD segment
output 34
General-purpose digital I/O / transmit data in − USCI_A0/UART or IrDA mode / LCD segment
output 35
General-purpose digital I/O / external clock input—USART1/UART or SPI mode, clock
output—USART1/SPI MODE / LCD segment output 36
General-purpose digital I/O / slave out/master in of USART1/SPI mode / LCD segment output
37
P4.4/SOMI1/S37
General-purpose digital I/O / slave in/master out of USART1/SPI mode / LCD segment output
38
P4.3/SIMO1/S38
General-purpose digital I/O / slave transmit enable—USART1/SPI mode / LCD segment output
39
P4.2/STE1/S39
COM0
52
53
54
55
56
O
COM0−3 are used for LCD backplanes.
P5.2/COM1
P5.3/COM2
P5.4/COM3
P5.5/R03
I/O
I/O
I/O
I/O
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
General-purpose digital I/O / Input port of lowest analog LCD level (V5)
General-purpose digital I/O / External reference voltage input for regulated LCD voltage / Input
port of third most positive analog LCD level (V4 or V3)
P5.6/LCDREF/R13
57
I/O
P5.7/R23
58
59
60
61
62
63
I/O
I
General-purpose digital I/O / Input port of second most positive analog LCD level (V2)
LCD Capacitor connection / Input/output port of most positive analog LCD level (V1)
Digital supply voltage, positive terminal.
LCDCAP/R33
DV
DV
CC2
SS2
Digital supply voltage, negative terminal.
P4.1/URXD1
P4.0/UTXD1
I/O
I/O
General-purpose digital I/O / receive data in—USART1/UART mode
General-purpose digital I/O / transmit data out—USART1/UART mode
General-purpose digital I/O / Timer_B7 CCR6. Capture: CCI6A/CCI6B input, compare: Out6
output
P3.7/TB6
P3.6/TB5
P3.5/TB4
64
65
66
I/O
I/O
I/O
General-purpose digital I/O / Timer_B7 CCR5. Capture: CCI5A/CCI5B input, compare: Out5
output
General-purpose digital I/O / Timer_B7 CCR4. Capture: CCI4A/CCI4B input, compare: Out4
output
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
MSP430FG461x Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
NO.
P3.4/TB3
67
I/O General-purpose digital I/O / Timer_B7 CCR3. Capture: CCI3A/CCI3B input, compare: Out3 output
General-purpose digital I/O / external clock input—USCI_B0/UART or SPI mode, clock
output—USCI_B0/SPI mode
P3.3/UCB0CLK
68
69
I/O
P3.2/UCB0SOMI/
UCB0SCL
General-purpose digital I/O / slave out/master in of USCI_B0/SPI mode /I2C clock USCI_B0/I2C
mode
I/O
P3.1/UCB0SIMO/
UCB0SDA
General-purpose digital I/O / slave in/master out of USCI_B0/SPI mode, I2C data − USCI_B0/I2C
mode
70
71
72
I/O
P3.0/UCB0STE
I/O General-purpose digital I/O / slave transmit enable—USCI_B0/SPI mode
P2.7/ADC12CLK/
DMAE0
I/O General-purpose digital I/O / conversion clock—12-bit ADC / DMA Channel 0 external trigger
P2.6/CAOUT
P2.5/UCA0RXD
P2.4/UCA0TXD
P2.3/TB2
73
74
75
76
77
78
79
80
81
I/O General-purpose digital I/O / Comparator_A output
I/O General-purpose digital I/O / receive data in—USCI_A0/UART or IrDA mode
I/O General-purpose digital I/O / transmit data out—USCI_A0/UART or IrDA mode
I/O General-purpose digital I/O / Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output
I/O General-purpose digital I/O / Timer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output
I/O General-purpose digital I/O / Timer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output
I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output
I/O General-purpose digital I/O / Comparator_A input
P2.2/TB1
P2.1/TB0
P2.0/TA2
P1.7/CA1
P1.6/CA0
I/O General-purpose digital I/O / Comparator_A input
General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by 1, 2, 4,
or 8)
P1.5/TACLK/ACLK
P1.4/TBCLK/SMCLK
P1.3/TBOUTH/SVSOUT
P1.2/TA1
82
83
84
85
86
I/O
I/O General-purpose digital I/O / input clock TBCLK—Timer_B7 / submain system clock SMCLK output
General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B7 TB0
to TB6 / SVS: output of SVS comparator
I/O
I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 output
General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
P1.1/TA0/MCLK
I/O
P1.0/TA0
XT2OUT
XT2IN
87
88
89
90
91
92
93
94
I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL transmit
O
I
Output terminal of crystal oscillator XT2
Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI
TDI/TCLK
TMS
I/O Test data output port. TDO/TDI data output or programming data input terminal
I
I
I
I
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
Test mode select. TMS is used as an input port for device programming and test.
Test clock. TCK is the clock input port for device programming and test.
Reset input or nonmaskable interrupt input port
TCK
RST/NMI
General-purpose digital I/O / analog input a0 − 12-bit ADC / OA0 input multiplexer on +terminal and
− terminal
P6.0/A0/OA0I0
P6.1/A1/OA0O
P6.2/A2/OA0I1
95
96
97
I/O
I/O General-purpose digital I/O / analog input a1 − 12-bit ADC / OA0 output
General-purpose digital I/O / analog input a2 − 12-bit ADC / OA0 input multiplexer on + terminal and
− terminal
I/O
Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, FLL+, comparator_A,
port 1
AV
SS
98
99
DV
Digital supply voltage, negative terminal.
SS1
Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, FLL+, comparator_A,
AV
100
CC
port 1; must not power up prior to DV /DV .
CC1 CC2
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
short-form description
CPU
Program Counter
Stack Pointer
PC/R0
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
R4
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
R5
R6
R7
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
R8
R9
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
R10
R11
The MSP430FG461x device family utilizes the
MSP430X CPU and is completely backwards
compatible with the MSP430 CPU. For a complete
description of the MSP430X CPU, refer to the
MSP430x4xx Family User’s Guide.
R12
R13
R14
R15
instruction set
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the
expanded address range. Each instruction can
operate on word and byte data. Table 1 shows
examples of the three types of instruction formats;
the address modes are listed in Table 2.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
Table 1. Instruction Word Formats
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
e.g. ADD R4,R5
R4 + R5 −−−> R5
e.g. CALL
e.g. JNE
R8
PC −−>(TOS), R8−−> PC
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
Register
S
D
SYNTAX
MOV Rs,Rd
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
OPERATION
F
F
F
F
F
F
F
F
F
R10 —> R11
Indexed
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV & MEM, & TCDAT
MOV @Rn,Y(Rm)
M(2+R5)—> M(6+R6)
M(EDE) —> M(TONI)
M(MEM) —> M(TCDAT)
M(R10) —> M(Tab+R6)
Symbolic (PC relative)
Absolute
Indirect
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
Indirect
autoincrement
M(R10) —> R11
R10 + 2—> R10
F
F
MOV @Rn+,Rm
Immediate
MOV #X,TONI
#45 —> M(TONI)
NOTE: S = source
D = destination
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D
D
Active mode AM;
All clocks are active
Low-power mode 0 (LPM0);
−
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
FLL+ Loop control remains active
D
D
Low-power mode 1 (LPM1);
−
CPU is disabled
FLL+ Loop control is disabled
ACLK and SMCLK remain active. MCLK is disabled
Low-power mode 2 (LPM2);
−
CPU is disabled
MCLK and FLL+ loop control and DCOCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D
D
Low-power mode 3 (LPM3);
−
CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
Low-power mode 4 (LPM4);
−
CPU is disabled
ACLK is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
interrupt vector addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh − 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 3. Interrupt Sources, Flags, and Vectors of MSP430FG461x Configurations
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
PRIORITY
Power-Up
External Reset
Watchdog
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh
31, highest
Flash Memory
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
30
Timer_B7
TBCCR0 CCIFG0 (see Note 2)
Maskable
0FFFAh
0FFF8h
29
28
TBCCR1 CCIFG1 ... TBCCR6 CCIFG6,
TBIFG (see Notes 1 and 2)
Timer_B7
Maskable
Comparator_A
Watchdog Timer+
USCI_A0/USCI_B0 Receive
USCI_A0/USCI_B0 Transmit
ADC12
CAIFG
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
0FFECh
27
26
25
24
23
22
WDTIFG
UCA0RXIFG, UCB0RXIFG (see Notes 1)
UCA0TXIFG, UCB0TXIFG (see Notes 1)
ADC12IFG (see Notes 1 and 2)
TACCR0 CCIFG0 (see Note 2)
Timer_A3
TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (see Notes 1 and 2)
Timer_A3
Maskable
0FFEAh
21
I/O Port P1 (Eight Flags)
USART1 receive
USART1 transmit
I/O Port P2 (Eight Flags)
Basic Timer1/RTC
DMA
P1IFG.0 to P1IFG.7 (see Notes 1 and 2)
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
0FFE8h
0FFE6h
0FFE4h
0FFE2h
0FFE0h
0FFDEh
20
19
18
17
16
15
URXIFG1
UTXIFG1
P2IFG.0 to P2IFG.7 (see Notes 1 and 2)
BTIFG
DMA0IFG, DMA1IFG, DMA2IFG (see Notes 1
and 2)
DAC12
DAC12.0IFG, DAC12.1IFG (see Notes 1 and 2)
Maskable
0FFDCh
0FFDAh
...
14
13
...
Reserved
Reserved (see Note 4)
0FFC0h
0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh).
.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot
disable it.
4. The interrupt vectors at addresses 0FFDAh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
special function registers
The MSP430 special function registers(SFR) are located in the lowest address space, and are organized as
byte mode registers. SFRs should be accessed with byte instructions.
interrupt enable 1 and 2
7
6
5
4
3
2
1
0
Address
0h
ACCVIE
NMIIE
OFIE
WDTIE
rw–0
rw–0
rw–0
rw–0
WDTIE
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as a general-purpose timer.
OFIE
Oscillator-fault-interrupt enable
Nonmaskable-interrupt enable
Flash access violation interrupt enable
NMIIE
ACCVIE
7
6
5
4
3
2
1
0
Address
01h
BTIE
UTXIE1
URXIE1
UCB0TXIE
UCB0RXIE
UCA0TXIE UCA0RXIE
rw–0 rw–0
rw–0
rw–0
rw–0
rw–0
rw–0
UCA0RXIE USCI_A0 receive-interrupt enable
UCA0TXIE USCI_A0 transmit-interrupt enable
UCB0RXIE USCI_B0 receive-interrupt enable
UCB0TXIE USCI_B0 transmit-interrupt enable
URXIE1
UTXIE1
BTIE
USART1 UART and SPI receive-interrupt enable
USART1 UART and SPI transmit-interrupt enable
Basic timer interrupt enable
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢒ
ꢀ
ꢋ
ꢌ
ꢍ
ꢎ
ꢁ
ꢋ
ꢇ
ꢏ
ꢐ
ꢑ
ꢀ
ꢋ
ꢒ
ꢓ
ꢔ
ꢔ
ꢏ
ꢕ
ꢓ
ꢔ
ꢑ
ꢑ
ꢍ
ꢓ
SLAS508 − APRIL 2006
interrupt flag register 1 and 2
7
6
5
4
3
2
1
0
Address
02h
NMIIFG
OFIFG
rw–1
WDTIFG
rw–0
rw–(0)
WDTIFG:
Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on V power-on or a reset condition at the RST/NMI pin in reset mode
CC
OFIFG:
Flag set on oscillator fault
Set via RST/NMI pin
NMIIFG:
7
6
5
4
3
2
1
0
Address
03h
UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG
rw–0 rw–0
UTXIFG1
URXIFG1
BTIFG
rw–0
rw–0
rw–0
rw–1
rw–0
UCA0RXIFG USCI_A0 receive-interrupt flag
UCA0TXIFG USCI_A0 transmit-interrupt flag
UCB0RXIFG USCI_B0 receive-interrupt flag
UCB0TXIFG
URXIFG0:
UTXIFG0:
BTIFG:
USCI_B0 transmit-interrupt flag
USART1: UART and SPI receive flag
USART1: UART and SPI transmit flag
Basic timer flag
module enable registers 1 and 2
7
6
5
4
4
3
3
2
2
1
1
0
0
Address
04h
7
6
5
Address
05h
UTXE1
URXE1
USPIE1
rw–0
rw–0
URXE1:
USART1: UART mode receive enable
USART1: UART mode transmit enable
UTXE1:
USPIE1:
USART1: SPI mode transmit and receive enable
Legend
rw:
Bit can be read and written.
rw-0,1:
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
rw-(0,1):
SFR bit is not present in device
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
memory organization
MSP430FG4616
MSP430FG4617
MSP430FG4618
MSP430FG4619
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
92KB
0FFFFh − 0FFC0h
018FFFh − 002100h
92KB
0FFFFh − 0FFC0h
019FFFh − 003100h
116KB
0FFFFh − 0FFC0h
01FFFFh − 003100h
120KB
0FFFFh − 0FFC0h
01FFFFh − 002100h
RAM (Total)
Size
Size
Size
4KB
8KB
8KB
4KB
020FFh − 01100h
030FFh − 01100h
030FFh − 01100h
020FFh − 01100h
Extended
2KB
6KB
6KB
2KB
020FFh − 01900h
030FFh − 01900h
030FFh − 01900h
020FFh − 01900h
Mirrored
2KB
2KB
2KB
2KB
018FFh − 01100h
018FFh − 01100h
018FFh − 01100h
018FFh − 01100h
Information memory
Boot memory
Size
Flash
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Size
1KB
1KB
1KB
1KB
ROM
0FFFh − 0C00h
0FFFh − 0C00h
0FFFh − 0C00h
0FFFh − 0C00h
RAM
Size
2KB
2KB
2KB
2KB
(mirrored at
018FFh − 01100h)
09FFh − 0200h
09FFh − 0200h
09FFh − 0200h
09FFh − 0200h
Peripherals
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. A bootstrap loader
security key is provided at address 0FFBEh to disable the BSL completely or to disable the erasure of the flash
if an invalid password is supplied. For complete description of the features of the BSL and its implementation,
see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089.
BSLKEY
00000h
Description
Erasure of flash disabled if an invalid password is supplied
BSL disabled
0AA55h
any other value
BSL enabled
BSL Function
PZ Package Pins
87 − P1.0
Data Transmit
Data Receive
86 − P1.1
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D
Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D
D
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A and B can be erased individually, or as a group with segments 0−n.
Segments A and B are also called information memory.
D
New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide.
DMA controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to
or from a peripheral.
oscillator and system clock
The clock system in the MSP430FG461x family of devices is supported by the FLL+ module that includes
support for a 32768 Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high
frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system
cost and low-power consumption. The FLL+ features digital frequency locked loop (FLL) hardware which in
conjunction with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch
crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The
FLL+ module provides the following clock signals:
D
D
D
D
Auxiliary clock (ACLK), sourced from a 32768 Hz watch crystal or a high frequency crystal.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on
and power-off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, V
may not
CC
have ramped to V
reaches V
at that time. The user must insure the default FLL+ settings are not changed until V
CC(min)
CC
. If desired, the SVS circuit can be used to determine when V
reaches V
.
CC(min)
CC
CC(min)
digital I/O
There are ten 8-bit I/O ports implemented—ports P1 through P10:
D
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Ports P7/P8 and P9/P10 can be accessed word−wise as ports PA and PB respectively.
Basic Timer1 and Real−Time Clock
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 is extended to provide an integrated Real−Time
Clock (RTC). An internal calendar compensates for months with less than 31 days and includes leap year
correction.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
LCD_A drive with regulated charge pump
The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump.
Furthermore it is possible to control the level of the LCD voltage and thus contrast by software.
WDT+ watchdog timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
USCI
The universal serial communication interface (USCI) modules are used for serial data communication. The
USCI module supports synchronous communication protocols like SPI (3 or 4 pin), I2C and asynchronous
communication protocols like UART, enhanced UART with automatic baudrate detection, and IrDA.
The USCI_A0 module provides support for SPI (3 or 4 pin), UART, enhanced UART and IrDA.
The USCI_B0 module provides support for SPI (3 or 4 pin) and I2C.
USART1
The hardware universal synchronous/asynchronous receive transmit (USART) peripheral module is used for
serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART
communication protocols, using double-buffered transmit and receive channels.
hardware multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16 16,
16 8, 8 16, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number
Output Pin Number
PZ
Device Input
Signal
Module Input
Name
Module
Block
Module Output
Signal
PZ
82- P1.5
TACLK
ACLK
SMCLK
TACLK
TA0
TACLK
ACLK
Timer
CCR0
CCR1
CCR2
NA
TA0
TA1
TA2
SMCLK
INCLK
CCI0A
CCI0B
GND
82 - P1.5
87 - P1.0
86 - P1.1
87 - P1.0
TA0
DV
DV
SS
V
CC
CC
85 - P1.2
79 - P2.0
TA1
CAOUT (internal)
CCI1A
CCI1B
GND
85 - P1.2
ADC12 (internal)
DV
DV
SS
V
CC
CC
TA2
ACLK (internal)
CCI2A
CCI2B
GND
79 - P2.0
DV
DV
SS
V
CC
CC
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
timer_B7
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_B7 Signal Connections
Input Pin Number
PZ
Output Pin Number
PZ
Device Input
Signal
Module Input
Name
Module
Block
Module Output
Signal
83 - P1.4
TBCLK
ACLK
SMCLK
TBCLK
TB0
TBCLK
ACLK
Timer
CCR0
CCR1
CCR2
CCR3
CCR4
CCR5
CCR6
NA
SMCLK
INCLK
CCI0A
CCI0B
GND
83 - P1.4
78 - P2.1
78 - P2.1
78 - P2.1
TB0
ADC12 (internal)
TB0
TB1
TB2
TB3
TB4
TB5
TB6
DV
DV
SS
V
CC
CC
77 - P2.2
77 - P2.2
TB1
TB1
CCI1A
CCI1B
GND
77 - P2.2
ADC12 (internal)
DV
SS
DV
V
CC
CC
76 - P2.3
76 - P2.3
TB2
TB2
CCI2A
CCI2B
GND
76 - P2.3
67 - P3.4
66 - P3.5
65 - P3.6
64 - P3.7
DV
SS
DV
V
CC
CC
67 - P3.4
67 - P3.4
TB3
TB3
CCI3A
CCI3B
GND
DV
SS
DV
V
CC
CC
66 - P3.5
66 - P3.5
TB4
TB4
CCI4A
CCI4B
GND
DV
SS
DV
V
CC
CC
65 - P3.6
65 - P3.6
TB5
TB5
CCI5A
CCI5B
GND
DV
SS
DV
V
CC
CC
64 - P3.7
TB6
ACLK (internal)
CCI6A
CCI6B
GND
DV
SS
CC
DV
V
CC
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
ADC12
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without
any CPU intervention.
DAC12
The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode,
and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may
be grouped together for synchronous operation.
OA
The MSP430FG461x has three configurable low-current general-purpose operational amplifiers. Each OA
input and output terminal is software-selectable and offer a flexible choice of connections for various
applications. The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital
conversion.
OA Signal Connections
Input Pin
Number
Output Pin
Number
Module
Output
Signal
Device
Output
Signal
Device Input
Signal
Module Input
Name
Module
Block
PZ
PZ
95 - P6.0
97 - P6.2
OA0I0
OA0I1
OA0I0
OA0I1
OA0O
OA0O
96 - P6.1
ADC12 (internal)
DAC12_0OUT
(internal)
DAC12_0OUT
OA0
OA1
OA2
OA0OUT
OA1OUT
OA2OUT
DAC12_1OUT
(internal)
DAC12_1OUT
3 - P6.4
13 - P5.0
OA1I0
OA1I1
OA1I0
OA1I1
OA1O
OA1O
2 - P6.3
13- P5.0
DAC12_0OUT
(internal)
DAC12_0OUT
OA1O
ADC12 (internal)
DAC12_1OUT
(internal)
DAC12_1OUT
5 - P6.6
OA2I0
OA2I1
OA2I0
OA2I1
OA2O
OA2O
4 - P6.5
14- P10.7
14- P10.7
DAC12_0OUT
(internal)
DAC12_0OUT
OA2O
ADC12 (internal)
DAC12_1OUT
(internal)
DAC12_1OUT
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog timer control
Watchdog+
Timer_B7
WDTCTL
TBCCR6
TBCCR5
TBCCR4
TBCCR3
TBCCR2
TBCCR1
TBCCR0
TBR
0120h
019Eh
019Ch
019Ah
0198h
0196h
0194h
0192h
0190h
018Eh
018Ch
018Ah
0188h
0186h
0184h
0182h
0180h
011Eh
0176h
0174h
0172h
0170h
0166h
0164h
0162h
0160h
012Eh
013Eh
013Ch
013Ah
0138h
0136h
0134h
0132h
0130h
012Ch
012Ah
0128h
Capture/compare register 6
Capture/compare register 5
Capture/compare register 4
Capture/compare register 3
Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_B register
Capture/compare control 6
Capture/compare control 5
Capture/compare control 4
Capture/compare control 3
Capture/compare control 2
Capture/compare control 1
Capture/compare control 0
Timer_B control
TBCCTL6
TBCCTL5
TBCCTL4
TBCCTL3
TBCCTL2
TBCCTL1
TBCCTL0
TBCTL
Timer_B interrupt vector
Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_A register
TBIV
Timer_A3
TACCR2
TACCR1
TACCR0
TAR
Capture/compare control 2
Capture/compare control 1
Capture/compare control 0
Timer_A control
TACCTL2
TACCTL1
TACCTL0
TACTL
Timer_A interrupt vector
Sum extend
TAIV
Hardware
Multiplier
SUMEXT
RESHI
Result high word
Result low word
RESLO
OP2
Second operand
Multiply signed + accumulate/operand1
Multiply + accumulate/operand1
Multiply signed/operand1
Multiply unsigned/operand1
Flash control 3
MACS
MAC
MPYS
MPY
Flash
FCTL3
Flash control 2
FCTL2
Flash control 1
FCTL1
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
peripheral file map (continued)
PERIPHERALS WITH WORD ACCESS (CONTINUED)
DMA
DMA module control 0
DMACTL0
0122h
0124h
0126h
01D0h
01D2h
01D6h
01DAh
01DCh
01DEh
01E2h
01E6h
01E8h
01EAh
01EEh
01F2h
DMA module control 1
DMACTL1
DMAIV
DMA interrupt vector
DMA Channel 0
DMA channel 0 control
DMA0CTL
DMA0SA
DMA0DA
DMA0SZ
DMA1CTL
DMA1SA
DMA1DA
DMA1SZ
DMA2CTL
DMA2SA
DMA2DA
DMA2SZ
DMA channel 0 source address
DMA channel 0 destination address
DMA channel 0 transfer size
DMA channel 1 control
DMA Channel 1
DMA Channel 2
DMA channel 1 source address
DMA channel 1 destination address
DMA channel 1 transfer size
DMA channel 2 control
DMA channel 2 source address
DMA channel 2 destination address
DMA channel 2 transfer size
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
peripheral file map (continued)
PERIPHERALS WITH WORD ACCESS (CONTINUED)
ADC12
Conversion memory 15
Conversion memory 14
Conversion memory 13
Conversion memory 12
Conversion memory 11
Conversion memory 10
Conversion memory 9
Conversion memory 8
Conversion memory 7
Conversion memory 6
Conversion memory 5
Conversion memory 4
Conversion memory 3
Conversion memory 2
Conversion memory 1
Conversion memory 0
Interrupt-vector-word register
Inerrupt-enable register
Inerrupt-flag register
Control register 1
ADC12MEM15 015Eh
ADC12MEM14 015Ch
ADC12MEM13 015Ah
ADC12MEM12 0158h
ADC12MEM11 0156h
ADC12MEM10 0154h
See also Peripherals
with Byte Access
ADC12MEM9
ADC12MEM8
ADC12MEM7
ADC12MEM6
ADC12MEM5
ADC12MEM4
ADC12MEM3
ADC12MEM2
ADC12MEM1
ADC12MEM0
ADC12IV
0152h
0150h
014Eh
014Ch
014Ah
0148h
0146h
0144h
0142h
0140h
01A8h
01A6h
01A4h
01A2h
01A0h
ADC12IE
ADC12IFG
ADC12CTL1
ADC12CTL0
DAC12_1DAT
DAC12_1CTL
DAC12_0DAT
DAC12_0CTL
PASEL
Control register 0
DAC12
Port PA
Port PB
DAC12_1 data
01CAh
01C2h
01C8h
01C0h
03Eh
03Ch
03Ah
038h
DAC12_1 control
DAC12_0 data
DAC12_0 control
Port PA selection
Port PA direction
PADIR
Port PA output
PAOUT
Port PA input
PAIN
Port PB selection
PBSEL
00Eh
00Ch
00Ah
008h
Port PB direction
PBDIR
Port PB output
PBOUT
Port PB input
PBIN
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
OA2
Operational Amplifier 2 control register 1
Operational Amplifier 2 control register 0
OA2CTL1
OA2CTL0
0C5h
0C4h
OA1
Operational Amplifier 1 control register 1
Operational Amplifier 1 control register 0
OA1CTL1
OA1CTL0
0C3h
0C2h
OA0
Operational Amplifier 0 control register 1
Operational Amplifier 0 control register 0
OA0CTL1
OA0CTL0
0C1h
0C0h
LCD_A
LCD Voltage Control 1
LCD Voltage Control 0
LCD Voltage Port Control 1
LCD Voltage Port Control 0
LCD memory 20
:
LCDAVCTL1
LCDAVCTL0
LCDAPCTL1
LCDAPCTL0
LCDM20
:
0AFh
0AEh
0ADh
0ACh
0A4h
:
LCD memory 16
LCD memory 15
:
LCDM16
LCDM15
:
0A0h
09Fh
:
LCD memory 1
LCDM1
091h
090h
LCD control and mode
LCDCTL
ADC12
ADC memory-control register 15
ADC memory-control register 14
ADC memory-control register 13
ADC memory-control register 12
ADC memory-control register 11
ADC memory-control register 10
ADC memory-control register 9
ADC memory-control register 8
ADC memory-control register 7
ADC memory-control register 6
ADC memory-control register 5
ADC memory-control register 4
ADC memory-control register 3
ADC memory-control register 2
ADC memory-control register 1
ADC memory-control register 0
Transmit buffer
ADC12MCTL15 08Fh
ADC12MCTL14 08Eh
ADC12MCTL13 08Dh
ADC12MCTL12 08Ch
ADC12MCTL11 08Bh
ADC12MCTL10 08Ah
(Memory control
registers require byte
access)
ADC12MCTL9
ADC12MCTL8
ADC12MCTL7
ADC12MCTL6
ADC12MCTL5
ADC12MCTL4
ADC12MCTL3
ADC12MCTL2
ADC12MCTL1
ADC12MCTL0
U1TXBUF
089h
088h
087h
086h
085h
084h
083h
082h
081h
080h
07Fh
07Eh
07Dh
07Ch
07Bh
07Ah
079h
078h
USART1
Receive buffer
U1RXBUF
Baud rate
U1BR1
Baud rate
U1BR0
Modulation control
U1MCTL
Receive control
U1RCTL
Transmit control
U1TCTL
USART control
U1CTL
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
USCI
USCI I2C Slave Address
USCI I2C Own Address
USCI Synchronous Transmit Buffer
USCI Synchronous Receive Buffer
USCI Synchronous Status
USCI Synchronous Bit Rate 1
USCI Synchronous Bit Rate 0
USCI Synchronous Control 1
USCI Synchronous Control 0
USCI Transmit Buffer
UCBSA
UCBOA
011Ah
0118h
06Fh
06Eh
06Dh
06Bh
06Ah
069h
068h
067h
066h
065h
064h
063h
062h
061h
060h
05Fh
05Eh
05Dh
05Bh
05Ah
059h
056h
054h
053h
052h
051h
050h
04Fh
04Eh
04Dh
04Ch
047h
046h
045h
UCBTXBUF
UCBRXBUF
UCBSTAT
UCBBR1
UCBBR0
UCBCTL1
UCBCTL0
UCATXBUF
UCARXBUF
UCASTAT
UCAMCTL
UCABR1
USCI Receive Buffer
USCI Status
USCI Modulation Control
USCI Baud Rate 1
USCI Baud Rate 0
UCABR0
USCI Control 1
UCACTL1
UCACTL0
USCI Control 0
USCI IrDA Receive Control
USCI IrDA Transmit Control
USCI LIN Control
UCAIRRCTL
UCAIRTCTL
UCAABCTL
CAPD
Comparator_A
Comparator_A port disable
Comparator_A control 2
Comparator_A control 1
CACTL2
CACTL1
BrownOUT, SVS
FLL+Clock
SVS control register (Reset by brownout signal) SVSCTL
FLL+ Control 1
FLL_CTL1
FLL_CTL0
SCFQCTL
SCFI1
FLL+ Control 0
System clock frequency control
System clock frequency integrator
System clock frequency integrator
Real Time Clock Year High Byte
Real Time Clock Year Low Byte
Real Time Clock Month
Real Time Clock Day of Month
Basic Timer1 Counter 2
Basic Timer1 Counter 1
Real Time Counter 4
SCFI0
RTC (Basic Timer 1)
RTCYEARH
RTCYEARL
RTCMON
RTCDAY
BTCNT2
BTCNT1
RTCNT4
(RTCDOW)
RTCNT3
(RTCHOUR)
RTCNT2
(RTCMIN)
RTCNT1
(RTCSEC)
RTCCTL
BTCTL
(Real Time Clock Day of Week)
Real Time Counter 3
044h
043h
042h
(Real Time Clock Hour)
Real Time Counter 2
(Real Time Clock Minute)
Real Time Counter 1
(Real Time Clock Second)
Real Time Clock Control
Basic Timer1 Control
041h
040h
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P10
Port P9
Port P8
Port P7
Port P6
Port P5
Port P4
Port P3
Port P2
Port P10 selection
Port P10 direction
Port P10 output
Port P10 input
P10SEL
00Fh
00Dh
00Bh
009h
00Eh
00Ch
00Ah
008h
03Fh
03Dh
03Bh
039h
03Eh
03Ch
03Ah
038h
037h
036h
035h
034h
033h
032h
031h
030h
01Fh
01Eh
01Dh
01Ch
01Bh
01Ah
019h
018h
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
026h
025h
024h
023h
022h
021h
020h
P10DIR
P10OUT
P10IN
P9SEL
P9DIR
P9OUT
P9IN
Port P9 selection
Port P9 direction
Port P9 output
Port P9 input
Port P8 selection
Port P8 direction
Port P8 output
P8SEL
P8DIR
P8OUT
P8IN
Port P8 input
Port P7 selection
Port P7 direction
Port P7 output
P7SEL
P7DIR
P7OUT
P7IN
Port P7 input
Port P6 selection
Port P6 direction
Port P6 output
P6SEL
P6DIR
P6OUT
P6IN
Port P6 input
Port P5 selection
Port P5 direction
Port P5 output
P5SEL
P5DIR
P5OUT
P5IN
Port P5 input
Port P4 selection
Port P4 direction
Port P4 output
P4SEL
P4DIR
P4OUT
P4IN
Port P4 input
Port P3 selection
Port P3 direction
Port P3 output
P3SEL
P3DIR
P3OUT
P3IN
Port P3 input
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt-edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
Port P2 input
Port P1
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt-edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
Port P1 input
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Special functions
SFR module enable 2
SFR module enable 1
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
ME2
ME1
005h
004h
003h
002h
001h
000h
IFG2
IFG1
IE2
IE1
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Voltage applied at V
to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
CC
SS
Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA
+ 0.3 V
CC
Storage temperature, T : (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
stg
(programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to V
The JTAG fuse-blow voltage, V , is allowed to exceed the absolute maximum rating. The voltage is applied
SS.
FB
to the TDI/TCLK pin when blowing the JTAG fuse.
recommended operating conditions
MIN
NOM
MAX UNITS
Supply voltage during program execution,
1.8
3.6
3.6
V
V
V
CC
(AV
CC
= DV
CC1/2
= V )
CC
Supply voltage during flash memory programming,
(AV = DV = V
2.7
2
V
CC
)
CC CC1/2 CC
Supply voltage during program execution,
SVS enabled and PORON = 1 (see Note 1),
3.6
V
V
(AV
= DV
= V
)
CC
CC
CC1/2
CC
= DV
Supply voltage, V
SS
(AV
= V
)
0
0
V
SS
SS1/2
SS
Operating free-air temperature range, T
−40
85
°C
A
LF selected,
XTS_FLL=0
Watch crystal
Ceramic resonator
Crystal
32.768
kHz
kHz
kHz
XT1 selected,
XTS_FLL=1
LFXT1 crystal frequency, f
(see Note 2)
(LFXT1)
450
8000
8000
XT1 selected,
XTS_FLL=1
1000
Ceramic resonator
Crystal
450
1000
DC
8000
8000
3.0
XT2 crystal frequency, f
(XT2)
kHz
V
CC
V
CC
V
CC
= 1.8 V
= 2.0 V
= 3.6 V
MHz
MHz
DC
4.6
Processor frequency (signal MCLK), f
(System)
DC
8.0
NOTES: 1. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply
voltage. POR is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the SVS
circuitry.
2. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
f
(MHz)
System
8.0 MHz
Supply voltage range,
MSP430FG461x, during
program execution
Supply voltage range, MSP430FG461x,
during flash memory programming
4.6 MHz
3.0 MHz
1.8 2.0
2.7
3
3.6
Supply Voltage − V
Figure 1. Frequency vs Supply Voltage, typical characteristic
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AV
+ DV
excluding external current
CC
CC
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
Active mode, (see Note 1 and Note 4)
V
V
= 2.2 V
= 3 V
350
450
CC
f
= f = 1 MHz,
(MCLK) (SMCLK)
I
I
I
T
= −40°C to 85°C
= −40°C to 85°C
= −40°C to 85°C
µA
(AM)
A
f
= 32,768 Hz
(ACLK)
550
700
CC
XTS=0, SELM=(0,1)
V
V
= 2.2 V
= 3 V
55
85
70
Low-power mode, (LPM0)
(see Note 1 and Note 4)
CC
T
A
µA
µA
(LPM0)
(LPM2)
110
CC
Low-power mode, (LPM2),
V
= 2.2 V
= 3 V
13
18
22
30
CC
CC
f
f
= f
= 0 MHz,
(MCLK)
(ACLK)
(SMCLK)
= 32,768 Hz, SCG0 = 0 (see Note 2 and
T
A
V
Note 4)
T
= −40°C
= 25°C
= 60°C
= 85°C
= −40°C
= 25°C
= 60°C
= 85°C
= −40°C
= 25°C
= 60°C
= 85°C
= −40°C
= 25°C
= 60°C
= 85°C
= −40°C
= 25°C
= 60°C
= 85°C
= −40°C
= 25°C
= 60°C
= 85°C
1.0
1.1
2.0
7.0
1.8
1.6
2.5
8.5
2.5
2.5
3.0
8.0
2.9
2.9
4.0
10.0
0.1
0.3
1.7
7.0
0.1
0.4
2.0
8.0
2.0
2.0
A
Low-power mode, (LPM3)
T
A
f
= f
= 0 MHz,
= 32,768 Hz, SCG0 = 1
(MCLK) (SMCLK)
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.2 V
µA
µA
µA
µA
µA
µA
T
A
5.0
f
(ACLK)
Basic Timer1 enabled, ACLK selected
LCD_A enabled, LCDCPEN = 0;
T
A
15.0
2.8
I
I
I
(LPM3)
(LPM3)
(LPM4)
T
A
(static mode; f /32)
= f
LCD (ACLK)
T
A
2.7
(see Note 2 and Note 3 and Note 4)
= 3 V
T
A
7.0
T
A
21.0
3.5
T
A
Low-power mode, (LPM3)
T
A
3.5
f
= f
= 0 MHz,
= 32,768 Hz, SCG0 = 1
(MCLK) (SMCLK)
= 2.2 V
T
A
6.0
f
(ACLK)
Basic Timer1 enabled, ACLK selected
LCD_A enabled, LCDCPEN = 0;
T
A
16.0
4.0
T
A
(4−mux mode; f /32)
= f
(see Note 2 and Note 3 and Note 4)
LCD (ACLK)
T
A
4.0
= 3 V
T
A
8.0
T
A
22.0
0.5
T
A
T
A
0.7
= 2.2 V
T
A
5.0
Low-power mode, (LPM4)
T
A
15.0
0.8
f
f
= 0 MHz, f = 0 MHz,
(SMCLK)
(MCLK)
(ACLK)
= 0 Hz, SCG0 = 1
T
A
(see Note 2 and Note 4)
T
A
0.9
= 3 V
T
A
7.0
T
A
21.0
NOTES: 1. Timer_B is clocked by f
= f
= 1 MHz. All inputs are tied to 0 V or to V . Outputs do not source or sink any current.
(DCOCLK) (DCO)
CC
2. All inputs are tied to 0 V or to V . Outputs do not source or sink any current.
CC
3. The LPM3 currents are characterized with a Micro Crystal CC4V−T1A (9 pF) crystal and OSCCAPx = 1h.
4. Current for brownout included.
Current consumption of active mode versus system frequency, F-version:
I
= I
[1 MHz] × f
[MHz]
(AM)
(AM)
(System)
Current consumption of active mode versus supply voltage, F-version:
= I + 200 µA/V × (V – 3 V)
I
(AM)
(AM) [3 V]
CC
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SCHMITT-trigger inputs − Ports P1 to P10; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER
TEST CONDITIONS
MIN
1.1
1.5
0.4
0.9
0.3
0.5
TYP
MAX
1.55
1.98
0.9
UNIT
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.2 V
= 3 V
V
IT+
V
IT−
V
hys
Positive-going input threshold voltage
V
= 2.2 V
= 3 V
Negative-going input threshold voltage
V
V
1.3
= 2.2 V
= 3 V
1.1
Input voltage hysteresis (V
IT+
− V )
IT−
1
inputs Px.x, TAx, TBx
PARAMETER
TEST CONDITIONS
V
MIN
62
TYP
MAX
UNIT
CC
2.2 V
3 V
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag, (see Note 1)
t
t
External interrupt timing
ns
(int)
50
TA0, TA1, TA2
2.2 V
3 V
62
Timer_A, Timer_B capture
timing
ns
(cap)
TB0, TB1, TB2, TB3, TB4, TB5, TB6
50
Timer_A, Timer_B clock
frequency externally applied
to pin
f
f
2.2 V
3 V
8
(TAext)
TACLK, TBCLK, INCLK: t = t
(H) (L)
MHz
10
(TBext)
f
f
2.2 V
3 V
8
(TAint)
Timer_A, Timer_B clock
frequency
SMCLK or ACLK signal selected
MHz
10
(TBint)
NOTES: 1. The external signal sets the interrupt flag every time the minimum t
parameters are met. It may be set even with trigger signals
(int)
shorter than t
.
(int)
leakage current − Ports P1 to P10 (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Leakage
current
V
(see Note 2)
(Px.y)
(1 ≤ x ≤ 10, 0 ≤ y ≤ 7)
I
Port Px
V
CC
= 2.2 V/3 V
50
nA
lkg(Px.y)
NOTES: 1. The leakage current is measured with V
2. The port pin must be selected as input.
or V
CC
applied to the corresponding pin(s), unless otherwise noted.
SS
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1 to P10
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
I
I
I
I
I
I
I
= −1.5 mA,
= −6 mA,
= −1.5 mA,
= −6 mA,
= 1.5 mA,
= 6 mA,
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.2 V,
= 2.2 V,
= 3 V,
See Note 1
See Note 2
See Note 1
See Note 2
See Note 1
See Note 2
See Note 1
See Note 2
V
−0.25
V
V
V
V
OH(max)
OH(max)
OH(max)
OH(max)
OL(max)
OL(max)
OL(max)
OL(max)
CC
CC
CC
CC
CC
V
−0.6
CC
−0.25
V
High-level output voltage
V
OH
OL
V
CC
= 3 V,
V
−0.6
CC
= 2.2 V,
= 2.2 V,
= 3 V,
V
V
+0.25
SS
SS
SS
SS
SS
V
V
V
V
+0.6
SS
V
Low-level output voltage
V
= 1.5 mA,
= 6 mA,
V
SS
+0.25
= 3 V,
V
+0.6
SS
NOTES: 1. The maximum total current, I
specified voltage drop.
and I
for all outputs combined, should not exceed 12 mA to satisfy the maximum
OH(max)
OL(max),
OL(max),
2. The maximum total current, I
specified voltage drop.
and I
for all outputs combined, should not exceed 48 mA to satisfy the maximum
OH(max)
output frequency
PARAMETER
TEST CONDITIONS
MIN
DC
DC
TYP
MAX
10
UNIT
MHz
MHz
V
= 2.2 V
= 3 V
C
I
= 20 pF,
CC
CC
L
L
f
(1 ≤ x ≤ 10, 0 ≤ y ≤ 7)
(Px.y)
=
1.5 mA
V
12
f
f
f
P1.1/TA0/MCLK,
(MCLK)
(SMCLK)
(ACLK)
V
= 2.2 V
= 3 V
10
MHz
MHz
CC
CC
P1.4/TBCLK/SMCLK,
P1.5/TACLK/ACLK
C
= 20 pF
L
V
DC
40%
30%
12
60%
70%
f
f
f
f
= f
= f
(ACLK) (LFXT1) (XT1)
P1.5/TACLK/ACLK,
C
= f
= f
= 20 pF
= 2.2 V / 3 V
(ACLK) (LFXT1) (LF)
L
V
CC
= f
50%
50%
(ACLK) (LFXT1)
= f
40%
60%
(MCLK) (XT1)
= f
P1.1/TA0/MCLK,
t
Duty cycle of output frequency
C
V
= 20 pF,
= 2.2 V / 3 V
(Xdc)
50%−
15 ns
50%+
15 ns
L
f
f
f
(MCLK) (DCOCLK)
CC
= f
40%
60%
(SMCLK) (XT2)
P1.4/TBCLK/SMCLK,
C
V
= 20 pF,
= 2.2 V / 3 V
50%−
15 ns
50%+
15 ns
L
= f
50%
(SMCLK) (DCOCLK)
CC
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics − outputs
TYPICAL LOW-LEVEL OUTPUT CURRENT
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
25.0
20.0
15.0
10.0
5.0
50.0
40.0
30.0
20.0
10.0
0.0
V
CC
P2.0
= 2.2 V
T
= 25°C
V
CC
P2.0
= 3 V
A
T
= 25°C
= 85°C
A
T
= 85°C
A
T
A
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OL
− Low-Level Output Voltage − V
V
OL
− Low-Level Output Voltage − V
Figure 2
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
0.0
−5.0
0.0
−10.0
−20.0
−30.0
−40.0
−50.0
V
= 2.2 V
CC
P2.0
V
= 3 V
CC
P2.0
−10.0
−15.0
−20.0
−25.0
T
= 85°C
A
T
A
= 85°C
T
A
= 25°C
T
= 25°C
A
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OH
− High-Level Output Voltage − V
V
OH
− High-Level Output Voltage − V
Figure 4
Figure 5
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
wake-up LPM3
PARAMETER
TEST CONDITIONS
f = 1 MHz
MIN
TYP
MAX
UNIT
6
6
6
f = 2 MHz
f = 3 MHz
t
Delay time
V
CC
= 2.2 V/3 V
µs
d(LPM3)
RAM
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VRAMh
CPU halted (see Note 1)
1.6
V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
LCD_A
PARAMETER
TEST CONDITIONS
Charge pump enabled
MIN
TYP
MAX
UNIT
V
CC
Supply Voltage Range (see Note
2)
V
2.2
3.6
V
CC(LCD)
(LCDCPEN = 1; VLCDx > 0000)
V
=3V; LCDCPEN = 1;
LCD(typ)
VLCDx= 1000; all segments on.
/32
f
f
I
Supply Current (see Note 2 )
2.2 V
3
µA
µF
LCD = ACLK
no LCD connected (see Note 4)
= 25°C
CC(LCD)
T
A
Capacitor on LCDCAP (see Note
1 and Note 3)
Charge pump enabled
(LCDCPEN = 1; VLCDx > 0000)
C
4.7
LCD
f
LCD frequency
1.1
kHz
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
LCD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
LCD voltage (see Note 3)
LCD voltage (see Note 3)
LCD voltage (see Note 3)
LCD voltage (see Note 3)
LCD voltage (see Note 3)
LCD voltage (see Note 3)
LCD voltage (see Note 3)
LCD voltage (see Note 3)
LCD voltage (see Note 3)
LCD voltage (see Note 3)
LCD voltage (see Note 3)
LCD voltage (see Note 3)
LCD voltage (see Note 3)
LCD voltage (see Note 3)
LCD voltage (see Note 3)
LCD voltage (see Note 3)
VLCDx = 0000
VLCDx = 0001
VLCDx = 0010
VLCDx = 0011
VLCDx = 0100
VLCDx = 0101
VLCDx = 0110
VLCDx = 0111
VLCDx = 1000
VLCDx = 1001
VLCDx = 1010
VLCDx = 1011
VLCDx = 1100
VLCDx = 1101
VLCDx = 1110
VLCDx = 1111
V
CC
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
2.60
2.66
2.72
2.78
2.84
2.90
2.96
3.02
3.08
3.14
3.20
3.26
3.32
3.38
3.44
3.60
10
V
=3V; CPEN = 1;
LCD
VLCDx = 1000, I
R
LCD Driver Output Impedance
2.2 V
kΩ
LCD
= ꢀ 10 µΑ
LOAD
NOTES: 1. Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device.
2. Refer to the supply current specifications I for additional current specifications with the LCD_A module active.
(LPM3)
3. Segments S0 through S3 must be disabled and cannot be used when the LCD charge pump feature is enabled. In addition, when
using segments S0 through S3 with an external LCD voltage supply, V ≤ AV
.
CC
LCD
4. Connecting an actual display will increase the current consumption depending on the size of the LCD.
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Comparator_A (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
25
MAX
40
UNIT
V
V
= 2.2 V
= 3 V
CC
I
CAON=1, CARSEL=0, CAREF=0
µA
(CC)
45
30
60
50
CC
CAON=1, CARSEL=0, CAREF=1/2/3,
No load at P1.6/CA0 and
P1.7/CA1
V
= 2.2 V
= 3 V
CC
CC
I
µA
(Refladder/RefDiode)
V
45
71
Voltage @ 0.25 V
node
node
PCA0=1, CARSEL=1, CAREF=1,
No load at P1.6/CA0 and P1.7/CA1
CC
V
V
V
= 2.2 V / 3 V
= 2.2V / 3 V
0.23
0.47
0.24
0.25
(Ref025)
(Ref050)
CC
V
CC
Voltage @ 0.5 V
PCA0=1, CARSEL=1, CAREF=2,
No load at P1.6/CA0 and P1.7/CA1
CC
V
0.48
0.5
CC
V
CC
PCA0=1, CARSEL=1, CAREF=3,
No load at P1.6/CA0 and P1.7/CA1;
V
V
= 2.2 V
= 3 V
390
400
480
490
540
550
CC
V
V
mV
V
(RefVT)
T
A
= 85°C
CC
Common-mode input
voltage range
CAON=1
V
CC
= 2.2 V / 3 V
0
V
−1
30
IC
CC
V −V
p
Offset voltage
See Note 2
CAON = 1
VCC = 2.2 V / 3 V
−30
0
mV
mV
S
V
hys
Input hysteresis
V
= 2.2 V / 3 V
= 2.2 V
= 3 V
0.7
210
150
1.9
1.4
300
240
3.4
CC
CC
CC
CC
CC
CC
CC
CC
CC
V
160
80
T
A
= 25°C,
ns
µs
ns
µs
Overdrive 10 mV, without filter: CAF = 0
V
t
(response LH)
V
= 2.2 V
= 3 V
1.4
0.9
130
80
T
A
= 25°C
Overdrive 10 mV, with filter: CAF = 1
V
1.5
2.6
V
= 2.2 V
= 3 V
210
150
1.9
300
240
3.4
T
A
= 25°C
Overdrive 10 mV, without filter: CAF = 0
V
t
(response HL)
V
V
= 2.2 V
= 3 V
1.4
0.9
T
= 25°C,
A
Overdrive 10 mV, with filter: CAF = 1
1.5
2.6
NOTES: 1. The leakage current for the Comparator_A terminals is identical to I
specification.
lkg(Px.x)
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢍ
ꢀ
ꢋ
ꢌ
ꢎ
ꢁ
ꢋ
ꢇ
ꢏ
ꢐ
ꢑ
ꢀ
ꢋ
ꢒ
ꢓ
ꢔꢒ
ꢔꢏ
ꢕ
ꢓ
ꢔꢑ
ꢑꢍ
ꢓ
SLAS508 − APRIL 2006
typical characteristics
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
650
600
550
500
450
400
650
600
550
500
450
400
V
CC
= 3 V
V
= 2.2 V
CC
Typical
Typical
−45
−25
−5
15
35
55
75
95
−45
−25
−5
15
35
55
75
95
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 6. V
vs Temperature
Figure 7. V
vs Temperature
(RefVT)
(RefVT)
0 V
0
V
CC
1
CAF
CAON
To Internal
Modules
Low-Pass Filter
0
1
0
1
+
_
V+
V−
CAOUT
Set CAIFG
Flag
τ ≈ 2 µs
Figure 8. Block Diagram of Comparator_A Module
V
CAOUT
Overdrive
V−
400 mV
V+
t
(response)
Figure 9. Overdrive Definition
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
POR/brownout reset (BOR) (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µs
t
2000
d(BOR)
V
dV /dt ≤ 3 V/s (see Figure 10)
CC
0.7 × V
(B_IT−)
V
CC(start)
Brownout
V
V
dV /dt ≤ 3 V/s (see Figure 10 through Figure 12)
CC
dV /dt ≤ 3 V/s (see Figure 10)
CC
1.71
180
V
(B_IT−)
(see Note 2)
70
2
130
mV
hys(B_IT−)
Pulse length needed at RST/NMI pin to accepted reset internally,
t
µs
(reset)
V
CC
= 2.2 V/3 V
NOTES: 1. The current consumption of the brownout module is already included in the I
current consumption data. The voltage level V
(B_IT−)
CC
+ V
is ≤ 1.8V.
2. During power up, the CPU begins code execution following a period of t
hys(B_IT−)
after V
CC
= V
(B_IT−)
+ V . The default
hys(B_IT−)
d(BOR)
FLL+ settings must not be changed until V
CC
≥ V
CC(min)
, where V
is the minimum supply voltage for the desired
CC(min)
operating frequency. See the MSP430x4xx Family User’s Guide for more information on the brownout/SVS circuit.
typical characteristics
V
CC
V
hys(B_IT−)
V
(B_IT−)
V
CC(start)
1
0
t
d(BOR)
Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage
V
t
CC
pw
2
3 V
V
= 3 V
CC
Typical Conditions
1.5
1
V
CC(drop)
0.5
0
0.001
1
1000
1 ns
1 ns
− Pulse Width − µs
t
− Pulse Width − µs
t
pw
pw
Figure 11. V
Level With a Square Voltage Drop to Generate a POR/Brownout Signal
CC(drop)
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢍ
ꢀ
ꢋ
ꢌ
ꢎ
ꢁ
ꢋ
ꢇ
ꢏ
ꢐ
ꢑ
ꢀ
ꢋ
ꢒ
ꢓ
ꢔꢒ
ꢔꢏ
ꢕ
ꢓ
ꢔꢑ
ꢑꢍ
ꢓ
SLAS508 − APRIL 2006
typical characteristics
V
t
CC
pw
2
3 V
V
= 3 V
CC
Typical Conditions
1.5
1
V
CC(drop)
0.5
0
t = t
f
r
0.001
1
1000
t
t
r
f
t
− Pulse Width − µs
t
− Pulse Width − µs
pw
pw
Figure 12. V
Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
CC(drop)
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
SVS (supply voltage supervisor/monitor) (see Note 1)
PARAMETER
TEST CONDITIONS
dV /dt > 30 V/ms (see Figure 13)
MIN
NOM
MAX
150
2000
150
12
UNIT
µs
5
CC
t
(SVSR)
dV /dt ≤ 30 V/ms
CC
µs
t
t
SVSon, switch from VLD=0 to VLD ≠ 0, V
= 3 V
20
µs
d(SVSon)
CC
‡
VLD ≠ 0
µs
settle
V
VLD ≠ 0, V /dt ≤ 3 V/s (see Figure 13)
CC
1.55
120
1.7
V
(SVSstart)
VLD = 1
70
155
mV
V
/dt ≤ 3 V/s (see Figure 13)
V
V
CC
CC
(SVS_IT−)
x 0.001
(SVS_IT−)
x 0.016
VLD = 2 .. 14
V
hys(SVS_IT−)
V
on A7
/dt ≤ 3 V/s (see Figure 13), external voltage applied
VLD = 15
4.4
20
mV
VLD = 1
VLD = 2
VLD = 3
VLD = 4
VLD = 5
VLD = 6
VLD = 7
VLD = 8
VLD = 9
VLD = 10
VLD = 11
VLD = 12
VLD = 13
VLD = 14
1.8
1.9
2.1
2.05
2.23
2.35
2.46
2.58
2.69
2.84
2.97
3.10
3.26
3.39
1.94
2.05
2.14
2.24
2.33
2.46
2.58
2.69
2.83
2.94
3.11
3.24
3.43
2.2
2.3
2.4
2.5
2.65
2.8
V
CC
/dt ≤ 3 V/s (see Figure 13)
V
V
(SVS_IT−)
2.9
3.05
3.2
†
†
†
3.35
3.5
3.58
3.73
3.96
†
3.7
V
on A7
/dt ≤ 3 V/s (see Figure 13), external voltage applied
CC
VLD = 15
1.1
1.2
10
1.3
15
I
CC(SVS)
(see Note 1)
VLD ≠ 0, V
= 2.2 V/3 V
µA
CC
†
‡
The recommended operating voltage range is limited to 3.6 V.
is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
t
settle
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 1: The current consumption of the SVS module is not included in the I
current consumption data.
CC
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
typical characteristics
Software Sets VLD>0:
SVS is Active
V
CC
V
hys(SVS_IT−)
V
(SVS_IT−)
V
(SVSstart)
V
hys(B_IT−)
V
(B_IT−)
V
CC(start)
Brown-
Out
Region
Brownout
Region
Brownout
1
0
t
t
SVS
Out
d(BOR)
d(BOR)
SVS Circuit is Active From VLD > to V < V(
CC
B_IT−)
1
0
t
t
d(SVSon)
d(SVSR)
Set POR
1
undefined
0
Figure 13. SVS Reset (SVSR) vs Supply Voltage
V
CC
t
pw
3 V
2
1.5
1
Rectangular Drop
V
CC(drop)
Triangular Drop
1 ns
1 ns
0.5
V
t
CC
pw
3 V
0
1
10
100
1000
V
t
− Pulse Width − µs
pw
CC(drop)
t = t
f
r
t
t
r
f
t − Pulse Width − µs
Figure 14. V
With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
CC(drop)
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
DCO
PARAMETER
TEST CONDITIONS
V
MIN
TYP
1
MAX
UNIT
CC
f
N
=01E0h, FN_8=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0
(DCO)
2.2 V/3 V
2.2 V
3 V
MHz
(DCOCLK)
0.3
0.3
2.5
2.7
0.7
0.8
5.7
6.5
1.2
1.3
9
0.65
0.7
5.6
6.1
1.3
1.5
10.8
12.1
2
1.25
1.3
10.5
11.3
2.3
2.5
18
f
f
f
f
f
f
f
f
f
f
FN_8=FN_4=FN_3=FN_2=0 ; DCOPLUS = 1
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
(DCO2)
2.2 V
3 V
FN_8=FN_4=FN_3=FN_2=0; DCOPLUS = 1, (see Note 1)
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1
(DCO27)
(DCO2)
(DCO27)
(DCO2)
(DCO27)
(DCO2)
(DCO27)
(DCO2)
(DCO27)
2.2 V
3 V
2.2 V
3 V
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1, (see Note 1)
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1, (see Note 1)
FN_8=0, FN_4= 1, FN_3= FN_2=x; DCOPLUS = 1
FN_8=0, FN_4=1, FN_3= FN_2=x; DCOPLUS = 1, (see Note 1)
FN_8=1, FN_4=FN_3=FN_2=x; DCOPLUS = 1
20
2.2 V
3 V
3
2.2
15.5
17.9
2.8
3.4
21.5
26.6
4.2
6.3
32
3.5
25
2.2 V
3 V
10.3
1.8
2.1
13.5
16
28.5
4.2
5.2
33
2.2 V
3 V
2.2 V
3 V
41
2.2 V
3 V
2.8
4.2
21
6.2
9.2
46
2.2 V
3 V
FN_8=1,FN_4=FN_3=FN_2=x; DCOPLUS = 1, (see Note 1)
Step size between adjacent DCO taps:
30
46
70
1 < TAP ≤ 20
TAP = 27
2.2 V
3 V
1.06
1.07
–0.2
–0.2
1.11
1.17
–0.4
–0.4
S
n
S
n
= f
/ f
, (see Figure 16 for taps 21 to 27)
DCO(Tap n+1) DCO(Tap n)
–0.3
–0.3
Temperature drift, N
(DCO)
= 01E0h, FN_8=FN_4=FN_3=FN_2=0
D
D
%/C
t
D = 2; DCOPLUS = 0
Drift with V variation, N
= 01E0h, FN_8=FN_4=FN_3=FN_2=0
CC (DCO)
0
5
15
%/V
V
D = 2; DCOPLUS = 0
NOTES: 1. Do not exceed the maximum system frequency.
f
f
(DCO)
(DCO)
f
f
5
(DCO3V)
(DCO20 C)
1.0
1.0
0
1.8
2.4
3.0
3.6
−40
−20
0
20
40
60
85
V
CC
− V
T − °C
A
Figure 15. DCO Frequency vs Supply Voltage V
and vs Ambient Temperature
CC
40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
1.17
Max
1.11
1.07
1.06
Min
1
20
27
DCO Tap
Figure 16. DCO Tap Step Size
Legend
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
9
2
5
to 2 in SCFI1 {N }
{DCO}
Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_3=x
FN_4=x
FN_8=1
Figure 17. Five Overlapping DCO Ranges Controlled by FN_x Bits
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
0
MAX
UNIT
OSCCAPx = 0h, V
OSCCAPx = 1h, V
OSCCAPx = 2h, V
OSCCAPx = 3h, V
OSCCAPx = 0h, V
OSCCAPx = 1h, V
OSCCAPx = 2h, V
OSCCAPx = 3h, V
= 2.2 V / 3 V
= 2.2 V / 3 V
= 2.2 V / 3 V
= 2.2 V / 3 V
= 2.2 V / 3 V
= 2.2 V / 3 V
= 2.2 V / 3 V
= 2.2 V / 3 V
CC
CC
CC
CC
CC
CC
CC
CC
10
14
18
0
Integrated input capacitance
(see Note 4)
C
C
pF
XIN
10
14
18
Integrated output capacitance
(see Note 4)
pF
V
XOUT
V
V
V
0.2×V
CC
IL
SS
0.8×V
Input levels at XIN
V
CC
= 2.2 V/3 V (see Note 3)
V
CC
IH
CC
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is
(C x C ) / (C + C ). This is independent of XTS_FLL.
XIN
XOUT XIN XOUT
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.
− Keep as short of a trace as possible between the ’FG461x and the crystal.
− Design a good ground plane around the oscillator pins.
− Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
− Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
− Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
− If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
− Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.
4. External capacitance is recommended for precision real-time clock applications; OSCCAPx = 0h.
crystal oscillator, XT2 oscillator (see Note 1)
PARAMETER
TEST CONDITIONS
= 2.2 V/3 V
MIN
NOM
MAX
UNIT
pF
pF
V
C
C
Integrated input capacitance
Integrated output capacitance
V
V
2
2
XT2IN
XT2OUT
IL
CC
= 2.2 V/3 V
CC
V
V
V
0.2 × V
CC
SS
0.8 × V
Input levels at XT2IN
V
CC
= 2.2 V/3 V (see Note 2)
V
CC
V
IH
CC
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
USCI (UART Mode)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
External: UCLK
Duty Cycle = 50% 10%
f
USCI input clock frequency
f
MHz
USCI
SYSTEM
1
BITCLK clock frequency
(equals Baudrate in MBaud)
f
t
2.2 V /3.0 V
MHz
BITCLK
2.2 V
3.0 V
50
50
150
100
600
600
ns
ns
UART receive deglitch time
(see Note 1)
τ
NOTES: 1. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode, see Figure 18 and Figure 19)
PARAMETER
TEST CONDITIONS
SMCLK, ACLK
Duty Cycle = 50% 10%
V
CC
MIN
TYP
MAX UNIT
f
t
t
t
USCI input clock frequency
f
MHz
USCI
SYSTEM
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
TBD
TBD
0
ns
ns
ns
ns
ns
ns
SOMI input data setup time
SOMI input data hold time
SIMO output data valid time
SU,MI
HD,MI
0
30
30
TBD
TBD
UCLK edge to SIMO valid;
= 20 pF
VALID,MO
C
L
USCI (SPI Slave Mode, see Figure 20 and Figure 21)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX UNIT
STE lead time
STE low to clock
t
t
t
t
2.2 V/3.0 V
2.2 V/3.0 V
2.2 V/3.0 V
2.2 V/3.0 V
50
ns
STE,LEAD
STE,LAG
STE,ACC
STE,DIS
STE lag time
Last clock to STE high
10
ns
ns
ns
STE access time
STE low to SOMI data out
C
= 20 pF
50
50
L
STE disable time
STE high to SOMI high impedance
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
TBD
TBD
0
ns
ns
ns
ns
t
t
t
SIMO input data setup time
SIMO input data hold time
SOMI output data valid time
SU,SI
HD,SI
0
50
50
TBD
TBD
ns
ns
UCLK edge to SOMI valid;
= 20 pF
VALID,SO
C
L
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLOW/HIGH tLOW/HIGH
tSU,MI
tHD,MI
SOMI
SIMO
tACC
tVALID ,MO
tDIS
Figure 18. SPI Master Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLOW/HIGH tLOW/HIGH
tHD,MI
tSU,MI
SOMI
SIMO
tACC
tVALID ,MO
tDIS
Figure 19. SPI Master Mode, CKPH = 1
44
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLOW/HIGH tLOW/HIGH
tSU,SI
tHD,SI
SIMO
SOMI
tACC
tVALID ,SO
tDIS
Figure 20. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
CKPL=1
UCLK
tLOW/HIGH tLOW/HIGH
tHD,SI
tSU,SI
SIMO
SOMI
tACC
tVALID ,SO
tDIS
Figure 21. SPI Slave Mode, CKPH = 1
45
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
USCI (I2C Mode, see Figure 22)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX UNIT
MHz
SYSTEM
Internal: SMCLK, ACLK
External: UCLK
Duty Cycle = 50% 10%
f
USCI input clock frequency
f
USCI
f
t
SCL clock frequency
2.2 V/3.0 V
2.2 V/3.0 V
2.2 V/3.0 V
2.2 V/3.0 V
2.2 V/3.0 V
2.2 V/3.0 V
2.2 V/3.0 V
2.2 V/3.0 V
2.2 V
0
4.0
0.6
4.7
0.6
0
400 kHz
SCL
f
f
f
f
≤ 100kHz
> 100kHz
≤ 100kHz
> 100kHz
us
us
us
us
ns
ns
us
SCL
SCL
SCL
SCL
Hold time (repeated) START
HD,STA
t
Set−up time for a repeated START
SU,STA
t
t
t
Data hold time
HD,DAT
SU,DAT
SU,STO
Data set−up time
Set−up time for STOP
250
4.0
50
150
100
600
600
ns
ns
Pulse width of spikes suppressed by
input filter
t
SP
3.0 V
50
tHD
tSU
tHD
tBUF
,STA
,STA
,STA
SDA
tLOW
tHIGH
tSP
SCL
tSU ,DAT
tSU
,STO
tHD
,DAT
Figure 22. I2C Mode Timing
USART1 (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
200
150
NOM MAX
UNIT
V
CC
V
CC
= 2.2 V
= 3 V
430
280
800
500
t
(τ)
USART1: deglitch time
ns
NOTES: 1. The signal applied to the USART1 receive signal/terminal (URXD1) should meet the timing requirements of t to ensure that the
(τ)
URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t . The operating
(τ)
conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative
transitions on the URXD1 line.
46
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, power supply and input range conditions (see Note 1)
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
AV
AV
and DV
are connected together
are connected together
CC
SS
CC
AV
Analog supply voltage
and DV
2.2
3.6
V
CC
SS
V
= V
= 0 V
(AVSS)
(DVSS)
All external Ax terminals. Analog inputs
selected in ADC12MCTLx register and P6Sel.x=1
Analog input voltage
range (see Note 2)
V
0
V
V
(P6.x/Ax)
AVCC
V
≤ V ≤ V
(AVSS)
Ax (AVCC)
Operating supply current
f
= 5.0 MHz
V
V
= 2.2 V
= 3 V
0.65
0.8
1.3
1.6
ADC12CLK
CC
into AV
terminal
ADC12ON = 1, REFON = 0
SHT0=0, SHT1=0, ADC12DIV=0
I
mA
mA
CC
ADC12
REF+
(see Note 3)
CC
f
= 5.0 MHz
ADC12CLK
ADC12ON = 0,
REFON = 1, REF2_5V = 1
V
= 3 V
0.5
0.8
CC
Operating supply current
I
into AV
terminal
CC
f
= 5.0 MHz
V
V
= 2.2 V
= 3 V
0.5
0.5
0.8
0.8
ADC12CLK
CC
(see Note 4)
ADC12ON = 0,
mA
REFON = 1, REF2_5V = 0
CC
Only one terminal can be selected
at one time, Ax
C
R
Input capacitance
V
V
= 2.2 V
= 3 V
40
pF
I
I
CC
Input MUX ON resistance 0V ≤ V ≤ V
Ax AVCC
2000
Ω
CC
NOTES: 1. The leakage current is defined in the leakage current table with Ax parameter.
2. The analog input voltage range must be within the selected reference voltage range V
to V
for valid conversion results.
R+
R−
3. The internal reference supply current is not included in current consumption parameter I
.
ADC12
4. The internal reference current is supplied via terminal AV . Consumption is independent of the ADC12ON control bit, unless a
CC
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
12-bit ADC, external reference (see Note 1)
PARAMETER
TEST CONDITIONS
/V
MIN NOM
MAX
UNIT
Positive external
reference voltage input
V
> V
REF− eREF−
eREF+
V
1.4
V
V
eREF+
AVCC
1.2
(see Note 2)
Negative external
reference voltage input
V
> V
/V
eREF+
REF− eREF−
V
V
0
V
V
REF− / eREF−
(see Note 3)
(V
V
−
Differential external
V
> V
/V
eREF+
eREF+ REF− eREF−
1.4
V
AVCC
V
)
reference voltage input
(see Note 4)
REF−/ eREF−
I
I
Input leakage current
Input leakage current
0V ≤V
≤ V
AVCC
V
V
= 2.2 V/3 V
= 2.2 V/3 V
1
1
µA
µA
VeREF+
eREF+
CC
0V ≤ V
eREF−
≤ V
AVCC
VREF−/VeREF−
CC
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, C , is also
I
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
47
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, built-in reference
PARAMETER
TEST CONDITIONS
REF2_5V = 1 for 2.5 V
max ≤ I ≤ I
MIN NOM
MAX
UNIT
V
V
= 3 V
=
2.4
2.5
1.5
2.6
CC
I
min
VREF+ VREF+ VREF+
Positive built-in reference
voltage output
V
REF+
V
REF2_5V = 0 for 1.5 V
max ≤ I ≤ I
CC
1.44
1.56
I
min 2.2 V/3 V
VREF+ VREF+ VREF+
REF2_5V = 0, I
REF2_5V = 1, I
REF2_5V = 1, I
max ≤ I
min ≥ I
≤ I
min
2.2
2.8
VREF+
VREF+
VREF+
VREF+ VREF+
AV
CC
minimum voltage,
Positive built-in reference
active
≥ −0.5mA
AV
CC(min)
V
VREF+
VREF+
min ≥ I
≥ −1mA
2.9
V
= 2.2 V
= 3 V
0.01
0.01
−0.5
−1
Load current out of V
terminal
CC
CC
REF+
I
mA
VREF+
V
I
= 500 µA +/− 100 µA
V
= 2.2 V
= 3 V
2
2
VREF+
CC
CC
Analog input voltage ~0.75 V;
REF2_5V = 0
LSB
V
Load-current regulation
terminal
I
L(VREF)+
V
I
= 500 µA 100 µA
REF+
VREF+
Analog input voltage ~1.25 V;
REF2_5V = 1
V
CC
= 3 V
2
LSB
I
C
=100 µA → 900 µA,
=5 µF, ax ~0.5 x V
VREF+
VREF+
Load current regulation
terminal
I
V
V
= 3 V
=
20
ns
REF+
DL(VREF) +
CC
V
REF+
Error of conversion result ≤ 1 LSB
Capacitance at pin V
(see Note 1)
REFON =1,
REF+
CC
C
5
10
µF
VREF+
0 mA ≤ I
≤ I
max
2.2 V/3 V
VREF+ VREF+
Temperature coefficient of
built-in reference
I
is a constant in the range of
V
=
VREF+
0 mA ≤ I
CC
2.2 V/3 V
T
100 ppm/°C
REF+
≤ 1 mA
VREF+
Settle time of internal
reference voltage (see
Figure 23 and Note 2)
I
V
= 0.5 mA, C
= 10 µF,
= 2.2 V
AVCC
VREF+
= 1.5 V, V
VREF+
17
ms
t
REFON
REF+
NOTES: 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses
two capacitors between pins V
REF+
and AV
SS
and V
/V
and AV : 10 µF tantalum and 100 nF ceramic.
REF− eREF−
SS
2. The condition is that the error in a conversion started after t
capacitive load.
is less than 0.5 LSB. The settling time depends on the external
REFON
C
VREF+
100 µF
t
≈ .66 x C
[ms] with C in µF
VREF+
REFON
VREF+
10 µF
1 µF
0
10 ms
1 ms
100 ms
t
REFON
Figure 23. Typical Settling Time of Internal Reference t
vs External Capacitor on V
+
REFON
REF
48
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
DV
DV
From
Power
Supply
CC1/2
+
−
SS1/2
10 µF 100 nF
AV
CC
SS
+
−
MSP430FG461x
AV
10 µF 100 nF
Apply External Reference [V
or Use Internal Reference [V
]
eREF+
REF+
V
REF+
or V
eREF+
]
+
−
10 µF 100 nF
Apply
V −/V
REF eREF−
External
Reference
+
−
10 µF 100 nF
Figure 24. Supply Voltage and Reference Voltage Design V
V
External Supply
REF−/ eREF−
DV
From
Power
Supply
CC1/2
+
−
DV
SS1/2
10 µF 100 nF
AV
CC
SS
+
−
MSP430FG461x
AV
10 µF 100 nF
Apply External Reference [V
or Use Internal Reference [V
]
eREF+
REF+
V
REF+
or V
]
eREF+
+
−
10 µF 100 nF
Reference Is Internally
Switched to AV
V
/V
REF− eREF−
SS
Figure 25. Supply Voltage and Reference Voltage Design V
V
= AV , Internally Connected
REF−/ eREF− SS
49
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, timing parameters
PARAMETER
TEST CONDITIONS
For specified performance of
MIN
NOM
MAX
UNIT
V
=
CC
2.2V/3 V
f
f
0.45
5
6.3
MHz
ADC12CLK
ADC12 linearity parameters
Internal ADC12
oscillator
ADC12DIV=0,
V
=
CC
2.2 V/ 3 V
3.7
5
6.3
MHz
µs
ADC12OSC
f
=f
ADC12CLK ADC12OSC
C
≥ 5 µF, Internal oscillator,
V
=
VREF+
CC
= 3.7 MHz to 6.3 MHz 2.2 V/ 3 V
2.06
3.51
f
ADC12OSC
t
Conversion time
CONVERT
External f
ADC12SSEL ≠ 0
from ACLK, MCLK or SMCLK:
13×ADC12DIV×
ADC12CLK
µs
1/f
ADC12CLK
Turn on settling time of
the ADC
t
t
(see Note 1)
100
ns
ADC12ON
V
V
2.2 V
= 3 V
=
1220
1400
R
= 400 Ω, R = 1000 Ω,
CC
S
I
C = 30 pF, τ = [R + R ] x C
Sampling time
ns
I
S
I
I
Sample
CC
(see Note 2)
NOTES: 1. The condition is that the error in a conversion started after t
settled.
is less than 0.5 LSB. The reference and input signal are already
ADC12ON
2. Approximately ten Tau (τ) are needed to get an error of less than 0.5 LSB:
n+1
= ln(2
t
) x (R + R ) x C + 800 ns where n = ADC resolution = 12, R = external source resistance.
Sample
S
I
I
S
12-bit ADC, linearity parameters
PARAMETER
TEST CONDITIONS
/V ) min ≤ 1.6 V
MIN NOM MAX
UNIT
1.4 V ≤ (V
− V
− V
2
eREF+
REF− eREF−
/V
V
=
CC
2.2 V/3 V
E
E
Integral linearity error
LSB
I
1.6 V < (V
) min ≤ [V
REF− eREF− AVCC
]
1.7
eREF+
Differential linearity
error
(V
eREF+
VREF+
− V
/V
)
≤ (V
− V
/V
),
),
V
=
REF− eREF− min
eREF+
= 10 µF (tantalum) and 100 nF (ceramic)
REF− eREF−
CC
2.2 V/3 V
1
LSB
LSB
D
C
(V
− V
/V
)
≤ (V
eREF+
S
− V
/V
eREF+
Internal impedance of source R < 100 Ω,
REF− eREF− min
REF− eREF−
V
=
CC
2.2 V/3 V
E
O
2
4
Offset error
Gain error
C
= 10 µF (tantalum) and 100 nF (ceramic)
VREF+
(V
− V
/V
)
≤ (V
eREF+
− V
/V
),
),
V
=
eREF+
REF− eREF− min
REF− eREF−
CC
2.2 V/3 V
E
E
1.1
2
2
5
LSB
LSB
G
C
= 10 µF (tantalum) and 100 nF (ceramic)
VREF+
(V
− V
/V
)
≤ (V
eREF+
− V
/V
V
=
Total unadjusted
error
eREF+
REF− eREF− min
REF− eREF−
CC
2.2 V/3 V
T
C
= 10 µF (tantalum) and 100 nF (ceramic)
VREF+
50
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, temperature sensor and built-in V
MID
PARAMETER
TEST CONDITIONS
V
MIN
NOM
40
MAX
120
UNIT
CC
2.2 V
3 V
Operating supply current into REFON = 0, INCH = 0Ah,
I
µA
SENSOR
AV
CC
terminal (see Note 1)
ADC12ON=NA, T = 25_C
60
160
A
ADC12ON = 1, INCH = 0Ah,
2.2 V/
3 V
V
(see Note 2)
986
mV
SENSOR
T
A
= 0°C
2.2 V/
3 V
TC
ADC12ON = 1, INCH = 0Ah
3.55 3%
mV/°C
SENSOR
Sample time required if
channel 10 is selected
(see Note 3)
2.2 V
3 V
30
30
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
t
µs
SENSOR(sample)
VMID
2.2 V
3 V
NA
NA
Current into divider at
channel 11 (see Note 4)
I
ADC12ON = 1, INCH = 0Bh,
ADC12ON = 1, INCH = 0Bh,
µA
2.2 V
3 V
1.1
1.1 0.04
V
AV
CC
divider at channel 11
V
MID
V
MID
is ~0.5 x V
AVCC
1.5 1.50 0.04
Sample time required if
channel 11 is selected
(see Note 5)
2.2 V
3 V
1400
1220
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
t
ns
VMID(sample)
NOTES: 1. The sensor current I
is consumed if (ADC12ON = 1 and REFON=1), or (ADC12ON=1 AND INCH=0Ah and sample signal
SENSOR
is high). When REFON = 1, I
is already included in I .
SENSOR
REF+
2. The temperature sensor offset can be as much as 20_C. A single-point calibration is recommended in order to minimize the offset
error of the built-in temperature sensor.
3. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t
SENSOR(on)
4. No additional current is needed. The V
5. The on-time t
VMID(on)
is used during sampling.
MID
is included in the sampling time t ; no additional on time is needed.
VMID(sample)
12-bit DAC, supply specifications
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
AV
AV
DV
,
CC =
CC
SS
AV
CC
Analog supply voltage
2.20
3.60
V
= DV
=0 V
SS
DAC12AMPx=2, DAC12IR=0,
DAC12_xDAT=0800h
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V
50
50
110
110
DAC12AMPx=2, DAC12IR=1,
Supply Current:
DAC12_xDAT=0800h
V
=V = AV
,
eREF+ REF+
CC
CC
CC
Single DAC Channel
(see Notes 1 and 2)
I
µA
DD
DAC12AMPx=5, DAC12IR=1,
DAC12_xDAT=0800h, V
200
700
440
=V
= AV
= AV
eREF+ REF+
DAC12AMPx=7, DAC12IR=1,
1500
DAC12_xDAT=0800h, V =V
eREF+ REF+
DAC12_xDAT = 800h, V
= 1.5 V
REF
Power supply
∆AV
CC
= 100mV
rejection ratio
PSRR
70
dB
DAC12_xDAT = 800h, V
∆AV = 100mV
= 1.5 V or 2.5 V
REF
(see Notes 3 and 4)
3V
CC
NOTES: 1. No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
2. Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input
specifications.
3. PSRR = 20*log{∆AV /∆V
}.
is applied externally. The internal reference is not used.
CC DAC12_xOUT
4.
V
REF
51
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (see Figure 26)
PARAMETER
TEST CONDITIONS
(12-bit Monotonic)
= 1.5 V
V
MIN
TYP
MAX
UNIT
CC
Resolution
12
bits
V
ref
DAC12AMPx = 7, DAC12IR = 1
2.2V
3V
Integral nonlinearity
(see Note 1)
INL
2.0
8.0
LSB
LSB
V
= 2.5 V
ref
DAC12AMPx = 7, DAC12IR = 1
V
= 1.5 V
ref
DAC12AMPx = 7, DAC12IR = 1
2.2V
3V
Differential nonlinearity
(see Note 1)
DNL
0.4
1.0
21
V
= 2.5 V
ref
DAC12AMPx = 7, DAC12IR = 1
V
= 1.5 V
ref
DAC12AMPx = 7, DAC12IR = 1
2.2V
3V
Offset voltage w/o
calibration
V
= 2.5 V
ref
DAC12AMPx = 7, DAC12IR = 1
(see Notes 1, 2)
E
O
mV
V
= 1.5 V
ref
DAC12AMPx = 7, DAC12IR = 1
2.2V
3V
Offset voltage with
calibration
2.5
V
= 2.5 V
ref
DAC12AMPx = 7, DAC12IR = 1
(see Notes 1, 2)
Offset error
d
/d
/d
E(O)
T
temperature coefficient
(see Note 1)
2.2V/3V
30
10
µV/C
V
V
= 1.5 V
= 2.5 V
2.2V
3V
REF
E
Gain error (see Note 1)
3.50 % FSR
G
REF
Gain temperature
ppm of
FSR/°C
d
E(G)
2.2V/3V
T
coefficient (see Note 1)
DAC12AMPx=2
2.2V/3V
2.2V/3V
2.2V/3V
100
Time for offset calibration
(see Note 3)
DAC12AMPx=3,5
DAC12AMPx=4,6,7
32
6
t
ms
Offset_Cal
NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and
“b” of the first order equation: y = a + b*x. V = E + (1 + E ) * (V /4095) * DAC12_xDAT, DAC12IR = 1.
DAC12_xOUT eREF+
O
G
2. The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx
={0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may
effect accuracy and is not recommended.
DAC V
OUT
DAC Output
V
R+
R
=
Load
Ideal transfer
function
AV
CC
2
Offset Error
Positive
Gain Error
C
= 100pF
Load
Negative
DAC Code
Figure 26. Linearity Test Load Conditions and Gain/Offset Definition
52
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (continued)
TYPICAL INL ERROR
vs
DIGITAL INPUT DATA
4
V
= 2.2 V, V = 1.5V
REF
CC
DAC12AMPx = 7
DAC12IR = 1
3
2
1
0
−1
−2
−3
−4
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT − Digital Code
TYPICAL DNL ERROR
vs
DIGITAL INPUT DATA
2.0
1.5
V
= 2.2 V, V = 1.5V
REF
CC
DAC12AMPx = 7
DAC12IR = 1
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT − Digital Code
53
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, output specifications
PARAMETER
TEST CONDITIONS
No Load, Ve = AV
V
CC
MIN
TYP
MAX
UNIT
,
REF+ CC
DAC12_xDAT = 0h, DAC12IR = 1,
2.2V/3V
2.2V/3V
2.2V/3V
0
0.005
DAC12AMPx = 7
No Load, Ve
REF+
= AV ,
CC
DAC12_xDAT = 0FFFh, DAC12IR = 1,
AV −0.05
CC
AV
Output voltage
CC
DAC12AMPx = 7
range
V
O
V
(see Note 1,
Figure 29)
R
= 3 kΩ, Ve
Load REF+
= AV ,
CC
DAC12_xDAT = 0h, DAC12IR = 1,
0
0.1
DAC12AMPx = 7
R
= 3 kΩ, Ve
Load REF+
= AV ,
CC
DAC12_xDAT = 0FFFh, DAC12IR = 1,
2.2V/3V
2.2V/3V
AV −0.13
CC
AV
CC
DAC12AMPx = 7
Max DAC12
C
100
pF
L(DAC12)
load capacitance
2.2V
3V
−0.5
−1.0
+0.5
+1.0
Max DAC12
load current
I
mA
L(DAC12)
R
= 3 kΩ, V
< 0.3 V,
Load O/P(DAC12)
2.2V/3V
2.2V/3V
2.2V/3V
150
150
1
250
250
4
DAC12AMPx = 2, DAC12_xDAT = 0h
R
V
= 3 kΩ,
Load
Output
> AV −0.3 V
CC
R
Ω
Resistance
(see Figure 29)
O/P(DAC12)
O/P(DAC12)
DAC12_xDAT = 0FFFh
R
= 3 kΩ,
Load
0.3V ≤ V
≤ AV
CC
− 0.3V
O/P(DAC12)
NOTES: 1. Data is valid after the offset calibration of the output amplifier.
R
O/P(DAC12_x)
Max
R
Load
I
Load
AV
CC
DAC12
2
C
= 100pF
O/P(DAC12_x)
Min
Load
0.3
AV
−0.3V
V
CC
OUT
AV
CC
Figure 29. DAC12_x Output Resistance Tests
54
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
12-bit DAC, reference input specifications
PARAMETER
Reference input
TEST CONDITIONS
DAC12IR=0, (see Notes 1 and 2)
DAC12IR=1, (see Notes 3 and 4)
DAC12_0 IR=DAC12_1 IR =0
DAC12_0 IR=1, DAC12_1 IR = 0
DAC12_0 IR=0, DAC12_1 IR = 1
V
MIN
TYP
MAX
UNIT
CC
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
AV /3 AV +0.2
CC CC
Ve
V
REF+
voltage range
AVcc AVcc+0.2
20
40
MΩ
48
24
56
28
kΩ
kΩ
Ri
Ri
,
Reference input
resistance
(VREF+)
DAC12_0 IR=DAC12_1 IR =1
DAC12_0 SREFx = DAC12_1 SREFx
(see Note 5)
(VeREF+)
2.2V/3V
20
NOTES: 1. For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AV ).
CC
2. The maximum voltage applied at reference input voltage terminal Ve
3. For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AV ).
4. The maximum voltage applied at reference input voltage terminal Ve
REF+
= [AV
CC
− V ] / [3*(1 + E )].
E(O) G
REF+
CC
= [AV
CC
− V ] / (1 + E ).
E(O) G
5. When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
12-bit DAC, dynamic specifications; V = V , DAC12IR = 1 (see Figure 30 and Figure 31)
ref
CC
PARAMETER
TEST CONDITIONS
DAC12AMPx=0 → {2, 3, 4}
DAC12AMPx=0 → {5, 6}
DAC12AMPx=0 → 7
DAC12AMPx=2
V
MIN
TYP
60
15
6
MAX
120
30
UNIT
CC
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
2.2V/3V
DAC12_xDAT = 800h,
Error 0.5 LSB
DAC12 on-
time
<
t
t
t
µs
V(O)
ON
(see Note 1,Figure 30)
12
100
40
15
5
200
80
Settling
DAC12_xDAT =
DAC12AMPx=3,5
DAC12AMPx=4,6,7
DAC12AMPx=2
µs
µs
S(FS)
time,full-scale 80h→ F7Fh→ 80h
30
DAC12_xDAT =
Settling time,
DAC12AMPx=3,5
DAC12AMPx=4,6,7
DAC12AMPx=2
2
3F8h→ 408h→ 3F8h
code to code
S(C-C)
BF8h→ C08h→ BF8h
1
0.05
0.35
1.5
0.12
0.7
2.7
600
150
30
DAC12_xDAT =
DAC12AMPx=3,5
DAC12AMPx=4,6,7
DAC12AMPx=2
80h→ F7Fh→ 80h
(see Note 2)
SR
Slew Rate
V/µs
nV-s
DAC12_xDAT =
DAC12AMPx=3,5
DAC12AMPx=4,6,7
Glitch energy: full-scale
80h→ F7Fh→ 80h
NOTES: 1. R
and C
Load
connected to AV
SS
(not AV /2) in Figure 30.
CC
Load
2. Slew rate applies to output voltage steps >= 200mV.
Conversion 1
Conversion 2
Conversion 3
+/− 1/2 LSB
V
+/− 1/2 LSB
DAC Output
OUT
Glitch
Energy
R
= 3 kΩ
Load
I
Load
AV
CC
2
C
= 100pF
Load
R
O/P(DAC12.x)
t
t
settleHL
settleLH
Figure 30. Settling Time and Glitch Energy Testing
55
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
Conversion 1
Conversion 2
Conversion 3
V
OUT
90%
90%
10%
10%
t
t
SRHL
SRLH
Figure 31. Slew Rate Testing
12-bit DAC, dynamic specifications continued (T = 25°C unless otherwise noted)
A
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
2.2V/3V
2.2V/3V
2.2V/3V
40
3-dB bandwidth,
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
180
550
BW
−3dB
kHz
V
=1.5V, V =0.1V
AC PP
DC
(see Figure 32)
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
DAC12_0DAT = 800h, No Load,
DAC12_1DAT = 80h<−>F7Fh, R
= 3kΩ
= 10kHz @ 50/50 duty cycle
2.2V/3V
2.2V/3V
−80
−80
Load
f
DAC12_1OUT
dB
Channel-to-channel crosstalk
(see Note 1 and Figure 33)
DAC12_0DAT = 80h<−>F7Fh, R
DAC12_1DAT = 800h, No Load
= 3kΩ,
Load
f
= 10kHz @ 50/50 duty cycle
DAC12_0OUT
NOTES: 1. R
= 3 kΩ, C
LOAD
= 100 pF
LOAD
R
= 3 kΩ
Load
I
Load
Ve
REF+
AV
CC
DAC12_x
2
DACx
AC
DC
C
= 100pF
Load
Figure 32. Test Conditions for 3-dB Bandwidth Specification
R
Load
I
Load
AV
DAC12_xDAT 080h
7F7h
080h
7F7h
080h
CC
DAC12_0
2
DAC0
V
OUT
C
= 100pF
Load
V
V
V
DAC12_yOUT
DAC12_xOUT
REF+
R
Load
I
Load
AV
CC
e
DAC12_1
2
f
DAC1
Toggle
C
= 100pF
Load
Figure 33. Crosstalk Test Conditions
56
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
operational amplifier OA, supply specifications
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
V
CC
Supply voltage
—
2.2
3.6
V
Fast Mode, OARRIP OFF
Medium Mode, OARRIP OFF
Slow Mode, OARRIP OFF
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
180
290
190
80
110
50
Supply current
(see Note 1)
I
µA
CC
Fast Mode, OARRIP ON
Medium Mode, OARRIP ON
Slow Mode, OARRIP ON
Non-inverting
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
300
190
90
490
350
190
PSRR Power supply rejection ratio
70
dB
NOTES: 1. P6SEL.x = 1 for each corresponding pin when used in OA input or OA output mode.
operational amplifier OA, input/output specifications
PARAMETER
TEST CONDITIONS
OARRIP OFF
OARRIP ON
V
MIN
TYP
MAX
UNIT
V
CC
—
—
—
—
—
—
—
—
—
—
−0.1
−0.1
−5
V
CC
−1.2
+0.1
5
V
I/P
Voltage supply, I/P
V
CC
V
T
= −40 to +55_C
0.5
5
nA
nA
Input leakage current, I/P
(see Notes 1 and 2)
A
I
Ikg
T
A
= +55 to +85_C
−20
20
Fast Mode
50
80
140
30
50
65
Medium Mode
Slow Mode
Fast Mode
f
= 1 kHz
V(I/P)
V
V
Voltage noise density, I/P
nV/√Hz
n
Medium Mode
Slow Mode
f
= 10 kHz
V(I/P)
Offset voltage, I/P
2.2 V/3 V
2.2 V/3 V
10
mV
IO
Offset temperature drift, I/P
see Note 3
10
µV/°C
Offset voltage drift
with supply, I/P
0.3V ≤ V ≤ V −0.3V
IN CC
2.2 V/3 V
1.5
mV/V
∆V
≤
10%, T = 25°C
CC
A
Fast Mode, I
Slow Mode,I
Fast Mode, I
Slow Mode,I
≤ −500µA
2.2 V
3 V
V
V
−0.2
−0.1
V
V
SOURCE
SOURCE
SOURCE
SOURCE
CC
CC
V
V
High-level output voltage, O/P
Low-level output voltage, O/P
V
V
OH
≤ −150µA
≤ +500µA
≤ +150µA
CC
CC
0.2
2.2 V
3 V
V
SS
OL
V
SS
0.1
R
= 3 kΩ, C
Load Load
= 50pF,
OARRIP ON,
< 0.2 V
2.2 V/3 V
2.2 V/3 V
150
150
250
250
4
V
O/P(OAx)
Output
Resistance
(see Figure 34 and Note 4)
R
= 3 kΩ, C
Load Load
= 50pF,
R
O/P
OARRIP ON,
> AV
Ω
)
(OAx
V
− 0.2 V
O/P(OAx)
CC
R
= 3 kΩ, C
= 50pF,
Load
OARRIP ON,
0.2 V ≤ V
Load
2.2 V/3 V
2.2 V/3 V
0.1
70
≤ AV
CC
− 0.2 V
O/P(OAx)
CMRR Common-mode rejection ratio Non-inverting
NOTES: 1. ESD damage can degrade input current leakage.
dB
2. The input bias current is overridden by the input leakage current.
3. Calculated using the box method.
4. Specification valid for voltage-follower OAx configuration.
57
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
R
O/P(OAx)
Max
R
Load
I
Load
AV
CC
OAx
2
C
O/P(OAx)
Min
Load
0.2V
AV
−0.2V
CC
V
AV
OUT
CC
Figure 34. OAx Output Resistance Tests
operational amplifier OA, dynamic specifications
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
Fast Mode
—
1.2
0.8
0.3
100
60
Medium Mode
Slow Mode
—
SR
Slew rate
V/µs
—
—
Open-loop voltage gain
Phase margin
dB
deg
dB
φ
m
C
C
= 50 pF
= 50 pF
—
L
L
Gain margin
—
20
Non−inverting, Fast Mode, R = 47kΩ, C = 50pF
2.2 V/3 V
2.2
1.4
0.5
10
L
L
Gain-Bandwidth Product
(see Figure 35
and Figure 36)
GBW
Non−inverting, Medium Mode, R =300kΩ, C = 50pF 2.2 V/3 V
MHz
L
L
Non−inverting, Slow Mode, R =300kΩ, C = 50pF
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
L
L
t
t
Enable time on
Enable time off
t , non-inverting, Gain = 1
on
20
µs
µs
en(on)
1
en(off)
TYPICAL PHASE vs FREQUENCY
TYPICAL OPEN-LOOP GAIN vs FREQUENCY
Fast Mode
0
140
120
100
80
−50
−100
−150
−200
−250
Fast Mode
Medium Mode
60
40
20
Medium Mode
Slow Mode
Slow Mode
0
−20
−40
−60
−80
0.001 0.01
0.1
1
10
100 1000 10000
1
10
100
1000
10000
Input Frequency − kHz
Input Frequency − kHz
Figure 35
Figure 36
58
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
Flash Memory
TEST
CONDITIONS
PARAMETER
V
CC
MIN
TYP
MAX
UNIT
V
CC(PGM/
ERASE)
Program and Erase supply voltage
Flash Timing Generator frequency
2.7
3.6
V
f
I
I
257
476
5
kHz
mA
mA
FTG
Supply current from DV
Supply current from DV
during program
during erase
during global
2.7 V/ 3.6 V
2.7 V/ 3.6 V
3
3
PGM
CC
CC
CC
see Note 3
see Note 4
see Note 1
7
ERASE
Supply current from DV
mass erase
I
2.7 V/ 3.6 V
6
14
10
mA
GMERASE
t
t
Cumulative program time
2.7 V/ 3.6 V
2.7 V/ 3.6 V
ms
ms
CPT
Cumulative mass erase time
Program/Erase endurance
Data retention duration
20
CMErase
4
5
10
100
10
cycles
years
t
t
t
T = 25°C
J
Retention
Word or byte program time
30
25
Word
st
Block program time for 1 byte or word
Block, 0
Block program time for each additional byte
or word
t
18
Block, 1-63
see Note 2
t
FTG
t
t
t
t
Block program end-sequence wait time
Mass erase time
6
10593
10593
4819
Block, End
Mass Erase
Global Mass Erase
Seg Erase
Global mass erase time
Segment erase time
NOTES: 1. The cumulative program time must not be exceeded during a block-write operation. This parameter is only relevant if the block write
feature is used.
2. These values are hardwired into the Flash Controller’s state machine (t
3. Lower 64-KB or upper 64-KB Flash memory erased.
4. All Flash memory erased.
= 1/f
FTG
).
FTG
JTAG Interface
TEST
CONDITIONS
PARAMETER
V
CC
MIN
TYP
MAX
UNIT
2.2 V
3 V
0
0
5
10
90
MHz
MHz
kΩ
f
TCK input frequency
see Note 1
TCK
R
Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2
may be restricted to meet the timing requirements of the module selected.
2.2 V/ 3 V
25
60
Internal
NOTES: 1. f
TCK
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG Fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
V
CC
MIN
TYP
MAX
UNIT
V
V
Supply voltage during fuse-blow condition
Voltage level on TDI/TCLK for fuse-blow: F versions
Supply current into TDI/TCLK during fuse blow
Time to blow fuse
T
A
= 25°C
2.5
6
V
V
CC(FB)
7
100
1
FB
I
t
mA
ms
FB
FB
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
59
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
input/output schematic
Port P1, P1.0 to P1.5, input/output with Schmitt-trigger
Pad Logic
DV
DV
SS
SS
DV
SS
P1DIR.x
0
1
Direction
0: Input
1: Output
P1OUT.x
0
1
Module X OUT
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
Bus
Keeper
P1SEL.x
EN
P1IN.x
EN
D
Module X IN
P1IE.x
EN
P1IRQ.x
Q
Set
P1IFG.x
Interrupt
Edge
Select
P1SEL.x
P1IES.x
Note: x = 0,1,2,3,4,5
Port P1 (P1.0 to P1.5) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
P1DIR.x
P1SEL.x
P1.0/TA0
0
P1.0 (I/O)
I: 0; O: 1
0
1
1
0
1
1
Timer_A3.CCI0A
Timer_A3.TA0
P1.1 (I/O)
0
1
P1.1/TA0/MCLK
1
I: 0; O: 1
Timer_A3.CCI0B
MCLK
0
1
60
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
Port P1 (P1.0 to P1.5) pin functions (continued)
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
P1.2/TA1
X
FUNCTION
P1DIR.x
P1SEL.x
2
P1.2 (I/O)
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
Timer_A3.CCI1A
Timer_A3.TA1
P1.3 (I/O)
0
1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
3
4
5
I: 0; O: 1
Timer_B7.TBOUTH
SVSOUT
0
1
P1.4 (I/O)
I: 0; O: 1
Timer_B7.TBCLK
SMCLK
0
1
P1.5 (I/O)
I: 0; O: 1
Timer_A3.TACLK
ACLK
0
1
61
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
Port P1, P1.6, P1.7, input/output with Schmitt-trigger
Pad Logic
DV
DV
SS
SS
CAPD.x
P1DIR.x
0
1
Direction
0: Input
1: Output
P1OUT.x
0
1
Module X OUT
P1.6/CA0
P1.7/CA1
Bus
Keeper
P1SEL.x
EN
P1IN.x
EN
D
Module X IN
P2CA0
P1IE.x
EN
P1IRQ.x
Comp_A
0
1
Q
CA0
CA1
Set
P1IFG.x
+
−
Interrupt
Edge
P1SEL.x
P1IES.x
0
1
Select
Note: x = 6,7
P2CA1
Port P1 (P1.6 and P1.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
CAPD.x
P1DIR.x
I: 0; O: 1
X
P1SEL.x
P1.6/CA0
6
P1.6 (I/O)
CA0
0
1
0
1
0
X
0
P1.7/CA1
7
P1.6 (I/O)
CA0
I: 0; O: 1
X
X
NOTES: 1. X: Don’t care.
62
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
port P2, P2.0 to P2.3, P2.6 to P2.7, input/output with Schmitt-trigger
Pad Logic
DV
DV
SS
SS
TBOUTH
P2DIR.x
0
1
Direction
0: Input
1: Output
P2OUT.x
0
1
Module X OUT
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
Bus
Keeper
P2SEL.x
EN
P2.6/CAOUT
P2.7/ADC12CLK/DMAE0
P2IN.x
EN
D
Module X IN
P2IE.x
EN
P2IRQ.x
Q
Set
P2IFG.x
Interrupt
Edge
Select
P2SEL.x
P2IES.x
Note: x = 0,1,2,3,6,7
63
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
Port P2 (P2.0, P2.1, P2.2, P2.3, P2.6 and P2.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
P2.0/TA2
X
FUNCTION
P2DIR.x
P2SEL.x
0
P2.0 (I/O)
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
1
Timer_A3.CCI2A
Timer_A3.TA2
P2.1 (I/O)
0
1
P2.1/TB0
P2.2/TB1
P2.3/TB3
1
2
3
I: 0; O: 1
Timer_B7.CCI0A and Timer_B7.CCI0B
Timer_B7.TB0 (see Note 1)
P2.2 (I/O)
0
1
I: 0; O: 1
Timer_B7.CCI1A and Timer_B7.CCI1B
Timer_B7.TB1 (see Note 1)
P2.3 (I/O)
0
1
I: 0; O: 1
Timer_B7.CCI2A and Timer_B7.CCI2B
Timer_B7.TB3 (see Note 1)
P2.6 (I/O)
0
1
P2.6/CAOUT
6
7
I: 0; O: 1
CAOUT
1
P2.7/ADC12CLK/DMAE0
P2.7 (I/O)
I: 0; O: 1
ADC12CLK
1
0
DMAE0
NOTES: 1. Setting TBOUTH causes all Timer_B outputs to be set to high impedance.
64
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
port P2, P2.4 to P2.5, input/output with Schmitt-trigger
Pad Logic
DV
DV
SS
SS
DV
SS
P2DIR.x
0
1
Direction
0: Input
1: Output
Direction control
from Module X
P2OUT.x
0
1
Module X OUT
P2.4/UCA0TXD
P2.5/UCA0RXD
Bus
Keeper
P2SEL.x
EN
P2IN.x
EN
D
Module X IN
P2IE.x
EN
P2IRQ.x
Q
Set
P2IFG.x
Interrupt
Edge
Select
P2SEL.x
P2IES.x
Note: x = 4,5
65
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
Port P2 (P2.4 and P2.5) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
X
FUNCTION
P2DIR.x
I: 0; O: 1
X
P2SEL.x
P2.4/UCA0TXD
4
P2.4 (I/O)
0
1
0
1
USCI_A0.UCA0TXD (see Note 1, 2)
P2.5 (I/O)
P2.5/UCA0RXD
5
I: 0; O: 1
X
USCI_A0.UCA0RXD (see Note 1, 2)
NOTES: 1. X: Don’t care.
2. When in USCI mode, P2.4 is set to output, P2.5 is set to input.
66
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
port P3, P3.0 to P3.3, input/output with Schmitt-trigger
Pad Logic
DV
DV
SS
SS
DV
SS
P3DIR.x
0
1
Direction
0: Input
1: Output
P3OUT.x
0
1
Module X OUT
P3.0/UCB0STE
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK
Bus
Keeper
P3SEL.x
P3IN.x
EN
EN
D
Module X IN
Note: x = 0,1,2,3
Port P3 (P3.0 to P3.3) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P3.X)
X
FUNCTION
P3DIR.x
I: 0; O: 1
X
P3SEL.x
P3.0/UCB0STE
0
P3.0 (I/O)
0
1
0
1
0
1
0
1
UCB0STE (see Notes 1, 2)
P3.1 (I/O)
P3.1/UCB0SIMO/
UCB0SDA
1
2
3
I: 0; O: 1
X
UCB0SIMO/UCB0SDA (see Notes 1, 2, 3)
P3.2 (I/O)
P3.2/UCB0SOMI/
UCB0SCL
I: 0; O: 1
X
UCB0SOMI/UCB0SCL (see Notes 1, 2, 3)
P3.3 (I/O)
P3.3/UCB0CLK
I: 0; O: 1
X
UCB0CLK (see Notes 1, 2)
NOTES: 1. X: Don’t care.
2. The pin direction is controlled by the USCI module.
3. In case the I2C functionality is selected the output drives only the logical 0 to V
level.
SS
67
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
port P3, P3.4 to P3.7, input/output with Schmitt-trigger
Pad Logic
DV
DV
SS
SS
TBOUTH
P3DIR.x
0
1
Direction
0: Input
1: Output
P3OUT.x
0
1
Module X OUT
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
Bus
Keeper
P3SEL.x
P3IN.x
EN
EN
D
Module X IN
Note: x = 4,5,6,7
Port P3 (P3.4 to P3.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P3.X)
X
FUNCTION
P3DIR.x
P3SEL.x
P3.4/TB3
4
P3.4 (I/O)
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
Timer_B7.CCI3A and Timer_B7.CCI3B
Timer_B7.TB3 (see Note 1)
P3.5 (I/O)
0
1
P3.5/TB4
P3.6/TB5
P3.7/TB6
5
6
7
I: 0; O: 1
Timer_B7.CCI4A and Timer_B7.CCI4B
Timer_B7.TB4 (see Note 1)
P3.6 (I/O)
0
1
I: 0; O: 1
Timer_B7.CCI5A and Timer_B7.CCI5B
Timer_B7.TB5 (see Note 1)
P3.7 (I/O)
0
1
I: 0; O: 1
Timer_B7.CCI6A and Timer_B7.CCI6B
Timer_B7.TB6 (see Note 1)
0
1
NOTES: 1. Setting TBOUTH causes all Timer_B outputs to be set to high impedance.
68
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
port P4, P4.0 to P4.1, input/output with Schmitt-trigger
Pad Logic
DV
SS
DV
SS
DV
SS
P4DIR.x
0
1
Direction
0: Input
1: Output
Direction control
from Module X
0
1
P4OUT.x
Module X OUT
P4.1/URXD1
P4.0/UTXD1
Bus
Keeper
P4SEL.x
EN
P4IN.x
Module X IN
Note: x = 0,1
EN
D
Port P4 (P4.0 to P4.1) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P4.X)
X
FUNCTION
P4DIR.x
I: 0; O: 1
X
P4SEL.x
P4.0/UTXD1
0
P4.0 (I/O)
0
1
0
1
USART1.UTXD1 (see Notes 1, 2)
P4.1 (I/O)
P4.1/URXD1
1
I: 0; O: 1
X
USART1.URXD1 (see Notes 1, 2)
NOTES: 1. X: Don’t care.
2. When in USART1 mode, P4.0 is set to output, P4.1 is set to input.
69
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
port P4, P4.2 to P4.7, input/output with Schmitt-trigger
Pad Logic
LCDS32/36
Segment Sy
DV
SS
P4DIR.x
0
1
Direction
0: Input
1: Output
Direction control
from Module X
0
1
P4OUT.x
Module X OUT
P4.7/UCA0RXD/S34
P4.6/UCA0TXD/S35
P4.5/UCLK1/S36
P4.4/SOMI1/S37
P4.3/SIMO1/S38
P4.2/STE1/S39
Bus
Keeper
P4SEL.x
EN
P4IN.x
EN
D
Module X IN
Note :x = 2,3,4,5,6,7
= 34,35,36,37,38,39
y
Port P4 (P4.2 to P4.5) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P4.X)
X
FUNCTION
P4DIR.x
P4SEL.x
LCDS36
P4.2/STE1/S39
2
P4.2 (I/O)
I: 0; O: 1
0
1
X
0
1
X
0
1
X
0
1
X
0
0
1
0
0
1
0
0
1
0
0
1
USART1.STE1
S39 (see Note 1)
P4.3 (I/O)
0
X
P4.3/SIMO/S38
P4.4/SOMI/S37
P4.5/SOMI/S36
3
4
5
I: 0; O: 1
USART1.SIMO1 (see Notes 1, 2)
S38 (see Note 1)
0
X
P4.4 (I/O)
I: 0; O: 1
USART1.SOMI1 (see Notes 1, 2)
S37 (see Note 1)
0
X
P4.5 (I/O)
I: 0; O: 1
USART1.UCLK1 (see Notes 1, 2)
S36 (see Note 1)
0
X
NOTES: 1. X: Don’t care.
2. The pin direction is controlled by the USART1 module.
70
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
Port P4 (P4.6 to P4.7) pin functions (continued)
CONTROL BITS / SIGNALS
PIN NAME (P4.X)
X
FUNCTION
P4DIR.x
P4SEL.x
LCDS32
P4.6/UCA0TXD/S35
6
P4.6 (I/O)
I: 0; O: 1
0
1
X
0
1
X
0
0
1
0
0
1
USCI_A0.UCA0TXD (see Notes 1, 2)
S35 (see Note 1)
X
X
P4.7/UCA0RXD/S34
7
P4.7 (I/O)
I: 0; O: 1
USCI_A0.UCA0RXD (see Notes 1, 2)
S34 (see Note 1)
0
X
NOTES: 1. X: Don’t care.
2. When in USCI mode, P4.6 is set to output, P4.7 is set to input.
71
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
port P5, P5.0, input/output with Schmitt-trigger
#
INCH=13
Pad Logic
#
A13
LCDS0
Segment Sy
P5DIR.x
0
1
Direction
0: Input
1: Output
0
1
P5OUT.x
DV
SS
P5.0/S1/A13/OA1I1
Bus
Keeper
P5SEL.x
EN
P5IN.x
Note: x = 0
y
= 1
+
OA1
−
72
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
Port P5 (P5.0) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P5.X)
X
FUNCTION
P5DIR.x
P5SEL.x
INCHx
OANx(OA1)
LCDS0
P5.0/S1/A13/OA1I1
0
P5.0 (I/O) (see Note 1)
OAI11 (see Note 1)
I: 0; O: 1
0
X
1
0
1
X
X
X
1
0
0
X
1
1
X
X
X
X
A13 (see Notes 1, 3)
S1 enabled (see Note 1)
S1 disabled (see Note 1)
13
X
X
X
X
X
NOTES: 1. X: Don’t care.
2. N/A: Not available or not applicable.
3. Setting the P5SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
73
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
port P5, P5.1, input/output with Schmitt-trigger
#
INCH=12
Pad Logic
#
A12
LCDS0
Segment Sy
DAC12.1OPS
P5DIR.x
0
1
Direction
0: Input
1: Output
0
1
P5OUT.x
DV
SS
P5.1/S0/A12/DAC1
Bus
Keeper
P5SEL.x
P5IN.x
EN
Note: x = 1
y= 0
0
1
2
DV
SS
DAC1
0 if DAC12.1AMPx = 0 and DAC12.1OPS= 1
1 if DAC12.1AMPx = 1 and DAC12.1OPS= 1
2 if DAC12.1AMPx > 1 and DAC12.1OPS= 1
74
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
Port P5 (P5.1) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P5.X)
X
FUNCTION
P5DIR.x
P5SEL.x
INCHx
DAC12.1OPS DAC12.1AMPx
LCDS0
P5.0/S0/A12/DAC1
1
P5.0 (I/O) (see Note 1)
I: 0; O: 1
0
X
0
1
1
1
X
0
DAC1 high impedance
(see Note 1)
X
X
X
X
X
X
X
X
X
0
X
X
X
DVSS (see Note 1)
1
DAC1 output
(see Note 1)
> 1
A12 (see Notes 1, 2)
X
X
X
1
0
1
12
X
0
0
0
X
X
X
0
1
1
S0 enabled (see Note 1)
S0 disabled (see Note 1)
X
NOTES: 1. X: Don’t care.
2. Setting theP5SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
75
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
port P5, P5.2 to P5.4, input/output with Schmitt-trigger
Pad Logic
LCD Signal
DV
SS
P5DIR.x
P5OUT.x
0
1
Direction
0: Input
1: Output
0
1
DV
SS
P5.2/COM1
P5.3/COM2
P5.4/COM3
Bus
Keeper
P5SEL.x
EN
P5IN.x
Note: x = 2,3,4
Port P5 (P5.2 to P5.4) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P5.X)
X
FUNCTION
P5DIR.x
I: 0; O: 1
X
P5SEL.x
P5.2/COM1
2
P5.2 (I/O)
0
1
0
1
0
1
COM1 (see Note 1)
P5.3 (I/O)
P5.3/COM2
P5.4/COM3
3
4
I: 0; O: 1
X
COM2 (see Note 1)
P5.4 (I/O)
I: 0; O: 1
X
COM3 (see Note 1)
NOTES: 1. X: Don’t care.
76
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
port P5, P5.5 to P5.7, input/output with Schmitt-trigger
Pad Logic
LCD Signal
DV
SS
P5DIR.x
P5OUT.x
0
1
Direction
0: Input
1: Output
0
1
DV
SS
P5.5/R03
P5.6/LCDREF/R13
P5.7/R03
Bus
Keeper
P5SEL.x
EN
P5IN.x
Note:x = 5,6,7
Port P5 (P5.5 to P5.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P5.X)
X
FUNCTION
P5DIR.x
I: 0; O: 1
X
P5SEL.x
P5.5/R03
5
P5.5 (I/O)
0
1
0
1
0
1
R03 (see Note 1)
P5.6 (I/O)
P5.6/LCDREF/R13
P5.7/R03
6
7
I: 0; O: 1
X
R13 or LCDREF (see Notes 1, 2)
P5.7 (I/O)
I: 0; O: 1
X
R03 (see Note 1)
NOTES: 1. X: Don’t care.
2. External reference for the LCD_A charge pump is applied when VLCDREFx = 01. Otherwise R13 is selected.
77
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
port P6, P6.0, P6.2, and P6.4, input/output with Schmitt-trigger
#
INCH=0/2/4
Pad Logic
#
Ay
P6DIR.x
0
1
Direction
0: Input
1: Output
P6.0/A0/OA0I0
P6.2/A2/OA0I1
P6.4/A4/OA1I0
0
1
P6OUT.x
DV
SS
Bus
Keeper
P6SEL.x
EN
P6IN.x
Note: x = 0,2,4
y= 0,1
Signal from or to ADC12
#
+
OA0/1
−
78
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
Port P6 (P6.0, P6.2, and P6.4) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
X
FUNCTION
OAPx (OA0)
OANx (OA0)
OAPx (OA1)
OANx(OA1)
P6DIR.x
P6SEL.x
INCHx
P6.0/A0/OA0I0
0
P6.0 (I/O) (see Note 1)
OA0I0 (see Note 1)
A0 (see Notes 1, 3)
P6.2 (I/O) (see Note 1)
OA0I1 (see Note 1)
A2 (see Notes 1, 3)
P6.4 (I/O) (see Note 1)
OA1I0 (see Note 1)
A4 (see Notes 1, 3)
I: 0; O: 1
0
X
1
0
X
1
0
X
1
X
0
X
X
X
X
X
X
X
0
X
X
0
X
X
X
X
1
P6.2/A2/OA0I1
P6.4/A4/OA1I0
2
4
I: 0; O: 1
X
X
2
X
X
X
X
X
X
I: 0; O: 1
X
X
4
X
X
X
NOTES: 1. X: Don’t care.
2. N/A: Not available or not applicable.
3. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
79
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
port P6, P6.1, P6.3, and P6.5 input/output with Schmitt-trigger
#
INCH=1/3/5
Pad Logic
#
Ay
P6DIR.x
0
1
Direction
0:Input
1:Output
P6.1/A1/OA0O
P6.3/A3/OA1O
P6.5/A5/OA2O
0
1
P6OUT.x
DV
SS
Bus
Keeper
P6SEL.x
P6IN.x
EN
OAPMx> 0
OAADC1
+
OAy
−
Note: x = 1,3,5
y= 0,1,2
Signal from or to ADC12
#
80
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
Port P6 (P6.1, P6.3, and P6.5) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
X
FUNCTION
P6DIR.x
P6SEL.x
OAADC1
OAPMx
INCHx
P6.1/A1/OA0O
1
P6.1 (I/O) (see Note 1)
OA0O (see Notes 1, 4)
A1 (see Notes 1, 3)
I: 0; O: 1
0
X
1
0
X
1
0
X
1
X
1
X
> 0
X
X
X
1
X
X
X
X
1
P6.3/A3/OA1O
P6.5/A5/OA2O
3
5
P6.3 (I/O) (see Note 1)
OA1O (see Notes 1, 4)
A3 (see Notes 1, 3)
I: 0; O: 1
X
X
X
3
X
> 0
X
X
X
X
1
P6.5 (I/O) (see Note 1)
OA2O (see Notes 1, 4)
A5 (see Notes 1, 3)
I: 0; O: 1
X
X
X
5
X
X
> 0
X
X
NOTES: 1. X: Don’t care.
2. N/A: Not available or not applicable.
3. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. Setting the OAADC1 bit or setting OAFCx = 00 will cause the operational amplifier to be present at the pin as well as internally
connected to the corresponding ADC12 input.
81
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
port P6, P6.6, input/output with Schmitt-trigger
#
INCH=6
Pad Logic
#
A6
P6DIR.x
P6OUT.x
0
1
Direction
0: Input
1: Output
P6.6/A6/DAC0/OA2I0
0
1
DV
SS
Bus
Keeper
P6SEL.x
DAC12.0AMP> 0
DAC12.0OPS
EN
P6IN.x
Note: x = 6
#
Signal from or to ADC12
+
OA2
−
0
DVSS
1
2
DAC0
0 if DAC12.0AMPx= 0 and DAC12.0OPS = 0
1 if DAC12.0AMPx= 1 and DAC12.0OPS = 0
2 if DAC12.0AMPx> 1 and DAC12.0OPS = 0
82
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
Port P6 (P6.6) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
X
FUNCTION
OAPx (OA2)
OANx (OA2)
P6DIR.x
P6SEL.x
INCHx
DAC12.0OPS DAC12.0AMPx
P6.6/A6/DAC0/OA2I0
6
P6.6 (I/O) (see Note 1)
I: 0; O: 1
0
X
X
X
X
X
X
X
1
0
0
0
X
0
X
DAC0 high impedance
(see Note 1)
X
X
X
X
X
X
DVSS (see Note 1)
1
DAC0 output
(see Note 1)
>1
A6 (see Notes 1, 2)
OA2I0 (see Note 1)
X
X
1
6
0
X
X
X
X
X
0
X
NOTES: 1. X: Don’t care.
2. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
83
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
port P6, P6.7, input/output with Schmitt-trigger
To SVS Mux
#
INCH=7
Pad Logic
#
A7
P6DIR.x
P6OUT.x
0
1
Direction
0: Input
1: Output
0
1
DV
SS
P6.7/A7/DAC1/SVSIN
Bus
Keeper
P6SEL.x
VLD =15
EN
DAC12.1AMP> 0
DAC12.1OPS
P6IN.x
Note: x = 7
#
Signal from or to ADC12
0
DVSS
1
2
DAC1
0 if DAC12.1AMPx = 0 and DAC12.1OPS= 0
1 if DAC12.1AMPx = 1 and DAC12.1OPS= 0
2 if DAC12.1AMPx > 1 and DAC12.1OPS= 0
84
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
Port P6 (P6.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
X
FUNCTION
P6DIR.x
P6SEL.x
INCHx
DAC12.1OPS DAC12.1AMPx
P6.7/A7/DAC1/SVSIN
7
P6.7 (I/O) (see Note 1)
I: 0; O: 1
0
X
1
0
0
0
X
DAC1 high impedance
(see Note 1)
X
X
X
X
X
X
X
X
X
0
DVSS (see Note 1)
1
DAC1 output
(see Note 1)
> 1
A7 (see Notes 1, 2)
X
0
1
1
7
0
X
1
X
X
SVSIN (see Notes 1,3)
NOTES: 1. X: Don’t care.
2. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
3. Setting VLDx = 15 will also cause the external SVSIN to be used. In this case, the P6SEL.x bit is a do not care.
85
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
port P7, P7.0 − P7.3, input/output with Schmitt-trigger
Pad Logic
LCDS28/32
Segment Sy
DV
SS
P7DIR.x
0
1
Direction
0: Input
1: Output
Direction control
from Module X
0
1
P7OUT.x
Module X OUT
P7.3/UCA0CLK/S30
P7.2/UCA0SOMI/S31
P7.1/UCA0SIMO/S32
P7.0/UCA0STE/S33
Bus
Keeper
P7SEL.x
EN
P7IN.x
EN
D
Module X IN
Note: x = 0,1,2,3
y= 30,31,32,33
Port P7 (P7.0 to P7.1) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P7.X)
X
FUNCTION
P7DIR.x
P7SEL.x
LCDS32
P7.0/UCA0STE/S33
0
P7.0 (I/O)
I: 0; O: 1
0
1
X
0
1
X
0
0
1
0
0
1
USCI_A0.UCA0STE (see Notes 1, 2)
S33 (see Note 1)
X
X
P7.1/UCA0SIMO/S32
1
P7.1 (I/O)
I: 0; O: 1
USCI_A0.UCA0SIMO (see Notes 1, 2)
S32 (see Note 1)
X
X
NOTES: 1. X: Don’t care.
2. The pin direction is controlled by the USCI module.
86
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
Port P7 (P7.2 to P7.3) pin functions (continued)
CONTROL BITS / SIGNALS
PIN NAME (P7.X)
X
FUNCTION
P7DIR.x
P7SEL.x
LCDS28
P7.2/UCA0SOMI/S31
2
P7.2 (I/O)
I: 0; O: 1
0
1
X
0
1
X
0
0
1
0
0
1
USCI_A0.UCA0SOMI (see Notes 1, 2)
S31 (see Note 1)
X
X
P7.3/UCA0CLK/S30
3
P7.3 (I/O)
I: 0; O: 1
USCI_A0.UCA0CLK (see Notes 1, 2)
S30 (see Note 1)
X
X
NOTES: 1. X: Don’t care.
2. The pin direction is controlled by the USCI module.
87
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
port P7, P7.4 − P7.7, input/output with Schmitt-trigger
Pad Logic
LCDS24/28
Segment Sy
DV
SS
P7DIR.x
0
1
Direction
0: Input
1: Output
0
1
P7OUT.x
DV
SS
P7.7/S26
P7.6/S27
P7.5/S28
P7.4/S29
Bus
Keeper
P7SEL.x
EN
P7IN.x
Note:x = 4,5,6,7
y= 26,27,28,29
Port P7 (P7.4 to P7.5) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P7.X)
X
FUNCTION
P7DIR.x
P7SEL.x
LCDS28
P7.4/S29
4
P7.4 (I/O)
I: 0; O: 1
0
X
0
0
1
0
1
S29 (see Note 1)
P7.5 (I/O)
X
I: 0; O: 1
X
P7.5/S28
5
S28 (see Note 1)
X
NOTES: 1. X: Don’t care.
88
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
Port P7 (P7.6 to P7.7) pin functions (continued)
CONTROL BITS / SIGNALS
PIN NAME (P7.X)
X
FUNCTION
P7DIR.x
I: 0; O: 1
X
P7SEL.x
LCDS24
P7.6/S27
6
P7.6 (I/O)
0
X
0
0
1
0
1
S27 (see Note 1)
P7.7 (I/O)
P7.7/S26
7
I: 0; O: 1
X
S26 (see Note 1)
X
NOTES: 1. X: Don’t care.
89
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
port P8, P8.0 − P8.7, input/output with Schmitt-trigger
Pad Logic
LCDS16/20/24
Segment Sy
DV
SS
P8DIR.x
P8OUT.x
0
1
Direction
0: Input
1: Output
0
1
DV
SS
P8.7/S18
P8.6/S19
P8.5/S20
P8.4/S21
P8.3/S22
P8.2/S23
P8.1/S24
P8.0/S25
Bus
Keeper
P8SEL.x
P8IN.x
EN
Note: x = 0,1,2,3,4,5,6,7
y= 25,24,23,22,21,20,19,18
Port P8 (P8.0 to P8.1) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P8.X)
X
FUNCTION
P8DIR.x
P8SEL.x
LCDS16
P8.0/S18
0
P8.0 (I/O)
I: 0; O: 1
0
X
0
0
1
0
1
S18 (see Note 1)
P8.0 (I/O)
X
I: 0; O: 1
X
P8.1/S19
0
S19 (see Note 1)
X
NOTES: 1. X: Don’t care.
90
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
Port P8 (P8.2 to P8.5) pin functions (continued)
CONTROL BITS / SIGNALS
PIN NAME (P8.X)
X
FUNCTION
P8DIR.x
I: 0; O: 1
X
P8SEL.x
LCDS20
P8.2/S20
2
P8.2 (I/O)
0
X
0
0
1
0
1
0
1
0
1
S20 (see Note 1)
P8.3 (I/O)
P8.3/S21
P8.4/S22
P8.5/S23
3
4
5
I: 0; O: 1
X
S21 (see Note 1)
P8.4 (I/O)
X
0
I: 0; O: 1
X
S22 (see Note 1)
P8.5 (I/O)
X
0
I: 0; O: 1
X
S23 (see Note 1)
X
NOTES: 1. X: Don’t care.
Port P8 (P8.6 to P8.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P8.X)
X
FUNCTION
P8DIR.x
P8SEL.x
LCDS24
P8.6/S24
6
P8.6 (I/O)
I: 0; O: 1
0
X
0
0
1
0
1
S24 (see Note 1)
P8.7 (I/O)
X
I: 0; O: 1
X
P8.7/S25
7
S25 (see Note 1)
X
NOTES: 1. X: Don’t care.
91
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
port P9, P9.0 − P9.7, input/output with Schmitt-trigger
Pad Logic
LCDS8/12/16
Segment Sy
DV
SS
P9DIR.x
0
1
Direction
0:Input
1:Output
0
1
P9OUT.x
DV
SS
P9.7/S10
P9.6/S11
P9.5/S12
P9.4/S13
P9.3/S14
P9.2/S15
P9.1/S16
P9.0/S17
Bus
Keeper
P9SEL.x
P9IN.x
EN
Note: x = 0,1,2,3,4,5,6,7
y= 17,16,15,14,13,12,11,10
Port P9 (P9.0 to P9.1) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P9.X)
X
FUNCTION
P9DIR.x
P9SEL.x
LCDS16
P9.0/S17
0
P9.0 (I/O)
I: 0; O: 1
0
X
0
0
1
0
1
S17 (see Note 1)
P9.1 (I/O)
X
I: 0; O: 1
X
P9.1/S16
1
S16 (see Note 1)
X
NOTES: 1. X: Don’t care.
92
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
Port P9 (P9.2 to P9.5) pin functions (continued)
CONTROL BITS / SIGNALS
PIN NAME (P9.X)
X
FUNCTION
P9DIR.x
I: 0; O: 1
X
P9SEL.x
LCDS12
P9.2/S20
2
P9.2 (I/O)
0
X
0
0
1
0
1
0
1
0
1
S15 (see Note 1)
P9.3 (I/O)
P9.3/S21
P9.4/S22
P9.5/S23
3
4
5
I: 0; O: 1
X
S14 (see Note 1)
P9.4 (I/O)
X
0
I: 0; O: 1
X
S13 (see Note 1)
P9.5 (I/O)
X
0
I: 0; O: 1
X
S12 (see Note 1)
X
NOTES: 1. X: Don’t care.
Port P9 (P9.6 to P9.7) pin functions (continued)
CONTROL BITS / SIGNALS
PIN NAME (P9.X)
X
FUNCTION
P9DIR.x
P9SEL.x
LCDS8
P9.6/S24
6
P9.6 (I/O)
I: 0; O: 1
0
X
0
0
1
0
1
S11 (see Note 1)
P9.7 (I/O)
X
I: 0; O: 1
X
P9.7/S25
7
S10 (see Note 1)
X
NOTES: 1. X: Don’t care.
93
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
port P10, P10.0 − P10.5, input/output with Schmitt-trigger
Pad Logic
LCDS4/8
Segment Sy
DV
SS
P10DIR.x
P10OUT.x
0
1
Direction
0: Input
1: Output
0
1
DV
SS
P10.5/S4
P10.4/S5
P10.3/S6
P10.2/S7
P10.1/S8
P10.0/S9
Bus
Keeper
P10SEL.x
P10IN.x
EN
Note:x = 0,1,2,3,4,5
y= 9,8,7,6,5,4
Port P10 (P10.0 to P10.1) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P10.X)
X
FUNCTION
P10DIR.x
P10SEL.x
LCDS8
P10.0/S8
0
P10.0 (I/O)
I: 0; O: 1
0
X
0
0
1
0
1
S8 (see Note 1)
P10.1 (I/O)
X
I: 0; O: 1
X
P10.1/S7
1
S7 (see Note 1)
X
NOTES: 1. X: Don’t care.
94
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
Port P10 (P10.2 to P10.5) pin functions (continued)
CONTROL BITS / SIGNALS
PIN NAME (P10.X)
X
FUNCTION
P10DIR.x
P10SEL.x
LCDS4
P10.2/S7
2
P10.2 (I/O)
I: 0; O: 1
0
X
0
0
1
0
1
0
1
0
1
S7 (see Note 1)
P10.3 (I/O)
X
P10.3/S6
P10.4/S5
P10.5/S4
3
4
5
I: 0; O: 1
S6 (see Note 1)
P10.4 (I/O)
X
I: 0; O: 1
X
X
0
S5 (see Note 1)
P10.5 (I/O)
X
0
I: 0; O: 1
X
S4 (see Note 1)
X
NOTES: 1. X: Don’t care.
95
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
port P10, P10.6, input/output with Schmitt-trigger
#
INCH=15
Pad Logic
#
A15
LCDS0
Segment Sy
P10DIR.x
P10OUT.x
0
1
Direction
0: Input
1: Output
0
1
DV
SS
P10.6/S3/A15
Bus
Keeper
P10SEL.x
EN
P10IN.x
Note: x = 6
= 3
y
Port P10 (P10.6) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P10.X)
X
FUNCTION
P10DIR.x
P10SEL.x
INCHx
LCDS0
P10.6/S3/A15
6
P5.0 (I/O) (see Note 1)
I: 0; O: 1
0
1
0
1
X
15
X
0
0
1
1
A15 (see Notes 1, 3)
X
X
X
S3 enabled (see Note 1)
S3 disabled (see Note 1)
X
NOTES: 1. X: Don’t care.
2. N/A: Not available or not applicable.
3. Setting the P10SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
96
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
port P10, P10.7, input/output with Schmitt-trigger
#
INCH=14
Pad Logic
#
A14
LCDS0
Segment Sy
P10DIR.x
P10OUT.x
0
1
Direction
0: Input
1: Output
0
1
DV
SS
P10.7/S2/A14/OA2I1
Bus
Keeper
P10SEL.x
P10IN.x
EN
Note: x = 7
y= 2
+
OA2
−
97
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
Port P10 (P10.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P10.X)
X
FUNCTION
OAPx (OA1)
OANx (OA1)
P10DIR.x
P10SEL.x
INCHx
LCDS0
P10.7/S2/A14/OA2I1
7
P10.7 (I/O) (see Note 1)
A14 (see Notes 1, 3)
I: 0; O: 1
0
1
X
0
1
X
14
X
X
X
1
0
0
0
1
1
X
X
X
X
OA2I1 (see Notes 1, 3)
S2 enabled (see Note 1)
X
X
X
S2 disabled (see Note 1)
X
NOTES: 1. X: Don’t care.
2. N/A: Not available or not applicable.
3. Setting the P10SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
98
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
Ve
/DAC0
REF+
DAC12.0OPS
DAC0_2_OA
0
1
P6.6/A6/DAC0/OA2I0
Reference Voltage to DAC1
Reference Voltage to ADC12
#
Ve REF+ /DAC0
Reference Voltage to DAC0
’0’, if DAC12CALON = 0
DAC12AMPx>1 AND DAC12OPS=1
+
1
0
−
’1’, if DAC12AMPx>1
’1’, if DAC12AMPx=1
DAC12OPS
#
If the reference of DAC0 is taken from pin VeREF+ /DAC0, unpredictable voltage levels will be on pin.
In this situation, the DAC0 output is fed back to its own reference input.
99
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
input/output schematic (continued)
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
TDO
Controlled by JTAG
Controlled by JTAG
TDO/TDI
JTAG
Controlled
DV
CC
by JTAG
TDI
Burn and Test
Fuse
TDI/TCLK
CC
Test
and
DV
TMS
TCK
Emulation
Module
TMS
DV
CC
TCK
RST/NMI
Tau ~ 50 ns
Brownout
D
U
S
G
D
U
S
TCK
G
100
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋꢌꢍ ꢎ ꢁꢋ ꢇ ꢏꢐꢑ ꢀ ꢋꢒꢓꢔ ꢒꢔ ꢏꢕ ꢓꢔ ꢑꢑ ꢍꢓ
SLAS508 − APRIL 2006
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current (I
) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be
(TF)
taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 37). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition). The JTAG pins are terminated internally and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
I
(TF)
I
TDI/TCLK
Figure 37. Fuse Check Mode Current
101
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢀ ꢋ ꢌ ꢍꢎ ꢁꢋ ꢇꢏ ꢐ ꢑ ꢀꢋ ꢒ ꢓꢔꢒ ꢔꢏ ꢕꢓ ꢔꢑ ꢑꢍ ꢓ
SLAS508 − APRIL 2006
Data Sheet Revision History
Literature
Number
Summary
SLAS508
Preliminary PRODUCT PREVIEW datasheet release.
NOTE: The referring page and figure numbers are referred to the respective document revision.
102
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
Drawing
MSP430FG4616IPZ
MSP430FG4616IPZR
MSP430FG4617IPZ
MSP430FG4617IPZR
MSP430FG4618IPZ
MSP430FG4618IPZR
MSP430FG4619IPZ
MSP430FG4619IPZR
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PZ
100
100
100
100
100
100
100
100
90
1000
90
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
PZ
PZ
PZ
1000
90
PZ
PZ
1000
90
PZ
PZ
1000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
M
0,08
51
50
76
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
0,25
16,20
SQ
0,05 MIN
0°–7°
15,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2006, Texas Instruments Incorporated
相关型号:
MSP430FG478IZCAR
具有 48KB 闪存、2KB SRAM、16 位 Σ-Δ ADC、双通道 DAC、2 个运算放大器和 128 段 LCD 的 8MHz MCU | ZCA | 113 | -40 to 85
TI
©2020 ICPDF网 联系我们和版权申明