MSP430FR2311IRGYT [TI]
具有 3.75KB FRAM、运算放大器、TIA、比较器、DAC 和 10 位 ADC 的 16MHz 集成模拟微控制器 | RGY | 16 | -40 to 85;
| 型号： | MSP430FR2311IRGYT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 3.75KB FRAM、运算放大器、TIA、比较器、DAC 和 10 位 ADC 的 16MHz 集成模拟微控制器 | RGY | 16 | -40 to 85 放大器 控制器 微控制器 运算放大器 比较器 |
| 文件： | 总100页 (文件大小：1783K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MSP430FR2311, MSP430FR2310
ZHCSF32E –FEBRUARY 2016–REVISED DECEMBER 2019
MSP430FR231x 混合信号微控制器
1 器件概述
1.1 特性
1
– 耐写次数达 1015
– 抗辐射和非磁性
• 智能数字外设
次
• 嵌入式微控制器
– 频率高达 16MHz 的 16 位精简指令集计算机
(RISC) 架构
– 3.6V 至 1.8V 的宽电源电压范围（最低电源电压
受限于 SVS 电平，请参阅 SVS 规格）
• 经优化的低功耗模式（3V 时）
– 激活模式：126µA/MHz
– 红外调制逻辑
– 两个 16 位计时器，每个计时器有 3 个捕捉/比较
寄存器 (Timer_B3)
– 一个仅用作计数器的 16 位 RTC 计数器
– 16 位循环冗余校验器 (CRC)
• 增强型串行通信
– 待机模式：实时时钟 (RTC) 计数器（LPM3.5，
采用 32768Hz 晶振）0.71µA
– 关断模式 (LPM4.5)：32nA（无 SVS）
• 高性能模拟
– 增强型 USCI A (eUSCI_A) 支持 UART、IrDA 和
SPI
– 增强型 USCI B (eUSCI_B) 支持 SPI 和 I2C，并
提供重映射功能（请参阅 信号说明）
(1)
– 跨阻放大器 (TIA)
– 电流至电压转换
– 半轨输入
• 时钟系统 (CS)
– 片上 32kHz RC 振荡器 (REFO)
– 仅针对 TSSOP16 封装，将低泄漏负输入降至
5pA
– 轨至轨输出
– 带有锁频环 (FLL) 的片上 16MHz 数控振荡器
(DCO)
– 室温下的精度为 ±1%（具有片上基准）
– 片上超低频 10kHz 振荡器 (VLO)
– 片上高频调制振荡器 (MODOSC)
– 外部 32kHz 晶振 (LFXT)
– 多个输入信号选项
– 可配置的高功率和低功率模式
– 8 通道 10 位模数转换器 (ADC)
– 1.5V 的内部基准电压
– 外部高频晶体振荡器，频率高达 16MHz (HFXT)
– 可编程 MCLK 预分频器（1 至 128）
– 通过可编程预分频器（1、2、4 或 8）从 MCLK
获得的 SMCLK
– 采样与保持 200ksps
– 增强型比较器 (eCOMP)
– 集成 6 位数模转换器 (DAC) 作为基准电压
– 可编程迟滞
– 可配置的高功率和低功率模式
– 智能模拟组合 (SAC-L1)
– 支持通用运算放大器
• 通用输入/输出和引脚功能
– 20 引脚封装有 16 个 I/O
– 12 个中断引脚（8 个 P1 引脚和 4 个 P2 引脚）
可将 MCU 从 LPM 唤醒
– 所有 I/O 均为电容式触控 I/O
• 开发工具和软件
– LaunchPad™开发套件 (MSP‑EXP430FR2311)
– 目标开发板 (MSP‑TS430PW20)
• 系列成员（另请参阅 器件比较）
– 轨至轨输入和输出
– 多个输入信号选项
– 可配置的高功率和低功率模式
• 低功耗铁电 RAM (FRAM)
– 非易失性存储器容量高达 3.75KB
– 内置错误修正码 (ECC)
– 可配置的写保护
– MSP430FR2311：3.75KB 程序 FRAM 和 1KB
RAM
– 对程序、常量和存储的统一存储
– MSP430FR2310：2KB 程序 FRAM 和 1KB
RAM
(1) 以前，跨阻放大器在描述性文字、引脚名称和电阻器名称中的
缩写都是 TRI。现在将所有描述性文字中的缩写改成了 TIA，
但引脚名称和电阻器名称仍然使用 TRI。
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASE58
MSP430FR2311, MSP430FR2310
ZHCSF32E –FEBRUARY 2016–REVISED DECEMBER 2019
www.ti.com.cn
• 封装选项
– 16 引脚 TSSOP (PW16)
– 16 引脚 VQFN (RGY16)
– 20 引脚 TSSOP (PW20)
1.2 应用
•
•
•
烟雾探测器
•
•
电源监控
移动电源
个人电子产品
便携式保健和健身设备
1.3 说明
MSP430FR231x FRAM 微控制器 (MCU) 属于 MSP430™MCU 超值系列检测系列中的一员。这些器件集成
了可配置的低泄漏跨阻放大器 (TIA) 和通用运算放大器。MCU 具有功能强大的 16 位 RISC CPU、16 位寄
存器和常数发生器，有助于实现最大编码效率。数控振荡器 (DCO) 还可以让器件在不到 10µs 的时间内从低
功耗模式唤醒至活动模式。这些 MCU 的功能集 非常适合从 烟雾探测器到便携式医疗和健身配件等多种应
用。
超低功耗的 MSP430FR231x MCU 系列包含多种器件，其中配备了嵌入式非易失性 FRAM 和不同的外设
集，适用于各种检测和测量 应用中的数字输入 D 类音频放大器。该架构、FRAM 和外设与多种低功耗模式
相结合，专为在便携式无线感测应用 中延长电池使用寿命而进行了优化中的数字输入 D 类音频放大器。
FRAM 是一种非易失性存储器技术，它将 SRAM 的速度、灵活性和耐用性与闪存的稳定性和可靠性相结
合，并且总功耗更低。
MSP430FR231x MCU 由一个由各种软、硬件资源组成的生态系统提供支持，并配套提供有参考设计和代码
示例，可帮助您快速开展设计。开发套件包括 MSP‑EXP430FR2311 LaunchPad™开发套件和
MSP‑TS430PW20 20 引脚目标开发板。TI 提供免费的 MSP430Ware™ 软件，可作为 Code Composer
Studio™ IDE 台式机和云版本（位于 TI Resource Explorer）的组件。MSP430 MCU 还通过 E2E™ 社区论
坛提供广泛的在线配套资料、培训和在线支持。
有关完整的模块说明，请参阅《MSP430FR4xx 和 MSP430FR2xx 系列器件用户指南》。
器件信息(1)
封装
器件型号
MSP430FR2311IPW20
MSP430FR2310IPW20
MSP430FR2311IPW16
MSP430FR2310IPW16
MSP430FR2311IRGY
MSP430FR2310IRGY
封装尺寸(2)
TSSOP (20)
6.5mm × 4.4mm
TSSOP (16)
VQFN (16)
5mm × 4.4mm
4mm × 3.5mm
(1) 要获得最新的产品、封装和订购信息，请参见封装选项附录（节 9），或者访问德州仪器 (TI) 网站
www.ti.com.cn。
(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参见机械数据（节 9中）。
CAUTION
系统级静电放电 (ESD) 保护必须符合器件级 ESD 规范，以防发生电气过载或对
数据或代码存储器造成干扰。有关更多信息，请参阅《MSP430™ 系统级 ESD
注意事项》。
1.4 功能框图
图 1-1 所示为功能框图。
2
器件概述
版权 © 2016–2019, Texas Instruments Incorporated
MSP430FR2311, MSP430FR2310
www.ti.com.cn
ZHCSF32E –FEBRUARY 2016–REVISED DECEMBER 2019
P1.x, P2.x
XIN XOUT
Cap Touch I/O
I/O Ports
P1 (1×8 IOs)
P2 (1×4 IOs)
Interrupt
XT1
ADC
FRAM
RAM
1KB
SAC0
TRI0
eCOMP0
DVCC
DVSS
8 channels,
single-ended,
10 bit,
Clock
System
Control
Power
Management
Module
3.75KB
2KB
GP only
Trans-
impedance
amplifier
with 6-bit
DAC
and Wakeup
200 ksps
PA (P1, P2)
1×16 IOs
RST/NMI
MAB
16-MHz CPU
including
16 registers
MDB
EEM
RTC
Counter
BAKMEM
SYS
TB0
TB1
eUSCI_A0
eUSCI_B0
(SPI, I2C)
CRC16
TCK
TMS
16-bit
cyclic
redundancy
check
16-bit
Real-Time
Clock
32 Bytes
Backup
Memory
JTAG
SBW
Timer_B
3 CC
Registers
Timer_B
3 CC
Registers
TDI/TCLK
TDO
(UART,
IrDA, SPI)
SBWTCK
SBWTDIO
Watchdog
LPM3.5 Domain
图 1-1. MSP430FR231x 功能方框图
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MCU 的主电源对 DVCC 和 DVSS 分别为数字模块和模拟模块供电。推荐的旁路电容和去耦电容分别为
4.7μF 至 10μF 和 0.1μF，精度为 ±5%。
P1 的 8 个引脚和 P2 的 4 个引脚均具备引脚中断功能，可将 MCU 从所有低功耗模式 (LPM) 唤醒（包括
LPM4、LPM3.5 和 LPM4.5）。
每个 Timer_B3 具有三个捕捉/比较寄存器。仅 CCR1 和 CCR2 从外部连接。CCR0 寄存器仅用于内部周
期时序和生成中断。
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在 LPM3.5 模式下，RTC 计数器与备用存储器可继续工作，而其余外设停止工作。
所有通用 I/O 均可配置为电容式触控 I/O。
版权 © 2016–2019, Texas Instruments Incorporated
器件概述
3
MSP430FR2311, MSP430FR2310
ZHCSF32E –FEBRUARY 2016–REVISED DECEMBER 2019
www.ti.com.cn
内容
1
器件概述.................................................... 1
1.1 特性 ................................................... 1
1.2 应用 ................................................... 2
1.3 说明 ................................................... 2
1.4 功能框图 .............................................. 2
修订历史记录............................................... 5
Device Comparison ..................................... 7
3.1 Related Products ..................................... 7
Terminal Configuration and Functions.............. 8
4.1 Pin Diagrams ......................................... 8
4.2 Pin Attributes ........................................ 10
4.3 Signal Descriptions.................................. 12
4.4 Pin Multiplexing ..................................... 14
4.5 Buffer Type.......................................... 14
4.6 Connection of Unused Pins ......................... 14
Specifications ........................................... 15
5.1 Absolute Maximum Ratings ........................ 15
5.2 ESD Ratings ........................................ 15
5.3 Recommended Operating Conditions............... 15
6
Detailed Description ................................... 44
6.1 Overview ............................................ 44
6.2 CPU ................................................. 44
6.3 Operating Modes.................................... 44
6.4 Interrupt Vector Addresses.......................... 46
6.5 Memory Organization ............................... 47
6.6 Bootloader (BSL).................................... 47
6.7 JTAG Standard Interface............................ 48
6.8 Spy-Bi-Wire Interface (SBW)........................ 48
6.9 FRAM................................................ 48
6.10 Memory Protection .................................. 49
6.11 Peripherals .......................................... 50
6.12 Input/Output Diagrams .............................. 68
6.13 Device Descriptors (TLV) ........................... 72
6.14 Identification ......................................... 73
Applications, Implementation, and Layout........ 74
2
3
4
5
7
8
7.1
Device Connection and Layout Fundamentals...... 74
7.2
Peripheral- and Interface-Specific Design
Information .......................................... 77
7.3 Typical Applications ................................. 78
器件和文档支持 .......................................... 79
8.1 使用入门............................................. 79
8.2 器件命名规则 ........................................ 79
8.3 工具和软件 .......................................... 80
8.4 文档支持............................................. 82
8.5 相关链接............................................. 83
8.6 社区资源............................................. 83
8.7 商标.................................................. 83
8.8 静电放电警告 ........................................ 83
8.9 Glossary ............................................. 83
机械、封装和可订购信息................................ 84
5.4
Active Mode Supply Current Into VCC Excluding
External Current..................................... 16
5.5 Active Mode Supply Current Per MHz .............. 16
5.6
5.7
5.8
5.9
Low-Power Mode LPM0 Supply Currents Into VCC
Excluding External Current.......................... 16
Low-Power Mode LPM3 and LPM4 Supply Currents
(Into VCC) Excluding External Current .............. 17
Low-Power Mode LPMx.5 Supply Currents (Into
VCC) Excluding External Current.................... 18
Production Distribution of LPM Supply Currents.... 19
5.10 Typical Characteristics – Current Consumption Per
Module .............................................. 20
5.11 Thermal Resistance Characteristics ................ 20
5.12 Timing and Switching Characteristics............... 21
9
4
内容
版权 © 2016–2019, Texas Instruments Incorporated
MSP430FR2311, MSP430FR2310
www.ti.com.cn
ZHCSF32E –FEBRUARY 2016–REVISED DECEMBER 2019
2 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
从修订版本 D 更改为修订版本 E
Changes from August 29, 2018 to December 9, 2019
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Updated Section 3.1, Related Products ........................................................................................... 7
Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in
Section 5.3, Recommended Operating Conditions ............................................................................. 15
Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in
Section 5.3, Recommended Operating Conditions ............................................................................. 15
Changed the note that begins "A capacitor tolerance of ±20% or better is required..." in Section 5.3,
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Recommended Operating Conditions ............................................................................................ 15
Combined former sections 5.8 and 5.10 to Section 5.9, Production Distribution of LPM Supply Currents ............. 19
Corrected "SVS Enabled" test condition on Figure 5-2, LPM3.5 Supply Current vs Temperature ...................... 19
Added the note "See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing" to
Table 5-3, XT1 Crystal Oscillator (Low Frequency) ............................................................................ 23
Changed the note that begins "Requires external capacitors at both terminals..." in Table 5-3, XT1 Crystal
Oscillator (Low Frequency) ........................................................................................................ 23
Added the tTB,cap parameter in Table 5-13, Timer_B............................................................................ 30
Changed the parameter symbol from RI to RI,MUX in Table 5-20, ADC, Power Supply and Input Range Conditions.. 36
Corrected the test conditions for the RI,MUX parameter in Table 5-20, ADC, Power Supply and Input Range
Conditions ............................................................................................................................ 36
Added RI,Misc TYP value of 34 kΩ in Table 5-20, ADC, Power Supply and Input Range Conditions..................... 36
Added formula for RI in Table 5-21, ADC, 10-Bit Timing Parameters........................................................ 36
Added the note that begins "tSample = ln(2n+1) × τ ..." in Table 5-21, ADC, 10-Bit Timing Parameters.................... 36
Corrected bitfield from RTCCLK to RTCCKSEL in Table 6-8, Clock Distribution .......................................... 51
Corrected bitfield from IRDSEL to IRDSSEL in Section 6.11.8, Timers (Timer0_B3, Timer1_B3) , in the
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description that starts "The interconnection of Timer0_B3 and ..." ........................................................... 54
Added P1SELC information in Table 6-31, Port P1, P2 Registers (Base Address: 0200h) .............................. 65
Added P2SELC information in Table 6-31, Port P1, P2 Registers (Base Address: 0200h) .............................. 65
Added note to "ADC calibration" in Table 6-46, Device Descriptors ......................................................... 72
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从修订版本 C 更改为修订版本 D
Changes from September 12, 2017 to August 28, 2018
Page
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Updated Section 3.1, Related Products ........................................................................................... 7
Combined former sections 5.8 and 5.10 to Section 5.9, Production Distribution of LPM Supply Currents ............. 19
Added note to VSVSH- and VSVSH+ parameters in Table 5-1, PMM, SVS and BOR.......................................... 21
Added the tTB,cap parameter in Table 5-13, Timer_B............................................................................ 30
Corrected ADCINCHx column heading in Table 6-16, ADC Channel Connections ........................................ 58
更新了节 8.2器件命名规则 中的文本和图 ........................................................................................ 79
从修订版本 B 更改为修订版本 C
Changes from June 1, 2016 to September 11, 2017
Page
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更正了“关断模式 (LPM4.5)” 特性 列表项中的电流................................................................................ 1
根据测试数据，低泄漏输入从 50pA 降为 5pA .................................................................................... 1
Added Section 3.1, Related Products ............................................................................................. 7
Combined former sections 5.8 and 5.10 to Section 5.9, Production Distribution of LPM Supply Currents ............. 19
Added the tTB,cap parameter in Table 5-13, Timer_B............................................................................ 30
Removed ADCDIV from the formula for the TYP value in the second row of the tCONVERT parameter in Table 5-
21, ADC, 10-Bit Timing Parameters (removed because ADCCLK is after division)........................................ 36
Changed the entries for eUSCI_A0 and eUSCI_B0 in the LPM3 column from Off to Optional in Table 6-1,
•
版权 © 2016–2019, Texas Instruments Incorporated
修订历史记录
5
MSP430FR2311, MSP430FR2310
ZHCSF32E –FEBRUARY 2016–REVISED DECEMBER 2019
www.ti.com.cn
Operating Modes .................................................................................................................... 45
Added the sentence that begins "This device supports blank device detection..." in Section 6.6, Bootloader (BSL).. 47
Added the note "Controlled by the RTCCLK bit in the SYSCFG2 register" on Table 6-8, Clock Distribution .......... 51
Added Figure 6-1, Clock Distribution Block Diagram .......................................................................... 51
Added Figure 6-2, Timer_B Connections ........................................................................................ 55
Removed SYSBERRIV register (not supported) in Table 6-26, SYS Registers ............................................ 64
Changed from "If the RST/NMI pin is unused...with a 2.2-nF pulldown capacitor" to "If the RST/NMI pin is
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unused...with a 10-nF pulldown capacitor"....................................................................................... 76
从修订版本 A 更改为修订版本 B
Changes from March 30, 2016 to May 31, 2016
Page
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将器件状态从“产品预发布”更改为“生产数据” ..................................................................................... 1
Changed the value of fXT1 in the table note that starts "Low-power mode 4, VLO,..." ..................................... 17
Combined former sections 5.8 and 5.10 to Section 5.9, Production Distribution of LPM Supply Currents ............. 19
Added Test Conditions to module Timer_B in Section 5.10, Typical Characteristics – Current Consumption Per
Module................................................................................................................................ 20
Added "16 MHz" to the parameter description of tFLL, lock in Table 5-5, DCO FLL ......................................... 25
Added the tTB,cap parameter in Table 5-13, Timer_B............................................................................ 30
Removed ±3℃ from calibration temperatures in the table note that starts "The device descriptor structure
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contains calibration values..."...................................................................................................... 37
Changed the unit on the ENI parameter in Table 5-24, SAC0 (SAC-L1, OA) ............................................... 39
Changed the unit on the ENI parameter in Table 5-25, TIA0 .................................................................. 40
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从初始发行版更改为修订版本 A
Changes from February 23, 2016 to March 29, 2016
Page
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已将整篇文档中 TIA 模块的名称由“TRI0”更改为“TIA0” .......................................................................... 2
Changed TYP values for the IAM, FRAM(0%) parameter in Section 5.4, Active Mode Supply Current Into VCC
Excluding External Current ........................................................................................................ 16
Combined former sections 5.8 and 5.10 to Section 5.9, Production Distribution of LPM Supply Currents ............. 19
Added the tTB,cap parameter in Table 5-13, Timer_B............................................................................ 30
Changed MAX values of the tVALID,SO parameter in Table 5-18, eUSCI (SPI Slave Mode) Switching
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Characteristics ...................................................................................................................... 33
Changed the TYP value of the CMRR parameter with Test Conditions of "TRIPM = 0" from 70 dB to 80 dB in
Table 5-25, TIA0..................................................................................................................... 40
Changed the TYP value of the PSRR parameter with Test Conditions of "TRIPM = 0" from 70 dB to 80 dB in
Table 5-25, TIA0..................................................................................................................... 40
已将旧版中的开发工具支持部分替换为节 8.3，工具和软件 ................................................................... 80
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6
修订历史记录
Copyright © 2016–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR2311 MSP430FR2310
MSP430FR2311, MSP430FR2310
www.ti.com.cn
ZHCSF32E –FEBRUARY 2016–REVISED DECEMBER 2019
3 Device Comparison
Table 3-1 summarizes the features of the available family members.
Table 3-1. Device Comparison(1) (2)
PROGRAM
FRAM (KB)
SRAM
(Bytes)
10-BIT ADC SAC0
DEVICE
TB0, TB1
3 CCR(3)
3 CCR(3)
3 CCR(3)(4)
3 CCR(3)(4)
3 CCR(3)
3 CCR(3)
eUSCI_A
eUSCI_B
TIA0
eCOMP0
I/O
16
16
11
11
12
12
PACKAGE
CHANNELS
(OA)
20 PW
(TSSOP)
MSP430FR2311IPW20
MSP430FR2310IPW20
MSP430FR2311IPW16
MSP430FR2310IPW16
MSP430FR2311IRGY
MSP430FR2310IRGY
3.75
2
1024
1024
1024
1024
1024
1024
1
1
1
1
1
1
1
1
1
1
1
1
8
1
1
1
1
1
1
1
1
1
1
1
1
1
20 PW
(TSSOP)
8
8
8
8
8
1
1
1
1
1
16 PW
(TSSOP)
3.75
2
16 PW
(TSSOP)
16 RGY
(VQFN)
3.75
2
16 RGY
(VQFN)
(1) For the most current device, package, and ordering information, see the Package Option Addendum in 节 9, or see the TI website at
www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
(3) A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM
outputs.
(4) TB1 provides only one external connection (TB1.1) on this package.
3.1 Related Products
For information about other devices in this family of products or related products, see the following links.
TI 16-bit and 32-bit microcontrollers
High-performance, low-power solutions to enable the autonomous future
Products for MSP430 ultra-low-power sensing & measurement MCUs
One platform. One ecosystem. Endless possibilities.
Companion products for MSP430FR2311
Review products that are frequently purchased or used with this product.
Reference designs for MSP430FR2311
Find reference designs leveraging the best in TI technology – from analog and power management to
embedded processors
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4 Terminal Configuration and Functions
4.1 Pin Diagrams
Figure 4-1 shows the pinout of the 20-pin PW package.
P1.1/UCB0CLK/ACLK/C1/A1
P1.0/UCB0STE/SMCLK/C0/A0/Veref+
TEST/SBWTCK
1
2
20
19
18
17
16
15
14
13
12
11
P1.2/UCB0SIMO/UCB0SDA/TB0TRG/OA0-/A2/Veref-
P1.3/UCB0SOMI/UCB0SCL/OA0O/A3
P1.4/UCA0STE/TCK/OA0+/A4
P1.5/UCA0CLK/TMS/TRI0O/A5
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/TRI0-/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/TRI0+/A7/VREF+
P2.0/TB1.1/COUT
3
RST/NMI/SBWTDIO
DVCC
4
5
MSP430FR2311IPW20
MSP430FR2310IPW20
DVSS
6
P2.7/TB0CLK/XIN
7
P2.1/TB1.2
P2.6/MCLK/XOUT
8
P2.2/UCB0STE/TB1CLK
P2.5/UCB0SOMI/UCB0SCL
P2.4/UCB0SIMO/UCB0SDA
9
P2.3/UCB0CLK/TB1TRG
10
Figure 4-1. 20-Pin PW (TSSOP) (Top View)
Figure 4-2 shows the pinout of the 16-pin PW package.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P1.1/UCB0CLK/ACLK/C1/A1
P1.0/UCB0STE/SMCLK/C0/A0/Veref+
TEST/SBWTCK
P1.2/UCB0SIMO/UCB0SDA/TB0TRG/OA0-/A2/Veref-
P1.3/UCB0SOMI/UCB0SCL/OA0O/A3
P1.4/UCA0STE/TCK/OA0+/A4
RST/NMI/SBWTDIO
DVCC
P1.5/UCA0CLK/TMS/TRI0O/A5
MSP430FR2311IPW16
MSP430FR2310IPW16
TRI0-
DVSS
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/TRI0+/A7/VREF+
P2.0/TB1.1/COUT
P2.7/TB0CLK/XIN
P2.6/MCLK/XOUT
Figure 4-2. 16-Pin PW (TSSOP) (Top View)
8
Terminal Configuration and Functions
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Figure 4-3 shows the pinout of the 16-pin RGY package.
15 14 13 12 11 10
P1.2/UCB0SIMO/UCB0SDA/TB0TRG/OA0-/A2/Veref-
16
9
8
P2.1/TB1.2
MSP430FR2311IRGY
MSP430FR2310IRGY
1
P2.6/MCLK/XOUT
P1.1/UCB0CLK/ACLK/C1/A1
2
3
4
5
6
7
Figure 4-3. 16-Pin RGY (VQFN) (Top View)
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4.2 Pin Attributes
Table 4-1 lists the attributes of all pins.
Table 4-1. Pin Attributes
PIN NUMBER
RGY
SIGNAL
TYPE(3)
RESET STATE
AFTER BOR(5)
SIGNAL NAME(1) (2)
BUFFER TYPE(4) POWER SOURCE
PW20
PW16
P1.1 (RD)
UCB0CLK
ACLK
I/O
I/O
O
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
OFF
N/A
N/A
N/A
N/A
OFF
N/A
N/A
N/A
N/A
N/A
OFF
N/A
OFF
N/A
N/A
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
1
1
1
C1
I
A1
I
Analog
P1.0 (RD)
UCB0STE
SMCLK
C0
I/O
I/O
O
LVCMOS
LVCMOS
LVCMOS
Analog
2
2
2
I
A0
I
Analog
Veref+
I
Power
TEST (RD)
SBWTCK
RST (RD)
NMI
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Power
3
4
3
4
3
4
I
I/O
I
SBWTDIO
DVCC
I/O
P
5
6
5
6
5
6
DVSS
P
Power
P2.7 (RD)
TB0CLK
XIN
I/O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
7
8
7
8
–
–
–
7
8
–
–
–
I
P2.6 (RD)
MCLK
I/O
O
XOUT
O
P2.5 (RD)
UCB0SOMI
UCB0SCL
P2.4 (RD)
UCB0SIMO
UCB0SDA
P2.3 (RD)
UCB0CLK
TB1TRG
P2.2 (RD)
UCB0STE
TB1CLK
P2.1(RD)
TB1.2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
9
10
11
I/O
I/O
I
12
13
–
9
–
–
I/O
I/O
(1) Signals names with (RD) denote the reset default pin name.
(2) To determine the pin mux encodings for each pin, see Section 6.12, Input/Output Diagrams.
(3) Signal Types: I = Input, O = Output, I/O = Input or Output.
(4) Buffer Types: LVCMOS, Analog, or Power
(5) Reset States:
OFF = High-impedance input with pullup or pulldown disabled (if available)
N/A = Not applicable
10
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Table 4-1. Pin Attributes (continued)
PIN NUMBER
SIGNAL
TYPE(3)
RESET STATE
AFTER BOR(5)
SIGNAL NAME(1) (2)
BUFFER TYPE(4) POWER SOURCE
PW20
RGY
PW16
P2.0 (RD)
TB1.1
I/O
I/O
O
I/O
O
I/O
I/O
O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
OFF
N/A
N/A
OFF
N/A
N/A
N/A
N/A
N/A
N/A
N/A
OFF
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
OFF
N/A
N/A
N/A
N/A
OFF
N/A
N/A
N/A
N/A
OFF
N/A
N/A
N/A
N/A
OFF
N/A
N/A
N/A
N/A
N/A
N/A
14
10
9
COUT
P1.7 (RD)
UCA0TXD
UCA0SIMO
TB0.2
15
11
10
TDO
TRI0+
A7
I
Analog
VREF+
P1.6 (RD)
UCA0RXD
UCA0SOMI
TB0.1
O
I/O
I
Power
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
I/O
I/O
I
16
12
11
TDI
TCLK
TRI0-(6)
I
I
A6
I
Analog
–
–
12
13
TRI0-
I
Analog
P1.5 (RD)
UCA0CLK
TMS
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
17
13
TRI0O
O
I
A5
Analog
P1.4 (RD)
UCA0STE
TCK
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
18
19
14
15
14
15
OA0+
I
A4
I
Analog
P1.3 (RD)
UCB0SOMI
UCB0SCL
OA0O
I/O
I/O
I/O
O
I
LVCMOS
LVCMOS
LVCMOS
Analog
A3
Analog
P1.2 (RD)
UCB0SIMO
UCB0SDA
TB0TRG
OA0-
I/O
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
20
16
16
I
A2
I
Analog
Veref-
I
Power
(6) Not available on TSSOP-16 package
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4.3 Signal Descriptions
Table 4-2 describes the signals for all device variants and package options.
Table 4-2. Signal Descriptions
PIN NUMBER
FUNCTION
SIGNAL NAME
PIN TYPE
DESCRIPTION
PW20 RGY PW16
A0
A1
A2
A3
A4
A5
A6
A7
2
1
2
1
2
1
I
I
Analog input A0
Analog input A1
Analog input A2
Analog input A3
Analog input A4
Analog input A5
Analog input A6
Analog input A7
ADC positive reference
ADC negative reference
20
19
18
17
16
15
2
16
15
14
13
12
11
2
16
15
14
13
11
10
2
I
I
I
ADC
I
I
I
Veref+
Veref-
C0
I
20
2
16
2
16
2
I
I
Comparator input channel C0
Comparator input channel C1
Comparator output channel COUT
TIA0 positive input
eCOMP0
TIA0
C1
1
1
1
I
COUT
TRI0+
TRI0-
TRI0O
OA0+
OA0-
14
15
16
17
18
20
19
1
10
11
12
13
14
16
15
1
9
O
I
10
12
13
14
16
15
1
I
TIA0 negative input
TIA0 output
O
I
SAC0, OA positive input
SAC0, OA negative input
SAC0, OA output
SAC0
I
OA0O
ACLK
MCLK
SMCLK
XIN
O
O
O
O
I
ACLK output
8
8
8
MCLK output
Clock
2
2
2
SMCLK output
7
7
7
Input terminal for crystal oscillator
Output terminal for crystal oscillator
Spy-Bi-Wire input clock
Spy-Bi-Wire data input/output
Test clock
XOUT
SBWTCK
SBWTDIO
TCK
8
8
8
O
I
3
3
3
4
4
4
I/O
I
18
16
16
15
17
3
14
12
12
11
13
3
14
11
11
10
13
3
TCLK
TDI
I
Test clock input
Debug
I
Test data input
TDO
O
I
Test data output
TMS
Test mode select
TEST
NMI
I
Test Mode pin – selected digital I/O on JTAG pins
Nonmaskable interrupt input
4
4
4
I
System
Power
RST
4
4
4
I/O
P
P
P
Reset input, active-low
DVCC
DVSS
VREF+
5
5
5
Power supply
6
6
6
Power ground
15
11
10
Output of positive reference voltage with ground as reference
12
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FUNCTION
ZHCSF32E –FEBRUARY 2016–REVISED DECEMBER 2019
Table 4-2. Signal Descriptions (continued)
PIN NUMBER
SIGNAL NAME
P1.1
PIN TYPE
DESCRIPTION
PW20 RGY PW16
1
1
16
12
14
13
12
11
10
9
1
16
15
14
13
11
10
9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
P1.2
20
19
18
17
16
15
14
13
12
11
10
9
P1.3
(1)
(1)
P1.4
P1.5
P1.6
General-purpose I/O(1)
General-purpose I/O(1)
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
eUSCI_B0 I2C clock
eUSCI_B0 I2C data
eUSCI_B0 I2C clock
eUSCI_B0 I2C data
P1.7
GPIO
P2.0
P2.1
–
P2.2
–
–
P2.3
–
–
P2.4
–
–
P2.5
–
–
P2.6
8
8
8
P2.7
7
7
7
UCB0SCL
UCB0SDA
UCB0SCL(2)
UCB0SDA(2)
UCA0STE
UCA0CLK
UCA0SOMI
UCA0SIMO
19
20
9
15
16
–
15
16
–
I2C
10
18
17
16
15
–
–
14
13
12
11
14
13
11
10
eUSCI_A0 SPI slave transmit enable
eUSCI_A0 SPI clock input/output
eUSCI_A0 SPI slave out/master in
eUSCI_A0 SPI slave in/master out
UCB0STE
UCB0CLK
UCB0SIMO
UCB0SOMI
2
1
2
1
2
1
I/O
I/O
I/O
I/O
eUSCI_B0 slave transmit enable
eUSCI_B0 clock input/output
SPI
20
19
16
15
16
15
eUSCI_B0 SPI slave in/master out
eUSCI_B0 SPI slave out/master in
UCB0STE(2)
UCB0CLK(2)
UCB0SIMO(2)
UCB0SOMI(2)
UCA0RXD
12
11
10
9
–
–
–
–
I/O
I/O
I/O
I/O
I
eUSCI_B0 slave transmit enable
eUSCI_B0 clock input/output
–
–
eUSCI_B0 SPI slave in/master out
eUSCI_B0 SPI slave out/master in
eUSCI_A0 UART receive data
eUSCI_A0 UART transmit data
–
–
16
15
12
11
11
10
UART
UCA0TXD
O
Timer TB0 CCR1 capture: CCI1A input, compare: Out1
outputs
TB0.1
TB0.2
16
15
12
11
11
10
I/O
I/O
Timer TB0 CCR2 capture: CCI2A input, compare: Out2
outputs
TB0CLK
TB0TRG
7
7
7
I
I
Timer clock input TBCLK for TB0
20
16
16
TB0 external trigger input for TB0OUTH
Timer_B
Timer TB1 CCR1 capture: CCI1A input, compare: Out1
outputs
TB1.1
TB1.2
14
13
10
9
9
–
I/O
I/O
Timer TB1 CCR2 capture: CCI2A input, compare: Out2
outputs
TB1CLK
TB1TRG
12
11
–
–
–
–
I
I
Timer clock input TBCLK for TB1
TB1 external trigger input for TB1OUTH
(1) Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to
prevent collisions.
(2) This is the remapped functionality controlled by the USCIBRMP bit of the SYSCFG2 register. Only one selected port is valid at any time.
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Table 4-2. Signal Descriptions (continued)
PIN NUMBER
FUNCTION
SIGNAL NAME
PIN TYPE
DESCRIPTION
PW20 RGY PW16
VQFN package exposed thermal pad. TI recommends
connection to VSS
VQFN Pad
VQFN Thermal pad
–
Pad
–
.
NOTE
Functions shared with the four JTAG pins cannot be debugged if 4-wire JTAG is used for
debug.
4.4 Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and schematics of the
multiplexed ports, see Section 6.12.
4.5 Buffer Type
Table 4-3 defines the pin buffer types that are listed in Table 4-1.
Table 4-3. Buffer Type
NOMINAL
OUTPUT
DRIVE
STRENGTH
(mA)
BUFFER TYPE
(STANDARD)
NOMINAL
VOLTAGE
PU OR PD
STRENGTH
(µA)
OTHER
CHARACTERISTICS
HYSTERESIS
PU OR PD
See
See
LVCMOS
Analog
3.0 V
3.0 V
Y(1)
N
Programmable
N
Section 5.12.4 Section 5.12.4.1
See analog modules in
Section 5 for details.
N/A
N/A
SVS enables hysteresis on
DVCC.
Power (DVCC)
Power (AVCC)
3.0 V
3.0 V
N
N
N
N
N/A
N/A
N/A
N/A
(1) Only for input pins.
4.6 Connection of Unused Pins
Table 4-4 shows the correct termination of unused pins.
Table 4-4. Connection of Unused Pins(1)
PIN
Px.0 to Px.7
RST/NMI
TEST
POTENTIAL
Open
COMMENT
Set to port function, output direction (PxDIR.n = 1)
47-kΩ pullup or internal pullup selected with 10-nF (or 1.1-nF(2)) pulldown
This pin always has an internal pulldown enabled.
This pin is a high-impedance output.
DVCC
Open
TRI0-
Open
(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection
guidelines.
(2) The pulldown capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode with TI tools like
FET interfaces or GANG programmers. TI recommends a 1-nF capacitor to enable high-speed SBW communication.
14
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5 Specifications
5.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Voltage applied at DVCC pin to VSS
Voltage applied to any pin(2)
–0.3
4.1
V
VCC + 0.3
(4.1 V Max)
–0.3
V
Diode current at any device pin
±2
85
mA
°C
Maximum junction temperature, TJ
(3)
Storage temperature, Tstg
–40
125
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS
.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD) Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±250 V may actually have higher performance.
5.3 Recommended Operating Conditions
MIN
NOM
MAX UNIT
VCC
VSS
TA
Supply voltage applied at DVCC pin(1)(2)(3)(4)
Supply voltage applied at DVSS pin
Operating free-air temperature
1.8
3.6
V
V
0
–40
–40
4.7
85
85
°C
°C
µF
TJ
Operating junction temperature
Recommended capacitor at DVCC(5)
CDVCC
10
No FRAM wait states
(NWAITSx = 0)
0
0
8
fSYSTEM
Processor frequency (maximum MCLK frequency)(4)(6)
MHz
With FRAM wait states
(NWAITSx = 1)(7)
16(8)
fACLK
Maximum ACLK frequency
Maximum SMCLK frequency
40
16(8)
kHz
fSMCLK
MHz
(1) Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range. Following the
data sheet recommendation for capacitor CDVCC limits the slopes accordingly.
(2) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(3) TI recommends that power to the DVCC pin must not exceed the limits specified in Recommended Operating Conditions. Exceeding the
specified limits can cause malfunction of the device including erroneous writes to RAM and FRAM.
(4) The minimum supply voltage is defined by the SVS levels. See the SVS threshold parameters in Table 5-1.
(5) A capacitor tolerance of ±20% or better is required. A low-ESR ceramic capacitor of 100 nF (minimum) should be placed as close as
possible (within a few millimeters) to the respective pin pair.
(6) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(7) Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executed
without wait states.
(8) If clock sources such as HF crystals or the DCO with frequencies >16 MHz are used, the clock must be divided in the clock system to
comply with this operating condition.
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5.4 Active Mode Supply Current Into VCC Excluding External Current(1)
FREQUENCY (fMCLK = fSMCLK
)
1 MHz
0 WAIT STATES
(NWAITSx = 0)
8 MHz
0 WAIT STATES
(NWAITSx = 0)
16 MHz
1 WAIT STATE
(NWAITSx = 1)
EXECUTION
MEMORY
TEST
CONDITIONS
PARAMETER
UNIT
TYP
474
516
196
205
219
MAX
TYP
2639
2919
585
MAX
TYP
3156
3205
958
MAX
3.0 V, 25°C
3.0 V, 85°C
3.0 V, 25°C
3.0 V, 85°C
3.0 V, 25°C
FRAM
0% cache hit ratio
IAM, FRAM(0%)
µA
FRAM
100% cache hit ratio
IAM, FRAM(100%)
µA
µA
598
974
(2)
IAM, RAM
RAM
750
1250
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. Characterized with program executing typical data
processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency
Program and data entirely reside in FRAM. All execution is from FRAM.
(2) Program and data reside entirely in RAM. All execution is from RAM. No access to FRAM.
5.5 Active Mode Supply Current Per MHz
VCC = 3.0 V, TA = 25°C (unless otherwise noted)
PARAMETER
Active mode current consumption per MHz, [(IAM 75% cache hit rate at 8 MHz) –
execution from FRAM, no wait states(1)
(IAM 75% cache hit rate at 1 MHz)] / 7 MHz
(1) All peripherals are turned on in default settings.
TEST CONDITIONS
TYP
UNIT
dIAM,FRAM/df
126
µA/MHz
5.6 Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
(2)
VCC = 3.0 V, TA = 25°C (unless otherwise noted)(1)
FREQUENCY (fSMCLK
8 MHz
)
PARAMETER
VCC
1 MHz
TYP MAX
16 MHz
TYP MAX
UNIT
TYP
307
318
MAX
2.0 V
3.0 V
158
169
415
427
ILPM0
µA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Current for watchdog timer clocked by SMCLK included.
fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK at specified frequency.
16
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5.7 Low-Power Mode LPM3 and LPM4 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (see Figure 5-1)
–40°C
TYP MAX
25°C
TYP
85°C
TYP
PARAMETER
VCC
UNIT
µA
MAX
MAX
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
1.01
0.99
0.88
0.86
0.96
0.94
0.50
0.48
0.34
0.34
0.48
0.48
0.89
0.88
1.16
1.13
1.02
1.00
1.11
1.09
0.60
0.59
0.45
0.44
0.59
0.58
1.04
1.02
2.53
2.49
2.39
2.35
2.49
2.45
1.93
1.91
1.77
1.75
1.91
1.89
2.41
2.38
5.25
ILPM3,XT1
Low-power mode 3, includes SVS(2) (3) (4)
Low-power mode 3, VLO, excludes SVS(5)
Low-power mode 3, RTC, excludes SVS(6)
Low-power mode 4, includes SVS(7)
Low-power mode 4, excludes SVS(7)
5.06
ILPM3,VLO
µA
ILPM3, RTC
ILPM4, SVS
ILPM4
µA
µA
µA
Low-power mode 4, RTC is sourced from VLO,
excludes SVS(8)
ILPM4, RTC, VLO
µA
Low-power mode 4, RTC is sourced from XT1,
excludes SVS(6)(9)
ILPM4, RTC, XT1
µA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Not applicable for devices with HF crystal oscillator only.
(3) Characterized with a Seiko Crystal SC-32S crystal with a load capacitance chosen to closely match the required load.
(4) Low-power mode 3, includes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Low-power mode 3, VLO, excludes SVS test conditions:
Current for watchdog timer clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fMCLK = fSMCLK = 0 MHz
(6) RTC is sourced from external 32768-Hz crystal.
(7) CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4), CPU and all clocks are disabled, WDT and RTC disabled
(8) Low-power mode 4, VLO, excludes SVS test conditions:
Current for RTC clocked by VLO included. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fMCLK = fSMCLK = 0 MHz
(9) Low-power mode 4, XT1, excludes SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 32768 Hz, fMCLK = fSMCLK = 0 MHz
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5.8 Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
–40°C
TYP MAX
25°C
TYP
85°C
PARAMETER
VCC
UNIT
MAX
MAX
TYP
Low-power mode 3.5, includes SVS(1) (2) (3)
(also see Figure 5-2)
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
0.64
0.61
0.71
0.69
0.86
0.83
0.30
0.29
1.23
µA
ILPM3.5, XT1
ILPM4.5, SVS
ILPM4.5
Low-power mode 4.5, includes SVS(4) (also see
Figure 5-3)
0.23
0.25
0.45
µA
0.21
0.24
0.020
0.022
0.032
0.034
0.071 0.120
0.068
Low-power mode 4.5, excludes SVS(5)
µA
(1) Not applicable for devices with HF crystal oscillator only.
(2) Characterized with a Seiko Crystal SC-32S crystal with a load capacitance chosen to closely match the required load.
(3) Low-power mode 3.5, includes SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(4) Low-power mode 4.5, includes SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
(5) Low-power mode 4.5, excludes SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
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5.9 Production Distribution of LPM Supply Currents
3.0
10
9
2.5
8
7
2.0
6
1.5
5
4
1.0
3
2
0.5
1
0.0
0
Temperature (°C)
Temperature (°C)
DVCC = 3 V
XT1 Enabled
SVS Enabled
DVCC = 3 V
RTC Enabled
SVS Disabled
Figure 5-2. LPM3.5 Supply Current vs Temperature
Figure 5-1. LPM3 Supply Current vs Temperature
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature (°C)
DVCC = 3 V
SVS Enabled
Figure 5-3. LPM4.5 Supply Current vs Temperature
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5.10 Typical Characteristics – Current Consumption Per Module
MODULE
Timer_B
TEST CONDITIONS
SMCLK = 8 MHz, MC = 10b
REFERENCE CLOCK
Module input clock
TYP
5
UNIT
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
nA
eUSCI_A
eUSCI_A
eUSCI_B
eUSCI_B
RTC
UART mode
SPI mode
Module input clock
Module input clock
Module input clock
Module input clock
32 kHz
7
5
SPI mode
I2C mode, 100 kbaud
5
5
85
8.5
CRC
From start to end of operation
MCLK
µA/MHz
5.11 Thermal Resistance Characteristics
VALUE
UNIT
VQFN 16 pin (RGY)
TSSOP 20 pin (PW20)
TSSOP 16 pin (PW16)
VQFN 16 pin (RGY)
TSSOP 20 pin (PW20)
TSSOP 16 pin (PW16)
VQFN 16 pin (RGY)
TSSOP 20 pin (PW20)
TSSOP 16 pin (PW16)
41.8
92.6
104.1
49.1
26.1
38.5
18.5
45.0
49.1
θJA
θJC
θJB
Junction-to-ambient thermal resistance, still air(1)
Junction-to-case (top) thermal resistance(2)
Junction-to-board thermal resistance(3)
ºC/W
ºC/W
ºC/W
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
20
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5.12 Timing and Switching Characteristics
5.12.1 Power Supply Sequencing
Table 5-1 lists the characteristics of the SVS and BOR.
Table 5-1. PMM, SVS and BOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-4)
PARAMETER
Safe BOR power-down level(1)
Safe BOR reset delay(2)
TEST CONDITIONS
MIN
0.1
10
TYP
MAX UNIT
VBOR, safe
tBOR, safe
ISVSH,AM
ISVSH,LPM
VSVSH-
V
ms
SVSH current consumption, active mode
SVSH current consumption, low-power modes
SVSH power-down level(3)
VCC = 3.6 V
VCC = 3.6 V
1.5
µA
nA
V
240
1.80
1.88
80
1.71
1.76
1.87
1.99
VSVSH+
SVSH power-up level(3)
V
VSVSH_hys
tPD,SVSH, AM
SVSH hysteresis
mV
µs
µs
SVSH propagation delay, active mode
10
tPD,SVSH, LPM SVSH propagation delay, low-power modes
100
(1) A safe BOR is correctly generated only if DVCC drops below this voltage before it rises.
(2) When an BOR occurs, a safe BOR is correctly generated only if DVCC is kept low longer than this period before it reaches VSVSH+.
(3) For additional information, see the Dynamic Voltage Scaling Power Solution for MSP430 Devices With Single-Channel LDO Reference
Design.
Figure 5-4 shows the reset conditions.
V
Power Cycle Reset
SVS Reset
BOR Reset
VSVS+
VSVS–
VBOR
tBOR
t
Figure 5-4. Power Cycle, SVS, and BOR Reset Conditions
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5.12.2 Reset Timing
Table 5-2 lists the wake-up times from low-power modes and reset.
Table 5-2. Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
(Additional) wake-up time to activate the FRAM
in AM if previously disabled through the FRAM
controller or from a LPM if immediate activation
is selected for wakeup(1)
tWAKE-UP FRAM
3 V
10
µs
200 +
ns
(1)
tWAKE-UP LPM0
Wake-up time from LPM0 to active mode
3 V
2.5 / fDCO
(1)
tWAKE-UP LPM3
tWAKE-UP LPM4
Wake-up time from LPM3 to active mode
3 V
3 V
3 V
3 V
3 V
10
10
µs
µs
µs
µs
ms
(2)
Wake-up time from LPM4 to active mode
(2)
tWAKE-UP LPM3.5 Wake-up time from LPM3.5 to active mode
350
350
1
SVSHE = 1
SVSHE = 0
(2)
tWAKE-UP LPM4.5 Wake-up time from LPM4.5 to active mode
Wake-up time from RST or BOR event to active
mode
tWAKE-UP-RESET
tRESET
3 V
1
ms
µs
(2)
Pulse duration required at RST/NMI pin to
accept a reset
2
(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first
externally observable MCLK clock edge.
(2) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
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5.12.3 Clock Specifications
Table 5-3 lists the characteristics of the XT1 crystal oscillator (low frequency).
Table 5-3. XT1 Crystal Oscillator (Low Frequency)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
XT1 oscillator crystal, low
frequency
fXT1, LF
LFXTBYPASS = 0
32768
Hz
Measured at MCLK,
fLFXT = 32768 Hz
DCXT1, LF
fXT1,SW
XT1 oscillator LF duty cycle
30%
70%
XT1 oscillator logic-level square-
wave input frequency
(3) (4)
LFXTBYPASS = 1
LFXTBYPASS = 1
32768
Hz
LFXT oscillator logic-level square-
wave input duty cycle
DCXT1, SW
OALFXT
CL,eff
40%
60%
Oscillation allowance for
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32768 Hz, CL,eff = 12.5 pF
200
(7)1
kΩ
(5)
LF crystals
Integrated effective load
pF
(6)
capacitance
fOSC = 32768 Hz
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF
(8)
tSTART,LFXT
fFault,LFXT
Start-up time
1000
ms
(9)
Oscillator fault frequency
XTS = 0(10)
0
3500
Hz
(1) To improve EMI on the LFXT oscillator, observe the following guidelines.
•
•
•
•
•
•
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces under or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing.
(3) When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW
.
(4) Maximum frequency of operation of the entire device cannot be exceeded.
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
•
•
•
•
For LFXTDRIVE = {0}, CL,eff = 3.7 pF.
For LFXTDRIVE = {1}, 6 pF ≤ CL,eff ≤ 9 pF.
For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 10 pF.
For LFXTDRIVE = {3}, 6 pF ≤ CL,eff ≤ 12 pF.
(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
(7) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds
additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance
of the selected crystal is met.
(8) Includes start-up counter of 1024 clock cycles.
(9) Frequencies above the MAX specification do not set the fault flag. Frequencies in between the MIN and MAX specification may set the
flag. A static condition or stuck at fault condition sets the flag.
(10) Measured with logic-level input frequency but also applies to operation with crystals.
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Table 5-4 lists the characteristics of the XT1 crystal oscillator (high frequency).
Table 5-4. XT1 Crystal Oscillator (High Frequency)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
1
TYP
MAX UNIT
XT1BYPASS = 0, XTS = 1, XT1HFFREQ = 00
XT1BYPASS = 0, XTS = 1, XT1HFFREQ = 01
XT1BYPASS = 0, XTS = 1, XT1HFFREQ = 10
4
HFXT oscillator crystal
frequency, crystal mode
fHFXT
4.01
6.01
6
MHz
16
HFXT oscillator logic-level
square-wave input frequency, XT1BYPASS = 1, XTS = 1
bypass mode
(2) (3)
fHFXT,SW
DCHFXT
1
16 MHz
60%
60%
HFXT oscillator duty cycle
Measured at ACLK, fHFXT,HF = 4 MHz(4)
40%
40%
DCHFXT,
SW
HFXT oscillator logic-level
square-wave input duty cycle
XT1BYPASS = 1
Oscillation allowance for
HFXT crystals(5)
XT1BYPASS = 0, XT1HFSEL = 1,
fHFXT,HF = 16 MHz, CL,eff = 18 pF
OAHFXT
2.4
1.6
kΩ
ms
pF
fOSC = 4 MHz, XTS = 1(4)
,
XT1BYPASS = 0, XT1HFFREQ = 00,
XT1DRIVE = 3, TA = 25°C, CL,eff = 18 pF
tSTART,HFXT Start-up time(6)
fOSC = 16 MHz, XTS = 1(4)
,
XT1BYPASS = 0, XT1HFFREQ = 00,
XT1DRIVE = 3, TA = 25°C, CL,eff = 18 pF
1.1
1
Integrated effective load
CL,eff
capacitance(7) (8)
fFault,HFXT
Oscillator fault frequency(9) (10)
0
800 kHz
(1) To improve EMI on the HFXT oscillator, the following guidelines should be observed.
•
•
•
•
•
•
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces under or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When XT1BYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics defined
in the Schmitt-trigger Inputs section of this datasheet. Duty cycle requirements are defined by DCHFXT, SW
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) 4-MHz crystal used for lab characterization: Abracon HC49/U AB-4.000MHZ-B2
16-MHz crystal used for lab characterization: Abracon HC49/U AB-16.000MHZ-B2
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(6) Includes start-up counter of 4096 clock cycles.
.
(7) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the oscillator frequency through
MCLK or SMCLK. For a correct setup, the effective load capacitance should always match the specification of the used crystal.
(8) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Recommended values supported are
14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF.
(9) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX might set the flag. A static
condition or stuck at fault condition sets the flag.
(10) Measured with logic-level input frequency but also applies to operation with crystals.
24
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Table 5-5 lists the characteristics of the DCO FLL.
Table 5-5. DCO FLL
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
–1.0%
–2.0%
TYP
MAX UNIT
1.0%
FLL lock frequency, 16 MHz, 25°C
FLL lock frequency, 16 MHz, –40°C to 85°C
Measured at MCLK, internal
trimmed REFO as reference
2.0%
fDCO, FLL
3.0 V
Measured at MCLK, XT1 crystal
as reference
FLL lock frequency, 16 MHz, –40°C to 85°C
Duty cycle
–0.5%
40%
0.5%
60%
Measured at MCLK, XT1 crystal
as reference
fDUTY
3.0 V
3.0 V
3.0 V
3.0 V
50%
0.25%
0.022%
200
Measured at MCLK, XT1 crystal
as reference
Jittercc
Jitterlong
tFLL, lock
Cycle-to-cycle jitter, 16 MHz
Long-term jitter, 16 MHz
FLL lock time, 16 MHz
Measured at MCLK, XT1 crystal
as reference
Measured at MCLK, XT1 crystal
as reference
ms
Table 5-6 lists the characteristics of the DCO frequency.
Table 5-6. DCO Frequency
over recommended operating free-air temperature (unless otherwise noted) (see Figure 5-5)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DCORSEL = 101b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
7.8
DCORSEL = 101b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
12.5
18
30
6
fDCO, 16 MHz
fDCO, 12 MHz
fDCO, 8 MHz
fDCO, 4 MHz
DCO frequency, 16 MHz
MHz
DCORSEL = 101b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 101b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
DCORSEL = 100b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
DCORSEL = 100b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
9.5
13.5
22
3.8
6.5
9.5
16
2
DCO frequency, 12 MHz
DCO frequency, 8 MHz
DCO frequency, 4 MHz
MHz
MHz
MHz
DCORSEL = 100b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 100b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
DCORSEL = 011b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
DCORSEL = 011b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
DCORSEL = 011b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 011b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
DCORSEL = 010b,, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
DCORSEL = 010b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
3.2
4.8
8
DCORSEL = 010b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 010b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
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Table 5-6. DCO Frequency (continued)
over recommended operating free-air temperature (unless otherwise noted) (see Figure 5-5)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DCORSEL = 001b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
1
DCORSEL = 001b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
1.7
2.5
fDCO, 2 MHz
DCO frequency, 2 MHz
MHz
DCORSEL = 001b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 001b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
4.2
DCORSEL = 000b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
0.5
DCORSEL = 000b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
0.85
1.2
fDCO, 1 MHz
DCO frequency, 1 MHz
MHz
DCORSEL = 000b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 000b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
2.1
DCOFTRIM = 7
30
25
20
15
10
5
DCOFTRIM = 7
DCOFTRIM = 7
DCOFTRIM = 7
DCOFTRIM = 0
DCOFTRIM = 7
DCOFTRIM = 0
DCOFTRIM = 7
DCOFTRIM = 0
DCOFTRIM = 0
DCOFTRIM = 0
DCOFTRIM = 0
0
DCO
0
511
0
511
0
511
0
511
0
511
0
511
DCORSEL
0
1
2
3
4
5
Figure 5-5. Typical DCO Frequency
Table 5-7 lists the characteristics of the REFO.
Table 5-7. REFO
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
VCC
MIN
TYP
MAX UNIT
IREFO
REFO oscillator current consumption
REFO calibrated frequency
3.0 V
3.0 V
15
µA
Hz
Measured at MCLK
TA = –40°C to 85°C
Measured at MCLK(1)
32768
fREFO
REFO absolute calibrated tolerance
REFO frequency temperature drift
1.8 V to 3.6 V –3.5%
3.0 V
+3.5%
%/°C
dfREFO/dT
0.01
1
dfREFO
/
REFO frequency supply voltage drift
Measured at MCLK at 25°C(2)
1.8 V to 3.6 V
%/V
dVCC
fDC
REFO duty cycle
Measured at MCLK
1.8V to 3.6 V
40%
50%
50
60%
µs
tSTART
REFO start-up time
40% to 60% duty cycle
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
26
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Table 5-8 lists the characteristics of the internal very-low-power low-frequency oscillator (VLO).
Table 5-8. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLO frequency
VLO frequency temperature drift
TEST CONDITIONS
VCC
3.0 V
MIN
TYP
10
MAX UNIT
kHz
fVLO
Measured at MCLK
dfVLO/dT
Measured at MCLK(1)
Measured at MCLK(2)
Measured at MCLK
3.0 V
0.5
4
%/°C
dfVLO/dVCC VLO frequency supply voltage drift
fVLO,DC Duty cycle
1.8 V to 3.6 V
3.0 V
%/V
50%
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
NOTE
The VLO clock frequency is reduced by 15% (typical) when the device switches from active
mode or LPM0 to LPM3 or LPM4, because the reference changes. This lower frequency is
not a violation of the VLO specifications (see Table 5-8).
Table 5-9 lists the characteristics of the module oscillator (MODOSC).
Table 5-9. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
3.0 V
MIN
TYP
4.8
MAX UNIT
5.8 MHz
%/℃
fMODOSC
MODOSC frequency
MODOSC frequency temperature drift
3.8
fMODOSC/dT
3.0 V
0.102
1.02
50%
fMODOSC/dVCC MODOSC frequency supply voltage drift
fMODOSC,DC Duty cycle
1.8 V to 3.6 V
3.0 V
%/V
40%
60%
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5.12.4 Digital I/Os
Table 5-10 lists the characteristics of the digital inputs.
Table 5-10. Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2 V
3 V
2 V
3 V
2 V
3 V
MIN
0.90
1.35
0.50
0.75
0.3
TYP
MAX UNIT
1.50
V
VIT+
VIT–
Vhys
Positive-going input threshold voltage
2.25
1.10
V
Negative-going input threshold voltage
1.65
0.8
V
Input voltage hysteresis (VIT+ – VIT–
Pullup or pulldown resistor
)
0.4
1.2
For pullup: VIN = VSS
For pulldown: VIN = VCC
RPull
CI,dig
CI,ana
20
35
3
50
kΩ
pF
pF
nA
Input capacitance, digital only port pins
VIN = VSS or VCC
Input capacitance, port pins with shared analog
functions
Ilkg(Px.y) High-impedance leakage current(1)(2)
VIN = VSS or VCC
5
2 V, 3 V
2 V, 3 V
–20
50
+20
Ports with interrupt capability
(see block diagram and
terminal function descriptions)
External interrupt timing (external trigger pulse
t(int)
ns
duration to set interrupt flag)(3)
(1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
(3) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. The interrupt flag may be set by
trigger signals shorter than t(int)
.
Table 5-11 lists the characteristics of the digital outputs. Also see Figure 5-6 through Figure 5-9.
Table 5-11. Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA(1)
I(OHmax) = –5 mA(1)
I(OLmax) = 3 mA(1)
I(OLmax) = 5 mA(1)
VCC
MIN
1.4
2.4
0.0
0.0
16
TYP
MAX UNIT
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0
V
VOH
High-level output voltage
3.0
0.60
V
VOL
Low-level output voltage
0.60
fPort_CLK
trise,dig
tfall,dig
Clock output frequency
CL = 20 pF(2)
CL = 20 pF
CL = 20 pF
MHz
ns
16
10
7
Port output rise time, digital only port pins
Port output fall time, digital only port pins
10
5
ns
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
(2) The port can output frequencies at least up to the specified limit and might support higher frequencies.
28
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5.12.4.1 Digital I/O Typical Characteristics
25
20
15
10
5
10
7.5
5
TA = 85°C
TA = 25°C
TA = -40°C
TA = 85°C
TA = 25°C
TA = -40°C
2.5
0
0
-5
0
0.5
1
1.5
2
2.5
3
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
Low-Level Output Voltage (V)
Low-Level Output Voltage (V)
Figure 5-6. Typical Low-Level Output Current
Figure 5-7. Typical Low-Level Output Current
vs
vs
Low-Level Output Voltage (DVCC = 3 V)
Low-Level Output Voltage (DVCC = 2 V)
5
0
0
-2.5
-5
TA = 85°C
TA = 25°C
TA = -40°C
TA = 85°C
TA = 25°C
TA = -40°C
-5
-10
-15
-20
-25
-30
-7.5
-10
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
0
0.5
1
1.5
2
2.5
3
High-Level Output Voltage (V)
High-Level Output Voltage (V)
Figure 5-9. Typical High-Level Output Current
Figure 5-8. Typical High-Level Output Current
vs
vs
High-Level Output Voltage (DVCC = 2 V)
High-Level Output Voltage (DVCC = 3 V)
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5.12.5 VREF+ Built-in Reference
Table 5-12 lists the characteristics of the VREF+.
Table 5-12. VREF+
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
EXTREFEN = 1 with 1-mA load
current to ground
VREF+
Positive built-in reference voltage
2.0 V, 3.0 V
1.15
1.19
1.23
V
Temperature coefficient of built-in
reference voltage
EXTREFEN = 1 with 1-mA load
current
TCREF+
30
µV/°C
5.12.6 Timer_B
Table 5-13 lists the characteristics of the Timer_B clock frequency.
Table 5-13. Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK or ACLK,
External: TBCLK,
fTB
Timer_B input clock frequency
2.0 V, 3.0 V
16 MHz
Duty cycle = 50% ±10%
All capture inputs, minimum pulse
duration required for capture
tTB,cap
Timer_B capture timing
2.0 V, 3.0 V
20
ns
30
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5.12.7 eUSCI
Table 5-14 lists the clock frequency of the eUSCI in UART mode.
Table 5-14. eUSCI (UART Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK or MODCLK,
External: UCLK,
feUSCI
eUSCI input clock frequency
2.0 V, 3.0 V
16 MHz
Duty cycle = 50% ±10%
BITCLK clock frequency
(equals baud rate in Mbaud)
fBITCLK
2.0 V, 3.0 V
5
MHz
Table 5-15 lists the switching characteristics of the eUSCI in UART mode.
Table 5-15. eUSCI (UART Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UCGLITx = 0
VCC
MIN
TYP
MAX UNIT
12
40
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
2.0 V,
3.0 V
(1)
tt UART receive deglitch time
ns
68
110
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To make sure that pulses are
correctly recognized, their duration must exceed the maximum specification of the deglitch time.
Table 5-16 lists the clock frequency of the eUSCI in SPI master mode.
Table 5-16. eUSCI (SPI Master Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
MAX UNIT
MHz
Internal: SMCLK or MODCLK,
Duty cycle = 50% ±10%
feUSCI eUSCI input clock frequency
8
Table 5-17 lists the switching characteristics of the eUSCI in SPI master mode.
Table 5-17. eUSCI (SPI Master Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
UCxCLK
cycles
tSTE,LEAD
tSTE,LAG
STE lead time, STE active to clock
UCSTEM = 1, UCMODEx = 01 or 10
1
UCxCLK
cycles
STE lag time, last clock to STE inactive
SOMI input data setup time
UCSTEM = 1, UCMODEx = 01 or 10
1
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
47
35
0
tSU,MI
ns
ns
ns
ns
tHD,MI
SOMI input data hold time
SIMO output data valid time(2)
SIMO output data hold time(3)
0
20
20
tVALID,MO
UCLK edge to SIMO valid, CL = 20 pF
CL = 20 pF
0
0
tHD,MO
(1) fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)
)
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-10 and Figure 5-11.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-
10 and Figure 5-11.
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 5-10. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
tVALID,MO
SIMO
Figure 5-11. SPI Master Mode, CKPH = 1
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Table 5-18 lists the switching characteristics of the eUSCI in SPI slave mode.
Table 5-18. eUSCI (SPI Slave Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
55
MAX UNIT
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
tSU,SI
STE lead time, STE active to clock
ns
45
20
STE lag time, last clock to STE inactive
ns
20
65
ns
40
STE access time, STE active to SOMI data out
40
ns
35
STE disable time, STE inactive to SOMI high
impedance
8
6
SIMO input data setup time
SIMO input data hold time
SOMI output data valid time(2)
ns
ns
12
12
tHD,SI
68
ns
42
UCLK edge to SOMI valid,
CL = 20 pF
tVALID,SO
5
5
(3)
tHD,SO
SOMI output data hold time
CL = 20 pF
ns
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)
)
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-12 and Figure 5-13.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-12
and Figure 5-13.
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tSU,SIMO
tHD,SIMO
tLOW/HIGH
tLOW/HIGH
SIMO
tACC
tVALID,SOMI
tDIS
SOMI
Figure 5-12. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tACC
tDIS
tVALID,SO
SOMI
Figure 5-13. SPI Slave Mode, CKPH = 1
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Table 5-19 lists the switching characteristics of the eUSCI (I2C mode).
Table 5-19. eUSCI (I2C Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-14)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK or MODCLK,
External: UCLK,
feUSCI
eUSCI input clock frequency
16 MHz
Duty cycle = 50% ±10%
fSCL
SCL clock frequency
2.0 V, 3.0 V
2.0 V, 3.0 V
0
4.0
0.6
4.7
0.6
0
400 kHz
µs
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
2.0 V, 3.0 V
µs
tHD,DAT
tSU,DAT
Data hold time
Data setup time
2.0 V, 3.0 V
2.0 V, 3.0 V
ns
ns
250
4.0
0.6
50
fSCL = 100 kHz
fSCL > 100 kHz
UCGLITx = 0
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
UCCLTOx = 1
UCCLTOx = 2
UCCLTOx = 3
tSU,STO
Setup time for STOP
2.0 V, 3.0 V
µs
600
25
300
ns
Pulse duration of spikes suppressed by
input filter
tSP
2.0 V, 3.0 V
12.5
6.3
150
75
27
30
33
tTIMEOUT Clock low time-out
2.0 V, 3.0 V
ms
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
SCL
tLOW
tHIGH
tSP
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-14. I2C Mode Timing
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5.12.8 ADC
Table 5-20 lists the characteristics of the ADC power supply and input range conditions.
Table 5-20. ADC, Power Supply and Input Range Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.0
0
TYP
MAX UNIT
DVCC
V(Ax)
ADC supply voltage
Analog input voltage range
3.6
V
V
All ADC pins
DVCC
Operating supply current into
DVCC terminal, reference
current not included, repeat-
single-channel mode
2 V
3 V
185
207
fADCCLK = 5 MHz, ADCON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADCDIV = 0, ADCCONSEQx = 10b
IADC
µA
Only one terminal Ax can be selected at one
time from the pad to the ADC capacitor array,
including wiring and pad
CI
Input capacitance
2.2 V
2.5
34
3.5
2
pF
RI,MUX
RI,Misc
Input MUX ON resistance
DVCC = 2 V, 0 V ≤ VAx ≤ DVCC
kΩ
kΩ
Input miscellaneous resistance
Table 5-21 lists the ADC 10-bit timing parameters.
Table 5-21. ADC, 10-Bit Timing Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
For specified performance of ADC linearity
parameters
2 V to
3.6 V
fADCCLK
fADCOSC
0.45
5
5.5 MHz
Internal ADC oscillator
(MODOSC)
2 V to
3.6 V
ADCDIV = 0, fADCCLK = fADCOSC
3.8
4.8
5.8 MHz
REFON = 0, Internal oscillator,
10 ADCCLK cycles, 10-bit mode,
fADCOSC = 4.5 MHz to 5.5 MHz
2 V to
3.6 V
2.18
2.67
µs
tCONVERT
Conversion time
External fADCCLK from ACLK, MCLK, or SMCLK,
ADCSSEL ≠ 0
2 V to
3.6 V
12 ×
1 / fADCCLK
The error in a conversion started after tADCON is
less than ±0.5 LSB.
Reference and input signal are already settled.
RS = 1000 Ω, RI(1) = 36000 Ω, CI = 3.5 pF,
Approximately 8 Tau (t) are required for an error
of less than ±0.5 LSB(2)
Turn-on settling time of
the ADC
tADCON
100
ns
µs
2 V
3 V
1.5
2.0
tSample
Sampling time
(1) RI = RI,MUX + RI,Misc
(2) tSample = ln(2n+1) × τ, where n = ADC resolution, τ = (RI + RS) × CI
36
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Table 5-22 lists the ADC 10-bit linearity parameters.
Table 5-22. ADC, 10-Bit Linearity Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
–2
TYP
MAX UNIT
Integral linearity error (10-bit mode)
Integral linearity error (8-bit mode)
Differential linearity error (10-bit mode)
Differential linearity error (8-bit mode)
Offset error (10-bit mode)
2.4 V to 3.6 V
2.0 V to 3.6 V
2.4 V to 3.6 V
2.0 V to 3.6 V
2.4 V to 3.6 V
2.0 V to 3.6 V
2
EI
Veref+ reference
Veref+ reference
Veref+ reference
LSB
2
–2
–1
1
ED
EO
LSB
1
–1
–6.5
–6.5
–2.0
–3.0%
–2.0
–3.0%
–2.0
–3.0%
–2.0
–3.0%
6.5
mV
6.5
Offset error (8-bit mode)
Veref+ as reference
Internal 1.5-V reference
Veref+ as reference
Internal 1.5-V reference
Veref+ as reference
Internal 1.5-V reference
Veref+ as reference
Internal 1.5-V reference
2.0
3.0%
2.0
LSB
LSB
LSB
LSB
Gain error (10-bit mode)
2.4 V to 3.6 V
2.0 V to 3.6 V
2.4 V to 3.6 V
2.0 V to 3.6 V
EG
Gain error (8-bit mode)
3.0%
2.0
Total unadjusted error (10-bit mode)
Total unadjusted error (8-bit mode)
3.0%
2.0
ET
3.0%
ADCON = 1, INCH = 0Ch,
TA = 0℃
(1)
VSENSOR
See
3 V
3 V
913
mV
(2)
TCSENSOR See
ADCON = 1, INCH = 0Ch
3.35
mV/℃
ADCON = 1, INCH = 0Ch,
Error of conversion result
≤1 LSB,
3 V
3 V
30
tSENSOR
(sample)
Sample time required if channel 12 is
selected(3)
AM and all LPMs above LPM3
µs
ADCON = 1, INCH = 0Ch,
Error of conversion result
≤1 LSB, LPM3
100
(1) The temperature sensor offset can vary significantly. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
(2) The device descriptor structure contains calibration values for 30℃ and 85℃ for each available reference voltage level. The sensor
voltage can be computed as VSENSE = TCSENSOR × (Temperature, ℃) + VSENSOR, where TCSENSOR and VSENSOR can be computed from
the calibration values for higher accuracy.
(3) The typical equivalent impedance of the sensor is 700 kΩ. The sample time required includes the sensor on time, tSENSOR(on)
.
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5.12.9 Enhanced Comparator (eCOMP)
Table 5-23 lists the characteristics of eCOMP0.
Table 5-23. eCOMP0
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.0
0
TYP
MAX UNIT
VCC
VIC
Supply voltage
3.6
V
V
Common-mode input range
VCC
CPEN = 1, CPHSEL = 00
0
10
20
30
CPEN = 1, CPHSEL = 01
VHYS
DC input hysteresis
mV
CPEN = 1, CPHSEL = 10
CPEN = 1, CPHSEL = 11
CPEN = 1, CPMSEL = 0
–30
–40
+30
+40
35
VOFFSET
Input offset voltage
mV
µA
CPEN = 1, CPMSEL = 1
VIC = VCC / 2, CPEN = 1, CPMSEL = 0
VIC = VCC / 2, CPEN = 1, CPMSEL = 1
24
1.6
1
Quiescent current draw from
VCC, only comparator
ICOMP
CIN
5
Input channel capacitance(1)
pF
kΩ
On (switch closed)
Off (switch open)
10
20
1
RIN
Input channel series resistance
50
MΩ
CPMSEL = 0, CPFLT = 0, VIC = VCC / 2,
Overdrive = 20 mV
Propagation delay, response
time
tPD
µs
µs
CPMSEL = 1, CPFLT = 0, VIC = VCC / 2,
Overdrive = 20 mV
3.2
8.5
1.4
CPEN = 0→1, CPMSEL = 0, V+ and V- from pads,
Overdrive = 20 mV
tEN_CP
Comparator enable time
CPEN = 0→1, CPMSEL = 1, V+ and V- from pads,
Overdrive = 20 mV
CPEN = 0→1, CPDACEN = 0→1, CPMSEL = 0,
CPDACREFS = 1, CPDACBUF1 = 0F,
Overdrive = 20 mV
8.5
Comparator with reference DAC
enable time
tEN_CP_DAC
µs
µs
CPEN = 0→1, CPDACEN = 0→1, CPMSEL = 1,
CPDACREFS = 1, CPDACBUF1 = 0F,
Overdrive = 20 mV
101
CPMSEL = 0, CPFLTDY = 00, Overdrive = 20 mV,
CPFLT = 1
0.7
1.1
1.9
3.4
CPMSEL = 0, CPFLTDY = 01, Overdrive = 20 mV,
CPFLT = 1
Propagation delay with analog
filter active
tFDLY
CPMSEL = 0, CPFLTDY = 10, Overdrive = 20 mV,
CPFLT = 1
CPMSEL = 0, CPFLTDY = 11, Overdrive = 20 mV,
CPFLT = 1
INL
Integral nonlinearity
–0.5
–0.5
0.5
0.5
LSB
LSB
DNL
Differential nonlinearity
(1) eCOMP CIN, model, see Figure 5-15 for details.
MSP430
RI
VI = External source voltage
RS = External source resistance
RI = Internal MUX-on input resistance
CIN = Input capacitance
CPAD = PAD capacitance
RS
VI
VC
CPext = Parasitic capacitance, external
VC = Capacitance-charging voltage
Cpext
CPAD
CIN
Figure 5-15. eCOMP Input Circuit
38
Specifications
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5.12.10 Smart Analog Combo (SAC)
Table 5-24 lists the characteristics of SAC0 (SAC-L1, OA).
Table 5-24. SAC0 (SAC-L1, OA)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Supply voltage
Input offset voltage
TEST CONDITIONS
MIN
2.0
–5
TYP
MAX
3.6
5
UNIT
V
VCC
VOS
mV
OAPM = 0
3
5
dVOS /dT Offset drift
µV/℃
OAPM = 1
IB
Input bias current
50
pA
V
VCM
Input voltage range
–0.1
VCC + 0.1
OAPM = 0
350
120
40
40
20
70
80
70
80
4
IIDD
Quiescent current
µA
µV
OAPM = 1
Input noise voltage, f = 0.1 Hz to 10 Hz
Input noise voltage density, f = 1 kHz
Input noise voltage, f = 10 kHz
Vin = VCC / 2, OAPM = 0
Vin = VCC / 2, OAPM = 0
Vin = VCC / 2, OAPM = 0
OAPM = 0
ENI
nV/√Hz
CMRR
PSRR
GBW
Common-mode rejection ratio
Power supply rejection ratio
Gain bandwidth
dB
dB
OAPM = 1
OAPM = 0
OAPM = 1
OAPM = 0
MHz
OAPM = 1
1.4
100
100
65
3
OAPM = 0
AOL
Open-loop voltage gain
Phase margin
dB
deg
V/us
OAPM = 1
φM
CL = 50 pF , RL = 2 kΩ
CL = 50 pF, OAPM = 0
CL = 50 pF, OAPM = 1
Common mode
RL = 10 kΩ
Positive slew rate
1
Cin
VO
Input capacitance
2
pF
Voltage output swing from supply rails
40
100
mV
To 0.1% final value, G = +1, 1-V setup,
CL = 50 pF, OAPM = 0
1
tST
OA settling time
µs
To 0.1% final value, G = +1, 1-V setup,
CL = 50 pF, OAPM = 1
4.5
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5.12.11 Transimpedance Amplifier (TIA)
Table 5-25 lists the characteristics of TIA0.
Table 5-25. TIA0
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Supply voltage
Input offset voltage
TEST CONDITIONS
MIN
2.0
–5
TYP
MAX
UNIT
V
VCC
VOS
3.6
5
mV
TRIPM = 0
3
5
dVOS /dT Offset drift
µV/℃
TRIPM = 1
VB = 0 V, TSSOP-16 package with OA-
dedicated pin input (see Figure 4-2)
5
pA
IB
Input bias current
TSSOP-20 and VQFN-16 packages
50
pA
V
VCM
IIDD
Input voltage range
Quiescent current
–0.1
VCC / 2
TRIPM = 0
350
120
40
40
16
80
70
80
70
5
µA
TRIPM = 1
Input noise voltage, f = 0.1 Hz to 10 Hz
Input noise voltage density, f = 1 kHz
Input noise voltage, f = 10 kHz
Vin = VCC / 2, TRIPM = 0
Vin = VCC / 2, TRIPM = 0
Vin = VCC / 2, TRIPM = 0
TRIPM = 0
µV
ENI
nV/√Hz
CMRR
PSRR
GBW
AOL
Common-mode rejection ratio
Power supply rejection ratio
Gain bandwidth
dB
dB
TRIPM = 1
TRIPM = 0
TRIPM = 1
TRIPM = 0
MHz
dB
TRIPM = 1
1.8
100
100
40
70
4
TRIPM = 0
Open-loop voltage gain
Phase margin
TRIPM = 1
CL = 50 pF , RL = 2 kΩ, TRIPM = 0
CL = 50 pF , RL = 2 kΩ, TRIPM = 1
CL = 50 pF, TRIPM = 0
CL = 50 pF, TRIPM = 1
Common mode
φM
deg
V/µs
Positive slew rate
1
Cin
VO
Input capacitance
7
pF
Voltage output swing from supply rails
RL = 10 kΩ
40
100
mV
To 0.1% final value, G = +1, 1-V setup,
CL = 50 pF, TRIPM = 0
3
5
tST
TIA settling time
µs
To 0.1% final value, G = +1, 1-V setup,
CL = 50 pF, TRIPM = 1
40
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5.12.12 FRAM
Table 5-26 lists the characteristics of the FRAM.
Table 5-26. FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Read and write endurance
TEST CONDITIONS
MIN
1015
100
40
TYP
MAX UNIT
cycles
TJ = 25°C
tRetention
Data retention duration
TJ= 70°C
TJ= 85°C
years
10
(1)
IWRITE
IERASE
tWRITE
Current to write into FRAM
Erase current
IREAD
nA
nA
ns
N/A(2)
(3)
Write time
tREAD
(4)
(4)
NWAITSx = 0
NWAITSx = 1
1/fSYSTEM
2/fSYSTEM
tREAD
Read time
ns
(1) Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read
current IREAD is included in the active mode current consumption numbers IAM, FRAM
(2) FRAM does not require a special erase sequence.
.
(3) Writing into FRAM is as fast as reading.
(4) The maximum read (and write) speed is specified by fSYSTEM using the appropriate wait state settings (NWAITSx).
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5.12.13 Emulation and Debug
Table 5-27 lists the characteristics of the 2-wire Spy-Bi-Wire interface.
Table 5-27. JTAG, Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-16)
PARAMETER
Spy-Bi-Wire input frequency
VCC
MIN
0
TYP
MAX UNIT
fSBW
2.0 V, 3.0 V
2.0 V, 3.0 V
8
MHz
µs
tSBW,Low
Spy-Bi-Wire low clock pulse duration
0.028
15
SBWTDIO setup time (before falling edge of SBWTCK in TMS and TDI
slot Spy-Bi-Wire)
tSU,SBWTDIO
tHD,SBWTDIO
tValid,SBWTDIO
2.0 V, 3.0 V
2.0 V, 3.0 V
4
ns
ns
ns
SBWTDIO hold time (after rising edge of SBWTCK in TMS and TDI slot
Spy-Bi-Wire)
19
SBWTDIO data valid time (after falling edge of SBWTCK in TDO slot
Spy-Bi-Wire)
2.0 V, 3.0 V
2.0 V, 3.0 V
31
(1)
tSBW, En
tSBW,Ret
Rinternal
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)
Spy-Bi-Wire return to normal operation time(2)
110
100
50
µs
µs
kΩ
15
20
Internal pulldown resistance on TEST
2.0 V, 3.0 V
35
(1) Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) Maximum tSBW,Rst time after pulling or releasing the TEST/SBWTCK pin low, the Spy-Bi-Wire pins revert from their Spy-Bi-Wire function
to their application function. This time applies only if the Spy-Bi-Wire mode was selected.
tSBW,EN
tSBW,Low
1/fSBW
tSBW,High
tSBW,Ret
TEST/SBWTCK
tEN,SBWTDIO
tValid,SBWTDIO
RST/NMI/SBWTDIO
tSU,SBWTDIO
tHD,SBWTDIO
Figure 5-16. JTAG Spy-Bi-Wire Timing
42
Specifications
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Table 5-28 lists the characteristics of the JTAG 4-wire interface.
Table 5-28. JTAG, 4-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-17)
PARAMETER
(1)
VCC
MIN
0
TYP
MAX UNIT
fTCK
TCK input frequency
2.0 V, 3.0 V
2.0 V, 3.0 V
2.0 V, 3.0 V
2.0 V, 3.0 V
2.0 V, 3.0 V
2.0 V, 3.0 V
2.0 V, 3.0 V
2.0 V, 3.0 V
2.0 V, 3.0 V
2.0 V, 3.0 V
10 MHz
tTCK,Low
tTCK,high
tSU,TMS
tHD,TMS
tSU,TDI
tHD,TDI
Spy-Bi-Wire low clock pulse duration
Spy-Bi-Wire high clock pulse duration
TMS setup time (before rising edge of TCK)
TMS hold time (after rising edge of TCK)
TDI setup time (before rising edge of TCK)
TDI hold time (after rising edge of TCK)
15
15
11
3
ns
ns
ns
ns
ns
ns
13
5
tz-Valid,TDO TDO high impedance to valid output time (after falling edge of TCK)
tValid,TDO TDO to new valid output time (after falling edge of TCK)
tValid-Z,TDO TDO valid to high-impedance output time (after falling edge of TCK)
26
26
ns
ns
ns
µs
kΩ
26
tJTAG,Ret
Rinternal
Spy-Bi-Wire return to normal operation time
Internal pulldown resistance on TEST
15
20
100
50
2.0 V, 3.0 V
35
(1) Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
1/fTCK
tTCK,Low
tTCK,High
TCK
TMS
tSU,TMS
tHD,TMS
TDI
(or TDO as TDI)
tSU,TDI
tHD,TDI
TDO
tZ-Valid,TDO
tValid,TDO
tValid-Z,TDO
tJTAG,Ret
TEST
Figure 5-17. JTAG 4-Wire Timing
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6 Detailed Description
6.1 Overview
The MSP430FR231x FRAM MCU features a powerful 16-bit RISC CPU, 16-bit registers, and constant
generators that contribute to maximum code efficiency. The DCO also allows the device to wake up from
low-power modes to active mode typically in less than 10 µs. The feature set of this microcontroller is ideal
for applications ranging from smoke detectors to portable health and fitness accessories.
6.2 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter (PC), stack pointer (SP), status register
(SR), and constant generator (CG), respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
6.3 Operating Modes
The MSP430 has one active mode and several software-selectable low-power modes of operation (see
Table 6-1). An interrupt event can wake up the device from low-power mode (LPM0, LPM3, or LPM4),
service the request, and restore back to the low-power mode on return from the interrupt program. Low-
power modes LPM3.5 and LPM4.5 disable the core supply to minimize power consumption.
Table 6-1. Operating Modes
AM
LPM0
CPU OFF
16 MHz
LPM3
STANDBY
40 kHz
LPM4
OFF
0
LPM3.5
LPM4.5
SHUTDOWN
0
MODE
Maximum system clock
ACTIVE
MODE
ONLY RTC
COUNTER
16 MHz
40 kHz
1.11 µA with
RTC counter
only in LFXT
0.71 µA with
RTC counter
only in LFXT
0.45 µA
without SVS
32 nA
without SVS
Power consumption at 25°C, 3 V
126 µA/MHz
40 µA/MHz
Wake-up time
N/A
N/A
instant
All
10 µs
10 µs
I/O
350 µs
350 µs
I/O
RTC Counter
I/O
Wake-up events
All
Full
Regulation
Full
Regulation
Partial Power Partial Power Partial Power
Regulator
Power Down
Down
Optional
On
Down
Optional
On
Down
Optional
On
Power
SVS
On
On
On
On
Optional
On
Brownout
44
Detailed Description
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Table 6-1. Operating Modes (continued)
AM
LPM0
LPM3
LPM4
OFF
LPM3.5
LPM4.5
MODE
MCLK
ACTIVE
MODE
ONLY RTC
COUNTER
CPU OFF
STANDBY
SHUTDOWN
Active
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
On
Off
Off
Off
Off
Off
Off
Off
Off
Off
SMCLK
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Off
FLL
Off
Off
Off
Off
DCO
Off
Off
Off
Off
MODCLK
REFO
Off
Off
Off
Off
Clock(1)
Optional
Optional
Off
Off
Off
Off
ACLK
Off
Off
Off
XT1HFCLK(2)
XT1LFCLK
VLOCLK
CPU
Off
Off
Off
Optional
Optional
Off
Off(3)
Off(3)
Off
Optional
Optional
Off
Off
Off
Off
FRAM
On
On
Off
Off
Off
Off
Core
RAM
On
On
On
On
Off
Off
Backup Memory(4)
Timer0_B3
Timer1_B3
WDT
On
On
On
On
On
Off
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
On
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
eUSCI_A0
eUSCI_B0
CRC
Off
Off
Off
Off
Off
Off
Peripherals
Off
Off
Off
ADC
Optional
Optional
Optional
Optional
Optional
State Held
Optional
Off
Off
Off
eCOMP
Optional
Optional
Optional
Off
Off
Off
TIA
Off
Off
SAC0
Off
Off
RTC Counter
General Digital Input/Output
Capacitive Touch I/O
Optional
State Held
Off
Off
State Held
Off
State Held
Off
I/O
Optional
(1) The status shown for LPM4 applies to internal clocks only.
(2) HFXT must be disabled before entering into LPM3, LPM4, or LPMx.5 mode.
(3) Refer to following NOTE for details info as below.
(4) Backup memory contains one 32-byte register in the peripheral memory space. See Table 6-23 and Table 6-38 for the memory
allocation of backup memory.
NOTE
XT1CLK and VLOCLK can be active during LPM4 if requested by low-frequency peripherals.
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6.4 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see
Table 6-2). The vector contains the 16-bit address of the interrupt-handler instruction sequence.
Table 6-2. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
System Reset
Power-up, Brownout, Supply Supervisor
External Reset RST
SVSHIFG
PMMRSTIFG
Watchdog Time-out, Key Violation
FRAM uncorrectable bit error detection
Software POR, BOR
WDTIFG
PMMPORIFG, PMMBORIFG
SYSRSTIV
Reset
FFFEh
63, Highest
FLL unlock error
FLLULPUC
System NMI
Vacant Memory Access
JTAG Mailbox
FRAM access time error
FRAM bit error detection
VMAIFG
JMBINIFG, JMBOUTIFG
CBDIFG, UBDIFG
(Non)maskable
(Non)maskable
FFFCh
FFFAh
62
61
User NMI
External NMI
Oscillator Fault
NMIIFG
OFIFG
Timer0_B3
Timer0_B3
Timer1_B3
Timer1_B3
TB0CCR0 CCIFG0
Maskable
Maskable
Maskable
Maskable
FFF8h
FFF6h
FFF4h
FFF2h
60
59
58
57
TB0CCR1 CCIFG1, TB0CCR2
CCIFG2, TB0IFG (TB0IV)
TB1CCR0 CCIFG0
TB1CCR1 CCIFG1, TB1CCR2
CCIFG2, TB1IFG (TB1IV)
RTC Counter
RTCIFG
WDTIFG
Maskable
Maskable
FFF0h
FFEEh
56
55
Watchdog Timer Interval mode
UCTXCPTIFG, UCSTTIFG,
UCRXIFG, UCTXIFG (UART
mode)
eUSCI_A0 Receive or Transmit
Maskable
FFECh
54
UCRXIFG, UCTXIFG (SPI mode)
(UCA0IV))
UCB0RXIFG, UCB0TXIFG (SPI
mode)
UCALIFG, UCNACKIFG,
UCSTTIFG, UCSTPIFG,
UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1,
UCRXIFG2, UCTXIFG2,
UCRXIFG3, UCTXIFG3,
UCCNTIFG,
eUSCI_B0 Receive or Transmit
Maskable
Maskable
FFEAh
FFE8h
53
52
UCBIT9IFG,UCCLTOIFG(I2C
mode)
(UCB0IV)
ADCIFG0, ADCINIFG,
ADCLOIFG, ADCHIIFG,
ADCTOVIFG, ADCOVIFG
(ADCIV)
ADC
P1
P2
P1IFG.0 to P1IFG.7 (P1IV)
P2IFG.0 to P2IFG.7 (P2IV)(1)
CPIIFG, CPIFG (CPIV)
Maskable
Maskable
Maskable
FFE6h
FFE4h
FFE2h
51
50
49
eCOMP
FFE0h to
FF88h
Reserved
Reserved
Maskable
(1) P2.0, P2.1, P2.6, and P2.7 support both pin and software interrupts. Others ports support software interrupts only.
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Table 6-2. Interrupt Sources, Flags, and Vectors (continued)
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
BSL Signature 2
BSL Signature 1
JTAG Signature 2
JTAG Signature 1
0FF86h
0FF84h
0FF82h
0FF80h
Signatures
6.5 Memory Organization
Table 6-3 summarizes the memory map of the MSP430FR231x MCUs.
Table 6-3. Memory Organization
ACCESS
MSP430FR2311
MSP430FR2310
Memory (FRAM)
Main: interrupt vectors and signatures
Main: code memory
3.75KB
FFFFh to FF80h
FFFFh to F100h
2KB
FFFFh to FF80h
FFFFh to F800h
Read/Write
(Optional Write Protect)(1)
1KB
23FFh to 2000h
1KB
23FFh to 2000h
RAM
Read/Write
Read only
Read only
Read/Write
Bootloader (BSL1) Memory (ROM) (TI
Internal Use)
2KB
17FFh to 1000h
2KB
17FFh to 1000h
Bootloader (BSL2) Memory (ROM) (TI
Internal Use)
1KB
1KB
FFFFFh to FFC00h
FFFFFh to FFC00h
4KB
0FFFh to 0000h
4KB
0FFFh to 0000h
Peripherals
(1) The Program FRAM can be write protected by setting the PFWP bit in the SYSCFG0 register. See the System Resets, Interrupts, and
Operating Modes, System Control Module (SYS) chapter in the MSP430FR4xx and MSP430FR2xx Family User's Guide for more details
6.6 Bootloader (BSL)
The BSL lets users program the FRAM or RAM using a UART or I2C serial interface. Access to the device
memory through the BSL is protected by a user-defined password. Use of the BSL requires four pins (see
Table 6-4 and Table 6-5). BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and
TEST/SBWTCK pins.
This device supports blank device detection to automatically invoke the BSL and skip the special entry
sequence, which saves time and simplifies onboard programming. For complete description of the
features of the BSL and its implementation, see MSP430 FRAM Device Bootloader (BSL) User's Guide.
Table 6-4. UART BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
Entry sequence signal
Entry sequence signal
Data transmit
RST/NMI/SBWTDIO
TEST/SBWTCK
P1.7
P1.6
VCC
Data receive
Power supply
VSS
Ground supply
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Table 6-5. I2C BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
Entry sequence signal
Entry sequence signal
Data receive and transmit
Clock
RST/NMI/SBWTDIO
TEST/SBWTCK
P1.2
P1.3
VCC
Power supply
VSS
Ground supply
6.7 JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin enables
the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO pin interfaces with MSP430
development tools and device programmers. Table 6-6 lists the JTAG pin requirements. For further details
on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's
Guide.
Table 6-6. JTAG Pin Requirements and Function
DEVICE SIGNAL
P1.4/UCA0STE/TCK/OA0+/A4
P1.5/UCA0CLK/TMS/TRI0O/A5
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/TRI0-/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/TRI0+/A7/VREF+
TEST/SBWTCK
DIRECTION
JTAG FUNCTION
JTAG clock input
IN
IN
JTAG state control
JTAG data input and TCLK input
JTAG data output
Enable JTAG pins
External reset
IN
OUT
IN
RST/NMI/SBWTDIO
IN
VCC
Power supply
VSS
Ground supply
6.8 Spy-Bi-Wire Interface (SBW)
The MSP430 family supports the 2-wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface with
MSP430 development tools and device programmers. Table 6-7 lists the Spy-Bi-Wire interface pin
requirements. For further details on interfacing to development tools and device programmers, see the
MSP430 Hardware Tools User's Guide.
Table 6-7. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
DIRECTION
SBW FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input and output
Power supply
IN
IN, OUT
–
–
VSS
Ground supply
6.9 FRAM
The FRAM can be programmed using the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in system by the
CPU. Features of the FRAM include:
•
•
•
Byte and word access capability
Programmable wait state generation
Error correction coding (ECC)
48
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6.10 Memory Protection
The device features memory protection of user access authority and write protection include:
•
Securing the whole memory map to prevent unauthorized access from JTAG port or BSL, by writing
JTAG and BSL signatures using the JTAG port, SBW, the BSL, or in system by the CPU.
•
Write protection enabled to prevent unwanted write operation to FRAM contents by setting the control
bits with accordingly password in System Configuration register 0. For more detailed information, see
the System Resets, Interrupts, and Operating Modes, System Control Module (SYS) chapter in the
MSP430FR4xx and MSP430FR2xx Family User's Guide.
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6.11 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. All peripherals can be
handled by using all instructions in the memory map. For complete module description, see the
MSP430FR4xx and MSP430FR2xx Family User's Guide.
6.11.1 Power-Management Module (PMM) and On-chip Reference Voltages
The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM
also includes supply voltage supervisor (SVS) and brownout protection. The brownout reset circuit (BOR)
is implemented to provide the proper internal reset signal to the device during power on and power off.
The SVS circuitry detects if the supply voltage drops below a user-selectable safe level. SVS circuitry is
available on the primary supply.
The device contains two on-chip reference: 1.5 V for internal reference and 1.2 V for external reference.
The 1.5-V reference is internally connected to ADC channel 13. DVCC is internally connected to ADC
channel 15. When DVCC is set as the reference voltage for ADC conversion, the DVCC can be easily
represent as Equation 1 by using ADC sampling 1.5-V reference without any external components
support.
DVCC = (1023 × 1.5 V) ÷ 1.5-V reference ADC result
(1)
The 1.5-V reference is also internally connected to the Comparator built-in DAC as reference voltage.
DVCC is internally connected to another source of DAC reference, and both are controlled by the
CPDACREFS bit. For more detailed information, see the Enhanced Comparator (eCOMP) chapter of the
MSP430FR4xx and MSP430FR2xx Family User's Guide.
A 1.2-V reference voltage can be buffered, when EXTREFEN = 1 on PMMCTL2 register, and it can be
output to P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/TRI0+/A7/VREF+ , meanwhile the ADC channel 7 can
also be selected to monitor this voltage. For more detailed information, see the MSP430FR4xx and
MSP430FR2xx Family User's Guide.
6.11.2 Clock System (CS) and Clock Distribution
The clock system includes a 32-kHz low-frequency oscillator (XT1 low frequency) or up to a 16-MHz high-
frequency crystal oscillator (XT1 high frequency), an internal very low-power low-frequency oscillator
(VLO), an integrated 32-kHz RC oscillator (REFO), an integrated internal digitally controlled oscillator
(DCO) that can use frequency-locked loop (FLL) locking with internal or external 32-kHz reference clock,
and on-chip asynchronous high-speed clock (MODOSC). The clock system is designed to target cost-
effective designs with minimal external components. A fail-safe mechanism is designed for XT1. The clock
system module offers the following clock signals.
•
Main Clock (MCLK): system clock used by the CPU and all relevant peripherals accessed by the bus.
All clock sources except MODOSC can be selected as the source with a predivider of 1, 2, 4, 8, 16,
32, 64, or 128.
•
•
Sub-Main Clock (SMCLK): subsystem clock used by the peripheral modules. SMCLK derives from the
MCLK with a predivider of 1, 2, 4, or 8. This means SMCLK is always equal to or less than MCLK.
Auxiliary Clock (ACLK): derived from the external XT1 clock or internal REFO clock up to 40 kHz.
All peripherals may have one or several clock sources depending on specific functionality. Table 6-8 and
Table 6-9 show the clock distribution used in this device.
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Table 6-8. Clock Distribution
CLOCK
SOURCE
SELECT
BITS(1)
MCLK
SMCLK
ACLK
MODCLK
VLOCLK
EXTERNAL PIN
Frequency
Range
DC to 16 MHz DC to 16 MHz DC to 40 kHz
5 MHz ±10%
10 kHz ±50%
–
CPU
N/A
N/A
Default
–
–
–
–
–
–
–
–
–
–
–
FRAM
RAM
Default
–
N/A
Default
–
–
–
–
–
CRC
N/A
Default
–
–
–
I/O
N/A
Default
–
–
–
–
TB0
TBSSEL
TBSSEL
UCSSEL
UCSSEL
WDTSSEL
ADCSSEL
RTCSS
–
–
–
–
–
–
–
10b
01b
01b
01b
01b
01b
01b
01b(2)
–
–
00b (TB0CLK pin)
TB1
10b
–
–
00b (TB1CLK pin)
eUSCI_A0
eUSCI_B0
WDT
10b or 11b
10b or 11b
00b
–
–
00b (UCA0CLK pin)
–
–
00b (UCB0CLK pin)
–
10b
–
–
–
–
ADC
10b or 11b
01b(2)
00b
–
RTC
11b
(1) N/A = not applicable
(2) Controlled by the RTCCKSEL bit in the SYSCFG2 register.
SRAM
CRC
CPU
FRAM
I/O
SAC0
TIA0
eCOMP0
MCLK
Timer_B
A1
eUSCI_A0
RTC
ADC10
Timer_B
A0
eUSCI_B0
WDT
Clock System (CS)
SMCLK
ACLK
VLOCLK
MODCLK
XT1CLK
Selected on SYSCFG2
Figure 6-1. Clock Distribution Block Diagram
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Table 6-9. XTCLK Distribution
XTLFCLK
(LPMx.5)
XTHFCLK
XTLFCLK
OPERATION
MODE
CLOCK SOURCE
SELECT BITS
AM TO LPM0
AM TO LPM3
AM TO LPM3.5
MCLK
SELMS
SELMS
SELREF
SELA
10b
10b
0b
0b
–
10b
10b
0b
10b
10b
0b
SMCLK
REFO
ACLK
RTC
0b
0b
RTCSS
10b
10b
6.11.3 General-Purpose Input/Output Port (I/O)
There are up to 16 I/O ports implemented.
•
•
•
P1 and P2 are full 8-bit ports.
All individual I/O bits are independently programmable.
Any combination of input and output is possible for P1 and P2. All inputs of P1 and four inputs of P2
(P2.0, P2.1, P2.6, P2.7) can be configured for interrupt input.
•
•
Programmable pullup or pulldown on all ports.
All inputs of P1 and four inputs of P2 (P2.0, P2.1, P2.6, P2.7) can be configured for edge-selectable
interrupt and for LPM3.5, LPM4, and LPM4.5 wake-up input capability.
•
•
•
Read and write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise or word-wise in pairs.
Capacitive Touch I/O functionality is supported on all pins.
NOTE
Configuration of digital I/Os after BOR reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance
with Schmitt triggers and module functions disabled. To enable the I/O functions after a BOR
reset, the ports must be configured first and then the LOCKLPM5 bit must be cleared. For
details, see the Configuration After Reset section in the Digital I/O chapter of the
MSP430FR4xx and MSP430FR2xx Family User's Guide.
6.11.4 Watchdog Timer (WDT)
The primary function of the WDT module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not
needed in an application, the module can be configured as interval timer and can generate interrupts at
selected time intervals.
Table 6-10. WDT Clocks
NORMAL OPERATION
WDTSSEL
(WATCHDOG AND INTERVAL TIMER MODE)
00
01
10
11
SMCLK
ACLK
VLOCLK
Reserved
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6.11.5 System Module (SYS)
The SYS module handles many of the system functions within the device. These system functions include
power-on reset (POR) and power-up clear (PUC) handling, NMI source selection and management, reset
interrupt vector generators, bootloader entry mechanisms, and configuration management (device
descriptors) (see Table 6-11). SYS also includes a data exchange mechanism through SBW called a
JTAG mailbox that can be used in the application.
Table 6-11. System Module Interrupt Vector Registers
INTERRUPT VECTOR
ADDRESS
INTERRUPT EVENT
VALUE
PRIORITY
REGISTER
No interrupt pending
Brownout (BOR)
00h
02h
Highest
RSTIFG RST/NMI (BOR)
PMMSWBOR software BOR (BOR)
LPMx.5 wakeup (BOR)
Security violation (BOR)
Reserved
04h
06h
08h
0Ah
0Ch
0Eh
SVSHIFG SVSH event (BOR)
Reserved
10h
Reserved
12h
SYSRSTIV, System Reset
015Eh
PMMSWPOR software POR (POR)
WDTIFG watchdog time-out (PUC)
WDTPW password violation (PUC)
FRCTLPW password violation (PUC)
Uncorrectable FRAM bit error detection
Peripheral area fetch (PUC)
PMMPW PMM password violation (PUC)
Reserved
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
FLL unlock (PUC)
24h
Reserved
26h to 3Eh
00h
Lowest
Highest
No interrupt pending
SVS low-power reset entry
Uncorrectable FRAM bit error detection
Reserved
02h
04h
06h
Reserved
08h
Reserved
0Ah
Reserved
0Ch
0Eh
SYSSNIV, System NMI
015Ch
Reserved
Reserved
10h
VMAIFG Vacant memory access
JMBINIFG JTAG mailbox input
JMBOUTIFG JTAG mailbox output
Correctable FRAM bit error detection
Reserved
12h
14h
16h
18h
1Ah to 1Eh
00h
Lowest
Highest
Lowest
No interrupt pending
NMIIFG NMI pin or SVSH event
OFIFG oscillator fault
Reserved
02h
SYSUNIV, User NMI
015Ah
04h
06h to 1Eh
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6.11.6 Cyclic Redundancy Check (CRC)
The 16-bit cyclic redundancy check (CRC) module produces a signature based on a sequence of data
values and can be used for data checking purposes. The CRC generation polynomial is compliant with
CRC-16-CCITT standard of x16 + x12 + x5 + 1.
6.11.7 Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
The eUSCI modules are used for serial data communications. The eUSCI_A module supports either
UART or SPI communications. The eUSCI_B module supports either SPI or I2C communications. In
addition, the eUSCI_A module supports automatic baud-rate detection and IrDA.. The eUSCI_B module is
connected either from P1 port or P2 port, it can be selected from the USCIBRMAP bit of the SYSCFG2
register (see Table 6-12).
Table 6-12. eUSCI Pin Configurations
PIN
UART
TXD
RXD
–
SPI
SIMO
SOMI
SCLK
STE
P1.7
eUSCI_A0
P1.6
P1.5
P1.4
–
PIN (USCIBRMP = 0)
I2C
SPI
P1.0
–
STE
P1.1
–
SCLK
SIMO
SOMI
SPI
P1.2
SDA
SCL
I2C
–
P1.3
eUSCI_B0
PIN (USCIBRMP = 1)
P2.2
P2.3
P2.4
P2.5
STE
–
SCLK
SIMO
SOMI
SDA
SCL
6.11.8 Timers (Timer0_B3, Timer1_B3)
The Timer0_B3 and Timer1_B3 modules are 16-bit timers and counters with three capture/compare
registers each. Each can support multiple captures or compares, PWM outputs, and interval timing (see
Table 6-13 and Table 6-14). Each has extensive interrupt capabilities. Interrupts may be generated from
the counter on overflow conditions and from each of the capture/compare registers. The CCR0 registers
on TB0 and TB1 are not externally connected and can be used only for hardware period timing and
interrupt generation. In Up mode, they can set the overflow value of the counter.
The interconnection of Timer0_B3 and Timer1_B3 can modulate the eUSCI_A pin of
UCA0TXD/UCA0SIMO in either ASK or FSK mode, with which a user can easily acquire a modulated
infrared command for directly driving an external IR diode (see Figure 6-2). The IR functions are fully
controlled by the SYS configuration registers including IREN (enable), IRPSEL (polarity select), IRMSEL
(mode select), IRDSSEL (data select), and IRDATA (data) bits. For more information, see the System
Resets, Interrupts, and Operating Modes, System Control Module (SYS) chapter in the MSP430FR4xx
and MSP430FR2xx Family User's Guide.
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Timer_B0
Timer_B1
P2.7_TB0CLK
ACLK
00
01
10
11
P2.2_TB1CLK
ACLK
00
01
16-bit Counter
SMCLK
16-bit Counter
Capcitive Touch IO
SMCLK
10
11
00
01
10
11
RTC
ACLK
DVSS
DVCC
DVSS
TB0.0A
TB0.0B
00
CCR0
CCR1
CCR2
01
10
11
TB0.0A
TB0.0B
CCR0
CCR1
CCR2
DVSS
DVCC
P1.6
eCOMP
DVSS
00
01
10
11
TB0.1A
TB0.1B
P1.6
P2.0
00
01
10
11
TB0.1A
TB0.1B
P2.0
DVCC
DVSS
DVCC
To ADC Trigger
P1.7
Capcitive Touch IO
DVSS
00
01
10
11
TB0.2A
TB0.2B
P1.7
P2.1
00
01
10
11
TB0.2A
TB0.2B
P2.1
DVCC
DVSS
DVCC
Coding
Carrier
Infrared
Logic (SYS)
P1.7/UCA0TXD/UCA0SIMO
UCA0TXD/UCA0SIMO
eUSCI_A0
Data
Figure 6-2. Timer_B Connections
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Table 6-13. Timer0_B3 Signal Connections
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
PORT PIN
MODULE BLOCK
P2.7
TB0CLK
TBCLK
ACLK
ACLK (internal)
SMCLK (internal)
Timer
N/A
TB0
TB1
SMCLK
From Capacitive
Touch I/O (internal)
INCLK
CCI0A
CCI0B
From RTC (internal)
Timer1_B3 CCI0B
input
ACLK (internal)
CCR0
CCR1
DVSS
DVCC
TB0.1
GND
VCC
P1.6
P1.7
CCI1A
TB0.1
From eCOMP
(internal)
Timer1_B3 CCI1B
input
CCI1B
DVSS
DVCC
TB0.2
GND
VCC
CCI2A
TB0.2
Timer1_B3 INCLK
Timer1_B3 CCI2B
input,
From Capacitive
Touch I/O (internal)
CCI2B
CCR2
TB2
IR input
DVSS
DVCC
GND
VCC
Table 6-14. Timer1_B3 Signal Connections
DEVICE INPUT
MODULE INPUT
NAME
MODULE OUTPUT
DEVICE OUTPUT
SIGNAL
PORT PIN
MODULE BLOCK
SIGNAL
SIGNAL
P2.2
TB1CLK
TBCLK
ACLK
ACLK (internal)
SMCLK (internal)
Timer
N/A
SMCLK
Timer0_B3 CCR2B
output (internal)
INCLK
CCI0A
CCI0B
DVSS
Timer0_B3 CCR0B
output (internal)
CCR0
CCR1
CCR2
TB0
TB1
TB2
DVSS
DVCC
TB1.1
GND
VCC
P2.0
P2.1
CCI1A
TB1.1
Timer0_B3 CCR1B
output (internal)
CCI1B
To ADC trigger
DVSS
DVCC
TB1.2
GND
VCC
CCI2A
TB1.2
Timer0_B3 CCR2B
output (internal)
CCI2B
IR input
DVSS
DVCC
GND
VCC
56
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The Timer_B module includes a feature that puts all Timer_B outputs into a high-impedance state when
the selected source is triggered. The source can be selected from an external pin or an internal signal,
and it is controlled by TBxTRG in SYS. For more information, see the System Resets, Interrupts, and
Operating Modes, System Control Module (SYS) chapter in the MSP430FR4xx and MSP430FR2xx Family
User's Guide.
Table 6-15 lists the Timer_B high-impedance trigger source selections.
Table 6-15. TBxOUTH
TBxOUTH TRIGGER SOURCE
SELECTION
Timer_B PAD OUTPUT HIGH
IMPEDANCE
TBxTRGSEL
TB0TRGSEL = 0
TB0TRGSEL= 1
TB1TRGSEL = 0
TB1TRGSEL = 1
eCOMP0 output (internal)
P1.6, P1.7
P2.0, P2.1
P1.2
eCOMP0 output (internal)
P2.3
6.11.9 Backup Memory (BAKMEM)
The BAKMEM supports data retention during LPM3.5 mode. This device provides up to 32 bytes that are
retained during LPM3.5.
6.11.10 Real-Time Clock (RTC) Counter
The RTC counter is a 16-bit modulo counter that is functional in AM, LPM0, LPM3, LPM4, and LPM3.5.
This module may periodically wake up the CPU from LPM0, LPM3, LPM4, and LPM3.5 based on timing
from a low-power clock source such as the XT1, ACLK, or VLO clocks. In AM, RTC can be driven by
SMCLK to generate high-frequency timing events and interrupts. ACLK and SMCLK both can source to
the RTC, however only one of them can be selected simultaneously. The RTC overflow events trigger:
•
•
Timer0_B3 CCI0A
ADC conversion trigger when ADCSHSx bits are set as 01b
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6.11.11 10-Bit Analog-to-Digital Converter (ADC)
The 10-bit ADC module supports fast 10-bit analog-to-digital conversions with single-ended input. The
module implements a 10-bit SAR core, sample select control, a reference generator, and a conversion
result buffer. A window comparator with lower and upper limits allows CPU-independent result monitoring
with three window comparator interrupt flags.
The ADC supports 10 external inputs and 4 internal inputs (see Table 6-16).
Table 6-16. ADC Channel Connections
ADCINCHx
ADC CHANNELS
A0/Veref+
A1
EXTERNAL PIN
P1.0
0
1
P1.1
2
A2/Veref-
A3
P1.2
3
P1.3
4
A4
P1.4
5
A5
P1.5
6
A6
P1.6
7
A7(1)
P1.7
8
Not used
Not used
Not used
Not used
N/A
9
N/A
10
11
N/A
N/A
On-chip temperature
sensor
12
N/A
13
14
15
Reference voltage (1.5 V)
N/A
N/A
N/A
DVSS
DVCC
(1) When A7 is used, the PMM 1.2-V reference voltage can be output to
this pin by setting the PMM control register. The 1.2-V voltage can
be measured by the A7 channel.
The analog-to-digital conversion can be started by software or a hardware trigger. Table 6-17 lists the
trigger sources that are available.
Table 6-17. ADC Trigger Signal Connections
ADCSHSx
TRIGGER SOURCE
BINARY
DECIMAL
00
01
10
11
0
1
2
3
ADCSC bit (software trigger)
RTC event
TB1.1B
eCOMP0 COUT
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6.11.12 eCOMP0
The enhanced comparator is an analog voltage comparator with built-in 6-bit DAC as an internal voltage
reference. The integrated 6-bit DAC can be set up to 64 steps for comparator reference voltage. This
module has 4-level programmable hysteresis and configurable power modes, high power or low power.
eCOMP0 supports external inputs and internal inputs (see Table 6-18) and outputs (see Table 6-19).
Table 6-18. eCOMP0 Input Channel Connections
CPPSEL, CPNSEL
EXTERNAL OR INTERNAL
CONNECTION
eCOMP0 CHANNELS
BINARY
000
C0
P1.0
P1.1
N/A
001
C1
010
Not used
Not used
011
N/A
SAC0 , OA0O on positive port
TIA0, TRI0O on negative port
100
C4
101
110
Not used
C6
N/A
Built-in 6-bit DAC
Table 6-19. eCOMP0 Output Channel Connections
eCOMP0 OUT
EXTERNAL PIN OUT, MODULE
P2.0
1
2
TB0.1B, TB0 (TB0OUTH), TB1 (TB1OUTH), ADC
6.11.13 SAC0
The Smart Analog Combo (SAC) integrates a high-performance low-power operational amplifier. SAC-L1
is integrated in FR231x. SAC-L1 supports only a general-purpose amplifier. For more information, see the
Smart Analog Combo (SAC) chapter in the MSP430FR4xx and MSP430FR2xx Family User's Guide.
SAC0 supports external inputs and internal inputs (see Table 6-20 and Table 6-21).
Table 6-20. SAC0 Positive Input Channel Connections
PSEL
00
SAC0 CHANNELS
EXTERNAL PIN OUT, MODULE
SAC0, OA0 positive channel 1
SAC0, OA0 positive channel 2
P1.4
10
TRI0O
Table 6-21. SAC0 Negative Input Channel Connections
NSEL
00
SAC0 CHANNELS
SAC0, OA0 negative channel 1
Not used
EXTERNAL PIN OUT, MODULE
P1.2
N/A
10
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6.11.14 TIA0
The Transimpedance Amplifier (TIA) is a high-performance low-power amplifier with rail-to-rail output. This
module is an amplifier that converts current to voltage. It has programmable power modes: high power or
low power. For more information, see the Transimpedance Amplifier (TIA) chapter in the MSP430FR4xx
and MSP430FR2xx Family User's Guide.
The FR231x device in the TSSOP-16 package supports a dedicated low-leakage pad for TIA negative
input to support low-leakage performance. In other packages (TSSOP-20 and VQFN-16), the TIA negative
port is shared with a GPIO to support the transimpedance amplifier function. For more information, see
Section 4 and Table 5-25.
The TIA supports external input (see Table 6-22 and Section 4).
Table 6-22. TIA Input Channel Connections
TRIPSEL
TIA0 CHANNELS
Positive input
Not used
EXTERNAL PIN OUT, MODULE
00
01
10
11
P1.7
N/A
N/A
N/A
Not used
Not used
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6.11.15 eCOMP0, SAC0, TIA0, and ADC in SOC Interconnection
Figure 6-3 shows how the high-performance analog modules are internally connected.
P1.6 & TRI0–
Double Bonding
in TSSOP-20 & QFN16
A6
P1.6
A5
–
TRI0–
P1.5/TRI0O
P1.7/TRI+
00
10
+
TIA
A7
A0
A1
A2
A3
A4
A5
A6
A7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
A1
A0
00
01
10
11
Software Trigger
from RTC
ADC
Core
from TB1.1B
from eCOMP
DAC
Core
A12
A13
A14
A15
On-chip Temperature Sensor
1.5V Reference Voltage
DVSS
HW Trigger
Selection
DVCC
ADC
000
P1.1/C1
001
100
110
–
+
Invert
Non-invert
Logic
P2.0/COUT
P1.0/C0
000
001
100
110
eCOMP
10
00
+
–
P1.4/OA0+
P1.2/OA0–
P1.3/OA0O
00
10
SAC-L1
A3
A4
A2
Figure 6-3. High-Performance Analog SOC Interconnection
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Figure 6-4 shows how the analog modules can be connected internally.
Timer_B0
Timer_B1
P2.7_TB0CLK
ACLK
00
01
10
11
P2.2_TB1CLK
ACLK
00
01
10
11
16-bit Counter
SMCLK
16-bit Counter
from
CapTouch
SMCLK
RTC
ACLK
DVSS
DVCC
00
01
10
11
P1.6
Double Bonding
in TSSOP-20 QFN16
& TRI0–
TB0.0A
TB0.0B
DVSS
00
01
10
11
&
CCR0
TB0.0A
TB0.0B
CCR0
DVSS
DVCC
P1.6
A6
P1.6
00
01
10
11
from
COMP
TRI0–
P1.7
–
+
TB0.1A
TB0.1B
P1.6
P2.0
00
01
10
11
CCR1
A5
DVSS
TB0.1A
TB0.1B
P2.0
CCR1
00
10
DVCC
DVSS
DVCC
TIA
A7
A1
P1.7
00
01
10
11
from
CapTouch
TB0.2A
TB0.2B
P1.7
P2.1
00
01
10
11
CCR2
DVSS
DVCC
TB0.2A
TB0.2B
P2.1
A0
A1
P1.0
CCR2
DVSS
DVCC
P1.1
A2
P1.2
TB0OUTH
TB1OUTH
A3
P1.3
DAC
Core
P1.5
A4
P1.4
TB1TRG
A5
P1.5
TB0TRG
1
0
0
1
A6
P1.6
C0O
C0O
000
001
100
110
A7
P1.7
C1
P1.1
A8
Not Used
Software Trigger
from RTC
RTC
Overflow
SYS
00
01
10
11
A9
Not Used
TB0TRGSEL
TB1TRGSEL
RTC Counter
A10
A11
A12
A13
A14
A15
Not Used
ADC
Core
from TB1.1B
from COMP
–
+
Not Used
Invert
Non-invert
Logic
On-chip Temperature Sensor
1.5V Reference Voltage
DVSS
HW Trigger
Selection
C0
P1.0
000
001
100
110
ADC
DVCC
eCOMP
Coding
IR Logic
A0
A3
Carrier
Data
P1.7/UCA0TXD/UCA0SIMO
10
00
+
–
P1.4/OA0+
P1.2/OA0–
UCA0TXD/UCA0SIMO
eUSCI_A
00
10
SAC-L1
P1.3/OA0O
A2
A4
P2.0
Figure 6-4. SOC Interconnection
6.11.16 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The EEM on these devices has the following features:
•
•
•
•
•
Three hardware triggers or breakpoints on memory access
One hardware trigger or breakpoint on CPU register write access
Up to four hardware triggers that can be combined to form complex triggers or breakpoints
One cycle counter
Clock control on module level
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6.11.17 Peripheral File Map
Table 6-23 lists the base address of the registers for each peripheral. Table 6-24 through Table 6-42 list
all of the available registers for each peripheral and their address offsets.
Table 6-23. Peripherals Summary
MODULE NAME
Special Functions (see Table 6-24)
BASE ADDRESS
0100h
SIZE
0010h
0020h
0040h
0020h
0010h
0008h
0002h
0020h
0010h
0010h
0030h
0030h
0020h
0030h
0020h
0040h
0020h
0010h
0010h
PMM (see Table 6-25)
0120h
SYS (see Table 6-26)
0140h
CS (see Table 6-27)
0180h
FRAM (see Table 6-28)
CRC (see Table 6-29)
01A0h
01C0h
01CCh
0200h
WDT (see Table 6-30)
Port P1, P2 (see Table 6-31)
Capacitive Touch I/O (see Table 6-32)
RTC (see Table 6-33)
02E0h
0300h
Timer0_B3 (see Table 6-34)
Timer1_B3 (see Table 6-35)
eUSCI_A0 (see Table 6-36)
eUSCI_B0 (see Table 6-37)
Backup Memory (see Table 6-38)
ADC (see Table 6-39)
0380h
03C0h
0500h
0540h
0660h
0700h
eCOMP0 (see Table 6-40)
SAC0 (see Table 6-41)
08E0h
0C80h
0F00h
TIA0 (see Table 6-42)
Table 6-24. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
SFRIE1
OFFSET
00h
SFR interrupt enable
SFR interrupt flag
SFRIFG1
SFRRPCR
02h
SFR reset pin control
04h
Table 6-25. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
PMMCTL0
PMMCTL1
PMMCTL2
PMMIFG
OFFSET
00h
PMM control 0
PMM control 1
PMM control 2
PMM interrupt flags
PM5 control 0
02h
04h
0Ah
PM5CTL0
10h
Table 6-26. SYS Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
SYSCTL
OFFSET
00h
System control
Bootloader configuration area
JTAG mailbox control
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
SYSBSLC
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
02h
06h
08h
0Ah
0Ch
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Table 6-26. SYS Registers (Base Address: 0140h) (continued)
REGISTER DESCRIPTION
JTAG mailbox output 1
REGISTER
SYSJMBO1
SYSUNIV
SYSSNIV
OFFSET
0Eh
1Ah
1Ch
1Eh
20h
22h
24h
User NMI vector generator
System NMI vector generator
Reset vector generator
System configuration 0
System configuration 1
System configuration 2
SYSRSTIV
SYSCFG0
SYSCFG1
SYSCFG2
Table 6-27. CS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
CSCTL0
CSCTL1
CSCTL2
CSCTL3
CSCTL4
CSCTL5
CSCTL6
CSCTL7
CSCTL8
OFFSET
00h
CS control 0
CS control 1
CS control 2
CS control 3
CS control 4
CS control 5
CS control 6
CS control 7
CS control 8
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
Table 6-28. FRAM Registers (Base Address: 01A0h)
REGISTER DESCRIPTION
REGISTER
FRCTL0
OFFSET
00h
FRAM control 0
General control 0
General control 1
GCCTL0
GCCTL1
04h
06h
Table 6-29. CRC Registers (Base Address: 01C0h)
REGISTER DESCRIPTION
REGISTER
CRC16DI
OFFSET
00h
CRC data input
CRC data input reverse byte
CRC initialization and result
CRC result reverse byte
CRCDIRB
CRCINIRES
CRCRESR
02h
04h
06h
Table 6-30. WDT Registers (Base Address: 01CCh)
REGISTER DESCRIPTION
REGISTER
OFFSET
Watchdog timer control
WDTCTL
00h
Table 6-31. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
P1IN
OFFSET
00h
Port P1 input
Port P1 output
P1OUT
P1DIR
02h
Port P1 direction
04h
Port P1 pulling enable
Port P1 selection 0
Port P1 selection 1
Port P1 interrupt vector word
P1REN
P1SEL0
P1SEL1
P1IV
06h
0Ah
0Ch
0Eh
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Table 6-31. Port P1, P2 Registers (Base Address: 0200h) (continued)
REGISTER DESCRIPTION
REGISTER
P1SELC
P1IES
OFFSET
16h
Port P1 complement selection
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
18h
P1IE
1Ah
1Ch
01h
P1IFG
P2IN
Port P2 output
P2OUT
P2DIR
P2REN
P2SEL0
P2SEL1
P2SELC
P2IV
03h
Port P2 direction
05h
Port P2 pulling enable
Port P2 selection 0
07h
0Bh
0Dh
17h
Port P2 selection 1
Port P2 complement selection
Port P2 interrupt vector word
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
1Eh
19h
P2IES
P2IE
1Bh
1Dh
P2IFG
Table 6-32. Capacitive Touch I/O Registers (Base Address: 02E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Capacitive touch I/O 0 control
CAPIO0CTL
0Eh
Table 6-33. RTC Registers (Base Address: 0300h)
REGISTER DESCRIPTION
REGISTER
RTCCTL
RTCIV
OFFSET
00h
RTC control
RTC interrupt vector
RTC modulo
04h
RTCMOD
RTCCNT
08h
RTC counter
0Ch
Table 6-34. Timer0_B3 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
TB0CTL
OFFSET
00h
TB0 control
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TB0 counter
TB0CCTL0
TB0CCTL1
TB0CCTL2
TB0R
02h
04h
06h
10h
Capture/compare 0
Capture/compare 1
Capture/compare 2
TB0 expansion 0
TB0CCR0
TB0CCR1
TB0CCR2
TB0EX0
12h
14h
16h
20h
TB0 interrupt vector
TB0IV
2Eh
Table 6-35. Timer1_B3 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
TB1CTL
OFFSET
00h
TB1 control
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TB1CCTL0
TB1CCTL1
TB1CCTL2
02h
04h
06h
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Table 6-35. Timer1_B3 Registers (Base Address: 03C0h) (continued)
REGISTER DESCRIPTION
REGISTER
TB1R
OFFSET
TB1 counter
10h
12h
14h
16h
20h
2Eh
Capture/compare 0
Capture/compare 1
Capture/compare 2
TB1 expansion 0
TB1 interrupt vector
TB1CCR0
TB1CCR1
TB1CCR2
TB1EX0
TB1IV
Table 6-36. eUSCI_A0 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
UCA0CTLW0
UCA0CTLW1
UCA0BR0
OFFSET
00h
eUSCI_A control word 0
eUSCI_A control word 1
eUSCI_A control rate 0
eUSCI_A control rate 1
eUSCI_A modulation control
eUSCI_A status
02h
06h
UCA0BR1
07h
UCA0MCTLW
UCA0STAT
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
lUCA0IRTCTL
IUCA0IRRCTL
UCA0IE
08h
0Ah
0Ch
0Eh
10h
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
12h
13h
1Ah
1Ch
1Eh
UCA0IFG
UCA0IV
Table 6-37. eUSCI_B0 Registers (Base Address: 0540h)
REGISTER DESCRIPTION
REGISTER
UCB0CTLW0
UCB0CTLW1
UCB0BR0
OFFSET
00h
eUSCI_B control word 0
eUSCI_B control word 1
eUSCI_B bit rate 0
02h
06h
eUSCI_B bit rate 1
UCB0BR1
07h
eUSCI_B status word
UCB0STATW
UCB0TBCNT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA0
UCB0I2COA1
UCB0I2COA2
UCB0I2COA3
UCB0ADDRX
UCB0ADDMASK
UCB0I2CSA
UCB0IE
08h
eUSCI_B byte counter threshold
eUSCI_B receive buffer
eUSCI_B transmit buffer
eUSCI_B I2C own address 0
eUSCI_B I2C own address 1
eUSCI_B I2C own address 2
eUSCI_B I2C own address 3
eUSCI_B receive address
eUSCI_B address mask
eUSCI_B I2C slave address
eUSCI_B interrupt enable
eUSCI_B interrupt flags
eUSCI_B interrupt vector word
0Ah
0Ch
0Eh
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Ah
2Ch
2Eh
UCB0IFG
UCB0IV
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Table 6-38. Backup Memory Registers (Base Address: 0660h)
REGISTER DESCRIPTION
REGISTER
BAKMEM0
BAKMEM1
BAKMEM2
BAKMEM3
BAKMEM4
BAKMEM5
BAKMEM6
BAKMEM7
BAKMEM8
BAKMEM9
BAKMEM10
BAKMEM11
BAKMEM12
BAKMEM13
BAKMEM14
BAKMEM15
OFFSET
00h
Backup memory 0
Backup memory 1
Backup memory 2
Backup memory 3
Backup memory 4
Backup memory 5
Backup memory 6
Backup memory 7
Backup memory 8
Backup memory 9
Backup memory 10
Backup memory 11
Backup memory 12
Backup memory 13
Backup memory 14
Backup memory 15
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
Table 6-39. ADC Registers (Base Address: 0700h)
REGISTER DESCRIPTION
REGISTER
ADCCTL0
ADCCTL1
ADCCTL2
ADCLO
OFFSET
00h
ADC control 0
ADC control 1
02h
ADC control 2
04h
ADC window comparator low threshold
ADC window comparator high threshold
ADC memory control 0
ADC conversion memory
ADC interrupt enable
06h
ADCHI
08h
ADCMCTL0
ADCMEM0
ADCIE
0Ah
12h
1Ah
1Ch
1Eh
ADC interrupt flags
ADCIFG
ADC interrupt vector word
ADCIV
Table 6-40. eCOMP0 Registers (Base Address: 08E0h)
REGISTER DESCRIPTION
REGISTER
CPCTL0
OFFSET
00h
Comparator control 0
Comparator control 1
CPCTL1
02h
Comparator interrupt
CPINT
06h
Comparator interrupt vector
Comparator built-in DAC control
Comparator built-in DAC data
CPIV
08h
CPDACCTL
CPDACDATA
10h
12h
Table 6-41. SAC0 Registers (Base Address: 0C80h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SAC0 OA control
SAC0OA
00h
Table 6-42. TIA0 Registers (Base Address: 0F00h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TIA control
TRICTL
00h
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6.12 Input/Output Diagrams
6.12.1 Port P1 Input/Output With Schmitt Trigger
Figure 6-5 shows the port diagram. Table 6-43 summarizes the selection of the port functions.
A0..A7
OA0+,OA0-,OA0O
TRI0+,TRI0-,TRI0O
C0,C1
From analog module
P1REN.x
P1DIR.x
From Module1
From Module2
00
01
10
11
2 bit
DVSS
DVCC
0
1
P1SEL.x= 11
00
01
P1OUT.x
From Module1
From Module2
DVSS
10
11
2 bit
P1SEL.x
EN
D
To module
P1IN.x
P1IE.x
Bus
Keeper
P1 Interrupt
D
S
Q
P1.0/UCB0STE/SMCLK/C0/A0/Veref+
P1.1/UCB0CLK/ACLK/C1/A1
P1IFG.x
P1.2/UCB0SIMO/UCB0SDA/TB0TRG/OA0-/A2/Veref-
P1.3/UCB0SOMI/UCB0SCL/OA0O/A3
Edge
Select
P1IES.x
P1.4/UCA0STE/TCK/OA0+/A4
From JTAG
P1.5/UCA0CLK/TMS/TRI0O/A5
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/TRI0-/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/TRI0+/A7/VREF+
To JTAG
NOTE: Functional representation only.
Figure 6-5. Port P1 Input/Output With Schmitt Trigger
68
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Table 6-43. Port P1 Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SELx
00
JTAG
N/A
P1.0 (I/O)
UCB0STE
SMCLK
I: 0; O: 1
X
01
N/A
P1.0/UCB0STE/SMCLK/
C0/A0/Veref+
0
1
10
N/A
VSS
0
C0, A0/Veref+
P1.1 (I/O)
UCB0CLK
ACLK
X
11
0
N/A
N/A
N/A
I: 0; O: 1
X
01
P1.1/UCB0CLK/ACLK/
C1A1
1
1
10
N/A
VSS
0
C1, A1
X
11
00
01
10
11
00
01
11
00
01
11
X
N/A
N/A
P1.2 (I/O)
I: 0; O: 1
P1.2/UCB0SIMO/
UCB0SDA/TB0TRG/
OA0-/A2/Veref-
UCB0SIMO/UCB0SDA
TB0TRG
X
N/A
2
3
4
0
N/A
OA0-, A2/Veref-
P1.3 (I/O)
X
N/A
I: 0; O: 1
N/A
P1.3/UCB0SOMI/
UCB0SCL/OA0O/A3
UCB0SOMI/UCB0SCL
OA0O, A3
X
N/A
X
N/A
P1.4 (I/O)
I: 0; O: 1
Disabled
Disabled
Disabled
TCK
UCA0STE
X
P1.4/UCA0STE/TCK/
OA0+/A4
OA0+, A4
X
JTAG TCK
X
P1.5 (I/O)
I: 0; O: 1
00
01
11
X
Disabled
Disabled
Disabled
TMS
UCA0CLK
X
P1.5/UCA0CLK/TMS/
TRI0O/A5
5
6
TRI0O, A5
X
JTAG TMS
X
P1.6 (I/O)
I: 0; O: 1
00
01
Disabled
Disabled
UCA0RXD/UCA0SOMI
TB0.CCI1A
X
P1.6/UCA0RXD/
UCA0SOMI/TB0.1/TDI/
TCLK/TRI0-/A6
0
10
Disabled
TB0.1
1
TRI0-, A6
X
11
X
Disabled
TDI/TCLK
Disabled
Disabled
JTAG TDI/TCLK
P1.7 (I/O)
X
I: 0; O: 1
00
01
UCA0TXD/UCA0SIMO
TB0.CCI2A
X
0
P1.7/UCA0TXD/
UCA0SIMO/TB0.2/TDO/
TRI0+/A7/VREF+
7
10
Disabled
TB0.2
1
TRI0+, A7, VREF+
JTAG TDO
X
X
11
X
Disabled
TDO
(1) X = don't care
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6.12.2 Port P2 Input/Output With Schmitt Trigger
Figure 6-6 shows the port diagram. Table 6-44 summarizes the selection of the port functions.
P2REN.x
P2DIR.x
From Module1
From Module2
00
01
10
11
2 bit
DVSS
DVCC
0
1
00
01
P2OUT.x
From Module1
From Module2
DVSS
10
11
2 bit
P2SEL.x
EN
D
To module
P2IN.x
P2IE.x
Bus
Keeper
P2 Interrupt
D
S
Q
P2.0/TB1.1/COUT
P2.1/TB1.2
P2IFG.x
P2IES.x
P2.2/UCB0STE/TB1CLK
P2.3/UCB0CLK/TB1TRG
P2.4/UCB0SIMO/UCB0SDA
P2.5/UCB0SOMI/UCB0SCL
P2.6/MCLK/XOUT
Edge
Select
P2.7/TB0CLK/XIN
NOTE: Functional representation only.
Figure 6-6. Port P2 Input/Output With Schmitt Trigger
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Table 6-44. Port P2 Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SELx
P2.0 (I/O)
TB1.CCI1A
TB1.1
I: 0; O: 1
00
0
P2.0/TB1.1/COUT
P2.1/TB1.2
0
01
1
COUT
1
10
00
P2.1 (I/O)0
TB1.CCI2A
TB1.2
I: 0; O: 1
1
2
3
0
01
1
P2.2 (I/O)
UCB0STE
TB1CLK
VSS
I: 0; O: 1
00
01
X
P2.2/UCB0STE/TB1CLK
P2.3/UCB0CLK/TB1TRG
0
10
1
P2.3 (I/O)
UCB0CLK
TB1TRG
P2.4 (I/O)
I: 0; O: 1
00
01
10
00
01
00
01
00
X
0
I: 0; O: 1
P2.4/UCB0SIMO/UCB0SDA
P2.5/UCB0SOMI/UCB0SCL
4
5
UCB0SIMO/UCB0SDA
X
P2.5 (I/O)
UCB0SOMI/UCB0SCL
P2.6 (I/O)
MCLK
I: 0; O: 1
X
I: 0; O: 1
1
P2.6/MCLK/XOUT
6
7
01
VSS
0
XOUT
X
10
00
P2.7 (I/O)
TB0CLK
VSS
I: 0; O: 1
0
1
X
P2.7/TB0CLK/XIN
(1) X = don't care
01
10
XIN
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6.13 Device Descriptors (TLV)
Table 6-45 lists the Device IDs of the MSP430FR231x MCU variants. Table 6-46 lists the contents of the
device descriptor tag-length-value (TLV) structure for the devices.
Table 6-45. Device IDs
DEVICE ID
DEVICE
1A04h
F0
1A05h
82
MSP430FR2311
MSP430FR2310
F1
82
Table 6-46. Device Descriptors
MSP430FR231x
ADDRESS
DESCRIPTION
Info length
VALUE
06h
1A00h
1A01h
1A02h
1A03h
1A04h
1A05h
1A06h
1A07h
1A08h
1A09h
1A0Ah
1A0Bh
1A0Ch
1A0Dh
1A0Eh
1A0Fh
1A10h
1A11h
1A12h
1A13h
1A14h
1A15h
1A16h
1A17h
1A18h
1A19h
1A1Ah
1A1Bh
1A1Ch
1A1Dh
CRC length
06h
Per unit
Per unit
CRC value(1)
Info block
Device ID
See Table 6-45.
Hardware revision
Firmware revision
Die record tag
Per unit
Per unit
08h
Die record length
0Ah
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Lot wafer ID
Die record
Die X position
Die Y position
Test result
ADC calibration tag
ADC calibration length
ADC gain factor
ADC calibration
ADC offset
ADC 1.5-V reference, temperature 30°C(2)
ADC 1.5-V reference, temperature 85°C(2)
(1) The CRC value covers the checksum from 0x1A04h to 0x1A77h by applying CRC-CCITT-16 polynomial of X16 + X12 + X5 + 1
(2) TI recommends to do a two-point calibration for the on-chip temperature sensor in precision application.
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Table 6-46. Device Descriptors (continued)
MSP430FR231x
DESCRIPTION
ADDRESS
1A1Eh
1A1Fh
1A20h
VALUE
12h
Calibration tag
Calibration length
04h
Per unit
Per unit
Per unit
Per unit
Reference and DCO
calibration
1.5-V reference factor
1A21h
1A22h
(3)
DCO tap settings for 16 MHz, temperature 30°C
1A23h
(3) This value can be directly loaded into the DCO bits in the CSCTL0 register to get an accurate 16-MHz frequency at room temperature,
especially when MCU exits from LPM3 and below. TI also suggests using a predivider to decrease the frequency if the temperature drift
might result an overshoot above 16 MHz.
6.14 Identification
6.14.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings. For links to all of the errata sheets for the devices
in this data sheet, see 节 8.4.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Hardware Revision" entries in Section 6.13.
6.14.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings. For links to all of the errata sheets for the devices in this data
sheet, see 节 8.4.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Device ID" entries in Section 6.13.
6.14.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
detail in the MSP430 Programming With the JTAG Interface.
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7 Applications, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI's customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their implementation to confirm system functionality.
7.1 Device Connection and Layout Fundamentals
This section describes the recommended guidelines when designing with the MSP430. These guidelines
are to make sure that the device has proper connections for powering, programming, debugging, and
optimum analog performance.
7.1.1 Power Supply Decoupling and Bulk Capacitors
TI recommends connecting a combination of a 10-µF capacitor and a 100-nF low-ESR ceramic decoupling
capacitor to the DVCC pin. Higher-value capacitors may be used but can affect supply rail ramp-up time.
Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few
millimeters).
DVCC
Digital
+
Power Supply
Decoupling
DVSS
10 µF
100 nF
Figure 7-1. Power Supply Decoupling
7.1.2 External Oscillator
Depending on the device variant (see Table 3-1), the device can support a low-frequency crystal (32 kHz)
on the LFXT pins, a high-frequency crystal on the HFXT pins, or both. External bypass capacitors for the
crystal oscillator pins are required.
It is also possible to apply digital clock signals to the LFXIN and HFXIN input pins that meet the
specifications of the respective oscillator if the appropriate LFXTBYPASS or HFXTBYPASS mode is
selected. In this case, the associated LFXOUT and HFXOUT pins can be used for other purposes. If the
LFXOUT and HFXOUT pins are left unused, they must be terminated according to Section 4.6.
Figure 7-2 shows a typical connection diagram.
LFXIN
or
LFXOUT
or
HFXIN
HFXOUT
CL1
CL2
Figure 7-2. Typical Crystal Connection
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See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal
oscillator with the MSP430 devices.
7.1.3 JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or
MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the
connections also support the MSP-GANG production programmers, thus providing an easy way to
program prototype boards, if desired. Figure 7-3 shows the connections between the 14-pin JTAG
connector and the target device required to support in-system programming and debugging for 4-wire
JTAG communication. Figure 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are
identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSP-
FET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an
alternate connection (pin 4 instead of pin 2). The VCC-sense feature detects the local VCC present on the
target board (that is, a battery or other local power supply) and adjusts the output signals accordingly.
Figure 7-3 and Figure 7-4 show a jumper block that supports both scenarios of supplying VCC to the target
board. If this flexibility is not required, the desired VCC connections may be hardwired to eliminate the
jumper block. Pins 2 and 4 must not be connected at the same time.
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User’s
Guide.
VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
DVCC
J2 (see Note A)
R1
47 kW
JTAG
RST/NMI/SBWTDIO
VCC TOOL
TDO/TDI
TDI
TDO/TDI
TDI
2
1
VCC TARGET
4
3
TMS
TMS
6
5
7
TEST
TCK
8
TCK
GND
RST
10
12
14
9
11
13
TEST/SBWTCK
DVSS
C1
1 nF
(see Note B)
Copyright © 2016, Texas Instruments Incorporated
A. If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,
make connection J2.
B. The upper limit for C1 is 1.1 nF when using TI tools. TI recommends a 1-nF capacitor to enable high-speed SBW
communication.
Figure 7-3. Signal Connections for 4-Wire JTAG Communication
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VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
J2 (see Note A)
DVCC
R1
47 kΩ
(see Note B)
JTAG
VCC TOOL
TDO/TDI
2
1
3
5
7
9
RST/NMI/SBWTDIO
VCC TARGET
4
6
TCK
8
GND
10
12
14
11
13
TEST/SBWTCK
DVSS
C1
1 nF
(see Note B)
Copyright © 2016, Texas Instruments Incorporated
A. Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the
debug or programming adapter.
B. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with
the device. The upper limit for C1 is 1.1 nF when using TI tools. TI recommends a 1-nF capacitor to enable high-
speed SBW communication.
Figure 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
7.1.4 Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function
Register (SFR), SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is
edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the
external NMI. When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either
pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.
If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an
external 47-kΩ pullup resistor to the RST/NMI pin with a 10-nF pulldown capacitor. The pulldown capacitor
should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire
JTAG mode with TI tools like FET interfaces or GANG programmers.
See the MSP430FR4xx and MSP430FR2xx Family User's Guide for more information on the referenced
control registers and bits.
7.1.5 Unused Pins
For details on the connection of unused pins, see Section 4.6.
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7.1.6 General Layout Recommendations
•
Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430
32-kHz Crystal Oscillators for recommended layout guidelines.
•
•
Proper bypass capacitors on DVCC, AVCC, and reference pins if used.
Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital
switching signals such as PWM or JTAG signals away from the oscillator circuit and ADC signals.
•
Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See MSP430 System-Level ESD Considerations for guidelines.
7.1.7 Do's and Don'ts
During power up, power down, and device operation, the voltage difference between AVCC and DVCC
must not exceed the limits specified in the Absolute Maximum Ratings section. Exceeding the specified
limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
7.2 Peripheral- and Interface-Specific Design Information
7.2.1 ADC Peripheral
7.2.1.1 Partial Schematic
Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used.
DVSS
Using an external
VREF+/VEREF+
positive reference
+
100 nF
10 µF
Using an external
negative reference
VEREF-
+
10 µF
100 nF
Figure 7-5. ADC Grounding and Noise Considerations
7.2.1.2 Design Requirements
As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should
be followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with
other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset
voltages that can add to or subtract from the reference or input voltages of the ADC. The general
guidelines in Section 7.1.1 combined with the connections shown in Figure 7-5 prevent this.
In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital
switching or switching power supplies can corrupt the conversion result. TI recommends a noise-free
design using separate analog and digital ground planes with a single-point connection to achieve high
accuracy.
Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The
internal reference module has a maximum drive current as described in the sections ADC Pin Enable and
1.2-V Reference Settings of the MSP430FR4xx and MSP430FR2xx Family User's Guide.
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The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are
selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage
enters the device. In this case, the 10-µF capacitor buffers the reference pin and filters any low-frequency
ripple. A bypass capacitor of 100 nF filters out any high-frequency noise.
7.2.1.3 Layout Guidelines
Components that are shown in the partial schematic (see Figure 7-5) should be placed as close as
possible to the respective device pins to avoid long traces, because they add additional parasitic
capacitance, inductance, and resistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),
because the high-frequency switching can be coupled into the analog signal.
7.3 Typical Applications
Table 7-1 provides a link to a LaunchPad™ development kit. For the most up-to-date list of available tools
and TI Designs, see the device-specific product folders listed in 节 8.5.
Table 7-1. Tools
NAME
LINK
MSP430FR2311 LaunchPad Development Kit
http://www.ti.com/tool/MSP-EXP430FR2311
78
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8 器件和文档支持
8.1 使用入门
有关可帮助进行开发的 MSP430™系列器件、工具和库的更多信息，请查看 MSP430™ 超低功耗感应和测
量 MCU 概述。
8.2 器件命名规则
为了标示产品开发周期所处的阶段，TI 为所有 MSP MCU 器件的部件号分配了前缀。每个 MSP MCU 商用
系列产品成员都具有以下两个前缀之一：MSP 或 XMS。这些前缀代表了产品开发的发展阶段，即从工程原
型 (XMS) 直到完全合格的生产器件 (MSP)。
XMS - 实验器件，不一定代表最终器件的电气规格
MSP - 完全合格的生产器件
XMS 器件在供货时附带如下免责声明：
“开发中的产品用于内部评估用途。”
MSP 器件的特性已经全部明确，并且器件的质量和可靠性已经完全论证。TI 的标准保修证书对该器件适
用。
预测显示原型器件 (XMS) 的故障率大于标准生产器件。由于这些器件的预计最终使用故障率尚不确定，德
州仪器 (TI) 建议不要将它们用于任何生产系统。请仅使用合格的生产器件。
TI 器件的命名规则还包括一个带有器件系列名称的后缀。此后缀表示温度范围、封装类型和配送形式。图 8-
1 提供了解读完整器件名称的图例。
MSP 430
311
I
FR
2
PW R
Distribution Format
Processor Family
MCU Platform
Packaging
Memory Type
Series
Temperature Range
Feature Set
Processor Family
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
MCU Platform
Memory Type
Series
MSP430 = TI’s MSP430 16-Bit Low-Power Microcontroller Platform
FR = FRAM
2 = FRAM 2 Series up to 16 MHz without LCD
Feature Set
First and Second Digits: Smart Analog Combo (SAC) Level /
ADC Channels / COMP / 16-bit Timers / I/O
31 = SAC-L1 / Up to 8 / 1 / 2 / Up to 16
Third Digit: FRAM (KB) / SRAM (KB)
1 = 4 / 1
0 = 2 / 1
Temperature Range
Packaging
I = –40°C to 85°C
www.ti.com/packaging
Distribution Format
T = Small reel
R = Large reel
No marking = Tube or tray
图 8-1. 器件命名规则
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8.3 工具和软件
表 8-1列出了这些微控制器 支持 的调试功能。请参阅《适用于 MSP430 MCU 的 Code Composer Studio
IDE 用户指南》，以了解有关可用 功能）的详细信息。
表 8-1. 硬件 特性
四线制
JTAG
两线制
JTAG
断点
(N)
跟踪缓冲 LPMx.5 调试支
MSP430 架构
范围断点
有
时钟控制
是
状态序列发生器
否
EEM 版本
器
持
MSP430Xv2
有
有
3
否
否
S
设计套件与评估模块
MSP430FR2311 LaunchPad 开发套件
MSP-EXP430FR2311 LaunchPad 开发套件是适用于 MSP430FR2311 MCU 的易用型微控制器开发板。它
包含了在 MSP430FR2x FRAM 平台上快速开始开发所需要的全部资源，包括用于编程、调试和能量测量的
板载仿真。
MSP-FET + MSP-TS430PW20 FRAM 微控制器开发套件包
MSP-FET430U20 开发套件包将两种调试工具相结合，支持 MSP430FR23x 微控制器的 20 引脚 PW 封装
（例如 MSP430FR2311PW20）。两种工具分别为 MSP-TS430PW20 和 MSP-FET。
MSP-TS430PW20 - 适用于 MSP430FR2x MCU 的 20 引脚目标开发板
MSP-TS430PW20 是一款独立的 ZIF 插座目标板，用于通过 JTAG 接口或 Spy-Bi-Wire（两线制 JTAG）协
议对 MSP430 MCU 进行系统内编程和调试。该开发板支持所有采用 20 引脚或 16 引脚 TSSOP 封装（TI
封装代码：PW）的 MSP430FR23x 和 MSP430FR21x 闪存器件。
软件
MSP430Ware™ 软件
MSP430Ware 软件集合了所有 MSP430 器件的代码示例、数据表以及其他设计资源，打包提供给用户。除
了提供已有 MSP430 设计资源的完整集合外，MSP430Ware 软件还包含名为 MSP430 驱动程序库的高级
API。借助该库可以轻松地对 MSP430 硬件进行编程。MSP430Ware 软件以 CCS 组件或独立软件包两种形
式提供。
MSP430FR231x 代码示例
根据不同应用需求配置各集成外设的每个 MSP 器件均具备相应的 C 代码示例。
MSP 驱动程序库
MSP 驱动程序库的抽象 API 提供易用的函数调用，无需直接操纵 MSP430 硬件的位与字节。完整的文档通
过具有帮助意义的 API 指南交付，其中包括有关每个函数调用和经过验证的参数的详细信息。开发人员可以
使用驱动程序库功能，以最低开销编写完整项目。
MSP EnergyTrace™ 技术
适用于 MSP430 微控制器的 EnergyTrace 技术是基于电能的代码分析工具，适用于测量和显示应用的电能
系统配置并帮助优化应用以实现超低功耗。
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ULP（超低功耗）Advisor
ULP Advisor™软件是一款辅助工具，旨在指导开发人员编写更为高效的代码，从而充分利用 MSP430 和
MSP432 微控制器 独特 功能。ULP Advisor 的目标人群是微控制器的资深开发者和开发新手，可以根据详
尽的 ULP 检验表检查代码，以便最大限度地减少应用程序的能耗。在编译时，ULP Advisor 会提供通知和
备注以突出显示代码中可以进一步优化的区域，进而实现更低功耗。
适用于 MSP 超低功耗微控制器的 FRAM 嵌入式软件实用程序
FRAM 实用程序旨在作为不断扩充的嵌入式软件实用程序集合，其中的实用程序充分利用 FRAM 的超低功
耗和近乎无限次的写入寿命。这些实用程序适用于 MSP430FRxx FRAM 微控制器并提供示例代码协助应用
程序开发。其中的实用程序包含功耗计算实用程序 (CTPL)。CTPL 是一套实用程序 API 集，通过 CTPL 能
够轻松使用 LPMx.5 低功耗模式以及强大的关断模式，允许应用程序在检测到功率损耗时节约能耗并恢复关
键的系统元件。
IEC60730 软件包
IEC60730 MSP430 软件包经过专门开发，用于协助客户达到 IEC 60730-1:2010（家用及类似用途的自动化
电气控制 - 第 1 部分：一般要求）B 类产品的要求。其中涵盖家用电器、电弧检测器、电源转换器、电动工
具、电动自行车及其他诸多产品。IEC60730 MSP430 软件包可以嵌入在 MSP430 MCU 中 运行的客户应
用， 从而帮助客户简化其消费类器件在功能安全方面遵循 IEC 60730-1:2010 B 类规范的认证工作。
适用于 MSP 的定点数学库
MSP IQmath 和 Qmath 库是为 C 语言开发者提供的一套经过高度优化的高精度数学运算函数集合，能够将
浮点算法无缝嵌入 MSP430 和 MSP432 器件的定点代码中。这些例程通常用于计算密集型实时 应用， 而
优化的执行速度、高精度以及超低能耗通常是影响这些实时应用的关键因素。与使用浮点数学算法编写的同
等代码相比，使用 IQmath 和 Qmath 库可以大幅提高执行速度并显著降低能耗。
适用于 MSP430 的浮点数学库
TI 在低功耗和低成本微控制器领域锐意创新，为您提供 MSPMATHLIB。此标量函数的浮点数学库，能够充
分利用器件的智能外设，使速度最高达到标准 MSP430 数学函数的 26 倍。Mathlib 能够轻松集成到您的设
计中。该运算库免费使用并集成在 Code Composer Studio IDE 和 IAR Embedded Workbench IDE 中。
开发工具
适用于 MSP 微控制器的 Code Composer Studio™ 集成开发环境
Code Composer Studio (CCS) 集成开发环境 (IDE) 支持所有 MSP 微控制器器件。CCS 包含一整套用于开
发和调试嵌入式 应用的工具。它包含了优化的 C/C++ 编译器、源代码编辑器、项目构建环境、调试器、描
述器以及其他多种 功能。
命令行编程器
MSP Flasher 是一款基于 shell 的开源接口，可使用 JTAG 或 Spy-Bi-Wire (SBW) 通信通过 FET 编程器或
eZ430 对 MSP 微控制器进行编程。MSP Flasher 可用于将二进制文件（.txt 或 .hex 文件）直接下载到
MSP 微控制器，而无需使用 IDE。
MSP MCU 编程器和调试器
MSP-FET 是一款强大的仿真开发工具（通常称为调试探针），可帮助用户在 MSP 低功耗微控制器 (MCU)
中快速开发应用。创建 MCU 软件通常需要将生成的二进制程序下载到 MSP 器件中，从而进行验证和调
试。
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MSP-GANG 生产编程器
MSP Gang 编程器是一款 MSP430 或 MSP432 器件编程器，可同时对多达八个完全相同的 MSP430 或
MSP432 闪存或 FRAM 器件进行编程。MSP Gang 编程器可使用标准的 RS-232 或 USB 连接与主机 PC
相连并提供灵活的编程选项，允许用户完全自定义流程。
8.4 文档支持
以下文档介绍了 MSP430FR231x 微控制器。www.ti.com.cn 网站上提供了这些文档的副本。
接收文档更新通知
要接收文档更新通知（包括芯片勘误表），请转至 ti.com.cn 上您的器件对应的产品文件夹（请参见节 8.5
获取产品文件夹链接）。请单击右上角的“通知我”按钮。点击注册后，即可收到产品信息更改每周摘要（如
有）。有关更改的详细信息，请查阅已修订文档的修订历史记录。
勘误
《MSP430FR2311 器件勘误表》
说明了功能规格的已知例外情况。
《MSP430FR2310 器件勘误表》
说明了功能规格的已知例外情况。
用户指南
《MSP430FR4xx 和 MSP430FR2xx 系列用户指南》
可 说明 。
《MSP430 FRAM 器件引导加载程序 (BSL) 用户指南》
MSP430 MCU 上的引导加载程序 (BSL) 允许用户在原型设计、投产和维护等各阶段与 MSP430 MCU 中的
嵌入式存储器进行通信。可编程存储器（FRAM 存储器）和数据存储器 (RAM) 均可按要求予以修改。
《通过 JTAG 接口对 MSP430 进行编程》
此文档介绍了使用 JTAG 通信端口擦除、编程和验证基于 MSP430 闪存和 FRAM 的微控制器系列的存储器
模块所需的功能。此外，该文档还介绍了如何编程所有 MSP430 器件上均具备的 JTAG 访问安全保险丝。
此文档介绍了使用标准四线制 JTAG 接口和两线制 JTAG 接口（也称为 Spy-Bi-Wire (SBW)）的器件访问。
《MSP430 硬件工具用户指南》
此手册介绍了 TI MSP-FET430 闪存仿真工具 (FET) 的硬件。FET 是针对 MSP430 超低功耗微控制器的程
序开发工具。文中对提供的接口类型，即并行端口接口和 USB 接口进行了说明。
应用报告
《MSP430 32kHz 晶体振荡器》
选择合适的晶体、正确的负载电路和适当的电路板布局是实现稳定的晶体振荡器的关键。该应用报告总结了
晶体振荡器的功能，并介绍了用于选择合适晶体以实现 MSP430 MCU 超低功耗运行的参数。此外，还给出
了正确电路板布局的提示和示例。此外，为了确保振荡器在大规模生产后能够稳定运行，还可能需要进行一
些振荡器测试，该文档中提供了有关这些测试的详细信息。
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《MSP430 系统级 ESD 注意事项》
随着芯片技术向更低电压方向发展以及设计具有成本效益的超低功耗组件的需求的出现，系统级 ESD 要求
变得越来越苛刻。该应用报告介绍了不同的 ESD 主题，旨在帮助电路板设计人员和 OEM 理解并设计出稳
健耐用的系统级设计。另外还介绍了若干实际应用系统级 ESD 保护设计示例及其结果。
8.5 相关链接
表 8-2 列出了快速访问链接。类别包括技术文档、支持与社区资源、工具与软件，以及申请样片或购买产品
的快速链接。
表 8-2. 相关链接
器件
产品文件夹
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
MSP430FR2311
MSP430FR2310
8.6 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术
规范，并且不一定反映 TI 的观点；请参见 TI 的 《使用条款》。
TI E2E™ 社区
TI 的工程师交流 (E2E) 社区. 此社区的创建目的是为了促进工程师之间协作。在 e2e.ti.com 中，您可以提
问、共享知识、拓展思路，在同领域工程师的帮助下解决问题。
TI 嵌入式处理器维基网页
德州仪器 (TI) 嵌入式处理器维基网页。此网站的建立是为了帮助开发人员熟悉德州仪器 (TI) 的嵌入式处理
器，并且也为了促进与这些器件相关的硬件和软件的总体知识的创新和增长。
8.7 商标
LaunchPad, MSP430, MSP430Ware, Code Composer Studio, E2E, EnergyTrace, ULP Advisor, 适用于
MSP 微控制器的 Code Composer Studio are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.8 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
8.9 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
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9 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430FR2310IPW16
MSP430FR2310IPW16R
MSP430FR2310IPW20
MSP430FR2310IPW20R
MSP430FR2310IRGYR
MSP430FR2310IRGYT
MSP430FR2311IPW16
MSP430FR2311IPW16R
MSP430FR2311IPW20
MSP430FR2311IPW20R
MSP430FR2311IRGYR
MSP430FR2311IRGYT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
PW
PW
16
16
20
20
16
16
16
16
20
20
16
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
FR2310
2000 RoHS & Green
70 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
FR2310
FR2310
FR2310
FR2310
FR2310
FR2311
FR2311
FR2311
FR2311
FR2311
FR2311
PW
PW
2000 RoHS & Green
3000 RoHS & Green
RGY
RGY
PW
VQFN
250
90
RoHS & Green
RoHS & Green
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
PW
2000 RoHS & Green
70 RoHS & Green
PW
PW
2000 RoHS & Green
3000 RoHS & Green
RGY
RGY
VQFN
250
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430FR2310IPW16R TSSOP
MSP430FR2310IPW20R TSSOP
PW
PW
16
20
16
16
16
20
16
16
2000
2000
3000
250
330.0
330.0
330.0
180.0
330.0
330.0
330.0
180.0
12.4
16.4
12.4
12.4
12.4
16.4
12.4
12.4
6.9
6.95
3.8
5.6
7.1
4.3
4.3
5.6
7.1
4.3
4.3
1.6
1.6
1.5
1.5
1.6
1.6
1.5
1.5
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
16.0
12.0
12.0
12.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
MSP430FR2310IRGYR
MSP430FR2310IRGYT
VQFN
VQFN
RGY
RGY
PW
3.8
MSP430FR2311IPW16R TSSOP
MSP430FR2311IPW20R TSSOP
2000
2000
3000
250
6.9
PW
6.95
3.8
MSP430FR2311IRGYR
MSP430FR2311IRGYT
VQFN
VQFN
RGY
RGY
3.8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430FR2310IPW16R
MSP430FR2310IPW20R
MSP430FR2310IRGYR
MSP430FR2310IRGYT
MSP430FR2311IPW16R
MSP430FR2311IPW20R
MSP430FR2311IRGYR
MSP430FR2311IRGYT
TSSOP
TSSOP
VQFN
PW
PW
16
20
16
16
16
20
16
16
2000
2000
3000
250
350.0
350.0
367.0
210.0
350.0
350.0
367.0
210.0
350.0
350.0
367.0
185.0
350.0
350.0
367.0
185.0
43.0
43.0
35.0
35.0
43.0
43.0
35.0
35.0
RGY
RGY
PW
VQFN
TSSOP
TSSOP
VQFN
2000
2000
3000
250
PW
RGY
RGY
VQFN
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
MSP430FR2310IPW16
MSP430FR2310IPW20
MSP430FR2311IPW16
MSP430FR2311IPW20
PW
PW
PW
PW
TSSOP
TSSOP
TSSOP
TSSOP
16
20
16
20
90
70
90
70
530
530
530
530
10.2
10.2
10.2
10.2
3600
3600
3600
3600
3.5
3.5
3.5
3.5
Pack Materials-Page 3
PACKAGE OUTLINE
PW0020A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1
2X
5.85
6.6
6.4
NOTE 3
10
B
11
0.30
20X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220206/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.5)
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
11
10
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
20X (1.5)
SYMM
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
10
11
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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