MSP430FR2476_技术文档

MSP430FR2476, MSP430FR2475

ZHCSJG5C –MARCH 2019 –REVISED SEPTEMBER 2021

MSP430FR247x 混合信号微控制器

• 时钟系统(CS)

1 特性

– 片上32kHz RC 振荡器(REFO)，具有1µA 支持

– 带有锁频环(FLL) 的片上16MHz 数控振荡器

(DCO)

• 嵌入式微控制器

– 16 位RISC 架构

– 支持的时钟频率最高可达16MHz

– 1.8 V 至3.6 V 的宽电源电压范围（最低电源电

压受限于SVS 电平，请参阅SVS 规格）

• 优化的超低功耗模式

• 室温下的精度为±1%（具有片上基准）

– 片上超低频10kHz 振荡器(VLO)

– 片上高频调制振荡器(MODOSC)

– 外部32kHz 晶振(LFXT)

– 工作模式：135µA/MHz（典型值）

– 待机：采用32768Hz 晶振的LPM3.5 实时时钟

(RTC) 计数器：660nA（典型值）

– 关断(LPM4.5)：37nA，未使用SVS

• 低功耗铁电RAM (FRAM)

– 可编程MCLK 预分频器（1 至128）

– 通过可编程预分频器（1、2、4 或8）从MCLK

获得的SMCLK

• 通用输入/输出和引脚功能

– LQFP-48 封装上的43 个I/O

– 所有GPIO 上的43 个中断引脚可以将MCU 从

低功耗模式下唤醒

– 容量高达64KB 的非易失性存储器

– 内置错误修正码(ECC)

– 可配置的写保护

• 开发工具和软件

– 对程序、常量和存储的统一存储

– 耐写次数达10¹⁵次

– 抗辐射和非磁性

– 开发工具

• 目标开发板MSP‑TS430PT48A

• LaunchPad™ 开发套件LP‑MSP430FR2476

• 系列成员（另请参阅器件比较）

• 智能数字外设

– 四个16 位计时器，每个计时器有3 个捕捉/比较

寄存器(Timer_A3)

– 一个16 位计时器，具有7 个捕捉/比较寄存器

(Timer_B7)

– MSP430FR2476：64KB 程序FRAM、512B 信

息FRAM、8KB RAM

– MSP430FR2475：32KB 程序FRAM、512B 信

息FRAM、6KB RAM

– 一个仅用作计数器的16 位RTC

– 16 位循环冗余校验(CRC)

• 增强型串行通信，支持引脚重映射功能

– 两个eUSCI_A 接口，支持UART、IrDA 和SPI

– 两个eUSCI_B 接口，支持SPI 和I²C

• 高性能模拟

• 封装选项

– 48 引脚：LQFP (PT)

– 40 引脚：VQFN (RHA)

– 32 引脚：VQFN (RHB)

2 应用

– 高达12 通道12 位模数转换器(ADC)

• 小型工业传感器

• 低功耗医疗、健康和健身器材

• 电池组

• 内部共享基准（1.5、2.0 或2.5V）

• 采样与保持200ksps

– 一个增强型比较器(eCOMP)

• EPOS

• 电器

• 恒温器

• 电动牙刷

• 集成6 位DAC 作为基准电压

• 可编程迟滞

• 可配置的高功率和低功率模式

• PC 配件

3 说明

MSP430FR247x 微控制器 (MCU) 是 MSP430™ MCU 超值系列超低功耗低成本器件产品系列的一部分，该产品

系列用于检测和测量应用。MSP430FR247x MCU 集成了一个 12 位 SAR ADC 和一个比较器。所有

MSP430FR247x MCU 均支持 –40° 至 105°C 的工作温度范围，因此这些器件的 FRAM 数据记录功能对更高温

度的工业应用来说意义重大。

MSP430FR247x MCU 由一系列由软、硬件组成的生态系统提供支持，并提供有参考设计和代码示例，可帮助您

快速开展设计。开发套件包括 MSP-TS430PT48 48 引脚目标开发板。TI 还提供免费的 MSP430Ware™ 软件，该

软件以 Code Composer Studio™ IDE 桌面和云版本组件的形式提供（位于 TI Resource Explorer 中）。我们为

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLASEO7

MSP430FR2476, MSP430FR2475

ZHCSJG5C –MARCH 2019 –REVISED SEPTEMBER 2021

www.ti.com.cn

MSP430 MCU 提供广泛的在线配套资料（例如内务处理型示例系列、MSP Academy 培训），也通过 TI E2E^™

支持论坛提供在线支持。

MSP430 超低功耗(ULP) FRAM 微控制器平台将独特的嵌入式 FRAM 和整体超低功耗系统架构相结合，从而使系

统设计人员能够在降低能耗的情况下提升性能。FRAM 技术将 RAM 的低功耗快速写入、灵活性和耐用性与闪存

的非易失性相结合。

TI MSP430 系列低功耗微控制器包含多种器件，其中配备了不同的外设集以满足各类应用的需求。此架构与多种

低功耗模式配合使用，是延长便携式测量应用电池寿命的最优选择。该MCU 具有一个强大的 16 位RISC CPU、

16 位寄存器和常数发生器，有助于获得最大编码效率。数控振荡器 (DCO) 可使 MCU 在不到 10μs（典型值）的

时间内从低功耗模式唤醒至活动模式。

有关完整的模块说明，请参阅MSP430FR4xx 和MSP430FR2xx 系列器件用户指南。

器件信息

器件型号⁽¹⁾

MSP430FR2476TPT

MSP430FR2475TPT

MSP430FR2476TRHA

MSP430FR2475TRHA

MSP430FR2476TRHB

MSP430FR2475TRHB

封装尺寸⁽²⁾

7mm × 7mm

6mm × 6mm

5mm x 5mm

封装

LQFP (48)

VQFN (40)

VQFN (32)

(1) 要获得最新的产品、封装和订购信息，请参阅节12 中的封装选项附录，或者访问德州仪器(TI) 网站

www.ti.com.cn。

(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参阅机械数据（节12 中）。

CAUTION

系统级静电放电 (ESD) 保护必须符合器件级 ESD 规范，以防发生电气过载或对数据或代码存储器造

成干扰。如需更多信息，请参阅MSP430 系统级ESD 注意事项。

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4 功能模块图

图4-1 给出了功能方框图。

图4-1. 功能模块图

• MCU 的主电源对DVCC 和DVSS 分别为数字模块和模拟模块供电。推荐的旁路电容和去耦电容分别为

4.7μF 至10μF 和0.1μF，精度为±5%。

• 所有GPIO 均具备引脚中断功能，可将MCU 从所有LPM 模式唤醒。

• 在LPM3.5 模式下，RTC 模块可在其他外设停止工作的情况下继续工作。

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Table of Contents

9 Detailed Description......................................................45

9.1 Overview...................................................................45

9.2 CPU.......................................................................... 45

9.3 Operating Modes...................................................... 45

9.4 Interrupt Vector Addresses....................................... 47

9.5 Bootloader (BSL)...................................................... 48

9.6 JTAG Standard Interface.......................................... 49

9.7 Spy-Bi-Wire Interface (SBW).................................... 49

9.8 FRAM........................................................................50

9.9 Memory Protection....................................................50

9.10 Peripherals..............................................................50

9.11 Input/Output Diagrams............................................65

9.12 Device Descriptors..................................................72

9.13 Memory...................................................................74

9.14 Identification............................................................83

10 Applications, Implementation, and Layout............... 84

10.1 Device Connection and Layout Fundamentals....... 84

10.2 Peripheral- and Interface-Specific Design

Information.................................................................. 87

11 Device and Documentation Support..........................89

11.1 Getting Started and Next Steps.............................. 89

11.2 Device Nomenclature..............................................89

11.3 Tools and Software..................................................90

11.4 Documentation Support.......................................... 92

11.5 支持资源..................................................................93

11.6 Trademarks............................................................. 93

11.7 Electrostatic Discharge Caution..............................93

11.8 Export Control Notice..............................................94

11.9 术语表..................................................................... 94

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 功能模块图.........................................................................3

5 Revision History.............................................................. 5

6 Device Comparison.........................................................7

6.1 Related Products........................................................ 8

7 Terminal Configuration and Functions..........................9

7.1 Pin Diagrams.............................................................. 9

7.2 Pin Attributes.............................................................12

7.3 Signal Descriptions................................................... 16

7.4 Pin Multiplexing.........................................................20

7.5 Buffer Types..............................................................20

7.6 Connection of Unused Pins...................................... 20

8 Specifications................................................................ 21

8.1 Absolute Maximum Ratings...................................... 21

8.2 ESD Ratings............................................................. 21

8.3 Recommended Operating Conditions.......................21

8.4 Active Mode Supply Current Into V_CCExcluding

External Current.......................................................... 22

8.5 Active Mode Supply Current Per MHz...................... 22

8.6 Low-Power Mode LPM0 Supply Currents Into

V_CCExcluding External Current.................................. 22

8.7 Low-Power Mode (LPM3, LPM4) Supply

Currents (Into V_CC) Excluding External Current.......... 23

8.8 Low-Power Mode LPMx.5 Supply Currents (Into

V_CC) Excluding External Current................................. 24

8.9 Typical Characteristics –Low-Power Mode

Supply Currents...........................................................25

8.10 Current Consumption Per Module.......................... 25

8.11 Thermal Resistance Characteristics....................... 26

8.12 Timing and Switching Characteristics..................... 26

Information.................................................................... 95

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5 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from revision B to revision C

Changes from December 11, 2019 to September 14, 2021

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• 通篇更正了MSP430FR2475 的RAM 大小（从4KB 更改为6KB）.................................................................. 1

• 在节3 说明中添加了指向在线配套资料的链接.................................................................................................. 1

• Corrected the pin numbers for the Veref+ and Veref- signals in 表7-2, Signal Descriptions .......................... 16

• Corrected the TAxRMP, USCIA0RMP, USCIB0RMP, and USCIB1RMP bit names in the notes for 表7-2,

Signal Descriptions ..........................................................................................................................................16

• Corrected the USCIA0RMP and USCIBxRMP bit names in 节9.10.7, Enhanced Universal Serial

Communication Interface (eUSCI_A0, eUSCI_B0) ......................................................................................... 55

• Corrected the TAxRMP bit name in the notes for 表9-16, TA2 and TA3 Pin Configurations of Remap

Functionality .....................................................................................................................................................56

• Added an inverter to the Schmitt-trigger enable in 图9-4, Port Input/Output With Schmitt Trigger .................65

• Corrected the value of the P5SEL.x column for P5.3 and P5.4 in 表9-27, Port P5 (P5.0 to P5.7) Pin

Functions ......................................................................................................................................................... 70

• Added the SYSCFG3 register to 表9-35, SYS Registers (Base Address: 0140h) ..........................................75

Changes from revision A to revision B

Changes from April 26, 2019 to December 10, 2019

Page

• 更新了节1 特性................................................................................................................................................ 1

• Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in 节

8.3, Recommended Operating Conditions .......................................................................................................21

• Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in 节

8.3, Recommended Operating Conditions .......................................................................................................21

• Changed the note that begins "A capacitor tolerance of ±20% or better is required..." in 节8.3,

Recommended Operating Conditions ..............................................................................................................21

• Added the note "See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing" to

节8.12.3.1, XT1 Crystal Oscillator (Low Frequency) ...................................................................................... 28

• Changed the note that begins "Requires external capacitors at both terminals..." in 节8.12.3.1, XT1 Crystal

Oscillator (Low Frequency) ..............................................................................................................................28

• Added the t_TA,capparameter in 节8.12.6.1, Timer_A .......................................................................................35

• Added the t_TB,capparameter in 节8.12.6.2, Timer_B .......................................................................................35

• Corrected the test conditions for the R_Iparameter in 节8.12.8.1, ADC, Power Supply and Input Range

Conditions ........................................................................................................................................................41

• Removed ADCDIV from the equations for t_CONVERTbecause ADCCLK is after division in 节8.12.8.2, ADC,

Timing Parameters .......................................................................................................................................... 41

• Added the note that begins "t_Sample= ln(2ⁿ⁺¹) × τ..." in 节8.12.8.2, ADC, Timing Parameters .................... 41

• Changed CRC covered end address to 0x1AF7 in table note (1) in 表9-30 , Device Descriptors ..................72

Changes from initial release to revision A

Changes from March 12, 2019 to April 25, 2019

Page

• 将文档状态更改为“量产数据”......................................................................................................................... 1

• 在图4-1、功能方框图中添加了MSP430FR2673 和MSP430FR2672 的存储器大小.......................................3

• Updated 节8.7 Low-Power Mode (LPM3, LPM4) Supply Currents (Into V_CC) Excluding External Current with

production values .............................................................................................................................................23

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• Updated 节8.12.3.2 DCO FLL, Frequency with production values..................................................................29

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6.1 Related Products

For information about other devices in this family of products or related products, see the following links.

Products for microcontrollers

Our diverse portfolio of 16- and 32-bit microcontrollers (MCUs) with real-time control capabilities and high-

precision analog integration are optimized for industrial and automotive applications. Backed by decades of

expertise and innovative hardware and software solutions, our MCUs can meet the needs of any design and

budget.

Products for MSP430 microcontrollers

Our 16-bit MSP430™ microcontrollers (MCUs) provide affordable solutions for all applications. Our leadership in

integrated precision analog enables designers to enhance system performance and lower system costs.

Designers can find a cost-effective MCU within the broad MSP430 portfolio of over 2000 devices for virtually any

need. Get started quickly and reduce time to market with our simplified tools, software, and best-in-class

support.

Reference designs for MSP430FR2476

Find reference designs leveraging the best in TI technology – from analog and power management to

embedded processors

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7 Terminal Configuration and Functions

7.1 Pin Diagrams

图7-1 shows the pinout of the 48-pin PT package.

DVCC

RST/NMI/SBWTDIO

1

36

35

34

33

32

31

30

29

28

27

26

25

P2.7/UCB1STE

P4.2/TA3CLK

2

TEST/SBWTCK

3

P4.1/TA3.0

P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+

P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5

P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6

P1.7/UCA0STE/SMCLK/TDO/A7

P4.3/UCB1SOMI/UCB1SCL/TB0.5/A8

P4.4/UCB1SIMO/UCB1SDA/TB0.6/A9

P5.3/UCB1CLK/TA3.0/A10

4

P4.0/TA3.1

5

P3.7/TA3.2

6

DNC

MSP430FR2476TPT

MSP430FR2475TPT

7

P2.6/UCA1TXD/UCA1SIMO

P2.5/UCA1RXD/UCA1SOMI

P2.4/UCA1CLK

P3.1/UCA1STE

P3.4/TA2CLK/COMP0OUT

P2.3/TA2.0

8

9

10

11

12

P5.4/UCB1STE/TA3CLK/A11

P1.0/UCB0STE/TA0CLK/A0/Veref+

图7-1. 48-Pin PT Package (Top View)

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图7-2 shows the pinout of the 40-pin RHA package.

1

2

DVCC

RST/NMI/SBWTDIO

TEST/SBWTCK

30

29

28

27

26

25

24

23

22

21

P2.7/UCB1STE

P4.2/TA3CLK

3

P4.1/TA3.0

4

P4.0/TA3.1

P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+

P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5

P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6

P1.7/UCA0STE/SMCLK/TDO/A7

5

P3.7/TA3.2

MSP430FR2476TRHA

MSP430FR2475TRHA

6

DNC

7

P2.6/UCA1TXD/UCA1SIMO

P2.5/UCA1RXD/UCA1SOMI

P2.4/UCA1CLK

P3.1/UCA1STE

8

P4.3/UCB1SOMI/UCB1SCL/TB0.5/A8

P4.4/UCB1SIMO/UCB1SDA/TB0.6/A9

P1.0/UCB0STE/TA0CLK/A0/Veref+

9

10

图7-2. 40-Pin RHA Package (Top View)

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图7-3 shows the pinout of the 32-pin RHB package.

26 25

32 31 30 29 28 27

24

RST/NMI/SBWTDIO

TEST/SBWTCK

1

2

3

4

5

6

7

8

P4.2/TA3CLK

23

22

21

20

19

18

17

P4.1/TA3.0

P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+

P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5

P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6

P1.7/UCA0STE/SMCLK/TDO/A7

P4.0/TA3.1

P3.7/TA3.2

MSP430FR2476TRHB

MSP430FR2475TRHB

DNC

P2.6/UCA1TXD/UCA1SIMO

P2.5/UCA1RXD/UCA1SOMI

P2.4/UCA1CLK

P1.0/UCB0STE/TA0CLK/A0/Veref+

P1.1/UCB0CLK/TA0.1/COMP0.0/A1

9 10 11 12 13 14 15 16

图7-3. 32-Pin RHB Package (Top View)

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7.2 Pin Attributes

表7-1 lists the attributes of all pins.

表7-1. Pin Attributes

PIN NUMBER

SIGNAL

BUFFER

TYPE⁽⁴⁾

POWER

RESET STATE

AFTER BOR⁽⁶⁾

SIGNAL NAME^{(1) (2)}

TYPE⁽³⁾

SOURCE⁽⁵⁾

PT

RHA

RHB

1

32

DVCC

P

I

Power

DVCC

N/A

PU

RST (RD)

NMI

LVCMOS

Analog

2

3

2

3

1

2

I

–

SBWTDIO

TEST (RD)

SBWTCK

P1.4 (RD)

UCA0TXD

UCA0SIMO

TA1.2

I/O

I

PD

I

–

I/O

O

I/O

I

OFF

–

4

3

–

TCK

–

A4

I

–

VREF+

P1.5 (RD)

UCA0RXD

UCA0SOMI

TA1.1

O

I/O

I

Power

–

LVCMOS

Analog

OFF

–

I/O

I

5

4

–

TMS

–

A5

I

–

P1.6 (RD)

UCA0CLK

TA1CLK

TDI

I/O

I

LVCMOS

Analog

OFF

–

6

5

I

–

TCLK

I

–

A6

I

–

P1.7 (RD)

UCA0STE

SMCLK

TDO

I/O

O

I

LVCMOS

Analog

OFF

–

7

8

9

7

8

9

6

–

A7

–

P4.3 (RD)

UCB1SOMI

UCB1SCL

TB0.5

I/O

I

LVCMOS

Analog

OFF

–

A8

–

P4.4 (RD)

UCB1SIMO

UCB1SDA

TB0.6

I/O

I

LVCMOS

Analog

OFF

–

A9

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表7-1. Pin Attributes (continued)

PIN NUMBER

SIGNAL

TYPE⁽³⁾

BUFFER

TYPE⁽⁴⁾

POWER

RESET STATE

AFTER BOR⁽⁶⁾

SIGNAL NAME^{(1) (2)}

SOURCE⁽⁵⁾

PT

RHA

RHB

P5.3 (RD)

I/O

I

LVCMOS

Analog

DVCC

OFF

UCB1CLK

TA3.0

–

10

–

A10

–

P5.4 (RD)

UCB1STE

TA3CLK

A11

I/O

I

LVCMOS

Analog

OFF

–

11

12

–

P1.0 (RD)

UCB0STE

TA0CLK

A0

I/O

I

LVCMOS

Analog

OFF

–

10

7

I

–

Veref+

I

Power

–

P1.1 (RD)

UCB0CLK

TA0.1

I/O

I

LVCMOS

Analog

OFF

–

13

14

15

11

12

13

8

9

A1

–

COMP0.0

P1.2 (RD)

UCB0SIMO

UCB0SDA

TA0.2

I

Analog

–

I/O

I

LVCMOS

Analog

OFF

–

A2

–

Veref-

I

Power

–

P1.3 (RD)

UCB0SOMI

UCB0SCL

MCLK

I/O

O

LVCMOS

Analog

OFF

–

10

–

A3

I

–

P2.2 (RD)

ACLK

I/O

O

LVCMOS

Analog

OFF

16

17

14

15

11

–

COMP0.1

P4.5 (RD)

UCB0SOMI

UCB0SCL

TA3.2

I

I/O

LVCMOS

OFF

–

P4.6 (RD)

UCB0SIMO

UCB0SDA

TA3.1

OFF

–

18

19

16

–

P5.5 (RD)

UCB0CLK

TA2CLK

OFF

–

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表7-1. Pin Attributes (continued)

PIN NUMBER

RHA

SIGNAL

TYPE⁽³⁾

BUFFER

TYPE⁽⁴⁾

POWER

RESET STATE

AFTER BOR⁽⁶⁾

SIGNAL NAME^{(1) (2)}

SOURCE⁽⁵⁾

PT

RHB

P5.6 (RD)

I/O

I

LVCMOS

Analog

DVCC

OFF

20

UCB0STE

TA2.0

–

P5.7 (RD)

TA2.1

OFF

21

22

–

COMP0.2

P6.0 (RD)

TA2.2

I/O

I

LVCMOS

Analog

OFF

–

COMP0.3

P3.0 (RD)

TA2.2

I/O

O

LVCMOS

OFF

23

24

25

17

18

19

12

13

14

–

P3.3 (RD)

TA2.1

OFF

–

P2.3 (RD)

TA2.0

OFF

–

P3.4 (RD)

TA2CLK

COMP0OUT

P3.1 (RD)

UCA1STE

P2.4 (RD)

UCA1CLK

P2.5 (RD)

UCA1RXD

UCA1SOMI

P2.6 (RD)

UCA1TXD

UCA1SIMO

DNC⁽⁷⁾

OFF

26

20

15

–

I/O

I

OFF

27

28

21

22

16

17

–

OFF

–

OFF

29

30

23

24

18

19

–

I/O

O

OFF

–

I/O

31

32

25

26

20

21

–

I/O

I

–

P3.7 (RD)

TA3.2

LVCMOS

DVCC

OFF

–

P4.0 (RD)

TA3.1

OFF

33

34

35

36

27

28

29

30

22

23

24

25

–

P4.1 (RD)

TA3.0

OFF

–

P4.2 (RD)

TA3CLK

P2.7 (RD)

UCB1STE

P3.5 (RD)

UCB1CLK

TB0TRG

OFF

–

OFF

–

OFF

37

31

26

–

14

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表7-1. Pin Attributes (continued)

PIN NUMBER

SIGNAL

TYPE⁽³⁾

BUFFER

TYPE⁽⁴⁾

POWER

RESET STATE

AFTER BOR⁽⁶⁾

SIGNAL NAME^{(1) (2)}

SOURCE⁽⁵⁾

PT

RHA

RHB

P3.2 (RD)

I/O

I

LVCMOS

Power

DVCC

OFF

38

32

27

UCB1SIMO

UCB1SDA

P3.6(RD)

UCB1SOMI

UCB1SCL

P6.1 (RD)

TB0CLK

P6.2 (RD)

TB0.0

–

OFF

39

33

28

–

OFF

40

41

–

OFF

–

P4.7 (RD)

UCA0STE

TB0.1

OFF

42

43

34

35

–

P5.0 (RD)

UCA0CLK

TB0.2

OFF

–

P5.1 (RD)

UCA0RXD

UCA0SOMI

TB0.3

I/O

I

OFF

–

44

36

–

I/O

O

–

P5.2 (RD)

UCA0TXD

UCA0SIMO

TB0.4

OFF

–

45

46

37

38

–

I/O

O

–

P2.0 (RD)

XOUT

OFF

29

–

P2.1 (RD)

XIN

I/O

I

OFF

47

48

39

40

30

31

–

DVSS

P

N/A

(1) Signals names with (RD) denote the reset default pin name.

(2) To determine the pin mux encodings for each pin, see 节9.11.

(3) Signal types: I = input, O = output, I/O = input or output

(4) Buffer types: LVCMOS, Analog, or Power (see 表7-3)

(5) The power source shown in this table is the I/O power source, which may differ from the module power source.

(6) Reset States:

OFF = High impedance with Schmitt trigger and pullup or pulldown (if available) disabled

PU = Pullup is enabled

PD = Pulldown is enabled

N/A = Not applicable

(7) DNC = do not connect

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7.3 Signal Descriptions

表7-2 describes the signals for all device variants and package options.

表7-2. Signal Descriptions

PIN NUMBER

PT RHA RHB

FUNCTION

SIGNAL NAME

A0

DESCRIPTION

TYPE⁽¹⁾

12

13

14

15

4

10

11

12

13

4

7

8

I

Analog input A0

Analog input A1

Analog input A2

Analog input A3

Analog input A4

Analog input A5

Analog input A6

Analog input A7

Analog input A8

Analog input A9

Analog input A10

Analog input A11

ADC positive reference

ADC negative reference

A1

I

A2

9

I

A3

10

3

I

A4

I

A5

5

4

I

A6

6

5

I

ADC

A7

7

6

I

A8

8

I

–

7

A9

9

I

A10

10

11

12

14

13

16

21

22

26

16

15

7

I

–

10

12

11

14

A11

Veref+

Veref-

COMP0.0

COMP0.1

COMP0.2

COMP0.3

COMP0OUT

ACLK

MCLK

SMCLK

XIN

I

9

I

8

I

Enhanced comparator input channel C0

Enhanced comparator input channel C1

Enhanced comparator input channel C2

Enhanced comparator input channel C3

Enhanced comparator output channel COUT

ACLK output

11

I

eCOMP0

I

–

20

14

13

7

–

15

11

10

6

I

O

I/O

O

I

MCLK output

Clock

SMCLK output

47

46

3

39

38

3

30

29

2

Input terminal for crystal oscillator

Output terminal for crystal oscillator

Spy-Bi-Wire input clock

XOUT

SBWTCK

SBWTDIO

TCK

O

I

2

1

I/O

I

Spy-Bi-Wire data input/output

Test clock

4

3

TCLK

TDI

6

5

I

Test clock input

Debug

6

5

I

Test data input

TDO

7

6

O

I

Test data output

TEST

TMS

3

5

2

4

Test Mode pin –selected digital I/O on JTAG pins

Test mode select

5

I

P1.0

12

13

14

15

4

10

11

12

13

4

7

I/O

General-purpose I/O with port interrupt and wake from LPMx.5

General-purpose I/O with port interrupt and wake from LPMx.5 ⁽²⁾

General-purpose I/O with port interrupt and wake from LPMx.5⁽²⁾

P1.1

8

P1.2

9

P1.3

10

3

GPIO, Port 1

P1.4

P1.5

5

4

P1.6

6

5

P1.7

7

6

16

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FUNCTION

表7-2. Signal Descriptions (continued)

PIN NUMBER

SIGNAL NAME

P2.0

DESCRIPTION

TYPE⁽¹⁾

PT RHA RHB

46

47

16

25

28

29

30

36

23

27

38

24

26

37

39

32

33

34

35

8

38

39

14

19

22

23

24

30

17

21

32

18

20

31

33

26

27

28

29

8

29

30

11

14

17

18

19

25

12

16

27

13

15

26

28

21

22

23

24

I/O

General-purpose I/O with port interrupt and wake from LPMx.5

eUSCI_B0 I²C clock

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

P4.0

P4.1

P4.2

P4.3

P4.4

P4.5

P4.6

P4.7

P5.0

P5.1

P5.2

P5.3

P5.4

P5.5

P5.6

P5.7

P6.0

P6.1

P6.2

UCB0SCL⁽³⁾

UCB0SDA⁽³⁾

GPIO, Port 2

GPIO, Port 3

GPIO, Port 4

–

10

9

17

18

42

43

44

45

10

11

19

20

21

22

40

41

15

14

15

16

34

35

36

37

–

13

12

GPIO, Port 5

GPIO, Port 6

eUSCI_B0 I²C data

UCB0SCL⁽⁴⁾

UCB0SDA⁽⁴⁾

17

18

15

16

I/O

eUSCI_B0 I²C clock

eUSCI_B0 I²C data

–

I²C

UCB1SCL⁽³⁾

UCB1SDA⁽³⁾

39

38

33

32

28

27

I/O

eUSCI_B1 I²C clock

eUSCI_B1 I²C data

UCB1SCL⁽⁴⁾

UCB1SDA⁽⁴⁾

8

9

8

9

I/O

eUSCI_B1 I²C clock

eUSCI_B1 I²C data

–

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表7-2. Signal Descriptions (continued)

PIN NUMBER

FUNCTION

SIGNAL NAME

DVCC

DESCRIPTION

TYPE⁽¹⁾

PT RHA RHB

1

48

4

1

40

4

32

31

3

P

Power supply

Power ground

Power

DVSS

VREF+

P

Output of positive reference voltage with ground as reference

eUSCI_A0 SPI slave transmit enable

eUSCI_A0 SPI clock input/output

UCA0STE⁽³⁾

UCA0CLK⁽³⁾

UCA0SOMI⁽³⁾

UCA0SIMO⁽³⁾

7

6

I/O

6

5

4

eUSCI_A0 SPI slave out/master in

4

3

eUSCI_A0 SPI slave in/master out

UCA0STE⁽⁴⁾

UCA0CLK⁽⁴⁾

UCA0SOMI⁽⁴⁾

UCA0SIMO⁽⁴⁾

42

43

44

45

34

35

36

37

I/O

eUSCI_A0 SPI slave transmit enable

eUSCI_A0 SPI clock input/output

eUSCI_A0 SPI slave out/master in

eUSCI_A0 SPI slave in/master out

–

UCA1STE

UCA1CLK

UCA1SOMI

UCA1SIMO

27

28

29

30

21

22

23

24

16

17

18

19

I/O

eUSCI_A1 SPI slave transmit enable

eUSCI_A1 SPI clock input/output

eUSCI_A1 SPI slave out/master in

eUSCI_A1 SPI slave in/master out

UCB0STE⁽³⁾

UCB0CLK⁽³⁾

UCB0SOMI⁽³⁾

UCB0SIMO⁽³⁾

12

13

15

14

10

11

13

12

7

8

I/O

eUSCI_B0 slave transmit enable

eUSCI_B0 clock input/output

SPI

10

9

eUSCI_B0 SPI slave out/master in

eUSCI_B0 SPI slave in/master out

UCB0STE⁽⁴⁾

UCB0CLK⁽⁴⁾

UCB0SOMI⁽⁴⁾

UCB0SIMO⁽⁴⁾

20

19

17

18

I/O

eUSCI_B0 slave transmit enable

eUSCI_B0 clock input/output

–

eUSCI_B0 SPI slave out/master in

eUSCI_B0 SPI slave in/master out

UCB1STE⁽³⁾

UCB1CLK⁽³⁾

UCB1SOMI⁽³⁾

UCB1SIMO⁽³⁾

36

37

39

38

30

31

33

32

25

26

28

27

I/O

eUSCI_B1 slave transmit enable

eUSCI_B1 clock input/output

eUSCI_B1 SPI slave out/master in

eUSCI_B1 SPI slave in/master out

UCB1STE⁽⁴⁾

UCB1CLK⁽⁴⁾

UCB1SOMI⁽⁴⁾

UCB1SIMO⁽⁴⁾

NMI

11

10

8

I/O

I

eUSCI_B1 slave transmit enable

eUSCI_B1 clock input/output

eUSCI_B1 SPI slave out/master in

eUSCI_B1 SPI slave in/master out

Nonmaskable interrupt input

Active-low reset input

–

2

–

1

9

2

System

RST

2

1

I

18

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FUNCTION

表7-2. Signal Descriptions (continued)

PIN NUMBER

SIGNAL NAME

TA0.1

DESCRIPTION

TYPE⁽¹⁾

PT RHA RHB

13

14

12

11

12

10

8

9

7

I/O

I

Timer TA0 CCR1 capture: CCI1A input, compare: Out1 outputs

Timer TA0 CCR2 capture: CCI2A input, compare: Out2 outputs

Timer clock input TACLK for TA0

TA0.2

TA0CLK

TA1.1

5

4

6

5

4

6

4

3

5

I/O

I

Timer TA1 CCR1 capture: CCI1A input, compare: Out1 outputs

Timer TA1 CCR2 capture: CCI2A input, compare: Out2 outputs

Timer clock input TACLK for TA1

TA1.2

TA1CLK

TA2.0⁽⁵⁾

TA2.1⁽⁵⁾

TA2.2⁽⁵⁾

TA2CLK⁽⁵⁾

25

24

23

26

19

18

17

20

14

13

12

15

I/O

I

Timer TA2 CCR0 capture: CCI0A input, compare: Out0 outputs

Timer TA2 CCR1 capture: CCI1A input, compare: Out1 outputs

Timer TA2 CCR2 capture: CCI2A input, compare: Out2 outputs

Timer clock input TACLK for TA2

TA2.0⁽⁶⁾

TA2.1⁽⁶⁾

TA2.2⁽⁶⁾

TA2CLK⁽⁶⁾

20

21

22

19

I/O

I

Timer TA2 CCR0 capture: CCI0A input, compare: Out0 outputs

Timer TA2 CCR1 capture: CCI1A input, compare: Out1 outputs

Timer TA2 CCR2 capture: CCI2A input, compare: Out2 outputs

Timer clock input TACLK for TA2

–

Timer_A

TA3.0⁽⁵⁾

TA3.1⁽⁵⁾

TA3.2⁽⁵⁾

TA3CLK⁽⁵⁾

34

33

32

35

28

27

26

29

23

22

21

24

I/O

I

Timer TA3 CCR0 capture: CCI0A input, compare: Out0 outputs

Timer TA3 CCR1 capture: CCI1A input, compare: Out1 outputs

Timer TA3 CCR2 capture: CCI2A input, compare: Out2 outputs

Timer clock input TACLK for TA3

TA3.0⁽⁶⁾

TA3.1⁽⁶⁾

TA3.2⁽⁶⁾

TA3CLK⁽⁶⁾

TB0.0

10

18

17

11

41

42

43

44

45

8

I/O

I

Timer TA3 CCR0 capture: CCI0A input, compare: Out0 outputs

Timer TA3 CCR1 capture: CCI1A input, compare: Out1 outputs

Timer TA3 CCR2 capture: CCI2A input, compare: Out2 outputs

Timer clock input TACLK for TA3

–

16

15

–

26

4

–

34

35

36

37

8

I/O

I

Timer TB0 CCR0 capture: CCI0A input, compare: Out0 outputs

Timer TB0 CCR1 capture: CCI1A input, compare: Out1 outputs

Timer TB0 CCR2 capture: CCI2A input, compare: Out2 outputs

Timer TB0 CCR3 capture: CCI3A input, compare: Out3 outputs

Timer TB0 CCR4 capture: CCI4A input, compare: Out4 outputs

Timer TB0 CCR5 capture: CCI5A input, compare: Out5 outputs

Timer TB0 CCR6 capture: CCI6A input, compare: Out6 outputs

Timer clock input TBCLK for TB0

TB0.1

TB0.2

TB0.3

Timer_B

TB0.4

TB0.5

TB0.6

9

TB0CLK

TB0TRG

UCA0RXD

UCA0TXD

40

37

5

–

31

5

Timer TB0 external trigger input for TB0OUTH

I

eUSCI_A0 UART receive data

4

3

O

eUSCI_A0 UART transmit data

UCA0RXD⁽³⁾

UCA0TXD⁽³⁾

44

45

36

37

I

eUSCI_A0 UART receive data

eUSCI_A0 UART transmit data

–

UART

O

UCA1RXD⁽⁴⁾

UCA1TXD⁽⁴⁾

Do not connect

29

30

31

23

24

25

18

19

20

I

eUSCI_A1 UART receive data

eUSCI_A1 UART transmit data

Do not connect

O

–

DNC

VQFN package exposed thermal pad. TI recommends connecting

to V_SS

VQFN pad

VQFN thermal pad

PAD

–

(1) Pin Types: I = Input, O = Output, I/O = Input or Output, P = Power

(2) Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to

prevent collisions.

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(3) This is the default functionality that can be remapped by the USCIBxRMP or USCIA0RMP bit of the SYSCFG2 or SYCFG3 register.

Only one selected port is valid at any time.

(4) This is the remapped functionality controlled by the USCIBxRMP or USCIA0RMP bit of the SYSCFG2 or SYCFG3 register. Only one

selected port is valid at any time.

(5) This is the default functionality that can be remapped by the TAxRMP bit of the SYSCFG3 register. Only one selected port is valid at

any time.

(6) This is the remapped functionality controlled by the TAxRMP bit of the SYSCFG3 register. Only one selected port is valid at any time.

7.4 Pin Multiplexing

Pin multiplexing for this MCU is controlled by both register settings and operating modes (for example, if the

MCU is in test mode). For details of the settings for each pin and diagrams of the multiplexed ports, see 节9.11.

7.5 Buffer Types

表7-3 defines the pin buffer types that are listed in 表7-1

表7-3. Buffer Types

NOMINAL

OUTPUT DRIVE

STRENGTH

(mA)

BUFFER TYPE

(STANDARD)

NOMINAL

VOLTAGE

PU OR PD

STRENGTH

(µA)

OTHER

CHARACTERISTICS

HYSTERESIS

PU OR PD

LVCMOS

Analog

3.0 V

Y⁽¹⁾

N

Programmable

N/A

See 节8.12.4

See analog modules in 节8

for details.

N/A

SVS enables hysteresis on

DVCC.

Power (DVCC)

Power (AVCC)

3.0 V

N

N/A

(1) Only for input pins.

7.6 Connection of Unused Pins

表7-4 lists the correct termination of unused pins.

表7-4. Connection of Unused Pins

PIN⁽¹⁾

POTENTIAL

Open

COMMENT

Switched to port function, output direction (PxDIR.n = 1)

Px.0 to Px.7

RST/NMI

TEST

47-kΩ pullup or internal pullup selected with 10-nF (or 1.1-nF) pulldown⁽²⁾

DV_CC

Open

This pin always has an internal pulldown enabled.

(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection

guidelines.

(2) The pulldown capacitor should not exceed 1.1 nF when using MCUs with Spy-Bi-Wire interface in Spy-Bi-Wire mode with TI tools like

FET interfaces or GANG programmers.

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8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

Voltage applied at DVCC pin to V_SS

Voltage applied to any other pin⁽²⁾

4.1

V

–0.3

V_CC+ 0.3

(4.1 V Max)

V

–0.3

Diode current at any device pin

Junction temperature, T_J

±2

115

125

mA

°C

(3)

Storage temperature, T_stg

°C

–40

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS

.

(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

8.2 ESD Ratings

VALUE

±1000

±250

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS‑001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22‑C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±1000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as

±250 V may actually have higher performance.

8.3 Recommended Operating Conditions

MIN

NOM

MAX UNIT

V_CC

V_SS

T_A

Supply voltage applied at DVCC pin^{(1) (3) (2)}

Supply voltage applied at DVSS pin

Operating free-air temperature

1.8⁽⁴⁾

3.6

V

0

105

115

°C

µF

–40

4.7

0

T_J

Operating junction temperature

C_DVCC

Recommended capacitor at DVCC⁽⁵⁾

10

No FRAM wait states (NWAITSx = 0)

With FRAM wait states (NWAITSx = 1)⁽⁷⁾

8

16⁽⁸⁾

40

Processor frequency

f_SYSTEM

MHz

(MCLK frequency)^{(4) (6)}

0

f_ACLK

ACLK frequency

kHz

f_SMCLK

SMCLK frequency

16⁽⁸⁾

MHz

(1) Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range. Following

the data sheet recommendation for capacitor C_DVCClimits the slopes accordingly.

(2) TI recommends that power to the DVCC pin must not exceed the limits specified in Recommended Operating Conditions. Exceeding

the specified limits can cause malfunction of the device including erroneous writes to RAM and FRAM.

(3) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.

(4) The minimum supply voltage is defined by the SVS levels. Refer to the SVS threshold parameters in 节8.12.1.1.

(5) A capacitor tolerance of ±20% or better is required. A low-ESR ceramic capacitor of 100 nF (minimum) should be placed as close as

possible (within a few millimeters) to the respective pin pair.

(6) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

(7) Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executed

without wait states.

(8) If clock sources such as HF crystals or the DCO with frequencies >16 MHz are used, the clock must be divided in the clock system to

comply with this operating condition.

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8.4 Active Mode Supply Current Into V_CCExcluding External Current

See ⁽¹⁾

FREQUENCY (f_MCLK= f_SMCLK

)

1 MHz

0 WAIT STATES

(NWAITSx = 0)

8 MHz

0 WAIT STATES

(NWAITSx = 0)

16 MHz

1 WAIT STATE

(NWAITSx = 1)

EXECUTION

MEMORY

TEST

CONDITION

PARAMETER

UNIT

TYP

567

578

593

324

340

354

241

255

270

268

MAX

TYP

3208

3226

3249

1272

1304

1321

604

MAX

TYP

3472

3471

3496

2022

2065

2085

1016

1041

1060

1446

MAX

3 V, 25°C

3 V, 85°C

3 V, 105°C

3 V, 25°C

3 V, 85°C

3 V, 105°C

3 V, 25°C

3 V, 85°C

3 V, 105°C

3 V, 25°C

FRAM

0% cache hit ratio

I_{AM, FRAM}(0%)

µA

3750

FRAM

75% cache hit ratio

I_{AM, FRAM}(75%)

FRAM

100% cache hit

ratio

I_{AM, FRAM}(100%)

624

µA

641

1150

(2)

I_{AM, RAM}

RAM

821

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current. Characterized with program executing typical data

processing.

f_ACLK= 32768 Hz, f_MCLK= f_SMCLK= f_DCOat specified frequency

Program and data entirely reside in FRAM. All execution is from FRAM.

(2) Program and data reside entirely in RAM. All execution is from RAM. No access to FRAM.

8.5 Active Mode Supply Current Per MHz

V_CC= 3 V, T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

TYP

UNIT

Active mode current consumption per MHz,

execution from FRAM, no wait states

[I_AM(75% cache hit rate) at 8 MHz –

I_AM(75% cache hit rate) at 1 MHz) / 7 MHz

dI_AM,FRAM/df

135

µA/MHz

8.6 Low-Power Mode LPM0 Supply Currents Into V_CCExcluding External Current

V_CC= 3 V, T_A= 25°C (unless otherwise noted)^{(1) (2)}

FREQUENCY (f_SMCLK

)

PARAMETER

V_CC

1 MHz

TYP

8 MHz

16 MHz

TYP MAX

UNIT

MAX

TYP

312

325

MAX

2 V

3 V

204

215

437

I_LPM0

µA

450

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) Current for watchdog timer clocked by SMCLK included.

f_ACLK= 32768 Hz, f_MCLK= 0 MHz, f_SMCLKat specified frequency.

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8.7 Low-Power Mode (LPM3, LPM4) Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) ⁽¹⁾

25°C

TYP MAX

1.48

85°C

105°C

–40°C

TYP MAX

PARAMETER

V_CC

UNIT

µA

TYP

MAX

TYP MAX

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

1.2

1.17

1.87

1.85

0.92

0.90

0.99

0.97

0.65

0.64

0.50

0.49

0.59

0.58

0.92

0.90

7.82

7.75

8.53

8.47

7.54

7.47

7.6

17.12

16.99

17.76

17.65

16.83

16.70

16.9

46

Low-power mode 3, 12.5-pF crystal,

includes SVS^{(2) (3) (4)}

I_LPM3,XT1

I_{LPM3, REFO}

I_LPM3,VLO

I_{LPM3, RTC}

I_{LPM4, SVS}

I_LPM4

1.46

2.20

Low-power mode 3, RTC, excludes

SVS⁽¹⁰⁾

µA

2.18

1.20

45.8

Low-power mode 3, VLO, excludes

SVS⁽⁵⁾

µA

1.17

1.27

Low-power mode 3, RTC, excludes

SVS⁽⁹⁾

1.24

7.53

7.19

7.13

7.02

6.96

7.12

7.06

7.54

7.47

16.77

16.41

16.30

16.24

16.13

16.35

16.24

16.84

16.70

0.90

Low-power mode 4, includes SVS⁽⁶⁾

Low-power mode 4, excludes SVS⁽⁶⁾

µA

0.89

0.74

0.73

0.83

Low-power mode 4, RTC is soured

from VLO, excludes SVS⁽⁷⁾

I_LPM4,VLO

0.82

1.2

Low-power mode 4, RTC is soured

from XT1, excludes SVS⁽⁸⁾

I_LPM4,XT1

1.18

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) Not applicable for MCUs with HF crystal oscillator only.

(3) Characterized with a Seiko Crystal SC-32S MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load

capacitance are chosen to closely match the required 12.5-pF load.

(4) Low-power mode 3, 12.5-pF crystal, includes SVS test conditions:

Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),

f_XT1= 32768 Hz, f_ACLK= f_XT1, f_MCLK= f_SMCLK= 0 MHz

(5) Low-power mode 3, VLO, excludes SVS test conditions:

Current for watchdog timer clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3)

f_XT1= 32768 Hz, f_ACLK= f_MCLK= f_SMCLK= 0 MHz

(6) Low-power mode 4, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4), CPU and all clocks are disabled, WDT and RTC

disabled

(7) Low-power mode 4, VLO, excludes SVS test conditions:

Current for RTC clocked by VLO included. Current for brownout included. SVS disabled (SVSHE = 0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4)

f_XT1= 0 Hz, f_MCLK= f_SMCLK= 0 MHz

(8) Low-power mode 4, XT1, excludes SVS test conditions:

Current for RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE = 0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4)

f_XT1= 32768 Hz, f_MCLK= f_SMCLK= 0 MHz

(9) RTC periodically wakes up every second with external 32768-Hz input as source.

(10) RTC periodically wakes up every second with internal REFO 32768-Hz input as source.

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8.8 Low-Power Mode LPMx.5 Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

25°C

TYP MAX

0.66

85°C

105°C

TYP MAX

–40°C

TYP MAX

PARAMETER

V_CC

UNIT

TYP

MAX

Low-power mode 3.5, 12.5-pF crystal,

includes SVS^{(1) (2) (3)}

(also see 图8-3)

3 V

2 V

0.60

0.58

0.96

0.92

1.41

1.33

2.95

I_{LPM3.5, XT1}

µA

0.65

3 V

2 V

3 V

2 V

0.24

0.23

0.26

0.25

0.40

0.37

0.61

0.56

1.10

0.80

I_{LPM4.5, SVS}

Low-power mode 4.5, includes SVS⁽⁴⁾

Low-power mode 4.5, excludes SVS⁽⁵⁾

µA

0.029

0.027

0.041

0.037

0.161

0.137

0.361

0.31

I_LPM4.5

(1) Not applicable for MCUs with HF crystal oscillator only.

(2) Characterized with a Seiko Crystal SC-32S MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load

capacitance are chosen to closely match the required 12.5-pF load.

(3) Low-power mode 3.5, 12.5-pF crystal, includes SVS test conditions:

Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

f_XT1= 32768 Hz, f_ACLK= 0, f_MCLK= f_SMCLK= 0 MHz

(4) Low-power mode 4.5, includes SVS test conditions:

Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5)

f_XT1= 0 Hz, f_ACLK= f_MCLK= f_SMCLK= 0 MHz

(5) Low-power mode 4.5, excludes SVS test conditions:

Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5)

f_XT1= 0 Hz, f_ACLK= f_MCLK= f_SMCLK= 0 MHz

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8.9 Typical Characteristics –Low-Power Mode Supply Currents

18

16

14

12

10

8

18

16

14

12

10

8

6

4

2

0

-40

-20

0

20

Temperature (°C)

40

60

80

100

120

-40

-20

0

20

Temperature (°C)

40

60

80

100

120

ilpm

V_CC= 3 V

RTC enabled

SVS disabled

V_CC= 2 V

RTC enabled

SVS disabled

图8-1. LPM3 Supply Current vs Temperature

图8-2. LPM3 Supply Current vs Temperature

2

1.8

1.6

1.4

1.2

1

0.35

0.3

0.25

0.2

0.15

0.1

0.05

0

0.8

-40 -25 -10

5

20

Temperature (°C)

35

50

65

80

95 110

-40 -25 -10

5

20

Temperature (°C)

35

50

65

80

95 110

ilpm

g-il

V_CC= 3 V

XT1 enabled

SVS enabled

V_CC= 3 V

SVS disabled

图8-3. LPM3.5 Supply Current vs Temperature

图8-4. LPM4.5 Supply Current vs Temperature

8.10 Current Consumption Per Module

MODULE

Timer_A

TEST CONDITIONS

REFERENCE CLOCK

Module input clock

MIN

TYP

5

MAX

UNIT

µA/MHz

nA

eUSCI_A

eUSCI_B

RTC

UART mode

Module input clock

32 kHz

7

SPI mode

5

SPI mode

5

I²C mode, 100 kbaud

5

85

8.5

CRC

From start to end of operation

MCLK

µA/MHz

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8.11 Thermal Resistance Characteristics

THERMAL METRIC⁽¹⁾

VALUE⁽²⁾

62.4

UNIT

LQFP 48 pin (PT)

VQFN 40 pin (RHA)

VQFN 32 pin (RHB)

LQFP 48 pin (PT)

VQFN 40 pin (RHA)

VQFN 32 pin (RHB)

LQFP 48 pin (PT)

VQFN 40 pin (RHA)

VQFN 32 pin (RHB)

Junction-to-ambient thermal resistance, still air

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

31.0

°C/W

Rθ_JA

Rθ_JC

Rθ_JB

30.8

22.1

22.3

°C/W

20.8

26.3

12.3

11.6

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (Rθ_JC) value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC

standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

8.12 Timing and Switching Characteristics

8.12.1 Power Supply Sequencing

8.12.1.1 PMM, SVS and BOR

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

0.1

10

TYP

MAX UNIT

V_{BOR, safe}

t_{BOR, safe}

I_SVSH,AM

Safe BOR power-down level⁽¹⁾

Safe BOR reset delay⁽²⁾

V

ms

SVS_Hcurrent consumption, active mode

SVS_Hcurrent consumption, low-power modes

SVS_Hpower-down level⁽⁴⁾

V_CC= 3.6 V

1.5 µA

nA

I_SVSH,LPM

V_SVSH-

240

1.80

1.88

100

1.71

1.76

1.87

1.99

V

V_SVSH+

SVS_Hpower-up level⁽⁴⁾

V_{SVSH_hys}

t_{PD,SVSH, AM}

t_{PD,SVSH, LPM}

SVS_Hhysteresis

mV

µs

SVS_Hpropagation delay, active mode

SVS_Hpropagation delay, low-power modes

10

100

(1) A safe BOR can be correctly generated only if DVCC drops below this voltage before it rises.

(2) When an BOR occurs, a safe BOR can be correctly generated only if DVCC is kept low longer than this period before it reaches

V_SVSH+

(3) This is a characterized result with external 1-mA load to ground from –40°C to 85°C.

.

(4) For additional information, see the Dynamic Voltage Scaling Power Solution for MSP430 Devices With Single-Channel LDO Reference

Design.

V

Power Cycle Reset

V_SVS+

SVS Reset

BOR Reset

V_SVS–

V_BOR

t_BOR

t

图8-5. Power Cycle, SVS, and BOR Reset Conditions

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8.12.2 Reset Timing

8.12.2.1 Wake-up Times From Low-Power Modes and Reset

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEST

CONDITIONS

PARAMETER

V_CC

3 V

MIN

TYP

MAX UNIT

Additional wake-up time to activate the FRAM in

AM if previously disabled by the FRAM controller or

from a LPM if immediate activation is selected for

wakeup⁽¹⁾

t_{WAKE-UP FRAM}

10

µs

200 +

ns

t_{WAKE-UP LPM0}

Wake-up time from LPM0 to active mode ⁽¹⁾

2.5 / f_DCO

t_{WAKE-UP LPM3}

t_{WAKE-UP LPM4}

Wake-up time from LPM3 to active mode ⁽²⁾

Wake-up time from LPM4 to active mode

3 V

10

µs

ms

t_{WAKE-UP LPM3.5}Wake-up time from LPM3.5 to active mode ⁽²⁾

350

1

SVSHE = 1

SVSHE = 0

t_{WAKE-UP LPM4.5}Wake-up time from LPM4.5 to active mode ⁽²⁾

3 V

Wake-up time from RST or BOR event to active

t_{WAKE-UP-RESET}

t_RESET

3 V

1

ms

µs

mode ⁽²⁾

Pulse duration required at RST/NMI pin to accept a

reset

2

(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first

externally observable MCLK clock edge.

(2) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first

instruction of the user program is executed.

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8.12.3 Clock Specifications

8.12.3.1 XT1 Crystal Oscillator (Low Frequency)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)^{(1) (2)}

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

f_{XT1, LF}

XT1 oscillator crystal, low frequency LFXTBYPASS = 0

32768

Hz

Measured at MCLK,

XT1 oscillator LF duty cycle

DC_{XT1, LF}

30%

70%

kHz

60%

kΩ

f_LFXT= 32768 Hz

XT1 oscillator logic-level square-

LFXTBYPASS = 1 ^{(3) (4)}

wave input frequency

f_XT1,SW

DC_{XT1, SW}

OA_LFXT

C_L,eff

32.768

LFXT oscillator logic-level square-

LFXTBYPASS = 1

40%

wave input duty cycle

Oscillation allowance for LF crystals LFXTBYPASS = 0, LFXTDRIVE = {3},

200

1

(5)

f_LFXT= 32768 Hz, C_L,eff= 12.5 pF

Integrated effective load

See ⁽⁷⁾

pF

capacitance⁽⁶⁾

f_OSC= 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {3},

T_A= 25°C, C_L,eff= 12.5 pF

t_START,LFXT

f_Fault,LFXT

Start-up time ⁽⁹⁾

1000

ms

Oscillator fault frequency ⁽¹⁰⁾

XTS = 0⁽⁸⁾

0

3500

Hz

(1) To improve EMI on the LFXT oscillator, observe the following guidelines:

•

Keep the trace between the device and the crystal as short as possible.

Design a good ground plane around the oscillator pins.

Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.

If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.

(2) See the MSP430 32-kHz Crystal Oscillators application note for details on crystal section, layout, and testing.

(3) When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics

defined in the Schmitt-trigger inputs section of this data sheet. Duty cycle requirements are defined by DC_{LFXT, SW}

(4) Maximum frequency of operation of the entire device cannot be exceeded.

.

(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the

LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following

guidelines, but should be evaluated based on the actual crystal selected for the application:

•

For LFXTDRIVE = {0}, C_L,eff= 3.7 pF

For LFXTDRIVE = {1}, 6 pF ≤C_L,eff≤9 pF

For LFXTDRIVE = {2}, 6 pF ≤C_L,eff≤10 pF

For LFXTDRIVE = {3}, 6 pF ≤C_L,eff≤12 pF

(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

(7) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers.

Recommended effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF.

The PCB adds additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective

load capacitance of the selected crystal is met.

(8) Measured with logic-level input frequency but also applies to operation with crystals.

(9) Includes start-up counter of 1024 clock cycles.

(10) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications might set the

flag. A static condition or stuck at fault condition sets the flag.

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8.12.3.2 DCO FLL, Frequency

over recommended operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

3 V

MIN

–1.0%

–3.0%

TYP

MAX UNIT

1.0%

FLL lock frequency, 16 MHz, 25°C

FLL lock frequency, 16 MHz, –40°C to 105°C

Measured at MCLK, Internal

trimmed REFO as reference

3.0%

f_{DCO, FLL}

Measured at MCLK, XT1

crystal as reference

3 V

0.5%

60%

FLL lock frequency, 16 MHz, –40°C to 105°C

–0.5%

f_DUTY

Duty cycle

3 V

40%

50%

0.25%

0.022%

200

Jitter_cc

Jitter_long

t_{FLL, lock}

Cycle-to-cycle jitter, 16 MHz

Long term jitter, 16 MHz

FLL lock time, 16MHz

Measured at MCLK, XT1

crystal as reference

ms

8.12.3.3 DCO Frequency

over recommended operating free-air temperature (unless otherwise noted) (see 图8-6)

PARAMETER

TEST CONDITIONS

V_CC

TYP

UNIT

DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 0

8.5

13.9

20

DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 511

f_{DCO, 16MHz}

f_{DCO, 12MHz}

f_{DCO, 8MHz}

f_{DCO, 4MHz}

DCO frequency, 16 MHz

3 V

MHz

DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 0

DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 511

32.7

6.4

DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 0

DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 511

10.5

15.4

24.8

4.3

DCO frequency, 12 MHz

DCO frequency, 8 MHz

DCO frequency, 4 MHz

MHz

DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 0

DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 511

DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 0

DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 511

7.1

DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 0

10.4

16.9

2.1

DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 511

DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 0

DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 511

3.5

DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 0

5.2

DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 511

8.5

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8.12.3.3 DCO Frequency (continued)

over recommended operating free-air temperature (unless otherwise noted) (see 图8-6)

PARAMETER

TEST CONDITIONS

V_CC

TYP

UNIT

DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 0

1.1

1.8

2.6

4.3

0.5

0.9

1.3

2.2

DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 511

f_{DCO, 2MHz}

DCO frequency, 2 MHz

3 V

MHz

DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 0

DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 511

DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 0

DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 511

f_{DCO, 1MHz}

DCO frequency, 1 MHz

3 V

MHz

DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 0

DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 511

35

30

25

20

15

10

DCOFTRIM = 7

DCOFTRIM = 0

DCOFTRIM = 7

DCOFTRIM = 0

5

DCOFTRIM = 0

DCOFTRIM = 7

DCOFTRIM = 0

0

DCOFTRIM = 0

DCO

0

511

0

511

0

511

0

511

0

511

0

511

DCORSEL

0

1

2

3

4

5

V_CC= 3 V

T_A= –40°C to 85°C

图8-6. Typical DCO Frequency

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8.12.3.4 REFO

over recommended operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

3 V

MIN

TYP

1

MAX UNIT

I_REFO

REFO oscillator current consumption

REFO calibrated frequency

T_A= 25°C

µA

Hz

Measured at MCLK

–40°C to 105°C

3 V

32768

f_REFO

REFO absolute calibrated tolerance

REFO frequency temperature drift

1.8 V to 3.6 V

3 V

+3.5%

%/°C

–3.5%

df_REFO/d_T

Measured at MCLK⁽¹⁾

0.01

1

df_REFO

d_VCC

/

REFO frequency supply voltage drift

Measured at MCLK at 25°C⁽²⁾

1.8 V to 3.6 V

%/V

f_DC

REFO duty cycle

Measured at MCLK

40%

50%

50

60%

µs

t_START

REFO start-up time

40% to 60% duty cycle

(1) Calculated using the box method: (MAX(–40°C to 105°C) –MIN(–40°C to 105°C)) / MIN(–40°C to 105°C) / (105°C –(–40°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) –MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V –1.8 V)

8.12.3.5 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

VLO frequency

VLO frequency temperature drift

TEST CONDITIONS

V_CC

TYP UNIT

10 kHz

0.5 %/°C

f_VLO

Measured at MCLK

3 V

df_VLO/d_T

Measured at MCLK⁽¹⁾

Measured at MCLK⁽²⁾

Measured at MCLK

3 V

df_VLO/dV_CCVLO frequency supply voltage drift

f_VLO,DCDuty cycle

1.8 V to 3.6 V

3 V

4

%/V

50%

(1) Calculated using the box method: (MAX(–40°C to 105°C) –MIN(–40°C to 105°C)) / MIN(–40°C to 105°C) / (105°C –(–40°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) –MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V –1.8 V)

Note

The VLO clock frequency is reduced by 15% (typical) when the device switches from active mode to

LPM3 or LPM4, because the reference changes. This lower frequency is not a violation of the VLO

specifications (see 节8.12.3.5).

8.12.3.6 Module Oscillator (MODOSC)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

3.8

MAX UNIT

4.6 MHz

%/℃

f_MODOSC

MODOSC frequency

3 V

3.0

f_MODOSC/dT

MODOSC frequency temperature drift

3 V

0.102

1.17

50%

f_MODOSC/dV_CCMODOSC frequency supply voltage drift

f_MODOSC,DCDuty cycle

1.8 V to 3.6 V

3 V

%/V

40%

60%

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8.12.4 Digital I/Os

8.12.4.1 Digital Inputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

2 V

3 V

2 V

3 V

2 V

3 V

MIN

0.90

1.35

0.50

0.75

0.3

TYP

MAX UNIT

1.50

V

2.25

V_IT+

V_IT–

V_hys

Positive-going input threshold voltage

1.10

V

1.65

Negative-going input threshold voltage

0.8

V

1.2

Input voltage hysteresis (V_IT+–V_IT–

)

0.4

For pullup: V_IN= V_SS

For pulldown: V_IN= V_CC

R_Pull

Pullup or pulldown resistor

20

35

3

50

20

kΩ

pF

nA

C_I,dig

Input capacitance, digital only port pins

V_IN= V_SSor V_CC

Input capacitance, port pins with shared analog

functions

C_I,ana

I_lkg(Px.y)

5

High-impedance leakage current of GPIO Pins See ^{(1) (2)}

Ports with interrupt capability

External interrupt timing (external trigger pulse (see block diagram and

2 V, 3 V

–20

t_(int)

50

ns

duration to set interrupt flag)⁽³⁾

terminal function

descriptions)

(1) The leakage current is measured with V_SSor V_CCapplied to the corresponding pins, unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is

disabled.

(3) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t_(int)is met. It may be set by trigger signals

shorter than t_(int)

.

8.12.4.2 Digital Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_(OHmax)= –3 mA⁽¹⁾

I_(OHmax)= –5 mA⁽¹⁾

I_(OLmax)= 3 mA⁽¹⁾

V_CC

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

MIN

1.4

2.4

0.0

16

TYP

MAX UNIT

2.0

V

3.0

V_OH

High-level output voltage

0.60

V

0.60

V_OL

Low-level output voltage

I_(OHmax)= 5 mA⁽¹⁾

f_{Port_CLK}

t_rise,dig

t_fall,dig

Clock output frequency

C_L= 20 pF⁽²⁾

C_L= 20 pF

MHz

ns

16

10

7

Port output rise time, digital only port pins

Port output fall time, digital only port pins

10

5

ns

(1) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage

drop specified.

(2) The port can output frequencies at least up to the specified limit and might support higher frequencies.

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8.12.4.3 Typical Characteristics –Outputs at 3 V and 2 V

25

10

9

8

7

6

5

4

3

2

1

0

20

15

10

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= 105èC

5

T_A= 25èC

T_A= 85èC

T_A= 105èC

0

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7

Low-Level Output Voltage (V)

3

0

0.2 0.4 0.6 0.8

1

Low-Level Output Voltage (V)

1.2 1.4 1.6 1.8

2

g-io

DVCC = 3 V

DVCC = 2 V

图8-7. Typical Low-Level Output Current vs Low-Level Output

图8-8. Typical Low-Level Output Current vs Low-Level Output

Voltage

5

2

T_A= -40èC

T_A= 25èC

0

T_A= 85èC

T_A= 105èC

T_A= 85èC

T_A= 105èC

-5

-2

-10

-15

-20

-25

-30

-4

-6

-8

-10

0

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7

High-Level Output Voltage (V)

3

0

0.2 0.4 0.6 0.8

1

High-Level Output Voltage (V)

1.2 1.4 1.6 1.8

2

g-io

DVCC = 3 V

DVCC = 2 V

图8-9. Typical High-Level Output Current vs High-Level Output

图8-10. Typical High-Level Output Current vs High-Level

Voltage

Output Voltage

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8.12.5 Internal Shared Reference

8.12.5.1 Internal Reference Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX

UNIT

mV

V_SENSOR

Temperature sensor voltage

Temperature sensor coefficient

Low-power threshold for eCOMP

2.0 V, 3.0 V

788

T_J= 30℃

TC_SENSOR

V_{eCOMP, LP}

2.5

mV/°C

V

T_J= 30℃

2.0 V, 3.0 V

1.20

Positive built-in reference output at

VREF+ pin with 1-mA load current

to ground

EXTREFEN = 1 with 1-mA load

current

V_{REF+, 1.2V Output}

TC_{REF+, 1.2V}

1.16

1.20

30

1.24

V

Temperature coefficient of VREF+ EXTREFEN = 1 with 1-mA load

= 1.2 V built-in reference current

3.0 V

µV/°C

The following parameters are for the 1.5-V, 2.0-V, and 2.5-V internal reference only and cannot be output to the VREF+ pin.

REFVSEL = {2} for 2.5 V,

3.0 V

2.5

±1.5%

±1.8%

130

INTREFEN = 1

Positive built-in reference voltage

as internal reference

REFVSEL = {1} for 2.0 V,

INTREFEN = 1

V_{REF+, 1.5V, 2.0V, 2.5V}

2.5 V

2.0 V

2.0

1.5

30

V

REFVSEL = {0} for 1.5 V,

INTREFEN = 1

From 0.1 Hz to 10 Hz,

REFVSEL = {0}

Noise

RMS noise at VREF ⁽³⁾

µV

V

REFVSEL = {0} for 1.5 V

REFVSEL = {1} for 2.0 V

REFVSEL = {2} for 2.5 V

1.8

2.2

2.7

DVCC minimum voltage, Positive

built-in reference active

DV_CC(min)

Operating supply current into

DVCC terminal⁽¹⁾

I_REF+

INTREFEN = 1

3 V

19

26

µA

Operating supply current into AVCC

terminal⁽¹⁾

I_{REF+_ADC_BUF}

ADC ON, REFVSEL = {0, 1, 2}

247

400

VREF (1.5 V, 2.0 V, 2.5 V)

maximum load current, VREF+

terminal

REFVSEL = {0, 1, 2},

AVCC = AVCC(min) for each

reference level, INTREFEN = 1

I_O(VREF+)

3 V

-1000

+10

µA

REFVSEL = {0, 1, 2},

Load-current regulation, VREF+

terminal

I_O(VREF+)= +10 µA or -1000 µA

AVCC = AVCC(min) for each

reference level, INTREFEN = 1

ΔVout/ ΔIo

(VREF+)

1500

µV/mA

Capacitance at VREF+ and VREF-

terminals

C_VREF+/-

TC_REF+

INTREFEN = 1

3 V

0

100

50

pF

Temperature coefficient of built-in

reference

REFVSEL = {0, 1, 2},

INTREFEN = 1,

T_A= –40°C to 105°C⁽⁴⁾

24

ppm/K

AV_CC= AV_{CC (min)}to AV_CC(max), T_A

25°C, REFVSEL = {0, 1, 2},

INTREFEN = 1

=

PSRR_DC

PSRR_AC

t_SETTLE

Power supply rejection ratio (DC)

Power supply rejection ratio (AC)

Settling time of reference voltage⁽²⁾

3 V

100

3.0

75

420

100

µV/V

mV/V

µs

ΔAV_CC= 0.1 V at 1 kHz

AV_CC= AV_{CC (min)}to AV_CC(max)

REFVSEL = {0, 1, 2},

,

INTREFEN = 0 →1

(1) The internal reference current is supplied through the AVCC terminal.

(2) The condition is that the error in a conversion started after t_REFONis less than ±0.5 LSB.

(3) The internal reference noise affects ADC performance when the ADC uses the internal reference.

(4) Calculated using the box method: (MAX(–40°C to 105°C) –MIN(–40°C to 105°C)) / MIN(–40°C to 105°C) / (105°C –(–40°C))

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8.12.6 Timer_A and Timer_B

8.12.6.1 Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Internal: SMCLK, ACLK

f_TA

Timer_A input clock frequency

External: TACLK

2 V, 3 V

16 MHz

Duty cycle = 50% ±10%

All capture inputs, minimum pulse

duration required for capture

t_TA,cap

Timer_A capture timing

2 V, 3 V

20

ns

8.12.6.2 Timer_B

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Internal: SMCLK, ACLK

f_TB

Timer_B input clock frequency

External: TBCLK

2 V, 3 V

16 MHz

Duty cycle = 50% ±10%

All capture inputs, minimum pulse

duration required for capture

t_TB,cap

Timer_B capture timing

2 V, 3 V

20

ns

t_TIMR

Timer Clock

CCR0-1

0h

1h

CCR0

CCR0-1

0h

CCR0

t_VALID,PWM

Timer

TAx.1

t_HD,PWM

图8-11. Timer PWM Mode

Capture

t_TIMR

Timer Clock

t_SU,CCIA

t_,HD,CCIA

TAx.CCIA

图8-12. Timer Capture Mode

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8.12.7 eUSCI

8.12.7.1 eUSCI (UART Mode) Clock Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Internal: SMCLK, MODCLK

External: UCLK

Duty cycle = 50% ±10%

f_eUSCIeUSCI input clock frequency

2 V, 3 V

16 MHz

f_BITCLKBITCLK clock frequency (equals baud rate in Mbaud)

5

MHz

8.12.7.2 eUSCI (UART Mode) Timing Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

TYP UNIT

UCGLITx = 0

12

UCGLITx = 1

UCGLITx = 2

UCGLITx = 3

40

ns

68

t_t

UART receive deglitch time ⁽¹⁾

2 V, 3 V

110

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized, their duration should exceed the maximum specification of the deglitch time.

8.12.7.3 eUSCI (SPI Master Mode) Clock Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

Internal: SMCLK, MODCLK

Duty cycle = 50% ±10%

MIN

MAX UNIT

MHz

f_eUSCIeUSCI input clock frequency

8

8.12.7.4 eUSCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX

UNIT

UCSTEM = 0, UCMODEx = 01 or 10

UCSTEM = 1, UCMODEx = 01 or 10

UCSTEM = 0, UCMODEx = 01 or 10

UCSTEM = 1, UCMODEx = 01 or 10

UCxCLK

cycles

t_STE,LEADSTE lead time, STE active to clock

1

UCxCLK

cycles

t_STE,LAGSTE lag time, last clock to STE inactive

1

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

58

40

0

t_SU,MI

SOMI input data setup time

SOMI input data hold time

ns

t_HD,MI

0

20

t_VALID,MOSIMO output data valid time⁽²⁾

UCLK edge to SIMO valid, C_L= 20 pF

C_L= 20 pF

-3

t_HD,MO

SIMO output data hold time⁽³⁾

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI= max(t_{VALID,MO(eUSCI)}+ t_SU,SI(Slave), t_SU,MI(eUSCI)+ t_{VALID,SO(Slave)}).

For the slave parameters t_SU,SI(Slave)and t_{VALID,SO(Slave)}, see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams

in 图8-13 and 图8-14.

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in 图

8-13 and 图8-14.

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UCMODEx = 01

UCMODEx = 10

t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

UCLK

CKPL = 1

t_LOW/HIGH

t_SU,MI

t_HD,MI

SOMI

SIMO

t_HD,MO

t_VALID,MO

t_STE,ACC

t_STE,DIS

图8-13. SPI Master Mode, CKPH = 0

UCMODEx = 01

STE

t_STE,LEAD

t_STE,LAG

UCMODEx = 10

1/f_UCxCLK

CKPL = 0

UCLK

CKPL = 1

t_LOW/HIGH

t_HD,MI

t_SU,MI

SOMI

SIMO

t_HD,MO

t_VALID,MO

t_STE,DIS

t_STE,ACC

图8-14. SPI Master Mode, CKPH = 1

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8.12.7.5 eUSCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

MIN

MAX UNIT

55

t_STE,LEADSTE lead time, STE active to clock

ns

45

20

t_STE,LAG

t_STE,ACC

t_STE,DIS

t_SU,SI

STE lag time, Last clock to STE inactive

STE access time, STE active to SOMI data out

STE disable time, STE inactive to SOMI high impedance

SIMO input data setup time

ns

20

65

ns

40

ns

35

15

6

ns

12

t_HD,SI

SIMO input data hold time

71

ns

42

UCLK edge to SOMI valid,

C_L= 20 pF

t_VALID,SOSOMI output data valid time⁽²⁾

5

t_HD,SO

SOMI output data hold time ⁽³⁾

C_L= 20 pF

ns

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI≥max(t_{VALID,MO(Master)}+ t_SU,SI(eUSCI), t_{SU,MI(Master)}+ t_{VALID,SO(eUSCI)}).

For the master parameters t_{SU,MI(Master)}and t_{VALID,MO(Master)}, see the SPI parameters of the attached master.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams

in 图8-15 and 图8-16.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in 图

8-15 and 图8-16.

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UCMODEx = 01

UCMODEx = 10

t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

UCLK

CKPL = 1

t_SU,SI

t_LOW/HIGH

t_HD,SI

SIMO

t_HD,SO

t_VALID,SO

t_STE,ACC

t_STE,DIS

SOMI

图8-15. SPI Slave Mode, CKPH = 0

UCMODEx = 01

UCMODEx = 10

t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

UCLK

CKPL = 1

t_LOW/HIGH

t_HD,SI

t_SU,SI

SIMO

t_HD,SO

t_VALID,SO

t_STE,ACC

t_STE,DIS

SOMI

图8-16. SPI Slave Mode, CKPH = 1

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8.12.7.6 eUSCI (I²C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see 图8-17)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, MODCLK

External: UCLK

f_eUSCI

eUSCI input clock frequency

16 MHz

Duty cycle = 50% ±10%

f_SCL

SCL clock frequency

2 V, 3 V

0

4.0

0.6

4.7

0.6

0

400 kHz

µs

f_SCL= 100 kHz

f_SCL> 100 kHz

f_SCL= 100 kHz

f_SCL> 100 kHz

t_HD,STA

Hold time (repeated) START

t_SU,STA

Setup time for a repeated START

2 V, 3 V

µs

t_HD,DAT

t_SU,DAT

Data hold time

Data setup time

2 V, 3 V

ns

250

4.0

0.6

50

f_SCL= 100 kHz

f_SCL> 100 kHz

UCGLITx = 0

UCGLITx = 1

UCGLITx = 2

UCGLITx = 3

UCCLTOx = 1

UCCLTOx = 2

UCCLTOx = 3

t_SU,STO

Setup time for STOP

2 V, 3 V

µs

600

25

300

ns

150

Pulse duration of spikes suppressed by

input filter

t_SP

2 V, 3 V

12.5

6.3

75

27

30

33

t_TIMEOUTClock low time-out

2 V, 3 V

ms

t_HD,STA

t_SU,STA

t_HD,STA

t_BUF

SDA

SCL

t_LOW

t_HIGH

t_SP

t_SU,DAT

t_SU,STO

t_HD,DAT

图8-17. I²C Mode Timing

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8.12.8 ADC

8.12.8.1 ADC, Power Supply and Input Range Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

2.0

0

TYP

MAX UNIT

DV_CC

V_(Ax)

ADC supply voltage

3.6

V

Analog input voltage range

All ADC pins

DV_CC

Operating supply current into DVCC

terminal, reference current not

included, repeat-single-channel mode ADCDIV = 0, ADCCONSEQx = 10b

f_ADCCLK= 5 MHz, ADCON = 1,

REFON = 0, SHT0 = 0, SHT1 = 0,

2.0 V

3.0 V

220

277

I_ADC

µA

Only one terminal Ax can be selected

at one time from the pad to the ADC

Input capacitance

C_I

R_I

2.2 V

4.5

5.5

2

pF

capacitor array, including wiring and

pad

Input MUX ON resistance

DV_CC= 2 V, 0 V ≤V_Ax≤DV_CC

kΩ

8.12.8.2 ADC, Timing Parameters

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX

UNIT

For specified performance of ADC linearity

parameters, 10-bit mode

2.4 V to

3.6 V

6

f_ADCCLK

MHz

For specified performance of ADC linearity

parameters, 12-bit mode

2.4 V to

3.6 V

4.4

External f_ADCCLKfrom ACLK, MCLK, or SMCLK,

ADCSSEL ≠0

2.4 V to

3.6 V

(2)

t_CONVERT

Conversion time

µs

ns

The error in a conversion started after t_ADCONis

less than ±0.5 LSB,

Reference and input signal already settled

Turn-on settling time of

the ADC

t_ADCON

100

R_S= 1000 Ω, R_I= 20000 Ω, C_I= 5.5 pF, C_EXT

= 8 pF,

2.4 V to

3.6 V

0.52

0.61

Approximately 7.62 Tau (t) are required for an

error of less than ±0.5 LSB, 10-bit mode.⁽³⁾

t_Sample

Sampling time

µs

R_S= 1000 Ω, R_I= 40000 Ω, C_I= 5.5 pF, C_EXT

= 8 pF,

2.4 V to

3.6 V

Approximately 9.01 Tau (t) are required for an

error of less than ±0.5 LSB, 12-bit mode.⁽³⁾

(1) 12 × 1/f_ADCCLK

(2) (n + 2) × 1/f_ADCCLK, n = ADC resolution (8, 10, 12)

(3) t_Sample= ln(2ⁿ⁺¹) × τ, where n = ADC resolution, τ= (R_I+ R_S) × C_I

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8.12.8.3 ADC, Linearity Parameters

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX

UNIT

Integral linearity error (12-bit

mode)

2.4 V to

3.6 V

Veref+ reference

2.5

2

–2.5

E_I

LSB

Integral linearity error (10-bit

mode)

2.4 V to

3.6 V

Veref+ reference

–2

–1

Differential linearity error (12-bit

mode)

2.4 V to

3.6 V

1.5

E_D

LSB

mV

Differential linearity error (10-bit

mode)

2.4 V to

3.6 V

Veref+ reference,

2.4 V to

3.6 V

Offset error (12-bit mode)

Offset error (10-bit mode)

Gain error (12-bit mode)

Gain error (10-bit mode)

TLV calibration data can be used

-4.0

4.0

9.0

3.0

5.0

2.0

to improve the parameter⁽²⁾

E_O

E_G

E_T

Veref+ reference,

2.4 V to

3.6 V

TLV calibration data can be used

to improve the parameter⁽²⁾

Veref+ as reference,

2.4 V to

3.6 V

TLV calibration data can be used

-9.0

LSB

to improve the parameter⁽²⁾

Veref+ as reference,

2.4 V to

3.6 V

TLV calibration data can be used

-3.0

to improve the parameter⁽²⁾

Veref+ as reference,

Total unadjusted error (12-bit

mode)

2.4 V to

3.6 V

TLV calibration data can be used

–5.0

–2.0

to improve the parameter⁽²⁾

Veref+ as reference,

Total unadjusted error (10-bit

mode)

2.4 V to

3.6 V

TLV calibration data can be used

to improve the parameter⁽²⁾

(1) The typical equivalent impedance of the sensor is 700 kΩ. The sample time required includes the sensor on time, t_SENSOR(on)

.

(2) For details, see the device descriptor in the MP430FR4xx and MP430FR2xx Family User's Guide, and see Designing With the

MP430FR4xx and MP430FR2xx ADC application note for details on optimizing ADC performance for your application with the choice

of internal or external reference.

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8.12.9 Enhanced Comparator (eCOMP)

8.12.9.1 eCOMP0 Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

2.0

0

TYP

MAX

3.6

UNIT

V

V_CC

V_IC

Supply voltage

Common mode input range

DC input hysteresis

VCC

V

CPEN = 1, CPHSEL= 00

0

10

20

30

CPEN = 1, CPHSEL= 01

V_HYS

mV

CPEN = 1, CPHSEL= 10

CPEN = 1, CPHSEL= 11

CPEN = 1, CPMSEL = 0

+30

+40

35

–30

–40

V_OFFSET

Input offset voltage

mV

µA

CPEN = 1, CPMSEL = 1

V_IC= V_CC/2, CPEN = 1, CPMSEL = 0

V_IC= V_CC/2, CPEN = 1, CPMSEL = 1

24

1.6

1

Quiescent current draw from V_CC

only comparator

,

I_COMP

C_IN

5

Input channel capacitance⁽¹⁾

Input channel series resistance

pF

kΩ

On (switch closed)

10

20

1

R_IN

Off (switch open)

50

MΩ

CPMSEL = 0, CPFLT = 0, Overdrive = 20 mV

CPMSEL = 1, CPFLT = 0, Overdrive = 20 mV

t_PD

Propagation delay, response time

Comparator enable time

µs

3.2

CPEN = 0→1, CPMSEL = 0,

V+ and V- from pads, Overdrive = 20 mV

10.91

t_{EN_CP}

CPEN = 0→1, CPMSEL = 1,

V+ and V- from pads, Overdrive = 20 mV

36.78

11

CPEN = 0→1, CPDACEN = 0→1,

CPMSEL = 0, CPDACREFS = 1,

CPDACBUF1 = 0F, Overdrive = 20 mV

Comparator with reference DAC

enable time

t_{EN_CP_DAC}

µs

CPEN = 0→1, CPDACEN = 0→1,

CPMSEL = 1, Overdrive = 20 mV,

CPDACREFS = 1, CPDACBUF1 = 0F

36.82

CPMSEL = 0, CPFLTDY = 00,

Overdrive = 20 mV, CPFLT = 1

0.7

1.1

1.9

3.4

CPMSEL = 0, CPFLTDY = 01,

Overdrive = 20 mV, CPFLT = 1

Propagation delay with analog filter

active

t_FDLY

µs

CPMSEL = 0, CPFLTDY = 10,

Overdrive = 20 mV, CPFLT = 1

CPMSEL = 0, CPFLTDY = 11,

Overdrive = 20 mV, CPFLT = 1

INL

Integral nonlinearity

0.5

LSB

–0.5

DNL

Differential nonlinearity

(1) See 图8-18 for eCOMP C_INmodel.

MSP430

V_I= External source voltage

R_S= External source resistance

R_I= Internal MUX-on input resistance

C_IN= Input capacitance

R_S

R_I

V_I

V_C

C_PAD= PAD capacitance

C_Pext= Parasitic capacitance, external

V_C= Capacitance-charging voltage

C_pext

C_PAD

C_IN

图8-18. eCOMP Input Circuit

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8.12.10 FRAM

8.12.10.1 FRAM Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

10¹⁵

100

40

TYP

MAX

UNIT

Read and write endurance

cycles

T_J= 25°C

T_J= 70°C

T_J= 95°C

T_J= 115°C

t_Retention

Data retention duration

years

10

(1)

I_WRITE

I_ERASE

t_WRITE

Current to write into FRAM

Erase current

I_READ

nA

ns

N/A⁽²⁾

(3)

Write time

t_READ

(4)

NWAITSx = 0

NWAITSx = 1

1 / f_SYSTEM

2 / f_SYSTEM

t_READ

Read time

ns

(1) Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read

current I_READis included in the active mode current consumption parameter I_AM,FRAM

.

(2) FRAM does not require a special erase sequence.

(3) Writing into FRAM is as fast as reading.

(4) The maximum read (and write) speed is specified by f_SYSTEMusing the appropriate wait state settings (NWAITSx).

8.12.11 Debug and Emulation

8.12.11.1 JTAG, 4-Wire and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

V_CC

MIN

TYP

MAX UNIT

f_SBW

Spy-Bi-Wire input frequency

2.2 V, 3.0 V

0

8

MHz

µs

t_SBW,Low

Spy-Bi-Wire low clock pulse duration

0.04

15

Spy-Bi-Wire enable time (TEST high to acceptance of first clock

edge)⁽¹⁾

t_{SBW, En}

t_SBW,Rst

2.2 V, 3.0 V

100

µs

Spy-Bi-Wire return to normal operation time

TCK input frequency, 4-wire JTAG⁽²⁾

15

0

100

10

µs

2.2 V

3.0 V

MHz

kΩ

f_TCK

0

10

R_internal

f_TCLK

t_{TCLK,Low/High}

f_TCLK,FRAM

Internal pulldown resistance on TEST

2.2 V, 3.0 V

20

35

50

TCLK/MCLK frequency during JTAG access, no FRAM access

16 MHz

(limited by f_SYSTEM

)

TCLK low or high clock pulse duration, no FRAM access

25

4

ns

MHz

ns

TCLK/MCLK frequency during JTAG access, including FRAM

access (limited by f_SYSTEMwith no FRAM wait states)

TCLK low or high clock pulse duration, including FRAM accesses

t_{TCLK,FRAM,Low/High}

100

(1) Tools that access the Spy-Bi-Wire and BSL interfaces must wait for the t_SBW,Entime after the first transition of the TEST/SBWTCK pin

(low to high), before the second transition of the pin (high to low) during the entry sequence.

(2) f_TCKmay be restricted to meet the timing requirements of the module selected.

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9 Detailed Description

9.1 Overview

The MSP430FR247x is an ultra-low-power MCU. The architecture, combined with extensive low-power modes,

is optimized to achieve extended battery life in, for example, portable measurement applications. The MCU

features five 16-bit timers, four eUSCIs that support UART, SPI, and I²C, a hardware multiplier, an RTC module,

and a high-performance 12-bit ADC, an enhanced comparator with built in 6-bit DAC for internal voltage

reference .

9.2 CPU

The MSP430^™CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,

other than program-flow instructions, are performed as register operations in conjunction with seven addressing

modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register

operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter (PC), stack pointer (SP), status register (SR),

and constant generator (CG), respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be handled with

all instructions.

9.3 Operating Modes

The MSP430 has one active mode and several software-selectable low-power modes of operation (see 表 9-1).

An interrupt event can wake the MCU from low-power mode LPM0, LPM3 or LPM4, service the request, and

restore the MCU back to the low-power mode on return from the interrupt program. Low-power modes LPM3.5

and LPM4.5 disable the core supply to minimize power consumption.

Note

XT1CLK and VLOCLK can be active during LPM4 mode if requested by low-frequency peripherals,

such as RTC and WDT.

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表9-1. Operating Modes

AM

LPM0

CPU OFF

16 MHz

LPM3

STANDBY

40 kHz

LPM4

OFF

0

LPM3.5

ONLY RTC

40 kHz

LPM4.5

SHUTDOWN

0

ACTIVE

MODE

(FRAM ON)

Maximum system clock

16 MHz

1.48 µA with

RTC counter

only in LFXT

0.66 µA with

RTC counter

only in LFXT

0.74 µA

without SVS

41 nA without

SVS

Power consumption at 25°C, 3 V

135 µA/MHz

40 µA/MHz

Wake-up time

N/A

Instant

All

10 µs

All

10 µs

I/O

350 µs

I/O

Wake-up events

RTC or I/O

Partial power Partial power Partial power

Regulator

Full regulation Full regulation

Power down

down

Optional

On

down

Optional

On

down

Optional

On

Power

SVS

On

Optional

On

Brownout

MCLK

SMCLK

FLL

On

Active

Off

Optional

On

Optional

Off

DCO

Off

Clock⁽²⁾

MODCLK

REFO

Off

Optional

Off

ACLK

Off

XT1CLK

VLOCLK

CPU

Off

Optional

Off

FRAM

On

Off

Core

RAM

On

Off

Backup memory⁽¹⁾

Timer0_A3

Timer1_A3

Timer2_A3

Timer3_A3

Timer0_B7

WDT

On

Off

Optional

On

Optional

Off

Peripherals

eUSCI_A0

eUSCI_A1

eUSCI_B0

eUSCI_B1

CRC

Off

ADC

Optional

State held

Off

RTC

Off

Optional

State held

Off

I/O

GPIO

State held

(1) Backup memory contains 32 bytes of register space in peripheral memory. See 表9-32 and 表9-54 for its memory allocation.

(2) The status shown for LPM4 applies to internal clocks only.

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9.4 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see 表 9-2).

The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

表9-2. Interrupt Sources, Flags, and Vectors

SYSTEM

INTERRUPT

WORD

ADDRESS

INTERRUPT SOURCE

INTERRUPT FLAG

PRIORITY

System Reset

Power up, Brownout, Supply supervisor

External reset RST

SVSHIFG

PMMRSTIFG

Watchdog time-out, key violation

FRAM uncorrectable bit error detection

Software POR, BOR

WDTIFG

PMMPORIFG, PMMBORIFG

SYSRSTIV

Reset

FFFEh

63, Highest

FLL unlock error

FLLUNLOCKIFG

System NMI

Vacant memory access

JTAG mailbox

FRAM access time error

FRAM bit error detection

VMAIFG

JMBINIFG, JMBOUTIFG

CBDIFG, UBDIFG

Nonmaskable

FFFCh

FFFAh

62

61

User NMI

External NMI

Oscillator fault

NMIIFG

OFIFG

Timer0_A3

Timer1_A3

Time2_A3

Timer2_A3

Timer3_A3

Timer0_B7

TA0CCR0 CCIFG0

Maskable

FFF8h

FFF6h

FFF4h

FFF2h

FFF0h

FFEEh

FFECh

FFEAh

FFE8h

60

59

58

57

56

55

54

53

52

TA0CCR1 CCIFG1, TA0CCR2 CCIFG2,

TA0IFG (TA0IV)

TA1CCR0 CCIFG0

TA1CCR1 CCIFG1, TA1CCR2 CCIFG2,

TA1IFG (TA1IV)

TA2CCR0 CCIFG0

TA2CCR1 CCIFG1, TA2CCR2 CCIFG2,

TA2IFG (TA2IV)

TA3CCR0 CCIFG0

TA3CCR1 CCIFG1, TA3CCR2 CCIFG2,

TA3IFG (TA3IV)

TB0CCR0 CCIFG0

TB0CCR1 CCIFG1, TB0CCR2 CCIFG2,

TB0CCR3 CCIFG3, TB0CCR4 CCIFG4,

TB0CCR5 CCIFG5, TB0CCR6 CCIFG6,

TB0IFG (TB0IV)

Timer0_B7

Maskable

FFE6h

51

RTC

RTCIFG

WDTIFG

Maskable

FFE4h

FFE2h

50

49

Watchdog timer interval mode

UCTXCPTIFG, UCSTTIFG, UCRXIFG,

UCTXIFG (UART mode)

UCRXIFG, UCTXIFG (SPI mode)

(UCA0IV)

eUSCI_A0 receive or transmit

eUSCI_A1 receive or transmit

Maskable

FFE0h

FFDEh

48

47

UCTXCPTIFG, UCSTTIFG, UCRXIFG,

UCTXIFG (UART mode)

UCRXIFG, UCTXIFG (SPI mode)

(UCA0IV)

UCB0RXIFG, UCB0TXIFG (SPI mode)

UCALIFG, UCNACKIFG, UCSTTIFG,

UCSTPIFG, UCRXIFG0, UCTXIFG0,

UCRXIFG1, UCTXIFG1, UCRXIFG2,

UCTXIFG2, UCRXIFG3, UCTXIFG3,

UCCNTIFG, UCBIT9IFG (I²C mode)

(UCB0IV)

eUSCI_B0 receive or transmit

Maskable

FFDCh

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PRIORITY

表9-2. Interrupt Sources, Flags, and Vectors (continued)

SYSTEM

INTERRUPT

WORD

ADDRESS

INTERRUPT SOURCE

INTERRUPT FLAG

UCB1RXIFG, UCB1TXIFG (SPI mode)

UCALIFG, UCNACKIFG, UCSTTIFG,

UCSTPIFG, UCRXIFG0, UCTXIFG0,

UCRXIFG1, UCTXIFG1, UCRXIFG2,

UCTXIFG2, UCRXIFG3, UCTXIFG3,

UCCNTIFG, UCBIT9IFG (I²C mode)

(UCB0IV)

eUSCI_B1 receive or transmit

Maskable

FFDAh

FFD8h

45

44

ADCIFG0, ADCINIFG, ADCLOIFG,

ADCHIIFG, ADCTOVIFG, ADCOVIFG

(ADCIV)

ADC

Maskable

P1

P2

P1IFG.0 to P1IFG.7 (P1IV)

P2IFG.0 to P2IFG.7 (P2IV)

P3IFG.0 to P2IFG.7 (P3IV)

P4IFG.0 to P4IFG.7 (P4IV)

P5IFG.0 to P5IFG.7 (P5IV)

P6IFG.0 to P6IFG.2 (P6IV)

CPIIFG, CPIFG (CP0IV)

Reserved

Maskable

FFD6h

FFD4h

43

42

P3

FFD2h

41

P4

FFD0h

40

39

P5

FFCEh

P6

FFCCh

38

eCOMP0

Reserved

FFCAh

37, Lowest

FFC6h–FF88h

表9-3. Signatures

SIGNATURE

BSL I2C Address⁽¹⁾

BSL Config

WORD ADDRESS

0FFA0h

0FF8Ah

0FF88h

0FF86h

0FF84h

0FF82h

0FF80h

BSL Config Signature

BSL Signature2

BSL Signature1

JTAG Signature2

JTAG Signature1

(1) 7-bit address BSL I²C interface

9.5 Bootloader (BSL)

The BSL lets users program the FRAM or RAM using either the UART serial interface or the I²C interface.

Access to the MCU memory through the BSL is protected by an user-defined password. Use of the BSL requires

four pins (see 表 9-4 and 表 9-5). The BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO

and TEST/SBWTCK pins. This device can support the blank device detection automatically to invoke the BSL

with bypass this special entry sequence for saving time and on board programmable. For the complete

description of the feature of the BSL, see the MSP430™ FRAM Devices Bootloader (BSL) User's Guide.

表9-4. UART BSL Pin Requirements and Functions

DEVICE SIGNAL

BSL FUNCTION

Entry sequence signal

Data transmit

RST/NMI/SBWTDIO

TEST/SBWTCK

P1.4

P1.5

VCC

VSS

Data receive

Power supply

Ground supply

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表9-5. I²C BSL Pin Requirements and Functions

DEVICE SIGNAL

BSL FUNCTION

RST/NMI/SBWTDIO

Entry sequence signal

Data transmit and receive

Clock

TEST/SBWTCK

P1.2

P1.3

VCC

VSS

Power supply

Ground supply

9.6 JTAG Standard Interface

The MSP low-power microcontrollers support the standard JTAG interface, which requires four signals for

sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin

enables the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with

MSP430 development tools and device programmers. 表 9-6 lists the JTAG pin requirements. For further details

on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide.

For details on using the JTAG interface, see MSP430 Programming With the JTAG Interface User's Guide.

表9-6. JTAG Pin Requirements and Function

DEVICE SIGNAL

DIRECTION

JTAG FUNCTION

JTAG clock input

JTAG state control

JTAG data input, TCLK input

JTAG data output

Enable JTAG pins

External reset

P1.4/.../TCK

IN

P1.5/.../TMS

P1.6/.../TDI/TCLK

P1.7/.../TDO

TEST/SBWTCK

RST/NMI/SBWTDIO

DVCC

IN

OUT

IN

Power supply

–

DVSS

Ground supply

–

9.7 Spy-Bi-Wire Interface (SBW)

The MSP low-power microcontrollers support the 2-wire SBW interface. SBW can be used to interface with MSP

development tools and device programmers. 表 9-7 lists the SBW interface pin requirements. For further details

on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide.

For details on using the SBW interface, see the MSP430 Programming With the JTAG Interface User's Guide.

表9-7. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL

TEST/SBWTCK

RST/NMI/SBWTDIO

DVCC

DIRECTION

SBW FUNCTION

Spy-Bi-Wire clock input

Spy-Bi-Wire data input and output

Power supply

IN

IN, OUT

–

DVSS

Ground supply

–

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9.8 FRAM

The FRAM can be programmed using the JTAG port, SBW, the BSL, or in-system by the CPU. Features of the

FRAM include:

• Byte and word access capability

• Programmable wait state generation

• Error correction coding (ECC)

9.9 Memory Protection

The device features memory protection for user access authority and write protection, including options to:

• Secure the whole memory map to prevent unauthorized access from JTAG port or BSL, by writing JTAG and

BSL signatures using the JTAG port, SBW, the BSL, or in-system by the CPU.

• Enable write protection to prevent unwanted write operation to FRAM contents by setting the control bits in

the System Configuration 0 register. For detailed information, see the SYS chapter in the MP430FR4xx and

MP430FR2xx Family User's Guide.

9.10 Peripherals

Peripherals are connected to the CPU through data, address, and control buses. All peripherals can be handled

by using all instructions in the memory map. For complete module description, see the MP430FR4xx and

MP430FR2xx Family User's Guide.

9.10.1 Power-Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM also

includes supply voltage supervisor (SVS) and brownout protection. The brownout reset circuit (BOR) is

implemented to provide the proper internal reset signal to the device during power on and power off. The SVS

circuitry detects if the supply voltage drops below a user-selectable safe level. SVS circuitry is available on the

primary supply.

The device contains two on-chip reference: 1.5 V for internal reference and 1.2 V for external reference.

The 1.5-V reference is internally connected to ADC channel 13. DVCC is internally connected to ADC channel

15. When DVCC is set as the reference voltage for ADC conversion, the DVCC can be easily represent as 方程

式1 by using ADC sampling 1.5-V reference without any external components support.

DVCC = (1023 × 1.5 V) ÷ 1.5-V reference ADC result

(1)

A 1.2-V reference voltage can be buffered, when EXTREFEN = 1 on PMMCTL2 register, and it can be output to

P1.4/../A1/VREF+ , meanwhile the ADC channel 1 can also be selected to monitor this voltage. For more

detailed information, see the MSP430FR4xx and MSP430FR2xx Family User's Guide.

9.10.2 Clock System (CS) and Clock Distribution

The clock system includes a 32-kHz crystal oscillator (XT1), an internal very-low-power low-frequency oscillator

(VLO), an integrated 32-kHz RC oscillator (REFO), an integrated internal digitally controlled oscillator (DCO) that

may use frequency-locked loop (FLL) locking with internal or external 32-kHz reference clock, and an on-chip

asynchronous high-speed clock (MODOSC). The clock system is designed for cost-effective designs with

minimal external components. A fail-safe mechanism is included for XT1. The clock system module offers the

following clock signals.

• Main Clock (MCLK): The system clock used by the CPU and all relevant peripherals accessed by the bus. All

clock sources except MODOSC can be selected as the source with a predivider of 1, 2, 4, 8, 16, 32, 64, or

128.

• Sub-Main Clock (SMCLK): The subsystem clock used by the peripheral modules. SMCLK derives from the

MCLK with a predivider of 1, 2, 4, or 8. This means SMCLK is always equal to or less than MCLK.

• Auxiliary Clock (ACLK): This clock is derived from the external XT1 clock, internal VLO or internal REFO

clock up to 40 kHz.

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All peripherals may have one or several clock sources depending on specific functionality. 表 9-8 lists the clock

distribution used in this device.

表9-8. Clock Distribution

CLOCK

SOURCE

SELECT

BITS

MCLK

SMCLK

ACLK

MODCLK

XT1CLK

VLOCLK

EXTERNAL PIN

Frequency

range

DC to

16 MHz

DC to

16 MHz

DC to 40 kHz 5 MHz ±10% DC to 40 kHz 10 kHz ±50%

–

CPU

N/A

Default

–

00b

–

10b

–

FRAM

RAM

–

N/A

–

CRC

N/A

–

MPY32

I/O

N/A

–

N/A

–

TA0

TASSEL

TBSSEL

UCSSEL

WDTSSEL

ADCSSEL

RTCSS

10b

01b

01b⁽¹⁾

11b

00b (TA0CLK pin)

00b (TA1CLK pin)

00b (TA2CLK pin)

00b (TA3CLK pin)

00b (TB0CLK pin)

00b (UCA0CLK pin)

00b (UCA1CLK pin)

00b (UCB0CLK pin)

00b (UCB1CLK pin)

TA1

10b

–

TA2

10b

11b

–

TA3

10b

–

TB0

10b

–

eUSCI_A0

eUSCI_A1

eUSCI_B0

eUSCI_B1

WDT

10b or 11b

00b

–

10b

–

ADC

10b or 11b

01b⁽¹⁾

–

RTC

11b

–

(1) Controlled by the RTCCKSEL bit in the SYSCFG2 register.

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SRAM

CRC

CPU

FRAM

I/O

eCOMP

MCLK

Timer_Bs

eUSCI_As

RTC

ADC

Timer_As

eUSCI_Bs

WDT

Clock System (CS)

SMCLK

ACLK

VLOCLK

MODCLK

Selected on SYSCFG2

XT1CLK

图9-1. Clock Distribution Block Diagram

9.10.3 General-Purpose Input/Output Port (I/O)

Up to 43 I/O ports are implemented.

• P1, P3, P4, and P5 implement 8 bits each. P2 implements 6 bits excluding the I/Os multiplexed with XIN and

XOUT. P6 implements 3 bits.

• All individual I/O bits are independently programmable.

• Any combination of input, output, and interrupt conditions is possible.

• Programmable pullup or pulldown on all ports.

• Edge-selectable interrupt and LPMx.5 wake-up input capability are available for all GPIOs (up to 43)

• Read and write access to port-control registers is supported by all instructions.

• Ports can be accessed byte-wise or word-wise as a pair.

Note

Configuration of digital I/Os after BOR reset

To prevent any cross currents during start-up of the device, all port pins are high-impedance with

Schmitt triggers and module functions disabled. To enable the I/O functions after a BOR reset, the

ports must be configured first and then the LOCKLPM5 bit must be cleared. For details, see the

Configuration After Reset section in the Digital I/O chapter of the MP430FR4xx and MP430FR2xx

Family User's Guide.

9.10.4 Watchdog Timer (WDT)

The primary function of the WDT module is to perform a controlled system restart after a software problem

occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed

in an application, the module can be configured as an interval timer and can generate interrupts at selected time

intervals. 表9-9 lists the system clocks that can be used to source the WDT.

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表9-9. WDT Clocks

NORMAL OPERATION

WDTSSEL

(WATCHDOG AND INTERVAL TIMER

MODE)

00

01

10

11

SMCLK

ACLK

VLOCLK

Reserved

9.10.5 System (SYS) Module

The SYS module handles many of the system functions within the device. These features include power-on reset

(POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector

generators, bootloader entry mechanisms, and configuration management (device descriptors). The SYS

module also includes a data exchange mechanism through SBW called a JTAG mailbox mail box that can be

used in the application. 表9-10 summarizes the interrupts that are managed by the SYS module.

表9-10. System Module Interrupt Vector Registers

INTERRUPT VECTOR

ADDRESS

INTERRUPT EVENT

VALUE

PRIORITY

REGISTER

No interrupt pending

Brownout (BOR)

00h

02h

Highest

RSTIFG RST/NMI (BOR)

PMMSWBOR software BOR (BOR)

LPMx.5 wakeup (BOR)

04h

06h

08h

Security violation (BOR)

Reserved

0Ah

0Ch

SVSHIFG SVSH event (BOR)

Reserved

0Eh

10h

SYSRSTIV, System Reset

015Eh

Reserved

12h

PMMSWPOR software POR (POR)

WDTIFG watchdog time-out (PUC)

WDTPW password violation (PUC)

FRCTLPW password violation (PUC)

Uncorrectable FRAM bit error detection

Peripheral area fetch (PUC)

PMMPW PMM password violation (PUC)

FLL unlock (PUC)

14h

16h

18h

1Ah

1Ch

1Eh

20h

24h

Reserved

22h, 26h to 3Eh

Lowest

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表9-10. System Module Interrupt Vector Registers (continued)

INTERRUPT VECTOR

REGISTER

ADDRESS

INTERRUPT EVENT

VALUE

PRIORITY

No interrupt pending

SVS low-power reset entry

Uncorrectable FRAM bit error detection

Reserved

00h

02h

Highest

04h

06h

Reserved

08h

Reserved

0Ah

Reserved

0Ch

SYSSNIV, System NMI

015Ch

Reserved

0Eh

Reserved

10h

VMAIFG vacant memory access

JMBINIFG JTAG mailbox input

JMBOUTIFG JTAG mailbox output

Correctable FRAM bit error detection

Reserved

12h

14h

16h

18h

1Ah to 1Eh

00h

Lowest

Highest

Lowest

No interrupt pending

NMIIFG NMI pin or SVS_Hevent

OFIFG oscillator fault

Reserved

02h

SYSUNIV, User NMI

015Ah

04h

06h to 1Eh

9.10.6 Cyclic Redundancy Check (CRC)

The 16-bit cyclic redundancy check (CRC) module produces a signature based on a sequence of data values

and can be used for data checking purposes. The CRC generation polynomial is compliant with CRC-16-CCITT

standard of x¹⁶+ x¹²+ x⁵+ 1.

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9.10.7 Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)

The eUSCI modules are used for serial data communications. The eUSCI_A module supports either UART or

SPI communications. The eUSCI_B module supports either SPI or I²C communications. Additionally, eUSCI_A

supports automatic baud-rate detection and IrDA. The eUSCI_A and eUSCI_B are connected either from P1 port

or P2 port, it can be selected from the USCIA0RMP or USCIBxRMP bits of SYSCFG2 and SYSCFG3. 表 9-11

lists the pin configurations that are required for each eUSCI mode.

表9-11. eUSCI Pin Configurations

PIN (PxSEL Selection)

UART

SPI

SIMO

SOMI

SCLK

STE

P1.4⁽¹⁾

TXD

P1.5⁽¹⁾

RXD

P1.6⁽¹⁾

–

P1.7⁽¹⁾

eUSCI_A0

eUSCI_A1

eUSCI_B0

PIN (PxSEL Selection)

UART

TXD

RXD

SPI

P5.2⁽²⁾

SIMO

SOMI

SCLK

STE

P5.1⁽²⁾

P5.0⁽²⁾

–

P4.7⁽²⁾

PIN (PxSEL Selection)

UART

TXD

RXD

SPI

P2.6

SIMO

SOMI

SCLK

STE

P2.5

P2.4

–

P3.1

PIN (PxSEL Selection)

P1.0⁽¹⁾

–

I²C

SPI

STE

–

P1.1⁽¹⁾

SCLK

SIMO

SOMI

SPI

P1.2⁽¹⁾

SDA

SCL

I²C

P1.3⁽¹⁾

PIN (PxSEL Selection)

P5.6⁽²⁾

STE

–

P5.5⁽²⁾

SCLK

SIMO

SOMI

SPI

P4.6⁽²⁾

SDA

SCL

I²C

P4.5⁽²⁾

PIN (PxSEL Selection)

P2.7⁽¹⁾

STE

–

P3.5⁽¹⁾

SCLK

SIMO

SOMI

SPI

P3.2⁽¹⁾

SDA

SCL

I²C

P3.6⁽¹⁾

eUSCI_B1

PIN (PxSEL Selection)

P5.4⁽²⁾

STE

–

P5.3⁽²⁾

SCLK

SIMO

SOMI

P4.4⁽²⁾

SDA

SCL

P4.3⁽²⁾

(1) This is the default functionality that can be remapped by the USCIBxRMP or USCIA0RMP bit of the

SYSCFG2 or SYCFG3 register. Only one selected port is valid at any time.

(2) This is the remapped functionality controlled by the USCIBxRMP or USCIA0RMP bit of the

SYSCFG2 or SYCFG3 register. Only one selected port is valid at any time.

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9.10.8 Timers (TA0, TA1, TA2, TA3 and TB0)

The TA0, TA1, TA2 and TA3 modules are 16-bit timers and counters with three capture/compare registers each.

Each timer supports multiple captures or compares, PWM outputs, and interval timing (see 表9-12 and 表9-13).

Each timer has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow

conditions and from each of the capture/compare registers. The CCR0 registers on both TA0 and TA2 are not

externally connected and can only be used for hardware period timing and interrupt generation. In Up mode,

they can be used to set the overflow value of the counter.

表9-12. Timer0_A0 Signal Connections

DEVICE INPUT

SIGNAL

MODULE INPUT

NAME

MODULE OUTPUT

SIGNAL

DEVICE OUTPUT

SIGNAL

PORT PIN

MODULE BLOCK

P1.0

TA0CLK

TACLK

ACLK

ACLK (internal)

SMCLK (internal)

VLO (internal)

ACLK (internal)

Timer

N/A

TA0

SMCLK

INCLK

CCI0A

Not used

Timer1_A1 CCI0B

input

VLO (internal)

CCI0B

CCR0

CCR1

DVSS

DVCC

TA0.1

GND

V_CC

P1.1

P1.2

CCI1A

TA0.1

Timer1_A1 CCI1B

input

RTC (internal)

CCI1B

TA1

TA2

DVSS

DVCC

TA0.2

GND

V_CC

CCI2A

TA0.2

Timer1_A1 INCLK

Timer1_A1 CCI2B

input,

N/A

CCI2B

CCR2

IR carrier input

DVSS

DVCC

GND

V_CC

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表9-13. Timer0_A1 Signal Connections

DEVICE INPUT

SIGNAL

MODULE INPUT

NAME

MODULE OUTPUT

SIGNAL

DEVICE OUTPUT

SIGNAL

PORT PIN

MODULE BLOCK

P1.6

TA1CLK

TACLK

ACLK

ACLK (internal)

SMCLK (internal)

Timer

N/A

TA0

TA1

TA2

SMCLK

Timer0_A3 CCR2B

output (internal)

INCLK

CCI0A

CCI0B

N/A

Not used

Timer0_A3 CCR0B

output (internal)

CCR0

CCR1

CCR2

DVSS

DVCC

TA1.1

GND

V_CC

P1.5

P1.4

CCI1A

TA1.1

Timer0_A3 CCR1B

output (internal)

CCI1B

To ADC trigger

DVSS

DVCC

TA1.2

GND

V_CC

CCI2A

TA1.2

Timer0_A3 CCR2B

output (internal)

CCI2B

IR coding input

DVSS

DVCC

GND

V_CC

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TA0

TA1

TA0CLK

ACLK

00

01

10

11

TA1CLK

ACLK

00

01

10

11

16-bit Counter

SMCLK

VLO

16-bit Counter

SMCLK

00

01

10

11

ACLK

VLO

TA0.0A

TA0.0B

00

01

10

11

CCR0

DVSS

DVCC

TA1.0A

TA1.0B

CCR0

DVSS

DVCC

P1.1

RTC

00

01

10

11

TA0.1A

TA0.1B

P1.1

P1.5

00

01

10

11

CCR1

DVSS

DVCC

TA1.1A

TA1.1B

P1.5

To ADC Trigger

CCR1

DVSS

DVCC

P1.2

00

01

10

11

TA0.2A

TA0.2B

P1.2

P1.4

00

01

10

11

CCR2

DVSS

DVCC

TA1.2A

TA1.2B

P1.4

CCR2

DVSS

DVCC

Coding

Carrier

Infrared

Logic (SYS)

P2.0/UCA0TXD/UCA0SIMO

UCA0TXD/UCA0SIMO

eUSCI_A0

Data

图9-2. TA0 and TA1 Signal Connections

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表9-14. Timer2_A3 and Timer3_A3 Signal Connections

DEVICE INPUT

SIGNAL

MODULE INPUT

NAME

MODULE OUTPUT

SIGNAL

DEVICE OUTPUT

SIGNAL

PORT PIN

MODULE BLOCK

P3.4

TA2CLK

ACLK (internal)

SMCLK (internal)

VLO (internal)

TA2.0

TACLK

ACLK

Timer

N/A

TA0

SMCLK

INCLK

CCI0A

P2.3

P3.3

P3.0

TA2.0

Timer3_A3 CCI0B

input

VLO (internal)

CCI0B

CCR0

CCR1

CCR2

DVSS

DVCC

TA2.1

GND

V_CC

CCI1A

TA2.1

Timer3_A3 CCI1B

input

RTC (internal)

CCI1B

TA1

TA2

DVSS

DVCC

TA2.2

GND

V_CC

CCI2A

TA2.2

Timer3_A3 CCI2B

input

N/A

CCI2B

DVSS

DVCC

GND

V_CC

P4.2

P4.1

P4.0

P3.7

TA3CLK

TACLK

ACLK

ACLK (internal)

SMCLK (internal)

Timer

CCR0

CCR1

CCR2

N/A

TA0

TA1

TA2

SMCLK

Timer2_A3 CCR2B

output (internal)

INCLK

CCI0A

CCI0B

TA3.0

Timer2_A3 CCR0B

output (internal)

Timer3_B0 CCI0B

input

DVSS

DVCC

TA3.1

GND

V_CC

CCI1A

TA3.1

Timer2_A3 CCR1B

output (internal)

Timer3_B0 CCI1B

input

CCI1B

DVSS

DVCC

TA3.2

GND

V_CC

CCI2A

TA3.2

Timer2_A3 CCR2B

output (internal)

Timer3_B0 CCI2B

input

CCI2B

DVSS

DVCC

GND

V_CC

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表9-15. Timer0_B7 Signal Connections

DEVICE INPUT

SIGNAL

MODULE INPUT

NAME

MODULE OUTPUT

SIGNAL

DEVICE OUTPUT

SIGNAL

PORT PIN

MODULE BLOCK

P6.1

TB0CLK

ACLK (internal)

SMCLK (internal)

N/A

TBCLK

ACLK

Timer

N/A

SMCLK

INCLK

CCI0A

P6.2

P4.7

P5.0

TB0.0

TB0.1

TB0.2

Timer3_A3 CCI0B

input (internal)

CCI0B

CCR0

CCR1

CCR2

TB0

DVSS

DVCC

TB0.1

GND

V_CC

CCI1A

Timer3_A3 CCI1B

input (internal)

CCI1B

TB1

TB2

DVSS

DVCC

TB0.2

GND

V_CC

CCI2A

Timer3_A3 CCI2B

input (internal)

CCI2B

DVSS

DVCC

TB0.3

N/A

GND

V_CC

P5.1

P5.2

P4.3

P4.4

CCI1A

CCI1B

GND

V_CC

TB0.3

TB0.4

TB0.5

TB0.6

CCR3

CCR4

CCR5

CCR6

TB3

TB4

TB5

TB6

DVSS

DVCC

TB0.4

N/A

CCI1A

CCI1B

GND

V_CC

DVSS

DVCC

TB0.5

N/A

CCI1A

CCI1B

GND

V_CC

DVSS

DVCC

TB0.6

N/A

CCI1A

CCI1B

GND

V_CC

DVSS

DVCC

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TA2

TA3

TB0

TA2CLK

ACLK

00

01

10

11

TA3CLK

ACLK

00

01

10

11

TB0CLK

ACLK

00

01

10

11

16-bit Counter

00

01

10

11

P5.1

SMCLK

VLO

16-bit Counter

TB0.3A

TB0.3B

P5.1

P5.2

P5.3

SMCLK

CCR3

CCR4

CCR5

DVSS

DVCC

00

01

10

11

P2.3

VLO

TA2.0A

TA2.0B

P4.1

00

01

10

11

P2.3

P3.3

P3.0

CCR0

P5.2

00

01

10

11

DVSS

DVCC

TA3.0A

TA3.0B

P6.2

00

01

10

11

P4.1

P4.0

P3.7

CCR0

TB0.4A

TB0.4B

DVSS

DVCC

TB0.0A

TB0.0B

P6.2

CCR0

CCR1

CCR2

DVSS

DVCC

DVSS

DVCC

TB0.2

P3.3

RTC

00

01

10

11

TA2.1A

TA2.1B

P4.0

00

01

10

11

CCR1

P5.3

00

01

10

11

DVSS

DVCC

TA3.1A

TA3.1B

P4.7

00

01

10

11

CCR1

TB0.5A

TB0.5B

DVSS

DVCC

TB0.1A

TB0.1B

P4.7

DVSS

DVCC

TB0.1

DVSS

DVCC

P3.0

00

01

10

11

TA2.2A

TA2.2B

P3.7

00

01

10

11

CCR2

P5.4

00

01

10

11

DVSS

DVCC

TA3.2A

TA3.2B

P5.0

00

01

10

11

CCR2

TB0.5A

TB0.5B

P5.4

DVSS

DVCC

TB0.2A

TB0.2B

P5.0

CCR6

DVSS

DVCC

DVSS

DVCC

TB0.0

TBOUTH

0

1

TB0TRG

COMP0OUT

TB0TRG

图9-3. TA2, TA3 and TB0 Signal Connections

表9-16. TA2 and TA3 Pin Configurations of Remap Functionality

DEVICE INPUT/OUTPUT

SIGNAL

PIN (PxSEL Selection)

P3.4⁽¹⁾

P2.3⁽¹⁾

P3.3⁽¹⁾

P3.0⁽¹⁾

TA2CLK

TA2.0

TA2.1

TA2.2

TA2

DEVICE INPUT/OUTPUT

SIGNAL

PIN (PxSEL Selection)

P5.5⁽²⁾

P5.6⁽²⁾

P5.7⁽²⁾

P6.0⁽²⁾

TA2CLK

TA2.0

TA2.1

TA2.2

DEVICE INPUT/OUTPUT

SIGNAL

PIN (PxSEL Selection)

P4.2⁽¹⁾

P4.1⁽¹⁾

P4.0⁽¹⁾

P3.7⁽¹⁾

TA3CLK

TA3.0

TA3.1

TA3.2

TA3

DEVICE INPUT/OUTPUT

SIGNAL

PIN (PxSEL Selection)

P5.4⁽²⁾

P5.3⁽²⁾

P4.6⁽²⁾

P4.5⁽²⁾

TA3CLK

TA3.0

TA3.1

TA3.2

(1) This is the default functionality that can be remapped by the TAxRMP bit of the SYSCFG3 register.

Only one selected port is valid at any time.

(2) This is the remapped functionality controlled by the TAxRMP bit of the SYSCFG3 register. Only one

selected port is valid at any time.

The interconnection of Timer0_A3 and Timer1_A3 can be used to modulate the eUSCI_A pin of UCA0TXD/

UCA0SIMO in either ASK or FSK mode, with which a user can easily acquire a modulated infrared command for

directly driving an external IR diode. The IR functions are fully controlled by SYS configuration register 1

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including IREN (enable), IRPSEL (polarity select), IRMSEL (mode select), IRDSSEL (data select), and IRDATA

(data) bits. For more information, see the SYS chapter in the MP430FR4xx and MP430FR2xx Family User's

Guide.

The Timer_B module feature the function to put Timer_B all outputs into a high impedance state when the

selected source is triggered. The source can be selected from external pin or internal of the device, it is

controlled by TBxTRG in SYS. For more information, see the SYS chapter in the MP430FR4xx and

MP430FR2xx Family User's Guide.

表9-17 lists the Timer_B high-impedance trigger source selections.

表9-17. TB0OUTH Selection

TB0OUTH TRIGGER SOURCE

TB0TRGSEL

Timer_B PAD OUTPUT HIGH IMPEDANCE

SELECTION

eCOMP0 output (internal)

P3.5

TB0TRGSEL = 0

TB0TRGSEL= 1

P6.2, P4.7, P5.0, P5.1, P5.2, P4.3, P4.4

9.10.9 Hardware Multiplier (MPY)

The multiplication operation is supported by a dedicated peripheral module. The module performs operations

with 32-, 24-, 16-, and 8-bit operands. The MPY module supports signed multiplication, unsigned multiplication,

signed multiply-and-accumulate, and unsigned multiply-and-accumulate operations.

9.10.10 Backup Memory (BAKMEM)

The BAKMEM supports data retention during LPM3.5. This device provides up to 32 bytes that are retained

during LPM3.5.

9.10.11 Real-Time Clock (RTC)

The RTC is a 16-bit modulo counter that is functional in AM, LPM0, LPM3, and LPM3.5. This module may

periodically wake up the CPU from LPM0, LPM3 and LPM3.5 based on timing from a low-power clock source

such as the XT1 and VLO clocks. RTC also can be sourced from ACLK controlled by RTCCKSEL in SYSCFG2.

In AM, RTC can be driven by SMCLK to generate high-frequency timing events and interrupts. The RTC

overflow events trigger:

• Timer0_B3 CCI1B

• ADC conversion trigger when ADCSHSx bits are set as 01b

表9-18. RTC Clock Source

RTCSS

CLOCK SOURCE

00

Reserved

01

SMCLK, or ACLK is selected⁽¹⁾

XT1CLK

10

11

VLOCLK

(1) Controlled by RTCCLK bit of SYSCFG2 register.

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9.10.12 12-Bit Analog-to-Digital Converter (ADC)

The 12-bit ADC module supports fast 12-bit analog-to-digital conversions with single-ended input. The module

implements a 12-bit SAR core, sample select control, reference generator and a conversion result buffer. A

window comparator with a lower and upper limits allows CPU-independent result monitoring with three window

comparator interrupt flags.

The ADC supports 12 external inputs and four internal inputs (see 表9-19).

表9-19. ADC Channel Connections

ADCINCHx

ADC CHANNELS

EXTERNAL PIN OUTPUT

0

1

A0/Veref+

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P4.3

P4.4

P5.3

P5.4

N/A

A1/

2

A2/Veref-

3

A3

4

A4⁽¹⁾

5

A5

6

A6

7

A7

8

A8

9

A9

10

11

12

13

14

15

A10

A11

On-chip temperature sensor

Internal shared reference voltage (1.5, 2.0, or 2.5-V)

N/A

DVSS

DVCC

N/A

(1) When A4 is used, the PMM 1.2-V reference voltage can be output to this pin by setting the PMM

control register. The 1.2-V voltage can be measured by channel A4.

The analog-to-digital conversion can be started by software or a hardware trigger. 表 9-20 shows the trigger

sources that are available.

表9-20. ADC Trigger Signal Connections

ADCSHSx

TRIGGER SOURCE

BINARY

DECIMAL

00

01

10

11

0

1

2

3

ADCSC bit (software trigger)

RTC event

TA1.1B

eCOMP0 COUT

9.10.13 eCOMP0

This device features one enhanced comparator. The enhanced comparator is an analog voltage comparator with

a built-in 6-bit DAC as an internal voltage reference. The integrated 6-bit DAC can be set to 64 steps for the

comparator reference voltage. This module has 4-level programmable hysteresis and configurable power

modes: high-power and low-power modes.

The eCOMP0 supports a propagation delay up to 1 µs in high-power mode. In low-power mode, eCOMP0

supports 3.2-µs delay with 1.5-µA leakage at room temperature, which can be an ideal wake-up source in LPM3

for a voltage monitor.

eCOMP0 contains a programmable 6-bit DAC that can use the internal shared reference (1.5 V, 2.0 V, or 2.5 V)

for a high-precision comparison threshold. In addition to the internal shared reference, a low-power 1.2‑V

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reference is fixed at channel 2 of both the inverting and noninverting paths and allows the DAC to be turned off

to reduce power consumption.

The eCOMP0 supports external inputs and internal inputs (see 表9-21) and outputs (see 表9-22)

表9-21. eCOMP0 Input Channel Connections

CPPSEL OR

eCOMP0 CHANNELS

CPNSEL

000

001

010

011

100

101

110

P1.1/.../COMP0.0

P2.2/.../COMP0.1

Low-power 1.2-V reference

P5.7/.../COMP0.2

P6.0/.../COMP0.3

N/A

eCOMP0 6-bit DAC

表9-22. eCOMP0 Output Channel Connections

ECOMP0 OUT

EXTERNAL PINOUT, MODULE

1

2

P3.4

TB0 (TB0OUTH), TB1 (TB1OUTH), ADC trigger

9.10.14 Embedded Emulation Module (EEM)

The EEM supports real-time in-system debugging. The EEM on these devices has the following features:

• Three hardware triggers or breakpoints on memory access

• One hardware trigger or breakpoint on CPU register write access

• Up to four hardware triggers can be combined to form complex triggers or breakpoints

• One cycle counter

• Clock control on module level

• EEM version: S

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9.11 Input/Output Diagrams

图9-4 shows the overall port diagram.

From analog modules

PxREN.x

PxDIR.x

00

01

From Module1

From Module2

10

11

2 bit

DVSS

DVCC

0

1

PxSEL.x= 11

00

01

PxOUT.x

From Module1

From Module2

DVSS

10

11

2 bit

PxSEL.x

EN

D

To module

PxIN.x

PxIE.x

Bus

Keeper

Px Interrupt

D

S

Q

PxIFG.x

Edge

Select

PxIES.x

From JTAG

To JTAG

NOTE: For details on the specific analog modules, digital function modules, interrupts, and JTAG, see the Port Pin Functions table.

图9-4. Port Input/Output With Schmitt Trigger

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9.11.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger

表9-23 summarizes the selection of the pin functions.

表9-23. Port P1 (P1.0 to P1.7) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME (P1.x)

x

FUNCTION

P1DIR.x

P1SELx

00

JTAG

P1.0 (I/O)

UCB0STE

TA0CLK

I: 0; O: 1

0

X

01

P1.0/UCB0STE/TA0CLK/A0/Veref+

0

1

0

10

0

A0,Veref+

P1.1 (I/O)

UCB0CLK

TA0.CCI1A

TA0.1

X

11

N/A

0

I: 0; O: 1

00

X

01

0

P1.1/UCB0CLK/TA0.1/COMP0.0/A1

0

10

0

1

A1, COMP0.0

P1.2 (I/O)

UCB0SIMO/UCB0SDA

TA0.CCI2A

TA0.2

X

11

00

01

N/A

0

I: 0; O: 1

X

0

P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref-

P1.3/UCB0SOMI/UCB0SCL/MCLK/A3

2

3

0

10

0

1

A2, Veref-

P1.3 (I/O)

UCB0SOMI/UCB0SCL

MCLK

X

11

00

01

10

11

00

01

N/A

I: 0; O: 1

0

X

1

0

A3

X

N/A

P1.4 (I/O)

UCA0TXD/UCA0SIMO

TA1.CCI2A

TA1.2

I: 0; O: 1

Disabled

X

0

P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+

4

10

Disabled

1

A4, VREF+

JTAG TCK

P1.5 (I/O)

UCA0RXD/UCA0SOMI

TA1.CCI1A

TA1.1

X

11

X

Disabled

TCK

X

I: 0; O: 1

00

01

Disabled

X

0

P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5

5

10

Disabled

1

A5

X

11

X

Disabled

TMS

JTAG TMS

P1.6 (I/O)

UCA0CLK

TA1CLK

X

I: 0; O: 1

00

01

10

11

X

Disabled

TDI/TCLK

Disabled

TDO

X

P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6

6

7

0

A6

X

JTAG TDI/TCLK

P1.7 (I/O)

UCA0STE

SMCLK

X

I: 0; O: 1

00

01

10

11

X

1

P1.7/UCA0STE/SMCLK/TDO/A7

(1) X = don't care

A7

X

JTAG TDO

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9.11.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger

表9-24 summarizes the selection of the pin functions.

表9-24. Port P2 (P2.0 to P2.7) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME (P2.x)

x

0

1

FUNCTION

P2DIR.x

P2SELx

00

P2.0 (I/O)

XOUT

I: 0; O: 1

P2.0/XOUT

P2.1/XIN

X

01

P2.1 (I/O)

XIN

I: 0; O: 1

00

X

01

P2.2 (I/O)

ACLK

I: 0; O: 1

00

P2.2/ACLK/COMP0.1

P2.3/TA2.0

2

3

1

10

COMP0.1

P2.3 (I/O)

TA2.CCI0A

TA2.0

X

11

I: 0; O: 1

00

0

01

1

P2.4 (I/O)

UCA1CLK

P2.5 (I/O)

I: 0; O: 1

00

01

00

01

00

01

0

P2.4/UCA1CLK

4

5

6

7

X

I: 0; O: 1

P2.5/UCA1RXD/UCA1SOMI

P2.6/UCA1TXD/UCA1SIMO

UCA1RXD/UCA1SOMI

P2.6 (I/O)

X

I: 0; O: 1

X

UCA1TXD/UCA1SIMO

P2.7 (I/O)

I: 0; O: 1

X

P2.7/UCB1STE

UCB1STE

01

(1) X = don't care

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9.11.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger

表9-25 summarizes the selection of the pin functions.

表9-25. Port P3 (P3.0 to P3.7) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME (P3.x)

x

FUNCTION

P3DIR.x

P3SEL.x

filter9

I: 0; O: 1

00

P3.0/TA2.2

0

TA2.CCI2A

TA2.2

0

01

1

P3.1 (I/O)

UCA1STE

P3.2 (I/O)

UCB1SIMO/UCB1SDA

P3.3 (I/O)

TA2.CCI1A

TA2.1

I: 0; O: 1

00

01

00

01

00

P3.1/UCA1STE

1

2

X

I: 0; O: 1

P3.2/UCB1SIMO/UCB1SDA

X

I: 0; O: 1

P3.3/TA2.1

3

4

0

01

1

P3.4 (I/O)

TA2CLK

I: 0; O: 1

00

01

10

00

01

10

00

01

00

P3.4/TA2CLK/COMP0OUT

0

COMP0OUT

P3.5 (I/O)

UCB1CLK

TB0TRG

1

I: 0; O: 1

P3.5/UCB1CLK/TB0TRG

5

6

7

X

0

P3.6 (I/O)

UCB1SOMI/UCB1SCL

P3.7 (I/O)

TA3.CCI2A

TA3.2

I: 0; O: 1

P3.6/UCB1SOMI/UCB1SCL

X

I: 0; O: 1

P3.7/TA3.2

0

1

01

(1) X = don't care

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9.11.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger

表9-26 summarizes the selection of the pin functions.

表9-26. Port P4 (P4.0 to P4.7) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME (P4.x)

x

FUNCTION

P4DIR.x

P4SEL.x

P4.0 (I/O)

I: 0; O: 1

00

P4.0/TA3.1

0

TA3.CCI1A

TA3.1

0

01

00

01

1

P4.1 (I/O)

TA3.CCI0A

TA3.0

I: 0; O: 1

P4.1/TA3.0

1

2

0

1

P4.2 (I/O)

TA3CLK

I: 0; O: 1

00

01

00

01

P4.2/TA3CLK

0

P4.3 (I/O)

UCB1SOMI/UCB1SCL

TB0.CCI5A

TB0.5

I: 0; O: 1

X

P4.3/UCB1SOMI/UCB1SCL/TB0.5/A8

P4.4/UCB1SIMO/UCB1SDA/TB0.6/A9

3

4

0

10

1

A8

X

11

00

01

P3.4 (I/O)

UCB1SIMO/UCB1SDA

TB0.CCI6A

TB0.6

I: 0; O: 1

X

0

10

1

A9

X

11

00

01

P4.5 (I/O)

UCB0SOMI/UCB0SCL

TA3.CCI2A

TA3.2

I: 0; O: 1

X

P4.5/UCB0SOMI/UCB0SCL/TA3.2

P4.6/UCB0SIMO/UCB0SDA/TA3.1

5

6

7

0

10

1

P4.6 (I/O)

UCB0SIMO/UCB0SDA

TA3.CCI1A

TA3.1

I: 0; O: 1

00

01

X

0

10

1

P4.7 (I/O)

UCA0STE

TB0.CCI1A

TB0.1

I: 0; O: 1

00

01

X

0

1

P4.7/UCA0STE/TB0.1

(1) X = don't care

10

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9.11.5 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger

表9-27 summarizes the selection of the pin functions.

表9-27. Port P5 (P5.0 to P5.7) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

P5SEL.x

P5.0 (I/O)

UCA0CLK

TB0.CCI2A

TB0.2

I: 0; O: 1

00

01

X

P5.0/UCA0CLK/TB0.2

0

10

1

P5.1 (I/O)

I: 0; O: 1

00

01

UCA0RXD/UCA0SOMI

TB0.CCI3A

TB0.3

X

P5.1/UCA0RXD/UCA0SOMI/TB0.3

P5.2/UCA0TXD/UCA0SIMO/TB0.4

1

2

0

10

1

P5.2 (I/O)

UCA0TXD/UCA0SIMO

TB0.CCI4A

TB0.4

I: 0; O: 1

00

01

X

0

10

1

P5.3 (I/O)

UCB1CLK

TA3.CCI0A

TA3.0

I: 0; O: 1

00

01

X

P5.3/UCB1CLK/TA3.0/A10

3

0

10

1

A10

X

11

00

01

10

11

00

01

10

00

01

P5.4 (I/O)

UCB1STE

TA3CLK

I: 0; O: 1

X

P5.4/UCB1STE/TA3CLK/A11

P5.5/UCB0CLK/TA2CLK

P5.6/UCB0STE/TA2.0

4

5

6

0

A11

X

P5.5 (I/O)

UCB0CLK

TA2CLK

I: 0; O: 1

X

0

P5.6 (I/O)

UCB0STE

TA2.CCI0A

TA2.0

I: 0; O: 1

X

0

10

00

01

11

1

P5.7 (I/O)

TA2.CCI1A

TA2.1

I: 0; O: 1

0

1

X

P5.7/TA2.1/COMP0.2

(1) X = don't care

7

COMP0.2

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9.11.6 Port P6 (P6.0 to P6.2) Input/Output With Schmitt Trigger

表9-28 summarizes the selection of the pin functions.

表9-28. Port P6 (P6.0 to P6.2) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME (P6.x)

x

FUNCTION

P6DIR.x

P6SEL.x

P6.0 (I/O)

TA2.CCI2A

TA2.2

I: 0; O: 1

00

0

P6.0/TA2.2/COMP0.3

0

01

1

COMP0.3

P6.1 (I/O)

TB0CLK

P6.2 (I/O)

TB0.CCI0A

TB0.0

X

11

00

01

00

I: 0; O: 1

P6.1/TB0CLK

1

2

0

I: 0; O: 1

P6.2/TB0.0

0

1

01

(1) X = don't care

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9.12 Device Descriptors

表9-29 lists the Device IDs. 表9-30 lists the contents of the device descriptor tag-length-value (TLV) structure.

表9-29. Device IDs

DEVICE ID

DEVICE

1A05h

1A04h

2Ah

MSP430FR2476

MSP430FR2475

83h

2Bh

表9-30. Device Descriptors

DESCRIPTION

ADDRESS

1A00h

1A01h

1A02h

1A03h

1A04h

1A05h

1A06h

1A07h

1A08h

1A09h

1A0Ah

1A0Bh

1A0Ch

1A0Dh

1A0Eh

1A0Fh

1A10h

1A11h

1A12h

1A13h

VALUE

06h

Info length

CRC length

06h

Per unit

CRC value⁽¹⁾

Information block

Device ID

See 表9-29

Hardware revision

Firmware revision

Die record tag

Per unit

08h

Die record length

0Ah

Per unit

Lot wafer ID

Die record

Die X position

Die Y position

Test result

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表9-30. Device Descriptors (continued)

DESCRIPTION

ADDRESS

1A14h

1A15h

1A16h

1A17h

1A18h

1A19h

1A1Ah

1A1Bh

1A1Ch

1A1Dh

1A1Eh

1A1Fh

1A20h

1A21h

1A22h

1A23h

1A24h

1A25h

1A26h

1A27h

1A28h

1A29h

1A2Ah

1A2Bh

1A2Ch

1A2Dh

1A2Eh

1A2Fh

1A30h

1A31h

VALUE

11h

ADC calibration tag

ADC calibration length

ADC gain factor⁽³⁾

10h

Per unit

12h

ADC offset⁽⁴⁾

ADC internal shared 1.5-V reference, temperature sensor 30°C

ADC internal shared 1.5-V reference, temperature sensor 105°C

ADC internal shared 2.0-V reference, temperature sensor 30°C

ADC internal shared 2.0-V reference, temperature sensor 105°C

ADC internal shared 2.5-V reference, temperature sensor 30°C

ADC internal shared 2.5-V reference, temperature sensor 105°C

ADC calibration

Internal shared reference Calibration tag

Internal shared reference Calibration length

0Ah

Per unit

Internal shared 1.5-V reference factor

Internal shared 2.0-V reference factor

Reference and DCO

calibration

Internal shared 2.5-V reference factor

DCO tap settings for 16 MHz, temperature 30°C

DCO tap settings for 24 MHz, temperature 30°C ⁽²⁾

(1) CRC value covers the checksum from 0x1A04h to 0x1AF7h by applying CRC-CCITT-16 polynomial of x¹⁶+ x¹²+ x⁵+ 1.

(2) This value can be directly loaded into the DCO bits in the CSCTL0 register to get an accurate 24-MHz frequency at room temperature,

especially when MCU exits from LPM3 and below. TI also suggests to use a predivider to decrease the frequency if the temperature

drift might result an overshoot faster than 24 MHz.

(3) ADC gain: the gain correction factor is measured at 2.4 V and room temperature using ADCSREFx = 0x7, an external reference

without internal buffer. V_R+= V_eref+, V_R-= V_eref-. Other settings can result in different factors.

(4) ADC offset: the offset correction factor is measured at 2.4 V and room temperature using ADCSREFx = 0x7, an external reference

without internal buffer. V_R+= V_eref+, V_R-= V_eref-. Other settings can result in different factors

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9.13 Memory

9.13.1 Memory Organization

表9-31 summarizes the memory organization of the devices.

表9-31. Memory Organization

ACCESS

MSP430FR2476

MSP430FR2475

1KB

Bootloader (BSL2) memory (ROM)

Read only

FFFFFh to FFC00h

Memory (FRAM)

Main: interrupt vectors and signatures

Main: code memory

64KB

FFFFh to FF80h

17FFFh to 8000h

32KB

FFFFh to FF80h

FFFFh to 8000h

Read/Write

(Optional Write Protect)⁽¹⁾

8KB

3FFFh to 2000h

6KB

37FFh to 2000h

RAM

Read/Write

512 bytes

19FFh to 1800h

512 bytes

19FFh to 1800h

Information memory (FRAM)

Bootloader (BSL1) memory (ROM)

Peripherals

(Optional Write Protect)⁽²⁾

2KB

17FFh to 1000h

2KB

17FFh to 1000h

Read only

Read/Write

Read only

4KB

0FFFh to 0020h

4KB

0FFFh to 0020h

26 bytes

001Fh to 0006h

26 bytes

001Fh to 0006h

Tiny RAM

6 bytes

0005h to 0000h

6 bytes

0005h to 0000h

Reserved⁽³⁾

(1) The Program FRAM can be write protected by setting PFWP bit in SYSCFG0 register. See the SYS chapter in the MP430FR4xx and

MP430FR2xx Family User's Guide for more details

(2) The Information FRAM can be write protected by setting DFWP bit in SYSCFG0 register. See the SYS chapter in the MP430FR4xx

and MP430FR2xx Family User's Guide for more details

(3) Read as: D032h at 00h (Opcode: BIS.W LPM4, SR), 00F0h at 02h (Opcode: BIS.W LPM4, SR), 3FFFh at 04h (Opcode: JMP$)

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9.13.2 Peripheral File Map

表9-32 lists the available peripherals and the register base address for each.

表9-32. Peripherals Summary

MODULE NAME

Special Functions (see 表9-33)

BASE ADDRESS

0100h

0120h

0140h

0180h

01A0h

01C0h

01CCh

0200h

0220h

0240h

0300h

0380h

03C0h

0400h

0440h

0480h

04C0h

0500h

0520h

0540h

0580h

0660h

0700h

08E0h

SIZE

0010h

0020h

0040h

0020h

0010h

0008h

0002h

0020h

0010h

0030h

0020h

0030h

0020h

0040h

0020h

PMM (see 表9-34)

SYS (see 表9-35)

CS (see 表9-36)

FRAM (see 表9-37)

CRC (see 表9-38)

WDT (see 表9-39)

Port P1, P2 (see 表9-40)

Port P3, P4 (see 表9-41)

Port P5, P6 (see 表9-42)

RTC (see 表9-43)

Timer0_A3 (see 表9-44)

Timer1_A3 (see 表9-45)

Timer2_A3 (see 表9-46)

Timer3_A3 (see 表9-47)

Timer0_B7 (see 表9-48)

MPY32 (see 表9-49)

eUSCI_A0 (see 表9-50)

eUSCI_A1 (see 表9-51)

eUSCI_B0 (see 表9-52)

eUSCI_B1 (see 表9-53)

Backup Memory (see 表9-54)

ADC (see 表9-55)

eCOMP0 (see 表9-56)

表9-33. Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION

ACRONYM

OFFSET

00h

SFR interrupt enable

SFR interrupt flag

SFRIE1

SFRIFG1

SFRRPCR

02h

SFR reset pin control

04h

表9-34. PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION

ACRONYM

PMMCTL0

PMMCTL1

PMMCTL2

PMMIFG

OFFSET

00h

PMM control 0

PMM control 1

PMM control 2

PMM interrupt flags

PM5 control 0

02h

04h

0Ah

PM5CTL0

10h

表9-35. SYS Registers (Base Address: 0140h)

REGISTER DESCRIPTION

ACRONYM

OFFSET

System control

SYSCTL

00h

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表9-35. SYS Registers (Base Address: 0140h) (continued)

REGISTER DESCRIPTION

ACRONYM

SYSBSLC

SYSJMBC

SYSJMBI0

SYSJMBI1

SYSJMBO0

SYSJMBO1

SYSBERRIV

SYSUNIV

OFFSET

Bootloader configuration area

02h

06h

08h

0Ah

0Ch

0Eh

18h

1Ah

1Ch

1Eh

20h

22h

24h

26h

JTAG mailbox control

JTAG mailbox input 0

JTAG mailbox input 1

JTAG mailbox output 0

JTAG mailbox output 1

Bus error vector generator

User NMI vector generator

System NMI vector generator

Reset vector generator

System configuration 0

System configuration 1

System configuration 2

System configuration 3

SYSSNIV

SYSRSTIV

SYSCFG0

SYSCFG1

SYSCFG2

SYSCFG3

表9-36. CS Registers (Base Address: 0180h)

REGISTER DESCRIPTION

ACRONYM

CSCTL0

CSCTL1

CSCTL2

CSCTL3

CSCTL4

CSCTL5

CSCTL6

CSCTL7

CSCTL8

OFFSET

00h

CS control 0

CS control 1

CS control 2

CS control 3

CS control 4

CS control 5

CS control 6

CS control 7

CS control 8

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

表9-37. FRAM Registers (Base Address: 01A0h)

REGISTER DESCRIPTION

ACRONYM

OFFSET

00h

FRAM control 0

General control 0

General control 1

FRCTL0

GCCTL0

GCCTL1

04h

06h

表9-38. CRC Registers (Base Address: 01C0h)

REGISTER DESCRIPTION

ACRONYM

OFFSET

00h

CRC data input

CRC16DI

CRC data input reverse byte

CRC initialization and result

CRC result reverse byte

CRCDIRB

CRCINIRES

CRCRESR

02h

04h

06h

表9-39. WDT Registers (Base Address: 01CCh)

REGISTER DESCRIPTION

ACRONYM

OFFSET

Watchdog timer control

WDTCTL

00h

表9-40. Port P1, P2 Registers (Base Address: 0200h)

REGISTER DESCRIPTION

ACRONYM

OFFSET

Port P1 input

P1IN

00h

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表9-40. Port P1, P2 Registers (Base Address: 0200h) (continued)

REGISTER DESCRIPTION

ACRONYM

P1OUT

P1DIR

OFFSET

02h

Port P1 output

Port P1 direction

04h

Port P1 pulling enable

Port P1 selection 0

P1REN

P1SEL0

P1SEL1

P1IV

06h

0Ah

0Ch

0Eh

16h

Port P1 selection 1

Port P1 interrupt vector word

Port P1 complement selection

Port P1 interrupt edge select

Port P1 interrupt enable

Port P1 interrupt flag

P1SELC

P1IES

18h

P1IE

1Ah

1Ch

P1IFG

Port P2 input

P2IN

P2OUT

P2DIR

P2REN

P2SEL0

P2SEL1

P2IV

01h

03h

05h

07h

0Bh

0Dh

1Eh

17h

19h

1Bh

1Dh

Port P2 output

Port P2 direction

Port P2 pulling enable

Port P2 selection 0

Port P2 selection 1

Port P2 interrupt vector word

Port P2 complement selection

Port P2 interrupt edge select

Port P2 interrupt enable

Port P2 interrupt flag

P2SELC

P2IES

P2IE

P2IFG

表9-41. Port P3, P4 Registers (Base Address: 0220h)

REGISTER DESCRIPTION

ACRONYM

OFFSET

00h

Port P3 input

P3IN

Port P3 output

P3OUT

P3DIR

P3REN

P3SEL0

P3SEL1

P3IV

02h

Port P3 direction

04h

Port P3 pulling enable

Port P3 selection 0

06h

0Ah

0Ch

0Eh

16h

Port P3 selection 1

Port P3 interrupt vector word

Port P3 complement selection

Port P3 interrupt edge select

Port P3 interrupt enable

Port P3 interrupt flag

P3SELC

P3IES

18h

P3IE

1Ah

1Ch

P3IFG

Port P4 input

P4IN

P4OUT

P4DIR

P4REN

P4SEL0

P4SEL1

P4IV

01h

03h

05h

07h

0Bh

0Dh

1Eh

17h

19h

1Bh

Port P4 output

Port P4 direction

Port P4 pulling enable

Port P4 selection 0

Port P4 selection 1

Port P4 interrupt vector word

Port P4 complement selection

Port P4 interrupt edge select

Port P4 interrupt enable

P4SELC

P4IES

P4IE

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表9-41. Port P3, P4 Registers (Base Address: 0220h) (continued)

REGISTER DESCRIPTION

ACRONYM

OFFSET

Port P4 interrupt flag

P4IFG

1Dh

表9-42. Port P5, P6 Registers (Base Address: 0240h)

REGISTER DESCRIPTION

ACRONYM

OFFSET

00h

Port P5 input

P5IN

Port P5 output

P5OUT

P5DIR

P5REN

P5SEL0

P5SEL1

P5IV

02h

Port P5 direction

04h

Port P5 pulling enable

Port P5 selection 0

06h

0Ah

0Ch

0Eh

16h

Port P5 selection 1

Port P5 interrupt vector word

Port P5 complement selection

Port P5 interrupt edge select

Port P5 interrupt enable

Port P5 interrupt flag

P5SELC

P5IES

18h

P5IE

1Ah

1Ch

P5IFG

Port P6 input

P6IN

P6OUT

P6DIR

P6REN

P6SEL0

P6SEL1

P6IV

01h

03h

05h

07h

0Bh

0Dh

1Eh

17h

19h

1Bh

1Dh

Port P6 output

Port P6 direction

Port P6 pulling enable

Port P6 selection 0

Port P6 selection 1

Port P6 interrupt vector word

Port P6 complement selection

Port P6 interrupt edge select

Port P6 interrupt enable

Port P6 interrupt flag

P6SELC

P6IES

P6IE

P6IFG

表9-43. RTC Registers (Base Address: 0300h)

REGISTER DESCRIPTION

ACRONYM

RTCCTL

RTCIV

OFFSET

00h

RTC control

RTC interrupt vector

RTC modulo

04h

RTCMOD

RTCCNT

08h

RTC counter

0Ch

表9-44. Timer0_A3 Registers (Base Address: 0380h)

REGISTER DESCRIPTION

ACRONYM

OFFSET

00h

TA0 control

TA0CTL

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

TA0 counter

TA0CCTL0

TA0CCTL1

TA0CCTL2

TA0R

02h

04h

06h

10h

Capture/compare 0

Capture/compare 1

Capture/compare 2

TA0 expansion 0

TA0CCR0

TA0CCR1

TA0CCR2

TA0EX0

12h

14h

16h

20h

TA0 interrupt vector

TA0IV

2Eh

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表9-45. Timer1_A3 Registers (Base Address: 03C0h)

REGISTER DESCRIPTION

ACRONYM

OFFSET

00h

TA1 control

TA1CTL

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

TA1 counter

TA1CCTL0

TA1CCTL1

TA1CCTL2

TA1R

02h

04h

06h

10h

Capture/compare 0

Capture/compare 1

Capture/compare 2

TA1 expansion 0

TA1CCR0

TA1CCR1

TA1CCR2

TA1EX0

12h

14h

16h

20h

TA1 interrupt vector

TA1IV

2Eh

表9-46. Timer2_A3 Registers (Base Address: 0400h)

REGISTER DESCRIPTION

ACRONYM

OFFSET

00h

TA2 control

TA2CTL

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

TA2 counter

TA2CCTL0

TA2CCTL1

TA2CCTL2

TA2R

02h

04h

06h

10h

Capture/compare 0

Capture/compare 1

Capture/compare 2

TA2 expansion 0

TA2CCR0

TA2CCR1

TA2CCR2

TA2EX0

12h

14h

16h

20h

TA2 interrupt vector

TA2IV

2Eh

表9-47. Timer3_A3 Registers (Base Address: 0440h)

REGISTER DESCRIPTION

ACRONYM

OFFSET

00h

TA3 control

TA3CTL

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

TA3 counter

TA3CCTL0

TA3CCTL1

TA3CCTL2

TA3R

02h

04h

06h

10h

Capture/compare 0

Capture/compare 1

Capture/compare 2

TA3 expansion 0

TA3CCR0

TA3CCR1

TA3CCR2

TA3EX0

12h

14h

16h

20h

TA3 interrupt vector

TA3IV

2Eh

表9-48. Timer0_B7 Registers (Base Address: 0480h)

REGISTER DESCRIPTION

ACRONYM

OFFSET

00h

TB0 control

TB0CTL

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

Capture/compare control 3

Capture/compare control 4

Capture/compare control 5

Capture/compare control 6

TB0CCTL0

TB0CCTL1

TB0CCTL2

TB0CCTL3

TB0CCTL4

TB0CCTL5

TB0CCTL6

02h

04h

06h

08h

0Ah

0Ch

0Eh

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表9-48. Timer0_B7 Registers (Base Address: 0480h) (continued)

REGISTER DESCRIPTION

ACRONYM

OFFSET

TB0 counter

TB0R

10h

12h

14h

16h

18h

1Ah

1Ch

1Eh

20h

2Eh

Capture/compare 0

Capture/compare 1

Capture/compare 2

Capture/compare 3

Capture/compare 4

Capture/compare 5

Capture/compare 6

TB0 expansion 0

TB0 interrupt vector

TB0CCR0

TB0CCR1

TB0CCR2

TB0CCR3

TB0CCR4

TB0CCR5

TB0CCR6

TB0EX0

TB0IV

表9-49. MPY32 Registers (Base Address: 04C0h)

REGISTER DESCRIPTION

ACRONYM

OFFSET

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

18h

1Ah

1Ch

1Eh

20h

22h

24h

26h

28h

2Ah

2Ch

MPY

16-bit operand 1 –multiply

MPYS

16-bit operand 1 –signed multiply

16-bit operand 1 –multiply accumulate

16-bit operand 1 –signed multiply accumulate

16-bit operand 2

MAC

MACS

OP6

16 × 16 result low word

RESLO

RESHI

16 × 16 result high word

16 × 16 sum extension

SUMEXT

MPY32L

MPY32H

MPYS32L

MPYS32H

MAC32L

MAC32H

MACS32L

MACS32H

OP2L

32-bit operand 1 –multiply low word

32-bit operand 1 –multiply high word

32-bit operand 1 –signed multiply low word

32-bit operand 1 –signed multiply high word

32-bit operand 1 –multiply accumulate low word

32-bit operand 1 –multiply accumulate high word

32-bit operand 1 –signed multiply accumulate low word

32-bit operand 1 –signed multiply accumulate high word

32-bit operand 2 –low word

OP2H

32-bit operand 2 –high word

RES0

32 × 32 result 0 –least significant word

32 × 32 result 1

RES1

32 × 32 result 2

RES2

RES3

32 × 32 result 3 –most significant word

MPY32 control 0

MPY32CTL0

表9-50. eUSCI_A0 Registers (Base Address: 0500h)

REGISTER DESCRIPTION

ACRONYM

UCA0CTLW0

UCA0CTLW1

UCA0BR0

OFFSET

00h

eUSCI_A control word 0

eUSCI_A control word 1

eUSCI_A control rate 0

eUSCI_A control rate 1

eUSCI_A modulation control

eUSCI_A status

02h

06h

UCA0BR1

07h

UCA0MCTLW

UCA0STAT

08h

0Ah

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表9-50. eUSCI_A0 Registers (Base Address: 0500h) (continued)

REGISTER DESCRIPTION

ACRONYM

UCA0RXBUF

UCA0TXBUF

UCA0ABCTL

lUCA0IRTCTL

IUCA0IRRCTL

UCA0IE

OFFSET

0Ch

0Eh

eUSCI_A receive buffer

eUSCI_A transmit buffer

eUSCI_A LIN control

10h

eUSCI_A IrDA transmit control

eUSCI_A IrDA receive control

eUSCI_A interrupt enable

eUSCI_A interrupt flags

12h

13h

1Ah

UCA0IFG

1Ch

1Eh

eUSCI_A interrupt vector word

UCA0IV

表9-51. eUSCI_A1 Registers (Base Address: 0520h)

REGISTER DESCRIPTION

ACRONYM

UCA1CTLW0

UCA1CTLW1

UCA1BR0

OFFSET

00h

eUSCI_A control word 0

eUSCI_A control word 1

eUSCI_A control rate 0

eUSCI_A control rate 1

eUSCI_A modulation control

eUSCI_A status

02h

06h

UCA1BR1

07h

UCA1MCTLW

UCA1STAT

UCA1RXBUF

UCA1TXBUF

UCA1ABCTL

lUCA1IRTCTL

IUCA1IRRCTL

UCA1IE

08h

0Ah

0Ch

0Eh

10h

eUSCI_A receive buffer

eUSCI_A transmit buffer

eUSCI_A LIN control

eUSCI_A IrDA transmit control

eUSCI_A IrDA receive control

eUSCI_A interrupt enable

eUSCI_A interrupt flags

eUSCI_A interrupt vector word

12h

13h

1Ah

1Ch

1Eh

UCA1IFG

UCA1IV

表9-52. eUSCI_B0 Registers (Base Address: 0540h)

REGISTER DESCRIPTION

ACRONYM

UCB0CTLW0

UCB0CTLW1

UCB0BR0

OFFSET

00h

eUSCI_B control word 0

eUSCI_B control word 1

eUSCI_B bit rate 0

02h

06h

eUSCI_B bit rate 1

UCB0BR1

07h

eUSCI_B status word

UCB0STATW

UCB0TBCNT

UCB0RXBUF

UCB0TXBUF

UCB0I2COA0

UCB0I2COA1

UCB0I2COA2

UCB0I2COA3

UCB0ADDRX

UCB0ADDMASK

UCB0I2CSA

UCB0IE

08h

eUSCI_B byte counter threshold

eUSCI_B receive buffer

eUSCI_B transmit buffer

eUSCI_B I2C own address 0

eUSCI_B I2C own address 1

eUSCI_B I2C own address 2

eUSCI_B I2C own address 3

eUSCI_B receive address

eUSCI_B address mask

eUSCI_B I2C slave address

eUSCI_B interrupt enable

eUSCI_B interrupt flags

0Ah

0Ch

0Eh

14h

16h

18h

1Ah

1Ch

1Eh

20h

2Ah

2Ch

UCB0IFG

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表9-52. eUSCI_B0 Registers (Base Address: 0540h) (continued)

REGISTER DESCRIPTION

ACRONYM

OFFSET

eUSCI_B interrupt vector word

UCB0IV

2Eh

表9-53. eUSCI_B1 Registers (Base Address: 0580h)

REGISTER DESCRIPTION

ACRONYM

UCB1CTLW0

UCB1CTLW1

UCB1BR0

OFFSET

00h

eUSCI_B control word 0

eUSCI_B control word 1

eUSCI_B bit rate 0

02h

06h

eUSCI_B bit rate 1

UCB1BR1

07h

eUSCI_B status word

UCB1STATW

UCB1TBCNT

UCB1RXBUF

UCB1TXBUF

UCB1I2COA0

UCB1I2COA1

UCB1I2COA2

UCB1I2COA3

UCB1ADDRX

UCB1ADDMASK

UCB1I2CSA

UCB1IE

08h

eUSCI_B byte counter threshold

eUSCI_B receive buffer

eUSCI_B transmit buffer

eUSCI_B I2C own address 0

eUSCI_B I2C own address 1

eUSCI_B I2C own address 2

eUSCI_B I2C own address 3

eUSCI_B receive address

eUSCI_B address mask

eUSCI_B I2C slave address

eUSCI_B interrupt enable

eUSCI_B interrupt flags

eUSCI_B interrupt vector word

0Ah

0Ch

0Eh

14h

16h

18h

1Ah

1Ch

1Eh

20h

2Ah

2Ch

2Eh

UCB1IFG

UCB1IV

表9-54. Backup Memory Registers (Base Address: 0660h)

REGISTER DESCRIPTION

ACRONYM

BAKMEM0

BAKMEM1

BAKMEM2

BAKMEM3

BAKMEM4

BAKMEM5

BAKMEM6

BAKMEM7

BAKMEM8

BAKMEM9

BAKMEM10

BAKMEM11

BAKMEM12

BAKMEM13

BAKMEM14

BAKMEM15

OFFSET

00h

Backup memory 0

Backup memory 1

Backup memory 2

Backup memory 3

Backup memory 4

Backup memory 5

Backup memory 6

Backup memory 7

Backup memory 8

Backup memory 9

Backup memory 10

Backup memory 11

Backup memory 12

Backup memory 13

Backup memory 14

Backup memory 15

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

18h

1Ah

1Ch

1Eh

表9-55. ADC Registers (Base Address: 0700h)

REGISTER DESCRIPTION

REGISTER

ADCCTL0

ADCCTL1

ADCCTL2

OFFSET

00h

ADC control 0

ADC control 1

ADC control 2

02h

04h

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表9-55. ADC Registers (Base Address: 0700h) (continued)

REGISTER DESCRIPTION

REGISTER

OFFSET

06h

ADC window comparator low threshold

ADC window comparator high threshold

ADC memory control 0

ADCLO

ADCHI

08h

ADCMCTL0

ADCMEM0

ADCIE

0Ah

ADC conversion memory

ADC interrupt enable

12h

1Ah

ADC interrupt flags

ADCIFG

ADCIV

1Ch

1Eh

ADC interrupt vector word

表9-56. eCOMP Registers (Base Address: 08E0h)

REGISTER DESCRIPTION

REGISTER

CP0CTL0

CP0CTL1

CP0INT

OFFSET

00h

Comparator control 0

Comparator control 1

02h

Comparator interrupt

06h

Comparator interrupt vector

Comparator built-in DAC control

CP0IV

08h

CP0DACCTL

10h

9.14 Identification

9.14.1 Revision Identification

The device revision information is included as part of the top-side marking on the device package. The device-

specific errata sheet describes these markings.

The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For details on

this value, see the Hardware Revision entries in 节9.12.

9.14.2 Device Identification

The device type can be identified from the top-side marking on the device package. The device-specific errata

sheet describes these markings.

A device identification value is also stored in the Device Descriptor structure in the Info Block section. For details

on this value, see the Device ID entries in 节9.12.

9.14.3 JTAG Identification

Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in MSP430

Programming With the JTAG Interface.

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10 Applications, Implementation, and Layout

Note

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

10.1 Device Connection and Layout Fundamentals

This section discusses the recommended guidelines when designing with the MSP430 devices. These

guidelines are to make sure that the device has proper connections for powering, programming, debugging, and

optimum analog performance.

10.1.1 Power Supply Decoupling and Bulk Capacitors

TI recommends connecting a combination of a 10-µF plus a 100-nF low-ESR ceramic decoupling capacitor to

the DVCC and DVSS pins. Higher-value capacitors may be used but can impact supply rail ramp-up time.

Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few

millimeters). Additionally, TI recommends separated grounds with a single-point connection for better noise

isolation from digital-to-analog circuits on the board and to achieve high analog accuracy.

DVCC

Digital

+

Power Supply

Decoupling

DVSS

10 µF

100 nF

图10-1. Power Supply Decoupling

10.1.2 External Oscillator

This device supports only a low-frequency crystal (32 kHz) on the XIN and XOUT pins. External bypass

capacitors for the crystal oscillator pins are required.

It is also possible to apply digital clock signals to the XIN input pin that meet the specifications of the respective

oscillator if the appropriate XT1BYPASS mode is selected. In this case, the associated XOUT pin can be used

for other purposes. If the XIN and XOUT pins are not used, they must be terminated according to 节7.6.

图10-2 shows a typical connection diagram.

XIN

XOUT

C_L1

C_L2

图10-2. Typical Crystal Connection

See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal

oscillator with the MSP430 devices.

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10.1.3 JTAG

With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or MSP-

FET430UIF) can be used to program and debug code on the target board. In addition, the connections also

support the MSP-GANG production programmers, thus providing an easy way to program prototype boards, if

desired. 图 10-3 shows the connections between the 14-pin JTAG connector and the target device required to

support in-system programming and debugging for 4-wire JTAG communication. 图 10-4 shows the connections

for 2-wire JTAG mode (Spy-Bi-Wire).

The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are identical.

Both can supply V_CCto the target board (through pin 2). In addition, the MSP-FET and MSP-FET430UIF

interface modules and MSP-GANG have a V_CCsense feature that, if used, requires an alternate connection (pin

4 instead of pin 2). The V_CCsense feature detects the local V_CCpresent on the target board (that is, a battery or

other local power supply) and adjusts the output signals accordingly. 图 10-3 and 图 10-4 show a jumper block

that supports both scenarios of supplying V_CCto the target board. If this flexibility is not required, the desired V_CC

connections may be hard-wired to eliminate the jumper block. Pins 2 and 4 must not be connected at the same

time.

For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User's Guide.

V_CC

Important to connect

MSP430FRxxx

J1 (see Note A)

DVCC

J2 (see Note A)

R1

47 kW

JTAG

RST/NMI/SBWTDIO

VCC TOOL

TDO/TDI

TDI

TDO/TDI

TDI

2

1

VCC TARGET

4

3

TMS

6

5

7

TEST

TCK

8

TCK

GND

RST

10

12

14

9

11

13

TEST/SBWTCK

DVSS

C1

1 nF

(see Note B)

A. If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used, make connection

J2.

B. The upper limit for C1 is 1.1 nF when using current TI tools.

图10-3. Signal Connections for 4-Wire JTAG Communication

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V_CC

Important to connect

MSP430FRxxx

J1 (see Note A)

J2 (see Note A)

DVCC

R1

47 kΩ

(see Note B)

JTAG

VCC TOOL

TDO/TDI

2

1

3

5

7

9

RST/NMI/SBWTDIO

VCC TARGET

4

6

TCK

8

GND

10

12

14

11

13

TEST/SBWTCK

DVSS

C1

1 nF

(see Note B)

A. Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the debug or

programming adapter.

B. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during JTAG access, and

any capacitance that is attached to this signal may affect the ability to establish a connection with the device. The upper limit for C1 is

1.1 nF when using current TI tools.

图10-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)

10.1.4 Reset

The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function

Register (SFR), SFRRPCR.

In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing

specifications generates a BOR-type device reset.

Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is edge

sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the external NMI.

When an external NMI event occurs, the NMIIFG is set.

The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either pullup or

pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not. If the RST/NMI

pin is unused, it is required either to select and enable the internal pullup or to connect an external 47-kΩpullup

resistor to the RST/NMI pin with a 10-nF pulldown capacitor. The pulldown capacitor should not exceed 1.1 nF

when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools like

FET interfaces or GANG programmers.

See the MP430FR4xx and MP430FR2xx Family User's Guide for more information on the referenced control

registers and bits.

10.1.5 Unused Pins

For details on the connection of unused pins, see 节7.6.

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10.1.6 General Layout Recommendations

• Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430 32-kHz

Crystal Oscillators for recommended layout guidelines.

• Proper bypass capacitors on DVCC and reference pins, if used.

• Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital switching

signals such as PWM or JTAG signals away from the oscillator circuit.

• Proper ESD level protection should be considered to protect the device from unintended high-voltage

electrostatic discharge. See MSP430 System-Level ESD Considerations for guidelines.

10.1.7 Do's and Don'ts

During power up, power down, and device operation, DVCC must not exceed the limits specified in 节 8.1,

Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the device including

erroneous writes to RAM and FRAM.

10.2 Peripheral- and Interface-Specific Design Information

10.2.1 ADC Peripheral

10.2.1.1 Partial Schematic

图10-5 shows the recommended decoupling circuit when an external voltage reference is used.

DVSS

Using an external

VREF+/VEREF+

positive reference

+

100 nF

10 µF

Using an external

negative reference

VEREF-

+

10 µF

100 nF

图10-5. ADC Grounding and Noise Considerations

10.2.1.2 Design Requirements

As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should be

followed to eliminate ground loops, unwanted parasitic effects, and noise.

Ground loops are formed when return current from the ADC flows through paths that are common with other

analog or digital circuitry. If care is not taken, this current can generate small unwanted offset voltages that can

add to or subtract from the reference or input voltages of the ADC. The general guidelines in 节10.1.1 combined

with the connections shown in 图10-5 prevent this.

Quickly switching digital signals and noisy power supply lines can corrupt the conversion results, so keep the

ADC input trace shielded from those digital and power supply lines. Putting the MCU in low-power mode during

the ADC conversion improves the ADC performance in a noisy environment. If the device includes the analog

power pair inputs (AVCC and AVSS), TI recommends a noise-free design using separate analog and digital

ground planes with a single-point connection to achieve high accuracy.

图 10-5 shows the recommended decoupling circuit when an external voltage reference is used. The internal

reference module has a maximum drive current as described in the sections ADC Pin Enable and 1.2-V

Reference Settings of the MSP430FR4xx and MSP430FR2xx Family User's Guide.

The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are

selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage

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enters the device. In this case, the 10-µF capacitor buffers the reference pin and filters low-frequency ripple. A

100-nF bypass capacitor of filters high-frequency noise.

10.2.1.3 Layout Guidelines

Components that are shown in the partial schematic (see 图 10-5) should be placed as close as possible to the

respective device pins to avoid long traces, because they add additional parasitic capacitance, inductance, and

resistance on the signal.

Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM), because

the high-frequency switching can be coupled into the analog signal.

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11 Device and Documentation Support

11.1 Getting Started and Next Steps

For more information on the MSP low-power microcontrollers and the tools and libraries that are available to help

with your development, visit the MSP430™ ultra-low-power sensing & measurement MCUs overview.

11.2 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP

MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These

prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully

qualified production devices (MSP).

XMS –Experimental device that is not necessarily representative of the final device's electrical specifications

MSP –Fully qualified production device

XMS devices are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated

fully. TI's standard warranty applies.

Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.

TI recommends that these devices not be used in any production system because their expected end-use failure

rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature

range, package type, and distribution format. 图11-1 provides a legend for reading the complete device name.

476

MSP

430 FR

2

T

RHL

T

Processor Family

MCU Platform

Device Type

Series

Tape and Reel

Packaging

Temperature Range

Feature Set

Processor Family

MSP = Mixed-signal processor

XMS = Experimental silicon

MCU Platform

Device Type

430 = MSP430 16-bit low-power platform

Memory type

FR = FRAM

Series

2 = No LCD driver

Feature Set

First and second digits:

Third digit:

ADC12 channels / eUSCIs / 16-bit timers FRAM (KB) / SRAM (KB)

6 = 64 / 8

47 = Up to 12 / 4 / 5

5 = 32 / 6

Temperature Range

Packaging

T = –40°C to 105°C

www.ti.com/packaging

Distribution Format

T = Small reel

R = Large reel

No marking = Tube or tray

图11-1. Device Nomenclature

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11.3 Tools and Software

表 11-1 lists the debug features supported by these microcontrollers. See the Code Composer Studio™ IDE for

MSP430™ MCUs User's Guide for details on the available features.

表11-1. Hardware Features

BREAK-

POINTS

(N)

RANGE

BREAK-

POINTS

LPMx.5

DEBUGGING

SUPPORT

MSP430

ARCHITECTURE

4-WIRE

JTAG

2-WIRE

JTAG

CLOCK

CONTROL

STATE

SEQUENCER

TRACE

BUFFER

EEM

VERSION

MSP430Xv2

Yes

3

Yes

No

S

Design Kits and Evaluation Modules

MSP430FR2476 LaunchPad™ development kit

The LP-MSP430FR2476 LaunchPad development kit is an easy-to-use evaluation module (EVM) based on the

MSP430FR2476 value line sensing microcontroller (MCU). It contains everything needed to start developing on

the ultra-low-power MSP430FR2x value line sensing MCU platform, including on-board debug probe for

programming, debugging and energy measurements.

Target development board for MSP430FR2476 MCU

The MSP-TS430PT48A microcontroller development board is a standalone ZIF socket target board used to

program and debug the MSP430 in-system through the JTAG interface or the Spy Bi-Wire (2-wire JTAG)

protocol. This development board supports the MSP430FR2476 FRAM devices in a 48-pin QFP package (TI

package code: PT).

Software

MSP430Ware^™Software

MSP430Ware software is a collection of code examples, data sheets, and other design resources for all

MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing

MSP430 design resources, MSP430Ware software also includes a high-level API called MSP430 Driver Library.

This library makes it easy to program MSP430 hardware. MSP430Ware software is available as a component of

CCS or as a stand-alone package.

MSP430FR267x, MSP430FR247x Code Examples

C code examples that configure each of the integrated peripherals for various application needs.

MSP Driver Library

The driver library's abstracted API keeps you above the bits and bytes of the MSP430 hardware by providing

easy-to-use function calls. Thorough documentation is delivered through a helpful API guide, which includes

details on each function call and the recognized parameters. Developers can use driver library functions to write

complete projects with minimal overhead.

MSP EnergyTrace^™Technology

EnergyTrace technology for MSP430 microcontrollers is an energy-based code analysis tool that measures and

displays the application’s energy profile and helps to optimize it for ultra-low-power consumption.

ULP (Ultra-Low Power) Advisor

ULP Advisor^™software is a tool for guiding developers to write more efficient code to fully utilize the unique

ultra-low power features of MSP and MSP432 microcontrollers. Aimed at both experienced and new

microcontroller developers, ULP Advisor checks your code against a thorough ULP checklist to squeeze every

last nano amp out of your application. At build time, ULP Advisor will provide notifications and remarks to

highlight areas of your code that can be further optimized for lower power.

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FRAM Embedded Software Utilities for MSP Ultra-Low-Power Microcontrollers

The FRAM Utilities is designed to grow as a collection of embedded software utilities that leverage the ultra-low-

power and virtually unlimited write endurance of FRAM. The utilities are available for MSP430FRxx FRAM

microcontrollers and provide example code to help start application development. Included utilities include

Compute Through Power Loss (CTPL). CTPL is utility API set that enables ease of use with LPMx.5 low-power

modes and a powerful shutdown mode that allows an application to save and restore critical system components

when a power loss is detected.

IEC60730 Software Package

The IEC60730 MSP430 software package helps you comply with IEC 60730-1:2010 (Automatic Electrical

Controls for Household and Similar Use – Part 1: General Requirements) for up to Class B products, which

includes home appliances, arc detectors, power converters, power tools, e-bikes, and many others. The

IEC60730 MSP430 software package can be embedded in applications that run on MSP430 MCUs to help

simplify the certification efforts of functional safety compliant consumer devices to IEC 60730-1:2010 Class B.

Fixed-Point Math Library for MSP

The MSP IQmath and Qmath Libraries are a collection of highly optimized and high-precision mathematical

functions for C programmers to seamlessly port a floating-point algorithm into fixed-point code on MSP430 and

MSP432 devices. These routines are typically used in computationally intensive real-time applications where

optimal execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and Qmath

libraries, it is possible to achieve execution speeds considerably faster and energy consumption considerably

lower than equivalent code written using floating-point math.

Floating-Point Math Library for MSP430

Continuing to innovate in the low power and low cost microcontroller space, TI brings you MSPMATHLIB.

Leveraging the intelligent peripherals of our devices, this floating point math library of scalar functions brings you

up to 26x better performance. Mathlib is easy to integrate into your designs. This library is free and is integrated

in both Code Composer Studio IDE and IAR Embedded Workbench IDE.

Development Tools

Code Composer Studio^™Integrated Development Environment for MSP Microcontrollers

Code Composer Studio integrated development environment (IDE) supports all MSP microcontroller devices.

Code Composer Studio IDE comprises a suite of embedded software utilities used to develop and debug

embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,

debugger, profiler, and many other features.

IAR Embedded Workbench^®IDE

IAR Embedded Workbench IDE for MSP430 MCUs is a complete C/C++ compiler toolchain for building and

debugging embedded applications based on MSP430 microcontrollers. The debugger can be used for source

and disassembly code with support for complex code and data breakpoints. It also provides a hardware

simulator that allows debugging without a physical target connected.

Uniflash Standalone Flash Tool

CCS Uniflash is a stand-alone tool used to program on-chip flash memory on TI MCUs. Uniflash has a GUI,

command line, and scripting interface. Uniflash is a software tool available by TI Cloud Tools or desktop

application download from the TI web page.

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MSP MCU Programmer and Debugger

The MSP-FET is a powerful emulation development tool – often called a debug probe – that lets users quickly

begin application development on MSP low-power microcontrollers (MCU). Creating MCU software usually

requires downloading the resulting binary program to the MSP device for validation and debugging. The MSP-

FET provides a debug communication pathway between a host computer and the target MSP. Furthermore, the

MSP-FET also provides a backchannel UART connection between the computer's USB interface and the MSP

UART. This affords the MSP programmer a convenient method for communicating serially between the MSP and

a terminal running on the computer.

MSP-GANG Production Programmer

The MSP Gang Programmer can program up to eight identical MSP430 or MSP432 flash or FRAM devices at

the same time. The MSP Gang Programmer connects to a host PC using a standard RS-232 or USB connection

and provides flexible programming options that allow the user to fully customize the process. The MSP Gang

Programmer is provided with an expansion board, called the Gang Splitter, that implements the interconnections

between the MSP Gang Programmer and multiple target devices.

TIREX Resource Explorer (TIRex)

An online portal to examples, libraries, executables, and documentation for your device and development board.

TIRex can be accessed directly in Code Composer Studio IDE or in TI Cloud Tools.

TI Cloud Tools

Start development immediately on dev.ti.com. Begin by using the Resource Explorer interface to quickly find all

the files you need. Then, edit, build, and debug embedded applications in the cloud, using industry-leading Code

Composer Studio Cloud IDE.

GCC - Compiler for MSP

MSP430 and MSP432 GCC open source packages are complete debugger and open source C/C++ compiler

toolchains for building and debugging embedded applications based on MSP430 and MSP432 microcontrollers.

These free GCC compilers support all MSP430 and MSP432 devices without code size limitations. In addition,

these compilers can be used stand-alone from the command-line or within Code Composer Studio v6.0 or later.

Get started today whether you are using a Windows^®, Linux^®, or macOS^®environment.

11.4 Documentation Support

The following documents describe the MSP430FR247x microcontrollers. Copies of these documents are

available on the Internet at www.ti.com.

Receiving Notification of Document Updates

To receive notification of documentation updates—including silicon errata—go to the product folder for your

device on ti.com (for example, MSP430FR2476). In the upper right corner, click the "Alert me" button. This

registers you to receive a weekly digest of product information that has changed (if any). For change details,

check the revision history of any revised document.

Errata

MSP430FR2476 Device Erratasheet

Describes the known exceptions to the functional specifications.

MSP430FR2475 Device Erratasheet

Describes the known exceptions to the functional specifications.

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User's Guides

MSP430FR4xx and MSP430FR2xx Family User's Guide

Detailed description of all modules and peripherals available in this device family.

MSP430™ FRAM Devices Bootloader (BSL) User's Guide

The bootloader (BSL) on MSP430 microcontrollers (MCUs) lets users communicate with embedded memory in

the MSP430 MCU during the prototyping phase, final production, and in service. Both the programmable

memory (FRAM memory) and the data memory (RAM) can be modified as required.

MSP430™ Programming With the JTAG Interface

This document describes the functions that are required to erase, program, and verify the memory module of the

MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port.

MSP430™ Hardware Tools User's Guide

This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the

program development tool for the MSP430 ultra-low-power microcontroller. Both available interface types, the

parallel port interface and the USB interface, are described.

Application Reports

MSP430 32-kHz Crystal Oscillators

Selection of the right crystal, correct load circuit, and proper board layout are important for a stable crystal

oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the

correct crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout

are given. The document also contains detailed information on the possible oscillator tests to ensure stable

oscillator operation in mass production.

MSP430 System-Level ESD Considerations

System-level ESD has become increasingly demanding with silicon technology scaling towards lower voltages

and the need for designing cost-effective and ultra-low-power components. This application report addresses

ESD topics to help board designers and OEMs understand and design robust system-level designs.

11.5 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.6 Trademarks

TI E2E^™, MSP430^™, MSP430Ware^™, EnergyTrace^™, ULP Advisor^™, Code Composer Studio^™, and are

trademarks of Texas Instruments.

IAR Embedded Workbench^®is a registered trademark of IAR Systems.

Windows^®is a registered trademark of Microsoft Corporation.

Linux^®is a registered trademark of Linus Torvalds.

macOS^®is a registered trademark of Apple, Inc.

所有商标均为其各自所有者的财产。

11.7 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

Submit Document Feedback

93

Product Folder Links: MSP430FR2476 MSP430FR2475

MSP430FR2476, MSP430FR2475

ZHCSJG5C –MARCH 2019 –REVISED SEPTEMBER 2021

www.ti.com.cn

11.8 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as

defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled

product restricted by other applicable national regulations, received from disclosing party under nondisclosure

obligations (if any), or any direct product of such technology, to any destination to which such export or re-export

is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.

Department of Commerce and other competent Government authorities to the extent required by those laws.

11.9 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

94

Submit Document Feedback

Product Folder Links: MSP430FR2476 MSP430FR2475

MSP430FR2476, MSP430FR2475

ZHCSJG5C –MARCH 2019 –REVISED SEPTEMBER 2021

www.ti.com.cn

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, see the left-hand navigation.

Submit Document Feedback

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Product Folder Links: MSP430FR2476 MSP430FR2475

重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知

识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。

TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI

提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

GENERIC PACKAGE VIEW

RHB 32

5 x 5, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224745/A

www.ti.com

PACKAGE OUTLINE

RHB0032E

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

B

A

PIN 1 INDEX AREA

(0.1)

5.1

4.9

SIDE WALL DETAIL

20.000

OPTIONAL METAL THICKNESS

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 3.5

(0.2) TYP

3.45 0.1

9

EXPOSED

THERMAL PAD

16

28X 0.5

8

17

SEE SIDE WALL

DETAIL

2X

SYMM

33

3.5

0.3

0.2

32X

24

0.1

C A B

C

1

0.05

32

25

PIN 1 ID

(OPTIONAL)

SYMM

0.5

0.3

32X

4223442/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RHB0032E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.45)

SYMM

32

25

32X (0.6)

1

24

32X (0.25)

(1.475)

28X (0.5)

33

SYMM

(4.8)

(

0.2) TYP

VIA

8

17

(R0.05)

TYP

9

16

(1.475)

(4.8)

LAND PATTERN EXAMPLE

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223442/B 08/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RHB0032E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.49)

(0.845)

(R0.05) TYP

32

25

32X (0.6)

1

24

32X (0.25)

28X (0.5)

(0.845)

SYMM

33

(4.8)

17

8

METAL

TYP

16

9

SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4223442/B 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

GENERIC PACKAGE VIEW

RHA 40

6 x 6, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225870/A

www.ti.com

PACKAGE OUTLINE

RHA0040D

VQFN - 1 mm max height

S

C

A

L

E

2

.

2

0

PLASTIC QUAD FLATPACK - NO LEAD

6.1

5.9

B

A

PIN 1 INDEX AREA

0.5

0.3

6.1

5.9

0.3

0.2

DETAIL

OPTIONAL TERMINAL

TYPICAL

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 4.5

(0.1) TYP

2.9 0.1

EXPOSED

THERMAL PAD

11

20

36X 0.5

10

21

2X

41

SYMM

4.5

1

30

SEE TERMINAL

DETAIL

0.3

0.2

0.1

40X

40

31

SYMM

C A

B

PIN 1 ID

(OPTIONAL)

0.5

0.3

40X

0.05

4225822/A 03/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RHA0040D

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.9)

SYMM

40

31

40X (0.6)

1

30

40X (0.25)

(1.2)

TYP

41

SYMM

(5.8)

36X (0.5)

(

0.2) TYP

VIA

21

10

(R0.05)

TYP

11

20

(5.8)

LAND PATTERN EXAMPLE

SCALE:15X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4225822/A 03/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view.

www.ti.com

EXAMPLE STENCIL DESIGN

RHA0040D

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(R0.05) TYP

SYMM

40

31

40X (0.6)

1

30

4X ( 1.27)

40X (0.25)

(0.735) TYP

(0.735)

TYP

41

SYMM

(5.8)

36X (0.5)

METAL

TYP

21

10

20

11

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 41:

76.46% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:15X

4225822/A 03/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

PT0048A

LQFP - 1.6 mm max height

S

C

A

L

E

2

.

0

LOW PROFILE QUAD FLATPACK

9.2

8.8

7.2

6.8

B

A

9.2

8.8

7.2

6.8

0.27

48X

0.17

0.08

C A B

44X 0.5

4X 5.5

SEE DETAIL A

1.6 MAX

C

SEATING PLANE

0.1 C

1.45

1.35

0.25

GAGE PLANE

0.75

0.45

0.5 MIN

0 -7

A15.000

DETAIL A

4215159/A 12/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Reference JEDEC registration MS-026.

4. This may also be a thermally enhanced plastic package with leads conected to the die pads.

www.ti.com

EXAMPLE BOARD LAYOUT

PT0048A

LQFP - 1.6 mm max height

LOW PROFILE QUAD FLATPACK

PKG

SYMM

48

37

SEE SOLDER MASK

DETAILS

48X (1.6)

1

36

48X (0.3)

44X (0.5)

PKG SYMM

(8.2)

(R0.05) TYP

12

25

13

24

(8.2)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE 10.000

0.05 MAX

ALLAROUND

0.05 MIN

ALL AROUND

EXPOSED METAL

METAL EDGE

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4215159/A 12/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PT0048A

LQFP - 1.6 mm max height

LOW PROFILE QUAD FLATPACK

PKG

SYMM

48

37

48X (1.6)

1

36

48X (0.3)

44X (0.5)

PKG SYMM

(8.2)

(R0.05) TYP

12

25

13

24

(8.2)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE: 10X

4215159/A 12/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	MSP430FR2476
厂家：	TEXAS INSTRUMENTS
描述：	具有 64KB FRAM、8KB SRAM、比较器、12 位 ADC、UART/SPI/I2C 和计时器的 16MHz MCU 静态存储器比较器
文件：	总113页 (文件大小：4213K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MSP430FR2476 [TI]

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