MSP430FR2522IPW16R [TI]
具有 8 个触摸 IO（16 个传感器）、8KB FRAM、2KB SRAM、15 个 IO 和 10 位 ADC 的电容式触摸 MCU | PW | 16 | -40 to 85;
| 型号： | MSP430FR2522IPW16R |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 8 个触摸 IO（16 个传感器）、8KB FRAM、2KB SRAM、15 个 IO 和 10 位 ADC 的电容式触摸 MCU | PW | 16 | -40 to 85 静态存储器 传感器 |
| 文件： | 总94页 (文件大小：1366K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MSP430FR2522, MSP430FR2512
ZHCSHB4C –JANUARY 2018–REVISED DECEMBER 2019
MSP430FR25x2 电容式触摸感应混合信号微控制器
1 器件概述
1.1 特性
1
• CapTIvate™ 技术 – 电容式触控
– 性能
• 优化的超低功耗模式
– 激活模式：120µA/MHz（典型值）
– 待机模式：两个传感器的触摸唤醒电流小于 4µA
– 关断模式 (LPM4.5)：36nA，无 SVS
• 低功耗铁电 RAM (FRAM)
– 两路同步快速电极扫描
– 接近感应
– 可靠性
– 提高了针对电力线、射频及其他环境噪声的抗
扰度
– 非易失性存储器容量高达 7.5KB
– 内置错误修正码 (ECC)
– 内置扩展频谱、自动调优、噪声滤除和消抖算
法
– 可配置的写保护
– 对程序、常量和存储的统一存储
– 耐写次数达 1015
– 抗辐射和非磁性
– 提供可靠的触控解决方案，该方案具有 10V
RMS 共模噪声、4kV 电气快速瞬变以及 15kV
静电放电，符合 IEC‑61000-4-6、IEC-61000-
4-4 和 IEC‑61000-4-2 标准
– 降低了射频辐射，简化了电气设计
– 支持金属触控和防水设计
次
– FRAM 与 SRAM 之比高达 4：1
• 高性能模拟
– 高达 8 通道 10 位模数转换器 (ADC)
– 1.5V 的内部基准电压
– 采样与保持 200ksps
– 灵活性
– 多达 8 个自电容式电极和 16 个互电容式电极
– 在同一设计中混合使用自电容式电极和互电容
式电极
• 智能数字外设
– 两个 16 位计时器，每个计时器有三个捕捉/比较
寄存器 (Timer_A3)
– 一个 16 位计时器，采用 CapTIvate™技术
– 一个仅用作计数器的 16 位 RTC
– 16 位循环冗余校验 (CRC)
– 支持多点触控功能
– 宽电容检测范围；0 至 300pF 宽电极范围
– 低功耗
– 两个传感器的触摸唤醒电流小于 4µA
– 触摸唤醒状态机支持在 CPU 休眠过程中进行
电极扫描
• 增强型串行通信，支持引脚重映射功能（请参阅 器
件比较）
– 一个 eUSCI_A 接口，支持 UART、IrDA 和 SPI
– 一个 eUSCI_B 接口，支持 SPI 和 I2C
• 时钟系统 (CS)
– 用于环境补偿、滤波和阈值检测的硬件加速
– 易于使用
– CapTIvate 设计中心，PC GUI 允许工程师对
电容按钮进行实时设计和调试，无需编写代码
– 片上 32kHz RC 振荡器 (REFO)
– 带有锁频环 (FLL) 的片上 16MHz 数控振荡器
– 存储于 ROM 中的 CapTIvate 软件库为客户应
用提供充足的 FRAM
(DCO)
– 室温下的精度为 ±1%（具有片上基准）
– 片上超低频 10kHz 振荡器 (VLO)
– 片上高频调制振荡器 (MODOSC)
– 外部 32kHz 晶振 (LFXT)
• 嵌入式微控制器
– 16 位 RISC 架构
– 支持的时钟频率最高可达 16MHz
– 3.6V 至 1.8V 的宽电源电压范围（最低电源电压
受限于 SVS 电平，请参阅 SVS 规格）
– 可编程 MCLK 预分频器（1 至 128）
– 通过可编程预分频器（1、2、4 或 8）从 MCLK
获得的 SMCLK
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASEE4
MSP430FR2522, MSP430FR2512
ZHCSHB4C –JANUARY 2018–REVISED DECEMBER 2019
www.ti.com.cn
• 通用输入/输出和引脚功能
• 12KB ROM 库包含 CapTIvate 触控程序库和驱动程
序库
– 共计 15 个 I/O（采用 VQFN-20 封装）
• 系列成员（另请参阅 器件特性）
– 15 个中断引脚（P1 和 P2）可以将 MCU 从低功
耗模式下唤醒
– MSP430FR2522：7.25KB 程序 FRAM、256B
信息 FRAM、2KB RAM
• 开发工具和软件
– 开发工具
，多达 8 个自电容式传感器和 16 个互电容式传
感器
– MSP CapTIvate™ MCU 开发套件评估：与
CAPTIVATE‑PGMR 编程器和电容式触控
MSP430FR2522 MCU 板
– MSP430FR2512：7.25KB 程序 FRAM、256B
信息 FRAM、2KB RAM
，多达 4 个自电容式传感器或互电容式传感器
• 封装选项
BOOSTXL‑CAPKEYPAD 配合使用
– 目标开发板 MSP‑TS430RHL20
– 易于使用的生态系统
– 20 引脚：VQFN (RHL)
– 16 引脚：TSSOP (PW)
– CapTIvate 设计中心 – 代码生成、可自定义
GUI、实时调优
1.2 应用
•
•
•
•
•
•
电子智能锁、门键盘和读取器
车库门系统
•
•
•
•
•
A/V 接收器
电器
入侵 HMI 键盘和控制面板
电梯呼叫按钮
电动工具
照明开关
可视门铃
个人电子产品
无线扬声器和耳机
1.3 说明
MSP430FR25x2 包含一系列用于电容式触摸传感的超低功耗 MSP430™微控制器 (MCU)，它们均采用
CapTIvate™ 触控技术，适用于 应用 采用1到16个电容式按钮或接近感应的成本敏感型应用。
MSP430FR25x2 MCU 适用于 应用 电磁干扰、油液、水和油脂影响的工业应用，可以创造价值，实现高性
能。这些器件可提供 IEC 认证的解决方案，其功耗比同类竞争解决方案低 5 倍且支持接近感应以及透过玻
璃、塑料和金属镀层进行触摸操作。
TI 电容式触摸感应 MSP430 MCU 由一套全面的硬件和软件生态系统进行支持，并配套提供参考设计和代码
示例，协助用户快速开展设计。BOOSTXL-CAPKEYPAD BoosterPack™插件模块可搭配使用 CAPTIVATE-
PGMR 编程器电路板（单独使用或作为 MSP-CAPT-FR2633 CapTIvate 开发套件的一部分），或
LaunchPad 开发套件生态系统。TI 还提供免费的软件，如 CapTIvate 设计中心，工程师可以在其中 借助 方
便易用的 GUI 和 ™MSP430Ware™ 软件以及包括 CapTIvate 技术指南在内的综合性文档快速进行应用开
发。
采用 CapTIvate 技术的 MSP430 MCU 提供市面上集成度和自主性领先的电容式触控解决方案，可在最低功
耗下实现高可靠性和抗噪能力。有关更多信息，请访问 ti.com.cn/captivate。
有关完整的模块说明，请参阅《MSP430FR4xx 和 MSP430FR2xx 系列器件用户指南》。
器件信息(1)
封装
器件型号
MSP430FR2522IPW16
MSP430FR2522IRHL
MSP430FR2512IPW16
MSP430FR2512IRHL
封装尺寸(2)
5mm x 4.4mm
4.5mm x 3.5mm
5mm x 4.4mm
4.5mm x 3.5mm
TSSOP (16)
VQFN (20)
TSSOP (16)
VQFN (20)
(1) 要获得最新的产品、封装和订购信息，请参见封装选项附录（节 9），或者访问德州仪器 (TI) 网站
www.ti.com.cn。
(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参见机械数据（节 9中）。
2
器件概述
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2522, MSP430FR2512
www.ti.com.cn
ZHCSHB4C –JANUARY 2018–REVISED DECEMBER 2019
CAUTION
系统级静电放电 (ESD) 保护必须符合器件级 ESD 规范，以防发生电气过载或对
数据或代码存储器造成干扰。有关更多信息，请参阅《MSP430 系统级 ESD 注
意事项》。
版权 © 2018–2019, Texas Instruments Incorporated
器件概述
3
MSP430FR2522, MSP430FR2512
ZHCSHB4C –JANUARY 2018–REVISED DECEMBER 2019
www.ti.com.cn
1.4 功能框图
图 1-1 给出了功能框图。
XIN XOUT
P1.x/P2.x
FRAM
RAM
2KB
MPY32
32-bit
Hardware Redundancy
Multiplier
CRC16
I/O Ports
P1 : 8 IOs
P2 : 7 IOs
Interrupt,
Wakeup,
CapTIvate
DVCC
DVSS
LFXT
Power
Management
Module
16-bit
Cyclic
8 channels
(FR2522)
4 channels
(FR2512)
Clock
System
RST/NMI
VREG
7.25KB
+256B
Check
PA : 15 IOs
MAB
MDB
16-MHz CPU
including
16 registers
EEM
RTC
Counter
eUSCI_A0
2 × TA
eUSCI_B0
(SPI, I2C)
ADC
BAKMEM
SYS
TCK
TMS
8 channels
Single-end
10 bit
32-bytes
Backup
Memory
16-bit
Real-Time
Clock
Timer_A3
3 CC
Registers
JTAG
SBW
TDI/TCLK
TDO
(UART,
IrDA, SPI)
Watchdog
200 ksps
SBWTCK
SBWTDIO
LPM3.5 Domain
Copyright © 2017, Texas Instruments Incorporated
图 1-1. 功能框图
•
•
MCU 的主电源对 DVCC 和 DVSS 分别为数字模块和模拟模块供电。推荐的旁路电容和去耦电容分别为
4.7μF 至 10μF 和 0.1μF，精度为 ±5%。
VREG 是 CapTIvate 稳压器的去耦电容。所需去耦电容的建议值为 1µF，最大等效串联电阻 (ESR) ≤
200mΩ。
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•
P1 和 P2 特有引脚中断功能，可将 MCU 从所有低功耗模式 (LPM) 唤醒（包括 LPM3.5 和 LPM4）。
每个 Timer_A3 具有三个捕捉/比较寄存器。仅 CCR1 和 CCR2 从外部连接。CCR0 寄存器仅用于内部周
期时序和生成中断。
•
在 LPM3 或 LPM4 模式下，CapTIvate 模块可以正常工作，而其他外设则会关闭。
4
器件概述
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2522, MSP430FR2512
www.ti.com.cn
ZHCSHB4C –JANUARY 2018–REVISED DECEMBER 2019
内容
1
器件概述.................................................... 1
6.1 Overview ............................................ 43
6.2 CPU ................................................. 43
6.3 Operating Modes.................................... 43
6.4 Interrupt Vector Addresses.......................... 44
6.5 Bootloader (BSL).................................... 46
6.6 JTAG Standard Interface............................ 46
6.7 Spy-Bi-Wire Interface (SBW)........................ 47
6.8 FRAM................................................ 47
6.9 Memory Protection .................................. 47
6.10 Peripherals .......................................... 47
6.11 Input/Output Diagrams .............................. 56
6.12 Device Descriptors .................................. 60
6.13 Memory.............................................. 61
6.14 Identification ......................................... 69
Applications, Implementation, and Layout........ 70
1.1 特性 ................................................... 1
1.2 应用 ................................................... 2
1.3 说明 ................................................... 2
1.4 功能框图 .............................................. 4
修订历史记录............................................... 6
Device Comparison ..................................... 7
3.1 Related Products ..................................... 7
Terminal Configuration and Functions.............. 8
4.1 Pin Diagrams ......................................... 8
4.2 Pin Attributes ........................................ 10
4.3 Signal Descriptions.................................. 12
4.4 Pin Multiplexing ..................................... 15
4.5 Buffer Types......................................... 15
4.6 Connection of Unused Pins ......................... 15
Specifications ........................................... 16
5.1 Absolute Maximum Ratings......................... 16
5.2 ESD Ratings ........................................ 16
5.3 Recommended Operating Conditions............... 16
2
3
4
7
8
5
7.1
Device Connection and Layout Fundamentals...... 70
7.2
Peripheral- and Interface-Specific Design
Information .......................................... 73
7.3 CapTIvate Technology Evaluation .................. 76
器件和文档支持 .......................................... 77
8.1 入门和后续步骤...................................... 77
8.2 器件命名规则 ........................................ 77
8.3 工具和软件 .......................................... 78
8.4 文档支持............................................. 80
8.5 相关链接............................................. 81
8.6 社区资源............................................. 81
8.7 商标.................................................. 81
8.8 静电放电警告 ........................................ 82
8.9 Export Control Notice ............................... 82
8.10 Glossary ............................................. 82
机械、封装和可订购信息................................ 83
5.4
Active Mode Supply Current Into VCC Excluding
External Current..................................... 17
5.5 Active Mode Supply Current Per MHz .............. 17
5.6
5.7
5.8
5.9
Low-Power Mode (LPM0) Supply Currents Into VCC
Excluding External Current.......................... 17
Low-Power Mode (LPM3, LPM4) Supply Currents
(Into VCC) Excluding External Current .............. 18
Low-Power Mode (LPMx.5) Supply Currents (Into
VCC) Excluding External Current.................... 20
Typical Characteristics - Low-Power Mode Supply
Currents ............................................. 21
5.10 Thermal Resistance Characteristics ................ 22
5.11 Timing and Switching Characteristics............... 22
Detailed Description ................................... 43
9
6
版权 © 2018–2019, Texas Instruments Incorporated
内容
5
MSP430FR2522, MSP430FR2512
ZHCSHB4C –JANUARY 2018–REVISED DECEMBER 2019
www.ti.com.cn
2 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
从修订版本 B 更改为修订版本 C
Changes from August 20, 2019 to December 10, 2019
Page
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Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in
Section 5.3, Recommended Operating Conditions ............................................................................. 16
Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in
Section 5.3, Recommended Operating Conditions ............................................................................. 16
Changed the note that begins "A capacitor tolerance of ±20% or better is required..." in Section 5.3,
Recommended Operating Conditions ............................................................................................ 16
Added the note "See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing" to
Table 5-4, XT1 Crystal Oscillator (Low Frequency) ............................................................................ 24
Changed the note that begins "Requires external capacitors at both terminals..." in Table 5-4, XT1 Crystal
Oscillator (Low Frequency) ........................................................................................................ 24
Added the tTA,cap parameter in Table 5-13, Timer_A............................................................................ 30
Corrected the test conditions for the RI parameter in Table 5-20, ADC, Power Supply and Input Range Conditions. 37
Added the note that begins "tSample = ln(2n+1) × τ ..." in Table 5-21, ADC, 10-Bit Timing Parameters.................... 37
Changed the CRC covered end address to 0x1AF5 in note (1) in Table 6-18, Device Descriptors ..................... 60
Added "1.5-V reference factor" in Table 6-18, Device Descriptors .......................................................... 61
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从修订版本 A 更改为修订版本 B
Changes from November 8, 2018 to August 19, 2019
Page
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•
更新了节 1.1特性...................................................................................................................... 1
Changed CapTIvate BSWP demonstration board to CapTIvate phone demonstration board in note (11) on
Section 5.7, Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current ................ 18
Changed CapTIvate BSWP demonstration board to CapTIvate phone demonstration board in note (19) on
Section 5.7, Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current ................ 19
Added the tTA,cap parameter in Table 5-13, Timer_A............................................................................ 30
Moved CREG and CELECTRODE from Section 5.3, Recommended Operating Conditions to Table 5-23, CapTIvate
Electrical Characteristics ........................................................................................................... 39
Added test condition for CELECTRODE in Table 5-23 , CapTIvate Electrical Characteristics................................. 39
Changed the symbol and description of the DCCAPCLK parameter in Table 5-23, CapTIvate Electrical
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Characteristics ...................................................................................................................... 39
Moved the SNR parameter to Table 5-24, CapTIvate Signal-to-Noise Ratio Characteristics ............................ 39
Updated Section 7.2.2, CapTIvate Peripheral .................................................................................. 74
更新了节 8.2，器件命名规则....................................................................................................... 77
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从初始发行版更改为修订版本 A
Changes from January 12, 2018 to November 7, 2018
Page
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删除了节 1.1，特性 中“接近感应”项的“15cm” .................................................................................... 1
更改了 节 1.1，特性 中的列表项“3.6V 至 1.8V 的宽电源电压范围...”.......................................................... 1
Updated Section 3.1, Related Products ........................................................................................... 7
Changed HBM limit to ±1000 V and CDM limit to ±250 V in Section 5.2, ESD Ratings................................... 16
Changed the MIN value of the VCC parameter from 2 V to 1.8 V in Section 5.3, Recommended Operating
Conditions ............................................................................................................................ 16
Changed the crystal in the footnote that begins "Characterized with a Seiko Crystal SC-32S crystal..." in
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Section 5.7, Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current................. 18
Changed the crystal in the footnote that begins "Characterized with a Seiko Crystal SC-32S crystal..." in
Section 5.8, Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current ....................... 20
Added note on VSVSH- and VSVSH+ parameters to Table 5-2, PMM, SVS and BOR......................................... 22
6
修订历史记录
版权 © 2018–2019, Texas Instruments Incorporated
MSP430FR2522, MSP430FR2512
www.ti.com.cn
ZHCSHB4C –JANUARY 2018–REVISED DECEMBER 2019
•
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Changed the minimum VCC from 2.0 V to 1.8 V in the test conditions for the fREFO, dfREFO/ dVCC, and fDC
parameters and in note (2) in Table 5-7, REFO................................................................................. 26
Changed the minimum VCC from 2.0 V to 1.8 V in the test conditions for the dfVLO/dVCC parameter and in note
(2) in Table 5-8, Internal Very-Low-Power Low-Frequency Oscillator (VLO)................................................ 27
Changed the minimum VCC from 2.0 V to 1.8 V in the test conditions for the fMODOSC/dVCC parameter in Table 5-
9, Module Oscillator (MODOSC) ................................................................................................. 27
Added the tTA,cap parameter in Table 5-13, Timer_A............................................................................ 30
Added the SNR parameter in Table 5-23, CapTIvate Electrical Characteristics ........................................... 39
Corrected bitfield from RTCCLK to RTCCKSEL in table note that starts "Controlled by ..." in Table 6-8, Clock
Distribution .......................................................................................................................... 48
Corrected bitfield from IRDSEL to IRDSSEL in Section 6.10.8, Timers (Timer0_A3, Timer1_A3), in the
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description that starts "The interconnection of Timer0_A3 and ..." ........................................................... 53
Corrected ADCINCHx column heading in Table 6-13, ADC Channel Connections ....................................... 54
Corrected ADCINCHx column heading in Table 6-13, ADC Channel Connections ....................................... 55
Added P1SELC information in Table 6-28, Port P1, P2 Registers (Base Address: 0200h)............................... 64
Added P2SELC information in Table 6-28, Port P1, P2 Registers (Base Address: 0200h) .............................. 64
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Copyright © 2018–2019, Texas Instruments Incorporated
修订历史记录
7
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Product Folder Links: MSP430FR2522 MSP430FR2512
MSP430FR2522, MSP430FR2512
ZHCSHB4C –JANUARY 2018–REVISED DECEMBER 2019
www.ti.com.cn
3 Device Comparison
Table 3-1 summarizes the features of the available family members.
Table 3-1. Device Comparison(1)(2)
PROGRAM
FRAM +
INFORMATION
FRAM (bytes)
CapTIvate
TECHNOLOG
Y
SRAM
(bytes)
10-BIT ADC
CHANNELS
DEVICE
TA0,TA1
eUSCI_A
eUSCI_B
GPIOs
PACKAGE
CHANNELS
20 RHL
(VQFN)
MSP430FR2522IRHL
MSP430FR2522IPW16
MSP430FR2512IRHL
MSP430FR2512IPW16
7424 + 256
7424 + 256
7424 + 256
7424 + 256
2048
2048
2048
2048
2, 3 × CCR(3)
2, 3 × CCR(3)
2, 3 × CCR(3)
2, 3 × CCR(3)
1
1
1
1
1
1
1
1
8
5
8
5
8
8
4
4
15
11
15
11
16 PW
(TSSOP)
20 RHL
(VQFN)
16 PW
(TSSOP)
(1) For the most current package and ordering information, see the Package Option Addendum in 节 9, or see the TI website at www.ti.com
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging
(3) A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM
outputs.
3.1 Related Products
For information about other devices in this family of products or related products, see the following links.
TI 16-bit and 32-bit microcontrollers
High-performance, low-power solutions to enable the autonomous future
Products for MSP430 ultra-low-power sensing and measurement microcontrollers
One platform. One ecosystem. Endless possibilities.
Companion Products for MSP430FR2522
Review products that are frequently purchased or used in conjunction with this product.
Reference Designs
Find reference designs leveraging the best in TI technology to solve your system-level challenges
8
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4 Terminal Configuration and Functions
4.1 Pin Diagrams
Figure 4-1 shows the pinout for the 20-pin RHL package.
19 18 17 16 15 14 13 12
20
11
10
P2.4/TA1CLK/UCB0CLK/A6
P1.2/UCB0SIMO/UCB0SDA/SMCLK/A2/Veref-/CAP1.2
P1.1/UCB0CLK/ACLK/A1/VREF+/CAP1.1
MSP430FR2522IRHL
MSP430FR2512IRHL
1
P2.5/UCB0SIMO/UCB0SDA/A7
2
3
4
5
6
7
8
9
NOTE: CAP1.x are available only on MSP430FR2522 device and NOT available on MSP430FR2512 device.
Figure 4-1. 20-Pin RHL Package (Top View)
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Figure 4-2 shows the pinout for the 16-pin PW package.
P1.1/UCB0CLK/ACLK/A1/VREF+/CAP1.1
P1.0/UCB0STE/A0/Veref+/CAP1.0
TEST/SBWTCK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P1.2/UCB0SIMO/UCB0SDA/SMCLK/A2/Veref-/CAP1.2
P1.3/UCB0SOMI/UCB0SCL/MCLK/A3/CAP1.3
VREG
P1.4/UCA0TXD/UCA0SIMO/TA0.1/TCK/CAP0.0
P1.5/UCA0RXD/UCA0SOMI/TA0.2/TMS/CAP0.1
P1.6/UCA0CLK/TA0CLK/TDI/TCLK/CAP0.2
P1.7/UCA0STE/TDO/CAP0.3
RST/NMI/SBWTDIO
MSP430FR2522IPW16
MSP430FR2512IPW16
DVCC
DVSS
P2.1/UCA0RXD/UCA0SOMI/XIN
P2.0/UCA0TXD/UCA0SIMO/XOUT
P2.2/TA1.1/SYNC/A4
NOTE: CAP1.x are available only on MSP430FR2522 device and NOT available on MSP430FR2512 device.
Figure 4-2. 16-Pin PW Package (Top View)
10
Terminal Configuration and Functions
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4.2 Pin Attributes
Table 4-1 lists the attributes of all pins.
Table 4-1. Pin Attributes
PIN NUMBER
RHL PW16
SIGNAL
RESET STATE
SIGNAL NAME(1) (2)
BUFFER TYPE(4)
POWER SOURCE(5)
TYPE(3)
AFTER BOR(6)
P1.1 (RD)
UCB0CLK
ACLK
I/O
I/O
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
VREG
OFF
–
–
1
1
CAP1.1(7)
–
A1
Analog
DVCC
Power
DVCC
DVCC
VREG
–
VREF+
I
Analog
–
P1.0 (RD)
UCB0STE
CAP1.0(7)
A0
I/O
I/O
I/O
I
LVCMOS
LVCMOS
Analog
OFF
–
2
2
–
Analog
DVCC
Power
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
–
Veref+
I
Analog
–
TEST (RD)
SBWTCK
RST (RD)
NMI
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Power
OFF
–
3
4
3
4
I
I
OFF
–
I
SBWTDIO
DVCC
I/O
P
–
5
6
5
6
N/A
N/A
OFF
–
DVSS
P
Power
P2.1 (RD)
UCA0RXD
UCA0SOMI
XIN
I/O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
7
7
I/O
I
–
–
P2.0 (RD)
UCA0TXD
UCA0SIMO
XOUT
I/O
O
OFF
–
8
9
8
–
–
I/O
O
–
–
P2.6 (RD)
UCB0SOMI
UCB0SCL
P2.5 (RD)
UCB0SIMO
UCB0SDA
A7
I/O
I/O
I/O
I/O
I/O
I/O
I
OFF
–
–
OFF
–
10
–
–
P2.4 (RD)
TA1CLK
UCB0CLK
A6
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
11
–
I/O
I
–
–
(1) Signals names with (RD) denote the reset default pin name.
(2) To determine the pin mux encodings for each pin, see Section 6.11.
(3) Signal Types: I = Input, O = Output, I/O = Input or Output
(4) Buffer Types: LVCMOS, Analog, or Power (see Table 4-3)
(5) The power source shown in this table is the I/O power source, which may differ from the module power source.
(6) Reset States:
OFF = High-impedance with Schmitt trigger and pullup or pulldown (if available) disabled
N/A = Not applicable
(7) MSP430FR2522 only
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Table 4-1. Pin Attributes (continued)
PIN NUMBER
RHL PW16
SIGNAL
TYPE(3)
RESET STATE
SIGNAL NAME(1) (2)
BUFFER TYPE(4)
POWER SOURCE(5)
AFTER BOR(6)
P2.3 (RD)
TA1.2
I/O
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
VREG
OFF
–
12
–
UCB0STE
A5
–
–
P2.2 (RD)
TA1.1
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
13
14
9
SYNC
–
A4
I
–
P1.7 (RD)
UCA0STE
TDO
I/O
I/O
O
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
–
10
CAP0.3
P1.6 (RD)
UCA0CLK
TA0CLK
TDI
I/O
I/O
I/O
I
–
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
VREG
OFF
–
–
15
16
11
12
I
–
TCLK
I
–
CAP0.2
P1.5 (RD)
UCA0RXD
UCA0SOMI
TA0.2
I/O
I/O
I
–
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
VREG
OFF
–
I/O
I/O
I
–
–
TMS
–
CAP0.1
P1.4 (RD)
UCA0TXD
UCA0SIMO
TA0.1
I/O
I/O
O
–
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
VREG
OFF
–
I/O
I/O
I
–
17
18
19
13
14
15
–
TCK
–
CAP0.0
VREG
I/O
P
–
Power
VREG
N/A
OFF
–
P1.3 (RD)
UCB0SOMI
UCB0SCL
MCLK
I/O
I/O
I/O
O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
VREG
–
–
CAP1.3(7)
I/O
I
–
A3
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
VREG
–
P1.2 (RD)
UCB0SIMO
UCB0SDA
SMCLK
CAP1.2(7)
A2
I/O
I/O
I/O
O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
–
20
16
–
I/O
I
–
Analog
DVCC
Power
–
Veref-
I
Analog
–
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4.3 Signal Descriptions
Table 4-2 describes the signals for all device variants and package options.
Table 4-2. Signal Descriptions
PIN NUMBER
PIN
FUNCTION
SIGNAL NAME
DESCRIPTION
TYPE(1)
RHL
2
PW
2
A0
A1
A2
A3
A4
A5
A6
A7
I
Analog input A0
1
1
I
I
Analog input A1
20
19
13
12
11
10
2
16
15
9
Analog input A2
I
Analog input A3
I
Analog input A4
ADC
–
I
Analog input A5
–
I
Analog input A6
–
I
Analog input A7
Veref+
2
I
ADC positive reference
ADC negative reference
CapTIvate channel
CapTIvate channel
CapTIvate channel
CapTIvate channel
CapTIvate channel
CapTIvate channel
CapTIvate channel
CapTIvate channel
Veref-
20
17
16
15
14
2
16
13
12
11
10
2
I
CAP0.0
CAP0.1
CAP0.2
CAP0.3
CAP1.0(2)
CAP1.1(2)
CAP1.2(2)
CAP1.3(2)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CapTIvate
1
1
20
19
16
15
CapTIvate synchronous trigger input for processing and
conversion
SYNC
13
9
I
ACLK
MCLK
SMCLK
XIN
1
19
20
7
1
15
16
7
I/O
O
O
I
ACLK output
MCLK output
Clock
SMCLK output
Input terminal for crystal oscillator
Output terminal for crystal oscillator
Spy-Bi-Wire input clock
Spy-Bi-Wire data input/output
Test clock
XOUT
SBWTCK
SBWTDIO
TCK
8
8
O
I
3
3
4
4
I/O
I
17
15
15
14
3
13
11
11
10
3
TCLK
TDI
I
Test clock input
Debug
I
Test data input
TDO
O
I
Test data output
TEST
TMS
Test mode pin – selected digital I/O on JTAG pins
Test mode select
16
12
I
(1) Pin Types: I = Input, O = Output, I/O = Input or Output, P = Power
(2) MSP430FR2522 only
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Table 4-2. Signal Descriptions (continued)
PIN NUMBER
PIN
FUNCTION
SIGNAL NAME
P1.0
DESCRIPTION
TYPE(1)
RHL
2
PW
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O(3)
General-purpose I/O(3)
General-purpose I/O(3)
General-purpose I/O(3)
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
1
1
20
19
17
16
15
14
16
15
13
12
11
10
GPIO
P2.0
8
8
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
eUSCI_B0 I2C clock
eUSCI_B0 I2C data
P2.1
7
P2.2
13
12
11
10
9
9
P2.3
–
P2.4
–
P2.5
–
P2.6
–
UCB0SCL(4)
UCB0SDA(4)
19
20
15
16
I2C
UCB0SCL(4)
UCB0SDA(4)
DVCC
9
10
5
–
–
I/O
I/O
P
eUSCI_B0 I2C clock
eUSCI_B0 I2C data
Power supply
5
DVSS
6
6
P
Power ground
Power
VREF+
1
1
P
Output of positive reference voltage with ground as reference
CapTIvate regulator external decoupling capacitor
eUSCI_A0 SPI slave transmit enable
eUSCI_A0 SPI clock input/output
VREG
18
14
15
16
17
7
14
10
11
12
13
7
O
UCA0STE
I/O
I/O
I/O
I/O
I/O
I/O
UCA0CLK
UCA0SOMI(4)(5)
UCA0SIMO(4)(5)
UCA0SOMI(4)(5)
UCA0SIMO(4)(5)
eUSCI_A0 SPI slave out/master in
eUSCI_A0 SPI slave in/master out
eUSCI_A0 SPI slave out/master in
8
8
eUSCI_A0 SPI slave in/master out
UCB0STE(4)
UCB0CLK(4)
UCB0SOMI(4)
UCB0SIMO(4)
2
1
2
1
I/O
I/O
I/O
I/O
eUSCI_B0 slave transmit enable
eUSCI_B0 clock input/output
SPI
19
20
15
16
eUSCI_B0 SPI slave out/master in
eUSCI_B0 SPI slave in/master out
UCB0STE(4)
UCB0CLK(4)
UCB0SOMI(4)
UCB0SIMO(4)
NMI
12
11
9
–
–
–
–
4
4
I/O
I/O
I/O
I/O
I
eUSCI_B0 slave transmit enable
eUSCI_B0 clock input/output
eUSCI_B0 SPI slave out/master in
eUSCI_B0 SPI slave in/master out
Nonmaskable interrupt input
Active-low reset input
10
4
System
RST
4
I
(3) Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to
prevent collisions.
(4) These signal assignments are controlled by the USCIARMP bit of the SYSCFG3 register or the USCIBRMP bit of the SYSCFG2
register. Only one group can be selected at one time.
(5) Signal assignments on these pins are controlled by the remap functionality and are selected by the USCIARMP bit in the SYSCFG3
register. Only one group can be selected at one time. The CLK and STE assignments are fixed and shared by both SPI function groups.
14
Terminal Configuration and Functions
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Table 4-2. Signal Descriptions (continued)
PIN NUMBER
PIN
SIGNAL NAME
TA0.1
DESCRIPTION
TYPE(1)
RHL
17
PW
13
I/O
I/O
I
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 outputs
Timer TA0 CCR2 capture: CCI2A input, compare: Out2 outputs
Timer clock input TACLK for TA0
TA0.2
16
12
TA0CLK
15
11
Timer_A
TA1.1
13
12
11
16
17
9
–
I/O
I/O
I
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 outputs
Timer TA1 CCR2 capture: CCI2A input, compare: Out2 outputs
Timer clock input TACLK for TA1
TA1.2
TA1CLK
UCA0RXD(4)
UCA0TXD(4)
–
12
13
I
eUSCI_A0 UART receive data
O
eUSCI_A0 UART transmit data
UART
UCA0RXD(4)
UCA0TXD(4)
7
8
7
8
I
eUSCI_A0 UART receive data
O
eUSCI_A0 UART transmit data
QFN package exposed thermal pad. TI recommends connecting to
QFN Pad
QFN thermal pad
Pad
–
–
VSS
.
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4.4 Pin Multiplexing
Pin multiplexing for this MCU is controlled by both register settings and operating modes (for example, if
the MCU is in test mode). For details of the settings for each pin and diagrams of the multiplexed ports,
see Section 6.11.
4.5 Buffer Types
Table 4-3 defines the pin buffer types that are listed in Table 4-1
Table 4-3. Buffer Types
NOMINAL
OUTPUT
DRIVE
STRENGTH
(mA)
BUFFER TYPE
(STANDARD)
NOMINAL
VOLTAGE
PU OR PD
STRENGTH
(µA)
OTHER
CHARACTERISTICS
HYSTERESIS
PU OR PD
See
Section 5.11.4
See
Section 5.11.4
LVCMOS
Analog
3.0 V
3.0 V
Y(1)
N
Programmable
N/A
See analog modules in
Section 5 for details.
N/A
N/A
SVS enables hysteresis on
DVCC.
Power (DVCC)
Power (AVCC)
3.0 V
3.0 V
N
N
N/A
N/A
N/A
N/A
N/A
N/A
(1) Only for input pins.
4.6 Connection of Unused Pins
Table 4-4 lists the correct termination of unused pins.
Table 4-4. Connection of Unused Pins(1)
PIN
POTENTIAL
COMMENT
Switched to port function, output direction (PxDIR.n = 1)
47-kΩ pullup or internal pullup selected with 10-nF (or 1.1-nF) pulldown(2)
Px.0 to Px.7
RST/NMI
TEST
Open
DVCC
Open
This pin always has an internal pull-down enabled.
(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection
guidelines.
(2) The pulldown capacitor should not exceed 1.1 nF when using MCUs with Spy-Bi-Wire interface in Spy-Bi-Wire mode with TI tools like
FET interfaces or GANG programmers.
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5 Specifications
5.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
MAX
4.1
UNIT
V
Voltage applied at DVCC pin to VSS
(2)
Voltage applied to any pin in CapTIvate mode
VREG
V
VCC + 0.3
(4.1 V Max)
Voltage applied to any other pin(3)
–0.3
V
Diode current at any device pin
±2
85
mA
°C
Maximum junction temperature, TJ
(4)
Storage temperature, Tstg
–40
125
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) This applies I/Os worked in CapTIvate mode.
(3) All voltages referenced to VSS
.
(4) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS‑001(1)
Charged-device model (CDM), per JEDEC specification JESD22‑C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3 Recommended Operating Conditions
MIN
NOM
MAX UNIT
VCC
VSS
TA
Supply voltage applied at DVCC pin(1)(2)(3)(4)
Supply voltage applied at DVSS pin
Operating free-air temperature
1.8
3.6
V
V
0
–40
–40
4.7
85
85
°C
°C
µF
TJ
Operating junction temperature
Recommended capacitor at DVCC(5)
CDVCC
10
No FRAM wait states
(NWAITSx = 0)
0
0
8
fSYSTEM
Processor frequency (maximum MCLK frequency)(4)(6)
MHz
With FRAM wait states
(NWAITSx = 1)(7)
16(8)
fACLK
Maximum ACLK frequency
Maximum SMCLK frequency
40
16(8)
kHz
fSMCLK
MHz
(1) Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range. Following the
data sheet recommendation for capacitor CDVCC limits the slopes accordingly.
(2) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(3) TI recommends that power to the DVCC pin must not exceed the limits specified in Recommended Operating Conditions. Exceeding the
specified limits can cause malfunction of the device including erroneous writes to RAM and FRAM.
(4) The minimum supply voltage is defined by the SVS levels. See the SVS threshold parameters in Table 5-2.
(5) A capacitor tolerance of ±20% or better is required. A low-ESR ceramic capacitor of 100 nF (minimum) should be placed as close as
possible (within a few millimeters) to the respective pin pair.
(6) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(7) Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executed
without wait states.
(8) If clock sources such as HF crystals or the DCO with frequencies >16 MHz are used, the clock must be divided in the clock system to
comply with this operating condition.
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5.4 Active Mode Supply Current Into VCC Excluding External Current
(1)
See
FREQUENCY (fMCLK = fSMCLK
8 MHz
)
1 MHz
16 MHz
EXECUTION
MEMORY
TEST
CONDITION
PARAMETER
0 WAIT STATES
(NWAITSx = 0)
0 WAIT STATES
(NWAITSx = 0)
1 WAIT STATE
(NWAITSx = 1)
UNIT
TYP
454
471
191
MAX
TYP
2620
2700
573
MAX
TYP
2935
2980
950
MAX
3 V, 25°C
3 V, 85°C
3 V, 25°C
FRAM
0% cache hit ratio
IAM, FRAM(0%)
µA
3250
FRAM
100% cache hit
ratio
IAM, FRAM(100%)
µA
µA
3 V, 85°C
3 V, 25°C
199
216
592
772
974
1200
(2)
IAM, RAM
RAM
1300
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. Characterized with program executing typical data
processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency
Program and data entirely reside in FRAM. All execution is from FRAM.
(2) Program and data reside entirely in RAM. All execution is from RAM. No access to FRAM.
5.5 Active Mode Supply Current Per MHz
VCC = 3 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
UNIT
µA/MHz
Active mode current consumption per MHz,
execution from FRAM, no wait states
[IAM (75% cache hit rate) at 8 MHz –
IAM (75% cache hit rate) at 1 MHz) / 7 MHz
dIAM,FRAM/df
120
5.6 Low-Power Mode (LPM0) Supply Currents Into VCC Excluding External Current
VCC = 3 V, TA = 25°C (unless otherwise noted)(1)(2)
FREQUENCY (fSMCLK
8 MHz
)
PARAMETER
VCC
1 MHz
TYP
16 MHz
TYP MAX
UNIT
MAX
TYP
292
300
MAX
2 V
3 V
145
155
395
394
ILPM0
µA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Current for watchdog timer clocked by SMCLK included.
fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK at specified frequency.
18
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5.7 Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
–40°C
TYP MAX
25°C
TYP
85°C
TYP
PARAMETER
VCC
UNIT
MAX
MAX
3 V
2 V
3 V
2 V
3 V
0.96
0.93
0.77
0.75
0.90
1.11
1.08
0.92
0.90
1.05
2.75
2.78
2.66
2.60
2.77
6.2
Low-power mode 3, 12.5-pF crystal, includes
SVS(2)(3)(4)
ILPM3,XT1
µA
6.0
ILPM3,VLO
Low-power mode 3, VLO, excludes SVS(5)
Low-power mode 3, RTC, excludes SVS(6)
µA
µA
ILPM3, RTC
ILPM3, CapTIvate,
1 proximity, wake on
touch
Low-power mode 3, CapTIvate , excludes SVS(7)
Low-power mode 3, CapTIvate , excludes SVS(8)
Low-power mode 3, CapTIvate, excludes SVS(9)
3 V
3 V
3 V
4.7
3.0
3.2
µA
µA
µA
ILPM3, CapTIvate,
1 button, wake on
touch
ILPM3, CapTIvate,
2 buttons, wake on
touch
ILPM3, CapTIvate,
8 buttons
Low-power mode 3, CapTIvate, excludes SVS(10)
Low-power mode 3, CapTIvate, excludes SVS(11)
3 V
3 V
17
38
µA
µA
ILPM3, CapTIvate,
16 buttons
3 V
2 V
3 V
2 V
0.51
0.49
0.35
0.34
0.64
0.61
0.48
0.46
2.30
2.25
2.13
2.10
ILPM4, SVS
Low-power mode 4, includes SVS(12)
Low-power mode 4, excludes SVS(12)
µA
µA
ILPM4
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Not applicable for MCUs with HF crystal oscillator only.
(3) Characterized with a Seiko Crystal SC-32S crystal with a load capacitance chosen to closely match the required load.
(4) Low-power mode 3, 12.5-pF crystal, includes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Low-power mode 3, VLO, excludes SVS test conditions:
Current for watchdog timer clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3)
fXT1 = 32768 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
(6) RTC periodically wakes up every second with external 32768-Hz input as source.
(7) CapTIvate technology works in LPM3 with one proximity sensor for wake on touch. CapTIvate BSWP demonstration board with 1.5-mm
overlay. Current for brownout included. SVS disabled (SVSHE = 0).
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 800
(8) CapTIvate technology works in LPM3 with one button, wake on touch.CapTIvate BSWP demonstration board with 1.5-mm overlay,
Current for brownout included. SVS disabled (SVSHE = 0).
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250
(9) CapTIvate technology works in LPM3 with two self-capacitance buttons, wake on touch. CapTIvate BSWP demonstration board with
1.5-mm overlay. Current for brownout included. SVS disabled (SVSHE = 0).
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250
(10) CapTIvate technology works in LPM3 with 8 self-capacitance buttons. The CPU enters active mode in between time cycles to configure
the conversions and read the results. CapTIvate BSWP demonstration board with 1.5-mm overlay. Current for brownout included. SVS
disabled (SVSHE = 0).
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250
(11) CapTIvate technology works in LPM3 with 16 mutual-capacitance buttons. The CPU enters active mode in between time cycles to
configure the conversions and read the results. CapTIvate phone demonstration board with 1.5-mm overlay. Current for brownout
included. SVS disabled (SVSHE = 0).
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250
(12) Low-power mode 4, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4), CPU and all clocks are disabled, WDT and RTC
disabled
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Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External
Current (continued)
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
–40°C
TYP MAX
25°C
TYP
85°C
PARAMETER
VCC
UNIT
MAX
MAX
TYP
2.21
2.19
2.68
2.64
3 V
2 V
3 V
2 V
0.43
0.42
0.80
0.79
0.56
0.55
0.96
0.94
Low-power mode 4, RTC is soured from VLO,
excludes SVS(13)
ILPM4,VLO
µA
µA
Low-power mode 4, RTC is soured from XT1,
excludes SVS(14)
ILPM4,XT1
ILPM4, CapTIvate,
1 proximity, wake on
touch
Low-power mode 4, CapTIvate , excludes SVS(15)
Low-power mode 4, CapTIvate , excludes SVS(16)
Low-power mode 4, CapTIvate, excludes SVS(17)
3 V
3 V
3 V
4.5
2.7
2.9
µA
µA
µA
ILPM4, CapTIvate,
1 button, wake on
touch
ILPM4, CapTIvate,
2 buttons, wake on
touch
ILPM4, CapTIvate,
8 buttons
Low-power mode 4, CapTIvate, excludes SVS(18)
Low-power mode 4, CapTIvate, excludes SVS(19)
3 V
3 V
18
39
µA
µA
ILPM4, CapTIvate,
16 buttons
(13) Low-power mode 4, VLO, excludes SVS test conditions:
Current for RTC clocked by VLO included. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4)
fXT1 = 0 Hz, fMCLK = fSMCLK = 0 MHz
(14) Low-power mode 4, XT1, excludes SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4)
fXT1 = 32768 Hz, fMCLK = fSMCLK = 0 MHz
(15) CapTIvate technology works in LPM4 with one proximity sensor for wake on touch. CapTIvate BSWP demonstration board with 1.5-mm
overlay. Current for brownout included. SVS disabled (SVSHE = 0). The VLO (10 kHz) sources the CapTIvate timer, no external crystal.
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 800
(16) CapTIvate technology works in LPM4 with one button, wake on touch. CapTIvate BSWP demonstration board with 1.5-mm overlay,
Current for brownout included. SVS disabled (SVSHE = 0). The VLO (10 kHz) sources the CapTIvate timer, no external crystal.
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250
(17) CapTIvate technology works in LPM4 with two self-capacitance buttons, wake on touch. CapTIvate BSWP demonstration board with
1.5-mm overlay. Current for brownout included. SVS disabled (SVSHE = 0). VLO (10 kHz) sources the CapTIvate timer, no external
crystal.
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250
(18) CapTIvate technology works in LPM4 with 8 self-capacitance buttons. The CPU enters active mode in between time cycles to configure
the conversions and read the results. CapTIvate BSWP demonstration board with 1.5-mm overlay. Current for brownout included. SVS
disabled (SVSHE = 0). The VLO (10 kHz) sources the CapTIvate timer, no external crystal.
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250
(19) CapTIvate technology works in LPM4 with 16 mutual-capacitance buttons. The CPU enters active mode in between time cycles to
configure the conversions and read the results. CapTIvate phone demonstration board with 1.5-mm overlay. Current for brownout
included. SVS disabled (SVSHE = 0). The VLO (10 kHz) sources the CapTIvate timer, no external crystal.
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250
20
Specifications
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5.8 Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
–40°C
TYP MAX
25°C
TYP
85°C
TYP
PARAMETER
VCC
UNIT
MAX
MAX
Low-power mode 3.5, 12.5-pF crystal, includes
SVS(1)(2) (3)
(also see Figure 5-3)
3 V
2 V
0.57
0.54
0.63
0.60
0.81
0.79
1.54
ILPM3.5, XT1
µA
3 V
2 V
3 V
2 V
0.23
0.21
0.25
0.23
0.31
0.29
0.45
0.15
ILPM4.5, SVS
Low-power mode 4.5, includes SVS(4)
Low-power mode 4.5, excludes SVS(5)
µA
µA
0.027
0.022
0.036
0.031
0.080
0.073
ILPM4.5
(1) Not applicable for MCUs with HF crystal oscillator only.
(2) Characterized with a Seiko Crystal SC-32S crystal with a load capacitance chosen to closely match the required load.
(3) Low-power mode 3.5, 12.5-pF crystal, includes SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = 0, fMCLK = fSMCLK = 0 MHz
(4) Low-power mode 4.5, includes SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5)
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
(5) Low-power mode 4.5, excludes SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5)
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
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5.9 Typical Characteristics - Low-Power Mode Supply Currents
VCC = 3 V
RTC enabled
SVS disabled
VCC = 3 V
RTC enabled
SVS disabled
Figure 5-1. LPM3 Supply Current vs Temperature
Figure 5-2. LPM4 Supply Current vs Temperature
VCC = 3 V
XT1 enabled
SVS enabled
VCC = 3 V
SVS enabled
Figure 5-3. LPM3.5 Supply Current vs Temperature
Figure 5-4. LPM4.5 Supply Current vs Temperature
Table 5-1. Typical Characteristics – Current Consumption Per Module
MODULE
Timer_A
TEST CONDITIONS
REFERENCE CLOCK
Module input clock
MIN
TYP
5
MAX
UNIT
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
nA
eUSCI_A
eUSCI_A
eUSCI_B
eUSCI_B
RTC
UART mode
Module input clock
Module input clock
Module input clock
Module input clock
32 kHz
7
SPI mode
5
SPI mode
5
I2C mode, 100 kbaud
5
85
8.5
CRC
From start to end of operation
MCLK
µA/MHz
22
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5.10 Thermal Resistance Characteristics
THERMAL METRIC(1)
VALUE(2)
37.8
UNIT
VQFN 20 pin (RHL)
TSSOP 16 pin (PW16)
VQFN 20 pin (RHL)
TSSOP 16 pin (PW16)
VQFN 20 pin (RHL)
TSSOP 16 pin (PW16)
RθJA
RθJC
RθJB
Junction-to-ambient thermal resistance, still air
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ºC/W
101.7
34.1
ºC/W
ºC/W
33.7
15.3
47.5
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (RθJC) value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC
standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
5.11 Timing and Switching Characteristics
5.11.1 Power Supply Sequencing
Table 5-2 lists the characteristics of the SVS and BOR.
Table 5-2. PMM, SVS and BOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Safe BOR power-down level(1)
Safe BOR reset delay(2)
TEST CONDITIONS
MIN
0.1
10
TYP
MAX UNIT
VBOR, safe
tBOR, safe
ISVSH,AM
ISVSH,LPM
VSVSH-
V
ms
SVSH current consumption, active mode
SVSH current consumption, low-power modes
SVSH power-down level(3)
VCC = 3.6 V
VCC = 3.6 V
1.5
µA
nA
V
240
1.80
1.88
80
1.71
1.76
1.87
1.99
VSVSH+
SVSH power-up level(3)
V
VSVSH_hys SVSH hysteresis
mV
tPD,SVSH,
AM
SVSH propagation delay, active mode
10
µs
µs
tPD,SVSH,
LPM
SVSH propagation delay, low-power modes
100
(1) A safe BOR can be correctly generated only if DVCC drops below this voltage before it rises.
(2) When an BOR occurs, a safe BOR can be correctly generated only if DVCC is kept low longer than this period before it reaches VSVSH+
.
(3) For additional information, see the Dynamic Voltage Scaling Power Solution for MSP430 Devices With Single-Channel LDO Reference
Design.
V
Power Cycle Reset
VSVS+
SVS Reset
BOR Reset
VSVS–
VBOR
tBOR
t
Figure 5-5. Power Cycle, SVS, and BOR Reset Conditions
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5.11.2 Reset Timing
Table 5-3 lists the timing characteristics of wakeup from LPMs and reset.
Table 5-3. Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
3 V
3 V
MIN
TYP
MAX UNIT
Additional wake-up time to activate the FRAM in
AM if previously disabled by the FRAM controller or
from a LPM if immediate activation is selected for
wakeup(1)
tWAKE-UP FRAM
10
µs
200 +
ns
(1)
tWAKE-UP LPM0
Wake-up time from LPM0 to active mode
2.5 / fDCO
(2)
tWAKE-UP LPM3
tWAKE-UP LPM4
tWAKE-UP LPM3.5
Wake-up time from LPM3 to active mode
3 V
3 V
3 V
10
10
µs
µs
µs
µs
ms
Wake-up time from LPM4 to active mode
(2)
Wake-up time from LPM3.5 to active mode
350
350
1
SVSHE = 1
SVSHE = 0
(2)
tWAKE-UP LPM4.5
Wake-up time from LPM4.5 to active mode
3 V
Wake-up time from RST or BOR event to active
mode
tWAKE-UP-RESET
tRESET
3 V
3 V
1
ms
µs
(2)
Pulse duration required at RST/NMI pin to accept a
reset
2
(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first
externally observable MCLK clock edge.
(2) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
24
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5.11.3 Clock Specifications
Table 5-4 lists the characteristics of the LF XT1.
Table 5-4. XT1 Crystal Oscillator (Low Frequency)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
XT1 oscillator crystal, low
frequency
fXT1, LF
LFXTBYPASS = 0
32768
Hz
Measured at MCLK,
fLFXT = 32768 Hz
DCXT1, LF
fXT1,SW
XT1 oscillator LF duty cycle
30%
70%
kHz
60%
kΩ
XT1 oscillator logic-level square-
wave input frequency
(3)(4)
LFXTBYPASS = 1
LFXTBYPASS = 1
32.768
LFXT oscillator logic-level square-
wave input duty cycle
DCXT1, SW
OALFXT
CL,eff
40%
Oscillation allowance for
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32768 Hz, CL,eff = 12.5 pF
200
1
(5)
LF crystals
Integrated effective load
capacitance(6)
(7)
See
pF
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF
(8)
tSTART,LFXT Start-up time
fFault,LFXT
1000
ms
(9)
Oscillator fault frequency
XTS = 0(10)
0
3500
Hz
(1) To improve EMI on the LFXT oscillator, observe the following guidelines:
•
•
•
•
•
•
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing.
(3) When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW
.
(4) Maximum frequency of operation of the entire device cannot be exceeded.
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
•
•
•
•
For LFXTDRIVE = {0}, CL,eff = 3.7 pF
For LFXTDRIVE = {1}, 6 pF ≤ CL,eff ≤ 9 pF
For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 10 pF
For LFXTDRIVE = {3}, 6 pF ≤ CL,eff ≤ 12 pF
(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
(7) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds
additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance
of the selected crystal is met.
(8) Includes start-up counter of 1024 clock cycles.
(9) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications might set the
flag. A static condition or stuck at fault condition sets the flag.
(10) Measured with logic-level input frequency but also applies to operation with crystals.
Table 5-5 lists the frequency characteristics of the FLL.
Table 5-5. DCO FLL, Frequency
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
3 V
3 V
MIN
–1.0%
–2.0%
TYP
MAX UNIT
1.0%
FLL lock frequency, 16 MHz, 25°C
FLL lock frequency, 16 MHz, –40°C to 85°C
Measured at MCLK, Internal
trimmed REFO as reference
2.0%
fDCO, FLL
Measured at MCLK, XT1
crystal as reference
FLL lock frequency, 16 MHz, –40°C to 85°C
3 V
–0.5%
0.5%
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Table 5-5. DCO FLL, Frequency (continued)
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
3 V
3 V
3 V
3 V
MIN
TYP
50%
MAX UNIT
fDUTY
Duty cycle
40%
60%
Jittercc
Jitterlong
tFLL, lock
Cycle-to-cycle jitter, 16 MHz
Long term jitter, 16 MHz
FLL lock time, 16MHz
0.25%
0.022%
280
Measured at MCLK, XT1
crystal as reference
ms
Table 5-6 lists the characteristics of the DCO.
Table 5-6. DCO Frequency
over recommended operating free-air temperature (unless otherwise noted) (see Figure 5-6)
PARAMETER
TEST CONDITIONS
VCC
TYP
UNIT
DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
7.1
11.8
17
DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
fDCO, 16MHz DCO frequency, 16 MHz
3 V
3 V
3 V
3 V
3 V
MHz
DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
27.7
5.5
DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
9.1
fDCO, 12MHz DCO frequency, 12 MHz
MHz
MHz
MHz
MHz
DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
13.1
21.5
3.7
DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
6.3
fDCO, 8MHz
fDCO, 4MHz
fDCO, 2MHz
DCO frequency, 8 MHz
DCO frequency, 4 MHz
DCO frequency, 2 MHz
DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
9.0
DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
14.9
1.9
DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
3.2
DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
4.6
DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
7.8
DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
0.96
1.6
DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
2.3
DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
4.0
26
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Table 5-6. DCO Frequency (continued)
over recommended operating free-air temperature (unless otherwise noted) (see Figure 5-6)
PARAMETER
TEST CONDITIONS
VCC
TYP
UNIT
DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
0.5
DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
0.85
1.2
fDCO, 1MHz
DCO frequency, 1 MHz
3 V
MHz
DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
2.0
30
25
20
15
10
5
DCOFTRIM = 7
DCOFTRIM = 7
DCOFTRIM = 7
DCOFTRIM = 7
DCOFTRIM = 7
DCOFTRIM = 0
DCOFTRIM = 0
DCOFTRIM = 7
DCOFTRIM = 0
DCOFTRIM = 0
DCOFTRIM = 0
0
DCOFTRIM = 0
DCO
0
511
0
511
0
511
0
511
0
511
0
511
DCORSEL
0
1
2
3
4
5
VCC = 3 V
Figure 5-6. Typical DCO Frequency
Table 5-7 lists the characteristics of the REFO.
TA = –40°C to 85°C
Table 5-7. REFO
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
VCC
3 V
3 V
MIN
TYP
15
MAX UNIT
IREFO
REFO oscillator current consumption
REFO calibrated frequency
µA
Hz
Measured at MCLK
–40°C to 85°C
Measured at MCLK(1)
32768
fREFO
REFO absolute calibrated tolerance
REFO frequency temperature drift
1.8 V to 3.6 V
3 V
–3.5%
+3.5%
%/°C
dfREFO/dT
0.01
1
dfREFO
/
REFO frequency supply voltage drift
Measured at MCLK at 25°C(2)
1.8 V to 3.6 V
1.8 V to 3.6 V
%/V
dVCC
fDC
REFO duty cycle
Measured at MCLK
40%
50%
50
60%
µs
tSTART
REFO start-up time
40% to 60% duty cycle
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
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Table 5-8 lists the characteristics of the VLO.
Table 5-8. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLO frequency
VLO frequency temperature drift
TEST CONDITIONS
VCC
3 V
TYP UNIT
10 kHz
0.5 %/°C
fVLO
Measured at MCLK
dfVLO/dT
Measured at MCLK(1)
Measured at MCLK(2)
Measured at MCLK
3 V
dfVLO/dVCC VLO frequency supply voltage drift
fVLO,DC Duty cycle
1.8 V to 3.6 V
3 V
4
%/V
50%
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
NOTE
The VLO clock frequency is reduced by 15% (typical) when the device switches from active
mode to LPM3 or LPM4, because the reference changes. This lower frequency is not a
violation of the VLO specifications (see Table 5-8).
Table 5-9 lists the characteristics of the MODOSC.
Table 5-9. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
3 V
MIN
TYP
4.8
MAX UNIT
5.8 MHz
%/℃
fMODOSC
MODOSC frequency
3.8
fMODOSC/dT
MODOSC frequency temperature drift
3 V
0.102
1.02
50%
fMODOSC/dVCC MODOSC frequency supply voltage drift
fMODOSC,DC Duty cycle
1.8 V to 3.6 V
3 V
%/V
40%
60%
28
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5.11.4 Digital I/Os
Table 5-10 lists the characteristics of the digital inputs.
Table 5-10. Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2 V
3 V
2 V
3 V
2 V
3 V
MIN
0.90
1.35
0.50
0.75
0.3
TYP
MAX UNIT
1.50
V
VIT+
VIT–
Vhys
Positive-going input threshold voltage
2.25
1.10
V
Negative-going input threshold voltage
1.65
0.8
V
Input voltage hysteresis (VIT+ – VIT–
Pullup or pulldown resistor
)
0.4
1.2
For pullup: VIN = VSS
For pulldown: VIN = VCC
RPull
20
35
3
50
kΩ
pF
pF
nA
nA
CI,dig
Input capacitance, digital only port pins
VIN = VSS or VCC
Input capacitance, port pins with shared analog
functions
CI,ana
Ilkg(Px.y)
Ilkg(Px.y)
VIN = VSS or VCC
5
(1) (2)
High-impedance leakage current of GPIO pins See
2 V, 3 V
2 V, 3 V
–20
–30
20
30
High-impedance leakage current of GPIO pins
See
(1) (2)(3)
shared with CapTIvate functionality
Ports with interrupt capability
(see block diagram and
terminal function descriptions)
External interrupt timing (external trigger pulse
duration to set interrupt flag)(4)
t(int)
2 V, 3 V
50
ns
(1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
(3) Applies only to GPIOs that are shared with CapTIvate I/Os
(4) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int)
.
Table 5-11 lists the characteristics of the digital outputs.
Table 5-11. Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA(1)
I(OHmax) = –5 mA(1)
I(OLmax) = 3 mA(1)
VCC
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
MIN
1.4
2.4
0.0
0.0
16
TYP
MAX UNIT
2.0
V
VOH
High-level output voltage
3.0
0.60
V
VOL
Low-level output voltage
I(OHmax) = 5 mA(1)
0.60
fPort_CLK
trise,dig
tfall,dig
Clock output frequency
CL = 20 pF(2)
CL = 20 pF
CL = 20 pF
MHz
ns
16
10
7
Port output rise time, digital only port pins
Port output fall time, digital only port pins
10
5
ns
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
(2) The port can output frequencies at least up to the specified limit and might support higher frequencies.
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5.11.4.1 Typical Characteristics – Outputs at 3 V and 2 V
DVCC = 3 V
DVCC = 2 V
Figure 5-7. Typical Low-Level Output Current vs Low-Level
Output Voltage
Figure 5-8. Typical Low-Level Output Current vs Low-Level
Output Voltage
DVCC = 3 V
DVCC = 2 V
Figure 5-9. Typical High-Level Output Current vs High-Level
Output Voltage
Figure 5-10. Typical High-Level Output Current vs High-Level
Output Voltage
30
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5.11.5 VREF+ Built-in Reference
Table 5-12 lists the characteristics of the VREF+.
Table 5-12. VREF+
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
VREF+
Positive built-in reference voltage
EXTREFEN = 1 with 1-mA load current
2 V, 3 V
1.15
1.19
1.23
V
Temperature coefficient of built-in
reference voltage
TCREF+
30
µV/°C
5.11.6 Timer_A
Table 5-13 lists the characteristics of Timer_A.
Table 5-13. Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
fTA
Timer_A input clock frequency
External: TACLK
2 V, 3 V
16 MHz
Duty cycle = 50% ±10%
All capture inputs, minimum pulse
duration required for capture
tTA,cap
Timer_A capture timing
2 V, 3 V
20
ns
tTIMR
Timer Clock
CCR0-1
0h
1h
CCR0
CCR0-1
0h
CCR0
tVALID,PWM
Timer
TAx.1
tHD,PWM
Figure 5-11. Timer PWM Mode
Capture
tTIMR
Timer Clock
tSU,CCIA
t,HD,CCIA
TAx.CCIA
Figure 5-12. Timer Capture Mode
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5.11.7 eUSCI
Table 5-14 lists the supported frequencies of the eUSCI in UART mode.
Table 5-14. eUSCI (UART Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK, MODCLK
External: UCLK
feUSCI
eUSCI input clock frequency
2 V, 3 V
16 MHz
Duty cycle = 50% ±10%
BITCLK clock frequency
(equals baud rate in Mbaud)
fBITCLK
2 V, 3 V
5
MHz
Table 5-15 lists the characteristics of the eUSCI in UART mode.
Table 5-15. eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UCGLITx = 0
VCC
TYP UNIT
12
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
40
ns
68
(1)
tt
UART receive deglitch time
2 V, 3 V
110
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
Table 5-16 lists the supported frequencies of the eUSCI in SPI master mode.
Table 5-16. eUSCI (SPI Master Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
MHz
Internal: SMCLK, MODCLK
Duty cycle = 50% ±10%
feUSCI eUSCI input clock frequency
8
32
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Table 5-17 lists the characteristics of the eUSCI in SPI master mode.
Table 5-17. eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
UCxCLK
cycles
tSTE,LEAD STE lead time, STE active to clock
1
UCxCLK
cycles
tSTE,LAG
STE lag time, last clock to STE inactive
SOMI input data setup time
1
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
48
37
0
tSU,MI
ns
ns
ns
ns
tHD,MI
SOMI input data hold time
0
20
20
UCLK edge to SIMO valid,
CL = 20 pF
tVALID,MO SIMO output data valid time(2)
SIMO output data hold time(3)
-6
-5
tHD,MO
CL = 20 pF
(1) fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)
)
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-13 and Figure 5-14.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-
13 and Figure 5-14.
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UCMODEx = 01
STE
tSTE,LEAD
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
SIMO
tHD,MO
tVALID,MO
tSTE,ACC
tSTE,DIS
Figure 5-13. SPI Master Mode, CKPH = 0
UCMODEx = 01
STE
UCMODEx = 10
tSTE,LEAD
tSTE,LAG
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
SIMO
tHD,MO
tVALID,MO
tSTE,DIS
tSTE,ACC
Figure 5-14. SPI Master Mode, CKPH = 1
34
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Table 5-18 lists the characteristics of the eUSCI in SPI slave mode.
Table 5-18. eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
MIN
55
MAX UNIT
tSTE,LEAD STE lead time, STE active to clock
ns
45
20
tSTE,LAG
STE lag time, Last clock to STE inactive
ns
20
65
ns
40
tSTE,ACC STE access time, STE active to SOMI data out
40
ns
35
STE disable time, STE inactive to SOMI high
tSTE,DIS
impedance
8
6
tSU,SI
SIMO input data setup time
SIMO input data hold time
ns
ns
12
12
tHD,SI
68
ns
42
UCLK edge to SOMI valid,
CL = 20 pF
tVALID,SO SOMI output data valid time(2)
5
5
(3)
tHD,SO
SOMI output data hold time
CL = 20 pF
ns
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)
)
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-15 and Figure 5-16.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-15
and Figure 5-16.
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UCMODEx = 01
STE
tSTE,LEAD
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tSU,SI
tLOW/HIGH
tLOW/HIGH
tHD,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 5-15. SPI Slave Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
tSTE,LAG
STE
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 5-16. SPI Slave Mode, CKPH = 1
36
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Table 5-19 lists the characteristics of the eUSCI in I2C mode.
Table 5-19. eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-17)
PARAMETER
eUSCI input clock frequency
SCL clock frequency
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, MODCLK
External: UCLK
Duty cycle = 50% ±10%
feUSCI
fSCL
16 MHz
2 V, 3 V
2 V, 3 V
0
4.0
0.6
4.7
0.6
0
400 kHz
µs
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
tHD,STA Hold time (repeated) START
tSU,STA
Setup time for a repeated START
2 V, 3 V
µs
tHD,DAT Data hold time
tSU,DAT Data setup time
2 V, 3 V
2 V, 3 V
ns
ns
250
4.0
0.6
50
fSCL = 100 kHz
fSCL > 100 kHz
UCGLITx = 0
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
UCCLTOx = 1
UCCLTOx = 2
UCCLTOx = 3
tSU,STO Setup time for STOP
2 V, 3 V
µs
600
25
300
ns
Pulse duration of spikes suppressed by
input filter
tSP
2 V, 3 V
12.5
6.3
150
75
27
30
33
tTIMEOUT Clock low time-out
2 V, 3 V
ms
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
SCL
tLOW
tHIGH
tSP
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-17. I2C Mode Timing
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5.11.8 ADC
Table 5-20 lists the characteristics of the ADC power supply and input range conditions.
Table 5-20. ADC, Power Supply and Input Range Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.0
0
TYP
MAX UNIT
DVCC
V(Ax)
ADC supply voltage
Analog input voltage range
3.6
V
V
All ADC pins
DVCC
Operating supply current into
DVCC terminal, reference
current not included, repeat-
single-channel mode
2 V
3 V
185
207
fADCCLK = 5 MHz, ADCON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADCDIV = 0, ADCCONSEQx = 10b
IADC
µA
Only one terminal Ax can be selected at one
time from the pad to the ADC capacitor array,
including wiring and pad
CI
RI
Input capacitance
2.2 V
2.5
3.5
36
pF
Input MUX ON resistance
DVCC = 2 V, 0 V ≤ VAx ≤ DVCC
kΩ
Table 5-21 lists the ADC 10-bit timing parameters.
Table 5-21. ADC, 10-Bit Timing Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
For specified performance of ADC linearity
parameters
2 V to
3.6 V
fADCCLK
fADCOSC
0.45
5
5.5 MHz
Internal ADC oscillator
(MODOSC)
2 V to
3.6 V
ADCDIV = 0, fADCCLK = fADCOSC
3.8
4.8
5.8 MHz
REFON = 0, Internal oscillator,
10 ADCCLK cycles, 10-bit mode,
fADCOSC = 4.5 MHz to 5.5 MHz
2 V to
3.6 V
2.18
2.67
µs
tCONVERT
Conversion time
External fADCCLK from ACLK, MCLK, or SMCLK,
ADCSSEL ≠ 0
2 V to
3.6 V
12 ×
1 / fADCCLK
The error in a conversion started after tADCON is
less than ±0.5 LSB.
Reference and input signal are already settled.
Turnon settling time of
the ADC
tADCON
100
ns
µs
RS = 1000 Ω, RI = 36000 Ω, CI = 3.5 pF.
Approximately 8 Tau (t) are required for an error
of less than ±0.5 LSB.(1)
tSample
Sampling time
3 V
2.0
(1) tSample = ln(2n+1) × τ, where n = ADC resolution, τ = (RI + RS) × CI
38
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Table 5-22 lists the ADC 10-bit linearity parameters.
Table 5-22. ADC, 10-Bit Linearity Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
–2
TYP
MAX UNIT
Integral linearity error (10-bit mode)
Integral linearity error (8-bit mode)
Differential linearity error (10-bit mode)
Differential linearity error (8-bit mode)
Offset error (10-bit mode)
2.4 V to 3.6 V
2.0 V to 3.6 V
2.4 V to 3.6 V
2.0 V to 3.6 V
2.4 V to 3.6 V
2.0 V to 3.6 V
2
EI
Veref+ reference
Veref+ reference
Veref+ reference
LSB
2
–2
–1
1
ED
EO
LSB
1
–1
–6.5
–6.5
–2.0
–3.0%
–2.0
–3.0%
–2.0
–3.0%
–2.0
–3.0%
6.5
mV
6.5
Offset error (8-bit mode)
Veref+ as reference
Internal 1.5-V reference
Veref+ as reference
Internal 1.5-V reference
Veref+ as reference
Internal 1.5-V reference
Veref+ as reference
Internal 1.5-V reference
2.0
3.0%
2.0
LSB
LSB
LSB
LSB
Gain error (10-bit mode)
2.4 V to 3.6 V
2.0 V to 3.6 V
2.4 V to 3.6 V
2.0 V to 3.6 V
EG
Gain error (8-bit mode)
3.0%
2.0
Total unadjusted error (10-bit mode)
Total unadjusted error (8-bit mode)
3.0%
2.0
ET
3.0%
ADCON = 1, INCH = 0Ch,
TA = 0℃
(1)
VSENSOR
See
3 V
3 V
913
mV
(2)
TCSENSOR See
ADCON = 1, INCH = 0Ch
3.35
mV/℃
ADCON = 1, INCH = 0Ch,
Error of conversion result
≤1 LSB,
3 V
3 V
30
tSENSOR
(sample)
Sample time required if channel 12 is
selected(3)
AM and all LPMs above LPM3
µs
ADCON = 1, INCH = 0Ch,
Error of conversion result
≤1 LSB, LPM3
100
(1) The temperature sensor offset can vary significantly. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
(2) The device descriptor structure contains calibration values for 30℃ and 85℃ for each available reference voltage level. The sensor
voltage can be computed as VSENSE = TCSENSOR × (Temperature, ℃) + VSENSOR, where TCSENSOR and VSENSOR can be computed from
the calibration values for higher accuracy.
(3) The typical equivalent impedance of the sensor is 700 kΩ. The sample time required includes the sensor on time, tSENSOR(on)
.
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5.11.9 CapTIvate
Table 5-23 lists the characteristics of the CapTIvate module.
Table 5-23. CapTIvate Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
1.5
TYP MAX UNIT
VREG
CREG
Reference voltage output
External buffer capacitor
1.55
1
1.6
1.2
V
ESR ≤ 200 mΩ
0.8
µF
Maximum capacitance of all external
electrodes on all CapTIvate blocks
CELECTRODE
tWAKEUP,COLD
Running a conversion at 4 MHz
300
pF
Voltage regulator wake-up time
LDO completely off then turned on
700
260
16
µs
µs
tWAKEUP,WARM Voltage regulator wake-up time
LDO in low-power mode then turned on
TA = 25ºC, CAPCLK0, FREQSHFT = 00b
Excluding first clock cycle, DC = thigh × f
fCAPCLK
CapTIvate oscillator frequency, nominal
CapTIvate oscillator duty cycle
MHz
DCCAPCLK
40%
50% 60%
Table 5-24 lists the signal-to-noise ratio of the CapTIvate module.
Table 5-24. CapTIvate Signal-to-Noise Ratio Characteristics
over operating free-air temperature range from –40°C to 105°C ambient (TA), unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TA = 25°C, Ct > 0.5 pF, Cp < 20 pF, >2.5% change in
capacitance(2)
5:1
36:1
TA = 0°C, Ct > 0.5 pF, Cp < 20 pF, >2.5% change in
capacitance(2)
SNR
Signal-to-noise ratio(1)
28:1
19:1
TA = –40°C, Ct > 0.5 pF, Cp < 20 pF, >2.5% change in
capacitance(2)
(1) SNR is defined as the ratio of the measured change in electrode capacitance due to a touch compared with the measured change in
capacitance due to the device noise floor. For additional detail on SNR in capacitive sensing applications and how to measure it in your
system, see Sensitivity, SNR, and Design Margin in Capacitive Touch Applications.
(2) Ct represents the increase or decrease in electrode capacitance due to a touch. Cp represents the inherent parasitic capacitance of the
sensing electrode that is present when no touch is applied. Therefore, the touch signal is defined as Ct/Cp, expressed as a percent
change in capacitance. Increasing Ct or decreasing Cp increases signal.
40
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5.11.10 FRAM
Table 5-25 lists the characteristics of the FRAM.
Table 5-25. FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
1015
100
40
TYP
MAX
UNIT
Read and write endurance
cycles
TJ = 25°C
tRetention
Data retention duration
TJ = 70°C
TJ = 85°C
years
10
(1)
IWRITE
IERASE
tWRITE
Current to write into FRAM
Erase current
IREAD
nA
nA
ns
N/A(2)
(3)
Write time
tREAD
(4)
(4)
NWAITSx = 0
NWAITSx = 1
1 / fSYSTEM
2 / fSYSTEM
tREAD
Read time
ns
(1) Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read
current IREAD is included in the active mode current consumption parameter IAM,FRAM
.
(2) FRAM does not require a special erase sequence.
(3) Writing into FRAM is as fast as reading.
(4) The maximum read (and write) speed is specified by fSYSTEM using the appropriate wait state settings (NWAITSx).
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5.11.11 Debug and Emulation
Table 5-26 lists the characteristics of the 2-wire SBW interface.
Table 5-26. JTAG, Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18)
PARAMETER
Spy-Bi-Wire input frequency
VCC
MIN
0
TYP
MAX UNIT
fSBW
2 V, 3 V
2 V, 3 V
8
MHz
µs
tSBW,Low
Spy-Bi-Wire low clock pulse duration
0.028
15
SBWTDIO setup time (before falling edge of SBWTCK in TMS and
TDI slot, Spy-Bi-Wire)
tSU, SBWTDIO
tHD, SBWTDIO
tValid, SBWTDIO
tSBW, En
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
4
ns
ns
ns
µs
SBWTDIO hold time (after rising edge of SBWTCK in TMS and TDI
slot, Spy-Bi-Wire)
19
SBWTDIO data valid time (after falling edge of SBWTCK in TDO
slot, Spy-Bi-Wire)
31
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
110
(1)
edge)
tSBW,Ret
Rinternal
Spy-Bi-Wire return to normal operation time(2)
2 V, 3 V
2 V, 3 V
15
20
100
50
µs
Internal pulldown resistance on TEST
35
kΩ
(1) Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) Maximum tSBW,Ret time after pulling or releasing the TEST/SBWTCK pin low until the Spy-Bi-Wire pins revert from their Spy-Bi-Wire
function to their application function. This time applies only if the Spy-Bi-Wire mode is selected.
tSBW,EN
tSBW,Low
1/fSBW
tSBW,High
tSBW,Ret
TEST/SBWTCK
tEN,SBWTDIO
tValid,SBWTDIO
RST/NMI/SBWTDIO
tSU,SBWTDIO
tHD,SBWTDIO
Figure 5-18. JTAG Spy-Bi-Wire Timing
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Table 5-27 lists the characteristics of the 4-wire JTAG interface.
Table 5-27. JTAG, 4-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-19)
PARAMETER
VCC
MIN
0
TYP
MAX UNIT
fTCK
TCK input frequency(1)
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
10 MHz
tTCK,Low
tTCK,High
tSU,TMS
tHD,TMS
tSU,TDI
tHD,TDI
TCK low clock pulse duration
15
15
11
3
ns
ns
ns
ns
ns
ns
TCK high clock pulse duration
TMS setup time (before rising edge of TCK)
TMS hold time (after rising edge of TCK)
TDI setup time (before rising edge of TCK)
TDI hold time (after rising edge of TCK)
13
5
tZ-Valid,TDO TDO high impedance to valid output time (after falling edge of TCK)
tValid,TDO TDO to new valid output time (after falling edge of TCK)
tValid-Z,TDO TDO valid to high-impedance output time (after falling edge of TCK)
26
26
ns
ns
ns
µs
kΩ
26
tJTAG,Ret
Rinternal
Spy-Bi-Wire return to normal operation time
Internal pulldown resistance on TEST
15
20
100
50
2 V, 3 V
35
(1) fTCK may be restricted to meet the timing requirements of the module selected.
1/fTCK
tTCK,Low
tTCK,High
TCK
TMS
tSU,TMS
tHD,TMS
TDI
(or TDO as TDI)
tSU,TDI
tHD,TDI
TDO
tZ-Valid,TDO
tValid,TDO
tValid-Z,TDO
tJTAG,Ret
TEST
Figure 5-19. JTAG 4-Wire Timing
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6 Detailed Description
6.1 Overview
The MSP430FR2522 and MSP430FR2512 ultra-low-power MCUs are FRAM-based MCUs with integrated
high-performance charge-transfer CapTIvate technology in ultra-low-power high-reliability high-flexibility
MCUs. The MSP430FR2522 and MSP430FR2512 MCUs feature up to 8 self-capacitance or 16 mutual-
capacitance electrodes, proximity sensing, and high accuracy up to 1-fF detection. The MCUs also include
two 16-bit timers, eUSCIs that support UART, SPI, and I2C, a hardware multiplier, an RTC module, and a
high-performance 10-bit ADC.
6.2 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter (PC), stack pointer (SP), status register
(SR), and constant generator (CG), respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be handled
with all instructions.
6.3 Operating Modes
The MSP430 has one active mode and several software-selectable low-power modes of operation (see
Table 6-1). An interrupt event can wake the MCU from low-power mode LPM0, LPM3 or LPM4, service
the request, and restore the MCU back to the low-power mode on return from the interrupt program. Low-
power modes LPM3.5 and LPM4.5 disable the core supply to minimize power consumption.
NOTE
XT1CLK and VLOCLK can be active during LPM4 mode if requested by low-frequency
peripherals, such as RTC, WDT, and CapTIvate.
44
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Table 6-1. Operating Modes
AM
LPM0
CPU OFF
16 MHz
LPM3
STANDBY
40 kHz
LPM4
OFF
0
LPM3.5
ONLY RTC
40 kHz
LPM4.5
SHUTDOWN
0
ACTIVE
MODE
(FRAM ON)
MODE
Maximum system clock
16 MHz
1.7 µA/button
average with
8-Hz scan
0.73 µA with
RTC counter
only in LFXT
0.49 µA
without SVS
16 nA without
SVS
Power consumption at 25°C, 3 V
126 µA/MHz
40 µA/MHz
Wake-up time
N/A
N/A
Instant
All
10 µs
10 µs
350 µs
350 µs
I/O
CapTIvate
I/O
RTC
I/O
Wake-up events
All
Full
Regulation
Full
Regulation
Partial Power Partial Power Partial Power
Regulator
Power Down
Down
Optional
On
Down
Optional
On
Down
Optional
On
Power
SVS
On
On
Optional
On
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Brownout
MCLK
SMCLK
FLL
On
On
Active
Off
Off
Off
Off
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
On
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Off
Off
Off
Off
Off
Off
Off
DCO
Off
Off
Off
MODCLK
Off
Off
Off
Clock(1)
REFO
Optional
Optional
Optional
Optional
Optional
Off
Off
Off
ACLK
Off
Off
XT1CLK
Off
Optional
Optional
Off
VLOCLK
CapTIvate MODCLK
CPU
Off
Off
Off
Off
FRAM
On
On
Off
Off
Off
Core
RAM
On
On
On
On
Off
Backup memory(2)
Timer0_A3
Timer1_A3
WDT
On
On
On
On
On
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Off
Off
Off
Off
Off
Off
Off
eUSCI_A0
Off
Off
Peripherals
eUSCI_B0
CRC
Off
Off
Off
Off
ADC
Optional
Optional
Optional
Off
Off
RTC
Off
Optional
Off
CapTIvate
Off
General-purpose
digital input/output
I/O
On
Optional
State Held
State Held
State Held
State Held
(1) The status shown for LPM4 applies to internal clocks only.
(2) Backup memory contains 32 bytes of register space in peripheral memory. See Table 6-20 and Table 6-35 for its memory allocation.
6.4 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see
Table 6-2). The vector contains the 16-bit address of the appropriate interrupt-handler instruction
sequence.
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Table 6-2. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
System Reset
Power up, Brownout, Supply supervisor
External reset RST
Watchdog time-out, Key violation
FRAM uncorrectable bit error detection
Software POR, BOR
SVSHIFG
PMMRSTIFG
WDTIFG
Reset
FFFEh
63, Highest
PMMPORIFG, PMMBORIFG
SYSRSTIV
FLLUNLOCKIFG
FLL unlock error
System NMI
Vacant memory access
JTAG mailbox
FRAM access time error
FRAM bit error detection
VMAIFG
JMBINIFG, JMBOUTIFG
CBDIFG, UBDIFG
Nonmaskable
Nonmaskable
FFFCh
FFFAh
62
61
User NMI
External NMI
Oscillator fault
NMIIFG
OFIFG
Timer0_A3
Timer0_A3
Timer1_A3
Timer1_A3
TA0CCR0 CCIFG0
Maskable
Maskable
Maskable
Maskable
FFF8h
FFF6h
FFF4h
FFF2h
60
59
58
57
TA0CCR1 CCIFG1, TA0CCR2 CCIFG2,
TA0IFG (TA0IV)
TA1CCR0 CCIFG0
TA1CCR1 CCIFG1, TA1CCR2 CCIFG2,
TA1IFG (TA1IV)
RTC
RTCIFG
WDTIFG
Maskable
Maskable
FFF0h
FFEEh
56
55
Watchdog timer interval mode
UCTXCPTIFG, UCSTTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
(UCA0IV)
eUSCI_A0 receive or transmit
Maskable
FFECh
54
UCB0RXIFG, UCB0TXIFG (SPI mode)
UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1, UCRXIFG2,
UCTXIFG2, UCRXIFG3, UCTXIFG3,
UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB0IV)
eUSCI_B0 receive or transmit
Maskable
Maskable
FFEAh
FFE8h
53
52
ADCIFG0, ADCINIFG, ADCLOIFG,
ADCHIIFG, ADCTOVIFG, ADCOVIFG
(ADCIV)
ADC
P1
P2
P1IFG.0 to P1IFG.7 (P1IV)
P2IFG.0 to P2IFG.6 (P2IV)
Maskable
Maskable
FFE6h
FFE4h
51
50
(See CapTivate Design Center for
details)
CapTIvate
Reserved
Maskable
Maskable
FFE2h
49, Lowest
Reserved
FFE0h–FF88h
Table 6-3. Signatures
SIGNATURE
BSL Signature2
BSL Signature1
JTAG Signature2
JTAG Signature1
WORD ADDRESS
0FF86h
0FF84h
0FF82h
0FF80h
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6.5 Bootloader (BSL)
The BSL lets users program the FRAM or RAM using either the UART serial interface or the I2C interface.
Access to the MCU memory through the BSL is protected by an user-defined password. Use of the BSL
requires four pins (see Table 6-4 and Table 6-5). The BSL entry requires a specific entry sequence on the
RST/NMI/SBWTDIO and TEST/SBWTCK pins. This device can support the blank device detection
automatically to invoke the BSL with bypass this special entry sequence for saving time and on board
programmable. For the complete description of the feature of the BSL, see the MSP430 FRAM Device
Bootloader (BSL) User's Guide.
Table 6-4. UART BSL Pin Requirements and Functions
DEVICE SIGNAL
RST/NMI/SBWTDIO
TEST/SBWTCK
P1.4
BSL FUNCTION
Entry sequence signal
Entry sequence signal
Data transmit
P1.5
Data receive
DVCC
Power supply
DVSS
Ground supply
Table 6-5. I2C BSL Pin Requirements and Functions
DEVICE SIGNAL
RST/NMI/SBWTDIO
TEST/SBWTCK
P1.2
BSL FUNCTION
Entry sequence signal
Entry sequence signal
Data transmit and receive
Clock
P1.3
DVCC
Power supply
DVSS
Ground supply
6.6 JTAG Standard Interface
The MSP low-power microcontrollers support the standard JTAG interface, which requires four signals for
sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK
pin enables the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface
with MSP430 development tools and device programmers. Table 6-6 lists the JTAG pin requirements. For
further details on interfacing to development tools and device programmers, see the MSP430 Hardware
Tools User's Guide. For details on using the JTAG interface, see MSP430 Programming With the JTAG
Interface.
Table 6-6. JTAG Pin Requirements and Function
DEVICE SIGNAL
P1.4/.../TCK
DIRECTION
JTAG FUNCTION
JTAG clock input
JTAG state control
JTAG data input, TCLK input
JTAG data output
Enable JTAG pins
External reset
IN
IN
IN
OUT
IN
IN
–
P1.5/.../TMS
P1.6/.../TDI/TCLK
P1.7/.../TDO
TEST/SBWTCK
RST/NMI/SBWTDIO
DVCC
Power supply
DVSS
–
Ground supply
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6.7 Spy-Bi-Wire Interface (SBW)
The MSP low-power microcontrollers support the 2-wire SBW interface. SBW can be used to interface
with MSP development tools and device programmers. Table 6-7 lists the SBW interface pin requirements.
For further details on interfacing to development tools and device programmers, see the MSP430
Hardware Tools User's Guide. For details on using the SBW interface, see the MSP430 Programming
With the JTAG Interface.
Table 6-7. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
DVCC
DIRECTION
SBW FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input and output
Power supply
IN
IN, OUT
–
–
DVSS
Ground supply
6.8 FRAM
The FRAM can be programmed using the JTAG port, SBW, the BSL, or in-system by the CPU. Features
of the FRAM include:
•
•
•
Byte and word access capability
Programmable wait state generation
Error correction coding (ECC)
6.9 Memory Protection
The device features memory protection for user access authority and write protection, including options to:
•
Secure the whole memory map to prevent unauthorized access from JTAG port or BSL, by writing
JTAG and BSL signatures using the JTAG port, SBW, the BSL, or in-system by the CPU.
•
Enable write protection to prevent unwanted write operation to FRAM contents by setting the control
bits in the System Configuration 0 register. For detailed information, see the SYS chapter in the
MP430FR4xx and MP430FR2xx Family User's Guide.
6.10 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. All peripherals can be
handled by using all instructions in the memory map. For complete module description, see the
MP430FR4xx and MP430FR2xx Family User's Guide.
6.10.1 Power-Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM
also includes supply voltage supervisor (SVS) and brownout protection. The brownout reset circuit (BOR)
is implemented to provide the proper internal reset signal to the device during power on and power off.
The SVS circuitry detects if the supply voltage drops below a user-selectable safe level. SVS circuitry is
available on the primary supply.
The device contains two on-chip reference: 1.5 V for internal reference and 1.2 V for external reference.
The 1.5-V reference is internally connected to ADC channel 13. DVCC is internally connected to ADC
channel 15. When DVCC is set as the reference voltage for ADC conversion, the DVCC can be easily
represent as Equation 1 by using ADC sampling 1.5-V reference without any external components
support.
DVCC = (1023 × 1.5 V) ÷ 1.5-V reference ADC result
(1)
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A 1.2-V reference voltage can be buffered, when EXTREFEN = 1 on PMMCTL2 register, and it can be
output to P1.1/../A1/VREF+ , meanwhile the ADC channel 1 can also be selected to monitor this voltage.
For more detailed information, see the MSP430FR4xx and MSP430FR2xx Family User's Guide.
6.10.2 Clock System (CS) and Clock Distribution
The clock system includes a 32-kHz crystal oscillator (XT1), an internal very-low-power low-frequency
oscillator (VLO), an integrated 32-kHz RC oscillator (REFO), an integrated internal digitally controlled
oscillator (DCO) that may use frequency-locked loop (FLL) locking with internal or external 32-kHz
reference clock, and an on-chip asynchronous high-speed clock (MODOSC). The clock system is
designed for cost-effective designs with minimal external components. A fail-safe mechanism is included
for XT1. The clock system module offers the following clock signals.
•
Main Clock (MCLK): The system clock used by the CPU and all relevant peripherals accessed by the
bus. All clock sources except MODOSC can be selected as the source with a predivider of 1, 2, 4, 8,
16, 32, 64, or 128.
•
•
Sub-Main Clock (SMCLK): The subsystem clock used by the peripheral modules. SMCLK derives from
the MCLK with a predivider of 1, 2, 4, or 8. This means SMCLK is always equal to or less than MCLK.
Auxiliary Clock (ACLK): This clock is derived from the external XT1 clock or internal REFO clock up to
40 kHz.
All peripherals may have one or several clock sources depending on specific functionality. Table 6-8 lists
the clock distribution used in this device.
Table 6-8. Clock Distribution
CLOCK
SOURCE
SELECT
BITS
MCLK
SMCLK
ACLK
MODCLK
XT1CLK
VLOCLK
EXTERNAL PIN
Frequency
Range
DC to
16 MHz
DC to
16 MHz
DC to
40 kHz
5 MHz
±10%
DC to
40 kHz
10 kHz
±50%
–
CPU
N/A
N/A
Default
–
–
–
–
–
–
–
–
–
–
FRAM
RAM
Default
–
–
N/A
Default
–
–
–
–
–
–
CRC
N/A
Default
–
–
–
–
–
–
–
I/O
N/A
Default
–
–
–
–
–
TA0
TASSEL
TASSEL
UCSSEL
UCSSEL
WDTSSEL
ADCSSEL
CAPTSSEL
RTCSS
–
–
–
–
–
–
–
–
10b
01b
01b
01b
01b
01b
01b
00b
01b(1)
–
–
11b
–
00b (TA0CLK pin)
TA1
10b
–
–
00b (TA1CLK pin)
eUSCI_A0
eUSCI_B0
WDT
10b or 11b
10b or 11b
00b
–
–
–
00b (UCA0CLK pin)
–
–
–
00b (UCB0CLK pin)
–
–
10b
–
–
–
–
–
ADC
10b or 11b
–
01b(1)
00b
–
–
CapTIvate
RTC
–
01b
11b
–
10b
(1) Controlled by the RTCCKSEL bit in the SYSCFG2 register
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CPU
FRAM
SRAM
CRC
I/O
MCLK
Timer_A
A0
Timer_A
A1
eUSCI_A0
eUSCI_B0
WDT
RTC
ADC10
CapTIvate
Clock System (CS)
SMCLK
ACLK
VLOCLK
MODCLK
Selected on SYSCFG2
XT1CLK
Figure 6-1. Clock Distribution Block Diagram
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6.10.3 General-Purpose Input/Output Port (I/O)
Up to 15 I/O ports are implemented.
•
•
•
•
•
•
•
•
P1 implements 8 bits, and P2 implements 7 bits.
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Programmable pullup or pulldown on all ports.
Edge-selectable interrupt and LPMx.5 wake-up input capability are available for P1 and P2.
Read and write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise or word-wise as a pair.
CapTIvate functionality is supported on all CAPx.y pins.
NOTE
Configuration of digital I/Os after BOR reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance
with Schmitt triggers and module functions disabled. To enable the I/O functions after a BOR
reset, the ports must be configured first and then the LOCKLPM5 bit must be cleared. For
details, see the Configuration After Reset section in the Digital I/O chapter of the
MP430FR4xx and MP430FR2xx Family User's Guide.
6.10.4 Watchdog Timer (WDT)
The primary function of the WDT module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not
needed in an application, the module can be configured as an interval timer and can generate interrupts at
selected time intervals. Table 6-9 lists the system clocks that can be used to source the WDT.
Table 6-9. WDT Clocks
NORMAL OPERATION
WDTSSEL
(WATCHDOG AND INTERVAL TIMER MODE)
00
01
10
11
SMCLK
ACLK
VLOCLK
Reserved
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6.10.5 System (SYS) Module
The SYS module handles many of the system functions within the device. These features include power-
on reset (POR) and power-up clear (PUC) handling, NMI source selection and management, reset
interrupt vector generators, bootloader entry mechanisms, and configuration management (device
descriptors). The SYS module also includes a data exchange mechanism through SBW called a JTAG
mailbox mail box that can be used in the application. Table 6-10 summarizes the interrupts that are
managed by the SYS module.
Table 6-10. System Module Interrupt Vector Registers
INTERRUPT VECTOR
ADDRESS
INTERRUPT EVENT
VALUE
PRIORITY
REGISTER
No interrupt pending
Brownout (BOR)
00h
02h
Highest
RSTIFG RST/NMI (BOR)
PMMSWBOR software BOR (BOR)
LPMx.5 wakeup (BOR)
Security violation (BOR)
Reserved
04h
06h
08h
0Ah
0Ch
SVSHIFG SVSH event (BOR)
Reserved
0Eh
10h
SYSRSTIV, System Reset
015Eh
Reserved
12h
PMMSWPOR software POR (POR)
WDTIFG watchdog time-out (PUC)
WDTPW password violation (PUC)
FRCTLPW password violation (PUC)
Uncorrectable FRAM bit error detection
Peripheral area fetch (PUC)
PMMPW PMM password violation (PUC)
FLL unlock (PUC)
14h
16h
18h
1Ah
1Ch
1Eh
20h
24h
Reserved
22h, 26h to 3Eh
00h
Lowest
Highest
No interrupt pending
SVS low-power reset entry
Uncorrectable FRAM bit error detection
Reserved
02h
04h
06h
Reserved
08h
Reserved
0Ah
Reserved
0Ch
SYSSNIV, System NMI
015Ch
Reserved
0Eh
Reserved
10h
VMAIFG vacant memory access
JMBINIFG JTAG mailbox input
JMBOUTIFG JTAG mailbox output
Correctable FRAM bit error detection
Reserved
12h
14h
16h
18h
1Ah to 1Eh
00h
Lowest
Highest
Lowest
No interrupt pending
NMIIFG NMI pin or SVSH event
OFIFG oscillator fault
Reserved
02h
SYSUNIV, User NMI
015Ah
04h
06h to 1Eh
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6.10.6 Cyclic Redundancy Check (CRC)
The 16-bit cyclic redundancy check (CRC) module produces a signature based on a sequence of data
values and can be used for data checking purposes. The CRC generation polynomial is compliant with
CRC-16-CCITT standard of x16 + x12 + x5 + 1.
6.10.7 Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
The eUSCI modules are used for serial data communications. The eUSCI_A module supports either
UART or SPI communications. The eUSCI_B module supports either SPI or I2C communications.
Additionally, eUSCI_A supports automatic baud-rate detection and IrDA. The eUSCI_A and eUSCI_B are
connected either from P1 port or P2 port, it can be selected from the USCIARMP of SYSCFG3 or
USCIBRMP bit of SYSCFG2. Table 6-11 lists the pin configurations that are required for each eUSCI
mode.
Table 6-11. eUSCI Pin Configurations
PIN (USCIARMP = 0)
UART
TXD
RXD
–
SPI
SIMO
SOMI
SCLK
STE
P1.4
P1.5
P1.6
P1.7
–
eUSCI_A0
PIN (USCIARMP = 1)
UART
TXD
RXD
–
SPI
P2.0
SIMO
SOMI
SCLK
STE
P2.1
P1.6
P1.7
–
PIN (USCIBRMP = 0)
I2C
SPI
P1.0
–
STE
P1.1
–
SCLK
SIMO
SOMI
SPI
P1.2
SDA
SCL
I2C
–
P1.3
eUSCI_B0
PIN (USCIBRMP = 1)
P2.3
P2.4
P2.5
P2.6
STE
–
SCLK
SIMO
SOMI
SDA
SCL
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6.10.8 Timers (Timer0_A3, Timer1_A3)
The Timer0_A3 and Timer1_A3 modules are 16-bit timers and counters with three capture/compare
registers each. Each timer supports multiple captures or compares, PWM outputs, and interval timing (see
Figure 6-2). Each timer has extensive interrupt capabilities. Interrupts may be generated from the counter
on overflow conditions and from each of the capture/compare registers. The CCR0 registers on both
Timer0_A3 and Timer1_A3 are not externally connected and can only be used for hardware period timing
and interrupt generation. In Up mode, they can be used to set the overflow value of the counter.
Timer_A0
Timer_A1
TA0CLK
ACLK
00
01
10
11
TA1CLK
ACLK
00
01
10
11
16-bit Counter
SMCLK
VLO
16-bit Counter
SMCLK
00
01
10
11
ACLK
VLO
TA0.0A
TA0.0B
00
01
10
11
CCR0
DVSS
DVCC
TA0.0A
TA0.0B
CCR0
DVSS
DVCC
P1.4
RTC
00
01
10
11
TA0.1A
TA0.1B
P1.4
P2.2
00
01
10
11
CCR1
DVSS
DVCC
TA0.1A
TA0.1B
P2.2
CCR1
DVSS
DVCC
To ADC Trigger
P1.5
00
01
10
11
TA0.2A
TA0.2B
P1.5
P2.3
00
01
10
11
CCR2
DVSS
DVCC
TA0.2A
TA0.2B
P2.3
CCR2
DVSS
DVCC
Coding
Carrier
Infrared
Logic (SYS)
P2.0/UCA0TXD/UCA0SIMO
UCA0TXD/UCA0SIMO
eUSCI_A0
Data
Figure 6-2. Timer0_A3 and Timer1_A3 Signal Connections
The interconnection of Timer0_A3 and Timer1_A3 can be used to modulate the eUSCI_A pin of
UCA0TXD/UCA0SIMO in either ASK or FSK mode, with which a user can easily acquire a modulated
infrared command for directly driving an external IR diode. The IR functions are fully controlled by SYS
configuration registers 1 including IREN (enable), IRPSEL (polarity select), IRMSEL (mode select),
IRDSSEL (data select), and IRDATA (data) bits. For more information, see the SYS chapter in the
MP430FR4xx and MP430FR2xx Family User's Guide.
6.10.9 Hardware Multiplier (MPY)
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The MPY module supports signed multiplication,
unsigned multiplication, signed multiply-and-accumulate, and unsigned multiply-and-accumulate
operations.
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6.10.10 Backup Memory (BAKMEM)
The BAKMEM supports data retention during LPM3.5. This device provides up to 32 bytes that are
retained during LPM3.5.
6.10.11 Real-Time Clock (RTC)
The RTC is a 16-bit modulo counter that is functional in AM, LPM0, LPM3, and LPM3.5. This module can
periodically wake up the CPU from LPM0, LPM3, or LPM3.5 based on timing from a low-power clock
source such as the XT1 and VLO clocks. RTC also can be sourced from ACLK controlled by RTCCLK in
SYSCFG2. In AM, RTC can be driven by SMCLK to generate high-frequency timing events and interrupts.
The RTC overflow events trigger:
•
•
Timer0_B3 CCI1B
ADC conversion trigger when ADCSHSx bits are set as 01b
Table 6-12. RTC Clock Source
RTCSS
00
CLOCK SOURCE
Reserved
SMCLK or ACLK is selected(1)
XT1CLK
01
10
11
VLOCLK
(1) Controlled by the RTCCLK bit of the SYSCFG2 register
6.10.12 10-Bit Analog-to-Digital Converter (ADC)
The 10-bit ADC module supports fast 10-bit analog-to-digital conversions with single-ended input. The
module implements a 10-bit SAR core, sample select control, a reference generator, and a conversion
result buffer. A window comparator with lower and upper limits allows CPU-independent result monitoring
with three window comparator interrupt flags.
The ADC supports 10 external inputs and 4 internal inputs (see Table 6-13).
Table 6-13. ADC Channel Connections
ADCINCHx
ADC CHANNELS
EXTERNAL PIN
P1.0
P1.1
P1.2
P1.3
P2.2
P2.3
P2.4
P2.5
N/A
0
1
A0/Veref+
A1(1)
2
A2/Veref-
3
A3
4
A4
5
A5
6
A6
A7
7
8
Not used
9
Not used
N/A
10
11
12
13
Not used
N/A
Not used
N/A
On-chip temperature sensor
Reference voltage (1.5 V)
N/A
N/A
(1) When A7 is used, the PMM 1.2-V reference voltage can be output to
this pin by setting the PMM control register. The 1.2-V voltage can
be measured by the A1 channel.
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Table 6-13. ADC Channel Connections (continued)
ADCINCHx
ADC CHANNELS
DVSS
EXTERNAL PIN
14
15
N/A
N/A
DVCC
The analog-to-digital conversion can be started by software or a hardware trigger. Table 6-14 lists the
trigger sources that are available.
Table 6-14. ADC Trigger Signal Connections
ADCSHSx
TRIGGER SOURCE
BINARY
DECIMAL
00
01
10
11
0
1
2
3
ADCSC bit (software trigger)
RTC event
TA1.1B
Reserved
6.10.13 CapTIvate Technology
The CapTIvate module detects the capacitance changed with a charge-transfer method and is functional
in AM, LPM0, LPM3 and LPM4. The CapTIvate module can periodically wake the CPU from LPM0, LPM3
or LPM4 based on a CapTIvate timer source such as ACLK or VLO clock. The CapTIvate module also
can work on wake-on-touch state machine mode for better power saving without periodically woke up the
CPU. The CapTIvate module supports the following touch-sensing capability:
•
The MSP430FR2522 supports up to 16 CapTIvate buttons composed of 2 CapTIvate blocks.
The MSP430FR2512 supports up to 4 CapTIvate buttons composed of 1 CapTIvate block.
Each block consists of 4 I/Os, and these blocks scan in parallel of 2 electrodes.
•
Each block can be individually configured in self or mutual mode. Each CapTIvate I/O can be used for
either self or mutual electrodes.
•
•
•
Supports a wake-on-touch state machine.
Supports synchronized conversion on a zero-crossing event trigger.
Processing logic to perform filter calculation and threshold detection.
To learn more about MSP MCUs featuring CapTIvate technology, see the CapTIvate™ Technology Guide.
6.10.14 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The EEM on these devices has the following features:
•
•
•
•
•
•
Three hardware triggers or breakpoints on memory access
One hardware trigger or breakpoint on CPU register write access
Up to four hardware triggers can be combined to form complex triggers or breakpoints
One cycle counter
Clock control on module level
EEM version: S
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6.11 Input/Output Diagrams
6.11.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
Figure 6-3 shows the port diagram. Table 6-15 summarizes the selection of pin function.
A0 to A3
CAP0.0 to CAP0.3
CAP1.0 to CAP1.3
From CapTIvate
P1SEL.x = 11
P1REN.x
P1DIR.x
From Module1
From Module2
00
01
10
11
2 bit
DVSS
DVCC
0
1
00
01
P1OUT.x
From Module1
From Module2
DVSS
10
11
2 bit
P1SEL.x
EN
D
To module
P1IN.x
P1IE.x
Bus
Keeper
P1 Interrupt
D
S
Q
P1IFG.x
P1.0/UCB0STE/A0/Veref+/CAP1.0
Edge
Select
P1.1/UCB0CLK/ACLK/A1/VREF+/CAP1.1
P1.2/UCB0SIMO/UCB0SDA/SMCLK/A2/Veref-/CAP1.2
P1.3/UCB0SOMI/UCB0SCL/MCLK/A3/CAP1.3
P1.4/UCA0TXD/UCA0SIMO/TA0.1/TCK/CAP0.0
P1.5/UCA0RXD/UCA0SOMI/TA0.2/TMS/CAP0.1
P1.6/UCA0CLK/TA0CLK/TDI/TCLK/CAP0.2
P1.7/UCA0STE/TDO/CAP0.3
P1IES.x
From JTAG
To JTAG
NOTE: CapTIvate channel 1 is available on the MSP430FR2522 only.
Figure 6-3. Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
NOTE
CapTIvate shared with alternative functions
The CapTIvate function and alternative functions are powered by different power supplies
(1.5 V and 3.3 V, respectively).
To prevent pad damage when changing the function, TI recommends checking the external
application circuit of each pad before enabling the alternative function.
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Table 6-15. Port P1 (P1.0 to P1.7) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
ANALOG
P1DIR.x
P1SELx
JTAG
FUNCTION(2)
P1.0 (I/O)
UCB0STE
I: 0; O: 1
X
00
01
0
0
N/A
N/A
P1.0/UCB0STE/A0/
Veref+/CAP1.0(3)
0
ADCPCTLx = 1 (x = 0) from
SYSCFG2
A0,Veref+
X
N/A
CAP1.0(3)
P1.1 (I/O)
UCB0CLK
ACLK
X
P1SELx = 11, or from CapTIvate
I: 0; O: 1
00
01
10
0
0
0
N/A
N/A
N/A
X
1
P1.1/UCB0CLK/ACLK/
A1/VREF+/CAP1.1(3)
1
2
3
ADCPCTLx = 1 (x = 1) from
SYSCFG2
A1,VREF+
X
N/A
CAP1.1(3)
P1.2 (I/O)
X
P1SELx = 11, or from CapTIvate
I: 0; O: 1
00
01
10
0
0
0
N/A
N/A
N/A
UCB0SIMO/UCB0SDA
SMCLK
X
1
P1.2/UCB0SIMO/
UCB0SDA/SMCLK/A2/
Veref-/CAP1.2(3)
ADCPCTLx = 1 (x = 2) from
SYSCFG2
A2, Veref-
X
N/A
CAP1.2(3)
X
P1SELx = 11, or from CapTIvate
P1.3 (I/O)
I: 0; O: 1
00
01
10
0
0
0
N/A
N/A
N/A
UCB0SOMI/UCB0SCL
MCLK
X
1
P1.3/UCB0SOMI/
UCB0SCL/MCLK/A3/
CAP1.3(3)
ADCPCTLx = 1 (x = 3) from
SYSCFG2
A3
X
N/A
CAP1.3(3)
P1.4 (I/O)
X
P1SELx = 11, or from CapTIvate
I: 0; O: 1
00
01
0
0
Disabled
Disabled
UCA0TXD/UCA0SIMO
TA0.CCI1A
TA0.1
X
P1.4/UCA0TXD/
UCA0SIMO/TA0.1/
TCK/CAP0.0
0
4
5
10
0
Disabled
1
CAP0.0
X
P1SELx = 11, or from CapTIvate
Disabled
TCK
JTAG TCK
P1.5 (I/O)
X
X
X
0
0
I: 0; O: 1
00
01
Disabled
Disabled
UCA0RXD/UCA0SOMI
TA0.CCI2A
TA0.2
X
P1.5/UCA0RXD/
UCA0SOMI/TA0.2/
TMS/CAP0.1
0
10
0
Disabled
1
CAP0.1
X
P1SELx = 11, or from CapTIvate
Disabled
TMS
JTAG TMS
P1.6 (I/O)
X
X
X
0
0
0
I: 0; O: 1
00
01
10
Disabled
Disabled
Disabled
Disabled
TDI/TCLK
Disabled
Disabled
Disabled
TDO
UCA0CLK
TA0CLK
X
P1.6/UCA0CLK/
TA0CLK/TDI/TCLK/
CAP0.2
6
7
0
CAP0.2
X
P1SELx = 11, or from CapTIvate
JTAG TDI/TCLK
P1.7 (I/O)
X
X
X
0
0
I: 0; O: 1
00
01
UCA0STE
CAP0.3
X
X
X
P1.7/UCA0STE/TDO/
CAP0.3
P1SELx = 11, or from CapTIvate
JTAG TDO
X
X
(1) X = don't care
(2) Setting the bits disables both the output driver and input Schmitt trigger to prevent leakage when analog signals are applied.
(3) CapTIvate channel 1 is available on the MSP430FR2522 only.
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6.11.2 Port P2 (P2.0 to P2.6) Input/Output With Schmitt Trigger
Figure 6-4 shows the port diagram. Table 6-16 summarizes the selection of pin function.
A4 to A7
P2SEL.x = 11
P2REN.x
P2DIR.x
From Module1
From Module2
00
01
10
11
2 bit
DVSS
DVCC
0
1
00
01
P2OUT.x
From Module1
From Module2
DVSS
10
11
2 bit
P2SEL.x
EN
D
To module
P2IN.x
P2IE.x
Bus
Keeper
P2 Interrupt
D
S
Q
P2.0/UCA0TXD/UCA0SIMO/XOUT
P2.1/UCA0RXD/UCA0SOMI/XIN
P2.2/TA1.1/SYNC/A4
P2IFG.x
P2IES.x
Edge
Select
P2.3/TA1.2/UCB0STE/A5
P2.4/TA1CLK/UCB0CLK/A6
P2.5/UCB0SIMO/UCB0SDA/A7
P2.6/UCB0SOMI/UCB0SCL
Figure 6-4. Port P2 (P2.0 to P2.6) Input/Output With Schmitt Trigger
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Table 6-16. Port P2 (P2.0 to P2.6) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
ANALOG
P2DIR.x
P2SELx
FUNCTION(2)
P2.0 (I/O)
I: 0; O: 1
00
01
10
00
01
10
00
0
0
0
0
0
0
0
P2.0/UCA0TXD/
UCA0SIMO/XOUT
0
UCA0TXD/UCA0SIMO
XOUT
X
X
P2.1 (I/O)
I: 0; O: 1
P2.1/UCA0RXD/
UCA0SOMI/XIN
1
2
UCA0RXD/UCA0SOMI
XIN
X
X
P2.2 (I/O)
I: 0; O: 1
TA1.CCI1A
TA1.1
0
1
0
01
0
0
P2.2/TA1.1/SYNC/A4
SYNC
10
X
ADCPCTLx = 1 (x = 4)
from SYSCFG2(2)
A4
X
P2.3 (I/O)
TA1.CCI2A
TA1.2
I: 0; O: 1
00
0
0
0
0
1
X
01
P2.3/TA1.2/
UCB0STE/A5
3
4
UCB0STE
10
X
ADCPCTLx = 1 (x = 5)
from SYSCFG2(2)
A5
X
P2.4 (I/O)
TA1CLK
I: 0; O: 1
00
01
10
0
0
0
0
P2.4/TA1CLK/
UCB0CLK/A6
UCB0CLK
X
ADCPCTLx = 1 (x = 6)
from SYSCFG2(2)
A6
X
X
P2.5 (I/O)
I: 0; O: 1
X
00
10
0
0
P2.5/UCB0SIMO/
UCB0SDA/A7
UCB0SIMO/UCB0SDA
5
6
ADCPCTLx = 1 (x = 7)
from SYSCFG2(2)
A7
X
X
P2.6 (I/O)
I: 0; O: 1
X
00
10
0
0
P2.6/UCB0SOMI/
UCB0SCL
UCB0SOMI/UCB0SCL
(1) X = don't care
(2) Setting the bits disables both the output driver and input Schmitt trigger to prevent leakage when analog signals are applied.
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6.12 Device Descriptors
Table 6-17 lists the Device IDs of the devices. Table 6-18 lists the contents of the device descriptor tag-
length-value (TLV) structure for the devices.
Table 6-17. Device IDs
DEVICE ID
DEVICE
1A05h
83h
1A04h
10h
MSP430FR2522
MSP430FR2512
83h
1Ch
Table 6-18. Device Descriptors
MSP430FR25x2
ADDRESS
DESCRIPTION
VALUE
06h
Info length
1A00h
1A01h
1A02h
1A03h
1A04h
1A05h
1A06h
1A07h
1A08h
1A09h
1A0Ah
1A0Bh
1A0Ch
1A0Dh
1A0Eh
1A0Fh
1A10h
1A11h
1A12h
1A13h
1A14h
1A15h
1A16h
1A17h
1A18h
1A19h
1A1Ah
1A1Bh
1A1Ch
1A1Dh
CRC length
06h
Per unit
Per unit
CRC value(1)
Information Block
Device ID
See Table 6-17.
Hardware revision
Firmware revision
Die record tag
Per unit
Per unit
08h
Die record length
0Ah
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Lot wafer ID
Die Record
Die X position
Die Y position
Test result
ADC calibration tag
ADC calibration length
ADC gain factor
ADC calibration
ADC offset
ADC 1.5-V reference, temperature 30°C
ADC 1.5-V reference, temperature 85°C
(1) The CRC value covers the check sum from 0x1A04h to 0x1AF5h by applying the CRC-CCITT-16 polynomial of x16 + x12 + x5 + 1.
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Table 6-18. Device Descriptors (continued)
MSP430FR25x2
DESCRIPTION
ADDRESS
1A1Eh
1A1Fh
1A20h
VALUE
Calibration tag
12h
Calibration length
04h
Per unit
Per unit
Per unit
Per unit
Reference and DCO Calibration 1.5-V reference factor
1A21h
1A22h
DCO tap setting for 16 MHz, temperature 30°C(2)
1A23h
(2) This value can be directly loaded into DCO bits in CSCTL0 registers to get accurate 16-MHz frequency at room temperature, especially
when the MCU exits from LPM3 and below. TI suggests using the predivider to decrease the frequency if the temperature drift might
result an overshoot beyond 16 MHz.
6.13 Memory
6.13.1 Memory Organization
Table 6-19 summarizes the memory organization of the devices.
Table 6-19. Memory Organization
ACCESS
MSP430FR2522 MSP430FR2512
Memory (FRAM)
Main: interrupt vectors and signatures
Main: code memory
7.25KB
FFFFh to FF80h
FFFFh to E300h
Read/Write
(Optional Write Protect)(1)
2KB
27FFh to 2000h
RAM
Read/Write
Read/Write
256B
18FFh to 1800h
Information Memory (FRAM)
Bootloader (BSL1) Memory (ROM)
Bootloader (BSL2) Memory (ROM)
CapTIvate Libraries and Driver Libraries (ROM)
Peripherals
(Optional Write Protect)(2)
2KB
17FFh to 1000h
Read only
Read only
Read only
Read/Write
1KB
FFFFFh to FFC00h
12KB
6FFFh to 4000h
4KB
0FFFh to 0000h
(1) The Program FRAM can be write protected by setting PFWP bit in SYSCFG0 register. See the SYS chapter in the MP430FR4xx and
MP430FR2xx Family User's Guide for more details
(2) The Information FRAM can be write protected by setting DFWP bit in SYSCFG0 register. See the SYS chapter in the MP430FR4xx and
MP430FR2xx Family User's Guide for more details
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6.13.2 Peripheral File Map
Table 6-20 lists the available peripherals and the register base address for each.
Table 6-20. Peripherals Summary
MODULE NAME
Special Functions (See Table 6-21)
BASE ADDRESS
0100h
SIZE
0010h
0020h
0040h
0020h
0010h
0008h
0002h
0020h
0010h
0030h
0030h
0030h
0020h
0030h
0020h
0040h
0200h
PMM (See Table 6-22)
0120h
SYS (See Table 6-23)
0140h
CS (See Table 6-24)
0180h
FRAM (See Table 6-25)
01A0h
01C0h
01CCh
0200h
CRC (See Table 6-26)
WDT (See Table 6-27)
Port P1, P2 (See Table 6-28)
RTC (See Table 6-29)
0300h
Timer0_A3 (See Table 6-30)
Timer1_A3 (See Table 6-31)
MPY32 (See Table 6-32)
eUSCI_A0 (See Table 6-33)
eUSCI_B0 (See Table 6-34)
Backup Memory (See Table 6-35)
ADC (See Table 6-36)
0380h
03C0h
04C0h
0500h
0540h
0660h
0700h
CapTIvate (See CapTivate Design Center for details )
0A00h
Table 6-21. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
ACRONYM
SFRIE1
OFFSET
00h
SFR interrupt enable
SFR interrupt flag
SFRIFG1
SFRRPCR
02h
SFR reset pin control
04h
Table 6-22. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
ACRONYM
PMMCTL0
PMMCTL1
PMMCTL2
PMMIFG
OFFSET
00h
PMM control 0
PMM control 1
PMM control 2
PMM interrupt flags
PM5 control 0
02h
04h
0Ah
PM5CTL0
10h
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Table 6-23. SYS Registers (Base Address: 0140h)
REGISTER DESCRIPTION
ACRONYM
SYSCTL
OFFSET
System control
00h
02h
06h
08h
0Ah
0Ch
0Eh
18h
1Ah
1Ch
1Eh
20h
22h
24h
Bootloader configuration area
JTAG mailbox control
SYSBSLC
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSBERRIV
SYSUNIV
SYSSNIV
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
Bus error vector generator
User NMI vector generator
System NMI vector generator
Reset vector generator
System configuration 0
System configuration 1
System configuration 2
SYSRSTIV
SYSCFG0
SYSCFG1
SYSCFG2
Table 6-24. CS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
ACRONYM
CSCTL0
CSCTL1
CSCTL2
CSCTL3
CSCTL4
CSCTL5
CSCTL6
CSCTL7
CSCTL8
OFFSET
00h
CS control 0
CS control 1
CS control 2
CS control 3
CS control 4
CS control 5
CS control 6
CS control 7
CS control 8
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
Table 6-25. FRAM Registers (Base Address: 01A0h)
REGISTER DESCRIPTION
ACRONYM
FRCTL0
OFFSET
00h
FRAM control 0
General control 0
General control 1
GCCTL0
GCCTL1
04h
06h
Table 6-26. CRC Registers (Base Address: 01C0h)
REGISTER DESCRIPTION
ACRONYM
CRC16DI
OFFSET
00h
CRC data input
CRC data input reverse byte
CRC initialization and result
CRC result reverse byte
CRCDIRB
CRCINIRES
CRCRESR
02h
04h
06h
Table 6-27. WDT Registers (Base Address: 01CCh)
REGISTER DESCRIPTION
ACRONYM
OFFSET
Watchdog timer control
WDTCTL
00h
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Table 6-28. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
ACRONYM
P1IN
OFFSET
00h
02h
04h
06h
0Ah
0Ch
0Eh
18h
16h
1Ah
1Ch
01h
03h
05h
07h
0Bh
0Ch
17h
1Eh
19h
1Bh
1Dh
Port P1 input
Port P1 output
Port P1 direction
P1OUT
P1DIR
P1REN
P1SEL0
P1SEL1
P1IV
Port P1 pulling enable
Port P1 selection 0
Port P1 selection 1
Port P1 interrupt vector word
Port P1 interrupt edge select
Port P1 complement selection
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
P1IES
P1SELC
P1IE
P1IFG
P2IN
Port P2 output
P2OUT
P2DIR
P2REN
P2SEL0
P2SEL1
P2SELC
P2IV
Port P2 direction
Port P2 pulling enable
Port P2 selection 0
Port P2 selection 1
Port P2 complement selection
Port P2 interrupt vector word
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
P2IES
P2IE
P2IFG
Table 6-29. RTC Registers (Base Address: 0300h)
REGISTER DESCRIPTION
ACRONYM
RTCCTL
RTCIV
OFFSET
00h
RTC control
RTC interrupt vector
RTC modulo
04h
RTCMOD
RTCCNT
08h
RTC counter
0Ch
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Table 6-30. Timer0_A3 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
ACRONYM
TA0CTL
OFFSET
TA0 control
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA0 counter
TA0CCTL0
TA0CCTL1
TA0CCTL2
TA0R
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA0 expansion 0
TA0CCR0
TA0CCR1
TA0CCR2
TA0EX0
TA0 interrupt vector
TA0IV
Table 6-31. Timer1_A3 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
ACRONYM
TA1CTL
OFFSET
00h
TA1 control
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA1 counter
TA1CCTL0
TA1CCTL1
TA1CCTL2
TA1R
02h
04h
06h
10h
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA1 expansion 0
TA1CCR0
TA1CCR1
TA1CCR2
TA1EX0
12h
14h
16h
20h
TA1 interrupt vector
TA1IV
2Eh
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Table 6-32. MPY32 Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
ACRONYM
MPY
OFFSET
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
16-bit operand 1 – multiply
16-bit operand 1 – signed multiply
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
MPYS
MAC
MACS
OP2
16 × 16 result low word
RESLO
RESHI
16 × 16 result high word
16 × 16 sum extension
SUMEXT
MPY32L
MPY32H
MPYS32L
MPYS32H
MAC32L
MAC32H
MACS32L
MACS32H
OP2L
32-bit operand 1 – multiply low word
32-bit operand 1 – multiply high word
32-bit operand 1 – signed multiply low word
32-bit operand 1 – signed multiply high word
32-bit operand 1 – multiply accumulate low word
32-bit operand 1 – multiply accumulate high word
32-bit operand 1 – signed multiply accumulate low word
32-bit operand 1 – signed multiply accumulate high word
32-bit operand 2 – low word
32-bit operand 2 – high word
OP2H
32 × 32 result 0 – least significant word
32 × 32 result 1
RES0
RES1
32 × 32 result 2
RES2
32 × 32 result 3 – most significant word
MPY32 control 0
RES3
MPY32CTL0
Table 6-33. eUSCI_A0 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
ACRONYM
UCA0CTLW0
UCA0CTLW1
UCA0BR0
OFFSET
00h
eUSCI_A control word 0
eUSCI_A control word 1
eUSCI_A control rate 0
eUSCI_A control rate 1
eUSCI_A modulation control
eUSCI_A status
02h
06h
UCA0BR1
07h
UCA0MCTLW
UCA0STAT
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
lUCA0IRTCTL
IUCA0IRRCTL
UCA0IE
08h
0Ah
0Ch
0Eh
10h
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
12h
13h
1Ah
1Ch
1Eh
UCA0IFG
UCA0IV
Table 6-34. eUSCI_B0 Registers (Base Address: 0540h)
REGISTER DESCRIPTION
ACRONYM
UCB0CTLW0
UCB0CTLW1
UCB0BR0
OFFSET
00h
eUSCI_B control word 0
eUSCI_B control word 1
eUSCI_B bit rate 0
02h
06h
eUSCI_B bit rate 1
UCB0BR1
07h
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Table 6-34. eUSCI_B0 Registers (Base Address: 0540h) (continued)
REGISTER DESCRIPTION
eUSCI_B status word
ACRONYM
UCB0STATW
UCB0TBCNT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA0
UCB0I2COA1
UCB0I2COA2
UCB0I2COA3
UCB0ADDRX
UCB0ADDMASK
UCB0I2CSA
UCB0IE
OFFSET
08h
0Ah
0Ch
0Eh
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Ah
2Ch
2Eh
eUSCI_B byte counter threshold
eUSCI_B receive buffer
eUSCI_B transmit buffer
eUSCI_B I2C own address 0
eUSCI_B I2C own address 1
eUSCI_B I2C own address 2
eUSCI_B I2C own address 3
eUSCI_B receive address
eUSCI_B address mask
eUSCI_B I2C slave address
eUSCI_B interrupt enable
eUSCI_B interrupt flags
UCB0IFG
eUSCI_B interrupt vector word
UCB0IV
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Table 6-35. Backup Memory Registers (Base Address: 0660h)
REGISTER DESCRIPTION
ACRONYM
BAKMEM0
BAKMEM1
BAKMEM2
BAKMEM3
BAKMEM4
BAKMEM5
BAKMEM6
BAKMEM7
BAKMEM8
BAKMEM9
BAKMEM10
BAKMEM11
BAKMEM12
BAKMEM13
BAKMEM14
BAKMEM15
OFFSET
00h
Backup memory 0
Backup memory 1
Backup memory 2
Backup memory 3
Backup memory 4
Backup memory 5
Backup memory 6
Backup memory 7
Backup memory 8
Backup memory 9
Backup memory 10
Backup memory 11
Backup memory 12
Backup memory 13
Backup memory 14
Backup memory 15
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
Table 6-36. ADC Registers (Base Address: 0700h)
REGISTER DESCRIPTION
REGISTER
ADCCTL0
ADCCTL1
ADCCTL2
ADCLO
OFFSET
00h
ADC control 0
ADC control 1
02h
ADC control 2
04h
ADC window comparator low threshold
ADC window comparator high threshold
ADC memory control 0
ADC conversion memory
ADC interrupt enable
06h
ADCHI
08h
ADCMCTL0
ADCMEM0
ADCIE
0Ah
12h
1Ah
1Ch
1Eh
ADC interrupt flags
ADCIFG
ADC interrupt vector word
ADCIV
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6.14 Identification
6.14.1 Revision Identification
The device revision information is included as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the Hardware Revision entries in Section 6.12.
6.14.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the Device ID entries in Section 6.12.
6.14.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
detail in MSP430 Programming With the JTAG Interface.
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7 Applications, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
7.1 Device Connection and Layout Fundamentals
This section discusses the recommended guidelines when designing with the MSP430 devices. These
guidelines are to make sure that the device has proper connections for powering, programming,
debugging, and optimum analog performance.
7.1.1 Power Supply Decoupling and Bulk Capacitors
TI recommends connecting a combination of a 10-µF plus a 100-nF low-ESR ceramic decoupling
capacitor to the DVCC and DVSS pins. Higher-value capacitors may be used but can impact supply rail
ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple
(within a few millimeters). Additionally, TI recommends separated grounds with a single-point connection
for better noise isolation from digital-to-analog circuits on the board and to achieve high analog accuracy.
DVCC
Digital
+
Power Supply
Decoupling
DVSS
10 µF
100 nF
Figure 7-1. Power Supply Decoupling
7.1.2 External Oscillator
This device supports only a low-frequency crystal (32 kHz) on the XIN and XOUT pins. External bypass
capacitors for the crystal oscillator pins are required.
It is also possible to apply digital clock signals to the XIN input pin that meet the specifications of the
respective oscillator if the appropriate XT1BYPASS mode is selected. In this case, the associated XOUT
pin can be used for other purposes. If the XIN and XOUT pins are not used, they must be terminated
according to Section 4.6.
Figure 7-2 shows a typical connection diagram.
XIN
XOUT
CL1
CL2
Figure 7-2. Typical Crystal Connection
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See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal
oscillator with the MSP430 devices.
7.1.3 JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or
MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the
connections also support the MSP-GANG production programmers, thus providing an easy way to
program prototype boards, if desired. Figure 7-3 shows the connections between the 14-pin JTAG
connector and the target device required to support in-system programming and debugging for 4-wire
JTAG communication. Figure 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are
identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSP-
FET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an
alternate connection (pin 4 instead of pin 2). The VCC sense feature detects the local VCC present on the
target board (that is, a battery or other local power supply) and adjusts the output signals accordingly.
Figure 7-3 and Figure 7-4 show a jumper block that supports both scenarios of supplying VCC to the target
board. If this flexibility is not required, the desired VCC connections may be hard-wired to eliminate the
jumper block. Pins 2 and 4 must not be connected at the same time.
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User's
Guide.
VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
DVCC
J2 (see Note A)
R1
47 kW
JTAG
RST/NMI/SBWTDIO
VCC TOOL
TDO/TDI
TDI
TDO/TDI
TDI
2
1
VCC TARGET
4
3
TMS
TMS
6
5
7
TEST
TCK
8
TCK
GND
RST
10
12
14
9
11
13
TEST/SBWTCK
DVSS
C1
1 nF
(see Note B)
A. If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,
make connection J2.
B. The upper limit for C1 is 1.1 nF when using current TI tools.
Figure 7-3. Signal Connections for 4-Wire JTAG Communication
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VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
J2 (see Note A)
DVCC
R1
47 kΩ
(see Note B)
JTAG
VCC TOOL
VCC TARGET
TDO/TDI
2
1
3
5
7
9
RST/NMI/SBWTDIO
4
6
TCK
8
GND
10
12
14
11
13
TEST/SBWTCK
DVSS
C1
1 nF
(see Note B)
A. Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the
debug or programming adapter.
B. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with
the device. The upper limit for C1 is 1.1 nF when using current TI tools.
Figure 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
7.1.4 Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function
Register (SFR), SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is
edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the
external NMI. When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either
pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.
If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an
external 47-kΩ pullup resistor to the RST/NMI pin with a 10-nF pulldown capacitor. The pulldown capacitor
should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire
JTAG mode with TI tools like FET interfaces or GANG programmers.
See the MP430FR4xx and MP430FR2xx Family User's Guide for more information on the referenced
control registers and bits.
7.1.5 Unused Pins
For details on the connection of unused pins, see Section 4.6.
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7.1.6 General Layout Recommendations
•
Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430
32-kHz Crystal Oscillators for recommended layout guidelines.
•
•
Proper bypass capacitors on DVCC and reference pins, if used.
Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital
switching signals such as PWM or JTAG signals away from the oscillator circuit.
•
Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See MSP430 System-Level ESD Considerations for guidelines.
7.1.7 Do's and Don'ts
During power up, power down, and device operation, DVCC must not exceed the limits specified in
Section 5.1. Exceeding the specified limits may cause malfunction of the device including erroneous writes
to RAM and FRAM.
7.2 Peripheral- and Interface-Specific Design Information
7.2.1 ADC Peripheral
7.2.1.1 Partial Schematic
Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used.
DVSS
Using an external
VREF+/VEREF+
positive reference
+
100 nF
10 µF
Using an external
negative reference
VEREF-
+
10 µF
100 nF
Figure 7-5. ADC Grounding and Noise Considerations
7.2.1.2 Design Requirements
As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should
be followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with
other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset
voltages that can add to or subtract from the reference or input voltages of the ADC. The general
guidelines in Section 7.1.1 combined with the connections shown in Figure 7-5 prevent this.
Quickly switching digital signals and noisy power supply lines can corrupt the conversion results, so keep
the ADC input trace shielded from those digital and power supply lines. Putting the MCU in low-power
mode during the ADC conversion improves the ADC performance in a noisy environment. If the device
includes the analog power pair inputs (AVCC and AVSS), TI recommends a noise-free design using
separate analog and digital ground planes with a single-point connection to achieve high accuracy.
Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The
internal reference module has a maximum drive current as described in the sections ADC Pin Enable and
1.2-V Reference Settings of the MSP430FR4xx and MSP430FR2xx Family User's Guide.
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The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are
selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage
enters the device. In this case, the 10-µF capacitor buffers the reference pin and filters any low-frequency
ripple. A bypass capacitor of 100 nF filters out any high-frequency noise.
7.2.1.3 Layout Guidelines
Components that are shown in the partial schematic (see Figure 7-5) should be placed as close as
possible to the respective device pins to avoid long traces, because they add additional parasitic
capacitance, inductance, and resistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),
because the high-frequency switching can be coupled into the analog signal.
7.2.2 CapTIvate Peripheral
This section provides a brief introduction to the CapTIvate technology with examples of PCB layout and
performance from the design kit. A more detailed description of the CapTIvate technology and the tools
needed to be successful, application development tools, hardware design guides, and software library,
can be found in the CapTIvate™ Technology Guide.
7.2.2.1 Device Connection and Layout Fundamentals
To learn more on how to design the CapTIvate Technology, see the Capacitive Touch Design Flow for
MSP430™ MCUs With CapTIvate™ Technology application report.
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7.2.2.2 Measurements
The following measurements are taken from the CapTIvate Technology Design Center, using the
CAPTIVATE-PHONE and CAPTIVATE-BSWP panels. Unless otherwise stated, the settings used are the
out-of-box settings, which can be found in the example projects. The intent of these measurements is to
show performance in a configuration that is readily available and reproducible.
Figure 7-6. CAPTIVATE-PHONE and CAPTIVATE-BSWP Panels
7.2.2.2.1 SNR
The Sensitivity, SNR, and Design Margin in Capacitive Touch Applications application report provides a
specific view for analyzing the signal-to-noise ratio of each element.
7.2.2.2.2 Sensitivity
To show sensitivity, in terms of farads, the internal reference capacitor is used as the change in
capacitance. In the mutual-capacitance case, the 0.1-pF capacitor is used. In the self-capacitance case,
the 1-pF reference capacitor is used. For simplicity, the results for only button 1 on both the CAPTIVATE-
PHONE and CAPTIVATE-BSWP panels are reported in Table 7-1.
Table 7-1. Button Sensitivity
CAPTIVATE-PHONE BUTTON 1 CAPTIVATE-BSWP BUTTON 1
CONVERSION CONVERSION
COUNTS FOR
0.1-pF
CHANGE
CONVERSION
TIME (µs)
CONVERSION COUNTS FOR
COUNT
GAIN
TIME (µs)
1-pF CHANGE
100
200
200
800
800
800
100
200
100
400
200
100
25
50
6
50
8
10
100
100
400
400
400
16
50
21
31
200
200
200
70
112
202
333
140
257
An alternative measure in sensitivity is the ability to resolve capacitance change over a wide range of base
capacitance. Table 7-2 shows example conversion times (for a self-mode measurement of discrete
capacitors) that can be used to achieve the desired resolution for a given parasitic load capacitance.
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Table 7-2. Button Sensitivity
COUNTS FOR COUNTS FOR COUNTS FOR
CAPACITANC CONVERSION CONVERSION
0.130-pF
CHANGE
0.260-pF
CHANGE
0.520-pF
CHANGE
E Cp (pF)(1)
COUNT/GAIN
TIME (µs)
23
50
400/100
550/100
650/100
850/100
1200/200
1200/150
200
275
325
425
600
600
10
11
11
11
11
13
23
24
23
22
23
26
35
37
36
35
37
41
78
150
150(2)
200(2)
(1) These measurements were taken with the CapTIvate MCU processor board with the 470-Ω series
resistors replaced with 0-Ω resistors.
(2) 0-V discharge voltage is used.
7.2.2.2.3 Power
The low-power mode LPM3 and LPM4 specifications in Section 5.7 are derived from the CapTIvate
technology design kit as indicated in the notes.
7.3 CapTIvate Technology Evaluation
Table 7-3 lists tools that demonstrate the use of the MSP430FR25x2 devices. See CapTIvate Evaluation
Tools to get started with evaluating the CapTIvate technology in various real-world application scenarios.
Consult these evaluation tool designs for additional guidance regarding schematics, layout, and software
implementation.
Table 7-3. Evaluation Tools
DESIGN NAME
LINK
MSP430 CapTIvate™ Touch Keypad BoosterPack Plug-in Module
http://www.ti.com/tool/boostxl-capkeypad
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8 器件和文档支持
8.1 入门和后续步骤
有关帮助您进行开发的 MSP 低功耗微控制器、工具和库的更多信息，请访问《MSP430™ 超低功耗传感和
测量 MCU 概述》。
8.2 器件命名规则
为了标示产品开发周期所处的阶段，TI 为所有 MSP MCU 器件的部件号分配了前缀。每个 MSP MCU 商用
系列产品成员都具有以下两个前缀之一：MSP 或 XMS。这些前缀代表了产品开发的发展阶段，即从工程原
型 (XMS) 直到完全合格的生产器件 (MSP)。
XMS - 实验器件，不一定代表最终器件的电气规格
MSP - 完全合格的生产器件
XMS 器件在供货时附带如下免责声明：
“开发中的产品用于内部评估用途。”
MSP 器件的特性已经全部明确，并且器件的质量和可靠性已经完全论证。TI 的标准保修证书对该器件适
用。
预测显示原型器件 (XMS) 的故障率大于标准生产器件。由于这些器件的预计最终使用故障率尚不确定，德
州仪器 (TI) 建议不要将它们用于任何生产系统。请仅使用合格的生产器件。
TI 器件的命名规则还包括一个带有器件系列名称的后缀。此后缀表示温度范围、封装类型和配送形式。图 8-
1 提供了解读完整器件名称的图例。
MSP 430 FR 2 522 I RHL T
Processor Family
MCU Platform
Device Type
Series
Distribution Format
Packaging
Temperature Range
Feature Set
Processor Family
MCU Platform
MSP = Mixed-signal processor
XMS = Experimental silicon
430 = MSP430 16-bit low-power platform
FR = FRAM
Device Type
Series
2 = Up to 16 MHz without LCD
Feature Set
522 = 2 CapTIvate blocks, 8KB of FRAM, 2KB of RAM, up to 8 CapTIvate I/Os
512 = 1 CapTIvate block, 8KB of FRAM, 2KB of RAM, up to 4 CapTIvate I/Os
Temperature Range
Packaging
I = –40°C to 85°C
www.ti.com/packaging
Distribution Format
T = Small reel
R = Large reel
No marking = Tube or tray
图 8-1. 器件命名规则
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8.3 工具和软件
表 8-1 列出 调试 的调试功能。请参阅《适用于 MSP430 MCU 的 Code Composer Studio IDE 用户指
南》，以了解有关可用 功能）的详细信息。
表 8-1. 硬件 特性
四线制
JTAG
两线制
JTAG
断点
(N)
跟踪缓冲 LPMx.5 调试支
MSP430 架构
范围断点
有
时钟控制
是
状态序列发生器
否
EEM 版本
器
持
MSP430Xv2
有
有
3
否
否
S
设计套件与评估模块
适用于 MSP430FR2x MCU 的 MSP-TS430RHL20 20 引脚目标开发板
MSP-TS430RHL20 是独立的 ZIF 插接目标板，用于通过 JTAG 接口或 Spy Bi-Wire（双线制 JTAG）协议
对 MSP430 进行系统内编程和调试。该开发板支持采用 20 引脚 VQFN 封装（TI 封装代码：RHL）的所有
MSP430FR252x 和 MSP430FR242x 闪存部件。
MSP-FET + MSP-TS430RHL20 FRAM 微控制器开发套件包
MSP-FET430RHL20-BNDL
开发套件包包含适用于
MSP430FR2422
微控制器（例如
MSP430FR2422RHL）且支持 20 引脚 RHL 封装的两种调试工具。这两种工具分别为 MSP-TS430RHL20
和 MSP-FET。
软件
MSP430Ware™ 软件
MSP430Ware 软件集合了所有 MSP430 器件的代码示例、数据表以及其他设计资源，打包提供给用户。除
了提供已有 MSP430 设计资源的完整集合外，MSP430Ware 软件还包含名为 MSP430 驱动程序库的高级
API。借助该库可以轻松地对 MSP430 硬件进行编程。MSP430Ware 软件以 CCS 组件或独立软件包两种形
式提供。
MSP430FR2422 代码示例
根据不同应用需求配置各集成外设的每个 MSP 器件均具备相应的 C 代码示例。
MSP 驱动程序库
驱动程序库的抽象化 API 通过提供易于使用的函数调用使您不再拘泥于 MSP430 硬件的细节。完整的文档
通过具有帮助意义的 API 指南交付，其中包括有关每个函数调用和经过验证的参数的详细信息。开发人员可
以使用驱动程序库功能，以最低开销编写完整项目。
MSP EnergyTrace™ 技术
MSP430 微控制器的 EnergyTrace 技术是基于能量的代码分析工具，用于测量和显示应用的能量配置，同
时协助优化应用以实现超低功耗。
ULP（超低功耗）Advisor
ULP Advisor™软件是一款辅助工具，旨在指导开发人员编写更为高效的代码，从而充分利用 MSP
和
MSP432 微控制器独特的 超低功耗 功能。ULP Advisor 的目标人群是微控制器的资深开发者和开发新手，
可以根据详尽的 ULP 检验表检查代码，以便最大限度地利用应用程序。在编译时，ULP Advisor 会提供通
知和备注以突出显示代码中可以进一步优化的区域，进而实现更低功耗。
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适用于 MSP 超低功耗微控制器的 FRAM 嵌入式软件实用程序
FRAM 实用程序旨在作为不断扩充的嵌入式软件实用程序集合，其中的实用程序充分利用 FRAM 的超低功
耗和近乎无限次的写入寿命。这些实用程序适用于 MSP430FRxx FRAM 微控制器并提供示例代码协助应用
程序开发。其中的实用程序包含功耗计算实用程序 (CTPL)。CTPL 是一套实用程序 API 集，通过 CTPL 能
够轻松使用 LPMx.5 低功耗模式以及强大的关断模式，允许应用程序在检测到功率损耗时节约能耗并恢复关
键的系统元件。
IEC60730 软件包
IEC60730 MSP430 软件包经过专门开发，用于协助客户达到 IEC 60730-1:2010（家用及类似用途的自动化
电气控制 - 第 1 部分：一般要求）B 类产品的要求。其中涵盖家用电器、电弧检测器、电源转换器、电动工
具、电动自行车及其他诸多产品。IEC60730 MSP430 软件包可以嵌入在 MSP430 中 运行的客户应用， 从
而帮助客户简化其消费类器件在功能安全方面遵循 IEC 60730-1:2010 B 类规范的认证工作。
适用于 MSP 的定点数学库
MSP IQmath 和 Qmath 库是为 C 语言开发者提供的一套经过高度优化的高精度数学运算函数集合，能够将
浮点算法无缝嵌入 MSP430 和 MSP432 器件的定点代码中。这些例程通常用于计算密集型实时 应用， 而
优化的执行速度、高精度以及超低能耗通常是影响这些实时应用的关键因素。与使用浮点数学算法编写的同
等代码相比，使用 IQmath 和 Qmath 库可以大幅提高执行速度并显著降低能耗。
适用于 MSP430 的浮点数学库
TI 在低功耗和低成本微控制器领域锐意创新，为您提供 MSPMATHLIB。这是标量函数的浮点数学库，能够
充分利用器件的智能外设，使性能提升高达 26 倍。Mathlib 能够轻松集成到您的设计中。该运算库免费使用
并集成在 Code Composer Studio 和 IAR IDE 中。如需深入了解该数学库及相关基准，请阅读用户指南。
开发工具
适用于 MSP 微控制器的 Code Composer Studio™ 集成开发环境
Code Composer Studio 是一种集成开发环境 (IDE)，支持所有 MSP 微控制器。Code Composer Studio 包
含一整套开发和调试嵌入式应用 的嵌入式软件实用程序的工具。它包含了优化的 C/C++ 编译器、源代码编
辑器、项目构建环境、调试器、描述器以及其他多种 功能。直观的 IDE 提供了单个用户界面，有助于完成
应用程序开发流程的每个步骤。熟悉的实用程序和界面可提升用户的入门速度。Code Composer Studio 将
Eclipse 软件框架的优点和 TI 先进的嵌入式调试功能相结合，为嵌入式开发人员提供了一种功能丰富的优异
开发环境。当 CCS 与 MSP MCU 搭配使用时，可以使用独特而强大的插件和嵌入式软件实用程序，从而充
分利用 MSP 微控制器的功能。
命令行编程器
MSP Flasher 是一款基于 shell 的开源接口，可使用 JTAG 或 Spy-Bi-Wire (SBW) 通信通过 FET 编程器或
eZ430 对 MSP 微控制器进行编程。MSP Flasher 可用于将二进制文件（.txt 或 .hex 文件）直接下载到
MSP 微控制器，而无需使用 IDE。
80
器件和文档支持
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MSP430FR2522, MSP430FR2512
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ZHCSHB4C –JANUARY 2018–REVISED DECEMBER 2019
MSP MCU 编程器和调试器
MSP-FET 是一款强大的仿真开发工具（通常称为调试探针），可让用户在 MSP 低功耗微控制器 (MCU) 上
快速进行应用开发。创建 MCU 软件通常需要将生成的二进制程序下载到 MSP 器件，以进行验证和调试。
MSP-FET 在主机和目标 MSP 间提供调试通信通道。此外，MSP-FET 还在计算机的 USB 接口和 MSP
UART 之间提供反向通道 UART 连接。这为 MSP 编程器提供了一种便捷方法，实现了 MSP 和在计算机上
运行的终端之间的串行通信。
MSP-GANG 生产编程器
MSP Gang 编程器可同时对多达八个完全相同的 MSP430 或 MSP432 闪存或 FRAM 器件进行编程。MSP
Gang 编程器可使用标准的 RS-232 或 USB 连接与主机 PC 相连并提供灵活的编程选项，允许用户完全自定
义流程。MSP Gang 编程器配有扩展板“Gang 分离器”，可在 MSP Gang 编程器和多个目标器件间实现互
连。
8.4 文档支持
以下文档介绍了 MSP430FR25x2 微控制器。www.ti.com.cn 网站上提供了这些文档的副本。
接收文档更新通知
如需接收文档更新通知（包括器件勘误表），请转至
ti.com.cn
上相关器件的产品文件夹（例如，
MSP430FR2522）。请单击右上角的“通知我”按钮。点击注册后，即可收到产品信息更改每周摘要（如
有）。有关更改的详细信息，请查阅已修订文档的修订历史记录。
勘误
《MSP430FR2522 器件勘误表》
介绍了该器件的所有器件修订版本功能规格的已知例外情况。
《MSP430FR2512 器件勘误表》
介绍了该器件的所有器件修订版本功能规格的已知例外情况。
用户指南
《MSP430FR4xx 和 MSP430FR2xx 系列用户指南》
可 说明 。
《MSP430 FRAM 器件引导加载程序 (BSL) 用户指南》
BSL 能在 MSP430 MCU 项目开发和更新阶段对存储器进行编程。BSL 可由使用串行协议发送命令的工具激
活。BSL 支持用户控制 MSP430 器件的活动，可与个人计算机或其他设备进行数据交换。
《通过 JTAG 接口对 MSP430 进行编程》
此文档介绍了使用 JTAG 通信端口擦除、编程和验证基于 MSP430 闪存和 FRAM 的微控制器系列的存储器
模块所需的功能。此外，该文档还介绍了如何编程所有 MSP430 器件上均具备的 JTAG 访问安全保险丝。
此文档介绍了使用标准四线制 JTAG 接口和两线制 JTAG 接口（也称为 Spy-Bi-Wire (SBW)）的器件访问。
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产品主页链接: MSP430FR2522 MSP430FR2512
MSP430FR2522, MSP430FR2512
ZHCSHB4C –JANUARY 2018–REVISED DECEMBER 2019
www.ti.com.cn
《MSP430 硬件工具用户指南》
此手册介绍了 TI MSP-FET430 闪存仿真工具 (FET) 的硬件。FET 是针对 MSP430 超低功耗微控制器的程
序开发工具。
应用报告
《MSP430 32kHz 晶体振荡器》
选择合适的晶体、正确的负载电路和适当的电路板布局是实现稳定的晶体振荡器的关键。该应用报告总结了
晶体振荡器的功能，介绍了用于选择合适的晶体以实现 MSP430 超低功耗运行的参数。此外，还给出了正
确电路板布局的提示和示例。此外，为了确保振荡器在大规模生产后能够稳定运行，还可能需要进行一些振
荡器测试，该文档中提供了有关这些测试的详细信息。
《MSP430 系统级 ESD 注意事项》
随着芯片技术向更低电压方向发展以及设计具有成本效益的超低功耗组件的需求的出现，系统级 ESD 要求
变得越来越苛刻。该应用报告介绍了不同的 ESD 主题，旨在帮助电路板设计人员和 OEM 理解并设计出稳
健耐用的系统级设计。另外还介绍了若干实际应用系统级 ESD 保护设计示例及其结果。
8.5 相关链接
表 8-2 列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品
的快速链接。
表 8-2. 相关链接
器件
产品文件夹
单击此处
单击此处
立即订购
单击此处
单击此处
技术文档
单击此处
单击此处
工具和软件
单击此处
单击此处
支持和社区
单击此处
单击此处
MSP430FR2522
MSP430FR2512
8.6 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术
规范，并且不一定反映 TI 的观点；请参见 TI 的 《使用条款》。
TI E2E™ 社区
TI 的工程师交流 (E2E) 社区. 此社区的创建目的是为了促进工程师之间协作。在 e2e.ti.com 中，您可以提
问、共享知识、拓展思路，在同领域工程师的帮助下解决问题。
TI 嵌入式处理器维基网页
德州仪器 (TI) 嵌入式处理器维基网页。此网站的建立是为了帮助开发人员熟悉德州仪器 (TI) 的嵌入式处理
器，并且也为了促进与这些器件相关的硬件和软件的总体知识的创新和增长。
8.7 商标
CapTIvate, MSP430, BoosterPack, MSP430Ware, EnergyTrace, ULP Advisor, 适用于 MSP 微控制器的
Code Composer Studio, E2E are trademarks of Texas Instruments.
CapTIvate, MSP430, BoosterPack, are trademarks of ~ Texas Instruments.
All other trademarks are the property of their respective owners.
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MSP430FR2522, MSP430FR2512
www.ti.com.cn
ZHCSHB4C –JANUARY 2018–REVISED DECEMBER 2019
8.8 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
8.9 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
8.10 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
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产品主页链接: MSP430FR2522 MSP430FR2512
MSP430FR2522, MSP430FR2512
ZHCSHB4C –JANUARY 2018–REVISED DECEMBER 2019
www.ti.com.cn
9 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
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机械、封装和可订购信息
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MSP430FR2522, MSP430FR2512
www.ti.com.cn
ZHCSHB4C –JANUARY 2018–REVISED DECEMBER 2019
版权 © 2018–2019, Texas Instruments Incorporated
机械、封装和可订购信息
85
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产品主页链接: MSP430FR2522 MSP430FR2512
MSP430FR2522, MSP430FR2512
ZHCSHB4C –JANUARY 2018–REVISED DECEMBER 2019
www.ti.com.cn
PACKAGE OUTLINE
VQFN - 1 mm max height
RHL0020A
PLASTIC QUAD FLATPACK- NO LEAD
A
3.6
3.4
B
PIN 1 INDEX AREA
4.6
4.4
C
1 MAX
SEATING PLANE
0.08
C
2.05 0.1
2X 1.5
SYMM
0.5
0.3
20X
(0.2) TYP
10
11
14X 0.5
9
12
SYMM
2X
3.5
21
3.05 0.1
19
2
0.29
20X
0.19
0.1
0.05
20
4X (0.2)
2X (0.55)
1
PIN 1 ID
(OPTIONAL)
C
A B
C
4219071 / A 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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机械、封装和可订购信息
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MSP430FR2522, MSP430FR2512
www.ti.com.cn
ZHCSHB4C –JANUARY 2018–REVISED DECEMBER 2019
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RHL0020A
PLASTIC QUAD FLATPACK- NO LEAD
(3.3)
(2.05)
2X (1.5)
SYMM
1
20
2X (0.4)
20X (0.6)
19
2
20X (0.24)
14X (0.5)
SYMM
21
(3.05) (4.3)
6X (0.525)
2X (0.75)
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
9
12
(R0.05) TYP
(Ø0.2) VIA
TYP)
10
11
4X (0.2)
4X
(0.775)
2X (0.55)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 18X
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219071 / A 06/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271)
.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to theri
locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
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MSP430FR2522, MSP430FR2512
ZHCSHB4C –JANUARY 2018–REVISED DECEMBER 2019
www.ti.com.cn
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RHL0020A
PLASTIC QUAD FLATPACK- NO LEAD
(3.3)
2X (1.5)
(0.55)
TYP
(0.56)
TYP
1
20
SOLDER MASK EDGE
TYP
20X (0.6)
2
19
20X (0.24)
14X (0.5)
SYMM
(1.05)
TYP
(4.3)
21
6X
(0.85)
(R0.05) TYP
METAL
TYP
9
12
2X
(0.775)
2X (0.25)
11
10
4X (0.2)
6X (0.92)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1mm THICK STENCIL
EXPOSED PAD
75% PRINTED COVERAGE BY AREA
SCALE: 20X
4219071 / A 06/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
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机械、封装和可订购信息
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产品主页链接: MSP430FR2522 MSP430FR2512
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430FR2512IPW16
MSP430FR2512IPW16R
MSP430FR2512IRHLR
MSP430FR2512IRHLT
MSP430FR2522IPW16
MSP430FR2522IPW16R
MSP430FR2522IRHLR
MSP430FR2522IRHLT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
VQFN
PW
PW
16
16
20
20
16
16
20
20
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
FR2512
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
FR2512
FR2512
FR2512
FR2522
FR2522
FR2522
FR2522
RHL
RHL
PW
VQFN
250
90
RoHS & Green
RoHS & Green
TSSOP
TSSOP
VQFN
PW
2000 RoHS & Green
3000 RoHS & Green
RHL
RHL
VQFN
250
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jul-2022
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jan-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430FR2512IPW16R TSSOP
PW
RHL
RHL
PW
16
20
20
16
20
20
2000
3000
250
330.0
330.0
180.0
330.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
6.9
3.71
3.71
6.9
5.6
4.71
4.71
5.6
1.6
1.1
1.1
1.6
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
MSP430FR2512IRHLR
MSP430FR2512IRHLT
VQFN
VQFN
MSP430FR2522IPW16R TSSOP
2000
3000
250
MSP430FR2522IRHLR
MSP430FR2522IRHLT
VQFN
VQFN
RHL
RHL
3.71
3.71
4.71
4.71
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jan-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430FR2512IPW16R
MSP430FR2512IRHLR
MSP430FR2512IRHLT
MSP430FR2522IPW16R
MSP430FR2522IRHLR
MSP430FR2522IRHLT
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
PW
RHL
RHL
PW
16
20
20
16
20
20
2000
3000
250
367.0
367.0
210.0
367.0
367.0
210.0
367.0
367.0
185.0
367.0
367.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
2000
3000
250
RHL
RHL
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jan-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
MSP430FR2512IPW16
MSP430FR2522IPW16
PW
PW
TSSOP
TSSOP
16
16
90
90
530
530
10.2
10.2
3600
3600
3.5
3.5
Pack Materials-Page 3
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不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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