MSP430FR2533IRHBT [TI]
具有 16 个触摸 IO（24 个传感器）、16KB FRAM、2KB SRAM、19 个 IO、10 位 ADC 的电容式触控 MCU | RHB | 32 | -40 to 85;
| 型号： | MSP430FR2533IRHBT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 16 个触摸 IO（24 个传感器）、16KB FRAM、2KB SRAM、19 个 IO、10 位 ADC 的电容式触控 MCU | RHB | 32 | -40 to 85 静态存储器 外围集成电路 传感器 |
| 文件： | 总109页 (文件大小：3951K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532
ZHCSET6E –NOVEMBER 2015–REVISED DECEMBER 2019
MSP430FR263x、MSP430FR253x 电容式触控感应混合信号微控制器
1 器件概述
1.1 特性
1
• CapTIvate ™技术 – 电容式触控
– 性能
• 嵌入式微控制器
– 16 位 RISC 架构
– 四路同步快速电极扫描
– 支持点数高达 1024 的高分辨率滑块
– 接近感应
– 支持的时钟频率最高可达 16MHz
– 3.6V 至 1.8V 的宽电源电压范围（最低电源电压
受限于 SVS 电平，请参阅 SVS 规格）
• 优化的超低功耗模式
– 可靠性
– 激活模式：126µA/MHz（典型值）
– 待机模式：四个传感器的触摸唤醒电流小于 5µA
– 提高了针对电力线、射频及其他环境噪声的抗
扰度
– 内置扩展频谱、自动调优、噪声滤除和消抖算
法
– 采用 32768Hz 晶振的 LPM3.5 实时时钟 (RTC)
计数器：730nA（典型值）
– 提供可靠的触控解决方案，具有 10V RMS 共
模噪声、4kV 电气快速瞬变以及 15kV 静电放
电，符合 IEC‑61000-4-6、IEC‑61000-4-4 和
IEC‑61000-4-2 标准
– 降低了射频辐射，简化了电气设计
– 支持金属触控和防水设计
– 关断电流 (LPM4.5)：16nA（典型值）
• 高性能模拟
– 8 通道 10 位模数转换器 (ADC)
– 1.5V 的内部基准电压
– 采样与保持 200ksps
• 增强型串行通信
– 灵活性
– 两个增强型通用串行通信接口 (eUSCI_A) 支持
UART、IrDA 和 SPI
– 一个 eUSCI (eUSCI_B) 支持 SPI 和 I2C
• 智能数字外设
– 多达 16 个自电容式电极和 64 个互电容式电极
– 在同一设计中混合使用自电容式电极和互电容
式电极
– 支持多点触控功能
– 宽电容检测范围；0 至 300pF 宽电极范围
– 低功耗
– 四个 16 位计时器
– 两个计时器，每个计时器具有三个捕捉/比较寄
存器 (Timer_A3)
– 两个计时器，每个计时器具有两个捕捉/比较寄
存器 (Timer_A2)
– 四个传感器的触摸唤醒电流小于 5µA
– 触摸唤醒状态机支持在 CPU 休眠过程中进行
电极扫描
– 一个采用 CapTIvate 技术的 16 位计时器
– 一个仅用作计数器的 16 位 RTC
– 16 位循环冗余校验 (CRC)
– 用于环境补偿、滤波和阈值检测的硬件加速
– 易于使用
– CapTIvate 设计中心 PC GUI 允许工程师对电
容按钮进行实时设计和调试，无需编写代码
• 低功耗铁电 RAM (FRAM)
– 容量高达 15.5KB 的非易失性存储器
– 内置错误修正码 (ECC)
– 可配置的写保护
– 存储于 ROM 中的 CapTIvate 软件库为客户应
用提供充足的 FRAM
– 对程序、常量和存储的统一存储
– 耐写次数达 1015
– 抗辐射和非磁性
次
– FRAM 与 SRAM 之比高达 4：1
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLAS942
MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532
ZHCSET6E –NOVEMBER 2015–REVISED DECEMBER 2019
www.ti.com.cn
• 时钟系统 (CS)
– 目标开发板 (MSP‑TS430RGE24A)
– 易于使用的生态系统
– 片上 32kHz RC 振荡器 (REFO)
– 带有锁频环 (FLL) 的片上 16MHz 数控振荡器
– CapTIvate 设计中心 – 代码生成、可自定义
GUI、实时调优
(DCO)
– 室温下的精度为 ±1%（具有片上基准）
– 片上超低频 10kHz 振荡器 (VLO)
– 片上高频调制振荡器 (MODOSC)
– 外部 32kHz 晶振 (LFXT)
– 可编程 MCLK 预分频器（1 至 128）
– 通过可编程预分频器（1、2、4 或 8）从 MCLK
获得的 SMCLK
• 系列成员（另请参阅 器件比较）
– MSP430FR2633：15KB 程序 FRAM、512 字节
信息 FRAM、4KB RAM、多达 16 个自电容式传
感器或 64 个互电容式传感器
– MSP430FR2533：15KB 程序 FRAM、512 字节
信息 FRAM、2KB RAM、多达 16 个自电容式传
感器或 24 个互电容式传感器
– MSP430FR2632：8KB 程序 FRAM、512 字节
信息 FRAM、2KB RAM、多达 8 个自电容式传
感器或 16 个互电容式传感器
– MSP430FR2532：8KB 程序 FRAM、512 字节
信息 FRAM、1KB RAM、多达 8 个自电容式传
感器或 8 个互电容式传感器
• 通用输入/输出和引脚功能
– 共计 19 个 I/O（采用 TSSOP-32 封装）
– 16 个中断引脚（P1 和 P2）可以将 MCU 从低功
耗模式下唤醒
• 开发工具和软件
– 开发工具
• 封装选项
– MSP CapTIvate™ MCU 开发套件评估：与
CAPTIVATE-PGMR 编程器和电容式触控
MSP430FR2633 MCU 板
– 32 引脚：VQFN (RHB)
– 32 引脚：TSSOP (DA)
– 24 引脚：VQFN (RGE)
– 24 引脚：DSBGA (YQW)
CAPTIVATE‑FR2633 配合使用
1.2 应用
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电子智能锁、门键盘和读取器
车库门系统
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无线扬声器和耳机
手持式视频游戏控制器
A/V 接收器
入侵 HMI 键盘和控制面板
电动百叶窗
白色家电
遥控器
小型电器
个人电子产品
园艺和电动工具
1.3 说明
MSP430FR263x 和 MSP430FR253x 是用于电容式触控检测的超低功耗 MSP430™ 微控制器，采用
CapTIvate™ 触控技术，适用于按钮、滑块、滚轮及接近传感 应用中的数字输入 D 类音频放大器。采用
CapTIvate 技术的 MSP430 MCU 提供市面上最高集成度和自主性的电容式触控解决方案，具有高可靠性和
抗噪能力以及最低功耗。TI 的电容式触控技术支持在同一设计方案中同时使用自电容式和互电容式电极，最
大限度地提高了灵活性。采用 CapTIvate 技术的 MSP430 MCU 可以穿透厚玻璃、塑料外壳、金属和木材，
在恶劣的环境（包括潮湿、油腻和脏污环境）中工作。
TI 电容式触控感应 MSP430 MCU 由一个由各种软、硬件资源组成的生态系统提供支持，并配套提供有参考
设计和代码示例，可帮助您快速开展设计。开发套件包括 MSP-CAPT-FR2633 CapTIvate 技术开发套件。
TI 还提供免费的软件，如 CapTIvate 设计中心，工程师可以在其中 借助 方便易用的 GUI 和
MSP430Ware™ 软件以及包括 CapTIvate 技术指南在内的综合性文档快速进行应用开发。
TI 的 MSP430 超低功耗 (ULP) FRAM 微控制器平台将独特的嵌入式 FRAM 和全面的超低功耗系统架构相
结合，从而使系统设计人员能够在降低能耗的同时提升性能。FRAM 技术将 RAM 的低能耗快速写入、灵活
性和耐用性与闪存的非易失性相结合。
有关完整的模块说明，请参阅《MSP430FR4xx 和 MSP430FR2xx 系列器件用户指南》。
2
器件概述
版权 © 2015–2019, Texas Instruments Incorporated
MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532
www.ti.com.cn
ZHCSET6E –NOVEMBER 2015–REVISED DECEMBER 2019
器件信息(1)
封装
器件型号
MSP430FR2633IRHB
MSP430FR2533IRHB
MSP430FR2633IDA
MSP430FR2533IDA
MSP430FR2632IRGE
MSP430FR2532IRGE
MSP430FR2633IYQW
MSP430FR2632IYQW
封装尺寸(2)
5mm x 5mm
VQFN (32)
VQFN (32)
5mm × 5mm
TSSOP (32)
11mm × 6.2mm
11mm × 6.2mm
4mm x 4mm
TSSOP (32)
超薄四方扁平无引线 (VQFN) (24)
超薄四方扁平无引线 (VQFN) (24)
DSBGA (24)
4mm x 4mm
2.29mm × 2.34mm
2.29mm × 2.34mm
DSBGA (24)
(1) 要获得最新的产品、封装和订购信息，请参见封装选项附录（节 9），或者访问德州仪器 (TI) 网站
www.ti.com.cn。
(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参见机械数据（节 9中）。
CAUTION
系统级静电放电 (ESD) 保护必须符合器件级 ESD 规范，以防发生电气过载或对
数据或代码存储器造成干扰。有关更多信息，请参阅《MSP430 系统级 ESD 注
意事项》。
版权 © 2015–2019, Texas Instruments Incorporated
器件概述
3
MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532
ZHCSET6E –NOVEMBER 2015–REVISED DECEMBER 2019
www.ti.com.cn
1.4 功能框图
图 1-1 给出了功能框图。
XIN
XOUT
P1.x/P2.x
P3.x
I/O Ports
P1, P2
2×8 IOs
Interrupt
and Wakeup
PA
I/O Ports
P3
1×3 IOs
ADC
DVCC
DVSS
CapTIvate
FRAM
RAM
LFXT
Clock
MPY32
Power
Management
Module
Up to 8-ch
single-ended
10 bit
16-channel
8-channel
15KB+512B
8KB+512B
4KB
2KB
RST/NMI
VREG
32-bit
Hardware
Multiplier
System
PB
1×3 IOs
200 ksps
1×16 IOs
MAB
MDB
16-MHz CPU
including
16 Registers
EEM
RTC
Counter
2×eUSCI_A
CRC16
2×TA
2×TA
eUSCI_B0
(SPI, I2C)
BAKMEM
SYS
TCK
TMS
16-bit
Cyclic
Redundancy
Check
16-bit
Real-Time
Clock
32-byte
Backup
Memory
Timer_A3
3 CC
Registers
Timer_A2
2 CC
Registers
(UART,
IrDA, SPI)
JTAG
SBW
TDI/TCLK
TDO
Watchdog
LPM3.5 Domain
SBWTCK
SBWTDIO
图 1-1. 功能框图
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MCU 的主电源对 DVCC 和 DVSS 分别为数字模块和模拟模块供电。推荐的旁路电容和去耦电容分别为
4.7μF 至 10μF 和 0.1μF，精度为 ±5%。
VREG 是 CapTIvate 稳压器的去耦电容。所需去耦电容的建议值为 1µF，最大等效串联电阻 (ESR) ≤
200mΩ。
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P1 和 P2 特有引脚中断功能，可将 MCU 从所有低功耗模式 (LPM) 唤醒（包括 LPM3.5 和 LPM4）。
每个 Timer_A3 具有三个捕捉/比较寄存器。仅 CCR1 和 CCR2 从外部连接。CCR0 寄存器仅用于内部周
期时序和生成中断。
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每个 Timer_A2 具有两个捕捉/比较寄存器。两个寄存器仅用于内部周期时序和生成中断。
在 LPM3 模式下，CapTIvate 可在其他外设停止工作的情况下继续工作。
4
器件概述
版权 © 2015–2019, Texas Instruments Incorporated
MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532
www.ti.com.cn
ZHCSET6E –NOVEMBER 2015–REVISED DECEMBER 2019
内容
1
器件概述.................................................... 1
1.1 特性 ................................................... 1
6.1 Overview ............................................ 45
6.2 CPU ................................................. 45
6.3 Operating Modes.................................... 45
6.4 Interrupt Vector Addresses.......................... 47
6.5 Bootloader (BSL).................................... 48
6.6 JTAG Standard Interface............................ 49
6.7 Spy-Bi-Wire Interface (SBW)........................ 49
6.8 FRAM................................................ 49
6.9 Memory Protection .................................. 49
6.10 Peripherals .......................................... 50
6.11 Input/Output Diagrams .............................. 60
6.12 Device Descriptors .................................. 67
6.13 Memory.............................................. 68
6.14 Identification ......................................... 76
Applications, Implementation, and Layout........ 77
1.2 应用 ................................................... 2
1.3 说明 ................................................... 2
1.4 功能框图 .............................................. 4
修订历史记录............................................... 6
Device Comparison ..................................... 8
3.1 Related Products ..................................... 8
Terminal Configuration and Functions.............. 9
4.1 Pin Diagrams ......................................... 9
4.2 Pin Attributes ........................................ 13
4.3 Signal Descriptions.................................. 16
4.4 Pin Multiplexing ..................................... 19
4.5 Buffer Types......................................... 19
4.6 Connection of Unused Pins ......................... 19
Specifications ........................................... 20
5.1 Absolute Maximum Ratings......................... 20
5.2 ESD Ratings ........................................ 20
5.3 Recommended Operating Conditions............... 20
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7.1
Device Connection and Layout Fundamentals...... 77
7.2
Peripheral- and Interface-Specific Design
Information .......................................... 80
7.3 CapTIvate Technology Evaluation .................. 83
器件和文档支持 .......................................... 84
8.1 入门和后续步骤...................................... 84
8.2 器件命名规则 ........................................ 84
8.3 工具和软件 .......................................... 85
8.4 文档支持............................................. 87
8.5 相关链接............................................. 88
8.6 社区资源............................................. 88
8.7 商标.................................................. 88
8.8 静电放电警告 ........................................ 89
8.9 Export Control Notice ............................... 89
8.10 Glossary ............................................. 89
机械、封装和可订购信息................................ 90
5.4
Active Mode Supply Current Into VCC Excluding
External Current..................................... 21
5.5 Active Mode Supply Current Per MHz .............. 21
5.6
5.7
5.8
5.9
Low-Power Mode LPM0 Supply Currents Into VCC
Excluding External Current.......................... 21
Low-Power Mode (LPM3 and LPM4) Supply
Currents (Into VCC) Excluding External Current .... 22
Low-Power Mode LPMx.5 Supply Currents (Into
VCC) Excluding External Current.................... 23
Typical Characteristics - Low-Power Mode Supply
Currents ............................................. 24
5.10 Thermal Resistance Characteristics ................ 25
5.11 Timing and Switching Characteristics............... 26
Detailed Description ................................... 45
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6
版权 © 2015–2019, Texas Instruments Incorporated
内容
5
MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532
ZHCSET6E –NOVEMBER 2015–REVISED DECEMBER 2019
www.ti.com.cn
2 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
从修订版本 D 更改为修订版本 E
Changes from August 20, 2019 to December 9, 2019
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Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in
Section 5.3, Recommended Operating Conditions ............................................................................. 20
Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in
Section 5.3, Recommended Operating Conditions ............................................................................. 20
Changed the note that begins "A capacitor tolerance of ±20% or better is required..." in Section 5.3,
Recommended Operating Conditions ............................................................................................ 20
Changed the note that begins "Requires external capacitors at both terminals..." in Table 5-4, XT1 Crystal
Oscillator (Low Frequency) ........................................................................................................ 28
Added the t(int) parameter in Table 5-10, Digital Inputs ........................................................................ 32
Added the tTA,cap parameter in Table 5-13, Timer_A............................................................................ 34
Corrected the test conditions for the RI,MUX parameter in Table 5-20, ADC, Power Supply and Input Range
Conditions ............................................................................................................................ 40
Added the note that begins "tSample = ln(2n+1) × τ ..." in Table 5-21, ADC, 10-Bit Timing Parameters.................... 40
Moved CREG and CELECTRODE from Section 5.3, Recommended Operating Conditions to Table 5-23, CapTIvate
Electrical Characteristics ........................................................................................................... 42
Changed the CRC covered end address to 0x1AF5 in note (1) in Table 6-22, Device Descriptors ..................... 67
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从修订版本 C 更改为修订版本 D
Changes from August 29, 2018 to August 19, 2019
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更新了节 1.1特性...................................................................................................................... 1
在 节 1.1，特性 中添加了“目标开发板”信息 ....................................................................................... 2
Changed "fCONVER = 2 MHz" to "fCONVER = 4 MHz" in the note that begins "CapTIvate technology works in LPM3
with 64 mutual-capacitance buttons" on Section 5.7, Low-Power Mode (LPM3 and LPM4) Supply Currents (Into
VCC) Excluding External Current .................................................................................................. 22
Added the tTA,cap parameter in Table 5-13, Timer_A............................................................................ 34
Changed the parameter symbol from RI to RI,MUX in Table 5-20 , ADC, Power Supply and Input Range Conditions . 40
Added RI,Misc TYP value of 34 kΩ in Table 5-20 , ADC, Power Supply and Input Range Conditions ................... 40
Added formula for RI calculation in Table 5-21 , ADC, 10-Bit Timing Parameters ......................................... 40
Removed the description of "±3°C" in table note that starts "The device descriptor structure ..." of Table 5-22,
ADC, 10-Bit Linearity Parameters................................................................................................. 41
Moved CREG and CELECTRODE from Section 5.3, Recommended Operating Conditions to Table 5-23, CapTIvate
Electrical Characteristics ........................................................................................................... 42
Added test condition for CELECTRODE in Table 5-23 , CapTIvate Electrical Characteristics................................. 42
Changed the symbol and description of the DCCAPCLK parameter in Table 5-23, CapTIvate Electrical
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Characteristics ...................................................................................................................... 42
Moved the SNR parameter to Table 5-24, CapTIvate Signal-to-Noise Ratio Characteristics ............................ 42
Corrected bitfield from IRDSEL to IRDSSEL in Section 6.10.8, Timers (Timer0_A3, Timer1_A3, Timer2_A2 and
Timer3_A2), in the description that starts "The interconnection of Timer0_A3 and ..." .................................... 56
Corrected the ADCINCHx column heading in Table 6-15, ADC Channel Connections ................................... 58
Corrected the ADCSHSx column heading in Table 6-16, ADC Trigger Signal Connections.............................. 58
Added P1SELC information in Table 6-32, Port P1, P2 Registers (Base Address: 0200h) .............................. 71
Added P2SELC information in Table 6-32, Port P1, P2 Registers (Base Address: 0200h) .............................. 71
Added P3SELC information in Table 6-33, Port P3 Registers (Base Address: 0220h) ................................... 71
Updated Section 7.2.2, CapTIvate Peripheral .................................................................................. 81
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6
修订历史记录
版权 © 2015–2019, Texas Instruments Incorporated
MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532
www.ti.com.cn
ZHCSET6E –NOVEMBER 2015–REVISED DECEMBER 2019
从修订版本 B 更改为修订版本 C
Changes from June 9, 2017 to August 28, 2018
Page
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删除了节 1.1，特性 中“接近感应”项的“30cm” .................................................................................... 1
Updated Section 3.1, Related Products ........................................................................................... 8
Corrected package type in VQFN row (changed from QFN to VQFN) in Table 4-2, Signal Descriptions .............. 18
Changed HBM limit to ±1000 V and CDM limit to ±250 V in Section 5.2, ESD Ratings .................................. 20
Added note to VSVSH- and VSVSH+ parameters in Table 5-2, PMM, SVS and BOR.......................................... 26
Added the tTA,cap parameter in Table 5-13, Timer_A............................................................................ 34
Moved CREG and CELECTRODE from Section 5.3, Recommended Operating Conditions to Table 5-23, CapTIvate
Electrical Characteristics ........................................................................................................... 42
Added the SNR parameter in Table 5-23, CapTIvate Electrical Characteristics ........................................... 42
Moved "FRAM access time error" to "System Reset" row and added ACCTEIFG to interrupt flag column in
•
•
Table 6-2, Interrupt Sources, Flags, and Vectors............................................................................... 47
Corrected the offset for P2SEL1 in Table 6-32, Port P1, P2 Registers (Base Address: 0200h) ......................... 71
更新了节 8.2器件命名规则 中的文本和图 ........................................................................................ 84
•
•
从修订版本 A 更改为修订版本 B
Changes from December 10, 2015 to June 8, 2017
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
更改了 “特性” 列表的组织结构 ...................................................................................................... 1
在节 1.1，特性 中的“封装选项”列表中添加了 DSBGA (YQW) 封装............................................................ 2
更新了节 1.2，应用 中的列表 ....................................................................................................... 2
更新节 1.3，说明...................................................................................................................... 2
在器件信息 表（位于节 1.3“说明”中）中添加了 DSBGA (YQW) 封装选项.................................................... 3
Added MSP430FR2633IYQW and MSP430FR2632IYQW to Table 3-1, Device Comparison............................. 8
Added Section 3.1, Related Products.............................................................................................. 8
Added DSBGA (YQW) pinout ..................................................................................................... 12
Added DSBGA (YQW) package to Table 4-1, Pin Attributes.................................................................. 13
Added DSBGA (YQW) package to Table 4-2, Signal Descriptions........................................................... 16
Added row for VQFN thermal pad in Table 4-2, Signal Descriptions......................................................... 18
Removed FRAM reflow note....................................................................................................... 20
Updated the notes on ILPM3, CapTIvate, 16 buttons and ILPM3, CapTIvate, 64 buttons in Section 5.7, Low-Power Mode (LPM3
and LPM4) Supply Currents (Into VCC) Excluding External Current ......................................................... 22
Added DSBGA (YQW) package and changed notes for Section 5.10, Thermal Resistance Characteristics........... 25
Added the tTA,cap parameter in Table 5-13, Timer_A............................................................................ 34
Removed ADCDIV from the formula for the TYP value in the second row of the tCONVERT parameter in Table 5-
21, ADC, 10-Bit Timing Parameters (removed because ADCCLK is after division)........................................ 40
Moved CREG and CELECTRODE from Section 5.3, Recommended Operating Conditions to Table 5-23, CapTIvate
Electrical Characteristics ........................................................................................................... 42
Add description of blank device detection ....................................................................................... 48
Changed the paragraph that starts "Quickly switching digital signals and ..." in Section 7.2.1.2, Design
•
•
•
•
•
•
Requirements ........................................................................................................................ 80
更新了图 8-1，器件命名规则 ...................................................................................................... 84
将先前的开发工具支持 部分替换为节 8.3“工具和软件” ......................................................................... 85
更新了节 8.4“文档支持”的格式和内容............................................................................................. 87
•
•
•
从初始发行版更改为修订版本 A
Changes from November 6, 2015 to December 9, 2015
Page
•
•
•
•
将文档状态从“产品预览”更改为“生产数据”......................................................................................... 1
更改了开头为“提供可靠的触控解决方案...”的列表项.............................................................................. 1
向开头为“宽电源电压范围...”的列表项添加了说明 ................................................................................ 1
In the note that starts "Low-power mode 3, VLO, excludes SVS test conditions...", changed "fXT1 = 0 Hz" to
"fXT1 = 32768 Hz" .................................................................................................................... 22
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修订历史记录
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•
•
•
Added note that starts "The VLO clock frequency is reduced by 15%...".................................................... 31
Added the tTA,cap parameter in Table 5-13, Timer_A............................................................................ 34
Moved CREG and CELECTRODE from Section 5.3, Recommended Operating Conditions to Table 5-23, CapTIvate
Electrical Characteristics ........................................................................................................... 42
Added note to "Clock" in Table 6-1, Operating Modes......................................................................... 46
Added note that starts "XT1CLK and VLOCLK can be active during LPM4..." ............................................. 46
Corrected description in Section 6.10.10, Backup Memory (BKMEM) ....................................................... 57
•
•
•
8
修订历史记录
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ZHCSET6E –NOVEMBER 2015–REVISED DECEMBER 2019
3 Device Comparison
Table 3-1 summarizes the features of the available family members.
Table 3-1. Device Comparison(1)(2)
PROGRAM FRAM
+ INFORMATION
FRAM (BYTES)
eUSCI_A
UART
SRAM
(BYTES)
10-BIT ADC
CHANNELS
CapTIvate™
CHANNELS
PACKAGE
TYPE
DEVICE
TA0 TO TA3
eUSCI_B
GPIOs
SPI
2, 3 × CCR(3)
2, 2 × CCR
32 RHB
(VQFN)
MSP430FR2633IRHB
MSP430FR2533IRHB
MSP430FR2633IDA
MSP430FR2533IDA
MSP430FR2632IRGE
MSP430FR2532IRGE
MSP430FR2633IYQW
MSP430FR2632IYQW
15360 + 512
15360 + 512
15360 + 512
15360 + 512
8192 + 512
8192 + 512
15360 + 512
8192 + 512
4096
2048
4096
2048
2048
1024
4096
2048
up to 2
up to 2
up to 2
up to 2
up to 2
up to 2
up to 2
up to 2
up to 2
1
1
1
1
1
1
1
1
8
8
8
8
8
8
8
8
16(4)
16(4)
16(4)
16(4)
8(5)
19
19
19
19
15
15
17
17
2, 3 × CCR(3)
2, 2 × CCR
32 RHB
(VQFN)
up to 2
2, 3 × CCR(3)
2, 2 × CCR
32 DA
(TSSOP)
up to 2
2, 3 × CCR(3)
2, 2 × CCR
32 DA
(TSSOP)
up to 2
2, 3 × CCR(3)
2, 2 × CCR
24 RGE
(VQFN)
1
1
1
1
2, 3 × CCR(3)
2, 2 × CCR
24 RGE
(VQFN)
8(5)
2, 3 × CCR(3)
2, 2 × CCR
24 YQW
(DSBGA)
8(6)
2, 3 × CCR(3)
2, 2 × CCR
24 YQW
(DSBGA)
8(6)
(1) For the most current package and ordering information, see the Package Option Addendum in 节 9, or see the TI website at www.ti.com
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging
(3) A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM
outputs.
(4) Eight dedicated CapTIvate channels are included.
(5) Four dedicated CapTIvate channels are included.
(6) Two dedicated CapTIvate channels are included.
3.1 Related Products
For information about other devices in this family of products or related products, see the following links.
TI 16-bit and 32-bit microcontrollers
High-performance, low-power solutions to enable the autonomous future
Products for MSP430 ultra-low-power sensing & measurement MCUs
One platform. One ecosystem. Endless possibilities.
Companion products for MSP430FR2633
Review products that are frequently purchased or used with this product.
Reference designs for MSP430FR2633
Find reference designs leveraging the best in TI technology – from analog and power management to
embedded processors
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Device Comparison
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4 Terminal Configuration and Functions
4.1 Pin Diagrams
Figure 4-1 shows the pinout for the 32-pin RHB package.
26 25
32 31 30 29 28 27
24
23
22
21
20
19
18
17
RST/NMI/SBWTDIO
TEST/SBWTCK
1
2
3
4
5
6
7
8
CAP2.3
CAP2.2
CAP2.1
CAP2.0
VREG
P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+
P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5
P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6
P1.7/UCA0STE/SMCLK/TDO/A7
MSP430FR2633IRHB
MSP430FR2533IRHB
P2.6/UCA1TXD/UCA1SIMO/CAP1.3
P2.5/UCA1RXD/UCA1SOMI/CAP1.2
P2.4/UCA1CLK/CAP1.1
P1.0/UCB0STE/TA0CLK/A0/Veref+
P1.1/UCB0CLK/TA0.1/A1
9
10 11 12 13 14 15 16
Figure 4-1. 32-Pin RHB Package (Top View)
10
Terminal Configuration and Functions
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ZHCSET6E –NOVEMBER 2015–REVISED DECEMBER 2019
Figure 4-2 shows the pinout for the 32-pin DA package.
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P2.0/XOUT
P2.1/XIN
CAP3.3
2
3
P3.2/CAP3.2
DVSS
CAP3.1
4
DVCC
P2.7/CAP3.0
5
RST/NMI/SBWTDIO
CAP2.3
6
TEST/SBWTCK
CAP2.2
7
P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+
P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5
P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6
P1.7/UCA0STE/SMCLK/TDO/A7
P1.0/UCB0STE/TA0CLK/A0/Veref+
P1.1/UCB0CLK/TA0.1/A1
CAP2.1
8
CAP2.0
MSP430FR2633IDA
MSP430FR2533IDA
9
VREG
10
11
12
13
14
15
16
P2.6/UCA1TXD/UCA1SIMO/CAP1.3
P2.5/UCA1RXD/UCA1SOMI/CAP1.2
P2.4/UCA1CLK/CAP1.1
P3.1/UCA1STE/CAP1.0
CAP0.3
P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref-
P1.3/UCB0SOMI/UCB0SCL/MCLK/A3
P2.2/SYNC/ACLK
P2.3/CAP0.2
CAP0.1
P3.0/CAP0.0
Figure 4-2. 32-Pin DA Package (Top View)
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Terminal Configuration and Functions
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Figure 4-3 shows the pinout for the 24-pin RGE package.
24 23 22 21 20 19
RST/NMI/SBWTDIO
TEST/SBWTCK
CAP2.1
1
2
3
4
5
6
18
17
16
15
14
13
CAP2.0
P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+
P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5
P1.6/UCA0CLK/TA1CLK/TDI/TCLKA6
P1.7/UCA0STE/SMCLK/TDO/A7
VREG
MSP430FR2632IRGE
MSP430FR2532IRGE
P2.6/UCA1TXD/UCA1SIMO/CAP1.3
P2.5/UCA1RXD/UCA1SOMI/CAP1.2
CAP0.3
7
8
9
10 11 12
Figure 4-3. 24-Pin RGE Package (Top View)
12
Terminal Configuration and Functions
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ZHCSET6E –NOVEMBER 2015–REVISED DECEMBER 2019
Figure 4-4 shows the top view of the YQW package, and Figure 4-5 shows the bottom (ball-side) view.
Top View
PIN NO.
A1
SIGNAL NAME
P1.1/UCB0CLK/TA0.1/A1
PIN NO.
C4
SIGNAL NAME
E5
D5
C5
B5
A5
E4
D4
C4
B4
A4
E3
D3
C3
B3
A3
E
E2
D2
C2
B2
A2
E1
D1
CAP2.0
VREG
P1.3/UCB0SOMI/UCB0SCL/MCLK/A3
P2.2/SYNC/ACLK
A2
C5
A3
P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+
D1
P3.0/CAP0.0
TEST/SBWTCK
DVSS
A4
D2
P2.3/CAP0.2
A5
D3
P3.2/CAP3.2
CAP2.2
P1.0/UCB0STE/TA0CLK/A0/Veref+
P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref-
P1.7/UCA0STE/SMCLK/TDO/A7
P2.5/UCA1RXD/CAP1.2
B1
D4
D
B2
D5
B3
E1
RST/NMI/SBWTDIO
DVCC
B1
A1
B4
E2
B5
P2.6/UCA1TXD/CAP1.3
E3
P2.1/XIN
C2
P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5
P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6
E4
P2.0/XOUT
P2.7/CAP3.0
E5
C3
Figure 4-4. 24-Pin YQW Package (Top View)
Ball-SIde View
PIN NO.
A1
SIGNAL NAME
P1.1/UCB0CLK/TA0.1/A1
PIN NO.
C4
SIGNAL NAME
E1
D1
E2
D2
C2
B2
A2
E3
D3
C3
B3
A3
E4
E5
CAP2.0
P1.3/UCB0SOMI/UCB0SCL/MCLK/A3
P2.2/SYNC/ACLK
A2
C5
VREG
A3
P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+
D1
D4
D5
C5
B5
A5
P3.0/CAP0.0
TEST/SBWTCK
DVSS
A4
D2
P2.3/CAP0.2
A5
D3
P3.2/CAP3.2
CAP2.2
C4
B4
A4
B1
P1.0/UCB0STE/TA0CLK/A0/Veref+
P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref-
P1.7/UCA0STE/SMCLK/TDO/A7
P2.5/UCA1RXD/CAP1.2
D4
D
B2
D5
B3
E1
RST/NMI/SBWTDIO
DVCC
B1
A1
B4
E2
B5
P2.6/UCA1TXD/CAP1.3
E3
P2.1/XIN
C2
P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5
P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6
E4
P2.0/XOUT
P2.7/CAP3.0
E5
C3
E
Figure 4-5. 24-Pin YQW Package (Bottom View)
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Terminal Configuration and Functions
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4.2 Pin Attributes
Table 4-1 lists the attributes of all pins.
Table 4-1. Pin Attributes
SIGNAL NAME(1)
SIGNAL
TYPE(3)
POWER
RESET STATE
AFTER BOR(6)
PIN NUMBER
BUFFER TYPE(4)
SOURCE(5)
(2)
RHB
DA
RGE
YQW
RST (RD)
NMI
I
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
OFF
1
5
1
E1
–
SBWTDIO
TEST (RD)
SBWTCK
P1.4 (RD)
UCA0TXD
UCA0SIMO
TA1.2
I/O
I
–
OFF
2
3
6
7
2
3
D2
D1
I
–
I/O
O
I/O
I/O
I
OFF
–
–
–
TCK
–
A4
I
–
VREF+
P1.5 (RD)
UCA0RXD
UCA0SOMI
TA1.1
O
I/O
I
Power
–
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
I/O
I/O
I
–
4
5
8
9
4
5
C2
C3
–
TMS
–
A5
I
–
P1.6 (RD)
UCA0CLK
TA1CLK
TDI
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
–
I
–
TCLK
I
–
A6
I
–
P1.7 (RD)
UCA0STE
SMCLK
TDO
I/O
I/O
O
O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
6
7
10
11
6
7
B3
B1
–
–
A7
–
P1.0 (RD)
UCB0STE
TA0CLK
A0
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
–
I
–
Veref+
I
Power
–
(1) Signals names with (RD) denote the reset default pin name.
(2) To determine the pin mux encodings for each pin, see Section 6.11, Input/Output Diagrams.
(3) Signal Types: I = Input, O = Output, I/O = Input or Output
(4) Buffer Types: LVCMOS, Analog, or Power (see Table 4-3)
(5) The power source shown in this table is the I/O power source, which may differ from the module power source.
(6) Reset States:
OFF = High-impedance with Schmitt trigger and pullup or pulldown (if available) disabled
N/A = Not applicable
14
Terminal Configuration and Functions
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ZHCSET6E –NOVEMBER 2015–REVISED DECEMBER 2019
Table 4-1. Pin Attributes (continued)
SIGNAL NAME(1)
SIGNAL
TYPE(3)
POWER
RESET STATE
AFTER BOR(6)
PIN NUMBER
BUFFER TYPE(4)
SOURCE(5)
(2)
RHB
DA
RGE
YQW
P1.1 (RD)
UCB0CLK
TA0.1
I/O
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
VREG
OFF
–
8
12
8
A1
–
A1
–
P1.2 (RD)
UCB0SIMO
UCB0SDA
TA0.2
I/O
I/O
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
–
9
13
9
B2
–
A2
–
Veref-
I
Power
–
P1.3 (RD)
UCB0SOMI
UCB0SCL
MCLK
I/O
I/O
I/O
O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
10
11
14
15
10
11
A2
A3
–
–
A3
I
–
P2.2 (RD)
SYNC
I/O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
ACLK
O
–
P3.0 (RD)
CAP0.0
CAP0.1
P2.3 (RD)
CAP0.2
CAP0.3
P3.1 (RD)
UCA1STE
CAP1.0
P2.4 (RD)
UCA1CLK
CAP1.1
P2.5 (RD)
UCA1RXD
UCA1SOMI
CAP1.2
P2.6 (RD)
UCA1TXD
UCA1SIMO
CAP1.3
VREG
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
OFF
–
12
13
14
15
16
17
18
19
–
–
A4
–
Analog
VREG
OFF
OFF
–
LVCMOS
Analog
DVCC
VREG
12
13
A5
–
Analog
VREG
OFF
OFF
–
LVCMOS
LVCMOS
Analog
DVCC
DVCC
VREG
16
17
20
21
–
–
–
–
–
LVCMOS
LVCMOS
Analog
DVCC
DVCC
VREG
OFF
–
–
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
VREG
OFF
–
18
19
22
23
14
15
B4
B5
I/O
I/O
I/O
O
–
–
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
VREG
OFF
–
I/O
I/O
P
–
–
20
21
22
23
24
24
25
26
27
28
16
17
18
–
C5
C4
–
Power
VREG
N/A
OFF
OFF
OFF
OFF
OFF
–
CAP2.0
CAP2.1
CAP2.2
CAP2.3
P2.7 (RD)
CAP3.0
CAP3.1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Analog
VREG
Analog
VREG
D5
–
Analog
VREG
–
Analog
VREG
LVCMOS
Analog
DVCC
VREG
25
26
29
30
19
20
E5
–
Analog
VREG
OFF
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Table 4-1. Pin Attributes (continued)
SIGNAL NAME(1)
SIGNAL
TYPE(3)
POWER
RESET STATE
AFTER BOR(6)
PIN NUMBER
BUFFER TYPE(4)
SOURCE(5)
(2)
RHB
27
DA
31
32
1
RGE
YQW
D4
–
P3.2 (RD)
CAP3.2
CAP3.3
P2.0 (RD)
XOUT
I/O
I/O
I/O
I/O
O
LVCMOS
Analog
DVCC
VREG
OFF
–
–
28
–
Analog
VREG
OFF
OFF
–
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Power
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
29
21
E4
P2.1 (RD)
XIN
I/O
I
OFF
–
30
2
22
E3
31
32
3
4
23
24
D3
E2
DVSS
P
N/A
N/A
DVCC
P
Power
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4.3 Signal Descriptions
Table 4-2 describes the signals for all device variants and package options.
Table 4-2. Signal Descriptions
PIN NUMBER
PIN
FUNCTION
SIGNAL NAME
DESCRIPTION
TYPE(1)
RHB DA RGE YQW
A0
A1
A2
A3
A4
A5
A6
A7
7
11
12
13
14
7
7
8
B1
A1
B2
A2
D1
C2
C3
B3
B1
B2
A4
–
I
Analog input A0
Analog input A1
Analog input A2
Analog input A3
Analog input A4
Analog input A5
Analog input A6
Analog input A7
ADC positive reference
8
I
9
9
I
10
3
10
3
I
I
ADC
4
8
4
I
5
9
5
I
6
10
11
13
16
17
18
19
20
21
22
23
25
26
27
28
29
30
31
32
6
I
Veref+
7
7
I
Veref-
9
9
I
ADC negative reference
CapTIvate channel
CapTIvate channel
CapTIvate channel
CapTIvate channel
CapTIvate channel
CapTIvate channel
CapTIvate channel
CapTIvate channel
CapTIvate channel
CapTIvate channel
CapTIvate channel
CapTIvate channel
CapTIvate channel
CapTIvate channel
CapTIvate channel
CapTIvate channel
CAP0.0
CAP0.1
CAP0.2
CAP0.3
CAP1.0
CAP1.1
CAP1.2
CAP1.3
CAP2.0
CAP2.1
CAP2.2
CAP2.3
CAP3.0
CAP3.1
CAP3.2
CAP3.3
12
13
14
15
16
17
18
19
21
22
23
24
25
26
27
28
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
12
13
–
A5
–
–
–
–
14
15
17
18
–
B4
B5
C4
–
CapTIvate
D5
–
–
19
20
–
E5
–
D4
–
–
CapTIvate synchronous trigger input for processing and
conversion
SYNC
11
15
11
A3
I
ACLK
MCLK
SMCLK
XIN
11
10
6
15
14
10
2
11
10
6
A3
A2
B3
E3
E4
D2
E1
D1
C3
C3
B3
D2
C2
O
O
O
I
ACLK output
MCLK output
Clock
SMCLK output
30
29
2
22
21
2
Input terminal for crystal oscillator
Output terminal for crystal oscillator
Spy-Bi-Wire input clock
Spy-Bi-Wire data input/output
Test clock
XOUT
SBWTCK
SBWTDIO
TCK
1
O
I
6
1
5
1
I/O
I
3
7
3
TCLK
TDI
5
9
5
I
Test clock input
Debug
5
9
5
I
Test data input
TDO
6
10
6
6
O
I
Test data output
TEST
TMS
2
2
Test Mode pin – selected digital I/O on JTAG pins
Test mode select
4
8
4
I
(1) Pin Types: I = Input, O = Output, I/O = Input or Output, P = Power
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Table 4-2. Signal Descriptions (continued)
PIN NUMBER
PIN
FUNCTION
SIGNAL NAME
P1.0
DESCRIPTION
TYPE(1)
RHB DA RGE YQW
7
11
12
13
14
7
7
8
B1
A1
B2
A2
D1
C2
C3
B3
E4
E3
A3
A5
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O(2)
General-purpose I/O(2)
General-purpose I/O(2)
General-purpose I/O(2)
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
eUSCI_B0 I2C clock
eUSCI_B0 I2C data
Power supply
P1.1
8
P1.2
9
9
P1.3
10
3
10
3
P1.4
P1.5
4
8
4
P1.6
5
9
5
P1.7
6
10
1
6
P2.0
29
30
11
14
17
18
19
25
12
16
27
10
9
21
22
11
12
–
GPIO
P2.1
2
P2.2
15
18
21
22
23
29
16
20
31
14
13
4
P2.3
P2.4
P2.5
14
15
19
–
B4
B5
E5
A4
–
P2.6
P2.7
P3.0
P3.1
–
P3.2
–
D4
A2
B2
E2
D3
UCB0SCL
UCB0SDA
DVCC
DVSS
10
9
I2C
32
31
24
23
3
P
Power ground
Power
Output of positive reference voltage with ground as
reference
VREF+
3
7
3
D1
P
VREG
20
5
24
9
16
5
C5
C3
D1
C2
B3
–
O
CapTIvate regulator external decoupling capacitor
eUSCI_A0 SPI clock input/output
eUSCI_A0 SPI slave in/master out
eUSCI_A0 SPI slave out/master in
eUSCI_A0 SPI slave transmit enable
eUSCI_A1 SPI clock input/output
eUSCI_A1 SPI slave in/master out
eUSCI_A1 SPI slave out/master in
eUSCI_A1 SPI slave transmit enable
eUSCI_B0 clock input/output
UCA0CLK
UCA0SIMO
UCA0SOMI
UCA0STE
UCA1CLK
UCA1SIMO
UCA1SOMI
UCA1STE
UCB0CLK
UCB0SIMO
UCB0SOMI
UCB0STE
NMI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
3
7
3
4
8
4
6
10
21
23
22
20
12
13
14
11
5
6
17
19
18
16
8
–
15
14
–
B5
B4
–
SPI
8
A1
B2
A2
B1
E1
E1
9
9
eUSCI_B0 SPI slave in/master out
eUSCI_B0 SPI slave out/master in
eUSCI_B0 slave transmit enable
Nonmaskable interrupt input
10
7
10
7
1
1
System
RST
1
5
1
I
Active-low reset input
(2) Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to
prevent collisions.
18
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FUNCTION
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Table 4-2. Signal Descriptions (continued)
PIN NUMBER
PIN
SIGNAL NAME
TA0.1
DESCRIPTION
TYPE(1)
RHB DA RGE YQW
Timer TA0 CCR1 capture: CCI1A input, compare: Out1
outputs
8
12
8
A1
I/O
Timer TA0 CCR2 capture: CCI2A input, compare: Out2
outputs
TA0.2
9
7
4
13
11
8
9
7
4
B2
B1
C2
I/O
I
TA0CLK
TA1.1
Timer clock input TACLK for TA0
Timer_A
Timer TA1 CCR1 capture: CCI1A input, compare: Out1
outputs
I/O
Timer TA1 CCR2 capture: CCI2A input, compare: Out2
outputs
TA1.2
3
7
3
D1
I/O
TA1CLK
5
4
9
8
5
4
C3
C2
D1
B4
B5
I
I
Timer clock input TACLK for TA1
eUSCI_A0 UART receive data
UCA0RXD
UCA0TXD
UCA1RXD
UCA1TXD
3
7
3
O
I
eUSCI_A0 UART transmit data
UART
18
19
22
23
14
15
eUSCI_A1 UART receive data
O
eUSCI_A1 UART transmit data
VQFN package exposed thermal pad. TI recommends
VQFN Pad
VQFN thermal pad
Pad N/A Pad N/A
connecting to VSS
.
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4.4 Pin Multiplexing
Pin multiplexing for these MCUs is controlled by both register settings and operating modes (for example,
if the MCU is in test mode). For details of the settings for each pin and schematics of the multiplexed
ports, see Section 6.11.
4.5 Buffer Types
Table 4-3 defines the pin buffer types that are listed in Table 4-1.
Table 4-3. Buffer Types
NOMINAL
OUTPUT
DRIVE
STRENGTH
(mA)
BUFFER TYPE
(STANDARD)
NOMINAL
VOLTAGE
PU OR PD
STRENGTH
(µA)
OTHER
CHARACTERISTICS
HYSTERESIS
PU OR PD
See
Section 5.11.4
See
Section 5.11.4
LVCMOS
Analog
3.0 V
3.0 V
Y(1)
N
Programmable
N/A
See analog modules in
Section 5 for details.
N/A
N/A
SVS enables hysteresis on
DVCC.
Power (DVCC)
Power (AVCC)
3.0 V
3.0 V
N
N
N/A
N/A
N/A
N/A
N/A
N/A
(1) Only for input pins.
4.6 Connection of Unused Pins
Table 4-4 lists the correct termination of unused pins.
Table 4-4. Connection of Unused Pins(1)
PIN
POTENTIAL
COMMENT
Switched to port function, output direction (PxDIR.n = 1)
47-kΩ pullup or internal pullup selected with 10-nF (or 1.1-nF) pulldown(2)
Px.0 to Px.7
RST/NMI
TEST
Open
DVCC
Open
This pin always has an internal pulldown enabled.
These pins have internal pullup and pulldown resistors, and high impedance is their
default setting.
CAP2.x, CAPx.1, CAPx.3
Open
(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection
guidelines.
(2) The pulldown capacitor should not exceed 1.1 nF when using MCUs with Spy-Bi-Wire interface in Spy-Bi-Wire mode with TI tools like
FET interfaces or GANG programmers.
20
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5 Specifications
5.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
MAX
4.1
UNIT
V
Voltage applied at DVCC pin to VSS
(2)
Voltage applied to any dedicated CapTIvate pin or pin in CapTIvate mode
VREG
V
VCC + 0.3
(4.1 V Max)
Voltage applied to any other pin(3)
–0.3
V
Diode current at any device pin
±2
85
mA
°C
Maximum junction temperature, TJ
(4)
Storage temperature, Tstg
–40
125
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) This applies to dedicated CapTIvate I/Os only or I/Os worked in CapTIvate mode.
(3) All voltages referenced to VSS
.
(4) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS‑001(1)
Charged-device model (CDM), per JEDEC specification JESD22‑C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3 Recommended Operating Conditions
MIN
NOM
MAX UNIT
VCC
VSS
TA
Supply voltage applied at DVCC pin(1)(2)(3)(4)
Supply voltage applied at DVSS pin
Operating free-air temperature
1.8
3.6
V
V
0
–40
–40
4.7
85
85
°C
°C
µF
TJ
Operating junction temperature
Recommended capacitor at DVCC(5)
CDVCC
10
No FRAM wait states
(NWAITSx = 0)
0
0
8
fSYSTEM
Processor frequency (maximum MCLK frequency)(6)
MHz
With FRAM wait states
(NWAITSx = 1)(7)
16(8)
fACLK
Maximum ACLK frequency
Maximum SMCLK frequency
40
16(8)
kHz
fSMCLK
MHz
(1) Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range. Following the
data sheet recommendation for capacitor CDVCC limits the slopes accordingly.
(2) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(3) TI recommends that power to the DVCC pin must not exceed the limits specified in Recommended Operating Conditions. Exceeding the
specified limits can cause malfunction of the device including erroneous writes to RAM and FRAM.
(4) The minimum supply voltage is defined by the SVS levels. See the SVS threshold parameters in Table 5-2.
(5) A capacitor tolerance of ±20% or better is required. A low-ESR ceramic capacitor of 100 nF (minimum) should be placed as close as
possible (within a few millimeters) to the respective pin pair.
(6) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(7) Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executed
without wait states.
(8) If clock sources such as HF crystals or the DCO with frequencies >16 MHz are used, the clock must be divided in the clock system to
comply with this operating condition.
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5.4 Active Mode Supply Current Into VCC Excluding External Current(1)
VCC = 3 V, TA = 25°C (unless otherwise noted)
FREQUENCY (fMCLK = fSMCLK
)
1 MHz
0 WAIT STATES
(NWAITSx = 0)
8 MHz
0 WAIT STATES
(NWAITSx = 0)
16 MHz
1 WAIT STATE
(NWAITSx = 1)
EXECUTION
MEMORY
TEST
CONDITION
PARAMETER
UNIT
TYP
504
516
203
MAX
TYP
2772
2491
625
MAX
TYP
3047
2871
1000
MAX
3480
3 V, 25°C
3 V, 85°C
3 V, 25°C
FRAM
0% cache hit ratio
IAM, FRAM(0%)
µA
FRAM
100% cache hit
ratio
1215
IAM, FRAM(100%)
µA
µA
3 V, 85°C
3 V, 25°C
212
229
639
818
1016
1377
(2)
IAM, RAM
RAM
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. Characterized with program executing typical data
processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency
Program and data entirely reside in FRAM. All execution is from FRAM.
(2) Program and data reside entirely in RAM. All execution is from RAM. No access to FRAM.
5.5 Active Mode Supply Current Per MHz
VCC = 3 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
UNIT
µA/MHz
Active mode current consumption per MHz,
execution from FRAM, no wait states
[IAM (75% cache hit rate) at 8 MHz –
IAM (75% cache hit rate) at 1 MHz)] / 7 MHz
dIAM,FRAM/df
126
5.6 Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
VCC = 3 V, TA = 25°C (unless otherwise noted)(1)(2)
FREQUENCY (fSMCLK
8 MHz
)
PARAMETER
VCC
1 MHz
TYP
16 MHz
TYP MAX
UNIT
MAX
TYP
328
342
MAX
2 V
3 V
156
166
420
433
ILPM0
µA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Current for watchdog timer clocked by SMCLK included.
fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK at specified frequency.
22
Specifications
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5.7 Low-Power Mode (LPM3 and LPM4) Supply Currents (Into VCC) Excluding External Current
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
–40°C
TYP MAX
25°C
TYP
85°C
TYP
PARAMETER
VCC
UNIT
µA
MAX
MAX
3 V
2 V
3 V
2 V
0.98
0.96
0.78
0.76
1.18
1.16
0.98
0.96
1.65
3.24
3.21
3.04
3.01
Low-power mode 3, 12.5-pF crystal, includes
SVS(2)(3)(4)
ILPM3,XT1
1.40
ILPM3,VLO
ILPM3, RTC
Low-power mode 3, VLO, excludes SVS(5)
µA
Low-power mode 3, RTC, excludes SVS(6)
(see Figure 5-1)
3 V
0.93
1.13
5
3.19
µA
µA
µA
µA
µA
µA
ILPM3, CapTIvate,
1 proximity, wake on touch
ILPM3, CapTIvate,
1 button, wake on touch
ILPM3, CapTIvate,
4 buttons, wake on touch
ILPM3, CapTIvate,
16 buttons
Low-power mode 3, CapTIvate, excludes
SVS(7)
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Low-power mode 3, CapTIvate, excludes
SVS(8)
3.4
Low-power mode 3, CapTIvate, excludes
SVS(9)
3.6
Low-power mode 3, CapTIvate, excludes
SVS(10)
27.2
109.2
ILPM3, CapTIvate,
64 buttons
Low-power mode 3, CapTIvate, excludes
SVS(11)
3 V
2 V
3 V
2 V
0.51
0.49
0.35
0.34
0.65
0.64
0.49
0.48
2.65
2.63
2.49
2.46
ILPM4, SVS
Low-power mode 4, includes SVS
Low-power mode 4, excludes SVS
µA
ILPM4
µA
µA
ILPM4, CapTIvate,
1 proximity, wake on touch
Low-power mode 4, CapTIvate, excludes
SVS(12)
3 V
4.4
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Not applicable for MCUs with HF crystal oscillator only.
(3) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5-pF load.
(4) Low-power mode 3, 12.5-pF crystal, includes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Low-power mode 3, VLO, excludes SVS test conditions:
Current for watchdog timer clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3)
fXT1 = 32768 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
(6) RTC periodically wakes up every second with external 32768-Hz input as source.
(7) CapTIvate technology works in LPM3 with one proximity sensor for wake on touch. CapTIvate BSWP demonstration board with 1.5-mm
overlay. Current for brownout included. SVS disabled (SVSHE = 0).
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 800
(8) CapTIvate technology works in LPM3 with one button, wake on touch. CapTIvate BSWP demonstration board with 1.5-mm overlay,
Current for brownout included. SVS disabled (SVSHE = 0).
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250
(9) CapTIvate technology works in LPM3 with four self-capacitance buttons, wake on touch. CapTIvate BSWP demonstration board with
1.5-mm overlay. Current for brownout included. SVS disabled (SVSHE = 0).
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250
(10) CapTIvate technology works in LPM3 with 16 self-capacitance buttons. The CPU enters active mode between time cycles to configure
the conversions and read the results. CapTIvate BSWP demonstration board with 1.5-mm overlay. Current for brownout included. SVS
disabled (SVSHE = 0).
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250
(11) CapTIvate technology works in LPM3 with 64 mutual-capacitance buttons. The CPU enters active mode between time cycles to
configure the conversions and read the results. TIDM-CAPTIVATE-64-BUTTON 64-Button Capacitive Touch Panel. Current for
brownout included. SVS disabled (SVSHE = 0).
fSCAN = 8 Hz, fCONVER = 4 MHz, COUNTS = 250
(12) CapTIvate technology works in LPM4 with one proximity sensor for wake on touch. CapTIvate BSWP demonstration board with 1.5-mm
overlay. Current for brownout included. SVS disabled (SVSHE = 0). VLO (10 kHz) sources to CapTIvate timer, no external crystal.
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 800
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Low-Power Mode (LPM3 and LPM4) Supply Currents (Into VCC) Excluding External
Current (continued)
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
–40°C
TYP MAX
25°C
TYP
85°C
PARAMETER
VCC
UNIT
MAX
MAX
TYP
ILPM4, CapTIvate,
1 button, wake on touch
Low-power mode 4, CapTIvate, excludes
SVS(13)
3 V
2.7
3.0
µA
µA
ILPM4, CapTIvate,
4 buttons, wake on touch
Low-power mode 4, CapTIvate, excludes
SVS(14)
3 V
(13) CapTIvate technology works in LPM4 with one button, wake on touch. CapTIvate BSWP demonstration board with 1.5-mm overlay,
Current for brownout included. SVS disabled (SVSHE = 0). VLO (10 kHz) sources to CapTIvate timer, no external crystal.
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250
(14) CapTIvate technology works in LPM4 with four self-capacitance buttons, wake on touch. CapTIvate BSWP demonstration board with
1.5-mm overlay. Current for brownout included. SVS disabled (SVSHE = 0). VLO (10 kHz) sources to CapTIvate timer, no external
crystal.
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250
5.8 Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
–40°C
TYP MAX
25°C
TYP
85°C
TYP
PARAMETER
VCC
UNIT
µA
MAX
MAX
3 V
2 V
3 V
2 V
3 V
2 V
0.65
0.63
0.73
0.71
0.24
0.23
0.95
0.99
0.87
0.30
0.28
1.42
Low-power mode 3.5, 12.5-pF crystal, includes
SVS(1)(2)(3) (see Figure 5-2)
ILPM3.5, XT1
ILPM4.5, SVS
ILPM4.5
Low-power mode 4.5, includes SVS(4) (see Figure 5-
3)
0.22
0.31
0.38
µA
0.21
0.012
0.002
0.016 0.055 0.061 0.120
0.007 0.044
Low-power mode 4.5, excludes SVS(5)
µA
(1) Not applicable for MCUs with HF crystal oscillator only.
(2) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5-pF load.
(3) Low-power mode 3.5, 12.5-pF crystal, includes SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = 0, fMCLK = fSMCLK = 0 MHz
(4) Low-power mode 4.5, includes SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
(5) Low-power mode 4.5, excludes SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
24
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5.9 Typical Characteristics - Low-Power Mode Supply Currents
10
9
8
7
6
5
4
3
2
1
0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature (°C)
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature (°C)
VCC = 3 V
RTC
SVS Disabled
VCC = 3 V
XT1
SVS Enabled
Figure 5-1. LPM3 Supply Current vs Temperature
Figure 5-2. LPM3.5 Supply Current vs Temperature
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature (°C)
VCC = 3 V
SVS Enabled
Figure 5-3. LPM4.5 Supply Current vs Temperature
Table 5-1. Typical Characteristics – Current Consumption Per Module
MODULE
TEST CONDITIONS
REFERENCE CLOCK
Module input clock
MIN
TYP
5
MAX
UNIT
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
nA
Timer_A
eUSCI_A
eUSCI_A
eUSCI_B
eUSCI_B
RTC
UART mode
Module input clock
Module input clock
Module input clock
Module input clock
32 kHz
7
SPI mode
5
SPI mode
5
I2C mode, 100 kbaud
5
85
8.5
CRC
From start to end of operation
MCLK
µA/MHz
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5.10 Thermal Resistance Characteristics
THERMAL METRIC(1)
VQFN 32 pin (RHB)
TSSOP 32 pin (DA)
VALUE(2)
33.5
69.4
32.6
63.7
25.7
18.1
32.4
0.3
UNIT
RθJA
Junction-to-ambient thermal resistance, still air
ºC/W
VQFN 24 pin (RGE)
DSBGA 24 pin (YQW)
VQFN 32 pin (RHB)
TSSOP 32 pin (DA)
VQFN 24 pin (RGE)
DSBGA 24 pin (YQW)
VQFN 32 pin (RHB)
TSSOP 32 pin (DA)
VQFN 24 pin (RGE)
DSBGA 24 pin (YQW)
RθJC(top) Junction-to-case (top) thermal resistance
ºC/W
ºC/W
7.6
33.1
10.1
9.2
RθJB
Junction-to-board thermal resistance
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (RθJC) value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC
standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
26
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ZHCSET6E –NOVEMBER 2015–REVISED DECEMBER 2019
5.11 Timing and Switching Characteristics
5.11.1 Power Supply Sequencing
Table 5-2 lists the characteristics of the SVS and BOR.
Table 5-2. PMM, SVS and BOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-4)
PARAMETER
TEST CONDITIONS
MIN
0.1
10
TYP
MAX UNIT
VBOR, safe
tBOR, safe
ISVSH,AM
Safe BOR power-down level(1)
Safe BOR reset delay(2)
V
ms
SVSH current consumption, active mode
SVSH current consumption, low-power modes
SVSH power-down level(3)
VCC = 3.6 V
VCC = 3.6 V
1.5
µA
nA
V
ISVSH,LPM
VSVSH-
240
1.80
1.89
80
1.71
1.74
1.86
1.99
VSVSH+
SVSH power-up level(3)
V
VSVSH_hys
tPD,SVSH, AM
tPD,SVSH, LPM
VREF, 1.2V
SVSH hysteresis
mV
µs
µs
V
SVSH propagation delay, active mode
SVSH propagation delay, low-power modes
1.2-V REF voltage(4)
10
100
1.158
1.20
1.242
(1) A safe BOR can be correctly generated only if DVCC drops below this voltage before it rises.
(2) When an BOR occurs, a safe BOR can be correctly generated only if DVCC is kept low longer than this period before it reaches VSVSH+
(3) For additional information, see the Dynamic Voltage Scaling Power Solution for MSP430 Devices With Single-Channel LDO Reference
Design.
.
(4) This is a characterized result with external 1-mA load to ground from –40°C to 85°C.
V
Power Cycle Reset
VSVS+
SVS Reset
BOR Reset
VSVS–
VBOR
tBOR
t
Figure 5-4. Power Cycle, SVS, and BOR Reset Conditions
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5.11.2 Reset Timing
Table 5-3 lists the wake-up times.
Table 5-3. Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
3 V
3 V
MIN
TYP
MAX UNIT
Additional wake-up time to activate the FRAM in
AM if previously disabled by the FRAM controller or
from a LPM if immediate activation is selected for
wakeup(1)
tWAKE-UP FRAM
10
µs
200 +
ns
(1)
tWAKE-UP LPM0
Wake-up time from LPM0 to active mode
2.5 / fDCO
(2)
tWAKE-UP LPM3
tWAKE-UP LPM4
tWAKE-UP LPM3.5
Wake-up time from LPM3 to active mode
3 V
3 V
3 V
10
10
µs
µs
µs
µs
ms
Wake-up time from LPM4 to active mode
(2)
Wake-up time from LPM3.5 to active mode
350
350
1
SVSHE = 1
SVSHE = 0
(2)
tWAKE-UP LPM4.5
Wake-up time from LPM4.5 to active mode
3 V
Wake-up time from RST or BOR event to active
mode
tWAKE-UP-RESET
tRESET
3 V
3 V
1
ms
µs
(2)
Pulse duration required at RST/NMI pin to accept a
reset
2
(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first
externally observable MCLK clock edge.
(2) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
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5.11.3 Clock Specifications
Table 5-4 lists the characteristics of XT1.
Table 5-4. XT1 Crystal Oscillator (Low Frequency)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
XT1 oscillator crystal, low
frequency
fXT1, LF
LFXTBYPASS = 0
32768
Hz
Measured at MCLK,
fLFXT = 32768 Hz
DCXT1, LF
fXT1,SW
XT1 oscillator LF duty cycle
30%
70%
kHz
60%
kΩ
XT1 oscillator logic-level square-
wave input frequency
(2)(3)
LFXTBYPASS = 1
LFXTBYPASS = 1
32.768
LFXT oscillator logic-level square-
wave input duty cycle
DCXT1, SW
OALFXT
CL,eff
40%
Oscillation allowance for
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32768 Hz, CL,eff = 12.5 pF
200
1
(4)
LF crystals
Integrated effective load
capacitance(5)
(6)
See
pF
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF
(7)
tSTART,LFXT Start-up time
fFault,LFXT
1000
ms
(8)
Oscillator fault frequency
XTS = 0(9)
0
3500
Hz
(1) To improve EMI on the LFXT oscillator, observe the following guidelines:
•
•
•
•
•
•
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW
.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
•
•
•
•
For LFXTDRIVE = {0}, CL,eff = 3.7 pF
For LFXTDRIVE = {1}, 6 pF ≤ CL,eff ≤ 9 pF
For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 10 pF
For LFXTDRIVE = {3}, 6 pF ≤ CL,eff ≤ 12 pF
(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
(6) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds
additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance
of the selected crystal is met.
(7) Includes start-up counter of 1024 clock cycles.
(8) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications might set the
flag. A static condition or stuck at fault condition sets the flag.
(9) Measured with logic-level input frequency but also applies to operation with crystals.
Table 5-5 lists the characteristics of the FLL.
Table 5-5. DCO FLL, Frequency
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
3 V
3 V
MIN
–1.0%
–2.0%
TYP
MAX UNIT
1.0%
FLL lock frequency, 16 MHz, 25°C
FLL lock frequency, 16 MHz, –40°C to 85°C
Measured at MCLK, Internal
trimmed REFO as reference
2.0%
fDCO, FLL
Measured at MCLK, XT1
crystal as reference
FLL lock frequency, 16 MHz, –40°C to 85°C
3 V
–0.5%
0.5%
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Table 5-5. DCO FLL, Frequency (continued)
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
3 V
3 V
3 V
3 V
3 V
MIN
TYP
50%
MAX UNIT
fDUTY
Duty cycle
40%
60%
Jittercc
Jitterlong
tFLL, lock
tstart-up
Cycle-to-cycle jitter, 16 MHz
Long term jitter, 16 MHz
FLL lock time
0.25%
0.022%
280
Measured at MCLK, XT1
crystal as reference
ms
µs
DCO start-up time, 2 MHz
Measured at MCLK
16
Table 5-6 lists the characteristics of the DCO.
Table 5-6. DCO Frequency
over recommended operating free-air temperature (unless otherwise noted) (also see Figure 5-5)
PARAMETER
TEST CONDITIONS
VCC
TYP
UNIT
DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
7.46
12.26
17.93
29.1
5.75
9.5
DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
fDCO, 16MHz DCO frequency, 16 MHz
3 V
MHz
DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
fDCO, 12MHz DCO frequency, 12 MHz
3 V
3 V
3 V
3 V
MHz
MHz
MHz
MHz
DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
13.85
22.5
3.91
6.49
9.5
DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
fDCO, 8MHz
fDCO, 4MHz
fDCO, 2MHz
DCO frequency, 8 MHz
DCO frequency, 4 MHz
DCO frequency, 2 MHz
DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
15.6
2.026
3.407
4.95
8.26
DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
1.0225
1.729
2.525
4.25
DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
30
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Table 5-6. DCO Frequency (continued)
over recommended operating free-air temperature (unless otherwise noted) (also see Figure 5-5)
PARAMETER
TEST CONDITIONS
VCC
TYP
UNIT
DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
0.5319
DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
0.9029
1.307
2.21
fDCO, 1MHz
DCO frequency, 1 MHz
3 V
MHz
DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
30
25
20
15
10
5
DCOFTRIM = 7
DCOFTRIM = 7
DCOFTRIM = 7
DCOFTRIM = 7
DCOFTRIM = 7
DCOFTRIM = 0
DCOFTRIM = 0
DCOFTRIM = 7
DCOFTRIM = 0
DCOFTRIM = 0
DCOFTRIM = 0
0
DCOFTRIM = 0
DCO
0
511
0
511
0
511
0
511
0
511
0
511
DCORSEL
0
1
2
3
4
5
VCC = 3 V
Figure 5-5. Typical DCO Frequency
Table 5-7 lists the characteristics of the REFO.
TA = –40°C to 85°C
Table 5-7. REFO
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
VCC
3 V
3 V
MIN
TYP
15
MAX UNIT
IREFO
REFO oscillator current consumption
REFO calibrated frequency
µA
Hz
Measured at MCLK
–40°C to 85°C
Measured at MCLK(1)
32768
fREFO
REFO absolute calibrated tolerance
REFO frequency temperature drift
1.8 V to 3.6 V
3 V
–3.5%
+3.5%
%/°C
dfREFO/dT
0.01
1
dfREFO
/
REFO frequency supply voltage drift
Measured at MCLK at 25°C(2)
1.8 V to 3.6 V
1.8 V to 3.6 V
%/V
dVCC
fDC
REFO duty cycle
Measured at MCLK
40%
50%
50
60%
µs
tSTART
REFO start-up time
40% to 60% duty cycle
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
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Table 5-8 lists the characteristics of the VLO.
NOTE
The VLO clock frequency is reduced by 15% (typical) when the device switches from active
mode to LPM3 or LPM4, because the reference changes. This lower frequency is not a
violation of the VLO specifications (see Table 5-8).
Table 5-8. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLO frequency
VLO frequency temperature drift
TEST CONDITIONS
VCC
3 V
TYP
10
UNIT
kHz
fVLO
Measured at MCLK
dfVLO/dT
Measured at MCLK(1)
Measured at MCLK(2)
Measured at MCLK
3 V
0.5
4
%/°C
%/V
dfVLO/dVCC VLO frequency supply voltage drift
fVLO,DC Duty cycle
2 V to 3.6 V
3 V
50%
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Table 5-9 lists the characteristics of the MODOSC.
Table 5-9. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MODOSC frequency
MODOSC frequency temperature drift
VCC
3 V
MIN
TYP
4.8
MAX UNIT
fMODOSC
3.8
5.8
MHz
%/℃
%/V
fMODOSC/dT
3 V
0.102
1.02
50%
fMODOSC/dVCC MODOSC frequency supply voltage drift
fMODOSC,DC Duty cycle
1.8 V to 3.6 V
3 V
40%
60%
32
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5.11.4 Digital I/Os
Table 5-10 lists the characteristics of the digital inputs.
Table 5-10. Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2 V
3 V
2 V
3 V
2 V
3 V
MIN
0.90
1.35
0.50
0.75
0.3
TYP
MAX UNIT
1.50
V
VIT+
VIT–
Vhys
Positive-going input threshold voltage
2.25
1.10
V
Negative-going input threshold voltage
1.65
0.8
V
Input voltage hysteresis (VIT+ – VIT–
Pullup or pulldown resistor
)
0.4
1.2
For pullup: VIN = VSS
For pulldown: VIN = VCC
RPull
20
35
3
50
20
kΩ
pF
pF
nA
CI,dig
Input capacitance, digital only port pins
VIN = VSS or VCC
Input capacitance, port pins with shared analog
functions
CI,ana
Ilkg(Px.y)
VIN = VSS or VCC
5
(1) (2)
High-impedance leakage current
See
2 V, 3 V
2 V, 3 V
–20
50
Ports with interrupt capability
(see block diagram and
terminal function descriptions)
External interrupt timing (external trigger pulse
duration to set interrupt flag)(3)
t(int)
ns
(1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
(3) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int)
.
Table 5-11 lists the characteristics of the digital outputs.
Table 5-11. Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (also see Figure 5-
6, Figure 5-7, Figure 5-8, and Figure 5-9)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA(1)
I(OHmax) = –5 mA(1)
I(OLmax) = 3 mA(1)
VCC
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
MIN
1.4
2.4
0.0
0.0
16
TYP
MAX UNIT
2.0
V
VOH
High-level output voltage
3.0
0.60
V
VOL
Low-level output voltage
I(OHmax) = 5 mA(1)
0.60
fPort_CLK
trise,dig
tfall,dig
Clock output frequency
CL = 20 pF(2)
CL = 20 pF
CL = 20 pF
MHz
ns
16
10
7
Port output rise time, digital only port pins
Port output fall time, digital only port pins
10
5
ns
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
(2) The port can output frequencies at least up to the specified limit and might support higher frequencies.
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5.11.4.1 Typical Characteristics – Outputs at 3 V and 2 V
25
20
15
10
5
10
7.5
5
85°C
25°C
–40°C
85°C
25°C
–40°C
2.5
0
0
–5
0
0.5
1
1.5
2
2.5
3
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
Low-Level Output Voltage (V)
Low-Level Output Voltage (V)
DVCC = 3 V
DVCC = 2 V
Figure 5-6. Typical Low-Level Output Current vs Low-Level
Output Voltage
Figure 5-7. Typical Low-Level Output Current vs Low-Level
Output Voltage
5
0
85°C
85°C
0
25°C
25°C
–2.5
–40°C
–5
–10
–15
–20
–25
–30
–40°C
–5
–7.5
–10
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
0
0.5
1
1.5
2
2.5
3
High-Level Output Voltage (V)
High-Level Output Voltage (V)
DVCC = 3 V
DVCC = 2 V
Figure 5-8. Typical High-Level Output Current vs High-Level
Output Voltage
Figure 5-9. Typical High-Level Output Current vs High-Level
Output Voltage
34
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5.11.5 VREF+ Built-in Reference
Table 5-12 lists the characteristics of VREF+.
Table 5-12. VREF+
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
VREF+
Positive built-in reference voltage
EXTREFEN = 1 with 1-mA load current
2 V, 3 V
1.15
1.19
1.23
V
Temperature coefficient of built-in
reference voltage
TCREF+
30
µV/°C
5.11.6 Timer_A
Table 5-13 lists the characteristics of Timer_A.
Table 5-13. Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-10
and Figure 5-11)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK or ACLK,
External: TACLK,
fTA
Timer_A input clock frequency
2 V, 3 V
16 MHz
duty cycle = 50% ±10%
All capture inputs, minimum pulse
duration required for capture
tTA,cap Timer_A capture timing
2 V, 3 V
20
ns
tTIMR
Timer Clock
CCR0-1
0h
1h
CCR0
CCR0-1
0h
CCR0
tVALID,PWM
Timer
TAx.1
tHD,PWM
Figure 5-10. Timer PWM Mode
Capture
tTIMR
Timer Clock
tSU,CCIA
t,HD,CCIA
TAx.CCIA
Figure 5-11. Timer Capture Mode
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5.11.7 eUSCI
Table 5-14 lists the supported frequencies of the eUSCI in UART mode.
Table 5-14. eUSCI (UART Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK or MODCLK, External: UCLK,
duty cycle = 50% ±10%
feUSCI eUSCI input clock frequency
2 V, 3 V
16 MHz
BITCLK clock frequency
fBITCLK
2 V, 3 V
5
MHz
(equals baud rate in Mbaud)
Table 5-15 lists the characteristics of the eUSCI in UART mode.
Table 5-15. eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UCGLITx = 0
VCC
TYP UNIT
12
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
40
ns
68
(1)
tt
UART receive deglitch time
2 V, 3 V
110
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
Table 5-16 lists the supported frequencies of the eUSCI in SPI master mode.
Table 5-16. eUSCI (SPI Master Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
MHz
feUSCI eUSCI input clock frequency
Internal: SMCLK or MODCLK, duty cycle = 50% ±10%
8
Table 5-17 lists the characteristics of the eUSCI in SPI master mode.
Table 5-17. eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
UCxCLK
cycles
tSTE,LEAD STE lead time, STE active to clock
1
UCxCLK
cycles
tSTE,LAG
STE lag time, last clock to STE inactive
SOMI input data setup time
1
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
45
35
0
tSU,MI
ns
ns
ns
ns
tHD,MI
SOMI input data hold time
0
20
20
UCLK edge to SIMO valid,
CL = 20 pF
tVALID,MO SIMO output data valid time(2)
SIMO output data hold time(3)
0
0
tHD,MO
CL = 20 pF
(1) fUCxCLK = 1 / 2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)
)
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-12 and Figure 5-13.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-
12 and Figure 5-13.
36
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1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
SIMO
tVALID,MO
Figure 5-12. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
SIMO
tVALID,MO
Figure 5-13. SPI Master Mode, CKPH = 1
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Table 5-18 lists the characteristics of the eUSCI in SPI slave mode.
Table 5-18. eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
MIN
55
MAX UNIT
tSTE,LEAD STE lead time, STE active to clock
ns
45
20
tSTE,LAG
STE lag time, Last clock to STE inactive
ns
20
65
ns
40
tSTE,ACC STE access time, STE active to SOMI data out
40
ns
35
STE disable time, STE inactive to SOMI high
tSTE,DIS
impedance
6
4
tSU,SI
SIMO input data setup time
SIMO input data hold time
ns
ns
12
12
tHD,SI
65
ns
40
UCLK edge to SOMI valid,
CL = 20 pF
tVALID,SO SOMI output data valid time(2)
5
5
(3)
tHD,SO
SOMI output data hold time
CL = 20 pF
ns
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)
)
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-14 and Figure 5-15.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-14
and Figure 5-15.
38
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tSU,SIMO
tHD,SIMO
tLOW/HIGH
tLOW/HIGH
SIMO
SOMI
tACC
tVALID,SOMI
tDIS
Figure 5-14. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
SOMI
tACC
tDIS
tVALID,SO
Figure 5-15. SPI Slave Mode, CKPH = 1
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Table 5-19 lists the characteristics of the eUSCI in I2C mode.
Table 5-19. eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-16)
PARAMETER
eUSCI input clock frequency
SCL clock frequency
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK or MODCLK,
External: UCLK
Duty cycle = 50% ±10%
feUSCI
fSCL
16 MHz
2 V, 3 V
2 V, 3 V
0
4.0
0.6
4.7
0.6
0
400 kHz
µs
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
tHD,STA Hold time (repeated) START
tSU,STA
Setup time for a repeated START
2 V, 3 V
µs
tHD,DAT Data hold time
tSU,DAT Data setup time
2 V, 3 V
2 V, 3 V
ns
ns
250
4.0
0.6
50
fSCL = 100 kHz
fSCL > 100 kHz
UCGLITx = 0
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
UCCLTOx = 1
UCCLTOx = 2
UCCLTOx = 3
tSU,STO Setup time for STOP
2 V, 3 V
µs
600
25
300
ns
Pulse duration of spikes suppressed by
input filter
tSP
2 V, 3 V
12.5
6.3
150
75
27
30
33
tTIMEOUT Clock low time-out
2 V, 3 V
ms
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
SCL
tLOW
tHIGH
tSP
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-16. I2C Mode Timing
40
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5.11.8 ADC
Table 5-20 lists the input requirements of the ADC.
Table 5-20. ADC, Power Supply and Input Range Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.0
0
TYP
MAX UNIT
DVCC ADC supply voltage
3.6
V
V
V(Ax)
Analog input voltage range
All ADC pins
DVCC
Operating supply current into DVCC
terminal, reference current not
included, repeat-single-channel
mode
2 V
3 V
185
207
fADCCLK = 5 MHz, ADCON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADCDIV = 0, ADCCONSEQx = 10b
IADC
µA
Only one terminal Ax can be selected at one
time, from the pad to the ADC capacitor
array, including wiring and pad
CI
Input capacitance
2.2 V
1.6
34
2.0
2
pF
RI,MUX Input MUX ON resistance
DVCC = 2 V, 0 V ≤ VAx ≤ DVCC
kΩ
kΩ
RI,Misc Input miscellaneous resistance
Table 5-21 lists the timing parameters of the ADC.
Table 5-21. ADC, 10-Bit Timing Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
For specified performance of ADC linearity
parameters
2 V to
3.6 V
fADCCLK
fADCOSC
0.45
5
5.5 MHz
Internal ADC oscillator
(MODOSC)
2 V to
3.6 V
ADCDIV = 0, fADCCLK = fADCOSC
4.5
5.0
5.5 MHz
REFON = 0, Internal oscillator,
10 ADCCLK cycles, 10-bit mode,
fADCOSC = 4.5 MHz to 5.5 MHz
2 V to
3.6 V
2.18
2.67
µs
tCONVERT
Conversion time
External fADCCLK from ACLK or SMCLK,
ADCSSEL ≠ 0
2 V to
3.6 V
12 ×
1 / fADCCLK
The error in a conversion started after tADCON is
less than ±0.5 LSB,
Reference and input signal already settled
RS = 1000 Ω, RI(1) = 36000 Ω, CI = 3.5 pF,
Approximately 8 Tau (t) are required for an error
of less than ±0.5 LSB(2)
Turnon settling time of
the ADC
tADCON
100
ns
µs
2 V
3 V
1.5
2.0
tSample
Sampling time
(1) RI = RI,MUX + RI,Misc
(2) tSample = ln(2n+1) × τ, where n = ADC resolution, τ = (RI + RS) × CI
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Table 5-22 lists the linearity parameters of the ADC.
Table 5-22. ADC, 10-Bit Linearity Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
2.4 V to
3.6 V
Integral linearity error (10-bit mode)
–2
2
EI
Veref+ as reference
LSB
2
2 V to
3.6 V
Integral linearity error (8-bit mode)
Differential linearity error (10-bit mode)
Differential linearity error (8-bit mode)
Offset error (10-bit mode)
–2
–1
2.4 V to
3.6 V
1
ED
Veref+ as reference
Veref+ as reference
LSB
1
2 V to
3.6 V
–1
2.4 V to
3.6 V
–6.5
–6.5
6.5
mV
6.5
EO
2 V to
3.6 V
Offset error (8-bit mode)
Veref+ as reference
–2.0
–3.0%
–2.0
2.0
3.0%
2.0
LSB
LSB
LSB
LSB
2.4 V to
3.6 V
Gain error (10-bit mode)
Internal 1.5-V reference
Veref+ as reference
EG
2 V to
3.6 V
Gain error (8-bit mode)
Internal 1.5-V reference
Veref+ as reference
–3.0%
–2.0
3.0%
2.0
2.4 V to
3.6 V
Total unadjusted error (10-bit mode)
Total unadjusted error (8-bit mode)
Internal 1.5-V reference
Veref+ as reference
–3.0%
–2.0
3.0%
2.0
ET
2 V to
3.6 V
Internal 1.5-V reference
–3.0%
3.0%
ADCON = 1, INCH = 0Ch,
TA = 0°C
(1)
VSENSOR
See
3 V
3 V
913
mV
(2)
TCSENSOR See
ADCON = 1, INCH = 0Ch
3.35
mV/°C
ADCON = 1, INCH = 0Ch, Error
of conversion result ≤1 LSB,
AM and all LPMs above LPM3
3 V
3 V
30
tSENSOR
(sample)
Sample time required if channel 12 is
selected(3)
µs
ADCON = 1, INCH = 0Ch, Error
of conversion result ≤1 LSB,
LPM3
100
(1) The temperature sensor offset can vary significantly. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
(2) The device descriptor structure contains calibration values for 30°C and 85°C for each available reference voltage level. The sensor
voltage can be computed as VSENSE = TCSENSOR × (Temperature, °C) + VSENSOR , where TCSENSOR and VSENSOR can be computed
from the calibration values for higher accuracy.
(3) The typical equivalent impedance of the sensor is 700 kΩ. The sample time required includes the sensor on time, tSENSOR(on)
.
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5.11.9 CapTIvate
Table 5-23 lists the characteristics of the CapTIvate module.
Table 5-23. CapTIvate Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
1.5
TYP MAX UNIT
VREG
CREG
Reference voltage output
External buffer capacitor
1.55
1
1.6
1.2
V
ESR ≤ 200 mΩ
0.8
µF
Maximum capacitance of all external
electrodes on all CapTIvate blocks
CELECTRODE
tWAKEUP,COLD
Running a conversion at 4 MHz
300
pF
Voltage regulator wake-up time
LDO completely off then turned on
1
ms
us
tWAKEUP,WARM Voltage regulator wake-up time
LDO in low-power mode then turned on
300
fCAPCLK
Captivate oscillator frequency, nominal
CapTIvate oscillator duty cycle
TA = 25ºC, CAPCLK0, FREQSHFT = 00b –3%
Excluding first clock cycle, DC = thigh × f 40%
16 +3%
MHz
DCCAPCLK
50% 60%
Table 5-24 lists the signal-to-noise ratio of the CapTIvate module.
Table 5-24. CapTIvate Signal-to-Noise Ratio Characteristics
over operating free-air temperature range from –40°C to 105°C ambient (TA), unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TA = 25°C, Ct > 0.5 pF, Cp < 20 pF, >2.5% change in
capacitance(2)
5:1
36:1
TA = 0°C, Ct > 0.5 pF, Cp < 20 pF, >2.5% change in
capacitance(2)
SNR
Signal-to-noise ratio(1)
28:1
19:1
TA = –40°C, Ct > 0.5 pF, Cp < 20 pF, >2.5% change in
capacitance(2)
(1) SNR is defined as the ratio of the measured change in electrode capacitance due to a touch compared with the measured change in
capacitance due to the device noise floor. For additional detail on SNR in capacitive sensing applications and how to measure it in your
system, see Sensitivity, SNR, and Design Margin in Capacitive Touch Applications.
(2) Ct represents the increase or decrease in electrode capacitance due to a touch. Cp represents the inherent parasitic capacitance of the
sensing electrode that is present when no touch is applied. Therefore, the touch signal is defined as Ct/Cp, expressed as a percent
change in capacitance. Increasing Ct or decreasing Cp increases signal.
5.11.10 FRAM
Table 5-25 lists the characteristics of the FRAM.
Table 5-25. FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
1015
100
40
TYP
MAX
UNIT
Read and write endurance
cycles
TJ = 25°C
tRetention
Data retention duration
TJ = 70°C
TJ = 85°C
years
10
(1)
IWRITE
IERASE
tWRITE
Current to write into FRAM
Erase current
IREAD
nA
nA
ns
N/A(2)
(3)
Write time
tREAD
(4)
(4)
NWAITSx = 0
NWAITSx = 1
1/fSYSTEM
2/fSYSTEM
tREAD
Read time
ns
(1) Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read
current IREAD is included in the active mode current consumption parameter IAM,FRAM
.
(2) FRAM does not require a special erase sequence.
(3) Writing into FRAM is as fast as reading.
(4) The maximum read (and write) speed is specified by fSYSTEM using the appropriate wait state settings (NWAITSx).
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5.11.11 Debug and Emulation
Table 5-26 lists the characteristics of the Spy-Bi-Wire interface.
Table 5-26. JTAG, Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-17)
PARAMETER
Spy-Bi-Wire input frequency
VCC
MIN
0
TYP
MAX UNIT
fSBW
2 V, 3 V
2 V, 3 V
10
15
MHz
µs
tSBW,Low
Spy-Bi-Wire low clock pulse duration
0.028
SBWTDIO setup time (before falling edge of SBWTCK in TMS and
TDI slot, Spy-Bi-Wire)
tSU, SBWTDIO
tHD, SBWTDIO
tValid, SBWTDIO
tSBW, En
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
4
ns
ns
ns
µs
SBWTDIO hold time (after rising edge of SBWTCK in TMS and TDI
slot, Spy-Bi-Wire)
19
SBWTDIO data valid time (after falling edge of SBWTCK in TDO
slot, Spy-Bi-Wire)
31
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
110
(1)
edge)
tSBW,Ret
Rinternal
Spy-Bi-Wire return to normal operation time(2)
2 V, 3 V
2 V, 3 V
15
20
100
50
µs
Internal pulldown resistance on TEST
35
kΩ
(1) Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) Maximum tSBW,Ret time after pulling or releasing the TEST/SBWTCK pin low until the Spy-Bi-Wire pins revert from their Spy-Bi-Wire
function to their application function. This time applies only if the Spy-Bi-Wire mode is selected.
tSBW,EN
tSBW,Low
1/fSBW
tSBW,High
tSBW,Ret
TEST/SBWTCK
tEN,SBWTDIO
tValid,SBWTDIO
RST/NMI/SBWTDIO
tSU,SBWTDIO
tHD,SBWTDIO
Figure 5-17. JTAG Spy-Bi-Wire Timing
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Table 5-27 lists the characteristics of the 4-wire JTAG interface.
Table 5-27. JTAG, 4-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18)
PARAMETER
VCC
MIN
0
TYP
MAX UNIT
fTCK
TCK input frequency(1)
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
10 MHz
tTCK,Low
tTCK,High
tSU,TMS
tHD,TMS
tSU,TDI
tHD,TDI
TCK low clock pulse duration
15
15
11
3
ns
ns
ns
ns
ns
ns
TCK high clock pulse duration
TMS setup time (before rising edge of TCK)
TMS hold time (after rising edge of TCK)
TDI setup time (before rising edge of TCK)
TDI hold time (after rising edge of TCK)
13
5
tZ-Valid,TDO TDO high impedance to valid output time (after falling edge of TCK)
tValid,TDO TDO to new valid output time (after falling edge of TCK)
tValid-Z,TDO TDO valid to high-impedance output time (after falling edge of TCK)
26
26
ns
ns
ns
µs
kΩ
26
tJTAG,Ret
Rinternal
Spy-Bi-Wire return to normal operation time
Internal pulldown resistance on TEST
15
20
100
50
2 V, 3 V
35
(1) fTCK may be restricted to meet the timing requirements of the module selected.
1/fTCK
tTCK,Low
tTCK,High
TCK
TMS
tSU,TMS
tHD,TMS
TDI
(or TDO as TDI)
tSU,TDI
tHD,TDI
TDO
tZ-Valid,TDO
tValid,TDO
tValid-Z,TDO
tJTAG,Ret
TEST
Figure 5-18. JTAG 4-Wire Timing
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6 Detailed Description
6.1 Overview
The MSP430FR263x and MSP430FR253x ultra-low-power MCUs are the first FRAM-based MCUs with
integrated high-performance charge-transfer CapTIvate technology in ultra-low-power high-reliability high-
flexibility MCUs. The MSP430FR263x and MSP430FR253x MCUs feature up to 16 self-capacitance or 64
mutual-capacitance electrodes, proximity sensing, and high accuracy up to 1-fF detection. The MCUs also
include four 16-bit timers, eUSCIs that support UART, SPI, and I2C, a hardware multiplier, an RTC module
with alarm capabilities, and a high-performance 10-bit ADC.
6.2 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter (PC), stack pointer (SP), status register
(SR), and constant generator (CG), respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be
managed with all instructions.
6.3 Operating Modes
The MSP430FR263x and MSP430FR253x MCUs have one active mode and several software-selectable
low-power modes of operation (see Table 6-1). An interrupt event can wake the MCU from low-power
mode (LPM0 or LPM3), service the request, and restore the MCU back to the low-power mode on return
from the interrupt program. Low-power modes LPM3.5 and LPM4.5 disable the core supply to minimize
power consumption.
Table 6-1. Operating Modes
AM
LPM0
CPU OFF
16 MHz
LPM3
STANDBY
40 kHz
LPM4
OFF
0
LPM3.5
ONLY RTC
40 kHz
LPM4.5
SHUTDOWN
0
ACTIVE
MODE
(FRAM ON)
MODE
Maximum system clock
16 MHz
1.7 µA/button
average with
8-Hz scan
0.73 µA with
RTC counter
only in LFXT
0.49 µA
without SVS
16 nA without
SVS
Power consumption at 25°C, 3 V
126 µA/MHz
40 µA/MHz
Wake-up time
N/A
N/A
Instant
All
10 µs
10 µs
350 µs
350 µs
I/O
CapTIvate
I/O
RTC
I/O
Wake-up events
All
Full
Regulation
Full
Regulation
Partial Power Partial Power Partial Power
Regulator
Power Down
Down
Optional
On
Down
Optional
On
Down
Optional
On
Power
SVS
On
On
On
On
Optional
On
Brownout
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Table 6-1. Operating Modes (continued)
AM
LPM0
LPM3
LPM4
LPM3.5
LPM4.5
ACTIVE
MODE
MODE
CPU OFF
STANDBY
OFF
ONLY RTC
SHUTDOWN
(FRAM ON)
MCLK
Active
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
On
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
On
On
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
SMCLK
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Off
FLL
Off
Off
DCO
Off
Off
MODCLK
REFO
Off
Off
Clock(1)
Optional
Optional
Optional
Optional
Optional
Off
Off
ACLK
Off
XT1CLK
VLOCLK
CapTIvate MODCLK
CPU
Optional
Optional
Off
Off
FRAM
On
On
Off
Off
Core
RAM
On
On
On
Off
Backup memory(2)
Timer0_A3
Timer1_A3
Timer2_A2
Timer3_A2
WDT
On
On
On
On
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Off
Off
Off
Off
Off
Off
eUSCI_A0
eUSCI_A1
eUSCI_B0
CRC
Off
Peripherals
Off
Off
Off
Off
Off
Off
ADC
Optional
Optional
Optional
Off
RTC
Optional
Off
CapTIvate
General-purpose
digital input/output
I/O
On
Optional
State Held
State Held
State Held
State Held
(1) The status shown for LPM4 applies to internal clocks only.
(2) Backup memory contains 32 bytes of register space in peripheral memory. See Table 6-24 and Table 6-43 for its memory allocation.
NOTE
XT1CLK and VLOCLK can be active during LPM4 if requested by low-frequency peripherals,
such as RTC, WDT, or CapTIvate.
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6.4 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see
Table 6-2). The vector contains the 16-bit address of the appropriate interrupt-handler instruction
sequence.
Table 6-2. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
System Reset
Power up, Brownout, Supply supervisor
External reset RST
Watchdog time-out, Key violation
FRAM access time error
FRAM uncorrectable bit error detection
Software POR, BOR
PMMPORIFG, PMMBORIFG, SVSHIFG
PMMRSTIFG
WDTIFG
ACCTEIFG
UBDIFG
SYSRSTIV
FLLUNLOCKIFG
Reset
FFFEh
63, Highest
FLL unlock error
System NMI
Vacant memory access
JTAG mailbox
VMAIFG
JMBINIFG, JMBOUTIFG
CBDIFG, UBDIFG
Nonmaskable
Nonmaskable
FFFCh
FFFAh
62
61
FRAM bit error detection
User NMI
External NMI
Oscillator fault
NMIIFG
OFIFG
Timer0_A3
Timer0_A3
Timer1_A3
Timer1_A3
TA0CCR0 CCIFG0
Maskable
Maskable
Maskable
Maskable
Maskable
FFF8h
FFF6h
FFF4h
FFF2h
60
59
58
57
TA0CCR1 CCIFG1, TA0CCR2 CCIFG2,
TA0IFG (TA0IV)
TA1CCR0 CCIFG0
TA1CCR1 CCIFG1, TA1CCR2 CCIFG2,
TA1IFG (TA1IV)
Timer2_A2
Timer2_A2
TA2CCR0 CCIFG0
TA2CCR1 CCIFG1, TA2IFG (TA2IV)
TA3CCR0 CCIFG0
FFF0h
FFEEh
FFECh
FFEAh
FFE8h
FFE6h
56
55
54
53
52
51
Timer3_A2
Maskable
Timer3_A2
TA3CCR1 CCIFG1, TA3IFG (TA3IV)
RTCIFG
RTC
Maskable
Maskable
Watchdog timer interval mode
WDTIFG
UCTXCPTIFG, UCSTTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
(UCA0IV)
eUSCI_A0 receive or transmit
eUSCI_A1 receive or transmit
Maskable
Maskable
FFE4h
FFE2h
50
49
UCTXCPTIFG, UCSTTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
(UCA1IV)
UCB0RXIFG, UCB0TXIFG (SPI mode)
UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1, UCRXIFG2,
UCTXIFG2, UCRXIFG3, UCTXIFG3,
UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB0IV)
eUSCI_B0 receive or transmit
Maskable
Maskable
FFE0h
FFDEh
48
47
ADCIFG0, ADCINIFG, ADCLOIFG,
ADCHIIFG, ADCTOVIFG, ADCOVIFG
(ADCIV)
ADC
P1
P2
P1IFG.0 to P1IFG.7 (P1IV)
P2IFG.0 to P2IFG.7 (P2IV)
Maskable
Maskable
Maskable
FFDCh
FFDAh
FFD8h
46
45
CapTIvate
(See CapTivate Design Center for details)
44, Lowest
FFD6h to
FF88h
Reserved
Reserved
Maskable
48
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Table 6-2. Interrupt Sources, Flags, and Vectors (continued)
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
BSL Signature 2
BSL Signature 1
JTAG Signature 2
JTAG Signature 1
0FF86h
0FF84h
0FF82h
0FF80h
Signatures
6.5 Bootloader (BSL)
The BSL lets users program the FRAM or RAM using either the UART serial interface or the I2C interface.
Access to the MCU memory through the BSL is protected by an user-defined password. Use of the BSL
requires four pins (see Table 6-3 and Table 6-4). BSL entry requires a specific entry sequence on the
RST/NMI/SBWTDIO and TEST/SBWTCK pins. This device supports the blank device detection to
automatically invoke the BSL, skipping this special entry sequence, to save time and simplify onboard
programming. For a complete description of the features of the BSL, see the MSP430 FRAM Device
Bootloader (BSL) User's Guide.
Table 6-3. UART BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
Entry sequence signal
Entry sequence signal
Data transmit
RST/NMI/SBWTDIO
TEST/SBWTCK
P1.4
P1.5
VCC
VSS
Data receive
Power supply
Ground supply
Table 6-4. I2C BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
Entry sequence signal
Entry sequence signal
Data transmit and receive
Clock
RST/NMI/SBWTDIO
TEST/SBWTCK
P1.2
P1.3
VCC
VSS
Power supply
Ground supply
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6.6 JTAG Standard Interface
The MSP low-power microcontrollers support the standard JTAG interface, which requires four signals for
sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK
pin enables the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface
with MSP430 development tools and device programmers. Table 6-5 lists the JTAG pin requirements. For
further details on interfacing to development tools and device programmers, see the MSP430 Hardware
Tools User's Guide. For details on using the JTAG interface, see MSP430 Programming With the JTAG
Interface.
Table 6-5. JTAG Pin Requirements and Function
DEVICE SIGNAL
P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+
P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5
P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6
P1.7/UCA0STE/SMCLK/TDO/A7
TEST/SBWTCK
DIRECTION
JTAG FUNCTION
JTAG clock input
JTAG state control
JTAG data input, TCLK input
JTAG data output
Enable JTAG pins
External reset
IN
IN
IN
OUT
IN
IN
–
RST/NMI/SBWTDIO
DVCC
Power supply
DVSS
–
Ground supply
6.7 Spy-Bi-Wire Interface (SBW)
The MSP low-power microcontrollers support the 2-wire SBW interface. SBW can be used to interface
with MSP development tools and device programmers. Table 6-6 lists the SBW interface pin requirements.
For further details on interfacing to development tools and device programmers, see the MSP430
Hardware Tools User's Guide. For details on using the SBW interface, see the MSP430 Programming
With the JTAG Interface.
Table 6-6. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
DVCC
DIRECTION
SBW FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input and output
Power supply
IN
IN, OUT
–
–
DVSS
Ground supply
6.8 FRAM
The FRAM can be programmed using the JTAG port, SBW, the BSL, or in-system by the CPU. Features
of the FRAM include:
•
•
•
Byte and word access capability
Programmable wait state generation
Error correction coding (ECC)
6.9 Memory Protection
The device features memory protection for user access authority and write protection, including options to:
•
Secure the whole memory map to prevent unauthorized access from JTAG port or BSL, by writing
JTAG and BSL signatures using the JTAG port, SBW, the BSL, or in-system by the CPU.
•
Enable write protection to prevent unwanted write operation to FRAM contents by setting the control
bits in the System Configuration 0 register. For detailed information, see the System Resets, Interrupts,
and Operating Modes, System Control Module (SYS) chapter in the MP430FR4xx and MP430FR2xx
Family User's Guide.
50
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6.10 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. All peripherals can be
handled by using all instructions in the memory map. For complete module description, see the
MP430FR4xx and MP430FR2xx Family User's Guide.
6.10.1 Power-Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM
also includes supply voltage supervisor (SVS) and brownout protection. The brownout reset circuit (BOR)
is implemented to provide the proper internal reset signal to the device during power on and power off.
The SVS circuitry detects if the supply voltage drops below a user-selectable safe level. SVS circuitry is
available on the primary supply.
The device contains two on-chip reference: 1.5 V for internal reference and 1.2 V for external reference.
The 1.5-V reference is internally connected to ADC channel 13. DVCC is internally connected to ADC
channel 15. When DVCC is set as the reference voltage for ADC conversion, the DVCC can be easily
represent as Equation 1 by using ADC sampling 1.5-V reference without any external components
support.
DVCC = (1023 × 1.5 V) ÷ 1.5-V reference ADC result
(1)
A
1.2-V reference voltage can be buffered and output to P1.4/MCLK/TCK/A4/VREF+, when
EXTREFEN = 1 in the PMMCTL1 register. ADC channel 4 can also be selected to monitor this voltage.
For more detailed information, see the MP430FR4xx and MP430FR2xx Family User's Guide.
6.10.2 Clock System (CS) and Clock Distribution
The clock system includes a 32-kHz crystal oscillator (XT1), an internal very-low-power low-frequency
oscillator (VLO), an integrated 32-kHz RC oscillator (REFO), an integrated internal digitally controlled
oscillator (DCO) that may use frequency-locked loop (FLL) locking with internal or external 32-kHz
reference clock, and an on-chip asynchronous high-speed clock (MODOSC). The clock system is
designed for cost-effective designs with minimal external components. A fail-safe mechanism is included
for XT1. The clock system module offers the following clock signals.
•
Main Clock (MCLK): The system clock used by the CPU and all relevant peripherals accessed by the
bus. All clock sources except MODOSC can be selected as the source with a predivider of 1, 2, 4, 8,
16, 32, 64, or 128.
•
•
Sub-Main Clock (SMCLK): The subsystem clock used by the peripheral modules. SMCLK derives from
the MCLK with a predivider of 1, 2, 4, or 8. This means SMCLK is always equal to or less than MCLK.
Auxiliary Clock (ACLK): This clock is derived from the external XT1 clock or internal REFO clock up to
40 kHz.
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All peripherals may have one or several clock sources depending on specific functionality. Table 6-7 lists
the clock distribution used in this device.
Table 6-7. Clock Distribution
CLOCK
SOURCE
SELECT
BITS
MCLK
SMCLK
ACLK
MODCLK
XT1CLK
VLOCLK
EXTERNAL PIN
Frequency
Range
DC to
16 MHz
DC to
16 MHz
DC to
40 kHz
5 MHz
±10%
DC to
40 kHz
10 kHz
±50%
–
CPU
N/A
N/A
Default
–
–
–
–
–
–
–
–
–
FRAM
RAM
Default
–
–
–
N/A
Default
–
–
–
–
–
–
–
CRC
N/A
Default
–
–
–
–
–
I/O
N/A
Default
–
–
–
–
–
–
TA0
TASSEL
TASSEL
TASSEL
TASSEL
UCSSEL
UCSSEL
UCSSEL
WDTSSEL
ADCSSEL
CAPTSSEL
CAPCLKSEL
RTCSS
–
–
–
–
–
–
–
–
–
–
–
–
10b
01b
01b
01b
01b
–
–
–
–
00b (TA0CLK pin)
TA1
10b
–
–
–
00b (TA1CLK pin)
TA2
10b
–
–
–
–
TA3
10b
–
–
–
–
eUSCI_A0
eUSCI_A1
eUSCI_B0
WDT
10b or 11b
10b or 11b
10b or 11b
00b
01b
01b
01b
–
–
–
00b (UCA0CLK pin)
–
–
–
00b (UCA1CLK pin)
–
–
–
00b (UCB0CLK pin)
01b
01b
00b
–
–
10b or 11b
–
–
–
–
–
ADC
11b
00b
–
–
–
–
01b
–
CapTIvate
RTC
1b
–
–
01b
–
–
10b
11b
6.10.3 General-Purpose Input/Output Port (I/O)
Up to 19 I/O ports are implemented.
•
•
•
•
•
•
•
•
P1 and P2 are full 8-bit ports; P3 has 3 bits implemented.
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
All ports support programmable pullup or pulldown.
Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for P1 and P2.
Read and write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise or word-wise in pairs.
CapTIvate functionality is supported on all CAPx.y pins.
NOTE
Configuration of digital I/Os after BOR reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance
with Schmitt triggers and module functions disabled. To enable the I/O functions after a BOR
reset, the ports must be configured first and then the LOCKLPM5 bit must be cleared. For
details, see the Configuration After Reset section in the Digital I/O chapter of the
MP430FR4xx and MP430FR2xx Family User's Guide.
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6.10.4 Watchdog Timer (WDT)
The primary function of the WDT module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not
needed in an application, the module can be configured as interval timer and can generate interrupts at
selected time intervals. Table 6-8 lists the system clocks that can be used to source the WDT.
Table 6-8. WDT Clocks
NORMAL OPERATION
WDTSSEL
(WATCHDOG AND INTERVAL TIMER MODE)
00
01
10
11
SMCLK
ACLK
VLOCLK
Reserved
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6.10.5 System (SYS) Module
The SYS module handles many of the system functions within the device. These features include power-
on reset (POR) and power-up clear (PUC) handling, NMI source selection and management, reset
interrupt vector generators, bootloader entry mechanisms, and configuration management (device
descriptors). The SYS module also includes a data exchange mechanism through SBW called a JTAG
mailbox mail box that can be used in the application. Table 6-9 summarizes the interrupts that are
managed by the SYS module.
Table 6-9. System Module Interrupt Vector Registers
INTERRUPT VECTOR
ADDRESS
INTERRUPT EVENT
VALUE
PRIORITY
REGISTER
No interrupt pending
Brownout (BOR)
00h
02h
Highest
RSTIFG RST/NMI (BOR)
PMMSWBOR software BOR (BOR)
LPMx.5 wake up (BOR)
Security violation (BOR)
Reserved
04h
06h
08h
0Ah
0Ch
SVSHIFG SVSH event (BOR)
Reserved
0Eh
10h
SYSRSTIV, System Reset
015Eh
Reserved
12h
PMMSWPOR software POR (POR)
WDTIFG watchdog time-out (PUC)
WDTPW password violation (PUC)
FRCTLPW password violation (PUC)
Uncorrectable FRAM bit error detection
Peripheral area fetch (PUC)
PMMPW PMM password violation (PUC)
FLL unlock (PUC)
14h
16h
18h
1Ah
1Ch
1Eh
20h
24h
Reserved
22h, 26h to 3Eh
00h
Lowest
Highest
No interrupt pending
SVS low-power reset entry
Uncorrectable FRAM bit error detection
Reserved
02h
04h
06h
Reserved
08h
Reserved
0Ah
Reserved
0Ch
SYSSNIV, System NMI
015Ch
Reserved
0Eh
Reserved
10h
VMAIFG Vacant memory access
JMBINIFG JTAG mailbox input
JMBOUTIFG JTAG mailbox output
Correctable FRAM bit error detection
Reserved
12h
14h
16h
18h
1Ah to 1Eh
00h
Lowest
Highest
Lowest
No interrupt pending
NMIIFG NMI pin or SVSH event
OFIFG oscillator fault
Reserved
02h
SYSUNIV, User NMI
015Ah
04h
06h to 1Eh
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6.10.6 Cyclic Redundancy Check (CRC)
The 16-bit cyclic redundancy check (CRC) module produces a signature based on a sequence of data
values and can be used for data checking purposes. The CRC generation polynomial is compliant with
CRC-16-CCITT standard of x16 + x12 + x5 + 1.
6.10.7 Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
The eUSCI modules are used for serial data communications. The eUSCI_A module supports either
UART or SPI communications. The eUSCI_B module supports either SPI or I2C communications.
Additionally, eUSCI_A supports automatic baud-rate detection and IrDA. Table 6-10 lists the pin
configurations that are required for each eUSCI mode.
Table 6-10. eUSCI Pin Configurations
PIN
P1.4
P1.5
P1.6
P1.7
P2.6
P2.5
P2.4
P3.1
PIN
UART
TXD
RXD
–
SPI
SIMO
SOMI
SCLK
STE
eUSCI_A0
eUSCI_A1
eUSCI_B0
–
TXD
RXD
–
SIMO
SOMI
SCLK
STE
–
I2C
SPI
P1.0
P1.1
P1.2
P1.3
–
STE
–
SCLK
SIMO
SOMI
SDA
SCL
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6.10.8 Timers (Timer0_A3, Timer1_A3, Timer2_A2 and Timer3_A2)
The Timer0_A3 and Timer1_A3 modules are 16-bit timers and counters with three capture/compare
registers each. Both timers support multiple captures or compares, PWM outputs, and interval timing (see
Table 6-11 and Table 6-12). Both timers have extensive interrupt capabilities. Interrupts may be generated
from the counter on overflow conditions and from each capture/compare register.
The CCR0 registers on Timer0_A3 and Timer1_A3 are not externally connected and can be used only for
hardware period timing and interrupt generation. In Up mode, these CCR0 registers can be used to set the
overflow value of the counter.
Table 6-11. Timer0_A3 Signal Connections
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
PORT PIN
MODULE BLOCK
P1.0
TA0CLK
TACLK
ACLK
ACLK (internal)
SMCLK (internal)
Timer
N/A
SMCLK
CCI0A
Timer1_A3 CCI0B
input
CCI0B
CCR0
CCR1
TA0
DVSS
DVCC
TA0.1
GND
VCC
P1.1
P1.2
CCI1A
TA0.1
Timer1_A3 CCI1B
input
from RTC (internal)
CCI1B
TA1
TA2
DVSS
DVCC
TA0.2
GND
VCC
CCI2A
TA0.2
Timer1_A3 CCI2B
input,
CCI2B
CCR2
IR Input
DVSS
DVCC
GND
VCC
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Table 6-12. Timer1_A3 Signal Connections
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
PORT PIN
MODULE BLOCK
P1.6
TA1CLK
TACLK
ACLK
ACLK (internal)
SMCLK (internal)
Timer
N/A
SMCLK
CCI0A
Timer0_A3 CCR0B
output (internal)
CCI0B
CCR0
CCR1
CCR2
TA0
DVSS
DVCC
TA1.1
GND
VCC
P1.5
P1.4
CCI1A
TA1.1
Timer0_A3 CCR1B
output (internal)
CCI1B
to ADC trigger
TA1
TA2
DVSS
DVCC
TA1.2
GND
VCC
CCI2A
TA1.2
Timer0_A3 CCR2B
output (internal)
CCI2B
IR Input
DVSS
DVCC
GND
VCC
The interconnection of Timer0_A3 and Timer1_A3 can be used to modulate the eUSCI_A pin of
UCA0TXD/UCA0SIMO in either ASK or FSK mode, with which a user can easily acquire a modulated
infrared command for directly driving an external IR diode. The IR functions are fully controlled by SYS
configuration registers 1 including IREN (enable), IRPSEL (polarity select), IRMSEL (mode select),
IRDSSEL (data select), and IRDATA (data) bits. For more information, see the System Resets, Interrupts,
and Operating Modes, System Control Module (SYS) chapter in the MP430FR4xx and MP430FR2xx
Family User's Guide.
The Timer2_A2 and Timer3_A2 modules are 16-bit timers and counters with two capture/compare
registers each. Both timers support multiple captures or compares and interval timing (see Table 6-13 and
Table 6-14). Both timers have extensive interrupt capabilities. Interrupts may be generated from the
counter on overflow conditions and from each capture register.
The CCR0 registers on Timer2_TA2 and Timer3_TA2 are not externally connected and can be used only
for hardware period timing and interrupt generation. In Up mode, these CCR0 registers can be used to set
the overflow value of the counter. Timer2_A2 and Timer3_A2 are only internally connected and do not
support PWM output.
Table 6-13. Timer2_A2 Signal Connections
MODULE OUTPUT
DEVICE INPUT SIGNAL MODULE INPUT NAME
MODULE BLOCK
DEVICE OUTPUT SIGNAL
SIGNAL
ACLK (internal)
ACLK
SMCLK
CCI0A
CCI0B
GND
Timer
N/A
SMCLK (internal)
Timer3_A3 CCI0B input
Timer3_A3 CCI1B input
CCR0
CCR1
TA0
DVSS
DVCC
VCC
CCI1A
CCI1B
GND
CCR1
DVSS
DVCC
VCC
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Table 6-14. Timer3_A2 Signal Connections
MODULE OUTPUT
SIGNAL
DEVICE INPUT SIGNAL MODULE INPUT NAME
MODULE BLOCK
DEVICE OUTPUT SIGNAL
ACLK (internal)
ACLK
SMCLK
CCI0A
CCI0B
GND
Timer
N/A
SMCLK (internal)
Timer3_A3 CCI0B input
CCR0
CCR1
TA0
DVSS
DVCC
VCC
CCI1A
CCI1B
GND
Timer3_A3 CCI1B input
CCR1
DVSS
DVCC
VCC
6.10.9 Hardware Multiplier (MPY)
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The MPY module supports signed multiplication,
unsigned multiplication, signed multiply-and-accumulate, and unsigned multiply-and-accumulate
operations.
6.10.10 Backup Memory (BAKMEM)
The BAKMEM supports data retention during LPM3.5. This device provides up to 32 bytes that are
retained during LPM3.5.
6.10.11 Real-Time Clock (RTC)
The RTC is a 16-bit modulo counter that is functional in AM, LPM0, LPM3, and LPM3.5. This module may
periodically wake up the CPU from LPM0, LPM3, and LPM3.5 based on timing from a low-power clock
source such as the XT1 and VLO clocks. In AM, SMCLK can drive the RTC to generate high-frequency
timing events and interrupts. The RTC overflow events trigger:
•
•
Timer0_A3 CCR1B
ADC conversion trigger when ADCSHSx bits are set as 01b
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6.10.12 10-Bit Analog-to-Digital Converter (ADC)
The 10-bit ADC module supports fast 10-bit analog-to-digital conversions with single-ended input. The
module implements a 10-bit SAR core, sample select control, reference generator and a conversion result
buffer. A window comparator with lower and upper limits allows CPU-independent result monitoring with
three window comparator interrupt flags.
The ADC supports 10 external inputs and 4 internal inputs (see Table 6-15).
Table 6-15. ADC Channel Connections
ADCINCHx
ADC CHANNELS
EXTERNAL PINOUT
0
1
A0/Veref+
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
NA
A1
2
A2/Veref-
3
A3
A4(1)
4
5
A5
6
A6
7
A7
8
A8
9
A9
Not used
NA
10
11
12
13
14
15
N/A
N/A
N/A
N/A
N/A
N/A
Not used
On-chip temperature sensor
Reference voltage (1.5 V)
DVSS
DVCC
(1) When A4 is used, the PMM 1.2-V reference voltage can be output to this pin by setting the PMM
control register. The 1.2-V voltage can be directly measured by A4 channel.
Software or a hardware trigger can start the analog-to-digital conversion. Table 6-16 lists the trigger
sources that are available.
Table 6-16. ADC Trigger Signal Connections
ADCSHSx
TRIGGER SOURCE
BINARY
DECIMAL
00
01
10
11
0
1
2
3
ADCSC bit (software trigger)
RTC event
TA1.1B
--
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6.10.13 CapTIvate Technology
The CapTIvate module detects the capacitance changed with a charge-transfer method and is functional
in AM, LPM0, LPM3, and LPM4. The CapTIvate module can periodically wake the CPU from LPM0,
LPM3, or LPM4 based on a CapTIvate timer source such as ACLK or VLO clock. The CapTIvate module
supports the following touch-sensing capability:
•
Up to 64 CapTIvate buttons composed of 4 CapTIvate blocks. Each block consists of 4 I/Os, and these
blocks scan in parallel of 4 electrodes.
•
Each block can be individually configured in self or mutual mode. Each CapTIvate I/O can be used for
either self or mutual electrodes.
•
•
•
Supports a wake-on-touch state machine.
Supports synchronized conversion on a zero-crossing event trigger.
Processing logic to perform filter calculation and threshold detection.
To learn more about MSP MCUs featuring CapTIvate technology, see the CapTIvate™ Technology Guide.
6.10.14 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The EEM on these devices has the following features:
•
•
•
•
•
•
Three hardware triggers or breakpoints on memory access
One hardware trigger or breakpoint on CPU register write access
Up to four hardware triggers that can be combined to form complex triggers or breakpoints
One cycle counter
Clock control on module level
EEM version: S
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6.11 Input/Output Diagrams
6.11.1 Port P1 Input/Output With Schmitt Trigger
Figure 6-1 shows the port diagram. Table 6-17 summarizes the selection of pin function.
A0..A7
From SYS (ADCPCTLx)
P1REN.x
P1DIR.x
00
01
From Module1
10
11
2 bit
DVSS
DVCC
0
1
00
01
P1OUT.x
From Module1
From Module2
DVSS
10
11
2 bit
P1SEL.x
EN
D
To module
P1IN.x
P1IE.x
Bus
Keeper
P1 Interrupt
D
S
Q
P1.0/UCB0STE/TA0CLK/A0/Veref+
P1.1/UCB0CLK/TA0.1/A1
P1IFG.x
P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref-
P1.3/UCB0SOMI/UCB0SCL/MCLK/A3
P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+
P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5
P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6
P1.7/UCA0STE/SMCLK/TDO/A7
Edge
Select
P1IES.x
From JTAG
To JTAG
Figure 6-1. Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
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Table 6-17. Port P1 (P1.0 to P1.7) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SELx
ADCPCTLx(2)
JTAG
N/A
N/A
N/A
N/A
N/A
N/A
P1.0 (I/O)
UCB0STE
TA0CLK
A0/Veref+
P1.1 (I/O)
UCB0CLK
TA0.CCI1A
TA0.1
I: 0; O: 1
00
01
10
X
0
X
0
P1.0/UCB0STE/
TA0CLK/A0
0
0
0
X
1 (x = 0)
I: 0; O: 1
00
01
0
0
X
P1.1/UCB0CLK/TA0.1/
A1
1
0
10
0
N/A
1
A1
X
X
1 (x = 1)
N/A
N/A
N/A
P1.2 (I/O)
I: 0; O: 1
00
01
0
0
UCB0SIMO/UCB0SDA
TA0.CCI2A
TA0.2
X
P1.2/UCB0SIMO/
UCB0SDA/TA0.2/A2
2
3
0
10
0
N/A
1
A2/Veref-
X
X
1 (x = 2)
N/A
N/A
P1.3 (I/O)
UCB0SOMI/UCB0SCL
MCLK
I: 0; O: 1
00
01
10
X
0
X
0
N/A
P1.3/UCB0SOMI/
UCB0SCL/MCLK/A3
1
0
N/A
A3
X
1 (x = 3)
N/A
P1.4 (I/O)
UCA0TXD/UCA0SIMO
TA1.CCI2A
TA1.2
I: 0; O: 1
00
01
0
0
Disabled
Disabled
X
P1.4/UCA0TXD/
UCA0SIMO/TA1.2/TCK/
A4 /VREF+
0
4
5
10
0
Disabled
1
A4, VREF+
JTAG TCK
P1.5 (I/O)
UCA0RXD/UCA0SOMI
TA1.CCI1A
TA1.1
X
X
X
1 (x = 4)
Disabled
TCK
X
X
0
0
I: 0; O: 1
00
01
Disabled
Disabled
X
P1.5/UCA0RXD/
UCA0SOMI/TA1.1/TMS/
A5
0
10
0
Disabled
1
A5
X
X
X
1 (x = 5)
Disabled
TMS
JTAG TMS
P1.6 (I/O)
UCA0CLK
TA1CLK
X
X
0
I: 0; O: 1
00
01
10
X
Disabled
Disabled
Disabled
Disabled
TDI/TCLK
Disabled
Disabled
Disabled
Disabled
TDO
X
P1.6/UCA0CLK/
TA1CLK/TDI/TCLK/A6
6
7
0
0
A6
X
1 (x = 6)
JTAG TDI/TCLK
P1.7 (I/O)
UCA0STE
SMCLK
X
X
X
I: 0; O: 1
00
01
10
X
0
X
1
0
P1.7/UCA0STE/SMCLK/
TDO/A7
0
1 (x = 7)
X
A7
X
X
JTAG TDO
X
(1) X = don't care
(2) Setting the ADCPCTLx bit in SYSCFG2 register disables both the output driver and input Schmitt trigger to prevent leakage when
analog signals are applied.
62
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6.11.2 Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
Figure 6-2 shows the port diagram. Table 6-18 summarizes the selection of pin function.
P2REN.x
P2DIR.x
00
01
10
11
2 bit
DVSS
DVCC
0
1
00
01
P2OUT.x
From Module1
10
11
DVSS
DVSS
2 bit
P2SEL.x
EN
D
To module
P2IN.x
P2IE.x
Bus
Keeper
P2 Interrupt
D
S
Q
P2.0/XOUT
P2.1/XIN
P2.2/SYNC/ACLK
P2IFG.x
P2IES.x
Edge
Select
Figure 6-2. Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
Table 6-18. Port P2 (P2.0 to P2.2) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P2.x)
x
0
1
FUNCTION
P2DIR.x
P2SELx
00
P2.0 (I/O)
XOUT
I: 0; O: 1
P2.0/XOUT
X
01
P2.1 (I/O)
XIN
I: 0; O: 1
00
P2.1/XIN
X
01
P2.2 (I/O)
SYNC
I: 0; O: 1
00
P2.2/SYNC/ACLK
(1) X = don't care
2
0
1
01
ACLK
10
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6.11.3 Port P2 (P2.3 to P2.7) Input/Output With Schmitt Trigger
Figure 6-3 shows the port diagram. Table 6-19 summarizes the selection of pin function.
CAP0.2, CAP1.1, CAP1.2
CAP1.3, CAP3.0
From CapTIvate
P2REN.x
P2DIR.x
00
01
From Module1
10
11
2 bit
DVSS
DVCC
0
1
00
01
P2OUT.x
From Module1
10
11
DVSS
DVSS
2 bit
P2SEL.x
EN
D
To module
P2IN.x
P2IE.x
Bus
Keeper
P2 Interrupt
D
S
Q
P2.3/CAP0.2
P2.4/UCA1CLK/CAP1.1
P2.5/UCA1RXD/UCA1SOMI/CAP1.2
P2.6/UCA1TXD/UCA1SIMO/CAP1.3
P2.7/CAP3.0
P2IFG.x
P2IES.x
Edge
Select
Figure 6-3. Port P2 (P2.3 to P2.7) Input/Output With Schmitt Trigger
64
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Table 6-19. Port P2 (P2.3 to P2.7) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
ANALOG
FUNCTION
P2DIR.x
P2SELx
3
P2.3 (I/O)
CAP0.2
I: 0; O: 1
00
X
0
1
0
0
1
0
0
1
0
0
1
0
1
P2.3/CAP0.2
X
P2.4 (I/O)
UCA1CLK
CAP1.1
I: 0; O: 1
00
01
X
P2.4/UCA1CLK/
CAP1.1
4
5
X
X
P2.5 (I/O)
I: 0; O: 1
00
01
X
P2.5/UCA1RXD/
UCA1SOMI/CAP1.2
UCA1RXD/UCA1SOMI
CAP1.2
X
X
P2.6 (I/O)
I: 0; O: 1
00
01
X
P2.6/UCA1TXD/
UCA1SIMO/CAP1.3
6
7
UCA1TXD/UCA1SIMO
CAP1.3
X
X
I: 0; O: 1
X
P2.7 (I/O)
0
P2.7/CAP3.0
CAP3.0
X
(1) X = don't care
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6.11.4 Port P3 (P3.0 to P3.2) Input/Output With Schmitt Trigger
Figure 6-4 shows the port diagram. Table 6-20 summarizes the selection of pin function.
CAP0.0, CAP1.0, CAP3.2
From CapTIvate
P3REN.x
P3DIR.x
00
01
From Module1
10
11
2 bit
DVSS
DVCC
0
1
00
01
P3OUT.x
From Module1
10
11
DVSS
DVSS
2 bit
P3SEL.x
EN
D
To module
P3IN.x
Bus
Keeper
P3.0/CAP0.0
P3.1/UCA1STE/CAP1.0
P3.2/CAP3.2
Figure 6-4. Port P3 (P3.0 to P3.2) Input/Output With Schmitt Trigger
NOTE
CapTIvate shared with I/Os configuration
The CapTIvate function and GPIOs are powered by different power supplies (1.5 V and
3.3 V, respectively).
To prevent pad damage when changing the function, TI recommends checking the external
application circuit of each pad before enabling the alternate function.
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ZHCSET6E –NOVEMBER 2015–REVISED DECEMBER 2019
Table 6-20. Port P3 (P3.0 to P3.2) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P3.x)
x
FUNCTION
ANALOG
FUNCTION
P3DIR.x
P3SEL.x
P3.0 (I/O)
CAP0.0
I: 0; O: 1
00
X
0
1
0
0
1
0
1
P3.0/CAP0.0
0
X
P3.1 (I/O)
UCA1STE
CAP1.0
I: 0; O: 1
00
01
X
P3.1/UCA1STE/
CAP1.0
1
2
X
X
I: 0; O: 1
X
P3.2 (I/O)
CAP3.2
00
X
P3.2/CAP3.2
(1) X = don't care
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6.12 Device Descriptors
Table 6-21 lists the Device IDs of the devices. Table 6-22 lists the contents of the device descriptor tag-
length-value (TLV) structure for the devices.
Table 6-21. Device IDs
DEVICE ID
DEVICE
1A05h
82h
1A04h
3Ch
MSP430FR2633
MSP430FR2533
MSP430FR2632
MSP430FR2532
82h
3Dh
82h
3Eh
82h
3Fh
Table 6-22. Device Descriptors
MSP430FR2633, MSP430FR2632,
MSP430FR2533, MSP430FR2532
DESCRIPTION
ADDRESS
1A00h
1A01h
1A02h
1A03h
1A04h
1A05h
1A06h
1A07h
1A08h
1A09h
1A0Ah
1A0Bh
1A0Ch
1A0Dh
1A0Eh
1A0Fh
1A10h
1A11h
1A12h
1A13h
1A14h
1A15h
1A16h
1A17h
1A18h
1A19h
1A1Ah
1A1Bh
1A1Ch
1A1Dh
VALUE
06h
Info length
CRC length
06h
Per unit
Per unit
CRC value(1)
Information Block
Device ID
See Table 6-21.
Hardware revision
Firmware revision
Die record tag
Per unit
Per unit
08h
Die record length
0Ah
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Lot wafer ID
Die Record
Die X position
Die Y position
Test result
ADC calibration tag
ADC calibration length
ADC gain factor
ADC Calibration
ADC offset
ADC 1.5-V reference temperature 30°C
ADC 1.5-V reference temperature 85°C
(1) The CRC value covers the checksum from 0x1A04h to 0x1AF5h by applying the CRC-CCITT-16 polynomial of x16 + x12 + x5 + 1.
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Table 6-22. Device Descriptors (continued)
MSP430FR2633, MSP430FR2632,
MSP430FR2533, MSP430FR2532
DESCRIPTION
ADDRESS
1A1Eh
1A1Fh
1A20h
VALUE
12h
Calibration tag
Calibration length
04h
Per unit
Per unit
Per unit
Per unit
Reference and DCO Calibration 1.5-V reference factor
DCO tap setting for 16 MHz, temperature 30°C(2)
1A21h
1A22h
1A23h
(2) This value can be directly loaded into DCO bits in CSCTL0 registers to get accurate 16-MHz frequency at room temperature, especially
when the MCU exits from LPM3 and below. TI suggests using the predivider to decrease the frequency if the temperature drift might
result an overshoot beyond 16 MHz.
6.13 Memory
6.13.1 Memory Organization
Table 6-23 summarizes the memory map of the devices.
Table 6-23. Memory Organization
ACCESS
MSP430FR2633
MSP430FR2632
MSP430FR2533
MSP430FR2532
Memory (FRAM)
Main: interrupt vectors and
signatures
Read/Write
(Optional Write
Protect)(1)
15KB
FFFFh to FF80h
FFFFh to C400h
8KB
FFFFh to FF80h
FFFFh to E000h
15KB
FFFFh to FF80h
FFFFh to C400h
8KB
FFFFh to FF80h
FFFFh to E000h
Main: code memory
4KB
2FFFh to 2000h
2KB
27FFh to 2000h
2KB
27FFh to 2000h
1KB
23FFh to 2000h
RAM
Read/Write
Read/Write
(Optional Write
Protect)(2)
512 bytes
19FFh to 1800h
512 bytes
19FFh to 1800h
512 bytes
19FFh to 1800h
512 bytes
19FFh to 1800h
Information Memory (FRAM)
Bootstrap loader (BSL1)
Memory (ROM)
2KB
17FFh to 1000h
2KB
17FFh to 1000h
2KB
17FFh to 1000h
2KB
17FFh to 1000h
Read only
Read only
Read only
Read/Write
Bootstrap loader (BSL2)
Memory (ROM)
1KB
1KB
1KB
1KB
FFFFFh to FFC00h FFFFFh to FFC00h FFFFFh to FFC00h FFFFFh to FFC00h
CapTIvate Libraries and
Driver Libraries (ROM)
12KB
6FFFh to 4000h
12KB
6FFFh to 4000h
12KB
6FFFh to 4000h
12KB
6FFFh to 4000h
4KB
0FFFh to 0000h
4KB
0FFFh to 0000h
4KB
0FFFh to 0000h
4KB
0FFFh to 0000h
Peripherals
(1) The Program FRAM can be write protected by setting the PFWP bit in the SYSCFG0 register. See the SYS chapter in the
MSP430FR4xx and MSP430FR2xx Family User's Guide for more details.
(2) The Information FRAM can be write protected by setting the DFWP bit in the SYSCFG0 register. See the SYS chapter in the
MSP430FR4xx and MSP430FR2xx Family User's Guide for more details.
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6.13.2 Peripheral File Map
Table 6-24 lists the available peripherals and the register base address for each. Table 6-25 to list the
registers and address offsets for each peripheral.
Table 6-24. Peripherals Summary
MODULE NAME
Special Functions (See Table 6-25)
BASE ADDRESS
0100h
SIZE
0010h
0020h
0040h
0020h
0010h
0008h
0002h
0020h
0020h
0010h
0030h
0030h
0030h
0030h
0030h
0020h
0020h
0030h
0020h
0040h
0200h
PMM (See Table 6-26)
0120h
SYS (See Table 6-27)
0140h
CS (See Table 6-28)
0180h
FRAM (See Table 6-29)
01A0h
01C0h
01CCh
0200h
CRC (See Table 6-30)
WDT (See Table 6-31)
Port P1, P2 (See Table 6-32)
Port P3 (See Table 6-33)
RTC (See Table 6-34)
0220h
0300h
Timer0_A3 (See Table 6-35)
Timer1_A3 (See Table 6-36)
Timer2_A2 (See Table 6-37)
Timer3_A2 (See Table 6-38)
MPY32 (See Table 6-39)
eUSCI_A0 (See Table 6-40)
eUSCI_A1 (See Table 6-41)
eUSCI_B0 (See Table 6-42)
Backup Memory (See Table 6-43)
ADC (See Table 6-44)
0380h
03C0h
0400h
0440h
04C0h
0500h
0520h
0540h
0660h
0700h
CapTIvate (See CapTivate Design Center for details)
0A00h
Table 6-25. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
ACRONYM
SFRIE1
OFFSET
00h
SFR interrupt enable
SFR interrupt flag
SFRIFG1
SFRRPCR
02h
SFR reset pin control
04h
Table 6-26. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
ACRONYM
PMMCTL0
PMMCTL1
PMMCTL2
PMMIFG
OFFSET
00h
PMM control 0
PMM control 1
PMM control 2
PMM interrupt flags
PM5 control 0
02h
04h
0Ah
PM5CTL0
10h
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Table 6-27. SYS Registers (Base Address: 0140h)
REGISTER DESCRIPTION
ACRONYM
SYSCTL
OFFSET
00h
System control
Bootloader configuration area
JTAG mailbox control
SYSBSLC
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSBERRIV
SYSUNIV
SYSSNIV
02h
06h
JTAG mailbox input 0
08h
JTAG mailbox input 1
0Ah
0Ch
0Eh
18h
JTAG mailbox output 0
JTAG mailbox output 1
Bus error vector generator
User NMI vector generator
System NMI vector generator
Reset vector generator
System configuration 0
System configuration 1
System configuration 2
1Ah
1Ch
1Eh
20h
SYSRSTIV
SYSCFG0
SYSCFG1
SYSCFG2
22h
24h
Table 6-28. CS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
ACRONYM
CSCTL0
CSCTL1
CSCTL2
CSCTL3
CSCTL4
CSCTL5
CSCTL6
CSCTL7
CSCTL8
OFFSET
00h
CS control 0
CS control 1
CS control 2
CS control 3
CS control 4
CS control 5
CS control 6
CS control 7
CS control 8
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
Table 6-29. FRAM Registers (Base Address: 01A0h)
REGISTER DESCRIPTION
ACRONYM
FRCTL0
OFFSET
00h
FRAM control 0
General control 0
General control 1
GCCTL0
GCCTL1
04h
06h
Table 6-30. CRC Registers (Base Address: 01C0h)
REGISTER DESCRIPTION
ACRONYM
CRC16DI
OFFSET
00h
CRC data input
CRC data input reverse byte
CRC initialization and result
CRC result reverse byte
CRCDIRB
CRCINIRES
CRCRESR
02h
04h
06h
Table 6-31. WDT Registers (Base Address: 01CCh)
REGISTER DESCRIPTION
ACRONYM
OFFSET
Watchdog timer control
WDTCTL
00h
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Table 6-32. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
ACRONYM
P1IN
OFFSET
Port P1 input
00h
02h
04h
06h
0Ah
0Ch
0Eh
16h
18h
1Ah
1Ch
01h
03h
05h
07h
0Bh
0Dh
1Eh
17h
19h
1Bh
1Dh
Port P1 output
Port P1 direction
P1OUT
P1DIR
P1REN
P1SEL0
P1SEL1
P1IV
Port P1 pulling enable
Port P1 selection 0
Port P1 selection 1
Port P1 interrupt vector word
Port P1 complement selection
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
P1SELC
P1IES
P1IE
P1IFG
P2IN
Port P2 output
P2OUT
P2DIR
P2REN
P2SEL0
P2SEL1
P2IV
Port P2 direction
Port P2 pulling enable
Port P2 selection 0
Port P2 selection 1
Port P2 interrupt vector word
Port P2 complement selection
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
P2SELC
P2IES
P2IE
P2IFG
Table 6-33. Port P3 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
ACRONYM
P3IN
OFFSET
00h
02h
04h
06h
0Ah
0
Port P3 input
Port P3 output
P3OUT
P3DIR
Port P3 direction
Port P3 pulling enable
Port P3 selection 0
Port P3 selection 1
Port P3 complement selection
P3REN
P3SEL0
P3SEL1
P3SELC
16h
Table 6-34. RTC Registers (Base Address: 0300h)
REGISTER DESCRIPTION
ACRONYM
RTCCTL
RTCIV
OFFSET
00h
RTC control
RTC interrupt vector
RTC modulo
04h
RTCMOD
RTCCNT
08h
RTC counter
0Ch
72
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Table 6-35. Timer0_A3 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
00h
TA0 control
TA0CTL
TA0CCTL0
TA0CCTL1
TA0CCTL2
TA0R
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA0 counter
02h
04h
06h
10h
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA0 expansion 0
TA0CCR0
TA0CCR1
TA0CCR2
TA0EX0
12h
14h
16h
20h
TA0 interrupt vector
TA0IV
2Eh
Table 6-36. Timer1_A3 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
ACRONYM
TA1CTL
OFFSET
00h
TA1 control
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA1 counter
TA1CCTL0
TA1CCTL1
TA1CCTL2
TA1R
02h
04h
06h
10h
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA1 expansion 0
TA1CCR0
TA1CCR1
TA1CCR2
TA1EX0
12h
14h
16h
20h
TA1 interrupt vector
TA1IV
2Eh
Table 6-37. Timer2_A2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
ACRONYM
TA2CTL
OFFSET
00h
TA2 control
Capture/compare control 0
Capture/compare control 1
TA2 counter
TA2CCTL0
TA2CCTL1
TA2R
02h
04h
10h
Capture/compare 0
Capture/compare 1
TA2 expansion 0
TA2CCR0
TA2CCR1
TA2EX0
12h
14h
20h
TA2 interrupt vector
TA2IV
2Eh
Table 6-38. Timer3_A2 Registers (Base Address: 0440h)
REGISTER DESCRIPTION
ACRONYM
TA3CTL
OFFSET
00h
TA3 control
Capture/compare control 0
Capture/compare control 1
TA3 counter
TA3CCTL0
TA3CCTL1
TA3R
02h
04h
10h
Capture/compare 0
Capture/compare 1
TA3 expansion 0
TA3CCR0
TA3CCR1
TA3EX0
12h
14h
20h
TA3 interrupt vector
TA3IV
2Eh
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Table 6-39. MPY32 Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
16-bit operand 1 – multiply
ACRONYM
MPY
OFFSET
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
16-bit operand 1 – signed multiply
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
MPYS
MAC
MACS
OP2
16 × 16 result low word
RESLO
RESHI
16 × 16 result high word
16 × 16 sum extension
SUMEXT
MPY32L
MPY32H
MPYS32L
MPYS32H
MAC32L
MAC32H
MACS32L
MACS32H
OP2L
32-bit operand 1 – multiply low word
32-bit operand 1 – multiply high word
32-bit operand 1 – signed multiply low word
32-bit operand 1 – signed multiply high word
32-bit operand 1 – multiply accumulate low word
32-bit operand 1 – multiply accumulate high word
32-bit operand 1 – signed multiply accumulate low word
32-bit operand 1 – signed multiply accumulate high word
32-bit operand 2 – low word
32-bit operand 2 – high word
OP2H
32 × 32 result 0 – least significant word
32 × 32 result 1
RES0
RES1
32 × 32 result 2
RES2
32 × 32 result 3 – most significant word
MPY32 control 0
RES3
MPY32CTL0
Table 6-40. eUSCI_A0 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
ACRONYM
UCA0CTLW0
UCA0CTLW1
UCA0BR0
OFFSET
00h
eUSCI_A control word 0
eUSCI_A control word 1
eUSCI_A control rate 0
eUSCI_A control rate 1
eUSCI_A modulation control
eUSCI_A status
02h
06h
UCA0BR1
07h
UCA0MCTLW
UCA0STAT
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
lUCA0IRTCTL
IUCA0IRRCTL
UCA0IE
08h
0Ah
0Ch
0Eh
10h
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
12h
13h
1Ah
1Ch
1Eh
UCA0IFG
UCA0IV
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Table 6-41. eUSCI_A1 Registers (Base Address: 0520h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
00h
eUSCI_A control word 0
eUSCI_A control word 1
eUSCI_A control rate 0
eUSCI_A control rate 1
eUSCI_A modulation control
eUSCI_A status
UCA1CTLW0
UCA1CTLW1
UCA1BR0
02h
06h
UCA1BR1
07h
UCA1MCTLW
UCA1STAT
UCA1RXBUF
UCA1TXBUF
UCA1ABCTL
lUCA1IRTCTL
IUCA1IRRCTL
UCA1IE
08h
0Ah
0Ch
0Eh
10h
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
12h
13h
1Ah
1Ch
1Eh
UCA1IFG
UCA1IV
Table 6-42. eUSCI_B0 Registers (Base Address: 0540h)
REGISTER DESCRIPTION
ACRONYM
UCB0CTLW0
UCB0CTLW1
UCB0BR0
OFFSET
00h
eUSCI_B control word 0
eUSCI_B control word 1
eUSCI_B bit rate 0
02h
06h
eUSCI_B bit rate 1
UCB0BR1
07h
eUSCI_B status word
UCB0STATW
UCB0TBCNT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA0
UCB0I2COA1
UCB0I2COA2
UCB0I2COA3
UCB0ADDRX
UCB0ADDMASK
UCB0I2CSA
UCB0IE
08h
eUSCI_B byte counter threshold
eUSCI_B receive buffer
eUSCI_B transmit buffer
eUSCI_B I2C own address 0
eUSCI_B I2C own address 1
eUSCI_B I2C own address 2
eUSCI_B I2C own address 3
eUSCI_B receive address
eUSCI_B address mask
eUSCI_B I2C slave address
eUSCI_B interrupt enable
eUSCI_B interrupt flags
eUSCI_B interrupt vector word
0Ah
0Ch
0Eh
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Ah
2Ch
2Eh
UCB0IFG
UCB0IV
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Table 6-43. Backup Memory Registers (Base Address: 0660h)
REGISTER DESCRIPTION
ACRONYM
BAKMEM0
BAKMEM1
BAKMEM2
BAKMEM3
BAKMEM4
BAKMEM5
BAKMEM6
BAKMEM7
BAKMEM8
BAKMEM9
BAKMEM10
BAKMEM11
BAKMEM12
BAKMEM13
BAKMEM14
BAKMEM15
OFFSET
Backup memory 0
Backup memory 1
Backup memory 2
Backup memory 3
Backup memory 4
Backup memory 5
Backup memory 6
Backup memory 7
Backup memory 8
Backup memory 9
Backup memory 10
Backup memory 11
Backup memory 12
Backup memory 13
Backup memory 14
Backup memory 15
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
Table 6-44. ADC Registers (Base Address: 0700h)
REGISTER DESCRIPTION
ACRONYM
ADCCTL0
ADCCTL1
ADCCTL2
ADCLO
OFFSET
00h
ADC control 0
ADC control 1
02h
ADC control 2
04h
ADC window comparator low threshold
ADC window comparator high threshold
ADC memory control 0
ADC conversion memory
ADC interrupt enable
06h
ADCHI
08h
ADCMCTL0
ADCMEM0
ADCIE
0Ah
12h
1Ah
1Ch
1Eh
ADC interrupt flags
ADCIFG
ADC interrupt vector word
ADCIV
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6.14 Identification
6.14.1 Revision Identification
The device revision information is included as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings (see 节 8.4).
The hardware revision is also stored in the Device Descriptor structure in the Information Block section.
For details on this value, see the Hardware Revision entries in Table 6-22.
6.14.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings (see 节 8.4).
A device identification value is also stored in the Device Descriptor structure in the Information Block
section. For details on this value, see the Device ID entries in Table 6-22.
6.14.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
MSP430 Programming With the JTAG Interface.
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7 Applications, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
7.1 Device Connection and Layout Fundamentals
This section discusses the recommended guidelines when designing with the MSP430 devices. These
guidelines are to make sure that the device has proper connections for powering, programming,
debugging, and optimum analog performance.
7.1.1 Power Supply Decoupling and Bulk Capacitors
TI recommends connecting a combination of a 10-µF and a 100-nF low-ESR ceramic decoupling capacitor
to the DVCC and DVSS pins (see Figure 7-1). Higher-value capacitors may be used but can impact
supply rail ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they
decouple (within a few millimeters). Additionally, TI recommends separated grounds with a single-point
connection for better noise isolation from digital-to-analog circuits on the board and to achieve high analog
accuracy.
DVCC
Digital
+
Power Supply
Decoupling
DVSS
10 µF
100 nF
Figure 7-1. Power Supply Decoupling
7.1.2 External Oscillator
This device supports only a low-frequency crystal (32 kHz) on the XIN and XOUT pins. External bypass
capacitors for the crystal oscillator pins are required.
It is also possible to apply digital clock signals to the XIN input pin that meet the specifications of the
respective oscillator if the appropriate XT1BYPASS mode is selected. In this case, the associated XOUT
pin can be used for other purposes. If the XIN and XOUT pins are not used, they must be terminated
according to Section 4.6.
Figure 7-2 shows a typical connection diagram.
XIN
XOUT
CL1
CL2
Figure 7-2. Typical Crystal Connection
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See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal
oscillator with the MSP430 devices.
7.1.3 JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or
MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the
connections also support the MSP-GANG production programmers, thus providing an easy way to
program prototype boards, if desired. Figure 7-3 shows the connections between the 14-pin JTAG
connector and the target device required to support in-system programming and debugging for 4-wire
JTAG communication. Figure 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are
identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSP-
FET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an
alternate connection (pin 4 instead of pin 2). The VCC sense feature detects the local VCC present on the
target board (that is, a battery or other local power supply) and adjusts the output signals accordingly.
Figure 7-3 and Figure 7-4 show a jumper block that supports both scenarios of supplying VCC to the target
board. If this flexibility is not required, the desired VCC connections may be hard-wired to eliminate the
jumper block. Pins 2 and 4 must not be connected at the same time.
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User's
Guide.
VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
DVCC
J2 (see Note A)
R1
47 kW
JTAG
RST/NMI/SBWTDIO
VCC TOOL
TDO/TDI
TDI
TDO/TDI
TDI
2
1
VCC TARGET
4
3
TMS
TMS
6
5
7
TEST
TCK
8
TCK
GND
RST
10
12
14
9
11
13
TEST/SBWTCK
DVSS
C1
1 nF
(see Note B)
A. If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,
make connection J2.
B. The upper limit for C1 is 1.1 nF when using current TI tools.
Figure 7-3. Signal Connections for 4-Wire JTAG Communication
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VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
J2 (see Note A)
DVCC
R1
47 kΩ
(see Note B)
JTAG
VCC TOOL
TDO/TDI
2
1
3
5
7
9
RST/NMI/SBWTDIO
VCC TARGET
4
6
TCK
8
GND
10
12
14
11
13
TEST/SBWTCK
DVSS
C1
1 nF
(see Note B)
A. Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the
debug or programming adapter.
B. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with
the device. The upper limit for C1 is 1.1 nF when using current TI tools.
Figure 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
7.1.4 Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function
Register (SFR), SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is
edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the
external NMI. When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either
pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.
If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an
external 47-kΩ pullup resistor to the RST/NMI pin with a 1.1-nF pulldown capacitor. The pulldown
capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or
in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers.
See the MSP430FR4xx and MSP430FR2xx Family User's Guide for more information on the referenced
control registers and bits.
7.1.5 Unused Pins
For details on the connection of unused pins, see Section 4.6.
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7.1.6 General Layout Recommendations
•
Proper grounding and short traces for external crystal to reduce parasitic capacitance. For
recommended layout guidelines, see MSP430 32-kHz Crystal Oscillators.
•
•
Proper bypass capacitors on DVCC and reference pins, if used.
Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital
switching signals such as PWM or JTAG signals away from the oscillator circuit and ADC signals.
•
Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. For guidelines see MSP430 System-Level ESD Considerations.
7.1.7 Do's and Don'ts
During power up, power down, and device operation, DVCC must not exceed the limits specified in
Section 5.1. Exceeding the specified limits may cause malfunction of the device including erroneous writes
to RAM and FRAM.
7.2 Peripheral- and Interface-Specific Design Information
7.2.1 ADC Peripheral
7.2.1.1 Partial Schematic
Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used.
DVSS
Using an external
VREF+/VEREF+
positive reference
+
100 nF
10 µF
Using an external
negative reference
VEREF-
+
10 µF
100 nF
Figure 7-5. ADC Grounding and Noise Considerations
7.2.1.2 Design Requirements
As with any high-resolution ADC, appropriate PCB layout and grounding techniques must be followed to
eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with
other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset
voltages that can add to or subtract from the reference or input voltages of the ADC. The general
guidelines in Section 7.1.1 combined with the connections shown in Figure 7-5 prevent this.
Quickly switching digital signals and noisy power supply lines can corrupt the conversion results, so keep
the ADC input trace shielded from those digital and power supply lines. Putting the MCU in low-power
mode during the ADC conversion improves the ADC performance in a noisy environment. If the device
includes the analog power pair inputs (AVCC and AVSS), TI recommends a noise-free design using
separate analog and digital ground planes with a single-point connection to achieve high accuracy.
Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The
internal reference module has a maximum drive current as described in the sections ADC Pin Enable and
1.2-V Reference Settings of the MSP430FR4xx and MSP430FR2xx Family User's Guide.
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The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are
selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage
enters the device. In this case, the 10-µF capacitor buffers the reference pin and filters any low-frequency
ripple. A bypass capacitor of 100 nF filters out any high-frequency noise.
7.2.1.3 Layout Guidelines
Components that are shown in the partial schematic (see Figure 7-5) should be placed as close as
possible to the respective device pins to avoid long traces, because they add additional parasitic
capacitance, inductance, and resistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),
because the high-frequency switching can be coupled into the analog signal.
7.2.2 CapTIvate Peripheral
This section provides a brief introduction to the CapTIvate technology with examples of PCB layout and
performance from the design kit. A more detailed description of the CapTIvate technology and the tools
needed to be successful, application development tools, hardware design guides, and software library,
can be found in the CapTIvate™ Technology Guide.
7.2.2.1 Device Connection and Layout Fundamentals
To learn more on how to design the CapTIvate Technology, see the Capacitive Touch Design Flow for
MSP430™ MCUs With CapTIvate™ Technology application report.
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7.2.2.2 Measurements
The following measurements are taken from the CapTIvate Technology Design Center, using the
CAPTIVATE-PHONE and CAPTIVATE-BSWP panels. Unless otherwise stated, the settings used are the
out-of-box settings, which can be found in the example projects. The intent of these measurements is to
show performance in a configuration that is readily available and reproducible.
Figure 7-6. CAPTIVATE-PHONE and CAPTIVATE-BSWP Panels
7.2.2.2.1 SNR
The Sensitivity, SNR, and Design Margin in Capacitive Touch Applications application report provides a
specific view for analyzing the signal-to-noise ratio of each element.
7.2.2.2.2 Sensitivity
To show sensitivity, in terms of farads, the internal reference capacitor is used as the change in
capacitance. In the mutual-capacitance case, the 0.1-pF capacitor is used. In the self-capacitance case,
the 1-pF reference capacitor is used. For simplicity, the results for only button 1 on both the CAPTIVATE-
PHONE and CAPTIVATE-BSWP panels are reported in Table 7-1.
Table 7-1. Button Sensitivity
CAPTIVATE-PHONE BUTTON 1 CAPTIVATE-BSWP BUTTON 1
CONVERSION CONVERSION
COUNTS FOR
0.1-pF
CHANGE
CONVERSION
TIME (µs)
CONVERSION COUNTS FOR
COUNT
GAIN
TIME (µs)
1-pF CHANGE
100
200
200
800
800
800
100
200
100
400
200
100
25
50
6
50
8
10
100
100
400
400
400
16
50
21
31
200
200
200
70
112
202
333
140
257
An alternative measure in sensitivity is the ability to resolve capacitance change over a wide range of base
capacitance. Table 7-2 shows example conversion times (for a self-mode measurement of discrete
capacitors) that can be used to achieve the desired resolution for a given parasitic load capacitance.
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Table 7-2. Button Sensitivity
CAPACITANCE, Cp
(pF)(1)
CONVERSION
COUNT/GAIN
CONVERSION TIME
(µs)
COUNTS FOR
0.130-pF CHANGE
COUNTS FOR
0.260-pF CHANGE
COUNTS FOR
0.520-pF CHANGE
23
50
400/100
550/100
650/100
850/100
1200/200
1200/150
200
275
325
425
600
600
10
11
11
11
11
13
23
24
23
22
23
26
35
37
36
35
37
41
78
150
150(2)
200(2)
(1) These measurements were taken with the CapTIvate MCU processor board with the 470-Ω series resistors replaced with 0-Ω resistors.
(2) 0-V discharge voltage is used.
7.2.2.2.3 Power
The low-power mode LPM3 specifications in Section 5.7 are derived from the CapTIvate technology
design kit as indicated in the notes.
7.3 CapTIvate Technology Evaluation
Table 7-3 lists tools that demonstrate the use of the MSP430FR263x devices. See CapTIvate Evaluation
Tools to get started with evaluating the CapTIvate technology in various real-world application scenarios.
Consult these evaluation tool designs for additional guidance regarding schematics, layout, and software
implementation.
Table 7-3. Evaluation Tools
NAME
MSP CapTIvate MCU Development Kit
Capacitive Touch Thermostat User Interface Reference Design
LINK
http://www.ti.com/tool/msp-capt-fr2633
http://www.ti.com/tool/tidm-captivate-thermostat-ui
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8 器件和文档支持
8.1 入门和后续步骤
更过有关 MSP 低功耗微控制器以及开发协助工具和库的信息，请访问《MSP430™ 超低功耗传感和测量
MCU 概述》。
8.2 器件命名规则
为了标示产品开发周期所处的阶段，TI 为所有 MSP MCU 器件的部件号分配了前缀。每个 MSP MCU 商用
系列产品成员都具有以下两个前缀之一：MSP 或 XMS。这些前缀代表了产品开发的发展阶段，即从工程原
型 (XMS) 直到完全合格的生产器件 (MSP)。
XMS - 实验器件，不一定代表最终器件的电气规格
MSP - 完全合格的生产器件
XMS 器件在供货时附带如下免责声明：
“开发中的产品用于内部评估用途。”
MSP 器件的特性已经全部明确，并且器件的质量和可靠性已经完全论证。TI 的标准保修证书对该器件适
用。
预测显示原型器件 (XMS) 的故障率大于标准生产器件。由于这些器件的预计最终使用故障率尚不确定，德
州仪器 (TI) 建议不要将它们用于任何生产系统。请仅使用合格的生产器件。
TI 器件的命名规则还包括一个带有器件系列名称的后缀。此后缀表示温度范围、封装类型和配送形式。图 8-
1 提供了解读完整器件名称的图例。
MSP 430 FR 2 633 I RHB R
Distribution Format
Packaging
Temperature Range
Feature Set
Processor Family
MCU Platform
Memory Type
Series
MSP = Mixed-signal processor
XMS = Experimental silicon
Processor Family
MCU Platform
430 = MSP430 16-bit low-power platform
FR = FRAM
Memory Type
Series
2 = Up to 16 MHz without LCD
Feature Set
(see note)
CapTIvate Performance
633 = 4 CapTIvate blocks, 16KB of FRAM, 4KB of SRAM, up to 16 CapTIvate I/Os
533 = 4 CapTIvate blocks, 16KB of FRAM, 2KB of SRAM, up to 16 CapTIvate I/Os
632 = 4 CapTIvate blocks, 8KB of FRAM, 2KB of SRAM, up to 8 CapTIvate I/Os
532 = 4 CapTIvate blocks, 8KB of FRAM, 1KB of SRAM, up to 8 CapTIvate I/Os
I = –40°C to 85°C
Temperature Range
Packaging
www.ti.com/packaging
T = Small reel
R = Large reel
No marking = Tube or tray
Distribution Format
NOTE: 有关采用 CapTIvate 触控技术的器件的更多指导，请参阅《CapTIvate 技术指南》中的器件选择基准。
图 8-1. 器件命名规则
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产品主页链接: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532
MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532
ZHCSET6E –NOVEMBER 2015–REVISED DECEMBER 2019
www.ti.com.cn
8.3 工具和软件
所有 MSP 微控制器均受多种软件和硬件开发工具的支持。相关工具由 TI 以及多家第三方供应商提供。可从
低功耗 MCU 开发套件和软件获取全部信息。
表 8-1 列 调试 的调试功能。请参阅《适用于 MSP430 MCU 的 Code Composer Studio IDE 用户指南》，
以了解有关可用 功能）的详细信息。
表 8-1. 硬件调试 特性
四线制
JTAG
两线制
JTAG
断点
(N)
LPMx.5 调试支
持
MSP430 架构
范围断点
有
时钟控制
是
状态序列发生器
否
跟踪缓冲器
否
EEM 版本
MSP430Xv2
有
有
3
否
S
设计套件与评估模块
MSP CapTIvate MCU 开发套件
MSP CapTIvate MCU 开发套件是一种用于评估采用电容式触控技术的 MSP430FR2633 微控制器的易用综
合性平台。此套件包含基于 MSP430FR2633 的处理器板、采用 EnergyTrace 技术的编程器和调试器板（用
于通过 Code Composer Studio IDE 测量能耗），以及用于评估自电容、互电容、手势和接近传感的传感器
板。
软件
MSP430Ware 软件
MSP430Ware 是一套设计资源集，可帮助用户高效地创建和构建 MSP430 代码。MSP430Ware 包括各种
高度抽象的软件库，范围涵盖 MSP 驱动程序库或 USB 等特定于器件和外设的库，以及图形库和电容式触
控库等特定于应用的库。MSP430 驱动程序库是一个尤为重要的库，可以帮助软件开发人员利用便捷的 API
来控制错综复杂的低级别硬件外设，从而使生成的代码更易于读取和维护。
MSP430FR243x、MSP430FR253x、MSP430FR263x 代码示例
根据不同应用需求配置各集成外设的每个 MSP 器件均具备相应的 C 代码示例。
MSP 驱动程序库
MSP 驱动程序库的抽象 API 提供易用的函数调用，无需直接操纵 MSP430 硬件的位与字节。完整的文档通
过具有帮助意义的 API 指南交付，其中包括有关每个函数调用和经过验证的参数的详细信息。开发人员可以
使用驱动程序库功能，以最低开销编写完整项目。
MSP EnergyTrace™ 技术
适用于 MSP430 微控制器的 EnergyTrace 技术是基于电能的代码分析工具，适用于测量和显示应用的电能
系统配置并帮助优化应用以实现超低功耗。
ULP（超低功耗）Advisor
ULP Advisor™软件是一款辅助工具，旨在指导开发人员编写更为高效的代码，从而充分利用 MSP430 和
MSP432 微控制器 独特 功能。ULP Advisor 的目标人群是微控制器的资深开发者和开发新手，可以根据详
尽的 ULP 检验表检查代码，以便最大限度地减少应用程序的能耗。在编译时，ULP Advisor 会提供通知和
备注以突出显示代码中可以进一步优化的区域，进而实现更低功耗。
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www.ti.com.cn
ZHCSET6E –NOVEMBER 2015–REVISED DECEMBER 2019
IEC60730 软件包
IEC60730 MSP430 软件包经过专门开发，用于协助客户达到 IEC 60730-1:2010（家用及类似用途的自动化
电气控制 - 第 1 部分：一般要求）B 类产品的要求。其中涵盖家用电器、电弧检测器、电源转换器、电动工
具、电动自行车及其他诸多产品。IEC60730 MSP430 软件包可以嵌入在 MSP430 MCU 中 运行的客户应
用， 从而帮助客户简化其消费类器件在功能安全方面遵循 IEC 60730-1:2010 B 类规范的认证工作。
适用于 MSP 的定点数学库
MSP IQmath 和 Qmath 库是为 C 语言编程器提供的经过高度优化的高精度数学运算函数集合，能够将浮点
算法无缝嵌入 MSP430 和 MSP432 器件的定点代码中。这些例程通常用于计算密集型实时 应用， 而优化
的执行速度、高精度以及超低能耗通常是影响这些实时应用的关键因素。与使用浮点数学算法编写的同等代
码相比，使用 IQmath 和 Qmath 库可以大幅提高执行速度并显著降低能耗。
适用于 MSP430 的浮点数学库
TI 在低功耗和低成本微控制器领域锐意创新，为您提供 MSPMATHLIB。此标量函数的浮点数学库，能够充
分利用器件的智能外设，使速度最高达到标准 MSP430 数学函数的 26 倍。Mathlib 能够轻松集成到您的设
计中。该运算库免费使用并集成在 Code Composer Studio IDE 和 IAR Embedded Workbench IDE 中。
开发工具
适用于 MSP 微控制器的 Code Composer Studio™ 集成开发环境
Code Composer Studio (CCS) 集成开发环境 (IDE) 支持所有 MSP 微控制器器件。CCS 包含一整套用于开
发和调试嵌入式 应用的工具。它包含了优化的 C/C++ 编译器、源代码编辑器、项目构建环境、调试器、描
述器以及其他多种 功能。
命令行编程器
MSP Flasher 是一款基于 shell 的开源接口，可使用 JTAG 或 Spy-Bi-Wire (SBW) 通信通过 FET 编程器或
eZ430 对 MSP 微控制器进行编程。MSP Flasher 可用于将二进制文件（.txt 或 .hex 文件）直接下载到
MSP 微控制器，而无需使用 IDE。
MSP MCU 编程器和调试器
MSP-FET 是一款强大的仿真开发工具（通常称为调试探针），可让用户在 MSP 低功耗微控制器 (MCU) 上
快速进行应用开发。创建 MCU 软件通常需要将生成的二进制程序下载到 MSP 器件，以进行验证和调试。
MSP-FET 在主机和目标 MSP 间提供调试通信通道。此外，MSP-FET 还在计算机的 USB 接口和 MSP
UART 之间提供反向通道 UART 连接。这为 MSP 编程器提供了一种便捷方法，实现了 MSP 和在计算机上
运行的终端之间的串行通信。
MSP-GANG 生产编程器
MSP Gang 编程器可同时对多达八个完全相同的 MSP430 或 MSP432 闪存或 FRAM 器件进行编程。MSP
Gang 编程器可使用标准的 RS-232 或 USB 连接与主机 PC 相连并提供灵活的编程选项，允许用户完全自定
义流程。MSP Gang 编程器配有扩展板“Gang 分离器”，可在 MSP Gang 编程器和多个目标器件间实现互
连。
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产品主页链接: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532
MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532
ZHCSET6E –NOVEMBER 2015–REVISED DECEMBER 2019
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8.4 文档支持
以下文档对 MSP430FR263x 和 MSP430FR253x MCU 进行了介绍。www.ti.com.cn 网站上提供了这些文档
的副本。
接收文档更新通知
如需接收文档更新通知（包括器件勘误表），请转至 ti.com.cn 上相关器件的产品文件夹（关于这些产品文
件夹的链接，请参阅节 8.5）。单击右上角的“提醒我”(Alert me) 按钮。点击注册后，即可收到产品信息更改
每周摘要（如有）。有关更改的详细信息，请查阅已修订文档的修订历史记录。
勘误
《MSP430FR2633 器件勘误表》
说明了功能规格的已知例外情况。
《MSP430FR2533 器件勘误表》
说明了功能规格的已知例外情况。
《MSP430FR2632 器件勘误表》
说明了功能规格的已知例外情况。
《MSP430FR2532 器件勘误表》
说明了功能规格的已知例外情况。
用户指南
《MSP430FR4xx 和 MSP430FR2xx 系列用户指南》
详细介绍了该器件系列提供的模块和外设。
《MSP430 FRAM 器件引导加载程序 (BSL) 用户指南》
在 MSP430 MCU 项目开发和更新阶段，引导加载程序 (BSL) 提供存储器的编程方法。该程序可由使用串行
协议发送命令的工具激活。BSL 支持用户控制 MSP430 MCU 的活动，可与个人计算机或其他设备进行数据
交换。
《MSP430 硬件工具用户指南》
此手册介绍了 TI MSP-FET430 闪存仿真工具 (FET) 的硬件。FET 是针对 MSP430 超低功耗微控制器的程
序开发工具。
应用报告
MSP430 FRAM 技术 – 操作方法和最佳实践
FRAM 采用非易失性存储器技术，行为与 SRAM 类似，支持大量新 应用，还改变了固件的设计方式。该应
用程序报告从嵌入式软件开发方面概述了 FRAM 技术在 MSP430 中的使用方法和最佳实践。其中介绍了如
何按照应用程序特定的代码、常量、数据空间要求实施存储器布局以及如何使用 FRAM 优化应用程序的能
耗。
MSP430FR4xx 和 MSP430FR2xx 系列的 VLO 校准
MSP430FR4xx 和 MSP430FR2xx (FR4xx/FR2xx) 系列微控制器 (MCU) 提供了各种时钟源，包括一些高
速、高精度时钟以及一些低功耗、低系统成本时钟。用户可以选择以最佳方式权衡了性能、功耗和系统成本
的时钟。片上超低频振荡器 (VLO) 是 FR4xx/FR2xx 系列 MCU 中包含的频率为 10kHz（典型值）的时钟
源。VLO 具有超低的功耗， 因而 广泛适用于各种应用。
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www.ti.com.cn
ZHCSET6E –NOVEMBER 2015–REVISED DECEMBER 2019
《MSP430 32kHz 晶体振荡器》
选择合适的晶体、正确的负载电路和适当的电路板布局是实现稳定的晶体振荡器的关键。该应用报告总结了
晶体振荡器的功能，介绍了用于选择合适的晶体以实现 MSP430 超低功耗运行的参数。此外，还给出了正
确电路板布局的提示和示例。此外，为了确保振荡器在大规模生产后能够稳定运行，还可能需要进行一些振
荡器测试，该文档中提供了有关这些测试的详细信息。
《MSP430 系统级 ESD 注意事项》
随着芯片技术向更低电压方向发展以及设计具有成本效益的超低功耗组件的需求的出现，系统级 ESD 要求
变得越来越苛刻。该应用报告介绍了不同的 ESD 主题，旨在帮助电路板设计人员和 OEM 理解并设计出稳
健耐用的系统级设计。
8.5 相关链接
表 8-2 列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 8-2. 相关链接
器件
产品文件夹
单击此处
单击此处
单击此处
单击此处
立即订购
单击此处
单击此处
单击此处
单击此处
技术文档
单击此处
单击此处
单击此处
单击此处
工具和软件
单击此处
单击此处
单击此处
单击此处
支持和社区
单击此处
单击此处
单击此处
单击此处
MSP430FR2633
MSP430FR2632
MSP430FR2533
MSP430FR2532
8.6 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术
规范，并且不一定反映 TI 的观点；请参见 TI 的 《使用条款》。
TI E2E™ 社区
TI 的工程师交流 (E2E) 社区. 此社区的创建目的是为了促进工程师之间协作。在 e2e.ti.com 中，您可以提
问、共享知识、拓展思路，在同领域工程师的帮助下解决问题。
TI 嵌入式处理器维基网页
德州仪器 (TI) 嵌入式处理器维基网页。此网站的建立是为了帮助开发人员熟悉德州仪器 (TI) 的嵌入式处理
器，并且也为了促进与这些器件相关的硬件和软件的总体知识的创新和增长。
8.7 商标
CapTIvate, EnergyTrace, ULP Advisor, 适用于 MSP 微控制器的 Code Composer Studio, E2E are
trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
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产品主页链接: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532
MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532
ZHCSET6E –NOVEMBER 2015–REVISED DECEMBER 2019
www.ti.com.cn
8.8 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
8.9 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
8.10 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
90
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MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532
www.ti.com.cn
ZHCSET6E –NOVEMBER 2015–REVISED DECEMBER 2019
9 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015–2019, Texas Instruments Incorporated
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产品主页链接: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430FR2532IRGER
MSP430FR2532IRGET
MSP430FR2533IDA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
RGE
RGE
DA
24
24
32
32
32
32
24
24
24
24
32
32
32
32
24
24
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
FR2532
250
46
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
SNAGCU
SNAGCU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
SNAGCU
SNAGCU
FR2532
TSSOP
TSSOP
VQFN
FR2533
MSP430FR2533IDAR
MSP430FR2533IRHBR
MSP430FR2533IRHBT
MSP430FR2632IRGER
MSP430FR2632IRGET
MSP430FR2632IYQWR
MSP430FR2632IYQWT
MSP430FR2633IDA
DA
2000 RoHS & Green
3000 RoHS & Green
FR2533
RHB
RHB
RGE
RGE
YQW
YQW
DA
FR2533
VQFN
250
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
RoHS & Green
FR2533
VQFN
FR2632
VQFN
FR2632
DSBGA
DSBGA
TSSOP
TSSOP
VQFN
430FR2632
430FR2632
FR2633
250
46
RoHS & Green
RoHS & Green
MSP430FR2633IDAR
MSP430FR2633IRHBR
MSP430FR2633IRHBT
MSP430FR2633IYQWR
MSP430FR2633IYQWT
DA
2000 RoHS & Green
3000 RoHS & Green
FR2633
RHB
RHB
YQW
YQW
FR2633
VQFN
250
3000 RoHS & Green
250 RoHS & Green
RoHS & Green
FR2633
DSBGA
DSBGA
430FR2633
430FR2633
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430FR2532IRGER
MSP430FR2532IRGET
MSP430FR2533IDAR
MSP430FR2533IRHBR
MSP430FR2533IRHBT
MSP430FR2632IRGET
VQFN
VQFN
TSSOP
VQFN
VQFN
VQFN
RGE
RGE
DA
24
24
32
32
32
24
24
24
32
32
32
24
24
3000
250
330.0
180.0
330.0
330.0
180.0
180.0
180.0
180.0
330.0
330.0
180.0
180.0
180.0
12.4
12.4
24.4
12.4
12.4
12.4
8.4
4.25
4.25
8.6
4.25
4.25
11.5
5.3
1.15
1.15
1.6
1.1
1.1
1.15
0.8
0.8
1.6
1.1
1.1
0.8
0.8
8.0
8.0
12.0
8.0
8.0
8.0
4.0
4.0
12.0
8.0
8.0
4.0
4.0
12.0
12.0
24.0
12.0
12.0
12.0
8.0
Q2
Q2
Q1
Q2
Q2
Q2
Q1
Q1
Q1
Q2
Q2
Q1
Q1
2000
3000
250
RHB
RHB
RGE
YQW
YQW
DA
5.3
5.3
5.3
250
4.25
2.38
2.38
8.6
4.25
2.4
MSP430FR2632IYQWR DSBGA
MSP430FR2632IYQWT DSBGA
3000
250
8.4
2.4
8.0
MSP430FR2633IDAR
MSP430FR2633IRHBR
MSP430FR2633IRHBT
TSSOP
VQFN
VQFN
2000
3000
250
24.4
12.4
12.4
8.4
11.5
5.3
24.0
12.0
12.0
8.0
RHB
RHB
YQW
YQW
5.3
5.3
5.3
MSP430FR2633IYQWR DSBGA
MSP430FR2633IYQWT DSBGA
3000
250
2.38
2.38
2.4
8.4
2.4
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430FR2532IRGER
MSP430FR2532IRGET
MSP430FR2533IDAR
MSP430FR2533IRHBR
MSP430FR2533IRHBT
MSP430FR2632IRGET
MSP430FR2632IYQWR
MSP430FR2632IYQWT
MSP430FR2633IDAR
MSP430FR2633IRHBR
MSP430FR2633IRHBT
MSP430FR2633IYQWR
MSP430FR2633IYQWT
VQFN
VQFN
RGE
RGE
DA
24
24
32
32
32
24
24
24
32
32
32
24
24
3000
250
367.0
210.0
350.0
367.0
210.0
210.0
182.0
182.0
350.0
367.0
210.0
182.0
182.0
367.0
185.0
350.0
367.0
185.0
185.0
182.0
182.0
350.0
367.0
185.0
182.0
182.0
35.0
35.0
43.0
35.0
35.0
35.0
20.0
20.0
43.0
35.0
35.0
20.0
20.0
TSSOP
VQFN
2000
3000
250
RHB
RHB
RGE
YQW
YQW
DA
VQFN
VQFN
250
DSBGA
DSBGA
TSSOP
VQFN
3000
250
2000
3000
250
RHB
RHB
YQW
YQW
VQFN
DSBGA
DSBGA
3000
250
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jun-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
MSP430FR2533IDA
MSP430FR2633IDA
DA
DA
TSSOP
TSSOP
32
32
46
46
530
530
11.89
11.89
3600
3600
4.9
4.9
Pack Materials-Page 3
PACKAGE OUTLINE
YQW0024
DSBGA - 0.625 mm max height
SCALE 6.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
0.625 MAX
C
SEATING PLANE
0.05 C
BALL TYP
0.30
0.12
1.6
TYP
SYMM
E
D
C
1.6
TYP
SYMM
0.4
D: Max = 2.37 mm, Min = 2.31 mm
E: Max = 2.32 mm, Min = 2.26 mm
TYP
B
A
1
2
3
4
5
0.3
24X
C A
0.2
B
0.4 TYP
0.015
4221561/A 02/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YQW0024
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
24X ( 0.25)
1
2
4
5
A
(0.4) TYP
B
C
SYMM
D
E
SYMM
LAND PATTERN EXAMPLE
SCALE:30X
(
0.25)
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
METAL
(
0.25)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4221561/A 02/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YQW0024
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
24X ( 0.25)
(0.4) TYP
1
2
3
4
5
A
B
SYMM
C
D
E
METAL
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4221561/A 02/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
A
4.1
3.9
B
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
ꢀꢀꢀꢀꢁꢂꢃꢄꢂꢅ
(0.2) TYP
2X 2.5
12
7
20X 0.5
6
13
25
2X
SYMM
2.5
1
18
0.30
PIN 1 ID
(OPTIONAL)
24X
0.18
24
19
0.1
0.05
C A B
C
SYMM
0.48
0.28
24X
4219016 / A 08/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
2.7)
(
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.825)
2X
(1.1)
ꢆꢄꢂꢁꢇꢀ9,$
TYP
6
13
(R0.05)
7
12
2X(1.1)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219016 / A 08/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
4X ( 1.188)
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.825)
(0.694)
TYP
6
13
25
(R0.05) TYP
METAL
TYP
7
12
(0.694)
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X
4219016 / A 08/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
20.000
OPTIONAL METAL THICKNESS
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
SEE SIDE WALL
DETAIL
2X
SYMM
33
3.5
0.3
0.2
32X
24
0.1
C A B
C
1
0.05
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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