MSP430FR5733IRHAT [TI]
MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器
| 型号： | MSP430FR5733IRHAT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MIXED SIGNAL MICROCONTROLLER |
| 文件： | 总109页 (文件大小：1238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MSP430FR573x
MSP430FR572x
www.ti.com
SLAS639D –JULY 2011–REVISED AUGUST 2012
MIXED SIGNAL MICROCONTROLLER
1
FEATURES
23
•
Embedded Microcontroller
–
eUSCI_A0 and eUSCI_A1 Support:
–
16-Bit RISC Architecture up to 24-MHz
Clock
–
UART With Automatic Baud-Rate
Detection
–
–
Wide Supply Voltage Range (2 V to 3.6 V)
-40°C to 85°C Operation
–
–
IrDA Encode and Decode
SPI at Rates up to 10 Mbps
•
Optimized Ultra-Low Power Modes
–
–
eUSCI_B0 Supports:
–
–
I2C With Multi-Slave Addressing
Consumption
Mode
SPI at Rates up to 10 Mbps
(Typical)
81.4 µA/MHz
6.3 µA
Hardware UART or I2C Bootstrap Loader
(BSL)
Active Mode
Standby (LPM3 With VLO)
Real-Time Clock (LPM3.5 With Crystal)
Shutdown (LPM4.5)
•
•
Power Management System
1.5 µA
0.32 µA
–
–
Fully Integrated LDO
Supply Voltage Supervisor for Core and
Supply Voltages With Reset Capability
•
Ultra-Low Power Ferroelectric RAM
–
–
–
Up to 16KB Nonvolatile Memory
Ultra-Low Power Writes
–
–
Always-On Zero-Power Brownout Detection
Serial On-Board Programming With No
External Voltage Needed
Fast Write at 125 ns per Word (16KB in 1
ms)
Flexible Clock System
–
–
Built in Error Coding and Correction (ECC)
and Memory Protection Unit (MPU)
–
Fixed-Frequency DCO With Six Selectable
Factory-Trimmed Frequencies (Device
Dependent)
Universal Memory = Program + Data +
Storage
1015 Write Cycle Endurance
–
Low-Power Low-Frequency Internal Clock
Source (VLO)
–
–
Radiation Resistant and Nonmagnetic
–
–
32-kHz Crystals (LFXT)
•
Intelligent Digital Peripherals
High-Frequency Crystals (HFXT)
–
–
–
32-Bit Hardware Multiplier (MPY)
Three-Channel Internal DMA
•
•
Development Tools and Software
–
Free Professional Development
Environments (IAR, CCS, GCC)
Real-Time Clock With Calendar and Alarm
Functions
–
Low-Cost Full-Featured Kit (MSP-
EXP430FR5739)
–
–
Five 16-Bit Timers With up to Three
Capture/Compare
–
–
Full Development Kit (MSP-FET430U40A)
Target Board (MSP-TS430RHA40A)
16-Bit Cyclic Redundancy Checker (CRC)
•
High-Performance Analog
Family Members
–
16-Channel Analog Comparator With
Voltage Reference and Programmable
Hysteresis
–
20 Different Variants and 5 Available
Packages Summarized in Table 1 and
Table 2
–
14-Channel 10-Bit Analog-to-Digital
Converter (ADC) With Internal Reference
and Sample-and-Hold
–
For Complete Module Descriptions, See the
MSP430FR57xx Family User's Guide
(SLAU272)
–
200 ksps at 100-µA Consumption
•
Enhanced Serial Communication
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
MSP430 is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
3
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
MSP430FR573x
MSP430FR572x
SLAS639D –JULY 2011–REVISED AUGUST 2012
www.ti.com
CAUTION
CAUTION
These products use FRAM nonvolatile memory technology. FRAM retention is sensitive to extreme temperatures, such
as those experienced during reflow or hand soldering. See Absolute Maximum Ratings for more information.
System-level ESD protection must be applied in compliance with the device-level ESD specification to prevent electrical
overstress or disturb of data or code memory. See the application report MSP430™ System-Level ESD Considerations
(SLAA530) for more information.
DESCRIPTION
The Texas Instruments MSP430FR57xx family of ultralow-power microcontrollers consists of multiple devices
featuring embedded FRAM nonvolatile memory, ultralow power 16-bit MSP430 CPU, and different peripherals
targeted for various applications. The architecture, FRAM, and peripherals, combined with seven low-power
modes, are optimized to achieve extended battery life in portable and wireless sensing applications. FRAM is a
new nonvolatile memory that combines the speed, flexibility, and endurance of SRAM with the stability and
reliability of flash, all at lower total power consumption. Peripherals include 10-bit A/D converter, 16-channel
comparator with voltage reference generation and hysteresis capabilities, three enhanced serial channels
capable of I2C, SPI, or UART protocols, internal DMA, hardware multiplier, real-time clock, five 16-bit timers, and
more. The family members that are available are summarized in Table 1.
Table 1. Family Members
eUSCI
System
Clock
(MHz)
Channel
A:
UART,
IrDA, SPI
FRAM
(KB)
SRAM
(KB)
Device
ADC10_B Comp_D Timer_A(1) Timer_B(2)
I/O
Package
Channel
B:
SPI, I2C
32
30
RHA
DA
12 ext,
2 int ch.
MSP430FR5739
16
16
1
1
24
24
16 ch.
3, 3
3, 3
3, 3, 3
2
1
1
1
6 ext, 2 int
ch.
10 ch.
12 ch.
9 ch.
17
21
16
RGE
PW
8 ext, 2 int
ch.
MSP430FR5738
3
5 ext, 2 int
ch.
YFF(3)
32
30
17
21
16
32
30
RHA
DA
MSP430FR5737
MSP430FR5736
MSP430FR5735
16
16
8
1
1
1
24
24
24
16 ch.
3, 3
3, 3
3, 3
3, 3, 3
3
2
1
2
1
1
1
10 ch.
12 ch.
9 ch.
RGE
PW
YFF(3)
RHA
DA
12 ext,
2 int ch.
16 ch.
3, 3, 3
6 ext, 2 int
ch.
10 ch.
12 ch.
17
21
RGE
PW
MSP430FR5734
8
1
24
3, 3
3
1
1
8 ext, 2 int
ch.
32
30
17
21
32
30
RHA
DA
MSP430FR5733
MSP430FR5732
MSP430FR5731
8
8
4
1
1
1
24
24
24
16 ch.
3, 3
3, 3
3, 3
3, 3, 3
3
2
1
2
1
1
1
10 ch.
12 ch.
RGE
PW
RHA
DA
12 ext,
2 int ch.
16 ch.
3, 3, 3
(1) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
(2) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
(3) Product Preview
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Copyright © 2011–2012, Texas Instruments Incorporated
MSP430FR573x
MSP430FR572x
www.ti.com
SLAS639D –JULY 2011–REVISED AUGUST 2012
Table 1. Family Members (continued)
eUSCI
System
Clock
(MHz)
Channel
Channel
FRAM
(KB)
SRAM
(KB)
Device
ADC10_B Comp_D Timer_A(1) Timer_B(2)
I/O
Package
A:
B:
UART,
IrDA, SPI
SPI, I2C
6 ext, 2 int
10 ch.
ch.
17
21
16
RGE
PW
8 ext, 2 int
MSP430FR5730
4
1
24
12 ch.
9 ch.
3, 3
3
1
1
ch.
5 ext, 2 int
ch.
YFF(3)
32
30
RHA
DA
12 ext,
2 int ch.
MSP430FR5729
MSP430FR5728
16
16
1
1
8
8
16 ch.
3, 3
3, 3
3, 3, 3
2
1
1
1
6 ext, 2 int
ch.
10 ch.
12 ch.
17
21
RGE
PW
3
8 ext, 2 int
ch.
32
30
17
21
32
30
RHA
DA
MSP430FR5727
MSP430FR5726
MSP430FR5725
16
16
8
1
1
1
8
8
8
16 ch.
3, 3
3, 3
3, 3
3, 3, 3
3
2
1
2
1
1
1
10 ch.
12 ch.
RGE
PW
RHA
DA
12 ext,
2 int ch.
16 ch.
3, 3, 3
6 ext, 2 int
ch.
10 ch.
12 ch.
17
21
RGE
PW
MSP430FR5724
8
1
8
3, 3
3
1
1
8 ext, 2 int
ch.
32
30
17
21
32
30
RHA
DA
MSP430FR5723
MSP430FR5722
MSP430FR5721
8
8
4
1
1
1
8
8
8
16 ch.
3, 3
3, 3
3, 3
3, 3, 3
3
2
1
2
1
1
1
10 ch.
12 ch.
RGE
PW
RHA
DA
12 ext,
2 int ch.
16 ch.
3, 3, 3
6 ext, 2 int
ch.
10 ch.
12 ch.
17
21
RGE
PW
MSP430FR5720
4
1
8
3, 3
3
1
1
8 ext, 2 int
ch.
Copyright © 2011–2012, Texas Instruments Incorporated
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MSP430FR572x
SLAS639D –JULY 2011–REVISED AUGUST 2012
www.ti.com
Table 2. Ordering Information(1)
PACKAGED DEVICES(2)
PLASTIC 40-PIN
VQFN
PLASTIC 24-PIN
PLASTIC 38-PIN
PLASTIC 28-PIN
TSSOP
PLASTIC 25-BALL
DSBGA
TA
VQFN
(RGE)
TSSOP
(DA)
(RHA)
(PW)
(YFF)(3)
MSP430FR5721IRHA
MSP430FR5723IRHA
MSP430FR5725IRHA
MSP430FR5727IRHA
MSP430FR5729IRHA
MSP430FR5731IRHA
MSP430FR5733IRHA
MSP430FR5735IRHA
MSP430FR5737IRHA
MSP430FR5739IRHA
MSP430FR5720IRGE
MSP430FR5722IRGE
MSP430FR5724IRGE
MSP430FR5726IRGE
MSP430FR5728IRGE
MSP430FR5730IRGE
MSP430FR5732IRGE
MSP430FR5734IRGE
MSP430FR5736IRGE
MSP430FR5738IRGE
MSP430FR5721IDA
MSP430FR5723IDA
MSP430FR5725IDA
MSP430FR5727IDA
MSP430FR5729IDA
MSP430FR5731IDA
MSP430FR5733IDA
MSP430FR5735IDA
MSP430FR5737IDA
MSP430FR5739IDA
MSP430FR5720IPW
MSP430FR5722IPW
MSP430FR5724IPW
MSP430FR5726IPW
MSP430FR5728IPW
MSP430FR5730IPW
MSP430FR5732IPW
MSP430FR5734IPW
MSP430FR5736IPW
MSP430FR5738IPW
MSP430FR5730IYFF(3)
MSP430FR5736IYFF(3)
MSP430FR5738IYFF(3)
–40°C to
85°C
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
(3) Product Preview
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MSP430FR573x
MSP430FR572x
www.ti.com
SLAS639D –JULY 2011–REVISED AUGUST 2012
Functional Block Diagram –
MSP430FR5721IRHA, MSP430FR5725IRHA, MSP430FR5729IRHA,
MSP430FR5731IRHA, MSP430FR5735IRHA, MSP430FR5739IRHA
PA
PB
PJ.4/XIN
PJ.5/XOUT
DVCC DVSS VCORE AVCC AVSS
P1.x P2.x P3.x P4.x
16 KB
(’5739, ’5729)
I/O Ports
P1/P2
2×8 I/Os
I/O Ports
P3/P4
ACLK
SMCLK
SYS
8 KB
(’5735, ‘5725)
Clock
System
Power
Management
1×8 I/Os
1x 2 I/Os
Interrupt
& Wakeup
PB
1 KB
Boot
ROM
4 KB
(’5731, ‘5721)
Watchdog
REF
Interrupt
& Wakeup
PA
SVS
FRAM
RAM
MCLK
Memory
Protection
Unit
1×16 I/Os
1×10 I/Os
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S: 3+1)
eUSCI_A0: eUSCI_A1:
UART,
IrDA, SPI
TA0
TA1
TB0
TB1
TB2
ADC10_B
UART,
IrDA, SPI
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
JTAG/
SBW
Interface
10 Bit
200KSPS
Comp_D
RTC_B
MPY32
CRC
eUSCI_B0:
SPI, I2C
(2) Timer_A (3) Timer_B
3 CC
Registers
16 channels
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
3 CC
Registers
16 channels
(12 ext/2 int)
Functional Block Diagram –
MSP430FR5723IRHA, MSP430FR5727IRHA,
MSP430FR5733IRHA, MSP430FR5737IRHA
PA
PB
PJ.4/XIN
PJ.5/XOUT
DVCC DVSS VCORE AVCC AVSS
P1.x P2.x P3.x P4.x
16 KB
(’5737, ’5727)
I/O Ports
P1/P2
2×8 I/Os
I/O Ports
P3/P4
ACLK
SMCLK
SYS
8 KB
(’5733, ‘5723)
Clock
System
Power
Management
1×8 I/Os
1x 2 I/Os
Interrupt
& Wakeup
PB
1 KB
Boot
ROM
Watchdog
Interrupt
& Wakeup
PA
SVS
FRAM
RAM
MCLK
Memory
Protection
Unit
1×16 I/Os
1×10 I/Os
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S: 3+1)
TA0
TA1
TB0
TB1
TB2
eUSCI_A0:
UART,
IrDA, SPI
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
JTAG/
SBW
Interface
eUSCI_A1:
UART,
IrDA, SPI
Comp_D
RTC_B
MPY32
CRC
REF
(2) Timer_A (3) Timer_B
3 CC
Registers
16 channels
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
eUSCI_B0:
SPI, I2C
3 CC
Registers
Copyright © 2011–2012, Texas Instruments Incorporated
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MSP430FR572x
SLAS639D –JULY 2011–REVISED AUGUST 2012
www.ti.com
Pin Designation –
MSP430FR5721IRHA, MSP430FR5723IRHA, MSP430FR5725IRHA, MSP430FR5727IRHA,
MSP430FR5729IRHA,
MSP430FR5731IRHA, MSP430FR5733IRHA, MSP430FR5735IRHA, MSP430FR5737IRHA,
MSP430FR5739IRHA
RHA PACKAGE
(TOP VIEW)
AVSS
PJ.4/XIN
PJ.5/XOUT
AVSS
P2.4/TA1.0/UCA1CLK/A7*/CD11
P2.3/TA0.0/UCA1STE/A6*/CD10
P2.7
DVCC
DVSS
AVCC
1
2
30
29
28
27
26
25
24
23
22
21
P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF-*
P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+*
P1.2/TA1.1/TA0CLK/CDOUT/A2*/CD2
P3.0/A12*/CD12
VCORE
P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0
P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0
MSP430FR5721
MSP430FR5723
MSP430FR5725
MSP430FR5727
MSP430FR5729
MSP430FR5731
MSP430FR5733
MSP430FR5735
MSP430FR5737
MSP430FR5739
3
4
P3.7/TB2.2
P3.6/TB2.1/TB1CLK
P3.5/TB1.2/CDOUT
5
P3.1/A13*/CD13
P3.2/A14*/CD14
P3.3/A15*/CD15
6
7
P3.4/TB1.1/TB2CLK/SMCLK
P2.2/TB2.2/UCB0CLK/TB1.0
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
8
P1.3/TA1.2/UCB0STE/A3*/CD3
P1.4/TB0.1/UCA0STE/A4*/CD4
P1.5/TB0.2/UCA0CLK/A5*/CD5
9
10
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO/TB0OUTH/SMCLK/CD6
PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7
PJ.2/TMS/TB2OUTH/ACLK/CD8
PJ.3/TCK/CD9
P2.6/TB1.0/UCA1RXD/UCA1SOMI
P2.5/TB0.0/UCA1TXD/UCA1SIMO
P4.1
P4.0/TB2.0
* Not available on MSP430FR5737, MSP430FR5733, MSP430FR5727, MSP430FR5723
Note: Power Pad connection to VSS recommended.
6
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MSP430FR573x
MSP430FR572x
www.ti.com
SLAS639D –JULY 2011–REVISED AUGUST 2012
Functional Block Diagram –
MSP430FR5721IDA, MSP430FR5725IDA, MSP430FR5729IDA,
MSP430FR5731IDA, MSP430FR5735IDA, MSP430FR5739IDA
PA
PB
P3.x
PJ.4/XIN
PJ.5/XOUT
DVCC DVSS VCORE AVCC AVSS
P1.x P2.x
16 KB
(’5739, ’5729)
I/O Ports
P1/P2
2×8 I/Os
I/O Ports
P3
1×8 I/Os
ACLK
SMCLK
SYS
8 KB
(’5735, ‘5725)
Clock
System
Power
Management
1 KB
Boot
ROM
4 KB
(’5731, ‘5721)
Watchdog
REF
Interrupt
& Wakeup
PA
Interrupt
& Wakeup
PB
SVS
FRAM
RAM
MCLK
Memory
Protection
Unit
1×16 I/Os
1×8 I/Os
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S: 3+1)
eUSCI_A0: eUSCI_A1:
UART,
IrDA, SPI
TA0
TA1
TB0
TB1
TB2
ADC10_B
UART,
IrDA, SPI
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
JTAG/
SBW
Interface
10 Bit
200KSPS
Comp_D
RTC_B
MPY32
CRC
eUSCI_B0:
SPI, I2C
(2) Timer_A (3) Timer_B
3 CC
Registers
16 channels
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
3 CC
Registers
16 channels
(12 ext/2 int)
Functional Block Diagram –
MSP430FR5723IDA, MSP430FR5727IDA,
MSP430FR5733IDA, MSP430FR5737IDA
PA
PB
PJ.4/XIN
PJ.5/XOUT
DVCC DVSS VCORE AVCC AVSS
P1.x P2.x
P3.x
16 KB
(’5737, ’5727)
I/O Ports
P1/P2
2×8 I/Os
I/O Ports
P3
1×8 I/Os
ACLK
SMCLK
SYS
8 KB
(’5733, ‘5723)
Clock
System
Power
Management
1 KB
Boot
ROM
Watchdog
Interrupt
& Wakeup
PA
Interrupt
& Wakeup
PB
SVS
FRAM
RAM
MCLK
Memory
Protection
Unit
1×16 I/Os
1×8 I/Os
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S: 3+1)
TA0
TA1
TB0
TB1
TB2
eUSCI_A0:
UART,
IrDA, SPI
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
JTAG/
SBW
Interface
eUSCI_A1:
UART,
IrDA, SPI
Comp_D
RTC_B
MPY32
CRC
REF
(2) Timer_A (3) Timer_B
3 CC
Registers
16 channels
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
eUSCI_B0:
SPI, I2C
3 CC
Registers
Copyright © 2011–2012, Texas Instruments Incorporated
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MSP430FR572x
SLAS639D –JULY 2011–REVISED AUGUST 2012
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Pin Designation –
MSP430FR5721IDA, MSP430FR5723IDA, MSP430FR5725IDA, MSP430FR5727IDA,
MSP430FR5729IDA,
MSP430FR5731IDA, MSP430FR5733IDA, MSP430FR5735IDA, MSP430FR5737IDA,
MSP430FR5739IDA
DA PACKAGE
(TOP VIEW)
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
PJ.4/XIN
AVSS
2
PJ.5/XOUT
P2.4/TA1.0/UCA1CLK/A7*/CD11
P2.3/TA0.0/UCA1STE/A6*/CD10
3
AVSS
AVCC
4
P2.7
5
P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF-*
DVCC
DVSS
VCORE
MSP430FR5721
MSP430FR5723
MSP430FR5725
MSP430FR5727
MSP430FR5729
6
P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+*
P1.2/TA1.1/TA0CLK/CDOUT/A2*/CD2
7
8
P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0
P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0
P3.0/A12*/CD12
P3.1/A13*/CD13
9
10
11
12
13
14
15
16
17
18
19
P3.2/A14*/CD14
P3.7/TB2.2
MSP430FR5731
MSP430FR5733
MSP430FR5735
MSP430FR5737
MSP430FR5739
P3.3/A15*/CD15
P3.6/TB2.1/TB1CLK
P3.5/TB1.2/CDOUT
P1.3/TA1.2/UCB0STE/A3*/CD3
P1.4/TB0.1/UCA0STE/A4*/CD4
P1.5/TB0.2/UCA0CLK/A5*/CD5
PJ.0/TDO/TB0OUTH/SMCLK/CD6
PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7
PJ.2/TMS/TB2OUTH/ACLK/CD8
PJ.3/TCK/CD9
P3.4/TB1.1/TB2CLK/SMCLK
P2.2/TB2.2/UCB0CLK/TB1.0
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
RST/NMI/SBWTDIO
TEST/SBWTCK
P2.5/TB0.0/UCA1TXD/UCA1SIMO
P2.6/TB1.0/UCA1RXD/UCA1SOMI
* Not available on MSP430FR5737, MSP430FR5733, MSP430FR5727, MSP430FR5723
8
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Functional Block Diagram –
MSP430FR5720IRGE, MSP430FR5724IRGE, MSP430FR5728IRGE,
MSP430FR5730IRGE, MSP430FR5734IRGE, MSP430FR5738IRGE
PA
PJ.4/XIN
PJ.5/XOUT
DVCC DVSS VCORE AVCC AVSS
P1.x P2.x
16 KB
(’5738, ’5728)
I/O Ports
P1/P2
1×8 I/Os
1×3 I/Os
ACLK
SMCLK
SYS
8 KB
(’5734, ‘5724)
Clock
System
Power
Management
1 KB
Boot
ROM
4 KB
(’5730, ‘5720)
Watchdog
REF
SVS
Interrupt
& Wakeup
PA
FRAM
RAM
MCLK
Memory
Protection
Unit
1×11 I/Os
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S: 3+1)
eUSCI_A0:
UART,
IrDA, SPI
TA0
TA1
TB0
ADC10_B
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
JTAG/
SBW
Interface
10 Bit
200KSPS
Comp_D
RTC_B
MPY32
CRC
eUSCI_B0:
SPI, I2C
(2) Timer_A (1) Timer_B
3 CC
Registers
10 channels
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
3 CC
Registers
8 channels
(6 ext/2 int)
Functional Block Diagram –
MSP430FR5722IRGE, MSP430FR5726IRGE,
MSP430FR5732IRGE, MSP430FR5736IRGE
PA
PJ.4/XIN
PJ.5/XOUT
DVCC DVSS VCORE AVCC AVSS
P1.x P2.x
16 KB
(’5736, ’5726)
I/O Ports
P1/P2
1×8 I/Os
1×3 I/Os
ACLK
SMCLK
SYS
8 KB
(’5732, ‘5722)
Clock
System
Power
Management
1 KB
Boot
ROM
Watchdog
SVS
Interrupt
& Wakeup
PA
FRAM
RAM
MCLK
Memory
Protection
Unit
1×11 I/Os
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S: 3+1)
TA0
TA1
TB0
eUSCI_A0:
UART,
IrDA, SPI
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
JTAG/
SBW
Interface
Comp_D
RTC_B
MPY32
CRC
REF
(2) Timer_A (1) Timer_B
3 CC
Registers
10 channels
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
eUSCI_B0:
SPI, I2C
3 CC
Registers
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Pin Designation –
MSP430FR5720IRGE, MSP430FR5722IRGE, MSP430FR5724IRGE, MSP430FR5726IRGE,
MSP430FR5728IRGE,
MSP430FR5730IRGE, MSP430FR5732IRGE, MSP430FR5734IRGE, MSP430FR5736IRGE,
MSP430FR5738IRGE
RGE PACKAGE
(TOP VIEW)
PJ.5/XOUT
AVSS
AVCC
PJ.4/XIN
DVCC
DVSS
1
2
3
4
5
6
MSP430FR5720
MSP430FR5722
MSP430FR5724
MSP430FR5726
MSP430FR5728
MSP430FR5730
MSP430FR5732
MSP430FR5734
MSP430FR5736
MSP430FR5738
18
VCORE
17 P1.7/UCB0SOMI/UCB0SCL/TA1.0
P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF-*
P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+*
P1.2/TA1.1/TA0CLK/CDOUT/A2*/CD2
P1.3/TA1.2/UCB0STE/A3*/CD3
16
P1.6/UCB0SIMO/UCB0SDA/TA0.0
15
P2.2/UCB0CLK
P2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
14
P1.4/TB0.1/UCA0STE/A4*/CD4
13
P1.5/TB0.2/UCA0CLK/A5*/CD5
PJ.0/TDO/TB0OUTH/SMCLK/CD6
PJ.1/TDI/TCLK/MCLK/CD7
PJ.2/TMS/ACLK/CD8
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.3/TCK/CD9
* Not available on MSP430FR5736, MSP430FR5732, MSP430FR5726, MSP430FR5722
Note: Power Pad connection to VSS recommended.
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Pin Designation –
MSP430FR5730IYFF, MSP430FR5736IYFF, MSP430FR5738IYFF
YFF PACKAGE
(TOP VIEW)
NC1
P1.1
P1.3
P1.2
P1.5
A1
A2
A3
A4
A5
PJ.5
AVCC AVSS
P1.4
PJ.1
B1
B2
B3
B4
B5
PJ.4
AVSS
PJ.2
PJ.3
PJ.0
C1
C2
C4
C5
C3
DVCC DVSS
D1 D2
P2.1 RST/NMI TEST
D3
D4
D5
VCORE P1.6
E1 E2
P1.7
P2.2
P2.0
E3
E4
E5
1
NC (no connect). This ball must be attached but remain floating (no electrical connection).
P1.0 must be initialized properly to avoid the floating input of the device.
Package Dimensions: The package dimensions for the YFF package are shown in Table 3. See the package
drawing at the end of this data sheet for more details.
Table 3. YFF Package Dimensions
PACKAGED DEVICES
MSP430FR5738IYFF
MSP430FR5736IYFF
MSP430FR5730IYFF
D
E
2.04 ± 0.03
2.24 ± 0.03
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Functional Block Diagram –
MSP430FR5720IPW, MSP430FR5724IPW, MSP430FR5728IPW,
MSP430FR5730IPW, MSP430FR5734IPW, MSP430FR5738IPW
PA
PJ.4/XIN
PJ.5/XOUT
DVCC DVSS VCORE AVCC AVSS
P1.x P2.x
16 KB
(’5738, ’5728)
I/O Ports
P1/P2
1×8 I/Os
1×7 I/Os
ACLK
SMCLK
SYS
8 KB
(’5734, ‘5724)
Clock
System
Power
Management
1 KB
Boot
ROM
4 KB
(’5730, ‘5720)
Watchdog
REF
SVS
Interrupt
& Wakeup
PA
FRAM
RAM
MCLK
Memory
Protection
Unit
1×15 I/Os
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S: 3+1)
eUSCI_A0:
UART,
IrDA, SPI
TA0
TA1
TB0
ADC10_B
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
JTAG/
SBW
Interface
10 Bit
200KSPS
Comp_D
RTC_B
MPY32
CRC
eUSCI_B0:
SPI, I2C
(2) Timer_A (1) Timer_B
3 CC
Registers
12 channels
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
3 CC
Registers
12 channels
(8 ext/2 int)
Functional Block Diagram –
MSP430FR5722IPW, MSP430FR5726IPW,
MSP430FR5732IPW, MSP430FR5736IPW
PA
PJ.4/XIN
PJ.5/XOUT
DVCC DVSS VCORE AVCC AVSS
P1.x P2.x
16 KB
(’5736, ’5726)
I/O Ports
P1/P2
1×8 I/Os
1×7 I/Os
ACLK
SMCLK
SYS
8 KB
(’5732, ‘5722)
Clock
System
Power
Management
1 KB
Boot
ROM
Watchdog
SVS
Interrupt
& Wakeup
PA
FRAM
RAM
MCLK
Memory
Protection
Unit
1×15 I/Os
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S: 3+1)
TA0
TA1
TB0
eUSCI_A0:
UART,
IrDA, SPI
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
JTAG/
SBW
Interface
Comp_D
RTC_B
MPY32
CRC
REF
(2) Timer_A (1) Timer_B
3 CC
Registers
12 channels
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
eUSCI_B0:
SPI, I2C
3 CC
Registers
12
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SLAS639D –JULY 2011–REVISED AUGUST 2012
Pin Designation –
MSP430FR5720IPW, MSP430FR5722IPW, MSP430FR5724IPW, MSP430FR5726IPW,
MSP430FR5728IPW,
MSP430FR5730IPW, MSP430FR5732IPW, MSP430FR5734IPW, MSP430FR5736IPW,
MSP430FR5738IPW
PW PACKAGE
(TOP VIEW)
1
28
27
26
25
24
23
22
21
20
19
PJ.4/XIN
P2.4/TA1.0/A7*/CD11
2
PJ.5/XOUT
P2.3/TA0.0/A6*/CD10
DVCC
3
AVSS
AVCC
MSP430FR5738
MSP430FR5736
MSP430FR5734
MSP430FR5732
MSP430FR5730
4
DVSS
5
P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF-*
VCORE
P1.7/UCB0SOMI/UCB0SCL/TA1.0
P1.6/UCB0SIMO/UCB0SDA/TA0.0
6
P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+*
P1.2/TA1.1/TA0CLK/CDOUT/A2*/CD2
7
8
P1.3/TA1.2/UCB0STE/A3*/CD3
P1.4/TB0.1/UCA0STE/A4*/CD4
P1.5/TB0.2/UCA0CLK/A5*/CD5
PJ.0/TDO/TB0OUTH/SMCLK/CD6
PJ.1/TDI/TCLK/MCLK/CD7
P2.2/UCB0CLK
P2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
MSP430FR5728
MSP430FR5726
MSP430FR5724
9
10
11
12
13
14
MSP430FR5722 18
MSP430FR5720
RST/NMI/SBWTDIO
TEST/SBWTCK
P2.6
17
PJ.2/TMS/ACLK/CD8
16
15
P2.5/TB0.0
PJ.3/TCK/CD9
* Not available on MSP430FR5736, MSP430FR5732, MSP430FR5726, MSP430FR5722
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Table 4. Terminal Functions
TERMINAL
(1)
NO.
I/O
DESCRIPTION
NAME
RHA RGE
DA
PW
YFF
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TA0 CCR1 capture: CCI1A input, compare: Out1
External DMA trigger
P1.0/TA0.1/DMAE0/
RTCCLK/A0/CD0/VeREF-
(2)
1
1
5
5
I/O
RTC clock calibration output
Analog input A0 – ADC (not available on devices without ADC)
Comparator_D input CD0
External applied reference voltage (not available on devices without
ADC)
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TA0 CCR2 capture: CCI2A input, compare: Out2
TA1 input clock
P1.1/TA0.2/TA1CLK/
CDOUT/A1/CD1/VeREF+
2
2
6
6
A2
I/O
Comparator_D output
Analog input A1 – ADC (not available on devices without ADC)
Comparator_D input CD1
Input for an external reference voltage to the ADC (not available on
devices without ADC)
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TA1 CCR1 capture: CCI1A input, compare: Out1
TA0 input clock
P1.2/TA1.1/TA0CLK/
CDOUT/A2/CD2
3
3
7
7
A3
I/O
Comparator_D output
Analog input A2 – ADC (not available on devices without ADC)
Comparator_D input CD2
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options PW, RGE)
Analog input A12 – ADC (not available on devices without ADC or
package options PW, RGE)
P3.0/A12/CD12
P3.1/A13/CD13
P3.2/A14/CD14
P3.3/A15/CD15
4
5
6
7
N/A
N/A
N/A
N/A
8
9
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
I/O
I/O
I/O
I/O
Comparator_D input CD12 (not available on package options PW,
RGE)
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options PW, RGE)
Analog input A13 – ADC (not available on devices without ADC or
package options PW, RGE)
Comparator_D input CD13 (not available on package options PW,
RGE)
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options PW, RGE)
Analog input A14 – ADC (not available on devices without ADC or
package options PW, RGE)
10
11
Comparator_D input CD14 (not available on package options PW,
RGE)
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options PW, RGE)
Analog input A15 – ADC (not available on devices without ADC or
package options PW, RGE)
Comparator_D input CD15 (not available on package options PW,
RGE)
(1) I = input, O = output, N/A = not available
(2) The functions associated with P1.0 are implemented but not available on the device pinout. To avoid floating inputs, this digital I/O
should be properly configured. The pullup/down resistors of P1.0 should be enabled.
14
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Table 4. Terminal Functions (continued)
TERMINAL
(1)
NO.
DA
I/O
DESCRIPTION
NAME
RHA RGE
PW
YFF
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TA1 CCR2 capture: CCI2A input, compare: Out2
Slave transmit enable – eUSCI_B0 SPI mode
Analog input A3 – ADC (not available on devices without ADC)
Comparator_D input CD3
P1.3/TA1.2/UCB0STE/
A3/CD3
8
4
12
8
A4
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TB0 CCR1 capture: CCI1A input, compare: Out1
Slave transmit enable – eUSCI_A0 SPI mode
Analog input A4 – ADC (not available on devices without ADC)
Comparator_D input CD4
P1.4/TB0.1/UCA0STE/
A4/CD4
9
5
13
9
B4
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TB0 CCR2 capture: CCI2A input, compare: Out2
P1.5/TB0.2/UCA0CLK/
A5/CD5
10
6
14
10
A5
I/O
Clock signal input – eUSCI_B0 SPI slave mode, Clock signal
output – eUSCI_B0 SPI master mode
Analog input A5 – ADC (not available on devices without ADC)
Comparator_D input CD5
General-purpose digital I/O
Test data output port
PJ.0/TDO/TB0OUTH/
SMCLK/CD6
11
12
7
8
15
16
11
12
C3
B5
I/O
I/O
(3)
Switch all PWM outputs high impedance input – TB0
SMCLK output
Comparator_D input CD6
General-purpose digital I/O
Test data input or test clock input
PJ.1/TDI/TCLK/TB1OUTH/
Switch all PWM outputs high impedance input – TB1 (not available
on devices without TB1)
(3)
MCLK/CD7
MCLK output
Comparator_D input CD7
General-purpose digital I/O
Test mode select
PJ.2/TMS/TB2OUTH/
ACLK/CD8
Switch all PWM outputs high impedance input – TB2 (not available
on devices without TB2)
13
14
9
17
18
13
14
C4
C5
I/O
I/O
(3)
ACLK output
Comparator_D input CD8
General-purpose digital I/O
Test clock
(3)
PJ.3/TCK/CD9
10
Comparator_D input CD9
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options PW, RGE)
P4.0/TB2.0
P4.1
15
16
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
I/O
I/O
TB2 CCR0 capture: CCI0B input, compare: Out0 (not available on
devices without TB2 or package options DA, PW, RGE)
General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not
available on package options DA, PW, RGE)
(3) See JTAG Operation for use with JTAG function.
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Table 4. Terminal Functions (continued)
TERMINAL
(1)
NO.
I/O
DESCRIPTION
NAME
RHA RGE
DA
PW
YFF
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P2.5/TB0.0/UCA1TXD/
UCA1SIMO
17
18
N/A
19
15
N/A
I/O
TB0 CCR0 capture: CCI0A input, compare: Out0
Transmit data – eUSCI_A1 UART mode, Slave in, master out –
eUSCI_A1 SPI mode (not available on devices without UCSI_A1)
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P2.6/TB1.0/UCA1RXD/
UCA1SOMI
TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on
devices without TB1)
N/A
20
16
N/A
I/O
Receive data – eUSCI_A1 UART mode, Slave out, master in –
eUSCI_A1 SPI mode (not available on devices without UCSI_A1)
Test mode pin – enable JTAG pins
Spy-Bi-Wire input clock
(3) (4)
TEST/SBWTCK
19
20
11
12
21
22
17
18
D5
D4
I
Reset input active low
(3) (4)
RST/NMI/SBWTDIO
I/O
Non-maskable interrupt input
Spy-Bi-Wire data input/output
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TB2 CCR0 capture: CCI0A input, compare: Out0 (not available on
devices without TB2)
P2.0/TB2.0/UCA0TXD/
UCA0SIMO/TB0CLK/ACLK
21
13
23
19
E5
I/O
(4)
Transmit data – eUSCI_A0 UART mode, Slave in, master out –
eUSCI_A0 SPI mode
TB0 clock input
ACLK output
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TB2 CCR1 capture: CCI1A input, compare: Out1 (not available on
devices without TB2)
P2.1/TB2.1/UCA0RXD/
UCA0SOMI/TB0.0
22
23
24
14
24
25
26
20
D3
I/O
I/O
I/O
(5)
Receive data – eUSCI_A0 UART mode, Slave out, master in –
eUSCI_A0 SPI mode
TB0 CCR0 capture: CCI0A input, compare: Out0
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TB2 CCR2 capture: CCI2A input, compare: Out2 (not available on
devices without TB2)
P2.2/TB2.2/UCB0CLK/ TB1.0
15
21
E4
Clock signal input – eUSCI_B0 SPI slave mode, Clock signal
output – eUSCI_B0 SPI master mode
TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on
devices without TB1)
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options PW, RGE)
TB1 CCR1 capture: CCI1B input, compare: Out1 (not available on
devices without TB1)
P3.4/TB1.1/TB2CLK/ SMCLK
N/A
N/A
N/A
TB2 clock input (not available on devices without TB2 or package
options PW, RGE)
SMCLK output (not available on package options PW, RGE)
(4) See Bootstrap Loader (BSL) and JTAG Operation for use with BSL and JTAG functions.
(5) See Bootstrap Loader (BSL) and JTAG Operation for use with BSL and JTAG functions.
16
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SLAS639D –JULY 2011–REVISED AUGUST 2012
Table 4. Terminal Functions (continued)
TERMINAL
(1)
NO.
DA
I/O
DESCRIPTION
NAME
RHA RGE
PW
YFF
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options PW, RGE)
P3.5/TB1.2/CDOUT
25
N/A
27
N/A
N/A
I/O
TB1 CCR2 capture: CCI2B input, compare: Out2 (not available on
devices without TB1)
Comparator_D output (not available on package options PW, RGE)
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options PW, RGE)
TB2 CCR1 capture: CCI1B input, compare: Out1 (not available on
devices without TB2)
P3.6/TB2.1/TB1CLK
26
27
N/A
N/A
28
29
N/A
N/A
N/A
N/A
I/O
I/O
TB1 clock input (not available on devices without TB1 or package
options PW, RGE)
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options PW, RGE)
P3.7/TB2.2
TB2 CCR2 capture: CCI2B input, compare: Out2 (not available on
devices without TB2 or package options PW, RGE)
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TB1 CCR1 capture: CCI1A input, compare: Out1 (not available on
devices without TB1)
P1.6/TB1.1/UCB0SIMO/
UCB0SDA/TA0.0
28
16
30
22
E2
I/O
Slave in, master out – eUSCI_B0 SPI mode
I2C data – eUSCI_B0 I2C mode
TA0 CCR0 capture: CCI0A input, compare: Out0
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TB1 CCR2 capture: CCI2A input, compare: Out2 (not available on
devices without TB1)
P1.7/TB1.2/UCB0SOMI/
UCB0SCL/TA1.0
29
17
31
23
E3
I/O
Slave out, master in – eUSCI_B0 SPI mode
I2C clock – eUSCI_B0 I2C mode
TA1 CCR0 capture: CCI0A input, compare: Out0
Regulated core power supply (internal use only, no external current loading)
Digital ground supply
(6)
VCORE
30
31
32
18
19
20
32
33
34
24
25
26
E1
D2
D1
DVSS
DVCC
Digital power supply
General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not
available on package options PW, RGE)
P2.7
33
N/A
35
N/A
N/A
I/O
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options RGE)
TA0 CCR0 capture: CCI0B input, compare: Out0 (not available on
package options RGE)
P2.3/TA0.0/UCA1STE/
A6/CD10
34
N/A
36
27
N/A
Slave transmit enable – eUSCI_A1 SPI mode (not available on
devices without eUSCI_A1)
Analog input A6 – ADC (not available on devices without ADC)
Comparator_D input CD10 (not available on package options RGE)
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options RGE)
TA1 CCR0 capture: CCI0B input, compare: Out0 (not available on
package options RGE)
P2.4/TA1.0/UCA1CLK/
A7/CD11
35
N/A
37
28
N/A
I/O
Clock signal input – eUSCI_A1 SPI slave mode, Clock signal
output – eUSCI_A1 SPI master mode (not available on devices
without eUSCI_A1)
Analog input A7 – ADC (not available on devices without ADC)
Comparator_D input CD11 (not available on package options RGE)
(6) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE
.
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Table 4. Terminal Functions (continued)
TERMINAL
(1)
NO.
I/O
DESCRIPTION
NAME
RHA RGE
DA
PW
YFF
AVSS
36
N/A
38
N/A
B3
Analog ground supply
General-purpose digital I/O
PJ.4/XIN
37
21
1
2
1
2
C1
B1
I/O
Input terminal for crystal oscillator XT1
General-purpose digital I/O
PJ.5/XOUT
38
22
I/O
Output terminal of crystal oscillator XT1
Analog ground supply
AVSS
39
40
23
24
3
4
3
4
C2
B2
AVCC
Analog power supply
QFN Pad
Pad
Pad
N/A
N/A
N/A
QFN package pad. Connection to VSS recommended.
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SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,
other than program-flow instructions, are performed as register operations in conjunction with seven addressing
modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant
generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes and
additional instructions for the expanded address range. Each instruction can operate on word and byte data.
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Operating Modes
The MSP430 has one active mode and seven software-selectable low-power modes of operation. An interrupt
event can wake up the device from low-power modes LPM0 through LPM4, service the request, and restore back
to the low-power mode on return from the interrupt program. Low-power modes LPM3.5 and LPM4.5 disable the
core supply to minimize power consumption.
The following eight operating modes can be configured by software:
•
Active mode (AM)
All clocks are active
Low-power mode 0 (LPM0)
–
•
–
–
–
CPU is disabled
ACLK active, MCLK disabled, SMCLK optionally active
Complete data retention
•
•
•
Low-power mode 1 (LPM1)
–
–
–
–
CPU is disabled
ACLK active, MCLK disabled, SMCLK optionally active
DCO disabled
Complete data retention
Low-power mode 2 (LPM2)
–
–
–
–
CPU is disabled
ACLK active, MCLK disabled, SMCLK optionally active
DCO disabled
Complete data retention
Low-power mode 3 (LPM3)
–
–
–
–
CPU is disabled
ACLK active, MCLK and SMCLK disabled
DCO disabled
Complete data retention
•
•
Low-power mode 4 (LPM4)
–
–
–
CPU is disabled
ACLK, MCLK, SMCLK disabled
Complete data retention
Low-power mode 3.5 (LPM3.5)
–
–
–
–
–
RTC operation
Internal regulator disabled
No data retention
I/O pad state retention
Wake up from RST, general-purpose I/O, RTC events
•
Low-power mode 4.5 (LPM4.5)
–
–
–
–
Internal regulator disabled
No data retention
I/O pad state retention
Wake up from RST and general-purpose I/O
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Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 5. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
System Reset
Power-Up, Brownout, Supply
Supervisors
SVSLIFG, SVSHIFG
PMMRSTIFG
External Reset RST
WDTIFG
Watchdog Timeout (Watchdog
mode)
WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
DBDIFG
Reset
0FFFEh
63, highest
WDT, FRCTL MPU, CS, PMM
Password Violation
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
FRAM double bit error detection
MPU segment violation
Software POR, BOR
PMMPORIFG, PMMBORIFG
(1) (2)
(SYSRSTIV)
System NMI
Vacant Memory Access
JTAG Mailbox
FRAM access time error
Access violation
VMAIFG
JMBNIFG, JMBOUTIFG
ACCTIMIFG
(Non)maskable
(Non)maskable
0FFFCh
0FFFAh
62
61
ACCVIFG
SBDIFG, DBDIFG
FRAM single, double bit error
detection
(1)
(SYSSNIV)
User NMI
External NMI
Oscillator Fault
NMIIFG, OFIFG
(SYSUNIV)
(1) (2)
Comparator_D interrupt flags
Comparator_D
TB0
Maskable
Maskable
0FFF8h
0FFF6h
60
59
(1) (3)
(CBIV)
(3)
TB0CCR0 CCIFG0
TB0CCR1 CCIFG1 to TB0CCR2 CCIFG2,
TB0IFG
TB0
Maskable
Maskable
0FFF4h
0FFF2h
58
57
(1) (3)
(TB0IV)
Watchdog Timer
(Interval Timer Mode)
WDTIFG
UCA0RXIFG, UCA0TXIFG (SPI mode)
UCA0STTIFG, UCA0TXCPTIFG, UCA0RXIFG,
UXA0TXIFG (UART mode)
eUSCI_A0 Receive and Transmit
eUSCI_B0 Receive and Transmit
ADC10_B
Maskable
Maskable
Maskable
0FFF0h
0FFEEh
0FFECh
56
55
54
(1) (3)
(UCA0IV)
UCB0STTIFG, UCB0TXCPTIFG, UCB0RXIFG,
UCB0TXIFG (SPI mode)
UCB0ALIFG, UCB0NACKIFG, UCB0STTIFG,
UCB0STPIFG, UCB0RXIFG0, UCB0TXIFG0,
UCB0RXIFG1, UCB0TXIFG1, UCB0RXIFG2,
UCB0TXIFG2, UCB0RXIFG3, UCB0TXIFG3,
UCB0CNTIFG, UCB0BIT9IFG (I2C mode)
(1) (3)
(UCB0IV)
ADC10OVIFG, ADC10TOVIFG, ADC10HIIFG,
ADC10LOIFG
ADC10INIFG, ADC10IFG0
(1) (3) (4)
(ADC10IV)
(3)
TA0
TA0
TA0CCR0 CCIFG0
Maskable
Maskable
0FFEAh
0FFE8h
53
52
TA0CCR1 CCIFG1 to TA0CCR2 CCIFG2,
TA0IFG
(1) (3)
(TA0IV)
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(3) Interrupt flags are located in the module.
(4) Only on devices with ADC, otherwise reserved.
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Table 5. Interrupt Sources, Flags, and Vectors (continued)
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
UCA1RXIFG, UCA1TXIFG (SPI mode)
UCA1STTIFG, UCA1TXCPTIFG, UCA1RXIFG,
UXA1TXIFG (UART mode)
eUSCI_A1 Receive and Transmit
Maskable
0FFE6h
51
(1) (3)
(UCA1IV)
DMA0IFG, DMA1IFG, DMA2IFG
DMA
TA1
Maskable
Maskable
0FFE4h
0FFE2h
50
49
(1) (3)
(DMAIV)
(3)
TA1CCR0 CCIFG0
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG
TA1
Maskable
0FFE0h
48
(1) (3)
(TA1IV)
P1IFG.0 to P1IFG.7
I/O Port P1
TB1
Maskable
Maskable
0FFDEh
0FFDCh
47
46
(1) (3)
(P1IV)
(3)
TB1CCR0 CCIFG0
TB1CCR1 CCIFG1 to TB1CCR2 CCIFG2,
TB1IFG
TB1
Maskable
0FFDAh
45
(1) (3)
(TB1IV)
P2IFG.0 to P2IFG.7
I/O Port P2
TB2
Maskable
Maskable
0FFD8h
0FFD6h
44
43
(1) (3)
(P2IV)
(3)
TB2CCR0 CCIFG0
TB2CCR1 CCIFG1 to TB2CCR2 CCIFG2,
TB2IFG
TB2
Maskable
0FFD4h
42
(1) (3)
(TB2IV)
P3IFG.0 to P3IFG.7
I/O Port P3
I/O Port P4
Maskable
Maskable
0FFD2h
0FFD0h
41
40
(5) (6)
(P3IV)
P4IFG.0 to P4IFG.2
(5) (6)
(P4IV)
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG, RTCOFIFG
RTC_B
Maskable
0FFCEh
39
(5) (6)
(RTCIV)
0FFCCh
⋮
38
(7)
Reserved
Reserved
⋮
0FF80h
0, lowest
(5) Multiple source flags
(6) Interrupt flags are located in the module.
(7) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
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Memory Organization
(1) (2)
Table 6. Memory Organization
MSP430FR5726
MSP430FR5727
MSP430FR5728
MSP430FR5729
MSP430FR5736
MSP430FR5737
MSP430FR5738
MSP430FR5739
MSP430FR5722
MSP430FR5723
MSP430FR5724
MSP430FR5725
MSP430FR5732
MSP430FR5733
MSP430FR5734
MSP430FR5735
MSP430FR5720
MSP430FR5721
MSP430FR5730
MSP430FR5731
Memory (FRAM)
Total Size
15.5 KB
8.0 KB
4 KB
Main: interrupt vectors
Main: code memory
00FFFFh–00FF80h
00FF7Fh–00C200h
00FFFFh–00FF80h
00FF7Fh–00E000h
00FFFFh–00FF80h
00FF7Fh–00F000h
1 KB
001FFFh–001C00h
1 KB
001FFFh–001C00h
1 KB
001FFFh–001C00h
RAM
Device Descriptor Info
(TLV) (FRAM)
128 B
001A7Fh–001A00h
128 B
001A7Fh–001A00h
128 B
001A7Fh–001A00h
N/A
N/A
0019FFh–001980h
Address space mirrored to
Info A
0019FFh–001980h
Address space mirrored to
Info A
0019FFh–001980h
Address space mirrored to
Info A
00197Fh–001900h
Address space mirrored to
Info B
00197Fh–001900h
Address space mirrored to
Info B
00197Fh–001900h
Address space mirrored to
Info B
Information memory
(FRAM)
Info A
Info B
BSL 3
BSL 2
BSL 1
BSL 0
Size
128 B
0018FFh–001880h
128 B
0018FFh–001880h
128 B
0018FFh–001880h
128 B
00187Fh–001800h
128 B
00187Fh–001800h
128 B
00187Fh–001800h
512 B
0017FFh–001600h
512 B
0017FFh–001600h
512 B
0017FFh–001600h
512 B
0015FFh–001400h
512 B
0015FFh–001400h
512 B
0015FFh–001400h
Bootstrap loader (BSL)
memory (ROM)
512 B
0013FFh–001200h
512 B
0013FFh–001200h
512 B
0013FFh–001200h
512 B
0011FFh–001000h
512 B
0011FFh–001000h
512 B
0011FFh–001000h
4 KB
000FFFh–0h
4 KB
000FFFh–0h
4 KB
000FFFh–0h
Peripherals
(1) N/A = Not available
(2) All address space not listed in this table is considered vacant memory.
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Bootstrap Loader (BSL)
The BSL enables users to program the FRAM or RAM using a UART serial interface. Access to the device
memory by the BSL is protected by an user-defined password. Use of the BSL requires four pins as shown in
Table 7. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For
complete description of the features of the BSL and its implementation, see the MSP430 Programming Via the
Bootstrap Loader User's Guide (SLAU319).
Table 7. BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
Entry sequence signal
Entry sequence signal
Data transmit
RST/NMI/SBWTDIO
TEST/SBWTCK
P2.0
P2.1
VCC
VSS
Data receive
Power supply
Ground supply
JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface, which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. The JTAG pin requirements are shown in Table 8. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's
Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see
MSP430 Programming Via the JTAG Interface (SLAU320).
Table 8. JTAG Pin Requirements and Functions
DEVICE SIGNAL
PJ.3/TCK
DIRECTION
FUNCTION
JTAG clock input
JTAG state control
JTAG data input, TCLK input
JTAG data output
Enable JTAG pins
External reset
IN
IN
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
IN
OUT
IN
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
IN
Power supply
VSS
Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two-wire Spy-Bi-Wire interface. Spy-
Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire
interface pin requirements are shown in Table 9. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of
the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface
(SLAU320).
Table 9. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
DIRECTION
IN
FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input and output
Power supply
IN, OUT
VSS
Ground supply
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FRAM
The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU.
Features of the FRAM include:
•
•
•
•
Low-power ultrafast write nonvolatile memory
Byte and word access capability
Programmable and automated wait state generation
Error Correction Coding (ECC) with single bit detection and correction, double bit detection
Memory Protection Unit (MPU)
The FRAM can be protected from inadvertent CPU execution or write access by the MPU. Features of the MPU
include:
•
•
•
Main memory partitioning programmable up to three segments
Each segment's (main and information memory) access rights can be individually selected
Access violation flags with interrupt capability for easy servicing of access violations
Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430FR57xx Family User's Guide (SLAU272).
Digital I/O
There are up to four 8-bit I/O ports implemented:
•
•
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Programmable pullup or pulldown on all ports.
Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for all ports.
Read/write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise or word-wise in pairs.
Oscillator and Clock System (CS)
The clock system includes support for a 32-kHz watch crystal oscillator XT1 (LF mode), an internal very-low-
power low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a high-
frequency crystal oscillator XT1 (HF mode). The clock system module is designed to meet the requirements of
both low system cost and low power consumption. A fail-safe mechanism exists for all crystal sources. The clock
system module provides the following clock signals:
•
•
•
Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1 LF mode), a high-frequency crystal (XT1
HF mode), the internal VLO, or the internal DCO.
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by the same sources made
available to ACLK.
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
the same sources made available to ACLK.
Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM also
includes supply voltage supervisor (SVS) and brownout protection. The brownout circuit is implemented to
provide the proper internal reset signal to the device during power-on and power-off. The SVS circuitry detects if
the supply voltage drops below a user-selectable safe level. SVS circuitry is available on the primary and core
supplies.
Hardware Multiplier (MPY)
The multiplication operation is supported by a dedicated peripheral module. The module performs operations with
32-bit, 24-bit, 16-bit, and 8-bit operands. The module supports signed and unsigned multiplication as well as
signed and unsigned multiply-and-accumulate operations.
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Real-Time Clock (RTC_B)
The RTC_B module contains an integrated real-time clock (RTC) (calendar mode). Calendar mode integrates an
internal calendar which compensates for months with fewer than 31 days and includes leap year correction. The
RTC_B also supports flexible alarm functions and offset-calibration hardware. RTC operation is available in
LPM3.5 mode to minimize power consumption.
Watchdog Timer (WDT_A)
The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
System Module (SYS)
The SYS module handles many of the system functions within the device. These include power-on reset (POR)
and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector generators,
bootstrap loader entry mechanisms, and configuration management (device descriptors). It also includes a data
exchange mechanism using JTAG called a JTAG mailbox that can be used in the application.
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Table 10. System Module Interrupt Vector Registers
INTERRUPT VECTOR
REGISTER
ADDRESS
INTERRUPT EVENT
VALUE
PRIORITY
SYSRSTIV,
System Reset
019Eh
No interrupt pending
Brownout (BOR)
00h
02h
Highest
RSTIFG RST/NMI (BOR)
04h
PMMSWBOR software BOR (BOR)
LPMx.5 wake up (BOR)
06h
08h
Security violation (BOR)
0Ah
SVSLIFG SVSL event (BOR)
SVSHIFG SVSH event (BOR)
Reserved
0Ch
0Eh
10h
Reserved
12h
PMMSWPOR software POR (POR)
WDTIFG watchdog timeout (PUC)
WDTPW password violation (PUC)
FRCTLPW password violation (PUC)
DBDIFG FRAM double bit error (PUC)
Peripheral area fetch (PUC)
PMMPW PMM password violation (PUC)
MPUPW MPU password violation (PUC)
CSPW CS password violation (PUC)
MPUSEGIIFG information memory segment violation (PUC)
MPUSEG1IFG segment 1 memory violation (PUC)
MPUSEG2IFG segment 2 memory violation (PUC)
MPUSEG3IFG segment 3 memory violation (PUC)
Reserved
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
Reserved
30h to 3Eh
00h
Lowest
Highest
SYSSNIV, System NMI
019Ch
No interrupt pending
DBDIFG FRAM double bit error
ACCTIMIFG access time error
ACCVIFG access violation
VMAIFG Vacant memory access
JMBINIFG JTAG mailbox input
JMBOUTIFG JTAG mailbox output
SBDIFG FRAM single bit error
Reserved
02h
04h
0Eh
10h
12h
14h
16h
18h to 1Eh
00h
Lowest
Highest
SYSUNIV, User NMI
019Ah
No interrupt pending
NMIFG NMI pin
02h
OFIFG oscillator fault
04h
Reserved
06h
Reserved
08h
Reserved
0Ah to 1Eh
Lowest
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DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU intervention. For
example, the DMA controller can be used to move data from the ADC10_B conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or
from a peripheral.
(1)
Table 11. DMA Trigger Assignments
TRIGGER
0
CHANNEL 0
DMAREQ
CHANNEL 1
DMAREQ
CHANNEL 2
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
Reserved
2
3
4
5
6
Reserved
Reserved
Reserved
7
TB0CCR0 CCIFG
TB0CCR2 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
8
(2)
(2)
(2)
9
TB1CCR0 CCIFG
TB1CCR2 CCIFG
TB2CCR0 CCIFG
TB2CCR2 CCIFG
Reserved
TB1CCR0 CCIFG
TB1CCR2 CCIFG
TB2CCR0 CCIFG
TB2CCR2 CCIFG
Reserved
TB1CCR0 CCIFG
TB1CCR2 CCIFG
TB2CCR0 CCIFG
TB2CCR2 CCIFG
Reserved
(2)
(3)
(3)
(2)
(3)
(3)
(2)
(3)
(3)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
UCA0RXIFG
UCA0RXIFG
UCA0RXIFG
UCA0TXIFG
UCA0TXIFG
UCA0TXIFG
(4)
(4)
(4)
UCA1RXIFG
UCA1RXIFG
UCA1RXIFG
(4)
(4)
(4)
UCA1TXIFG
UCA1TXIFG
UCA1TXIFG
UCB0RXIFG0
UCB0TXIFG0
UCB0RXIFG1
UCB0TXIFG1
UCB0RXIFG2
UCB0TXIFG2
UCB0RXIFG3
UCB0TXIFG3
UCB0RXIFG0
UCB0TXIFG0
UCB0RXIFG1
UCB0TXIFG1
UCB0RXIFG2
UCB0TXIFG2
UCB0RXIFG3
UCB0TXIFG3
UCB0RXIFG0
UCB0TXIFG0
UCB0RXIFG1
UCB0TXIFG1
UCB0RXIFG2
UCB0TXIFG2
UCB0RXIFG3
UCB0TXIFG3
(5)
(5)
(5)
ADC10IFGx
ADC10IFGx
ADC10IFGx
Reserved
Reserved
MPY ready
DMA2IFG
Reserved
Reserved
MPY ready
DMA0IFG
Reserved
Reserved
MPY ready
DMA1IFG
(6)
(6)
(6)
DMAE0
DMAE0
DMAE0
(1) If a reserved trigger source is selected, no trigger is generated.
(2) Only on devices with TB1, otherwise reserved
(3) Only on devices with TB2, otherwise reserved
(4) Only on devices with eUSCI_A1, otherwise reserved
(5) Only on devices with ADC, otherwise reserved
(6) This function is not available on YFF package types.
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Enhanced Universal Serial Communication Interface (eUSCI)
The eUSCI modules are used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baudrate detection, and IrDA. Each eUSCI module contains two portions,
A and B.
The eUSCI_An module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, or IrDA.
The eUSCI_Bn module provides support for SPI (3 pin or 4 pin) or I2C.
The MSP430FR572x and MSP430FR573x series include one or two eUSCI_An modules (eUSCI_A0,
eUSCI_A1) and one eUSCI_Bn module (eUSCI_B).
TA0, TA1
TA0 and TA1 are 16-bit timers/counters (Timer_A type) with three capture/compare registers each. Each can
support multiple capture/compares, PWM outputs, and interval timing. Each has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 12. TA0 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
MODULE
BLOCK
RHA
RGE, YFF
DA
PW
RHA
RGE, YFF
DA
PW
3-P1.2,
A3‑P1.2
3-P1.2
7-P1.2
7-P1.2
TA0CLK
TACLK
ACLK
ACLK
(internal)
Timer
CCR0
CCR1
N/A
TA0
TA1
N/A
SMCLK
(internal)
SMCLK
TACLK
CCI0A
3-P1.2,
A3‑P1.2
3-P1.2
7-P1.2
7-P1.2
TA0CLK
TA0.0
16-P1.6,
E2‑P1.6
16-P1.6 ,
E2‑P1.6
28-P1.6
34-P2.3
30-P1.6
36-P2.3
22-P1.6
27-P2.3
28-P1.6
34-P2.3
30-P1.6
36-P2.3
22-P1.6
27-P2.3
N/A
TA0.0
DVSS
DVCC
CCI0B
GND
VCC
N/A
TA0.0
1-P1.0,
N/A
1-P1.0
5-P1.0
5-P1.0
TA0.1
CCI1A
1-P1.0
1-P1.0 , N/A
ADC10
5-P1.0
5-P1.0
ADC10
(internal)
ADC10
(internal)
ADC10
(1)
(1)
(1)
(1)
CDOUT
(internal)
(internal)
(internal)
CCI1B
TA0.1
ADC10SHSx ADC10SHSx ADC10SHSx ADC10SHSx
= {1}
= {1}
= {1}
= {1}
DVSS
DVCC
GND
VCC
2-P1.1,
A2‑P1.1
2-P1.1,
A2‑P1.1
2-P1.1
6-P1.1
6-P1.1
TA0.2
CCI2A
CCI2B
2-P1.1
6-P1.1
6-P1.1
ACLK
(internal)
CCR2
TA2
TA0.2
DVSS
DVCC
GND
VCC
(1) Only on devices with ADC
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Table 13. TA1 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
MODULE
BLOCK
RHA
RGE, YFF
DA
PW
RHA
RGE, YFF
DA
PW
2-P1.1,
A2‑P1.1
2-P1.1
6-P1.1
6-P1.1
TA1CLK
TACLK
ACLK
ACLK
(internal)
Timer
N/A
N/A
SMCLK
(internal)
SMCLK
TACLK
CCI0A
2-P1.1,
A2‑P1.1
2-P1.1
6-P1.1
6-P1.1
TA1CLK
TA1.0
17-P1.7,
E3‑P1.7
17-P1.7,
E3‑P1.7
29-P1.7
35-P2.4
31-P1.7
37-P2.4
23-P1.7
28-P2.4
29-P1.7
35-P2.4
31-P1.7
37-P2.4
23-P1.7
28-P2.4
N/A
TA1.0
DVSS
DVCC
TA1.1
CCI0B
GND
VCC
N/A
CCR0
CCR1
TA0
TA1
TA1.0
TA1.1
3-P1.2
8-P1.3
3-P1.2, N/A
7-P1.2
7-P1.2
8-P1.3
CCI1A
3-P1.2
8-P1.3
3-P1.2, N/A
7-P1.2
7-P1.2
8-P1.3
CDOUT
(internal)
CCI1B
DVSS
DVCC
GND
VCC
4-P1.3,
A4‑P1.3
4-P1.3,
A4‑P1.3
12-P1.3
TA1.2
CCI2A
CCI2B
12-P1.3
ACLK
(internal)
CCR2
TA2
TA1.2
DVSS
DVCC
GND
VCC
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TB0, TB1, TB2
TB0, TB1, and TB2 are 16-bit timers/counters (Timer_B type) with three capture/compare registers each. Each
can support multiple capture/compares, PWM outputs, and interval timing. Each has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 14. TB0 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
MODULE
BLOCK
RHA
RGE, YFF
DA
PW
RHA
RGE, YFF
DA
PW
13-P2.0,
E5‑P2.0
21-P2.0
23-P2.0
19-P2.0
TB0CLK
TBCLK
ACLK
ACLK
(internal)
Timer
N/A
N/A
SMCLK
(internal)
SMCLK
TBCLK
13-P2.0,
E5‑P2.0
21-P2.0
23-P2.0
19-P2.0
TB0CLK
14-P2.1,
D3‑P2.1
14-P2.1,
D3‑P2.1
22-P2.1
17-P2.5
24-P2.1
19-P2.5
20-P2.1
15-P2.5
TB0.0
TB0.0
CCI0A
CCI0B
22-P2.1
17-P2.5
24-P2.1
19-P2.5
20-P2.1
15-P2.5
N/A
N/A
ADC10
(internal)
ADC10
(internal)
ADC10
(internal)
ADC10
(1)
CCR0
TB0
TB0.0
(1)
(1)
(1)
(internal)
DVSS
GND
ADC10SHSx ADC10SHSx ADC10SHSx ADC10SHSx
= {2}
= {2}
= {2}
= {2}
DVCC
VCC
5-P1.4,
B4‑P1.4
5-P1.4,
B4‑P1.4
9-P1.4
13-P1.4
9-P1.4
TB0.1
CCI1A
9-P1.4
13-P1.4
9-P1.4
ADC10
(internal)
ADC10
(internal)
ADC10
(internal)
ADC10
(1)
(1)
(1)
(1)
CDOUT
(internal)
(internal)
CCI1B
CCR1
TB1
TB0.1
ADC10SHSx ADC10SHSx ADC10SHSx ADC10SHSx
= {3}
= {3}
= {3}
= {3}
DVSS
DVCC
GND
VCC
6‑P1.5, A5-
P1.5
6-P1.5,
A5‑P1.5
10-P1.5
14-P1.5
19-P1.5
TB0.2
CCI2A
CCI2B
10-P1.5
14-P1.5
19-P1.5
ACLK
(internal)
CCR2
TB2
TB0.2
DVSS
DVCC
GND
VCC
(1) Only on devices with ADC
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(1)
Table 15. TB1 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
MODULE
BLOCK
RHA
RGE, YFF
DA
PW
RHA
RGE, YFF
DA
PW
N/A (DVSS),
26-P3.6
28-P3.6
N/A (DVSS
)
TB1CLK
TBCLK
ACLK
N/A (DVSS
)
ACLK
(internal)
Timer
N/A
N/A
SMCLK
(internal)
SMCLK
TBCLK
CCI0A
CCI0B
N/A (DVSS),
N/A (DVSS
26-P3.6
23-P2.2
18-P2.6
28-P3.6
25-P2.2
20-P2.6
N/A (DVSS
N/A (DVSS
N/A (DVSS
)
)
)
TB1CLK
TB1.0
)
N/A (DVSS),
N/A (DVSS
23-P2.2
18-P2.6
N/A
N/A
25-P2.2
20-P2.6
N/A
N/A
)
N/A (DVSS),
N/A (DVSS
TB1.0
CCR0
CCR1
CCR2
TB0
TB1
TB2
TB1.0
TB1.1
TB1.2
(1)
)
DVSS
DVCC
GND
VCC
N/A (DVSS),
N/A (DVSS
28-P1.6
24-P3.4
30-P1.6
26-P3.4
N/A (DVSS
N/A (DVSS
)
)
TB1.1
TB1.1
CCI1A
CCI1B
28-P1.6
24-P3.4
N/A
N/A
30-P1.6
26-P3.4
N/A
N/A
)
N/A (DVSS),
N/A (DVSS
)
DVSS
DVCC
GND
VCC
N/A (DVSS),
N/A (DVSS
29-P1.7
25-P3.5
31-P1.7
27-P3.5
N/A (DVSS
N/A (DVSS
)
)
TB1.2
TB1.2
CCI2A
CCI2B
29-P1.7
25-P3.5
N/A
N/A
31-P1.7
27-P3.5
N/A
N/A
)
N/A (DVSS),
N/A (DVSS
)
DVSS
DVCC
GND
VCC
(1) TB1 is not present on all device types.
Table 16. TB2 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
MODULE
BLOCK
RHA
RGE, YFF
DA
PW
RHA
RGE, YFF
DA
PW
N/A (DVSS),
24-P3.4
26-P3.4
N/A (DVSS
)
TB2CLK
TBCLK
ACLK
N/A (DVSS
)
ACLK
(internal)
Timer
N/A
N/A
SMCLK
(internal)
SMCLK
TBCLK
CCI0A
CCI0B
N/A (DVSS),
N/A (DVSS
24-P3.4
21-P2.0
15-P4.0
26-P3.4
23-P2.0
N/A (DVSS
N/A (DVSS
N/A (DVSS
)
)
)
TB2CLK
TB2.0
)
N/A (DVSS),
N/A (DVSS
21-P2.0
15-P4.0
N/A
N/A
23-P2.0
36-P4.0
N/A
N/A
)
N/A (DVSS),
N/A (DVSS
N/A (DVSS
)
TB2.0
CCR0
CCR1
CCR2
TB0
TB1
TB2
TB2.0
TB2.1
TB2.2
)
DVSS
DVCC
GND
VCC
N/A (DVSS),
N/A (DVSS
22-P2.1
26-P3.6
24-P2.1
28-P3.6
N/A (DVSS
N/A (DVSS
)
)
TB2.1
TB2.1
CCI1A
CCI1B
22-P2.1
26-P3.6
N/A
N/A
24-P2.1
28-P3.6
N/A
N/A
)
N/A (DVSS),
N/A (DVSS
)
DVSS
DVCC
GND
VCC
N/A (DVSS),
N/A (DVSS
23-P2.2
27-P3.7
25-P2.2
29-P3.7
N/A (DVSS
N/A (DVSS
)
)
TB2.2
TB2.2
CCI2A
CCI2B
23-P2.2
27-P3.7
N/A
N/A
25-P2.2
29-P3.7
N/A
N/A
)
N/A (DVSS),
N/A (DVSS
)
DVSS
DVCC
GND
VCC
(1) TB2 is not present on all device types.
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ADC10_B
The ADC10_B module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator, and a conversion result buffer. A window comparator with a
lower limit and an upper limit allows CPU-independent result monitoring with three window comparator interrupt
flags.
Comparator_D
The primary function of the Comparator_D module is to support precision slope analog-to-digital conversions,
battery voltage supervision, and monitoring of external analog signals.
CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used for data
checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
Shared Reference (REF)
The reference module (REF) is responsible for generation of all critical reference voltages that can be used by
the various analog peripherals in the device.
Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The S version of the EEM implemented on all devices has the
following features:
•
•
•
•
•
Three hardware triggers or breakpoints on memory access
One hardware trigger or breakpoint on CPU register write access
Up to four hardware triggers can be combined to form complex triggers or breakpoints
One cycle counter
Clock control on module level
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Peripheral File Map
Table 17. Peripherals
OFFSET ADDRESS
RANGE
MODULE NAME
BASE ADDRESS
Special Functions (see Table 18)
PMM (see Table 19)
0100h
0120h
0140h
0150h
015Ch
0160h
0180h
01B0h
0200h
0220h
0320h
0340h
0380h
03C0h
0400h
0440h
04A0h
04C0h
0500h
0510h
0520h
0530h
05A0h
05C0h
05E0h
0640h
0700h
08C0h
000h-01Fh
000h-010h
000h-00Fh
000h-007h
000h-001h
000h-00Fh
000h-01Fh
000h-001h
000h-01Fh
000h-01Fh
000h-01Fh
000h-02Fh
000h-02Fh
000h-02Fh
000h-02Fh
000h-02Fh
000h-01Fh
000h-02Fh
000h-00Fh
000h-00Ah
000h-00Ah
000h-00Ah
000h-00Fh
000h-01Fh
000h-01Fh
000h-02Fh
000h-03Fh
000h-00Fh
FRAM Control (see Table 20)
CRC16 (see Table 21)
Watchdog (see Table 22)
CS (see Table 23)
SYS (see Table 24)
Shared Reference (see Table 25)
Port P1/P2 (see Table 26)
Port P3/P4 (see Table 27)
Port PJ (see Table 28)
TA0 (see Table 29)
TA1 (see Table 30)
TB0 (see Table 31)
TB1 (see Table 32)
TB2 (see Table 33)
Real-Time Clock (RTC_B) (see Table 34)
32-Bit Hardware Multiplier (see Table 35)
DMA General Control (see Table 36)
DMA Channel 0 (see Table 36)
DMA Channel 1 (see Table 36)
DMA Channel 2 (see Table 36)
MPU Control (see Table 37)
eUSCI_A0 (see Table 38)
eUSCI_A1 (see Table 39)
eUSCI_B0 (see Table 40)
ADC10_B (see Table 41)
Comparator_D (see Table 42)
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Table 18. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
SFRIE1
OFFSET
OFFSET
OFFSET
OFFSET
SFR interrupt enable
SFR interrupt flag
00h
02h
04h
SFRIFG1
SFR reset pin control
SFRRPCR
Table 19. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
PMMCTL0
PMM Control 0
PMM interrupt flags
PM5 Control 0
00h
0Ah
10h
PMMIFG
PM5CTL0
Table 20. FRAM Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
FRCTLCTL0
FRAM control 0
General control 0
General control 1
00h
04h
06h
GCCTL0
GCCTL1
Table 21. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
CRC16DI
CRC data input
00h
02h
04h
06h
CRC data input reverse byte
CRC initialization and result
CRC result reverse byte
CRCDIRB
CRCINIRES
CRCRESR
Table 22. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
REGISTER
WDTCTL
OFFSET
OFFSET
Watchdog timer control
00h
Table 23. CS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
CS control 0
CS control 1
CS control 2
CS control 3
CS control 4
CS control 5
CS control 6
CSCTL0
CSCTL1
CSCTL2
CSCTL3
CSCTL4
CSCTL5
CSCTL6
00h
02h
04h
06h
08h
0Ah
0Ch
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Table 24. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
SYSCTL
OFFSET
System control
00h
06h
08h
0Ah
0Ch
0Eh
18h
1Ah
1Ch
1Eh
JTAG mailbox control
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
Bus Error vector generator
User NMI vector generator
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSBERRIV
SYSUNIV
System NMI vector generator
Reset vector generator
SYSSNIV
SYSRSTIV
Table 25. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
REGISTER
REFCTL
OFFSET
OFFSET
Shared reference control
00h
Table 26. Port P1/P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
Port P1 input
P1IN
00h
02h
04h
06h
0Ah
0Ch
0Eh
16h
18h
1Ah
1Ch
01h
03h
05h
07h
0Bh
0Dh
17h
1Eh
19h
1Bh
1Dh
Port P1 output
Port P1 direction
P1OUT
P1DIR
P1REN
Port P1 pullup/pulldown enable
Port P1 selection 0
P1SEL0
P1SEL1
P1IV
Port P1 selection 1
Port P1 interrupt vector word
Port P1 complement selection
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
P1SELC
P1IES
P1IE
P1IFG
P2IN
Port P2 input
Port P2 output
P2OUT
P2DIR
P2REN
P2SEL0
P2SEL1
P2SELC
P2IV
Port P2 direction
Port P2 pullup/pulldown enable
Port P2 selection 0
Port P2 selection 1
Port P2 complement selection
Port P2 interrupt vector word
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
P2IES
P2IE
P2IFG
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Table 27. Port P3/P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
02h
04h
06h
0Ah
0Ch
0Eh
16h
18h
1Ah
1Ch
01h
03h
05h
07h
0Bh
0Dh
17h
1Eh
19h
1Bh
1Dh
Port P3 output
Port P3 direction
P3OUT
P3DIR
P3REN
Port P3 pullup/pulldown enable
Port P3 selection 0
P3SEL0
P3SEL1
P3IV
Port P3 selection 1
Port P3 interrupt vector word
Port P3 complement selection
Port P3 interrupt edge select
Port P3 interrupt enable
Port P3 interrupt flag
P3SELC
P3IES
P3IE
P3IFG
P4IN
Port P4 input
Port P4 output
P4OUT
P4DIR
P4REN
P4SEL0
P4SEL1
P4SELC
P4IV
Port P4 direction
Port P4 pullup/pulldown enable
Port P4 selection 0
Port P4 selection 1
Port P4 complement selection
Port P4 interrupt vector word
Port P4 interrupt edge select
Port P4 interrupt enable
Port P4 interrupt flag
P4IES
P4IE
P4IFG
Table 28. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
02h
04h
06h
0Ah
0Ch
16h
Port PJ output
PJOUT
PJDIR
PJREN
Port PJ direction
Port PJ pullup/pulldown enable
Port PJ selection 0
Port PJ selection 1
Port PJ complement selection
PJSEL0
PJSEL1
PJSELC
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Table 29. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
TA0CTL
OFFSET
TA0 control
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA0 counter register
TA0CCTL0
TA0CCTL1
TA0CCTL2
TA0R
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
TA0 expansion register 0
TA0 interrupt vector
TA0CCR0
TA0CCR1
TA0CCR2
TA0EX0
TA0IV
Table 30. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
TA1CTL
OFFSET
TA1 control
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA1 counter register
TA1CCTL0
TA1CCTL1
TA1CCTL2
TA1R
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
TA1 expansion register 0
TA1 interrupt vector
TA1CCR0
TA1CCR1
TA1CCR2
TA1EX0
TA1IV
Table 31. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
TB0CTL
OFFSET
TB0 control
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TB0 register
TB0CCTL0
TB0CCTL1
TB0CCTL2
TB0R
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
TB0 expansion register 0
TB0 interrupt vector
TB0CCR0
TB0CCR1
TB0CCR2
TB0EX0
TB0IV
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Table 32. TB1 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
TB1CTL
OFFSET
TB1 control
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TB1 register
TB1CCTL0
TB1CCTL1
TB1CCTL2
TB1R
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
TB1 expansion register 0
TB1 interrupt vector
TB1CCR0
TB1CCR1
TB1CCR2
TB1EX0
TB1IV
Table 33. TB2 Registers (Base Address: 0440h)
REGISTER DESCRIPTION
REGISTER
TB2CTL
OFFSET
TB2 control
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TB2 register
TB2CCTL0
TB2CCTL1
TB2CCTL2
TB2R
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
TB2 expansion register 0
TB2 interrupt vector
TB2CCR0
TB2CCR1
TB2CCR2
TB2EX0
TB2IV
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Table 34. Real-Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
RTCCTL0
OFFSET
RTC control 0
00h
01h
02h
03h
08h
0Ah
0Ch
0Dh
0Eh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Eh
RTC control 1
RTCCTL1
RTC control 2
RTCCTL2
RTC control 3
RTCCTL3
RTC prescaler 0 control
RTC prescaler 1 control
RTC prescaler 0
RTCPS0CTL
RTCPS1CTL
RTCPS0
RTC prescaler 1
RTCPS1
RTC interrupt vector word
RTC seconds, RTC counter register 1
RTC minutes, RTC counter register 2
RTC hours, RTC counter register 3
RTC day of week, RTC counter register 4
RTC days
RTCIV
RTCSEC, RTCNT1
RTCMIN, RTCNT2
RTCHOUR, RTCNT3
RTCDOW, RTCNT4
RTCDAY
RTC month
RTCMON
RTC year low
RTCYEARL
RTCYEARH
RTCAMIN
RTC year high
RTC alarm minutes
RTC alarm hours
RTCAHOUR
RTCADOW
RTCADAY
RTC alarm day of week
RTC alarm days
Binary-to-BCD conversion register
BCD-to-binary conversion register
BIN2BCD
BCD2BIN
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Table 35. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
16-bit operand 1 – signed multiply
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
MPYS
MAC
MACS
OP2
16 × 16 result low word
RESLO
RESHI
16 × 16 result high word
16 × 16 sum extension register
SUMEXT
MPY32L
MPY32H
MPYS32L
MPYS32H
MAC32L
MAC32H
MACS32L
MACS32H
OP2L
32-bit operand 1 – multiply low word
32-bit operand 1 – multiply high word
32-bit operand 1 – signed multiply low word
32-bit operand 1 – signed multiply high word
32-bit operand 1 – multiply accumulate low word
32-bit operand 1 – multiply accumulate high word
32-bit operand 1 – signed multiply accumulate low word
32-bit operand 1 – signed multiply accumulate high word
32-bit operand 2 – low word
32-bit operand 2 – high word
OP2H
32 × 32 result 0 – least significant word
32 × 32 result 1
RES0
RES1
32 × 32 result 2
RES2
32 × 32 result 3 – most significant word
MPY32 control register 0
RES3
MPY32CTL0
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Table 36. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTION
REGISTER
DMA0CTL
OFFSET
DMA channel 0 control
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
DMA channel 0 source address low
DMA channel 0 source address high
DMA channel 0 destination address low
DMA channel 0 destination address high
DMA channel 0 transfer size
DMA0SAL
DMA0SAH
DMA0DAL
DMA0DAH
DMA0SZ
DMA channel 1 control
DMA1CTL
DMA1SAL
DMA1SAH
DMA1DAL
DMA1DAH
DMA1SZ
DMA channel 1 source address low
DMA channel 1 source address high
DMA channel 1 destination address low
DMA channel 1 destination address high
DMA channel 1 transfer size
DMA channel 2 control
DMA2CTL
DMA2SAL
DMA2SAH
DMA2DAL
DMA2DAH
DMA2SZ
DMA channel 2 source address low
DMA channel 2 source address high
DMA channel 2 destination address low
DMA channel 2 destination address high
DMA channel 2 transfer size
DMA module control 0
DMACTL0
DMACTL1
DMACTL2
DMACTL3
DMACTL4
DMAIV
DMA module control 1
DMA module control 2
DMA module control 3
DMA module control 4
DMA interrupt vector
Table 37. MPU Control Registers (Base Address: 05A0h)
REGISTER DESCRIPTION
REGISTER
MPUCTL0
OFFSET
MPU control 0
00h
02h
04h
06h
MPU control 1
MPUCTL1
MPUSEG
MPUSAM
MPU Segmentation Register
MPU access management
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Table 38. eUSCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
UCA0CTLW0
OFFSET
eUSCI_A control word 0
eUSCI _A control word 1
eUSCI_A baud rate 0
eUSCI_A baud rate 1
eUSCI_A modulation control
eUSCI_A status
00h
03h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
UCA0CTLW1
UCA0BR0
UCA0BR1
UCA0MCTLW
UCA0STAT
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
UCA0IRTCTL
UCA0IRRCTL
UCA0IE
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
UCA0IFG
eUSCI_A interrupt vector word
UCA0IV
Table 39. eUSCI_A1 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
REGISTER
UCA1CTLW0
OFFSET
eUSCI_A control word 0
eUSCI _A control word 1
eUSCI_A baud rate 0
00h
03h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
UCA1CTLW1
UCA1BR0
eUSCI_A baud rate 1
UCA1BR1
eUSCI_A modulation control
eUSCI_A status
UCA1MCTLW
UCA1STAT
UCA1RXBUF
UCA1TXBUF
UCA1ABCTL
UCA1IRTCTL
UCA1IRRCTL
UCA1IE
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
UCA1IFG
UCA1IV
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Table 40. eUSCI_B0 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
UCB0CTLW0
OFFSET
eUSCI_B control word 0
eUSCI_B control word 1
eUSCI_B bit rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Ah
2Ch
2Eh
UCB0CTLW1
UCB0BR0
eUSCI_B bit rate 1
UCB0BR1
eUSCI_B status word
UCB0STATW
UCB0TBCNT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA0
UCB0I2COA1
UCB0I2COA2
UCB0I2COA3
UCB0ADDRX
UCB0ADDMASK
UCB0I2CSA
UCB0IE
eUSCI_B byte counter threshold
eUSCI_B receive buffer
eUSCI_B transmit buffer
eUSCI_B I2C own address 0
eUSCI_B I2C own address 1
eUSCI_B I2C own address 2
eUSCI_B I2C own address 3
eUSCI_B received address
eUSCI_B address mask
eUSCI I2C slave address
eUSCI interrupt enable
eUSCI interrupt flags
UCB0IFG
eUSCI interrupt vector word
UCB0IV
Table 41. ADC10_B Registers (Base Address: 0700h)
REGISTER DESCRIPTION
REGISTER
ADC10CTL0
OFFSET
ADC10_B Control register 0
00h
02h
04h
06h
08h
0Ah
12h
1Ah
1Ch
1Eh
ADC10_B Control register 1
ADC10CTL1
ADC10CTL2
ADC10LO
ADC10_B Control register 2
ADC10_B Window Comparator Low Threshold
ADC10_B Window Comparator High Threshold
ADC10_B Memory Control Register 0
ADC10_B Conversion Memory Register
ADC10_B Interrupt Enable
ADC10HI
ADC10MCTL0
ADC10MEM0
ADC10IE
ADC10_B Interrupt Flags
ADC10IGH
ADC10IV
ADC10_B Interrupt Vector Word
Table 42. Comparator_D Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
Comparator_D control register 0
REGISTER
CDCTL0
OFFSET
00h
02h
04h
06h
0Ch
0Eh
Comparator_D control register 1
Comparator_D control register 2
Comparator_D control register 3
Comparator_D interrupt register
Comparator_D interrupt vector word
CDCTL1
CDCTL2
CDCTL3
CDINT
CDIV
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(1)
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Voltage applied at VCC to VSS
–0.3 V to 4.1 V
–0.3 V to VCC + 0.3 V
±2 mA
(2)
Voltage applied to any pin (excluding VCORE)
Diode current at any device pin
(3) (4) (5)
Storage temperature range, Tstg
-55°C to 125°C
95°C
Maximum junction temperature, TJ
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
(3) Data retention on FRAM memory cannot be ensured when exceeding the specified maximum storage temperature, Tstg
.
(4) For soldering during board manufacturing, it is required to follow the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
(5) Programming of devices with user application code should only be performed after reflow or hand soldering. Factory programmed
information, such as calibration values, are designed to withstand the temperatures reached in the current JEDEC J-STD-020
specification.
Recommended Operating Conditions
MIN NOM
MAX UNIT
(1)
VCC
VSS
TA
Supply voltage during program execution and FRAM programming (AVCC = DVCC)
Supply voltage (AVSS = DVSS)
2.0
3.6
V
V
0
Operating free-air temperature
Operating junction temperature
Required capacitor at VCORE
I version
I version
-40
-40
470
85
85
°C
°C
nF
TJ
CVCORE
CVCC
CVCORE
/
Capacitor ratio of VCC to VCORE
10
0
(3)
No FRAM wait states
2 V ≤ VCC ≤ 3.6 V
,
8.0
(3)
(2)
With FRAM wait states
NACCESS = {2},
NPRECHG = {1},
2 V ≤ VCC ≤ 3.6 V
,
fSYSTEM
Processor frequency (maximum MCLK frequency)
MHz
0
24.0
(1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(3) When using manual wait state control, see the MSP430FR57xx Family User's Guide (SLAU272) for recommended settings for common
system frequencies.
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Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
(1) (2) (3)
over recommended operating free-air temperature (unless otherwise noted)
(4)
Frequency (fMCLK = fSMCLK
)
EXECUTION
MEMORY
(5)
(5)
(5)
PARAMETER
VCC
1 MHz
TYP MAX
0.27
4 MHz
TYP MAX
0.58
8 MHz
TYP MAX
1.0
16 MHz
TYP MAX
1.53
20 MHz
TYP MAX
1.9
24 MHz
TYP
UNIT
MAX
(6)
IAM, FRAM_UNI
FRAM
3 V
3 V
2.2
mA
mA
mA
FRAM
0% cache hit
ratio
(7)
IAM,0%
0.42
0.31
0.27
0.25
0.73
1.2
0.73
0.58
0.5
1.6
2.2
1.3
2.8
2.3
1.75
1.55
1.3
2.9
2.8
2.1
1.9
1.6
3.6
3.45
4.3
FRAM
50% cache hit
ratio
(7) (8)
IAM,50%
3 V
3 V
3 V
2.5
2.2
1.8
FRAM
66% cache hit
ratio
(7) (8)
IAM,66%
1.0
FRAM
75% cache hit
ratio
(7) (8)
IAM,75%
0.82
FRAM
100% cache hit
ratio
(7) (8)
IAM,100%
3 V
3 V
0.2
0.2
0.43
0.4
0.3
0.55
0.55
0.42
0.55
0.8
0.73
1.0
1.15
1.25
0.88
1.20
1.3
1.0
1.5
(8) (9)
IAM, RAM
RAM
0.35
0.75
1.45
1.45
1.75
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
(3) Characterized with program executing typical data processing.
(4) At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency,
fMCLK,eff, decreases. The effective MCLK frequency is also dependent on the cache hit ratio. SMCLK is not affected by the number of
wait states or the cache hit ratio. The following equation can be used to compute fMCLK,eff:
fMCLK,eff,MHZ= fMCLK,MHZ x 1 / [# of wait states x ((1 - cache hit ratio percent/100)) + 1]
(5) MSP430FR573x series only
(6) Program and data reside entirely in FRAM. No wait states enabled. DCORSEL = 0, DCOFSELx = 3 (fDCO = 8 MHz). MCLK = SMCLK.
(7) Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit
ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 25% ratio implies one of every
four accesses is from cache, the remaining are FRAM accesses.
For 1, 4, and 8 MHz, DCORSEL = 0, DCOFSELx = 3 (fDCO = 8 MHz). MCLK = SMCLK. No wait states enabled.
For 16 MHz, DCORSEL = 1, DCOFSELx = 0 (fDCO = 16 MHz).MCLK = SMCLK. One wait state enabled.
For 20 MHz, DCORSEL = 1, DCOFSELx = 2 (fDCO = 20 MHz).MCLK = SMCLK. Three wait states enabled.
For 24 MHz, DCORSEL = 1, DCOFSELx = 3 (fDCO = 24 MHz).MCLK = SMCLK. Three wait states enabled.
(8) See Figure 1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best
linear fit using the typical data shown in Active Mode Supply Current Into VCC Excluding External Current.
fACLK = 32786 Hz, fMCLK = fSMCLK at specified frequency. No peripherals active.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.
(9) All execution is from RAM.
For 1, 4, and 8 MHz, DCORSEL = 0, DCOFSELx = 3 (fDCO = 8 MHz). MCLK = SMCLK.
For 16 MHz, DCORSEL = 1, DCOFSELx = 0 (fDCO = 16 MHz). MCLK = SMCLK.
For 20 MHz, DCORSEL = 1, DCOFSELx = 2 (fDCO = 20 MHz). MCLK = SMCLK.
For 24 MHz, DCORSEL = 1, DCOFSELx = 3 (fDCO = 24 MHz). MCLK = SMCLK.
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Typical Active Mode Supply Current, No Wait States
2.50
2.00
1.50
1.00
0.50
0.00
IAM,0% (mA) = 0.2541 * (f, MHz) + 0.1724
IAM,50% (mA) = 0.1415 * (f, MHz) + 0.1669
IAM,66%(mA) = 0.1043 * (f, MHz) + 0.1646
IAM,75% (mA) = 0.0814 * (f, MHz) + 0.1708
IAM,RAM (mA) = 0.05 * (f, MHz) + 0.150
IAM,100% (mA) = 0.0314 * (f, MHz) + 0.1708
0
1
2
3
4
5
6
7
8
9
fMCLK = fSMCLK, MHz
Figure 1. Typical Active Mode Supply Currents, No Wait States
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1) (2)
-40°C
TYP MAX
25°C
MAX
60°C
MAX
85°C
PARAMETER
VCC
UNIT
TYP
TYP
TYP
MAX
2 V,
3 V
(3) (4)
(5) (4)
(6) (4)
(7) (8)
ILPM0,1MHz
Low-power mode 0
Low-power mode 0
Low-power mode 0
Low-power mode 2
166
175
190
225
µA
2 V,
3 V
170
274
56
177
285
61
244
195
315
75
225
340
110
48
360
455
µA
µA
µA
µA
µA
µA
µA
µA
LPM0,8MHz
2 V,
3 V
340
80
LPM0,24MHz
2 V,
3 V
ILPM2
210
150
150
150
5.0
Low-power mode 3, crystal
2 V,
3 V
ILPM3,XT1LF
ILPM3,VLO
ILPM4
3.4
3.3
2.9
1.3
0.3
6.4
6.3
5.9
1.5
0.32
15
18
(9) (8)
mode
Low-power mode 3,
2 V,
3 V
15
18
48
(10) (8)
VLO mode
2 V,
3 V
(11) (8)
Low-power mode 4
15
18
48
2 V,
3 V
(12)
ILPM3.5
Low-power mode 3.5
2.2
0.66
1.9
0.38
2.8
0.57
2 V,
3 V
(13)
ILPM4.5
Low-power mode 4.5
2.55
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = 1 MHz. DCORSEL = 0,
DCOFSELx = 3 (fDCO = 8 MHz)
(4) Current for brownout, high-side supervisor (SVSH) and low-side supervisor (SVSL) included.
(5) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = 8 MHz. DCORSEL = 0,
DCOFSELx = 3 (fDCO = 8 MHz)
(6) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = 24 MHz. DCORSEL = 1,
DCOFSELx = 3 (fDCO = 24 MHz)
(7) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCORSEL = 0,
DCOFSELx = 3, DCO bias generator enabled.
(8) Current for brownout, high-side supervisor (SVSH) included. Low-side supervisor disabled (SVSL).
(9) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
(10) Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
(11) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
(12) Internal regulator disabled. No data retention. RTC active.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM3.5), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
(13) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
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Schmitt-Trigger Inputs – General Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2 V
3 V
2 V
3 V
2 V
3 V
MIN
0.80
1.50
0.45
0.75
0.25
0.30
TYP
MAX UNIT
1.40
V
VIT+
VIT–
Vhys
Positive-going input threshold voltage
2.10
1.10
V
Negative-going input threshold voltage
1.65
0.8
V
Input voltage hysteresis (VIT+ – VIT–
)
1.0
For pullup: VIN = VSS
For pulldown: VIN = VCC
RPull
CI
Pullup or pulldown resistor
Input capacitance
20
35
5
50
kΩ
VIN = VSS or VCC
pF
(1)
Inputs – Ports P1 and P2
(P1.0 to P1.7, P2.0 to P2.7)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
(2)
t(int)
External interrupt timing
External trigger pulse duration to set interrupt flag
2 V, 3 V
20
ns
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int)
.
Leakage Current – General Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1) (2)
VCC
MIN
MAX UNIT
50 nA
Ilkg(Px.x)
High-impedance leakage current
2 V, 3 V
-50
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
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Outputs – General Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
VCC – 0.25
VCC – 0.60
VCC – 0.25
VCC – 0.60
MAX UNIT
(1)
I(OHmax) = –1 mA
VCC
2 V
(2)
(1)
(2)
I(OHmax) = –3 mA
I(OHmax) = –2 mA
I(OHmax) = –6 mA
VCC
VOH
High-level output voltage
V
VCC
3 V
2 V
3 V
VCC
(1)
I(OLmax) = 1 mA
I(OLmax) = 3 mA
I(OLmax) = 2 mA
I(OLmax) = 6 mA
VSS VSS + 0.25
(2)
VSS VSS + 0.60
VSS VSS + 0.25
VSS VSS + 0.60
VOL
Low-level output voltage
V
(1)
(2)
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
Output Frequency – General Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2 V
3 V
2 V
3 V
MIN
MAX UNIT
16
Port output frequency
(with load)
(1) (2)
fPx.y
Px.y
MHz
24
16
ACLK, SMCLK, or MCLK at configured output port,
fPort_CLK
Clock output frequency
MHz
24
(2)
CL = 20 pF, no DC loading
(1) A resistive divider with 2 × 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
CL = 20 pF is connected from the output to VSS
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
.
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Typical Characteristics – Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
16
14
12
10
8
VCC = 2.0 V
TA = -40 °C
Px.y
TA = 25 °C
TA = 85 °C
6
4
2
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
VOL Low-Level Output Voltage - V
Figure 2.
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
35
30
25
20
15
10
5
VCC = 3.0 V
Px.y
TA = -40 °C
TA = 25 °C
TA = 85 °C
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
VOL Low-Level Output Voltage - V
Figure 3.
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Typical Characteristics – Outputs (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
VCC = 2.0 V
Px.y
-2
-4
-6
-8
-10
TA = 85 °C
-12
TA = 25 °C
-14
TA = -40 °C
-16
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
VOH High-Level Output Voltage - V
Figure 4.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
-5
VCC = 3.0 V
Px.y
-10
-15
-20
-25
-30
-35
-40
TA = 85 °C
TA = 25 °C
TA = -40 °C
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
VOH High-Level Output Voltage - V
Figure 5.
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(1)
Crystal Oscillator, XT1, Low-Frequency (LF) Mode
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {1},
CL,eff = 9 pF, TA = 25°C,
3 V
60
Additional current consumption
XT1 LF mode from lowest drive
setting
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {2},
TA = 25°C, CL,eff = 9 pF
ΔIVCC.LF
3 V
3 V
90
nA
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {3},
TA = 25°C, CL,eff = 12 pF
140
XT1 oscillator crystal frequency,
LF mode
fXT1,LF0
XTS = 0, XT1BYPASS = 0
32768
Hz
XT1 oscillator logic-level square-
wave input frequency, LF mode
(2) (3)
fXT1,LF,SW
XTS = 0, XT1BYPASS = 1
10 32.768
210
50 kHz
XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {0},
fXT1,LF = 32768 Hz, CL,eff = 6 pF
Oscillation allowance for
OALF
kΩ
(4)
LF crystals
XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {3},
fXT1,LF = 32768 Hz, CL,eff = 12 pF
300
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
Duty cycle, LF mode
30
10
70
%
Oscillator fault frequency, LF mode
(6)
fFault,LF
tSTART,LF
CL,eff
XTS = 0
10000
Hz
(5)
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {0},
TA = 25°C, CL,eff = 6 pF
1000
(7)
Startup time, LF mode
3 V
ms
pF
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {3},
TA = 25°C, CL,eff = 12 pF
1000
1
Integrated effective load
XTS = 0
(8) (9)
capacitance, LF mode
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(2) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this data sheet.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the XT1DRIVE
settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following guidelines, but
should be evaluated based on the actual crystal selected for the application:
(a) For XT1DRIVE = {0}, CL,eff ≤ 6 pF.
(b) For XT1DRIVE = {1}, 6 pF ≤ CL,eff ≤ 9 pF.
(c) For XT1DRIVE = {2}, 6 pF ≤ CL,eff ≤ 10 pF.
(d) For XT1DRIVE = {3}, 6 pF ≤ CL,eff ≤ 12 pF.
(5) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(6) Measured with logic-level input frequency but also applies to operation with crystals.
(7) Includes startup counter of 4096 clock cycles.
(8) Requires external capacitors at both terminals.
(9) Values are specified by crystal manufacturers. Include parasitic bond and package capacitance (approximately 2 pF per pin).
Recommended values supported are 6 pF, 9 pF, and 12 pF. Maximum shunt capacitance of 1.6 pF.
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(1)
Crystal Oscillator, XT1, High-Frequency (HF) Mode
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 4 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {0},
TA = 25°C, CL,eff = 16 pF
175
fOSC = 8 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {1},
TA = 25°C, CL,eff = 16 pF
300
350
550
XT1 oscillator crystal current HF
mode
IVCC,HF
3 V
µA
fOSC = 16 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {2},
TA = 25°C, CL,eff = 16 pF
fOSC = 24 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {3},
TA = 25°C, CL,eff = 16 pF
XT1 oscillator crystal frequency,
HF mode 0
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {0}
fXT1,HF0
fXT1,HF1
fXT1,HF2
fXT1,HF3
fXT1,HF,SW
4
6
6
MHz
(2)
(3)
(3)
(3)
XT1 oscillator crystal frequency,
HF mode 1
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {1}
10 MHz
16 MHz
24 MHz
24 MHz
XT1 oscillator crystal frequency,
HF mode 2
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {2}
10
16
1
XT1 oscillator crystal frequency,
HF mode 3
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {3}
XT1 oscillator logic-level square-
wave input frequency, HF mode
XTS = 1,
XT1BYPASS = 1
(4) (3)
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {0},
fXT1,HF = 4 MHz, CL,eff = 16 pF
450
320
200
200
8
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {1},
fXT1,HF = 8 MHz, CL,eff = 16 pF
Oscillation allowance for
HF crystals
OAHF
Ω
(5)
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {2},
fXT1,HF = 16 MHz, CL,eff = 16 pF
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {3},
fXT1,HF = 24 MHz, CL,eff = 16 pF
fOSC = 4 MHz, XTS = 1,
XT2BYPASS = 0, XT2DRIVE = {0},
TA = 25°C, CL,eff = 16 pF
(6)
tSTART,HF
Startup time, HF mode
3 V
ms
fOSC = 24 MHz, XTS = 1,
XT2BYPASS = 0, XT2DRIVE = {3},
TA = 25°C, CL,eff = 16 pF
2
(1) To improve EMI on the XT1 oscillator the following guidelines should be observed.
(a) Keep the traces between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(2) Maximum frequency of operation of the entire device cannot be exceeded.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this data sheet.
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(6) Includes startup counter of 4096 clock cycles.
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Crystal Oscillator, XT1, High-Frequency (HF) Mode (1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Integrated effective load
capacitance
CL,eff
XTS = 1
1
pF
(7) (8)
XTS = 1, Measured at ACLK,
fXT1,HF2 = 24 MHz
Duty cycle, HF mode
40
50
60
%
Oscillator fault frequency, HF mode
(10)
fFault,HF
XTS = 1
145
900 kHz
(9)
(7) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should
always match the specification of the used crystal.
(8) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Recommended values supported are 14
pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF.
(9) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(10) Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLO frequency
VLO frequency temperature drift
TEST CONDITIONS
VCC
MIN
TYP
8.3
0.5
4
MAX UNIT
13 kHz
%/°C
fVLO
Measured at ACLK
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
5
(1)
(2)
dfVLO/dT
Measured at ACLK
Measured at ACLK
Measured at ACLK
dfVLO/dVCC VLO frequency supply voltage drift
fVLO,DC Duty cycle
%/V
40
50
60
%
(1) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(2.0 to 3.6 V) – MIN(2.0 to 3.6 V)) / MIN(2.0 to 3.6 V) / (3.6 V – 2 V)
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MAX UNIT
DCO Frequencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC
TA
PARAMETER
TEST CONDITIONS
MIN
TYP
2 V to 3.6 V
-40°C to 85°C
5.37 ±3.5%
5.37 ±2.0%
16.2 ±3.5%
16.2 ±2.0%
6.67 ±3.5%
6.67 ±2.0%
20 ±3.5%
Measured at ACLK,
DCORSEL = 0
MHz
MHz
MHz
MHz
MHz
2 V to 3.6 V
0°C to 50°C
fDCO,LO
DCO frequency low, trimmed
2 V to 3.6 V
-40°C to 85°C
Measured at ACLK,
(1)
DCORSEL = 1
2 V to 3.6 V
0°C to 50°C
2 V to 3.6 V
-40°C to 85°C
Measured at ACLK,
DCORSEL = 0
2 V to 3.6 V
0°C to 50°C
fDCO,MID
DCO frequency mid, trimmed
2 V to 3.6 V
-40°C to 85°C
Measured at ACLK,
(1)
DCORSEL = 1
2 V to 3.6 V
0°C to 50°C
20 ±2.0%
2 V to 3.6 V
-40°C to 85°C
8
8
±3.5%
±2.0%
Measured at ACLK,
DCORSEL = 0
2 V to 3.6 V
0°C to 50°C
fDCO,HI
DCO frequency high, trimmed
2 V to 3.6 V
23.8 ±3.5%
23.8 ±2.0%
-40°C to 85°C
Measured at ACLK,
DCORSEL = 1
MHz
%
(1)
2 V to 3.6 V
0°C to 50°C
Measured at ACLK, divide by 1,
No external divide, all DCO
settings
2 V to 3.6 V
-40°C to 85°C
fDCO,DC
Duty cycle
40
50
60
(1) MSP40FR573x devices only
MODOSC
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Current consumption
MODOSC frequency
Duty cycle
TEST CONDITIONS
VCC
MIN
TYP
44
MAX UNIT
80 µA
5.5 MHz
60
IMODOSC
Enabled
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
fMODOSC
4.5
40
5.0
50
fMODOSC,DC
Measured at ACLK, divide by 1
%
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PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
2 V ≤ DVCC ≤ 3.6 V
2 V ≤ DVCC ≤ 3.6 V
MIN
TYP
1.5
MAX UNIT
VCORE(AM)
Core voltage, active mode
Core voltage, low-current mode
V
V
VCORE(LPM)
1.5
PMM, SVS, BOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC = 3.6 V
MIN
TYP
MAX UNIT
ISVSH,AM
ISVSH,LPM
VSVSH-
SVSH current consumption, active mode
SVSH current consumption, low power modes
SVSH on voltage level, falling supply voltage
SVSH off voltage level, rising supply voltage
SVSH propagation delay, active mode
SVSH propagation delay, low power modes
SVSL current consumption
5
0.8
µA
VCC = 3.6 V
1.5
1.93
1.98
µA
V
1.83
1.88
1.88
1.93
10
VSVSH+
V
tPD,SVSH, AM
tPD,SVSH, LPM
ISVSL
dVCC/dt = 10 mV/µs
dVCC/dt = 1 mV/µs
µs
µs
µA
30
0.3
0.5
Wake-Up from Low Power Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC
TA
PARAMETER
TEST CONDITIONS
MIN
TYP
0.58
12
MAX UNIT
Wake-up time from LPM0 to active
2 V, 3 V
-40°C to 85°C
tWAKE-UP LPM0
tWAKE-UP LPM12
tWAKE-UP LPM34
1
25
µs
µs
µs
µs
µs
µs
ms
(1)
mode
Wake-up time from LPM1, LPM2 to
2 V, 3 V
-40°C to 85°C
(1)
active mode
Wake-up time from LPM3 or LPM4 to
2 V, 3 V
-40°C to 85°C
78
120
575
1100
210
(1)
active mode
2 V, 3 V
0°C to 85°C
310
310
170
1.6
Wake-up time from LPM3.5 or
LPM4.5 to active mode
tWAKE-UP LPMx.5
(1)
2 V, 3 V
-40°C to 85°C
Wake-up time from RST to active
2 V, 3 V
-40°C to 85°C
tWAKE-UP RESET
tWAKE-UP BOR
VCC stable
(2)
mode
Wake-up time from BOR or power-up
to active mode
2 V, 3 V
-40°C to 85°C
dVCC/dt = 2400 V/s
(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
(2) The wake-up time is measured from the rising edge of the RST signal until the first instruction of the user program is executed.
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Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
8
fTA
Timer_A input clock frequency
External: TACLK
Duty cycle = 50% ± 10%
2 V, 3 V
MHz
(1)
24
All capture inputs, Minimum pulse
duration required for capture
tTA,cap
Timer_A capture timing
2 V, 3 V
20
ns
(1) MSP430FR573x devices only
Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
8
fTB
Timer_B input clock frequency
External: TBCLK
Duty cycle = 50% ± 10%
2 V, 3 V
MHz
(1)
24
All capture inputs, Minimum pulse
duration required for capture
tTB,cap
Timer_B capture timing
2 V, 3 V
20
ns
(1) MSP430FR573x devices only
eUSCI (UART Mode) Recommended Operating Conditions
PARAMETER
CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
External: UCLK
feUSCI
eUSCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ± 10%
BITCLK clock frequency
(equals baud rate in MBaud)
fBITCLK
5
MHz
eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UCGLITx = 0
VCC
MIN
5
TYP
15
MAX UNIT
20
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
20
35
50
45
60
ns
(1)
tt
UART receive deglitch time
2 V, 3 V
80
120
110
180
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
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eUSCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER
CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%
feUSCI
eUSCI input clock frequency
fSYSTEM MHz
eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
UCSTEM = 0,
UCMODEx = 01 or 10
2 V, 3 V
1
UCxCLK
cycles
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
STE lead time, STE active to clock
UCSTEM = 1,
UCMODEx = 01 or 10
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
1
1
1
UCSTEM = 0,
UCMODEx = 01 or 10
STE lag time, Last clock to STE
inactive
UCxCLK
cycles
UCSTEM = 1,
UCMODEx = 01 or 10
UCSTEM = 0,
UCMODEx = 01 or 10
55
35
40
30
STE access time, STE active to SIMO
data out
ns
ns
UCSTEM = 1,
UCMODEx = 01 or 10
UCSTEM = 0,
UCMODEx = 01 or 10
STE disable time, STE inactive to
SIMO high impedance
UCSTEM = 1,
UCMODEx = 01 or 10
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
35
35
0
tSU,MI
SOMI input data setup time
SOMI input data hold time
ns
ns
ns
ns
tHD,MI
0
30
30
UCLK edge to SIMO valid,
CL = 20 pF
(2)
tVALID,MO
SIMO output data valid time
0
0
(3)
tHD,MO
SIMO output data hold time
CL = 20 pF
(1) fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 6 and Figure 7.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 6
and Figure 7.
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UCMODEx = 01
STE
tSTE,LEAD
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
SIMO
tSTE,ACC
tVALID,MO
tSTE,DIS
Figure 6. SPI Master Mode, CKPH = 0
UCMODEx = 01
STE
tSTE,LEAD
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
SIMO
tSTE,ACC
tVALID,MO
tSTE,DIS
Figure 7. SPI Master Mode, CKPH = 1
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eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
VCC
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
MIN
7
TYP
MAX UNIT
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
tSU,SI
STE lead time, STE active to clock
ns
7
0
STE lag time, Last clock to STE inactive
ns
0
65
ns
40
STE access time, STE active to SOMI data out
40
ns
35
STE disable time, STE inactive to SOMI high
impedance
2
2
5
5
SIMO input data setup time
SIMO input data hold time
ns
ns
tHD,SI
30
ns
30
UCLK edge to SOMI valid,
CL = 20 pF
(2)
tVALID,SO
SOMI output data valid time
4
4
(3)
tHD,SO
SOMI output data hold time
CL = 20 pF
ns
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 8 and Figure 9.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 8
and Figure 9.
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UCMODEx = 01
STE
tSTE,LEAD
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tSU,SIMO
tHD,SIMO
tLOW/HIGH
tLOW/HIGH
SIMO
SOMI
tACC
tVALID,SOMI
tDIS
Figure 8. SPI Slave Mode, CKPH = 0
UCMODEx = 01
STE
tSTE,LEAD
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
SOMI
tACC
tDIS
tVALID,SO
Figure 9. SPI Slave Mode, CKPH = 1
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SLAS639D –JULY 2011–REVISED AUGUST 2012
eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 10)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
External: UCLK
feUSCI
eUSCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ± 10%
fSCL
SCL clock frequency
2 V, 3 V
2 V, 3 V
0
4.0
0.6
4.7
0.6
0
400 kHz
µs
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
2 V, 3 V
µs
tHD,DAT
tSU,DAT
Data hold time
Data setup time
2 V, 3 V
2 V, 3 V
ns
ns
250
4.0
0.6
50
fSCL = 100 kHz
fSCL > 100 kHz
UCGLITx = 0
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
UCCLTOx = 1
UCCLTOx = 2
UCCLTOx = 3
tSU,STO
Setup time for STOP
2 V, 3 V
µs
600
300
150
75
ns
ns
25
Pulse duration of spikes suppressed by
input filter
tSP
2 V, 3 V
12.5
6.25
ns
ns
27
30
33
ms
ms
ms
tTIMEOUT
Clock low timeout
2 V, 3 V
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 10. I2C Mode Timing
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MAX UNIT
10-Bit ADC, Power Supply and Input Range Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.0
0
TYP
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
AVCC
Analog supply voltage
Analog input voltage range
3.6
V
V
V(Ax)
All ADC10 pins
AVCC
140
Operating supply current into fADC10CLK = 5 MHz, ADC10ON = 1,
2 V
3 V
90
IADC10_A
AVCC terminal, reference
current not included
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC10DIV = 0
µA
100
160
Only one terminal Ax can be selected at one
time from the pad to the ADC10_A capacitor
array including wiring and pad
CI
RI
Input capacitance
2.2 V
6
8
pF
Input MUX ON resistance
AVCC ≥ 2 V, 0 V ≤ VAx ≤ AVCC
36
kΩ
10-Bit ADC, Timing Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
For specified performance of ADC10 linearity
parameters
2 V to
3.6 V
fADC10CLK
fADC10OSC
0.45
5
5.5 MHz
Internal ADC10 oscillator
(MODOSC)
2 V to
3.6 V
ADC10DIV = 0, fADC10CLK = fADC10OSC
4.5
4.5
5.5 MHz
REFON = 0, Internal oscillator,
12 ADC10CLK cycles, 10-bit mode,
fADC10OSC = 4.5 MHz to 5.5 MHz
2 V to
3.6 V
2.18
2.67
µs
tCONVERT
Conversion time
External fADC10CLK from ACLK, MCLK, or SMCLK,
ADC10SSEL ≠ 0
2 V to
3.6 V
(1)
The error in a conversion started after tADC10ON is
less than ±0.5 LSB,
Reference and input signal already settled
Turn on settling time of
the ADC
tADC10ON
100
ns
µs
RS = 1000 Ω, RI = 36000 Ω, CI = 3.5 pF,
Approximately eight Tau (τ) are required to get an
error of less than ±0.5 LSB
2 V
3 V
1.5
2.0
tSample
Sampling time
(1) 12 × ADC10DIV × 1/fADC10CLK
10-Bit ADC, Linearity Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
1.4 V ≤ (VeREF+ – VREF–/VeREF–)min ≤ 1.6 V
1.6 V < (VeREF+ – VREF–/VeREF–)min ≤ VAVCC
VCC
MIN
-1.4
-1.1
TYP
MAX UNIT
1.4
Integral
linearity error
2 V to
3.6 V
EI
LSB
1.1
Differential
linearity error
2 V to
3.6 V
ED
EO
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–
)
)
)
-1
-6.5
-1.2
-4
1
LSB
mV
2 V to
3.6 V
Offset error
6.5
Gain error, external
reference
2 V to
3.6 V
1.2 LSB
EG
Gain error, internal
4
2
%
(1)
reference
Total unadjusted
error, external
reference
2 V to
3.6 V
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–
)
-2
-4
LSB
ET
Total unadjusted
error, internal
4
%
(1)
reference
(1) Error is dominated by the internal reference.
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REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
1.4
0
TYP
MAX UNIT
(2)
VeREF+
VeREF–
(VeREF+
Positive external reference voltage input
VeREF+ > VeREF–
AVCC
1.2
V
V
(3)
(4)
Negative external reference voltage input VeREF+ > VeREF–
–
Differential external reference voltage
VeREF+ > VeREF–
1.4
AVCC
V
VREF–/VeREF–
)
input
1.4 V ≤ VeREF+ ≤ VAVCC
VeREF– = 0 V,
,
fADC10CLK = 5 MHz,
ADC10SHTx = 1h,
Conversion rate 200 ksps
2.2 V, 3 V
2.2 V, 3 V
-6
6
µA
IVeREF+
IVeREF–
,
Static input current
1.4 V ≤ VeREF+ ≤ VAVCC
VeREF– = 0 V,
fADC10CLK = 5 MHz,
ADC10SHTx = 8h,
,
-1
1
µA
µF
Conversion rate 20 ksps
Capacitance at VREF+ or VREF- terminal
CVREF+, CVREF-
10
(5)
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC10_B. Also see the MSP430FR57xx Family User's Guide (SLAU272).
REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
REFVSEL = {2} for 2.5 V, REFON = 1
REFVSEL = {1} for 2 V, REFON = 1
REFVSEL = {0} for 1.5 V, REFON = 1
REFVSEL = {0} for 1.5 V
VCC
3 V
3 V
3 V
MIN
2.4
TYP
2.5
2.0
1.5
MAX UNIT
2.6
Positive built-in reference
voltage output
VREF+
1.92
1.44
2.0
2.08
1.56
V
AVCC minimum voltage,
Positive built-in reference
active
AVCC(min)
REFVSEL = {1} for 2 V
2.2
V
REFVSEL = {2} for 2.5 V
2.7
Operating supply current into fADC10CLK = 5 MHz,
IREF+
3 V
33
45
µA
(1)
AVCC terminal
REFON = 1, REFBURST = 0
Temperature coefficient of
built-in reference
ppm/
°C
TREF+
REFVSEL = (0, 1, 2}, REFON = 1
±35
AVCC = AVCC (min) - AVCC(max)
TA = 25°C, REFON = 1,
REFVSEL = (0} for 1.5 V
,
,
,
,
1600
1900
AVCC = AVCC (min) - AVCC(max)
TA = 25°C, REFON = 1,
REFVSEL = (1} for 2 V
Power supply rejection ratio
(DC)
PSRR_DC
µV/V
AVCC = AVCC (min) - AVCC(max)
TA = 25°C, REFON = 1,
REFVSEL = (2} for 2.5 V
3600
30
Settling time of reference
voltage
AVCC = AVCC (min) - AVCC(max)
REFVSEL = (0, 1, 2}, REFON = 0 → 1
tSETTLE
µs
(2)
(1) The internal reference current is supplied by terminal AVCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
(2) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
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REF, Temperature Sensor and Built-In VMID
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
790
MAX UNIT
mV
ADC10ON = 1, INCH = 0Ah,
TA = 0°C
(1)
VSENSOR
See
2 V, 3 V
TCSENSOR
ADC10ON = 1, INCH = 0Ah
2 V, 3 V
2 V
2.55
mV/°C
30
30
Sample time required if
channel 10 is selected
ADC10ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
tSENSOR(sample)
µs
(2)
3 V
2 V
0.97
1.46
1.0
1.5
1.03
V
ADC10ON = 1, INCH = 0Bh,
VMID is ~0.5 × VAVCC
VMID
AVCC divider at channel 11
Sample time required if
3 V
1.54
ADC10ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
tVMID(sample)
2 V, 3 V
1000
ns
(3)
channel 11 is selected
(1) The temperature sensor offset can vary significantly. A single-point calibration is recommended to minimize the offset error of the built-in
temperature sensor.
(2) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
.
(3) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
1050
1000
950
900
850
800
750
700
650
600
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Ambient Temperature - Degrees Celsius
Figure 11. Typical Temperature Sensor Voltage
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Comparator_D
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Overdrive = 10 mV,
VIN- = (VIN+ – 400 mV) to (VIN+ + 10 mV)
50
100
200
ns
ns
ns
Propagation delay,
AVCC = 2 V to 3.6 V
Overdrive = 100 mV,
VIN- = (VIN+ – 400 mV) to (VIN+ + 100 mV)
tpd
80
50
Overdrive = 250 mV,
(VIN+ – 400 mV) to (VIN+ + 250 mV)
CDF = 1, CDFDLY = 00
CDF = 1, CDFDLY = 01
CDF = 1, CDFDLY = 10
CDF = 1, CDFDLY = 11
AVCC = 2 V to 3.6 V
0.3
0.5
0.9
1.6
-20
0.5
0.9
1.6
3.0
0.9
1.5
2.8
5.5
20
µs
µs
Filter timer added to the
propagation delay of the
comparator
tfilter
µs
µs
Voffset
Input offset
mV
Common mode input
range
Vic
AVCC = 2 V to 3.6 V
0
AVCC - 1
V
Icomp(AVCC)
Iref(AVCC)
Comparator only
CDON = 1, AVCC = 2 V to 3.6 V
CDREFLx = 01, AVCC = 2 V to 3.6 V
29
20
34
24
µA
µA
Reference buffer and R-
ladder
CDON = 0 to CDON = 1,
AVCC = 2 V to 3.6 V
tenable,comp
Comparator enable time
1.1
1.1
2.0
2.0
µs
µs
Resistor ladder enable
time
CDON = 0 to CDON = 1,
AVCC = 2 V to 3.6 V
tenable,rladder
VIN ×
(n + 0.5)
/ 32
VIN ×
(n + 1)
/ 32
VIN ×
(n + 1.5)
/ 32
Reference voltage for a
tap
VIN = voltage input to the R-ladder,
n = 0 to 31
VCB_REF
V
FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Write supply voltage
TEST CONDITIONS
MIN
TYP
MAX UNIT
DVCC(WRITE)
tWRITE
2.0
3.6
120
60
V
ns
Word or byte write time
(1)
tACCESS
Read access time
ns
(1)
tPRECHARGE
tCYCLE
Precharge time
60
ns
(1)
Cycle time, read or write operation
Read and write endurance
120
1015
100
40
ns
cycles
TJ = 25°C
TJ = 70°C
TJ = 85°C
tRetention
Data retention duration
years
10
(1) When using manual wait state control, see the MSP430FR57xx Family User's Guide (SLAU272) for recommended settings for common
system frequencies.
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JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Spy-Bi-Wire input frequency
VCC
MIN
0
TYP
MAX UNIT
fSBW
2 V, 3 V
2 V, 3 V
2 V, 3 V
20 MHz
tSBW,Low
tSBW, En
tSBW,Rst
Spy-Bi-Wire low clock pulse duration
0.025
15
1
µs
µs
(1)
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)
Spy-Bi-Wire return to normal operation time
19
0
35
5
µs
2 V
3 V
MHz
(2)
fTCK
TCK input frequency, 4-wire JTAG
0
10 MHz
50 kΩ
Rinternal
Internal pulldown resistance on TEST
2 V, 3 V
20
35
(1) Tools accessing the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
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SLAS639D –JULY 2011–REVISED AUGUST 2012
INPUT/OUTPUT SCHEMATICS
Port P1, P1.0 to P1.2, Input/Output With Schmitt Trigger
Pad Logic
External ADC reference
(P1.0, P1.1)
To ADC
From ADC
To Comparator
From Comparator
CDPD.x
P1REN.x
P1DIR.x
0 0
0 1
1 0
1 1
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P1OUT.x
From module 1
From module 2
DVSS
P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREF-
P1.1/TA0.2/TA1CLK/CDOUT/A1/CD1/VeREF+
P1.2/TA1.1/TA0CLK/CDOUT/A2/CD2
P1SEL0.x
P1SEL1.x
P1IN.x
Bus
Keeper
EN
D
To modules
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Table 43. Port P1 (P1.0 to P1.2) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
(1)
P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREF-
0
P1.0 (I/O)
TA0.CCI1A
TA0.1
I: 0; O: 1
0
0
0
1
0
1
0
1
1
0
DMAE0
RTCCLK
(2) (3)
A0
(2) (4)
CD0
X
1
1
(2) (3)
VeREF-
P1.1 (I/O)
TA0.CCI2A
TA0.2
P1.1/TA0.2/TA1CLK/CDOUT/A1/CD1/VeREF+
1
I: 0; O: 1
0
0
0
1
0
1
0
1
TA1CLK
CDOUT
1
1
0
1
(2) (3)
A1
(2) (4)
CD1
X
(2) (3)
VeREF+
P1.2 (I/O)
TA1.CCI1A
TA1.1
P1.2/TA1.1/TA0CLK/CDOUT/A2/CD2
2
I: 0; O: 1
0
0
0
1
0
1
0
1
TA0CLK
CDOUT
1
1
0
1
(2) (3)
A2
X
(2) (4)
CD2
(1) This pin is tied to AVSS for YFF package types. All functions are therefore tied to ground at the pin.
(2) Setting P1SEL1.x and P1SEL0.x disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(3) Not available on all devices and package types.
(4) Setting the CDPD.x bit of the comparator disables the output driver as well as the input Schmitt trigger to prevent parasitic cross
currents when applying analog signals. Selecting the CDx input pin to the comparator multiplexer with the CDx bits automatically
disables output driver and input buffer for that pin, regardless of the state of the associated CDPD.x bit.
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Port P1, P1.3 to P1.5, Input/Output With Schmitt Trigger
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CDPD.x
P1REN.x
0 0
0 1
1 0
1 1
P1DIR.x
DVSS
DVCC
0
1
From module 2
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P1OUT.x
From module 1
From module 2
DVSS
P1.3/TA1.2/UCB0STE/A3/CD3
P1.4/TB0.1/UCA0STE/A4/CD4
P1.5/TB0.2/UCA0CLK/A5/CD5
P1SEL0.x
P1SEL1.x
P1IN.x
Bus
Keeper
EN
D
To modules
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Table 44. Port P1 (P1.3 to P1.5) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.3/TA1.2/UCB0STE/A3/CD3
3
P1.3 (I/O)
TA1.CCI2A
TA1.2
I: 0; O: 1
0
0
0
1
0
1
(1)
UCB0STE
X
1
1
0
0
1
0
(2) (3)
A3
X
(2) (4)
CD3
P1.4/TB0.1/UCA0STE/A4/CD4
P1.5/TB0.2/UCA0CLK/A5/CD5
4
5
P1.4 (I/O)
TB0.CCI1A
TB0.1
I: 0; O: 1
0
1
0
1
(5)
UCA0STE
X
1
1
0
0
1
0
(2) (3)
A4
X
(2) (4)
CD4
P1.5(I/O)
TB0.CCI2A
TB0.2
I: 0; O: 1
0
1
0
1
(5)
UCA0CLK
X
1
1
0
1
(2) (3)
A5
X
(2) (4)
CD5
(1) Direction controlled by eUSCI_B0 module.
(2) Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(3) Not available on all devices and package types.
(4) Setting the CDPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the CDx input pin to the comparator multiplexer with the CDx bits automatically disables output
driver and input buffer for that pin, regardless of the state of the associated CDPD.x bit
(5) Direction controlled by eUSCI_A0 module.
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Port P1, P1.6 to P1.7, Input/Output With Schmitt Trigger
Pad Logic
DVSS
P1REN.x
P1DIR.x
0 0
0 1
1 0
1 1
DVSS
DVCC
0
1
From module 2
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P1OUT.x
From module 1
From module 2
From module 3
P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0
P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0
P1SEL0.x
P1SEL1.x
P1IN.x
Bus
Keeper
EN
D
To modules
Table 45. Port P1 (P1.6 to P1.7) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0
6
P1.6 (I/O)
I: 0; O: 1
0
0
(1)
TB1.CCI1A
0
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
(1)
TB1.1
(2)
UCB0SIMO/UCB0SDA
TA0.CCI0A
X
0
TA0.0
1
P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0
7
P1.7 (I/O)
I: 0; O: 1
(1)
TB1.CCI2A
0
1
(1)
TB1.2
(3)
UCB0SOMI/UCB0SCL
TA1.CCI0A
X
0
1
TA1.0
(1) Not available on all devices and package types.
(2) Direction controlled by eUSCI_B0 module.
(3) Direction controlled by eUSCI_A0 module.
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Port P2, P2.0 to P2.2, Input/Output With Schmitt Trigger
Pad Logic
DVSS
P2REN.x
P2DIR.x
0 0
0 1
1 0
1 1
DVSS
DVCC
0
1
From module 2
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P2OUT.x
From module 1
From module 2
From module 3
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.2/TB2.2/UCB0CLK/TB1.0
P2SEL0.x
P2SEL1.x
P2IN.x
Bus
Keeper
EN
D
To modules
Table 46. Port P2 (P2.0 to P2.2) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL1.x
P2SEL0.x
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.2/TB2.2/UCB0CLK/TB1.0
0
P2.0 (I/O)
I: 0; O: 1
0
0
1
0
1
0
1
0
1
0
1
0
1
(1)
TB2.CCI0A
0
1
0
1
1
0
0
1
1
0
0
1
1
(1)
TB2.0
(2)
UCA0TXD/UCA0SIMO
TB0CLK
X
0
ACLK
1
1
2
P2.1 (I/O)
I: 0; O: 1
(1)
TB2.CCI1A
0
1
(1)
TB2.1
(2)
UCA0RXD/UCA0SOMI
TB0.CCI0A
X
0
TB0.0
1
P2.2 (I/O)
I: 0; O: 1
(1)
TB2.CCI2A
0
(1)
TB2.2
1
(3)
UCB0CLK
X
(1)
TB1.CCI0A
0
1
(1)
TB1.0
(1) Not available on all devices and package types.
(2) Direction controlled by eUSCI_A0 module.
(3) Direction controlled by eUSCI_B0 module.
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SLAS639D –JULY 2011–REVISED AUGUST 2012
Port P2, P2.3 to P2.4, Input/Output With Schmitt Trigger
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CDPD.x
P2REN.x
0 0
0 1
1 0
1 1
P2DIR.x
DVSS
DVCC
0
1
From module 2
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P2OUT.x
From module 1
From module 2
DVSS
P2.3/TA0.0/UCA1STE/A6/CD10
P2.4/TA1.0/UCA1CLK/A7/CD11
P2SEL0.x
P2SEL1.x
P2IN.x
Bus
Keeper
EN
D
To modules
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Table 47. Port P2 (P2.3 to P2.4) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL1.x
P2SEL0.x
P2.3/TA0.0/UCA1STE/A6/CD10
3
P2.3 (I/O)
TA0.CCI0B
TA0.0
I: 0; O: 1
0
0
0
1
0
1
(1)
UCA1STE
X
1
1
0
0
1
0
(2) (3)
A6
X
(2) (4)
CD10
P2.4/TA1.0/UCA1CLK/A7/CD11
4
P2.4 (I/O)
TA1.CCI0B
TA1.0
I: 0; O: 1
0
1
0
1
(1)
UCA1CLK
X
1
1
0
1
(2) (3)
A7
X
(2) (4)
CD11
(1) Direction controlled by eUSCI_A1 module.
(2) Setting P2SEL1.x and P2SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(3) Not available on all devices and package types.
(4) Setting the CDPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the CDx input pin to the comparator multiplexer with the CDx bits automatically disables output
driver and input buffer for that pin, regardless of the state of the associated CDPD.x bit.
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SLAS639D –JULY 2011–REVISED AUGUST 2012
Port P2, P2.5 to P2.6, Input/Output With Schmitt Trigger
Pad Logic
P2REN.x
0 0
0 1
1 0
1 1
P2DIR.x
DVSS
DVCC
0
1
From module 2
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P2OUT.x
From module 1
From module 2
DVSS
P2.5/TB0.0/UCA1TXD/UCA1SIMO
P2.6/TB1.0/UCA1RXD/UCA1SOMI
P2SEL0.x
P2SEL1.x
P2IN.x
Bus
Keeper
EN
D
To modules
Table 48. Port P2 (P2.5 to P2.6) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x P2SEL1.x P2SEL0.x
(1)
P2.5/TB0.0/UCA1TXD/UCA1SIMO
5
P2.5(I/O)
I: 0; O: 1
0
0
(1)
TB0.CCI0B
0
1
0
1
(1)
TB0.0
(1)
(2)
UCA1TXD/UCA1SIMO
X
1
0
0
0
(1)
P2.6/TB1.0/UCA1RXD/UCA1SOMI
6
P2.6(I/O)
I: 0; O: 1
(1)
TB1.CCI0B
0
1
0
1
1
0
(1)
TB1.0
(1)
(2)
UCA1RXD/UCA1SOMI
X
(1) Not available on all devices and package types.
(2) Direction controlled by eUSCI_A1 module.
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Port P2, P2.7, Input/Output With Schmitt Trigger
Pad Logic
P2REN.x
0 0
0 1
1 0
1 1
P2DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P2OUT.x
DVSS
DVSS
P2.7
DVSS
P2SEL0.x
P2SEL1.x
P2IN.x
Bus
Keeper
EN
D
To modules
Table 49. Port P2 (P2.7) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x P2SEL1.x P2SEL0.x
(1)
P2.7
7
P2.7(I/O)
I: 0; O: 1
0
0
(1) Not available on all devices and package types.
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SLAS639D –JULY 2011–REVISED AUGUST 2012
Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CDPD.x
P3REN.x
0 0
0 1
1 0
1 1
P3DIR.x
DVSS
DVCC
0
Direction
0: Input
1: Output
1
1
0 0
0 1
1 0
1 1
P3OUT.x
DVSS
DVSS
DVSS
P3.0/A12/CD12
P3.1/A13/CD13
P3.2/A14/CD14
P3.3/A15/CD15
P3SEL0.x
P3SEL1.x
P3IN.x
Bus
Keeper
EN
D
To modules
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Table 50. Port P3 (P3.0 to P3.3) Pin Functions
CONTROL BITS/SIGNALS
P3DIR.x P3SEL1.x P3SEL0.x
PIN NAME (P3.x)
P3.0/A12/CD12
x
FUNCTION
0
P3.0 (I/O)
I: 0; O: 1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(1) (2)
A12
X
(1) (3)
CD12
P3.1/A13/CD13
P3.2/A14/CD14
P3.3/A15/CD15
1
2
3
P3.1 (I/O)
I: 0; O: 1
(1) (2)
A13
X
I: 0; O: 1
X
(1) (3)
CD13
P3.2 (I/O)
(1) (2)
A14
(1) (3)
CD14
P3.3 (I/O)
I: 0; O: 1
X
(1) (2)
A15
(1) (3)
CD15
(1) Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(2) Not available on all devices and package types.
(3) Setting the CDPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the CDx input pin to the comparator multiplexer with the CDx bits automatically disables output
driver and input buffer for that pin, regardless of the state of the associated CDPD.x bit.
80
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Port P3, P3.4 to P3.6, Input/Output With Schmitt Trigger
Pad Logic
DVSS
P3REN.x
0 0
0 1
1 0
1 1
P3DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P3OUT.x
From module 1
DVSS
P3.4/TB1.1/TB2CLK/SMCLK
P3.5/TB1.2/CDOUT
P3.6/TB2.1/TB1CLK
From module 2
P3SEL0.x
P3SEL1.x
P3IN.x
Bus
Keeper
EN
D
To modules
Table 51. Port P3 (P3.4 to P3.6) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x P3SEL1.x P3SEL0.x
(1)
P3.4/TB1.1/TB2CLK/SMCLK
4
P3.4 (I/O)
I: 0; O: 1
0
0
(1)
TB1.CCI1B
0
0
1
(1)
TB1.1
1
(1)
TB2CLK
0
1
0
0
1
0
1
(1)
SMCLK
1
(1)
P3.5/TB1.2/CDOUT
P3.6/TB2.1/TB1CLK
5
6
P3.5 (I/O)
I: 0; O: 1
(1)
TB1.CCI2B
0
(1)
TB1.2
1
(1)
CDOUT
1
1
0
1
0
(1)
P3.6 (I/O)
I: 0; O: 1
(1)
TB2.CCI1B
0
1
0
0
1
1
1
(1)
TB2.1
(1)
TB1CLK
(1) Not available on all devices and package types.
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Port P3, P3.7, Input/Output With Schmitt Trigger
Pad Logic
P3REN.x
0 0
0 1
1 0
1 1
P3DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P3OUT.x
From module 1
DVSS
DVSS
P3.7/TB2.2
P3SEL0.x
P3SEL1.x
P3IN.x
Bus
Keeper
EN
D
To modules
Table 52. Port P3 (P3.7) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x P3SEL1.x P3SEL0.x
(1)
P3.7/TB2.2
7
P3.7 (I/O)
I: 0; O: 1
0
0
(1)
TB2.CCI2B
0
1
0
1
(1)
TB2.2
(1) Not available on all devices and package types.
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Port P4, P4.0, Input/Output With Schmitt Trigger
Pad Logic
P4REN.x
0 0
0 1
1 0
1 1
P4DIR.x
DVSS
DVCC
0
Direction
0: Input
1: Output
1
1
0 0
0 1
1 0
1 1
P4OUT.x
From module 1
DVSS
DVSS
P4.0/TB2.0
P4SEL0.x
P4SEL1.x
P4IN.x
Bus
Keeper
EN
D
To modules
Table 53. Port P4 (P4.0) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x P4SEL1.x P4SEL0.x
(1)
P4.0/TB2.0
0
P4.0 (I/O)
I: 0; O: 1
0
0
(1)
TB2.CCI0B
0
1
0
1
(1)
TB2.0
(1) Not available on all devices and package types.
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Port P4, P4.1, Input/Output With Schmitt Trigger
Pad Logic
P4REN.x
0 0
0 1
1 0
1 1
P4DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P4OUT.x
DVSS
DVSS
P4.1
DVSS
P4SEL0.x
P4SEL1.x
P4IN.x
Bus
Keeper
EN
D
To modules
Table 54. Port P4 (P4.1) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x P4SEL1.x P4SEL0.x
(1)
P4.1
1
P4.1 (I/O)
I: 0; O: 1
0
0
(1) Not available on all devices and package types.
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Port J, J.0 to J.3 JTAG pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or
Output
To Comparator
From Comparator
CDPD.x
From JTAG
From JTAG
From JTAG
Pad Logic
1
0
PJREN.x
PJDIR.x
0 0
0 1
1 0
1 1
1
0
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
JTAG enable
0 0
0 1
1 0
1 1
PJOUT.x
From module 1
DVSS
1
0
PJ.0/TDO/TB0OUTH/SMCLK/CD6
PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7
PJ.2/TMS/TB2OUTH/ACLK/CD8
DVSS
PJSEL0.x
PJSEL1.x
PJIN.x
Bus
Keeper
EN
D
To modules
and JTAG
To Comparator
From Comparator
CDPD.x
Pad Logic
From JTAG
From JTAG
From JTAG
1
0
PJREN.x
PJDIR.x
0 0
0 1
1 0
1 1
1
0
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
JTAG enable
0 0
0 1
1 0
1 1
PJOUT.x
DVSS
1
0
DVSS
DVSS
PJ.3/TCK/CD9
PJSEL0.x
PJSEL1.x
PJIN.x
Bus
Keeper
EN
D
To modules
and JTAG
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(1)
Table 55. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS/ SIGNALS
PIN NAME (PJ.x)
x
FUNCTION
PJDIR.x PJSEL1.x PJSEL0.x
(2)
PJ.0/TDO/TB0OUTH/SMCLK/CD6
0
PJ.0 (I/O)
I: 0; O: 1
0
0
(3)
TDO
X
X
X
TB0OUTH
SMCLK
CD6
0
0
1
1
X
1
0
X
1
0
X
(2)
PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7
PJ.2/TMS/TB2OUTH/ACLK/CD8
PJ.3/TCK/CD9
1
2
3
PJ.1 (I/O)
TDI/TCLK
TB1OUTH
MCLK
I: 0; O: 1
(3) (4)
X
0
0
1
1
CD7
X
1
0
X
1
0
X
(2)
PJ.2 (I/O)
I: 0; O: 1
(3) (4)
TMS
X
TB2OUTH
ACLK
0
0
1
1
CD8
X
1
0
X
1
1
0
X
1
(2)
PJ.3 (I/O)
I: 0; O: 1
(3) (4)
TCK
X
X
CD9
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module. JTAG mode selection is made by the SYS module or by the Spy-Bi-Wire four-wire
entry sequence. PJSEL1.x and PJSEL0.x have no effect in these cases.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.
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Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt Trigger
Pad Logic
To XT1 XIN
PJREN.4
0 0
0 1
1 0
1 1
PJDIR.4
DVSS
DVCC
0
Direction
0: Input
1: Output
1
1
0 0
0 1
1 0
1 1
PJOUT.4
DVSS
DVSS
DVSS
PJ.4/XIN
PJSEL0.4
PJSEL1.4
PJIN.4
Bus
Keeper
EN
D
To modules
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Pad Logic
To XT1 XOUT
PJSEL0.4
XT1BYPASS
PJREN.5
0 0
0 1
1 0
1 1
PJDIR.5
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
PJOUT.5
DVSS
DVSS
DVSS
PJ.5/XOUT
PJSEL0.5
PJSEL1.5
PJIN.5
Bus
Keeper
EN
D
To modules
Table 56. Port PJ (PJ.4 and PJ.5) Pin Functions
(1)
CONTROL BITS/SIGNALS
PIN NAME (P7.x)
x
FUNCTION
XT1
BYPASS
PJDIR.x PJSEL1.5 PJSEL0.5 PJSEL1.4 PJSEL0.4
PJ.4/XIN
4
PJ.4 (I/O)
I: 0; O: 1
X
X
X
0
X
X
X
0
0
0
0
0
0
1
1
0
X
0
1
X
(2)
XIN crystal mode
XIN bypass mode
PJ.5 (I/O)
X
X
(2)
PJ.5/XOUT
5
I: 0; O: 1
XOUT crystal mode
X
X
X
X
X
0
0
1
1
0
1
(3)
(4)
PJ.5 (I/O)
I: 0; O: 1
(1) X = Don't care
(2) Setting PJSEL1.4 = 0 and PJSEL0.4 = 1 causes the general-purpose I/O to be disabled. When XT1BYPASS = 0, PJ.4 and PJ.5 are
configured for crystal operation and PJSEL1.5 and PJSEL0.5 are do not care. When XT1BYPASS = 1, PJ.4 is configured for bypass
operation and PJ.5 is configured as general-purpose I/O.
(3) Setting PJSEL1.4 = 0 and PJSEL0.4 = 1 causes the general-purpose I/O to be disabled. When XT1BYPASS = 0, PJ.4 and PJ.5 are
configured for crystal operation and PJSEL1.5 and PJSEL0.5 are do not care. When XT1BYPASS = 1, PJ.4 is configured for bypass
operation and PJ.5 is configured as general-purpose I/O.
(4) When PJ.4 is configured in bypass mode, PJ.5 is configured as general-purpose I/O.
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DEVICE DESCRIPTORS (TLV)
The following tables list the complete contents of the device descriptor tag-length-value (TLV) structure for each
device type.
(1)
Table 57. Device Descriptor Table
FR5739
Value
05h
FR5738
Value
05h
FR5737
Value
05h
FR5736
Value
05h
FR5735
Value
05h
Description
Address
Info Block
Info length
01A00h
01A01h
01A02h
01A03h
01A04h
01A05h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Bh
01A0Ch
01A0Dh
01A0Eh
01A0Fh
01A10h
01A11h
01A12h
01A13h
CRC length
05h
05h
05h
05h
05h
per unit
per unit
03h
per unit
per unit
02h
per unit
per unit
01h
per unit
per unit
77h
per unit
per unit
76h
CRC value
Device ID
Device ID
81h
81h
81h
81h
81h
Hardware revision
Firmware revision
Die Record Tag
Die Record length
per unit
per unit
08h
per unit
per unit
08h
per unit
per unit
08h
per unit
per unit
08h
per unit
per unit
08h
Die Record
0Ah
0Ah
0Ah
0Ah
0Ah
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Lot/Wafer ID
Die X position
Die Y position
Test results
ADC10
Calibration
ADC10 Calibration
Tag
01A14h
01A15h
13h
10h
13h
10h
13h
10h
05h
10h
13h
10h
ADC10 Calibration
length
01A16h
01A17h
01A18h
01A19h
01A1Ah
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
per unit
per unit
per unit
per unit
per unit
ADC Gain Factor
ADC Offset
ADC 1.5-V
Reference
01A1Bh
01A1Ch
01A1Dh
01A1Eh
01A1Fh
01A20h
01A21h
01A22h
01A23h
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Temp. Sensor 30°C
ADC 1.5-V
Reference
Temp. Sensor 85°C
ADC 2.0-V
Reference
Temp. Sensor 30°C
ADC 2.0-V
Reference
Temp. Sensor 85°C
ADC 2.5-V
Reference
Temp. Sensor 30°C
(1) NA = Not applicable
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Table 57. Device Descriptor Table (1) (continued)
FR5739
Value
FR5738
Value
FR5737
Value
NA
FR5736
Value
NA
FR5735
Value
Description
Address
ADC 2.5-V
Reference
Temp. Sensor 85°C
01A24h
01A25h
per unit
per unit
per unit
per unit
12h
per unit
12h
NA
NA
per unit
12h
REF
Calibration
REF Calibration Tag
01A26h
01A27h
12h
12h
REF Calibration
length
06h
06h
06h
06h
06h
01A28h
01A29h
01A2Ah
01A2Bh
01A2Ch
01A2Dh
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
REF 1.5-V
Reference
REF 2.0-V
Reference
REF 2.5-V
Reference
(1)
Table 58. Device Descriptor Table
FR5734
Value
05h
FR5733
Value
05h
FR5732
Value
05h
FR5731
Value
05h
FR5730
Value
05h
Description
Address
Info Block
Info length
01A00h
01A01h
01A02h
01A03h
01A04h
01A05h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Bh
01A0Ch
01A0Dh
01A0Eh
01A0Fh
01A10h
01A11h
01A12h
01A13h
CRC length
05h
05h
05h
05h
05h
per unit
per unit
00h
per unit
per unit
7Fh
per unit
per unit
75h
per unit
per unit
7Eh
per unit
per unit
7Ch
CRC value
Device ID
Device ID
81h
80h
81h
80h
80h
Hardware revision
Firmware revision
Die Record Tag
Die Record length
per unit
per unit
08h
per unit
per unit
08h
per unit
per unit
08h
per unit
per unit
08h
per unit
per unit
08h
Die Record
0Ah
0Ah
0Ah
0Ah
0Ah
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Lot/Wafer ID
Die X position
Die Y position
Test results
ADC10
Calibration
ADC10 Calibration
Tag
01A14h
01A15h
13h
10h
13h
10h
13h
10h
05h
10h
13h
10h
ADC10 Calibration
length
01A16h
01A17h
01A18h
01A19h
01A1Ah
per unit
per unit
per unit
per unit
per unit
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC Gain Factor
ADC Offset
ADC 1.5-V
Reference
Temp. Sensor 30°C
01A1Bh
per unit
NA
NA
per unit
per unit
(1) NA = Not applicable
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Table 58. Device Descriptor Table (1) (continued)
FR5734
Value
FR5733
Value
NA
FR5732
Value
NA
FR5731
Value
FR5730
Value
Description
Address
ADC 1.5-V
Reference
Temp. Sensor 85°C
01A1Ch
01A1Dh
01A1Eh
01A1Fh
01A20h
01A21h
01A22h
01A23h
01A24h
01A25h
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.0-V
Reference
Temp. Sensor 30°C
ADC 2.0-V
Reference
Temp. Sensor 85°C
ADC 2.5-V
Reference
Temp. Sensor 30°C
ADC 2.5-V
Reference
Temp. Sensor 85°C
REF
Calibration
REF Calibration Tag
01A26h
01A27h
12h
06h
12h
06h
12h
06h
12h
06h
12h
06h
REF Calibration
length
01A28h
01A29h
01A2Ah
01A2Bh
01A2Ch
01A2Dh
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
REF 1.5-V
Reference
REF 2.0-V
Reference
REF 2.5-V
Reference
(1)
Table 59. Device Descriptor Table
FR5729
Value
05h
FR5728
Value
05h
FR5727
Value
05h
FR5726
Value
05h
FR5725
Value
05h
Description
Address
Info Block
Info length
01A00h
01A01h
01A02h
01A03h
01A04h
01A05h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Bh
01A0Ch
01A0Dh
01A0Eh
01A0Fh
01A10h
01A11h
01A12h
01A13h
CRC length
05h
05h
05h
05h
05h
per unit
per unit
7Bh
per unit
per unit
7Ah
per unit
per unit
79h
per unit
per unit
74h
per unit
per unit
78h
CRC value
Device ID
Device ID
80h
80h
80h
81h
80h
Hardware revision
Firmware revision
Die Record Tag
Die Record length
per unit
per unit
08h
per unit
per unit
08h
per unit
per unit
08h
per unit
per unit
08h
per unit
per unit
08h
Die Record
0Ah
0Ah
0Ah
0Ah
0Ah
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Lot/Wafer ID
Die X position
Die Y position
Test results
(1) NA = Not applicable
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Table 59. Device Descriptor Table (1) (continued)
FR5729
Value
FR5728
Value
FR5727
Value
FR5726
Value
FR5725
Value
Description
Address
ADC10
Calibration
ADC10 Calibration
Tag
01A14h
01A15h
13h
10h
13h
10h
13h
10h
05h
10h
13h
10h
ADC10 Calibration
length
01A16h
01A17h
01A18h
01A19h
01A1Ah
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
per unit
per unit
per unit
per unit
per unit
ADC Gain Factor
ADC Offset
ADC 1.5-V
Reference
01A1Bh
01A1Ch
01A1Dh
01A1Eh
01A1Fh
01A20h
01A21h
01A22h
01A23h
01A24h
01A25h
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Temp. Sensor 30°C
ADC 1.5-V
Reference
Temp. Sensor 85°C
ADC 2.0-V
Reference
Temp. Sensor 30°C
ADC 2.0-V
Reference
Temp. Sensor 85°C
ADC 2.5-V
Reference
Temp. Sensor 30°C
ADC 2.5-V
Reference
Temp. Sensor 85°C
REF
Calibration
REF Calibration Tag
01A26h
01A27h
12h
06h
12h
06h
12h
06h
12h
06h
12h
06h
REF Calibration
length
01A28h
01A29h
01A2Ah
01A2Bh
01A2Ch
01A2Dh
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
REF 1.5-V
Reference
REF 2.0-V
Reference
REF 2.5-V
Reference
(1)
Table 60. Device Descriptor Table
FR5724
Value
05h
FR5723
Value
05h
FR5722
Value
05h
FR5721
Value
05h
FR5720
Value
05h
Description
Address
Info Block
Info length
01A00h
01A01h
01A02h
01A03h
01A04h
01A05h
01A06h
01A07h
01A08h
01A09h
CRC length
05h
05h
05h
05h
05h
per unit
per unit
73h
per unit
per unit
72h
per unit
per unit
71h
per unit
per unit
77h
per unit
per unit
70h
CRC value
Device ID
Device ID
81h
81h
81h
80h
81h
Hardware revision
Firmware revision
Die Record Tag
Die Record length
per unit
per unit
08h
per unit
per unit
08h
per unit
per unit
08h
per unit
per unit
08h
per unit
per unit
08h
Die Record
0Ah
0Ah
0Ah
0Ah
0Ah
(1) NA = Not applicable
92 Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
MSP430FR573x
MSP430FR572x
www.ti.com
SLAS639D –JULY 2011–REVISED AUGUST 2012
Table 60. Device Descriptor Table (1) (continued)
FR5724
Value
FR5723
Value
FR5722
Value
FR5721
Value
FR5720
Value
Description
Address
01A0Ah
01A0Bh
01A0Ch
01A0Dh
01A0Eh
01A0Fh
01A10h
01A11h
01A12h
01A13h
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Lot/Wafer ID
Die X position
Die Y position
Test results
ADC10
Calibration
ADC10 Calibration
Tag
01A14h
01A15h
13h
10h
13h
10h
13h
10h
05h
10h
13h
10h
ADC10 Calibration
length
01A16h
01A17h
01A18h
01A19h
01A1Ah
per unit
per unit
per unit
per unit
per unit
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC Gain Factor
ADC Offset
ADC 1.5-V
Reference
01A1Bh
01A1Ch
01A1Dh
01A1Eh
01A1Fh
01A20h
01A21h
01A22h
01A23h
01A24h
01A25h
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Temp. Sensor 30°C
ADC 1.5-V
Reference
Temp. Sensor 85°C
ADC 2.0-V
Reference
Temp. Sensor 30°C
ADC 2.0-V
Reference
Temp. Sensor 85°C
ADC 2.5-V
Reference
Temp. Sensor 30°C
ADC 2.5-V
Reference
Temp. Sensor 85°C
REF
Calibration
REF Calibration Tag
01A26h
01A27h
12h
06h
12h
06h
12h
06h
12h
06h
12h
06h
REF Calibration
length
01A28h
01A29h
01A2Ah
01A2Bh
01A2Ch
01A2Dh
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
REF 1.5-V
Reference
REF 2.0-V
Reference
REF 2.5-V
Reference
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
93
MSP430FR573x
MSP430FR572x
SLAS639D –JULY 2011–REVISED AUGUST 2012
www.ti.com
REVISION HISTORY
REVISION
COMMENTS
SLAS639
SLAS639A
SLAS639B
SLAS639C
SLAS639D
Product Preview release
Updated Product Preview release including preliminary electrical specifications
Changes throughout for updated Product Preview
Production Data release
Changed PW package options from Product Preview to Production Data.
Added information for YFF package option throughout as Product Preview.
Table 26 and Table 27, Changed offset of PxSELC registers.
Table 28, Added PJSELC register.
Table 29, Removed registers that do no apply (TA0CCTL3,4 and TA0CCR3,4)
Absolute Maximum Ratings, Changed low limit of Tstg from -40°C to -55°C.
FRAM, Added tRetention MIN values for TJ = 25°C and TJ = 70°C.
94
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
MSP430FR5720IPWR
MSP430FR5720IRGER
MSP430FR5720IRGET
MSP430FR5721IDA
PREVIEW
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
TSSOP
VQFN
VQFN
TSSOP
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
PW
RGE
RGE
DA
28
24
24
38
38
40
40
28
24
24
38
38
40
40
28
24
24
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
40
Green (RoHS
& no Sb/Br)
MSP430FR5721IDAR
MSP430FR5721IRHAR
MSP430FR5721IRHAT
MSP430FR5722IPWR
MSP430FR5722IRGER
MSP430FR5722IRGET
MSP430FR5723IDA
DA
2000
2500
250
Green (RoHS
& no Sb/Br)
RHA
RHA
PW
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
RGE
RGE
DA
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
40
Green (RoHS
& no Sb/Br)
MSP430FR5723IDAR
MSP430FR5723IRHAR
MSP430FR5723IRHAT
MSP430FR5724IPWR
MSP430FR5724IRGER
MSP430FR5724IRGET
DA
2000
2500
250
Green (RoHS
& no Sb/Br)
RHA
RHA
PW
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
RGE
RGE
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2012
Status (1)
PREVIEW
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PREVIEW
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
MSP430FR5725IDA
MSP430FR5725IDAR
MSP430FR5725IRHAR
MSP430FR5726IPWR
MSP430FR5726IRGER
MSP430FR5726IRGET
MSP430FR5727IDA
TSSOP
TSSOP
VQFN
DA
DA
38
38
40
28
24
24
38
38
40
40
28
24
24
38
38
40
28
24
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
2000
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
RHA
PW
Green (RoHS
& no Sb/Br)
TSSOP
VQFN
Green (RoHS
& no Sb/Br)
RGE
RGE
DA
3000
250
Green (RoHS
& no Sb/Br)
VQFN
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
VQFN
40
Green (RoHS
& no Sb/Br)
MSP430FR5727IDAR
MSP430FR5727IRHAR
MSP430FR5727IRHAT
MSP430FR5728IPWR
MSP430FR5728IRGER
MSP430FR5728IRGET
MSP430FR5729IDA
DA
2000
2500
250
Green (RoHS
& no Sb/Br)
RHA
RHA
PW
Green (RoHS
& no Sb/Br)
VQFN
Green (RoHS
& no Sb/Br)
TSSOP
VQFN
Green (RoHS
& no Sb/Br)
RGE
RGE
DA
3000
250
Green (RoHS
& no Sb/Br)
VQFN
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
VQFN
40
Green (RoHS
& no Sb/Br)
MSP430FR5729IDAR
MSP430FR5729IRHAR
MSP430FR5730IPW
MSP430FR5730IRGER
DA
2000
2500
Green (RoHS
& no Sb/Br)
RHA
PW
Green (RoHS
& no Sb/Br)
TSSOP
VQFN
Green (RoHS
& no Sb/Br)
RGE
3000
Green (RoHS
& no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2012
Status (1)
ACTIVE
PREVIEW
ACTIVE
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
MSP430FR5730IRGET
MSP430FR5731IDA
VQFN
TSSOP
TSSOP
VQFN
RGE
DA
24
38
38
40
40
28
24
24
38
38
40
40
28
24
24
38
38
40
250
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
MSP430FR5731IDAR
MSP430FR5731IRHAR
MSP430FR5731IRHAT
MSP430FR5732IPWR
MSP430FR5732IRGER
MSP430FR5732IRGET
MSP430FR5733IDA
DA
2000
2500
250
Green (RoHS
& no Sb/Br)
RHA
RHA
PW
Green (RoHS
& no Sb/Br)
VQFN
Green (RoHS
& no Sb/Br)
TSSOP
VQFN
Green (RoHS
& no Sb/Br)
RGE
RGE
DA
3000
250
Green (RoHS
& no Sb/Br)
VQFN
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
VQFN
40
Green (RoHS
& no Sb/Br)
MSP430FR5733IDAR
MSP430FR5733IRHAR
MSP430FR5733IRHAT
MSP430FR5734IPWR
MSP430FR5734IRGER
MSP430FR5734IRGET
MSP430FR5735IDA
DA
2000
2500
250
Green (RoHS
& no Sb/Br)
RHA
RHA
PW
Green (RoHS
& no Sb/Br)
VQFN
Green (RoHS
& no Sb/Br)
TSSOP
VQFN
Green (RoHS
& no Sb/Br)
RGE
RGE
DA
3000
250
Green (RoHS
& no Sb/Br)
VQFN
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
VQFN
40
Green (RoHS
& no Sb/Br)
MSP430FR5735IDAR
MSP430FR5735IRHAR
DA
2000
2500
Green (RoHS
& no Sb/Br)
RHA
Green (RoHS
& no Sb/Br)
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2012
Status (1)
PREVIEW
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
MSP430FR5736IPWR
MSP430FR5736IRGER
MSP430FR5736IRGET
MSP430FR5737IDA
TSSOP
VQFN
VQFN
TSSOP
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
TSSOP
VQFN
VQFN
PW
RGE
RGE
DA
28
24
24
38
38
40
40
28
24
24
38
38
40
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
40
Green (RoHS
& no Sb/Br)
MSP430FR5737IDAR
MSP430FR5737IRHAR
MSP430FR5737IRHAT
MSP430FR5738IPWR
MSP430FR5738IRGER
MSP430FR5738IRGET
MSP430FR5739IDA
DA
2000
2500
250
Green (RoHS
& no Sb/Br)
RHA
RHA
PW
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
RGE
RGE
DA
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
40
Green (RoHS
& no Sb/Br)
MSP430FR5739IDAR
MSP430FR5739IRHAR
MSP430FR5739IRHAT
DA
2000
2500
250
Green (RoHS
& no Sb/Br)
RHA
RHA
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2012
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 5
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products
Audio
Applications
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
Medical
Logic
Security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense www.ti.com/space-avionics-defense
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
www.ti.com/video
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
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