MSP430FR58721IPMR [TI]
具有 64KB FRAM、2KB SRAM、12 位 ADC、比较器、DMA、UART/SPI/I2C 和计时器的 16MHz MCU | PM | 64 | -40 to 85;
| 型号： | MSP430FR58721IPMR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 64KB FRAM、2KB SRAM、12 位 ADC、比较器、DMA、UART/SPI/I2C 和计时器的 16MHz MCU | PM | 64 | -40 to 85 时钟 静态存储器 外围集成电路 比较器 装置 |
| 文件： | 总147页 (文件大小：3058K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
MSP430FR597x(1)、MSP430FR592x(1) MSP430FR587x(1) 混合信号
微控制器
1 器件概述
1.1 特性
1
– 针对随机数生成算法的真随机种子
– 用于 IP 封装和安全存储的可锁定内存段
• 多功能输入/输出端口
• 嵌入式微控制器
– 高达 16MHz 时钟频率的 16 位 RISC 架构
– 3.6V 至 1.8V 的宽电源电压范围（最低电源电压
受限于 SVS 电平，请参阅 SVS 规格）
– 所有 I/O 引脚均支持电容触摸功能，无需外部组
件
• 经优化的超低功耗模式
– 可每位、每字节和每字访问（成对访问）
– 可通过 P1 至 P4 端口从 LPM 唤醒，边沿可选
– 所有端口上可编程上拉和下拉
– 工作模式：大约 100µA/MHz
– 待机（具有低功率低频内部时钟源 (VLO) 的
LPM3）：0.4µA（典型值）
– 实时时钟 (RTC) (LPM3.5)：0.35µA（典型值）
• 增强型串行通信
(1)
– eUSCI_A0 和 eUSCI_A1 支持：
– 关断电流 (LPM4.5)：0.04µA（典型值）
• 超低功耗铁电 RAM (FRAM)
– 支持自动波特率侦测的通用异步收发器
(UART)
– 高达 64KB 的非易失性存储器
– 超低功耗写入
– 125ns 每个字的快速写入（4ms 内写入 64KB）
– 统一标准存储器 = 单个空间内的程序、数据和存
储
– 1015 写入周期持久性
– 抗辐射和非磁性
– IrDA 编码和解码
– 速率高达 10Mbps 的串行外设接口 (SPI)
– eUSCI_B0 和 eUSCI_B1 均支持：
– 支持多从器件寻址的 I2C
– 速率高达 10Mbps 的串行外设接口 (SPI)
• 灵活时钟系统
– 具有 10 个可选厂家调整频率的定频数控振荡器
• 智能数字外设
(DCO)
– 32 位硬件乘法器 (MPY)
– 三通道内部直接存储器存取 (DMA)
– 带有日历和和报警功能的 RTC
– 低功率低频内部时钟源 (VLO)
– 32kHz 晶振 (LFXT)
– 高频晶振 (HFXT)
– 5 个具有多达 7 个捕捉/比较寄存器的 16 位定时
器
• 开发工具和软件
– 自由的专业开发环境将 EnergyTrace++™ 技术用
于电源配置和调试
– 16 位和 32 位循环冗余校验器（CRC16、
CRC32）
• 高性能模拟
– 提供微控制器开发板
• 系列产品
– 多达 8 通道的模拟比较器
– 12 位模数转换器 (ADC)，具有内部基准和采样保
持以及多达 8 个外部输入通道
– 器件比较 汇总了可用变型和封装
• 要获得完整的模块说明，请参见
《MSP430FR58xx、MSP430FR59xx 和
MSP430FR6xx 系列用户指南》
• 代码安全性和加密
– 128 位或 256 位 AES 安全加密和解密协处理器
（只适用于 MSP430FR59xx(1)）
(1) RTC 由 3.7pF 晶振计时。
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASE66
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
1.2 应用
•
•
•
计量
•
•
传感器管理
数据日志
能量采集传感器节点
可穿戴电子产品
1.3 说明
该系列超低功耗 MSP430FRxx FRAM 微控制器种类繁多，各成员器件配有嵌入式非易失性 FRAM、16 位
CPU 以及不同的外设集以满足各类应用的 需求。这种架构、FRAM 和外设与 7 种低功耗模式相组合，专为
在便携式无线感测应用中延长电池的使用寿命而进行了 优化。FRAM 是全新的非易失性存储器，其完美结
合了 SRAM 的速度、灵活性和耐用性与闪存的稳定性和可靠性，并且总功耗更低。
器件信息(1)
封装
器件型号
MSP430FR5972IPMR
MSP430FR5972IRGC
MSP430FR5922IG56
封装尺寸(2)
10mm x 10mm
9mm x 9mm
LQFP (64)
VQFN (64)
TSSOP (56)
6.1mm x 14mm
(1) 要获得所有可用器件的最新部件、封装和订购信息，请参见封装选项附录（节 9）或浏览 TI 网站
www.ti.com.cn。
(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参见机械数据（节 9）。
2
器件概述
版权 © 2015–2018, Texas Instruments Incorporated
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
1.4 功能框图
图 1-1 给出了功能框图。
中的 48KB RAM 选项
P1.x,P2.x P3.x,P4.x P5.x,P6.x
up to
2x8
P7.x
up to
1x8
P9.x
PJ.x
up to
1x8
up to
2x8
up to
2x8
up to
1x8
LFXIN/ LFXOUT/
HFXIN HFXOUT
Capacitive Touch IO 0, Capacitive Touch IO 1
I/O Ports I/O Ports
P3, P4
2x8 I/Os
I/O Port
P5, P6
2x8 I/Os
I/O Port
P7
1x8 I/Os
I/O Port
P9
1x8 I/Os
I/O Port
PJ
1x8 I/Os
Comp_E
ADC12_B
REF_A
P1, P2
2x8 I/Os
MCLK
ACLK
Clock
System
(up to 16
inputs)
(up to 16
std. inputs,
up to 8
Voltage
Reference
SMCLK
PA
PB
PC
PD
1x16 I/Os 1x16 I/Os 1x16 I/Os 1x8 I/Os
PE
1x8 I/Os
diff. inputs)
DMA
Controller
Channel
3
MAB
MDB
Bus
Control
Logic
CPUXV2
incl. 16
Registers
MPU
IP Encap
CRC16
TA2
TA 3
Power
Mgmt
AES256
RAM
2KB
CRC-16-
CCITT
FRAM
Watchdog
Security
En-/De-
cryption
(128/256)
Timer_A
2 CC
Registers
(int. only)
Timer_A
5 CC
Registers
MPY32
LDO
SVS
Brownout
CRC32
64KB
32KB
EEM
(S: 3+1)
Tiny RAM
26B
CRC-32-
ISO-3309
MDB
MAB
JTAG
Interface
Spy-Bi-
Wire
TB0
TA0
TA1
RTC_C
eUSCI_A0
eUSCI_A1
eUSCI_B0
eUSCI_B1
Calendar
Timer_B
7 CC
Registers
(int./ext.)
Timer_A
3 CC
Registers
(int./ext.)
Timer_A
3 CC
Registers
(int./ext.)
and
Counter
Mode
(I2C, SPI)
(UART,
IrDA,
SPI)
LPM3.5 Domain
Copyright © 2016, Texas Instruments Incorporated
NOTE: MSP430FR587x 和 MSP430FR587x1 器件中未实现 AES256。
NOTE: MSP430FR592x 和 MSP430FR592x1 器件中未实现 HFXIN 和 HFOUT。
图 1-1. 功能框图
版权 © 2015–2018, Texas Instruments Incorporated
器件概述
3
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
内容
1
器件概述.................................................... 1
1.1 特性 ................................................... 1
1.2 应用 ................................................... 2
1.3 说明 ................................................... 2
1.4 功能框图 .............................................. 3
修订历史记录............................................... 5
Device Comparison ..................................... 6
3.1 Related Products ..................................... 8
Terminal Configuration and Functions.............. 9
4.1 Pin Diagrams ......................................... 9
4.2 Pin Attributes ........................................ 12
4.3 Signal Descriptions.................................. 17
4.4 Pin Multiplexing ..................................... 23
4.5 Buffer Type.......................................... 23
4.6 Connection of Unused Pins ......................... 23
Specifications ........................................... 24
5.1 Absolute Maximum Ratings......................... 24
5.2 ESD Ratings ........................................ 24
5.3 Recommended Operating Conditions............... 24
5.12 Timing and Switching Characteristics ............... 32
Detailed Description ................................... 58
6.1 Overview ............................................ 58
6.2 CPU ................................................. 58
6.3 Operating Modes .................................... 59
6.4 Interrupt Vector Table and Signatures .............. 61
6.5 Bootloader (BSL).................................... 64
6.6 JTAG Operation ..................................... 64
6.7 FRAM................................................ 65
6.8 RAM ................................................. 65
6
2
3
4
6.9 Tiny RAM............................................ 65
6.10 Memory Protection Unit (MPU) Including IP
Encapsulation ....................................... 65
6.11 Peripherals .......................................... 66
6.12 Device Descriptors (TLV) .......................... 101
6.13 Memory ............................................ 104
6.14 Identification........................................ 118
Applications, Implementation, and Layout ...... 119
5
7
8
7.1
Device Connection and Layout Fundamentals .... 119
Peripheral- and Interface-Specific Design
7.2
5.4
5.5
5.6
5.7
5.8
5.9
Active Mode Supply Current Into VCC Excluding
External Current .................................... 25
Typical Characteristics - Active Mode Supply
Information ......................................... 123
器件和文档支持......................................... 125
8.1 入门和后续步骤 .................................... 125
8.2 器件命名规则....................................... 125
8.3 工具与软件 ......................................... 126
8.4 文档支持 ........................................... 128
8.5 相关链接 ........................................... 129
8.6 社区资源 ........................................... 129
8.7 商标 ................................................ 130
8.8 静电放电警告....................................... 130
8.9 出口管制提示....................................... 130
8.10 术语表.............................................. 130
机械、封装和可订购信息 .............................. 131
Currents ............................................. 26
Low-Power Mode (LPM0, LPM1) Supply Currents
Into VCC Excluding External Current ................ 26
Low-Power Mode LPM2, LPM3, LPM4 Supply
Currents (Into VCC) Excluding External Current .... 27
Low-Power Mode LPMx.5 Supply Currents (Into
VCC) Excluding External Current.................... 29
Typical Characteristics, Low-Power Mode Supply
Currents ............................................. 30
5.10 Typical Characteristics, Current Consumption per
Module .............................................. 31
5.11 Thermal Resistance Characteristics ................ 31
9
4
内容
版权 © 2015–2018, Texas Instruments Incorporated
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
2 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from January 25, 2017 to August 30, 2018
Page
•
•
•
•
•
Updated Section 3.1, Related Products ........................................................................................... 8
Added note (1) to 表 5-2, SVS..................................................................................................... 32
Changed capacitor value from 4.7 µF to 470 nF in 图 7-5, ADC12_B Grounding and Noise Considerations ....... 123
Changed capacitor value from 4.7 µF to 470 nF in the last paragraph of 节 7.2.1.2, Design Requirements ......... 124
更新了节 8.2，器件命名规则 中的文本和图 .................................................................................... 125
Copyright © 2015–2018, Texas Instruments Incorporated
修订历史记录
5
Submit Documentation Feedback
Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
3 Device Comparison
Table 3-1 and Table 3-2 summarize the available family members.
Table 3-1. Device Comparison – Family Members With UART BSL
eUSCI
FRAM
(KB)
SRAM
(KB)
CLOCK
SYSTEM
DEVICE
Timer_A(1)
Timer_B(2)
AES
ADC12_B
I/O
PACKAGE
A(3)
B(4)
DCO
HFXT
LFXT
3, 3(5)
2, 5
64 PM
64 RGC
MSP430FR5972
64
64
32
64
32
2
2
2
2
2
7
2
2
2
2
2
2
yes
8 ext
51
(6)(7)
DCO
HFXT
LFXT
3, 3(5)
64 PM
64 RGC
MSP430FR5872
MSP430FR5970
MSP430FR5922
MSP430FR5870
7
7
7
7
2
2
2
2
no
yes
yes
no
8 ext
8 ext
8 ext
8 ext
51
51
(6)(7)
2, 5
DCO
HFXT
LFXT
3, 3(5)
64 PM
64 RGC
(6)(7)
2, 5
64 PM
64 RGC
56 DGG
DCO
LFXT
3, 3(5)
51
46 (DGG)
(6)(7)
2, 5
DCO
HFXT
LFXT
3, 3(5)
64 PM
64 RGC
51
(6)(7)
2, 5
(1) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
(2) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
(3) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
(4) eUSCI_B supports I2C with multiple slave addresses and SPI.
(5) Timer_A TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
(6) Timer_A TA2 provides only internal capture/compare inputs and only internal PWM outputs (if any).
(7) Timer_A TA3 provides only internal capture/compare inputs and only internal PWM outputs (if any) for FR592x(1) with RGC and PM packages. For FR592x(1) with DGG package and all
other devices, Timer_A TA3 provides internal, external capture/compare inputs and internal, external PWM outputs (if any).
6
Device Comparison
Copyright © 2015–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
Table 3-2. Device Comparison – Family Members With I2C BSL
eUSCI
FRAM
(KB)
SRAM
(KB)
CLOCK
SYSTEM
DEVICE
Timer_A(1)
Timer_B(2)
AES
ADC12_B
I/O
PACKAGE
A(3)
B(4)
DCO
HFXT
LFXT
3, 3(5)
2, 5
64 PM
64 RGC
MSP430FR59721
MSP430FR59221
MSP430FR58721
64
64
64
2
2
2
7
2
2
2
2
yes
8 ext
51
(6)(7)
64 PM
64 RGC
56 DGG
DCO
LFXT
3, 3(5)
51
46 (DGG)
7
7
2
2
yes
no
8 ext
8 ext
(6)(7)
2, 5
DCO
HFXT
LFXT
3, 3(5)
64 PM
64 RGC
51
(6)(7)
2, 5
(1) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
(2) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
(3) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
(4) eUSCI_B supports I2C with multiple slave addresses and SPI.
(5) Timer_A TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
(6) Timer_A TA2 provides only internal capture/compare inputs and only internal PWM outputs (if any).
(7) Timer_A TA3 provides only internal capture/compare inputs and only internal PWM outputs (if any) for FR592x(1) with RGC and PM packages. For FR592x(1) with DGG package and all
other devices, Timer_A TA3 provides internal, external capture/compare inputs and internal, external PWM outputs (if any).
Copyright © 2015–2018, Texas Instruments Incorporated
Device Comparison
7
Submit Documentation Feedback
Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
3.1 Related Products
For information about other devices in this family of products or related products, see the following links.
TI 16-bit and 32-bit microcontrollers High-performance, low-power solutions to enable the autonomous
future
Products for MSP430 ultra-low-power sensing and measurement microcontrollers One platform.
One ecosystem. Endless possibilities.
Products for MSP430 ultrasonic and performance sensing microcontrollers Ultra-low-power single-
chip MCUs with integrated sensing peripherals
Companion Products for MSP430FR5972 Review products that are frequently purchased or used with
this product.
Reference Designs for MSP430FR5972 The TI Designs Reference Design Library is a robust reference
design library that spans analog, embedded processor, and connectivity. Created by TI
experts to help you jump start your system design, all TI Designs include schematic or block
diagrams, BOMs, and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.
8
Device Comparison
Copyright © 2015–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
4 Terminal Configuration and Functions
4.1 Pin Diagrams
Figure 4-1 shows the pinout for the 64-pin PM and RGC packages of the MSP430FR597x(1) and
MSP430FR587x(1) MCUs.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P4.3/UCA0SOMI/UCA0RXD/UCB1STE
P1.4/UCB0CLK/UCA0STE/TA1.0
P1.5/UCB0STE/UCA0CLK/TA0.0
P1.6/UCB0SIMO/UCB0SDA/TA0.1
P1.7/UCB0SOMI/UCB0SCL/TA0.2
DNC
1
48 P9.7/A15/C15
2
47 P9.6/A14/C14
3
46 P9.5/A13/C13
4
45 P9.4/A12/C12
5
44 P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
43 P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
42 P1.2/TA1.1/TA0CLK/COUT/A2/C2
41 P1.3/TA1.2/A3/C3
6
P6.0
7
P6.1
8
MSP430FR597x
MSP430FR587x
P6.2/COUT
9
40 DVCC2
P6.3
10
11
12
13
14
15
16
39 DVSS2
P6.4/TB0.0
38 P7.4/SMCLK
P6.5/TB0.1
37 P7.3/TA0.2
P6.6/TB0.2
36 P7.2/TA0.1
P3.0/UCB1CLK/TA3.2
P3.1/UCB1SIMO/UCB1SDA/TA3.3
P3.2/UCB1SOMI/UCB1SCL/TA3.4
35 P7.1/TA0.0/ACLK
34 P7.0/TA0CLK
33 P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
On devices with UART BSL: P2.0: BSL_TX; P2.1: BSL_RX
On devices with I2C BSL: P1.6: BSL_DAT; P1.7: BSL_CLK
NOTE: TI recommends connecting the RGC package thermal pad to VSS.
Figure 4-1. 64-Pin PM and RGC Packages (Top View) – MSP430FR597x(1), MSP430FR587x(1)
Copyright © 2015–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
9
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Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
Figure 4-2 shows the pinout for the 64-pin PM and RGC packages of the MSP430FR592x(1) MCUs.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P4.3/UCA0SOMI/UCA0RXD/UCB1STE
P1.4/UCB0CLK/UCA0STE/TA1.0
P1.5/UCB0STE/UCA0CLK/TA0.0
P1.6/UCB0SIMO/UCB0SDA/TA0.1
P1.7/UCB0SOMI/UCB0SCL/TA0.2
DNC
1
48 P9.7/A15/C15
2
47 P9.6/A14/C14
3
46 P9.5/A13/C13
4
45 P9.4/A12/C12
5
44 P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
43 P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
42 P1.2/TA1.1/TA0CLK/COUT/A2/C2
41 P1.3/TA1.2/A3/C3
6
P6.0
7
P6.1
8
MSP430FR592x
P6.2/COUT
9
40 DVCC2
P6.3
10
11
12
13
14
15
16
39 DVSS2
P6.4/TB0.0
38 P7.4/SMCLK
P6.5/TB0.1
37 P7.3/TA0.2
P6.6/TB0.2
36 P7.2/TA0.1
P3.0/UCB1CLK/TA3.2
P3.1/UCB1SIMO/UCB1SDA/TA3.3
P3.2/UCB1SOMI/UCB1SCL/TA3.4
35 P7.1/TA0.0/ACLK
34 P7.0/TA0CLK
33 P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
A. On devices with UART BSL: P2.0: BSL_TX; P2.1: BSL_RX
On devices with I2C BSL: P1.6: BSL_DAT; P1.7: BSL_CLK
NOTE: TI recommends connecting the RGC package thermal pad to VSS.
Figure 4-2. 64-Pin PM and RGC Packages (Top View) – MSP430FR592x(1)
10
Terminal Configuration and Functions
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Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
Figure 4-3 shows the pinout for the 56-pin DGG package of the MSP430FR592x(1) MCUs.
P4.4/UCB1STE/TA1CLK
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
AVSS2
2
P4.5/UCB1CLK/TA1.0
P4.6/UCB1SIMO/UCB1SDA/TA1.1
P4.7/UCB1SOMI/UCB1SCL/TA1.2
DVSS3
PJ.5/LFXOUT
PJ.4/LFXIN
3
4
AVSS1
5
AVCC1
DVCC3
P1.4/UCB0CLK/UCA0STE/TA1.0
P1.5/UCB0STE/UCA0CLK/TA0.0
6
P9.7/A15/C15
P9.6/A14/C14
P9.5/A13/C13
P9.4/A12/C12
7
8
P1.6/UCB0SIMO/UCB0SDA/TA0.1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
P1.7/UCB0SOMI/UCB0SCL/TA0.2
P1.0/TA0.1/RTCCLK/DMAE0/A0/C0/VREF-/VeREF-
DNC
P6.0
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P1.3/TA1.2/A3/C3
DVCC2
P6.1
P6.2/COUT
MSP430FR592x
P6.3
DVSS2
P6.4/TB0.0
P7.4/SMCLK
P6.5/TB0.1
P7.3/TA0.2
P7.2/TA0.1
P6.6/TB0.2
P7.1/TA0.0/ACLK
P7.0/TA0CLK
P3.0/UCB1CLK/TA3.2
P3.1/UCB1SIMO/UCB1SDA/TA3.3
P3.2/UCB1SOMI/UCB1SCL/TA3.4
TEST/SBWTCK
P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK
P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0
P2.2/UCA0CLK/TB0.4/RTCCLK
P2.3/UCA0STE/TB0OUTH
RST/NMI/SBWTDIO
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1
PJ.1/TDI/TCLK/MCLK/SRSCG0
PJ.2/TMS/ACLK/SROSCOFF
PJ.3/TCK/COUT/SRCPUOFF
P3.3/TA1.1/TB0CLK
P3.7/UCA1STE/TB0.3
P3.6/UCA1CLK/TB0.2
P3.5/UCA1SOMI/UCA1RXD/TB0.1
P3.4/UCA1SIMO/UCA1TXD/TB0.0
A. On devices with UART BSL: P2.0: BSL_TX; P2.1: BSL_RX
On devices with I2C BSL: P1.6: BSL_DAT; P1.7: BSL_CLK
Figure 4-3. 56-Pin DGG Package (Top View) – MSP430FR592x(1)
Copyright © 2015–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
11
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Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
4.2 Pin Attributes
Table 4-1 lists the attributes of each pin.
Table 4-1. Pin Attributes
FR597x(1),
FR592x(1)
FR587x(1)
RESET
STATE
AFTER
BOR(5)
SIGNAL
TYPE(3)
BUFFER
TYPE(4)
POWER
SOURCE
SIGNAL NAME(1) (2)
PM, RGC
PIN NO.
PM, RGC
PIN NO.
DGG
PIN NO.
P4.3 (RD)
UCA0SOMI
UCA0RXD
UCB1STE
P1.4 (RD)
UCB0CLK
UCA0STE
TA1.0
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
–
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
–
OFF
–
1
2
3
1
2
3
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
–
OFF
–
7
8
–
–
P1.5 (RD)
UCB0STE
UCA0CLK
TA0.0
OFF
–
–
–
P1.6 (RD)
UCB0SIMO
UCB0SDA
BSL_DAT
TA0.1
OFF
–
4
5
4
5
9
–
–
I/O
I/O
I/O
I/O
I
–
P1.7 (RD)
UCB0SOMI
UCB0SCL
BSL_CLK
TA0.2
OFF
–
10
–
–
I/O
–
–
6
7
8
6
7
8
11
12
13
DNC(6)
–
P6.0 (RD)
P6.1 (RD)
P6.2 (RD)
COUT
I/O
I/O
I/O
O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
OFF
OFF
OFF
–
9
9
14
15
16
10
11
10
11
P6.3 (RD)
P6.4 (RD)
TB0.0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OFF
OFF
–
P6.5 (RD)
TB0.1
OFF
–
12
13
12
13
17
18
P6.6 (RD)
TB0.2
OFF
–
(1) Signals names with (RD) denote the reset default pin name.
(2) To determine the pin mux encodings for each pin, see the Port I/O Diagrams section.
(3) Signal Types: I = Input, O = Output, I/O = Input or Output.
(4) Buffer Types: LVCMOS, Analog, or Power (see Table 4-3 for details)
(5) Reset States:
OFF = High impedance with Schmitt-trigger inputs and pullup or pulldown (if available) disabled
N/A = Not applicable
(6) DNC = Do not connect
12
Terminal Configuration and Functions
Copyright © 2015–2018, Texas Instruments Incorporated
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Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
Table 4-1. Pin Attributes (continued)
FR597x(1),
FR587x(1)
RESET
STATE
AFTER
BOR(5)
FR592x(1)
PM, RGC
SIGNAL
TYPE(3)
BUFFER
TYPE(4)
POWER
SOURCE
SIGNAL NAME(1) (2)
PM, RGC
PIN NO.
DGG
PIN NO.
PIN NO.
P3.0 (RD)
UCB1CLK
TA3.2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Power
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
–
OFF
14
14
19
20
–
–
P3.1 (RD)
UCB1SIMO
UCB1SDA
TA3.3
OFF
–
15
15
16
–
–
P3.2 (RD)
UCB1SOMI
UCB1SCL
TA3.4
OFF
–
16
21
–
–
17
18
17
18
DVSS1
N/A
N/A
OFF
–
DVCC1
TEST
P
Power
–
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
19
19
22
23
SBWTCK
RST
I
I
OFF
–
20
20
NMI
I
SBWTDIO
PJ.0 (RD)
TDO
I/O
I/O
O
–
OFF
–
21
21
24
TB0OUTH
SMCLK
SRSCG1
PJ.1 (RD)
TDI
I
–
O
–
O
–
I/O
I
OFF
–
22
23
22
23
25
26
TCLK
I
–
MCLK
O
–
SRSCG0
PJ.2 (RD)
TMS
O
–
I/O
I
OFF
–
ACLK
O
–
SROSCOFF
PJ.3 (RD)
TCK
O
–
I/O
I
OFF
–
24
25
26
24
25
26
27
28
29
COUT
O
–
SRCPUOFF
P3.3 (RD)
TA1.1
O
–
I/O
I/O
I
OFF
–
TB0CLK
P3.4 (RD)
UCA1SIMO
UCA1TXD
TB0.0
–
I/O
I/O
O
OFF
–
–
I/O
–
Copyright © 2015–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
13
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Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
Table 4-1. Pin Attributes (continued)
FR597x(1),
FR592x(1)
FR587x(1)
RESET
STATE
AFTER
BOR(5)
SIGNAL
TYPE(3)
BUFFER
TYPE(4)
POWER
SOURCE
SIGNAL NAME(1) (2)
PM, RGC
PIN NO.
PM, RGC
PIN NO.
DGG
PIN NO.
P3.5 (RD)
UCA1SOMI
UCA1RXD
TB0.1
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Power
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
–
OFF
–
27
27
30
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
–
P3.6 (RD)
UCA1CLK
TB0.2
OFF
–
28
29
30
28
29
30
31
32
33
–
P3.7 (RD)
UCA1STE
TB0.3
OFF
–
–
P2.3 (RD)
UCA0STE
TB0OUTH
P2.2 (RD)
UCA0CLK
TB0.4
OFF
–
–
I/O
I/O
I/O
O
OFF
–
31
32
31
32
34
35
–
RTCCLK
P2.1 (RD)
UCA0SOMI
UCA0RXD
BSL_RX
TB0.5
–
I/O
I/O
I
OFF
–
–
I
–
I/O
I
–
DMAE0
–
P2.0 (RD)
UCA0SIMO
UCA0TXD
BSL_TX
TB0.6
I/O
I/O
O
OFF
–
–
33
33
36
O
–
I/O
I
–
TB0CLK
P7.0 (RD)
TA0CLK
P7.1 (RD)
TA0.0
–
I/O
I
OFF
–
34
35
34
35
37
38
I/O
I/O
O
OFF
–
ACLK
–
P7.2 (RD)
TA0.1
I/O
I/O
I/O
I/O
I/O
O
OFF
–
36
37
38
36
37
38
39
40
41
P7.3 (RD)
TA0.2
OFF
–
P7.4 (RD)
SMCLK
OFF
–
39
40
39
40
42
43
DVSS2
P
N/A
N/A
DVCC2
P
Power
–
14
Terminal Configuration and Functions
Copyright © 2015–2018, Texas Instruments Incorporated
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Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
Table 4-1. Pin Attributes (continued)
FR597x(1),
FR587x(1)
RESET
STATE
AFTER
BOR(5)
FR592x(1)
PM, RGC
SIGNAL
TYPE(3)
BUFFER
TYPE(4)
POWER
SOURCE
SIGNAL NAME(1) (2)
PM, RGC
PIN NO.
DGG
PIN NO.
PIN NO.
P1.3 (RD)
TA1.2
A3
I/O
LVCMOS
LVCMOS
Analog
DVCC
DVCC
AVCC
AVCC
DVCC
DVCC
DVCC
DVCC
AVCC
AVCC
DVCC
DVCC
DVCC
DVCC
AVCC
AVCC
AVCC
–
OFF
I/O
–
–
41
42
41
44
45
I
C3
I
I/O
I/O
I
Analog
–
P1.2 (RD)
TA1.1
TA0CLK
COUT
A2
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
–
42
O
I
–
–
C2
I
Analog
–
P1.1 (RD)
TA0.2
TA1CLK
COUT
A1
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
–
O
I
–
43
43
46
–
C1
I
Analog
–
VREF+
VeREF+
P1.0 (RD)
TA0.1
DMAE0
RTCCLK
A0
O
I
Analog
–
Analog
–
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
AVCC
AVCC
AVCC
–
OFF
–
–
O
I
–
44
44
47
–
C0
I
Analog
–
VREF-
VeREF-
P9.4 (RD)
A12
O
I
Analog
–
Analog
–
I/O
I
LVCMOS
Analog
DVCC
AVCC
AVCC
DVCC
AVCC
AVCC
DVCC
AVCC
AVCC
DVCC
AVCC
AVCC
–
OFF
–
45
46
47
48
45
46
47
48
48
49
50
51
C12
I
Analog
–
P9.5 (RD)
A13
I/O
I
LVCMOS
Analog
OFF
–
C13
I
Analog
–
P9.6 (RD)
A14
I/O
I
LVCMOS
Analog
OFF
–
C14
I
Analog
–
P9.7 (RD)
A15
I/O
I
LVCMOS
Analog
OFF
–
C15
I
Analog
–
49
50
49
50
52
53
AVCC1
AVSS1
PJ.4 (RD)
LFXIN
PJ.5 (RD)
LFXOUT
AVSS2
P
P
I/O
I
Power
N/A
N/A
OFF
–
Power
–
LVCMOS
Analog
DVCC
AVCC
DVCC
AVCC
–
51
51
54
I/O
O
P
LVCMOS
Analog
OFF
–
52
53
52
53
55
56
Power
N/A
Copyright © 2015–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
15
Submit Documentation Feedback
Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
Table 4-1. Pin Attributes (continued)
FR597x(1),
FR592x(1)
FR587x(1)
RESET
STATE
AFTER
BOR(5)
SIGNAL
TYPE(3)
BUFFER
TYPE(4)
POWER
SOURCE
SIGNAL NAME(1) (2)
PM, RGC
PIN NO.
PM, RGC
PIN NO.
DGG
PIN NO.
PJ.7 (RD)
HFXOUT
PJ.6 (RD)
HFXIN
I/O
O
LVCMOS
Analog
DVCC
AVCC
DVCC
AVCC
–
OFF
–
54
I/O
I
LVCMOS
Analog
OFF
–
55
56
AVSS3
P
Power
N/A
OFF
–
P5.4 (RD)
UCA1SIMO
UCA1TXD
P5.5 (RD)
UCA1SOMI
UCA1RXD
P5.6 (RD)
UCA1CLK
P5.7 (RD)
UCA1STE
TB0CLK
I/O
I/O
O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Power
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
–
54
–
I/O
I/O
I
OFF
–
55
56
57
–
I/O
I/O
I/O
I/O
I
OFF
–
OFF
–
57
58
59
–
P4.4 (RD)
UCB1STE
TA1CLK
I/O
I/O
I
OFF
–
58
59
1
2
–
P4.5 (RD)
UCB1CLK
TA1.0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
OFF
–
–
P4.6 (RD)
UCB1SIMO
UCB1SDA
TA1.1
OFF
–
60
61
60
61
3
4
–
–
P4.7 (RD)
UCB1SOMI
UCB1SCL
TA1.2
OFF
–
–
–
62
63
62
63
5
6
DVSS3
N/A
N/A
OFF
–
DVCC3
P
Power
–
P4.2 (RD)
UCA0SIMO
UCA0TXD
UCB1CLK
I/O
I/O
O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DVCC
DVCC
DVCC
DVCC
64
64
–
I/O
–
16
Terminal Configuration and Functions
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MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
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ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
4.3 Signal Descriptions
Table 4-2 describes the signals.
Table 4-2. Signal Descriptions
FR597x(1),
FR587x(1)
FR592x(1)
SIGNAL
TYPE
FUNCTION
SIGNAL NAME
PM,
RGC
DESCRIPTION
PM, RGC
DGG
PIN NO.
44
PIN NO. PIN NO.
A0
44
43
42
41
45
46
47
48
43
44
47
46
45
44
48
49
50
51
46
47
I
I
Analog input A0
Analog input A1
Analog input A2
Analog input A3
A1
43
A2
42
I
A3
41
I
A12
A13
A14
A15
VREF+
VREF-
45
I
Analog input A12
46
I
Analog input A13
47
I
Analog input A14
ADC
48
I
Analog input A15
43
O
O
Output of positive reference voltage
Output of negative reference voltage
44
Input for an external positive reference voltage
to the ADC
VeREF+
VeREF-
43
44
43
44
46
47
I
I
Input for an external negative reference
voltage to the ADC
BSL_CLK
BSL_DAT
BSL_RX
BSL_TX
5
4
5
4
10
9
I
I
BSL Clock (I2C BSL)
BSL Data (I2C BSL)
BSL (I2C)
32
33
32
33
35
36
I
BSL Receive (UART BSL)
BSL Transmit (UART BSL)
BSL (UART)
O
23
35
23
35
26
38
ACLK
O
ACLK output
HFXIN
55
54
51
52
22
I
Input terminal of crystal oscillator XT2
Output terminal for crystal oscillator XT2
Input terminal for crystal oscillator XT1
Output terminal of crystal oscillator XT1
MCLK output
HFXOUT
LFXIN
O
I
51
52
22
54
55
25
Clock
LFXOUT
MCLK
O
O
31
44
31
44
34
47
RTCCLK
SMCLK
O
O
RTC clock output for calibration
SMCLK output
21
38
21
38
24
41
C0
44
43
42
41
45
46
47
48
44
43
42
41
45
46
47
48
47
46
45
44
48
49
50
51
I
I
I
I
I
I
I
I
Comparator input C0
Comparator input C1
Comparator input C2
Comparator input C3
Comparator input C12
Comparator input C13
Comparator input C14
Comparator input C15
C1
C2
C3
C12
C13
C14
C15
Comparator
9
9
14
27
45
46
24
42
43
24
42
43
COUT
O
I
Comparator output
32
44
32
44
32
44
DMA
DMAE0
DMA external trigger input
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17
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Table 4-2. Signal Descriptions (continued)
FR597x(1),
FR592x(1)
FR587x(1)
SIGNAL
TYPE
FUNCTION
SIGNAL NAME
PM,
DESCRIPTION
PM, RGC
PIN NO.
6
DGG
RGC
PIN NO. PIN NO.
Do Not Connect (DNC). TI strongly
recommends leaving this pin not connected.
DNC
DNC
6
22
–
SBWTCK
SBWTDIO
19
20
19
20
23
27
I
Spy-Bi-Wire input clock
I/O
Spy-Bi-Wire data input/output
Low-power debug: CPU status register
CPUOFF
SRCPUOFF
SROSCOFF
24
23
24
23
26
25
O
O
Low-power debug: CPU status register
OSCOFF
SRSCG0
SRSCG1
TCK
22
21
24
22
22
21
19
23
22
21
24
22
22
21
19
23
24
27
25
25
24
22
26
23
O
O
I
Low-power debug: CPU status register SCG0
Low-power debug: CPU status register SCG1
Test clock
Debug
TCLK
TDI
I
Test clock input
I
Test data input
TDO
O
I
Test data output port
TEST
TMS
Test mode pin - select digital I/O on JTAG pins
Test mode select
I
18
Terminal Configuration and Functions
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MSP430FR5872, MSP430FR58721, MSP430FR5870
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ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
Table 4-2. Signal Descriptions (continued)
FR597x(1),
FR592x(1)
FR587x(1)
SIGNAL
TYPE
FUNCTION
SIGNAL NAME
PM,
DESCRIPTION
PM, RGC
DGG
RGC
PIN NO.
44
43
42
41
2
PIN NO. PIN NO.
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.4
P5.5
P5.6
P5.7
44
43
42
41
2
47
46
45
44
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
3
3
8
4
4
9
5
5
10
36
35
34
33
19
20
21
28
29
30
31
32
33
32
31
30
14
15
16
25
26
27
28
29
64
1
33
32
31
30
14
15
16
25
26
27
28
29
64
1
GPIO
58
59
60
61
58
59
60
61
54
55
56
57
1
2
3
4
57
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Terminal Configuration and Functions
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
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Table 4-2. Signal Descriptions (continued)
FR597x(1),
FR592x(1)
FR587x(1)
SIGNAL
TYPE
FUNCTION
SIGNAL NAME
PM,
DESCRIPTION
PM, RGC
DGG
RGC
PIN NO.
7
PIN NO. PIN NO.
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P7.0
P7.1
P7.2
P7.3
P7.4
P9.4
P9.5
P9.6
P9.7
PJ.0
7
12
13
14
15
16
17
18
37
38
39
40
41
48
49
50
51
24
25
26
27
54
55
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O
8
8
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
USCI_B0: I2C clock (I2C mode)
USCI_B0: I2C data (I2C mode)
9
9
10
11
12
13
34
35
36
37
38
45
46
47
48
21
22
23
24
51
52
55
54
5
10
11
12
13
34
35
36
37
38
45
46
47
48
21
22
23
24
51
52
55
54
5
GPIO
PJ.1
PJ.2
PJ.3
PJ.4
PJ.5
PJ.6
PJ.7
UCB0SCL
UCB0SDA
10
9
4
4
I2C
16
61
16
61
21
4
UCB1SCL
UCB1SDA
I/O
I/O
USCI_B1: I2C clock (I2C mode)
USCI_B1: I2C data (I2C mode)
15
60
15
60
20
3
AVCC1
AVSS1
AVSS2
AVSS3
DVCC1
DVCC2
DVCC3
DVSS1
DVSS2
DVSS3
49
50
53
56
18
40
63
17
39
62
49
50
53
52
53
56
P
P
P
P
P
P
P
P
P
P
Analog power supply
Analog ground supply
Analog ground supply
Analog ground supply
Digital power supply
Digital power supply
Digital power supply
Digital ground supply
Digital ground supply
Digital ground supply
18
40
63
17
39
62
Power
43
6
42
5
20
Terminal Configuration and Functions
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
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ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
Table 4-2. Signal Descriptions (continued)
FR597x(1),
FR592x(1)
FR587x(1)
SIGNAL
TYPE
FUNCTION
SIGNAL NAME
PM,
DESCRIPTION
PM, RGC
PIN NO.
DGG
RGC
PIN NO. PIN NO.
3
31
3
31
8
34
USCI_A0: Clock signal input (SPI slave mode),
Clock signal output (SPI master mode)
UCA0CLK
UCA0SIMO
UCA0SOMI
UCA0STE
UCA1CLK
UCA1SIMO
UCA1SOMI
UCA1STE
UCB0CLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
33
64
33
64
36
35
USCI_A0: Slave in, master out (SPI mode)
USCI_A0: Slave out, master in (SPI mode)
USCI_A0: Slave transmit enable (SPI mode)
1
32
1
32
2
30
2
30
7
33
28
56
USCI_A1: Clock signal input (SPI slave mode),
Clock signal output (SPI master mode)
28
26
27
31
29
30
32
7
26
54
USCI_A1: Slave in, master out (SPI mode)
USCI_A1: Slave out, master in (SPI mode)
27
55
29
57
29
57
SPI
USCI_A1: Slave transmit enable (SPI mode)
USCI_B0: Clock signal input (SPI slave mode),
Clock signal output (SPI master mode)
2
2
UCB0SIMO
UCB0SOMI
UCB0STE
4
5
3
4
5
3
9
10
8
I/O
I/O
I/O
USCI_B0: Slave in, master out (SPI mode)
USCI_B0: Slave out, master in (SPI mode)
USCI_B0: Slave transmit enable (SPI mode)
14
59
64
14
59
64
19
2
USCI_B1: Clock signal input (SPI slave mode),
Clock signal output (SPI master mode)
UCB1CLK
I/O
15
60
15
60
3
20
UCB1SIMO
UCB1SOMI
UCB1STE
I/O
I/O
I/O
USCI_B1: Slave in, master out (SPI mode)
USCI_B1: Slave out, master in (SPI mode)
USCI_B1: Slave transmit enable (SPI mode)
16
61
16
61
21
4
1
58
1
58
1
NMI
RST
20
20
20
20
23
23
I
I
Nonmaskable interrupt input
Reset input active low
System
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Terminal Configuration and Functions
21
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
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Table 4-2. Signal Descriptions (continued)
FR597x(1),
FR592x(1)
FR587x(1)
SIGNAL
TYPE
FUNCTION
SIGNAL NAME
PM,
DESCRIPTION
PM, RGC
PIN NO.
DGG
RGC
PIN NO. PIN NO.
3
35
3
35
8
38
Timer_A TA0 CCR0 capture: CCI0A input,
compare: Out0 output
TA0.0
TA0.1
I/O
I/O
4
36
44
4
36
44
9
39
47
Timer_A TA0 CCR1 capture: CCI1A input,
compare: Out1 output
5
37
43
5
37
43
10
40
46
Timer_A TA0 CCR2 capture: CCI2A input,
compare: Out2 output
TA0.2
I/O
34
42
34
42
37
45
TA0CLK
TA1.0
I
Timer_A TA0 clock signal TA0CLK input
2
59
2
59
7
2
Timer_A TA1 CCR0 capture: CCI0A input,
compare: Out0 output
I/O
Timer_A
25
42
60
25
42
60
28
45
3
Timer_A TA1 CCR1 capture: CCI1A input,
compare: Out1 output
TA1.1
I/O
41
61
41
61
44
4
Timer_A TA1 CCR2 capture: CCI2A input,
compare: Out2 output
TA1.2
TA1CLK
TA3.2
TA3.3
TA3.4
TB0.0
TB0.1
TB0.2
TB0.3
TB0.4
TB0.5
TB0.6
I/O
I
43
58
43
58
46
1
Timer_A TA1 clock signal TA1CLK input
Timer_A TA3 CCR2 capture: CCI2B input,
compare: Out2 output
14
15
16
14
15
16
19
20
21
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Timer_A TA3 CCR3 capture: CCI3B input,
compare: Out3 output
Timer_A TA3 CCR4 capture: CCI4B input,
compare: Out4 output
11
26
11
26
16
29
Timer_B TB0 CCR0 capture: CCI0B input,
compare: Out0 output
12
27
12
27
17
30
Timer_B TB0 CCR1 capture: CCI1A input,
compare: Out1 output
13
28
13
28
18
31
Timer_B TB0 CCR2 capture: CCI2A input,
compare: Out2 output
Timer_B TB0 CCR3 capture: CCI3B input,
compare: Out3 output
29
31
32
33
29
31
32
33
32
34
35
36
Timer_B TB0 CCR4 capture: CCI4B input,
compare: Out4 output
Timer_B
Timer_B TB0 CCR5 capture: CCI5B input,
compare: Out5 output
Timer_B TB0 CCR6 capture: CCI6B input,
compare: Out6 output
25
33
57
25
33
57
28
36
TB0CLK
I
Timer_B TB0 clock signal TB0CLK input
21
30
21
30
24
33
Switch all PWM outputs high impedance input -
Timer_B TB0
TB0OUTH
UCA0RXD
UCA0TXD
I
I
1
32
1
32
35
36
USCI_A0: Receive data (UART mode)
USCI_A0: Transmit data (UART mode)
33
64
33
64
O
UART
UCA1RXD
UCA1TXD
27
26
27
26
30
29
I
USCI_A1: Receive data (UART mode)
USCI_A1: Transmit data (UART mode)
O
RGC package only. VQFN package exposed
thermal pad. TI recommends connection to
Thermal Pad
VSS
.
22
Terminal Configuration and Functions
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
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ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
4.4 Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and schematics of the
multiplexed ports, see 节 6.11.22.
4.5 Buffer Type
Table 4-3 describes the buffer types that are referenced in Section 4.2.
Table 4-3. Buffer Type
NOMINAL
OUTPUT
DRIVE
STRENGTH
(mA)
BUFFER TYPE
(STANDARD)
NOMINAL
VOLTAGE
PU OR PD
STRENGTH
(µA)
OTHER
CHARACTERISTICS
HYSTERESIS
PU OR PD
See
LVCMOS
Analog
3.0 V
3.0 V
Y(1)
N
Programmable See Table 5-11
Section 5.12.5.1
See analog modules in
Section 5 for details
N/A
N/A
N/A
SVS enables hysteresis on
DVCC
Power (DVCC)
Power (AVCC)
3.0 V
3.0 V
N
N
N/A
N/A
N/A
N/A
N/A
N/A
(1) Only for Input pins.
4.6 Connection of Unused Pins
Table 4-4 lists the correct termination of all unused pins.
Table 4-4. Connection of Unused Pins(1)
PIN
POTENTIAL
DVCC
COMMENT
AVCC
AVSS
DVSS
Px.0 to Px.7
RST/NMI
Open
Switched to port function, output direction (PxDIR.n = 1)
47-kΩ pullup or internal pullup selected with 10-nF (2.2 nF(2)) pulldown
DVCC or VCC
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK
The JTAG pins are shared with general-purpose I/O function (PJ.x). If these pins are not used, they
should be set to port function and output direction. When used as JTAG pins, these pins should
remain open.
Open
Open
TEST
This pin always has an internal pulldown enabled.
(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection
guidelines.
(2) The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG
mode with TI tools like FET interfaces or GANG programmers.
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Terminal Configuration and Functions
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5 Specifications
5.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
4.1
UNIT
V
Voltage applied at DVCC and AVCC pins to VSS
Voltage difference between DVCC and AVCC pins(2)
–0.3
–0.3
–40
±0.3
V
VCC + 0.3
(4.1 Maximum)
(3)
Voltage applied to any pin
V
Diode current at any device pin
±2
mA
°C
(4)
Storage temperature, Tstg
125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device including erroneous
writes to RAM and FRAM.
(3) All voltages referenced to VSS
.
(4) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3 Recommended Operating Conditions
Typical data are based on VCC = 3.0 V, TA = 25°C (unless otherwise noted)
MIN NOM
MAX UNIT
VCC
VSS
TA
Supply voltage applied at all DVCC and AVCC pins(1) (2) (3)
Supply voltage applied at all DVSS and AVSS pins
Operating free-air temperature
1.8(4)
3.6
V
V
0
–40
–40
1–20%
0
85
85
°C
°C
µF
TJ
Operating junction temperature
Capacitor value at DVCC(5)
CDVCC
No FRAM wait states (NWAITSx = 0)
With FRAM wait states (NWAITSx = 1)(8)
8(7)
16(9)
Processor frequency (maximum MCLK
frequency)(6)
fSYSTEM
MHz
0
fACLK
Maximum ACLK frequency
Maximum SMCLK frequency
50 kHz
16(9) MHz
fSMCLK
(1) TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up, power down, and device
operation, the voltage difference between AVCC and DVCC must not exceed the limits specified in Absolute Maximum Ratings.
Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
(2) Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR
resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for
capacitor CDVCC should limit the slopes accordingly.
(3) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(4) The minimum supply voltage is defined by the supervisor SVS levels. See the PMM SVS threshold parameters in 表 5-2 for the exact
values.
(5) As decoupling capacitor for each supply pin pair (DVCC and DVSS, AVCC and AVSS), a low-ESR ceramic capacitor of 100 nF
(minimum) should be placed as close as possible (within a few millimeters) to the respective pin pairs.
(6) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(7) DCO settings and HF cyrstals with a typical value less than or equal to the specified MAX value are permitted.
(8) Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always excecuted
without wait states.
(9) DCO settings and HF cyrstals with a typical value less than or equal to the specified MAX value are permitted. If a clock source with a
higher typical value is used, the clock must be divided in the clock system.
24
Specifications
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5.4 Active Mode Supply Current Into VCC Excluding External Current
(2)
over recommended operating free-air temperature (unless otherwise noted)(1)
FREQUENCY (fMCLK = fSMCLK
)
1 MHz
0 WAIT
STATES
4 MHz
0 WAIT
STATES
8 MHz
0 WAIT
STATES
12 MHz
1 WAIT
STATES
16 MHz
1 WAIT
STATES
EXECUTION
MEMORY
PARAMETER
VCC
UNIT
(NWAITSx = 0)
(NWAITSx = 0)
(NWAITSx = 0)
(NWAITSx = 1)
(NWAITSx = 1)
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
IAM, FRAM_UNI
FRAM
3.0 V
3.0 V
210
640
1220
1475
1845
µA
µA
(Unified memory)(3)
FRAM
0% cache hit
ratio
IAM, FRAM(0%)(4)
370
240
200
170
110
1280
745
560
480
235
2510
1440
1070
890
2080
1575
1300
1155
640
2650
1990
1620
1420
730
(5)
FRAM
50% cache hit
ratio
IAM, FRAM(50%)(4)
3.0 V
3.0 V
3.0 V
3.0 V
µA
µA
µA
µA
(5)
FRAM
66% cache hit
ratio
IAM, FRAM(66%)(4)
(5)
FRAM
75% cache hit
ratio
IAM, FRAM(75%)(4)
255
180
1085
1310
1620
1300
(5)
FRAM
100% cache hit
ratio
IAM, FRAM(100%(4)
420
(5)
(6) (5)
IAM, RAM
RAM
RAM
3.0 V
3.0 V
130
100
320
290
585
555
890
860
1070
1040
µA
µA
(7) (5)
IAM, RAM only
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Characterized with program executing typical data processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO= 24 MHz and
fMCLK = fSMCLK = fDCO/2.
At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency
(fMCLK,eff) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by the number of wait
states or the cache hit ratio.
The following equation can be used to compute fMCLK,eff
:
fMCLK,eff = fMCLK / [wait states × (1 - cache hit ratio) + 1]
For example, with 1 wait state and 75% cache hit ratio fMCKL,eff = fMCLK / [1 × (1 - 0.75) + 1] = fMCLK / 1.25.
(3) Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM.
(4) Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit
ratio represents number cache accesess divided by the total number of FRAM accesses. For example, a 75% ratio implies three of
every four accesses is from cache, and the remaining are FRAM accesses.
(5) See Figure 5-1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best
linear fit using the typical data shown in Section 5.4.
(6) Program and data reside entirely in RAM. All execution is from RAM.
(7) Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
Copyright © 2015–2018, Texas Instruments Incorporated
Specifications
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5.5 Typical Characteristics - Active Mode Supply Currents
3000
I(AM,0%)
I(AM,50%)
2500
I(AM,66%)
I(AM,75%)
2000
1500
1000
500
0
I(AM,100%)
I(AM,75%)[uA] = 103*f[MHz] + 68
I(AM,RAMonly)
0
1
2
3
4
5
6
7
8
9
MCLK Frequency [MHz]
C001
NOTE: I(AM, cache hit ratio): Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with
cache hit-to-miss ratio as specified. Cache hit ratio represents number cache accesses divided by the total number of
FRAM accesses. For example, a 75% ratio implies three of every four accesses is from cache, and the remaining are
FRAM accesses.
NOTE: I(AM, RAMonly): Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
Figure 5-1. Typical Active Mode Supply Currents, No Wait States
5.6 Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
(2)
over recommended operating free-air temperature (unless otherwise noted)(1)
FREQUENCY (fSMCLK
8 MHz
)
PARAMETER
VCC
1 MHz
TYP
4 MHz
TYP
12 MHz
TYP
16 MHz
TYP
UNIT
MAX
120
65
MAX
TYP
165
175
130
130
MAX
MAX
MAX
275
2.2 V
3.0 V
2.2 V
3.0 V
75
80
40
40
105
115
65
250
260
215
215
230
240
195
195
ILPM0
µA
µA
ILPM1
65
220
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Current for watchdog timer clocked by SMCLK included.
fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO at specified frequency - except for 12 MHz: here fDCO=24MHz and fSMCLK = fDCO/2.
26
Specifications
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5.7 Low-Power Mode LPM2, LPM3, LPM4 Supply Currents (Into VCC) Excluding External
Current
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
–40°C
25°C
60°C
85°C
PARAMETER
VCC
UNIT
μA
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
0.8
0.8
0.7
0.7
0.5
0.5
0.7
0.7
0.6
1.2
1.2
1.1
1.1
0.9
0.9
0.9
0.9
0.7
3.1
3.1
3.0
3.0
2.8
2.8
1.2
1.2
1.1
8.8
8.8
8.7
8.7
8.5
8.5
2.5
2.5
2.4
Low-power mode 2, 12-pF
ILPM2,XT12
ILPM2,XT3.7
ILPM2,VLO
ILPM3,XT12
(3) (4)
crystal(2)
2.2
17
Low-power mode 2, 3.7-pF
μA
(5) (4)
crystal(2)
Low-power mode 2, VLO,
includes SVS(6)
μA
2.0
1.2
16.7
6.4
Low-power mode 3, 12-pF
μA
crystal, includes SVS(2)
(3) (7)
Low-power mode 3, 3.7-pF
(5) (8)
ILPM3,XT3.7
crystal, excludes SVS(2)
(also see Figure 5-2)
μA
μA
μA
3.0 V
0.6
0.7
1.1
2.4
2.2 V
3.0 V
2.2 V
0.35
0.35
0.35
0.4
0.4
0.4
0.9
0.9
0.8
1.8
1.8
1.7
Low-power mode 3,
ILPM3,VLO
VLO, excludes SVS(9)
0.8
0.7
6.1
5.2
Low-power mode 3,
ILPM3,VLO,
VLO, excludes SVS, RAM
powered down completely(10)
RAMoff
3.0 V
0.35
0.4
0.8
1.7
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Not applicable for devices with HF crystal oscillator only.
(3) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5 pF load.
(4) Low-power mode 2, crystal oscillator test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are
chosen to closely match the required 3.7-pF load.
(6) Low-power mode 2, VLO test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout and SVS included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
(7) Low-power mode 3, 12-pF crystal, includes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
(8) Low-power mode 3, 3.7-pF crystal, excludes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE =
0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
(9) Low-power mode 3, VLO, excludes SVS test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout included. SVS disabled
(SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
(10) Low-power mode 3, VLO, excludes SVS, RAM powered down completely test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout included. SVS disabled
(SVSHE = 0). RAM disabled (RCCTL0 = 5A55h).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
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Specifications
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Low-Power Mode LPM2, LPM3, LPM4 Supply Currents (Into VCC) Excluding External
Current (continued)
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
–40°C
25°C
60°C
85°C
PARAMETER
VCC
UNIT
MAX
TYP
MAX
TYP
MAX
0.8
TYP
MAX
TYP
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
0.45
0.45
0.25
0.25
0.25
0.55
0.55
0.4
0.9
0.9
0.7
0.7
0.7
1.8
1.8
1.6
1.6
1.4
Low-power mode 4, includes
SVS(11)
ILPM4,SVS
μA
6.2
Low-power mode 4, excludes
SVS(12)
ILPM4
μA
0.4
0.65
4.6
Low-power mode 4, excludes
SVS, RAM powered down
completely(13)
0.4
ILPM4,RAMoff
μA
3.0 V
0.25
0.4
0.65
0.7
1.4
4.6
Additional idle current if one or
more modules from Group A
(see 节 6.3.2) are activated in
LPM3 or LPM4
IIDLE,GroupA
3.0 V
0.02
0.4
1.0
1.0
0.8
μA
μA
μA
Additional idle current if one or
more modules from Group B
(see 节 6.3.2) are activated in
LPM3 or LPM4
IIDLE,GroupB
3.0 V
3.0 V
0.02
0.02
0.4
0.3
Additional idle current if one or
more modules from Group C
(see 节 6.3.2) are activated in
LPM3 or LPM4
IIDLE,GroupC
(11) Low-power mode 4, includes SVS test conditions:
Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
(12) Low-power mode 4, excludes SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
(13) Low-power mode 4, excludes SVS, RAM powered down completely test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). RAM disabled (RCCTL0 = 5A55h).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
28
Specifications
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5.8 Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
–40°C
25°C
60°C
85°C
PARAMETER
VCC
UNIT
μA
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
0.45
0.45
0.3
0.5
0.5
0.6
0.6
0.75
0.75
0.65
0.65
0.4
Low-power mode 3.5, 12-pF
ILPM3.5,XT12
ILPM3.5,XT3.7
ILPM4.5,SVS
ILPM4.5
crystal including SVS(2)
(3) (4)
0.75
1.4
0.35
0.35
0.3
0.4
Low-power mode 3.5, 3.7-pF
μA
crystal excluding SVS(2)
(5) (6)
0.3
0.4
0.2
0.35
0.35
0.06
0.06
Low-power mode 4.5, including
SVS(7)
μA
0.2
0.3
0.5
0.4
0.7
0.5
0.03
0.03
0.04
0.04
0.14
0.14
Low-power mode 4.5,
excluding SVS(8)
μA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Not applicable for devices with HF crystal oscillator only.
(3) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5 pF load.
(4) Low-power mode 3.5, 1-pF crystal including SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are
chosen to closely match the required 3.7-pF load.
(6) Low-power mode 3.5, 3.7-pF crystal excluding SVS test conditions:
Current for RTC clocked by XT1 included.Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(7) Low-power mode 4.5 including SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
(8) Low-power mode 4.5 excluding SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
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Specifications
29
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5.9 Typical Characteristics, Low-Power Mode Supply Currents
3
2.5
2
3
2.5
2
@ 3.0V, SVS off
@ 2.2V, SVS off
@ 3.0V, SVS on
@ 2.2V, SVS on
@ 3.0V, SVS off
@ 2.2V, SVS off
@ 3.0V, SVS on
@ 2.2V, SVS on
1.5
1
1.5
1
0.5
0
0.5
0
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Temperature [°C]
Temperature [°C]
C003
C001
Figure 5-2. LPM3 Supply Current vs Temperature (LPM3,XT3.7)
Figure 5-3. LPM4 Supply Current vs Temperature (LPM4,SVS)
7.00E-01
0.7
@ 3.0V, SVS off
@ 3.0V, SVS off
@ 2.2V, SVS off
6.00E-01
@ 2.2V, SVS off
@ 3.0V, SVS on
0.6
@ 2.2V, SVS on
5.00E-01
0.5
0.4
0.3
0.2
4.00E-01
3.00E-01
2.00E-01
1.00E-01
0.00E+00
-50
-25
0
25
50
75
100
-50.00
-25.00
0.00
25.00
50.00
75.00
100.00
Temperature [°C]
Temperature [°C]
C004
C003
Figure 5-5. LPM4.5 Supply Current vs Temperature (LPM4.5)
Figure 5-4. LPM3.5 Supply Current vs Temperature
(LPM3.5,XT3.7)
30
Specifications
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5.10 Typical Characteristics, Current Consumption per Module
MODULE
Timer_A
TEST CONDITIONS
REFERENCE CLOCK
Module input clock
MIN
TYP
3
MAX
UNIT
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
nA
Timer_B
eUSCI_A
eUSCI_A
eUSCI_B
eUSCI_B
RTC_C
MPY
Module input clock
Module input clock
Module input clock
Module input clock
Module input clock
32 kHz
5
UART mode
5.5
3.5
3.5
3.5
100
25
SPI mode
SPI mode
I2C mode, 100 kbaud
Only from start to end of operation
Only from start to end of operation
Only from start to end of operation
Only from start to end of operation
MCLK
μA/MHz
μA/MHz
μA/MHz
μA/MHz
AES
MCLK
21
CRC16
CRC32
MCLK
2.5
2.5
MCLK
5.11 Thermal Resistance Characteristics(1)
PARAMETER
PACKAGE
VALUE(1)
57.7
15.1
26.5
26.2
0.5
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJA
Junction-to-ambient thermal resistance, still air(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
θJC(TOP)
θJB
TSSOP-56 (DGG)
ΨJB
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
Junction-to-case (bottom) thermal resistance(5)
Junction-to-ambient thermal resistance, still air(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
ΨJT
θJC(BOTTOM)
θJA
θJC(TOP)
θJB
N/A
59.3
19.5
30.8
30.5
1.0
QFP-64 (PN)
ΨJB
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
Junction-to-case (bottom) thermal resistance(5)
Junction-to-ambient thermal resistance, still air(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
ΨJT
θJC(BOTTOM)
θJA
θJC(TOP)
θJB
N/A
29.6
15.8
8.5
QFN-64 (RGC)
ΨJB
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
Junction-to-case (bottom) thermal resistance(5)
8.5
ΨJT
0.2
θJC(BOTTOM)
1.2
(1) N/A = not applicable
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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Specifications
31
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5.12 Timing and Switching Characteristics
5.12.1 Power Supply Sequencing
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up,
power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the
limits specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the
device including erroneous writes to RAM and FRAM.
表 5-1 lists the reset power ramp requirements.
表 5-1. Brownout and Device Reset Power Ramp Requirements
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Brownout power-down level(1)
Brownout power-up level(1)
TEST CONDITIONS
| dDVCC/dt | < 3 V/s(2)
| dDVCC/dt | < 3 V/s(2)
MIN
0.73
0.79
MAX UNIT
VVCC_BOR–
VVCC_BOR+
1.66
1.68
V
V
(1) Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR
resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for
capacitor CDVCC should limit the slopes accordingly.
(2) The brownout levels are measured with a slowly changing supply.
表 5-2 lists the characteristics of the SVS.
表 5-2. SVS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
170
MAX UNIT
ISVSH,LPM
VSVSH-
SVSH current consumption, low power modes
SVSH power-down level(1)
SVSH power-up level(1)
300
1.85
1.99
120
10
nA
V
1.75
1.77
40
1.80
1.88
VSVSH+
V
VSVSH_hys
tPD,SVSH, AM
SVSH hysteresis
mV
µs
SVSH propagation delay, active mode
dVVcc/dt = –10 mV/µs
(1) For additional information, see the Dynamic Voltage Scaling Power Solution for MSP430 Devices With Single-Channel LDO Reference
Design.
5.12.2 Reset Timing
Table 5-11 lists the required reset input timing.
表 5-3. Reset Input
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
MAX
UNIT
t(RST) External reset pulse duration on RST(1)
2.2 V, 3.0 V
2
µs
(1) Not applicable if the RST/NMI pin is configured as NMI.
32
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5.12.3 Clock Specifications
Table 5-4 lists the characteristics of the LFXT.
Table 5-4. Low-Frequency Crystal Oscillator, LFXT(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
180
TA = 25°C, CL,eff = 3.7 pF, ESR ≈ 44 kΩ
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {1},
TA = 25°C, CL,eff = 6 pF, ESR ≈ 40 kΩ
185
225
IVCC.LFXT
Current consumption
3.0 V
nA
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {2},
TA = 25°C, CL,eff = 9 pF, ESR ≈ 40 kΩ
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF, ESR ≈
40 kΩ
330
LFXT oscillator crystal
frequency
fLFXT
LFXTBYPASS = 0
32768
Hz
Measured at ACLK,
fLFXT = 32768 Hz
DCLFXT
fLFXT,SW
DCLFXT, SW
LFXT oscillator duty cycle
30%
70%
LFXT oscillator logic-level
square-wave input frequency
LFXTBYPASS = 1(2) (3)
10.5 32.768
50 kHz
70%
LFXT oscillator logic-level
square-wave input duty cycle
LFXTBYPASS = 1
30%
210
300
2
LFXTBYPASS = 0, LFXTDRIVE = {1},
fLFXT = 32768 Hz, CL,eff = 6 pF
Oscillation allowance for
LF crystals(4)
OALFXT
kΩ
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32768 Hz, CL,eff = 12.5 pF
Integrated load capacitance at
LFXIN terminal(5) (6)
CLFXIN
pF
pF
Integrated load capacitance at
LFXOUT terminal(5) (6)
CLFXOUT
2
(1) To improve EMI on the LFXT oscillator, the following guidelines should be observed.
•
•
•
•
•
•
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins LFXIN and LFXOUT.
Avoid running PCB traces underneath or adjacent to the LFXIN and LFXOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator LFXIN and LFXOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW
.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
•
•
•
•
For LFXTDRIVE = {0}, CL,eff = 3.7 pF
For LFXTDRIVE = {1}, CL,eff = 6 pF
For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 9 pF
For LFXTDRIVE = {3}, 9 pF ≤ CL,eff ≤ 12.5 pF
(5) This represents all the parasitic capacitance present at the LFXIN and LFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN x COUT / (CIN + COUT), where CIN and COUT is the
total capacitance at the LFXIN and LFXOUT terminals, respectively.
(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Recommended values supported are 3.7
pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds additional capacitance, so it must also be
considered in the overall capacitance. Verify that the recommended effective load capacitance of the selected crystal is met.
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Specifications
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Table 5-4. Low-Frequency Crystal Oscillator, LFXT(1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
TA = 25°C, CL,eff = 3.7 pF
3.0 V
800
tSTART,LFXT
Start-up time(7)
ms
fOSC = 32768 Hz
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF
3.0 V
1000
fFault,LFXT
Oscillator fault frequency(8) (9)
0
3500
Hz
(7) Includes start-up counter of 1024 clock cycles.
(8) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specification may set the
flag. A static condition or stuck at fault condition will set the flag.
(9) Measured with logic-level input frequency but also applies to operation with crystals.
Table 5-5 lists the characteristics of the HFXT.
Table 5-5. High-Frequency Crystal Oscillator, HFXT(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0,
HFFREQ = 1(2)
TA = 25°C,
,
75
CL,eff = 18 pF, typical ESR, Cshunt
fOSC = 8 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 1
TA = 25°C,
120
190
250
CL,eff = 18 pF, typical ESR, Cshunt
HFXT oscillator crystal current HF
mode at typical ESR
IDVCC.HFXT
3.0 V
μA
fOSC = 16 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 2,
HFFREQ = 2,
TA = 25°C,
CL,eff = 18 pF, typical ESR, Cshunt
fOSC = 24 MHz
HFXTBYPASS = 0, HFXTDRIVE = 3,
HFFREQ = 3,
TA = 25°C,
CL,eff = 18 pF, typical ESR, Cshunt
(2)
HFXTBYPASS = 0, HFFREQ = 1
4
8
(3)
HFXT oscillator crystal frequency,
crystal mode
fHFXT
MHz
16
(3)
HFXTBYPASS = 0, HFFREQ = 2
8.01
(3)
HFXTBYPASS = 0, HFFREQ = 3
16.01
24
Measured at SMCLK,
fHFXT = 16 MHz
DCHFXT
HFXT oscillator duty cycle
40%
50%
60%
(1) To improve EMI on the HFXT oscillator the following guidelines should be observed.
•
•
•
•
•
•
Keep the traces between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins HFXIN and HFXOUT.
Avoid running PCB traces underneath or adjacent to the HFXIN and HFXOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator HFXIN and HFXOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(2) HFFREQ = {0} is not supported for HFXT crystal mode of operation.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
34
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Table 5-5. High-Frequency Crystal Oscillator, HFXT(1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
HFXTBYPASS = 1, HFFREQ = 0(4)
0.9
4
(3)
HFXTBYPASS = 1, HFFREQ = 1(4)
4.01
8.01
8
(3)
HFXT oscillator logic-level
square-wave input frequency,
bypass mode
fHFXT,SW
MHz
16
HFXTBYPASS = 1, HFFREQ = 2(4)
(3)
HFXTBYPASS = 1, HFFREQ = 3(4)
16.01
40%
24
(3)
DCHFXT,
HFXT oscillator logic-level
HFXTBYPASS = 1
HFXTBYPASS = 0,
60%
square-wave input duty cycle
SW
HFXTDRIVE = 0, HFFREQ = 1(2)
fHFXT,HF = 4 MHz, CL,eff = 16 pF
,
450
320
200
200
HFXTBYPASS = 0,
HFXTDRIVE = 1, HFFREQ = 1,
fHFXT,HF = 8 MHz, CL,eff = 16 pF
Oscillation allowance for
HFXT crystals(5)
OAHFXT
Ω
HFXTBYPASS = 0,
HFXTDRIVE = 2, HFFREQ = 2,
fHFXT,HF = 16 MHz, CL,eff = 16 pF
HFXTBYPASS = 0,
HFXTDRIVE = 3, HFFREQ = 3,
fHFXT,HF = 24 MHz, CL,eff = 16 pF
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0,
HFFREQ = 1,
TA = 25°C, CL,eff = 16 pF
3.0 V
3.0 V
1.6
0.6
tSTART,HFXT Start-up time(6)
ms
pF
fOSC = 24 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 3,
HFFREQ = 3,
TA = 25°C, CL,eff = 16 pF
Integrated load capacitance at
CHFXIN
2
2
HFXIN terminaI(7) (8)
Integrated load capacitance at
HFXOUT terminaI(7) (8)
Oscillator fault frequency(9) (10)
CHFXOUT
fFault,HFXT
pF
0
800 kHz
(4) When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCHFXT, SW
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(6) Includes start-up counter of 1024 clock cycles.
.
(7) This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN x COUT / (CIN + COUT), where CIN and COUT is the
total capacitance at the HFXIN and HFXOUT terminals, respectively.
(8) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Recommended values supported are
14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF. The PCB adds additional capacitance, so it must also be considered in
the overall capacitance. Verify that the recommended effective load capacitance of the selected crystal is met.
(9) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX might set the flag. A static
condition or stuck at fault condition will set the flag.
(10) Measured with logic-level input frequency but also applies to operation with crystals.
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Specifications
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Table 5-6 lists the characteristics of the DCO.
Table 5-6. DCO
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 0
DCORSEL = 1, DCOFSEL = 0
DCO frequency range 1 MHz,
trimmed
fDCO1
1
±3.5% MHz
DCO frequency range 2.7 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 1
fDCO2.7
fDCO3.5
fDCO4
2.667
3.5
4
±3.5% MHz
±3.5% MHz
±3.5% MHz
DCO frequency range 3.5 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 2
DCO frequency range 4 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 3
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 4
DCORSEL = 1, DCOFSEL = 1
DCO frequency range 5.3 MHz,
trimmed
fDCO5.3
fDCO7
fDCO8
5.333
±3.5% MHz
±3.5% MHz
±3.5% MHz
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 5
DCORSEL = 1, DCOFSEL = 2
DCO frequency range 7 MHz,
trimmed
7
8
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 6
DCORSEL = 1, DCOFSEL = 3
DCO frequency range 8 MHz,
trimmed
DCO frequency range 16 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 1, DCOFSEL = 4
fDCO16
fDCO21
fDCO24
16
21
24
±3.5%(1) MHz
±3.5%(1) MHz
±3.5%(1) MHz
DCO frequency range 21 MHz,
trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 5
DCO frequency range 24 MHz,
trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 6
Measured at SMCLK, divide by 1,
No external divide, all DCORSEL and
DCOFSEL settings except DCORSEL
= 1, DCOFSEL = 5 and DCORSEL =
1, DCOFSEL = 6
fDCO,DC
Duty cycle
48%
50%
52%
Based on fsignal = 10 kHz and DCO
used for 12-bit SAR ADC sampling
source. This achieves >74-dB SNR
due to jitter; that is, it is limited by
ADC performance.
tDCO,
JITTER
DCO jitter
2
3
ns
dfDCO/dT
DCO temperature drift(2)
3.0 V
0.01
%/ºC
(1) After a wakeup from LPM1, LPM2, LPM3 or LPM4, the DCO frequency fDCO might exceed the specified frequency range for a few
clocks cycles by up to 5% before settling into the specified steady state frequency range.
(2) Calculated using the box method: (MAX(–40°C to 85ºC) – MIN(–40°C to 85ºC)) / MIN(–40°C to 85ºC) / (85ºC – (–40ºC))
Table 5-7 lists the characteristics of the VLO.
Table 5-7. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
100
9.4
MAX UNIT
nA
IVLO
Current consumption
VLO frequency
fVLO
Measured at ACLK
6
14 kHz
%/°C
dfVLO/dT
dfVLO/dVCC
fVLO,DC
VLO frequency temperature drift
VLO frequency supply voltage drift
Duty cycle
Measured at ACLK(1)
Measured at ACLK(2)
Measured at ACLK
0.2
0.7
%/V
40%
50%
60%
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
36
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Table 5-8 lists the characteristics of the MODOSC.
Table 5-8. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
25
MAX UNIT
IMODOSC
Current consumption
Enabled
μA
fMODOSC
MODOSC frequency
4.0
4.8
5.4
MHz
fMODOSC/dT
MODOSC frequency temperature drift(1)
0.08
%/℃
MODOSC frequency supply voltage
drift(2)
fMODOSC/dVCC
DCMODOSC
1.4
%/V
Duty cycle
Measured at SMCLK, divide by 1
40%
50%
60%
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
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5.12.4 Wake-up Characteristics
Table 5-9 lists the device wake-up times.
Table 5-9. Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX UNIT
Additional wake-up time to activate the FRAM
in AM if previously disabled by the FRAM
controller or from an LPM if immediate
activation is selected
tWAKE-UP FRAM
6
10
μs
MCLKREQEN = 1
400 ns +
1.5 / fDCO
2.2 V, 3.0 V
2.2 V, 3.0 V
(1)
tWAKE-UP LPM0
Wake-up time from LPM0 to active mode
MCLKREQEN = 0
400 ns +
2.5 / fDCO
(1)(2)
tWAKE-UP LPM1
tWAKE-UP LPM2
tWAKE-UP LPM3
tWAKE-UP LPM4
Wake-up time from LPM1 to active mode(1)
Wake-up time from LPM2 to active mode(1)
Wake-up time from LPM3 to active mode(1)
Wake-up time from LPM4 to active mode(1)
2.2 V, 3.0 V
2.2 V, 3.0 V
2.2 V, 3.0 V
2.2 V, 3.0 V
2.2 V, 3.0 V
2.2 V, 3.0 V
2.2 V, 3.0 V
6
6
μs
μs
μs
μs
μs
μs
ms
7
10
10
7
tWAKE-UP LPM3.5 Wake-up time from LPM3.5 to active mode(3)
250
250
0.4
350
350
0.8
SVSHE = 1
SVSHE = 0
tWAKE-UP LPM4.5 Wake-up time from LPM4.5 to active mode(3)
Wake-up time from a RST pin triggered reset to
tWAKE-UP-RST
2.2 V, 3.0 V
2.2 V, 3.0 V
250
0.5
350
1.0
μs
active mode(3)
(3)
tWAKE-UP-BOR
Wake-up time from power-up to active mode
ms
(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first
externally observable MCLK clock edge with MCLKREQEN = 1. This time includes the activation of the FRAM during wakeup.
(2) With MCLKREQEN = 0, the MCLK is gated one additoinal one clock cycle (wake from LPM0, LPM1, LPM2, LPM3, and LPM4). The
device wake-up time is not affected by the status of the MCLKREQEN bit.
(3) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
Table 5-10 lists the typical charge required for wakeup.
Table 5-10. Typical Wake-up Charge(1)
PARAMETER
TEST CONDITIONS MIN
TYP
MAX UNIT
Charge used for activating the FRAM in AM or during wakeup
from LPM0 if previously disabled by the FRAM controller.
QWAKE-UP FRAM
QWAKE-UP LPM0
QWAKE-UP LPM1
QWAKE-UP LPM2
QWAKE-UP LPM3
QWAKE-UP LPM4
15.1
nAs
Charge used to wake up from LPM0 to active mode (with FRAM
active)
4.4
nAs
nAs
nAs
nAs
Charge used to wake up from LPM1 to active mode (with FRAM
active)
15.1
15.3
16.5
16.5
Charge used to wake up from LPM2 to active mode (with FRAM
active)
Charge used to wake up from LPM3 to active mode (with FRAM
active)
Charge used to wake up from LPM4 to active mode (with FRAM
active)
nAs
nAs
QWAKE-UP LPM3.5 Charge used to wake up from LPM3.5 to active mode(2)
QWAKE-UP LPM4.5 Charge used to wake up from LPM4.5 to active mode(2)
QWAKE-UP-RESET Charge used for reset from RST or BOR event to active mode(2)
76
77
SVSHE = 1
SVSHE = 0
nAs
nAs
77.5
75
(1) Charge used during the wake-up time from a given low-power mode to active mode. This does not include the energy required in active
mode (for example, for an interrupt service routine).
(2) Charge required until start of user code. This does not include the energy required to reconfigure the device.
38
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5.12.4.1 Typical Characteristics, Average LPM Currents vs Wake-up Frequency
10000.00
LPM0
LPM1
LPM2,XT12
1000.00
LPM3,XT12
LPM3.5,XT12
100.00
10.00
1.00
0.10
0.001
0.01
0.1
1
10
100
1000
10000
100000
Wake-up Frequency (Hz)
NOTE: The average wake-up current does not include the energy required in active mode; for example, for an interrupt
service routine or to reconfigure the device.
Figure 5-6. Average LPM Currents vs Wake-up Frequency at 25°C
10000.00
LPM0
LPM1
LPM2,XT12
1000.00
LPM3,XT12
LPM3.5,XT12
100.00
10.00
1.00
0.10
0.001
0.01
0.1
1
10
100
1000
10000
100000
Wake-up Frequency (Hz)
NOTE: The average wake-up current does not include the energy required in active mode; for example, for an interrupt
service routine or to reconfigure the device.
Figure 5-7. Average LPM Currents vs Wake-up Frequency at 85°C
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5.12.5 Digital I/Os
Table 5-11 lists the characteristics of the digital inputs.
Table 5-11. Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
1.2
TYP
MAX UNIT
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
1.65
V
VIT+
VIT–
Vhys
Positive-going input threshold voltage
1.65
0.55
0.75
0.44
0.60
2.25
1.00
V
Negative-going input threshold voltage
1.35
0.98
V
Input voltage hysteresis (VIT+ – VIT–
Pullup or pulldown resistor
)
1.30
For pullup: VIN = VSS
For pulldown: VIN = VCC
RPull
CI,dig
CI,ana
20
35
3
50
kΩ
pF
pF
Input capacitance, digital only port pins
VIN = VSS or VCC
Input capacitance, port pins with shared analog
functions(1)
VIN = VSS or VCC
5
2.2 V,
3.0 V
(2)(3)
Ilkg(Px.y)
High-impedance input leakage current
See
–20
20
2
+20
nA
ns
µs
Ports with interrupt capability
External interrupt timing (external trigger pulse (see block diagram and
2.2 V,
3.0 V
t(int)
duration to set interrupt flag)(4)
terminal function
descriptions).
2.2 V,
3.0 V
t(RST)
External reset pulse duration on RST(5)
(1) If the port pins PJ.4/LFXIN and PJ.5/LFXOUT are used as digital I/Os, they are connected by a 4-pF capacitor and a 35-MΩ resistor in
series. At frequencies of approximately 1 kHz and lower, the 4-pF capacitor can add to the pin capacitance of PJ.4/LFXIN and
PJ.5/LFXOUT.
(2) The input leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
(3) The input leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
(4) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int)
.
(5) Not applicable if the RST/NMI pin is configured as NMI.
40
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Table 5-12 lists the characteristics of the digital outputs.
Table 5-12. Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA(1)
VCC
MIN
TYP
MAX UNIT
VCC
–
VCC
0.25
2.2 V
VCC
–
I(OHmax) = –3 mA(2)
I(OHmax) = –2 mA(1)
I(OHmax) = –6 mA(2)
I(OLmax) = 1 mA(1)
I(OLmax) = 3 mA(2)
I(OLmax) = 2 mA(1)
I(OLmax) = 6 mA(2)
VCC
0.60
VOH
High-level output voltage
V
VCC
–
VCC
0.25
3.0 V
2.2 V
3.0 V
VCC
–
VCC
0.60
VSS
+
VSS
VSS
VSS
VSS
0.25
VSS
+
0.60
VOL
Low-level output voltage
V
VSS
+
0.25
VSS
+
0.60
2.2 V
3.0 V
2.2 V
16
16
16
Port output frequency (with load)(3)
Clock output frequency(3)
CL = 20 pF, RL
MHz
MHz
(4) (5)
fPx.y
ACLK, MCLK, or SMCLK at
configured output port
CL = 20 pF(5)
fPort_CLK
3.0 V
16
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
4
3
4
3
6
4
6
4
15
15
15
15
15
15
15
15
trise,dig
Port output rise time, digital only port pins
Port output fall time, digital only port pins
CL = 20 pF
CL = 20 pF
CL = 20 pF
CL = 20 pF
ns
ns
ns
ns
tfall,dig
Port output rise time, port pins with shared
analog functions
trise,ana
Port output fall time, port pins with shared
analog functions
tfall,ana
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
(3) The port can output frequencies at least up to the specified limit. It might support higher frequencies.
(4) A resistive divider with 2 × R1 and R1 = 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the
divider. CL = 20 pF is connected from the output to VSS
.
(5) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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5.12.5.1 Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
15
10
5
30
20
10
0
25°C
85°C
25°C
85°C
P1.1
P1.1
0
0
0.5
1
1.5
2
0
0.5
1
1.5
2
2.5
3
Low-Level Output Voltage (V)
Low-Level Output Voltage (V)
C001
C001
VCC = 2.2 V
VCC = 3.0 V
Figure 5-8. Typical Low-Level Output Current vs Low-Level
Output Voltage
Figure 5-9. Typical Low-Level Output Current vs Low-Level
Output Voltage
0
0
25°C
25°C
85°C
85°C
-5
-10
-10
-20
P1.1
P1.1
-15
-30
0
0.5
1
1.5
2
0
0.5
1
1.5
2
2.5
3
High-Level Output Voltage (V)
High-Level Output Voltage (V)
C001
C001
VCC = 2.2 V
VCC = 3.0 V
Figure 5-10. Typical High-Level Output Current vs High-Level
Output Voltage
Figure 5-11. Typical High-Level Output Current vs High-Level
Output Voltage
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Table 5-13 lists the characteristics of the pin oscillator.
Table 5-13. Pin-Oscillator Frequency, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Px.y, CL = 10 pF(1)
Px.y, CL = 20 pF(1)
VCC
MIN
TYP
1200
650
MAX UNIT
kHz
3.0 V
3.0 V
foPx.y
Pin-oscillator frequency
kHz
(1) CL is the external load capacitance connected from the output to VSS and includes all parasitic effects such as PCB traces.
5.12.5.2 Typical Characteristics, Pin-Oscillator Frequency
fitted
25°C
fitted
25°C
85°C
1000
85°C
1000
100
100
10
100
10
100
External Load Capacitance (incl. board etc.) [pF]
External Load Capacitance (incl. board etc.) [pF]
C002
C002
VCC = 2.2 V
One output active at a time.
VCC = 3.0 V
One output active at a time.
Figure 5-12. Typical Oscillation Frequency vs Load Capacitance Figure 5-13. Typical Oscillation Frequency vs Load Capacitance
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5.12.6 Timer_A and Timer_B
Table 5-14 lists the characteristics of the Timer_A.
Table 5-14. Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK or ACLK,
External: TACLK,
Duty cycle = 50% ±10%
2.2 V,
3.0 V
fTA
Timer_A input clock frequency
16 MHz
All capture inputs, minimum pulse
duration required for capture
2.2 V,
3.0 V
tTA,cap
Timer_A capture timing
20
ns
Table 5-15 lists the characteristics of the Timer_B.
Table 5-15. Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK or ACLK,
External: TBCLK,
Duty cycle = 50% ±10%
2.2 V,
3.0 V
fTB
Timer_B input clock frequency
16 MHz
All capture inputs, minimum pulse
duration required for capture
2.2 V,
3.0 V
tTB,cap
Timer_B capture timing
20
ns
5.12.7 eUSCI
Table 5-16 lists the supported clock frequencies for the eUSCI in UART mode.
Table 5-16. eUSCI (UART Mode) Clock Frequency
PARAMETER
CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK, ACLK
feUSCI
eUSCI input clock frequency
External: UCLK
16 MHz
Duty cycle = 50% ±10%
BITCLK clock frequency
(equals baud rate in MBaud)
fBITCLK
4
MHz
Table 5-17 lists the characteristics of the eUSCI in UART mode.
Table 5-17. eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UCGLITx = 0
VCC
MIN
5
TYP
MAX UNIT
30
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
20
35
50
90
ns
2.2 V,
3.0 V
tt
UART receive deglitch time(1)
160
220
(1) Pulses on the UART receive input (UCxRX) that are shorter than the UART receive deglitch time are suppressed. Thus the selected
deglitch time can limit the maximum usable baud rate. To make sure that pulses are correctly recognized, their duration should exceed
the maximum specification of the deglitch time.
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Table 5-18 lists the supported clock frequencies for the eUSCI in SPI master mode.
Table 5-18. eUSCI (SPI Master Mode) Clock Frequency
PARAMETER
CONDITIONS
Internal: SMCLK, ACLK
Duty cycle = 50% ±10%
VCC
MIN
MAX UNIT
feUSCI
eUSCI input clock frequency
16 MHz
Table 5-19 lists the characteristics of the eUSCI in SPI master mode.
Table 5-19. eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
STE lead time, STE active to clock
UCSTEM = 1, UCMODEx = 01 or 10
1
UCxCLK
cycles
STE lag time, last clock to STE
inactive
UCSTEM = 1, UCMODEx = 01 or 10
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 0, UCMODEx = 01 or 10
1
STE access time, STE active to
SIMO data out
2.2 V,
3.0 V
60
80
ns
ns
STE disable time, STE inactive to
SOMI high impedance
2.2 V,
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
40
40
0
tSU,MI
SOMI input data setup time
SOMI input data hold time
SIMO output data valid time(2)
SIMO output data hold time(3)
ns
ns
ns
ns
tHD,MI
0
10
10
UCLK edge to SIMO valid,
CL = 20 pF
tVALID,MO
0
0
tHD,MO
CL = 20 pF
(1) fUCxCLK = 1 / 2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-14 and Figure 5-15.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-
14 and Figure 5-15.
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UCMODEx = 01
tSTE,LEAD
tSTE,LAG
STE
UCMODEx = 10
CKPL = 0
1/fUCxCLK
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
SIMO
tHD,MO
tVALID,MO
tSTE,ACC
tSTE,DIS
Figure 5-14. SPI Master Mode, CKPH = 0
UCMODEx = 01
STE
tSTE,LEAD
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
SIMO
tHD,MO
tVALID,MO
tSTE,DIS
tSTE,ACC
Figure 5-15. SPI Master Mode, CKPH = 1
46
Specifications
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Table 5-20 lists the characteristics of the eUSCI in SPI slave mode.
Table 5-20. eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
50
40
2
TYP
MAX UNIT
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
tSU,SI
STE lead time, STE active to clock
ns
STE lag time, last clock to STE inactive
ns
3
50
ns
40
STE access time, STE active to SOMI data out
50
ns
45
STE disable time, STE inactive to SOMI high
impedance
4
4
7
7
SIMO input data setup time
SIMO input data hold time
SOMI output data valid time(2)
SOMI output data hold time(3)
ns
ns
tHD,SI
35
ns
35
UCLK edge to SOMI valid,
CL = 20 pF
tVALID,SO
0
0
tHD,SO
CL = 20 pF
ns
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)).
For the master parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-16 and Figure 5-17.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-16
and Figure 5-17.
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UCMODEx = 01
tSTE,LEAD
tSTE,LAG
STE
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tSU,SI
tLOW/HIGH
tLOW/HIGH
tHD,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 5-16. SPI Slave Mode, CKPH = 0
UCMODEx = 01
UCMODEx = 10
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 5-17. SPI Slave Mode, CKPH = 1
48
Specifications
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Table 5-21 lists the characteristics of the eUSCI in I2C mode.
Table 5-21. eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
External: UCLK
feUSCI
eUSCI input clock frequency
16 MHz
Duty cycle = 50% ±10%
fSCL
SCL clock frequency
2.2 V, 3.0 V
2.2 V, 3.0 V
0
4.0
0.6
4.7
0.6
0
400 kHz
µs
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
2.2 V, 3.0 V
µs
tHD,DAT
tSU,DAT
Data hold time
Data setup time
2.2 V, 3.0 V
2.2 V, 3.0 V
ns
ns
100
4.0
0.6
4.7
1.3
50
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
UCGLITx = 0
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
UCCLTOx = 1
UCCLTOx = 2
UCCLTOx = 3
tSU,STO
Setup time for STOP
2.2 V, 3.0 V
µs
Bus free time between a STOP and
START condition
tBUF
us
250
25
125
ns
Pulse duration of spikes suppressed by
input filter
tSP
2.2 V, 3.0 V
12.5
6.3
62.5
31.5
27
30
33
tTIMEOUT
Clock low time-out
2.2 V, 3.0 V
ms
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-18. I2C Mode Timing
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49
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5.12.8 ADC12
Table 5-22 lists the power supply and input range conditions for the ADC.
Table 5-22. 12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN NOM
MAX UNIT
V(Ax)
Analog input voltage(1)
All ADC12 analog input pins Ax
0
AVCC
199
V
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 0
REFON = 0, ADC12SHTx = 0,
ADC12DIV = 0
3.0 V
2.2 V
3.0 V
2.2 V
145
I(ADC12_B)
single-
ended mode
Operating supply current into
µA
AVCC plus DVCC terminal(2) (3)
140
175
170
190
245
230
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 1
REFON = 0, ADC12SHTx = 0,
ADC12DIV = 0
I(ADC12_B)
differential
mode
Operating supply current into
µA
AVCC and DVCC terminals(2) (3)
Only one terminal Ax can be selected
at one time
CI
RI
Input capacitance
2.2 V
10
15
pF
>2 V
<2 V
0.5
1
4
Input MUX ON resistance
0 V ≤ V(Ax) ≤ AVCC
kΩ
10
(1) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
(2) The internal reference supply current is not included in current consumption parameter I(ADC12_B).
(3) Typically about 60% of the total current into the AVCC and DVCC terminal is from AVCC.
Table 5-23 lists the timing parameter for the ADC.
Table 5-23. 12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
For specified performance of ADC12 linearity parameters
with ADC12PWRMD = 0,
If ADC12PWRMD = 1, the maximum is 1/4 of the value
shown here
fADC12CLK
Specified performance
0.45
5.4
MHz
fADC12CLK
fADC12OSC
Reduced performance Linearity parameters have reduced performance
32.768
4.8
kHz
Internal oscillator(1)
ADC12DIV = 0, fADC12CLK = fADC12OSC from MODCLK
4
5.4
3.5
MHz
REFON = 0, Internal oscillator,
fADC12CLK = fADC12OSC from MODCLK,
ADC12WINC = 0
2.6
tCONVERT
Conversion time
µs
External fADC12CLK from ACLK, MCLK, or SMCLK,
(2)
ADC12SSEL ≠ 0
Turnon settling time of
the ADC
(3)
tADC12ON
See
100
ns
ns
Time ADC must be off
before can be turned
on again
tADC12OFF
tADC12OFF must be met to make sure tADC12ON time holds
100
(1) The ADC12OSC is sourced directly from MODOSC inside the UCS.
(2) 14 × 1 / fADC12CLK. If ADC12WINC = 1, then 15 × 1 / fADC12CLK
(3) The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signals are already
settled.
50
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Table 5-23. 12-Bit ADC, Timing Parameters (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
All pulse sample mode
(ADC12SHP = 1) and
extended sample mode
(ADC12SHP = 0) with
buffered reference (ADC12
VRSEL = 0x1, 0x3, 0x5, 0x7,
0x9, 0xB, 0xD, 0xF)
1
µs
RS = 400 Ω, RI = 4 kΩ,
tSample
Sampling time
CI = 15 pF, Cpext= 8 pF(4)
Extended sample mode
(ADC12SHP = 0) with
unbuffered reference
(ADC12 VRSEL= 0x0, 0x2,
0x4, 0x6, 0xC, 0xE)
(5)
µs
(4) Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB: tsample = ln(2n+2) × (RS + RI) × (CI + Cpext), RS < 10 kΩ,
where n = ADC resolution = 12, RS= external source resistance, Cpext = external parasitic capacitance.
(5) 6 × (1 / fADC12CLK
)
Table 5-24 lists the linearity parameters of the ADC when using an external reference.
Table 5-24. 12-Bit ADC, Linearity Parameters With External Reference(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Number of no missing code
output-code bits
Resolution
12
bits
Integral linearity error (INL)
for differential input
EI
1.2 V ≤ VR+ – VR–≤ AVCC
±1.8
±2.2
+1.0
±1.5
LSB
LSB
LSB
mV
Integral linearity error (INL)
for single ended inputs
EI
1.2 V ≤ VR+ – VR–≤ AVCC
Differential linearity error
(DNL)
ED
EO
–0.99
ADC12 VRSEL = 0x2 or 0x4 without TLV calibration,
Offset error(2) (3)
±0.5
±0.8
TLV calibration data can be used to improve the parameter(4)
With external voltage reference without internal buffer
(ADC12 VRSEL = 0x2 or 0x4) without TLV calibration,
TLV calibration data can be used to improve the parameter(4)
VR+ = 2.5 V, VR– = AVSS
±2.5
±20
,
EG,ext
Gain error
LSB
LSB
With external voltage reference with internal buffer (ADC12
VRSEL = 0x3),
VR+ = 2.5 V, VR– = AVSS
±1
With external voltage reference without internal buffer
(ADC12 VRSEL = 0x2 or 0x4) without TLV calibration,
TLV calibration data can be used to improve the parameter(4)
VR+ = 2.5 V, VR– = AVSS
±1.4
±3.5
,
ET,ext
Total unadjusted error
With external voltage reference with internal buffer (ADC12
VRSEL = 0x3),
±1.4 ±21.0
VR+ = 2.5 V, VR– = AVSS
(1) See Table 5-26 and Table 5-32 for more information on internal reference performance and see Designing With the MSP430FR58xx,
FR59xx, FR68xx, and FR69xx ADC for details on optimizing ADC performance for your application with the choice of internal versus
external reference.
(2) Offset is measured as the input voltage (at which ADC output transitions from 0 to 1) minus 0.5 LSB.
(3) Offset increases as IR drop increases when VR– is AVSS.
(4) For details, see the device descriptor table section in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.
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Table 5-25 lists the differential dynamic performance characteristics of the ADC with an external
reference.
Table 5-25. 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VR+ = 2.5 V, VR– = AVSS
VR+ = 2.5 V, VR– = AVSS
MIN
68
TYP
71
MAX
UNIT
dB
SNR
Signal-to-noise ratio
Effective number of bits(2)
ENOB
10.7
11.2
bits
(1) See Table 5-26 and Table 5-32 for more information on internal reference performance and see Designing With the MSP430FR58xx,
FR59xx, FR68xx, and FR69xx ADC for details on optimizing ADC performance for your application with the choice of internal versus
external reference.
(2) ENOB = (SINAD – 1.76) / 6.02
Table 5-26 lists the differential dynamic performance characteristics of the ADC with an internal reference.
Table 5-26. 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Effective number of bits(2)
TEST CONDITIONS
VR+ = 2.5V, VR– = AVSS
MIN
TYP
MAX
UNIT
ENOB
10.3
10.7
Bits
(1) See Table 5-32 for more information on internal reference performance and see Designing With the MSP430FR58xx, FR59xx, FR68xx,
and FR69xx ADC for details on optimizing ADC performance for your application with the choice of internal versus external reference.
(2) ENOB = (SINAD – 1.76) / 6.02
Table 5-27 lists the single-ended dynamic performance characteristics of the ADC with an external
reference.
Table 5-27. 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VR+ = 2.5 V, VR– = AVSS
VR+ = 2.5 V, VR– = AVSS
MIN
64
TYP
68
MAX
UNIT
dB
SNR
Signal-to-noise ratio
Effective number of bits(2)
ENOB
10.2
10.7
bits
(1) See Table 5-28 and Table 5-32 for more information on internal reference performance and see Designing With the MSP430FR58xx,
FR59xx, FR68xx, and FR69xx ADC for details on optimizing ADC performance for your application with the choice of internal versus
external reference.
(2) ENOB = (SINAD – 1.76) / 6.02
Table 5-28 lists the single-ended dynamic performance characteristics of the ADC with an internal
reference.
Table 5-28. 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Effective number of bits(2)
TEST CONDITIONS
VR+ = 2.5 V, VR– = AVSS
MIN
TYP
MAX
UNIT
ENOB
9.4
10.4
bits
(1) See Table 5-32 for more information on internal reference performance and see Designing With the MSP430FR58xx, FR59xx, FR68xx,
and FR69xx ADC for details on optimizing ADC performance for your application with the choice of internal versus external reference.
(2) ENOB = (SINAD – 1.76) / 6.02
Table 5-29 lists the dynamic performance characteristics of the ADC with using a 32.768-kHz clock.
Table 5-29. 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Reduced performance with fADC12CLK from ACLK LFXT
at 32.768 kHz, VR+ = 2.5 V, VR– = AVSS
ENOB
Effective number of bits(1)
10
bits
(1) ENOB = (SINAD – 1.76) / 6.02
52
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Table 5-30 lists the temperature sensor and built-in V1/2 characteristics.
Table 5-30. 12-Bit ADC, Temperature Sensor and Built-In V1/2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
700
2.5
MAX UNIT
mV
ADC12ON = 1, ADC12TCMAP = 1,
TA = 0°C (see Figure 5-19)
(1) (2)
VSENSOR
See
(2)
TCSENSOR
See
ADC12ON = 1, ADC12TCMAP = 1
mV/°C
Sample time required if
tSENSOR(sample) ADCTCMAP = 1 and channel
(MAX – 1) is selected(3)
ADC12ON = 1, ADC12TCMAP = 1,
Error of conversion result ≤ 1 LSB
30
µs
AVCC voltage divider for
V1/2
ADC12BATMAP = 1 on MAX input
channel
ADC12ON = 1, ADC12BATMAP = 1
ADC12ON = 1, ADC12BATMAP = 1
ADC12ON = 1, ADC12BATMAP = 1
47.5%
50% 52.5%
current for battery monitor during
sample time
IV 1/2
38
72
µA
µs
Sample time required if
ADC12BATMAP = 1 and channel
MAX is selected(4)
tV 1/2 (sample)
1.7
(1) The temperature sensor offset can be as much as ±30°C. TI recommends a single-point calibration to minimize the offset error of the
built-in temperature sensor.
(2) The device descriptor structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference voltage
levels. The sensor voltage can be computed as VSENSE = TCSENSOR * (Temperature, °C) + VSENSOR, where TCSENSOR and VSENSOR can
be computed from the calibration values for higher accuracy.
(3) The typical equivalent impedance of the sensor is 250 kΩ. The sample time required includes the sensor on-time tSENSOR(on)
.
(4) The on-time tV 1/2(on) is included in the sampling time tV 1/2 (sample); no additional on time is needed.
950
900
850
800
750
700
650
600
550
500
–40
–20
0
20
40
60
80
Ambient Temperature (°C)
Figure 5-19. Typical Temperature Sensor Voltage
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Table 5-31 lists the external reference characteristics of the ADC.
Table 5-31. 12-Bit ADC, External Reference(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
Positive external reference voltage input
VeREF+ or VeREF- based on ADC12 VRSEL bit
VR+
VR+ > VR–
1.2
AVCC
V
Negative external reference voltage input
VeREF+ or VeREF- based on ADC12 VRSEL bit
VR–
VR+ > VR–
VR+ > VR–
0
1.2
V
V
(VR+ – VR–
)
Differential external reference voltage input
Static input current singled ended input mode
1.2
AVCC
1.2 V ≤ VeREF+≤ VAVCC, VeREF– = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 1h,
ADC12DIF = 0, ADC12PWRMD = 0
±10
±2.5
±20
±5
IVeREF+
IVeREF-
µA
uA
1.2 V ≤ VeREF+≤ VAVCC , VeREF– = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 8h,
ADC12DIF = 0, ADC12PWRMD = 01
1.2 V ≤ VeREF+≤ VAVCC, VeREF– = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 1h,
ADC12DIF = 1, ADC12PWRMD = 0
IVeREF+
IVeREF-
Static input current differential input mode
1.2 V ≤ VeREF+≤ VAVCC , VeREF– = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 8h,
ADC12DIF = 1, ADC12PWRMD = 1
IVeREF+
IVeREF+
CVeREF+/-
Peak input current with single ended input
Peak input current with differential input
Capacitance at VeREF+ or VeREF- terminal
0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 0
0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 1
1.5
3
mA
mA
µF
(2)
See
10
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2) Two decoupling capacitors, 10 µF and 470 nF, should be connected to VeREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_B. See also the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's
Guide.
54
Specifications
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MSP430FR5872, MSP430FR58721, MSP430FR5870
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5.12.9 REF Module
Table 5-32 lists the characteristics of the built-in voltage reference.
Table 5-32. REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
2.5 ±1.5%
2.0 ±1.5%
1.2 ±1.8%
MAX UNIT
REFVSEL = {2} for 2.5 V, REFON = 1
REFVSEL = {1} for 2.0 V, REFON = 1
REFVSEL = {0} for 1.2 V, REFON = 1
From 0.1 Hz to 10 Hz, REFVSEL = {0}
2.7 V
2.2 V
1.8 V
Positive built-in reference
voltage output
VREF+
V
Noise
RMS noise at VREF(1)
110
600
µV
VREF ADC BUF_INT buffer TA = 25°C , ADC ON, REFVSEL = {0},
VOS_BUF_INT
–12
–12
+12
mV
offset(2)
REFON = 1, REFOUT = 0
VREF ADC BUF_EXT
buffer offset(2)
TA = 25°C, REFVSEL = {0} , REFOUT = 1,
REFON = 1 or ADC ON
VOS_BUF_EXT
AVCC(min)
IREF+
+12
mV
V
REFVSEL = {0} for 1.2 V
REFVSEL = {1} for 2.0 V
REFVSEL = {2} for 2.5 V
1.8
2.2
2.7
AVCC minimum voltage,
Positive built-in reference
active
Operating supply current
into AVCC terminal(3)
REFON = 1
3 V
8
225
15
355
µA
ADC ON, REFOUT = 0, REFVSEL = {0, 1, 2},
ADC12PWRMD = 0,
ADC ON, REFOUT = 1, REFVSEL = {0, 1, 2},
ADC12PWRMD = 0
1030
120
1660
185
Operating supply current
into AVCC terminal(3)
ADC ON, REFOUT = 0, REFVSEL = {0, 1, 2},
ADC12PWRMD = 1
IREF+_ADC_BUF
3 V
µA
µA
ADC ON, REFOUT = 1, REFVSEL = {0, 1, 2},
ADC12PWRMD = 1
545
895
ADC OFF, REFON = 1, REFOUT = 1,
REFVSEL = {0, 1, 2}
1085
1780
REFVSEL = {0, 1, 2}, AVCC = AVCC(min) for
each reference level,
REFON = REFOUT = 1
VREF maximum load
current, VREF+ terminal
IO(VREF+)
–1000
+10
REFVSEL = {0, 1, 2},
ΔVout/ΔIo
(VREF+)
Load-current regulation,
VREF+ terminal
IO(VREF+) = +10 µA or –1000 µA,
AVCC = AVCC(min) for each reference level,
REFON = REFOUT = 1
2500 µV/mA
Capacitance at VREF+ and
VREF- terminals
CVREF+/-
TCREF+
REFON = REFOUT = 1
0
100
pF
Temperature coefficient of
built-in reference
REFVSEL = {0, 1, 2}, REFON = REFOUT = 1,
TA = –40°C to 85°C(4)
18
120
3.0
75
50 ppm/K
400 µV/V
mV/V
Power supply rejection ratio AVCC = AVCC(min) to AVCC(max), TA = 25°C,
(DC)
PSRR_DC
PSRR_AC
tSETTLE
REFVSEL = {0, 1, 2}, REFON = REFOUT = 1
Power supply rejection ratio
(AC)
dAVCC= 0.1 V at 1 kHz
Settling time of reference
voltage(5)
AVCC = AVCC (min) to AVCC(max)
REFVSEL = {0, 1, 2}, REFON = 0 → 1
,
80
µs
(1) Internal reference noise affects ADC performance when ADC uses internal reference. See Designing With the MSP430FR59xx and
MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal versus external
reference.
(2) Buffer offset affects ADC gain error and thus total unadjusted error.
(3) The internal reference current is supplied through the AVCC terminal.
(4) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
(5) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
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5.12.10 Comparator
Table 5-33 lists the characteristics of the comparator.
Table 5-33. Comparator_E
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
CEPWRMD = 00, CEON = 1,
CERSx = 00 (fast)
11
20
CEPWRMD = 01, CEON = 1,
CERSx = 00 (medium)
9
17
µA
0.5
Comparator operating supply
current into AVCC, excludes
reference resistor ladder
2.2 V,
3.0 V
IAVCC_COMP
CEPWRMD = 10, CEON = 1,
CERSx = 00 (slow), TA = 30°C
CEPWRMD = 10, CEON = 1,
CERSx = 00 (slow), TA = 85°C
1.3
CEREFLx = 01, CERSx = 10, REFON = 0,
CEON = 0, CEREFACC = 0
12
5
15
µA
7
Quiescent current of resistor
ladder into AVCC, including
REF module current
2.2 V,
3.0 V
IAVCC_REF
CEREFLx = 01, CERSx = 10, REFON = 0,
CEON = 0, CEREFACC = 1
CERSx = 11, CEREFLx = 01, CEREFACC = 0
CERSx = 11, CEREFLx = 10, CEREFACC = 0
CERSx = 11, CEREFLx = 11, CEREFACC = 0
CERSx = 11, CEREFLx = 01, CEREFACC = 1
CERSx = 11, CEREFLx = 10, CEREFACC = 1
CERSx = 11, CEREFLx = 11, CEREFACC = 1
1.8 V
2.2 V
2.7 V
1.8 V
2.2 V
2.7 V
1.17
1.92
2.40
1.10
1.90
2.35
0
1.2
2.0
2.5
1.2
2.0
2.5
1.23
2.08
2.60
V
1.245
VREF
Reference voltage level
2.08
2.60
VIC
Common-mode input range
Input offset voltage
VCC – 1
32
V
CEPWRMD = 00
–32
–32
–30
VOFFSET
CEPWRMD = 01
32
mV
CEPWRMD = 10
30
CEPWRMD = 00 or CEPWRMD = 01
CEPWRMD = 10
9
9
1
CIN
Input capacitance
pF
On (switch closed)
3
kΩ
RSIN
Series input resistance
Off (switch open)
50
MΩ
CEPWRMD = 00, CEF = 0, Overdrive ≥ 20 mV
CEPWRMD = 01, CEF = 0, Overdrive ≥ 20 mV
CEPWRMD = 10, CEF = 0, Overdrive ≥ 20 mV
260
350
330
460
15
ns
Propagation delay, response
time
tPD
µs
ns
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 00
700
1.0
2.0
4.0
0.9
0.9
15
1000
1.8
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 01
Propagation delay with filter
active
tPD,filter
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 10
3.5
µs
µs
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 11
7.0
CEON = 0 → 1, VIN+, VIN- from pins,
Overdrive ≥ 20 mV, CEPWRMD = 00
1.5
CEON = 0 → 1, VIN+, VIN- from pins,
Overdrive ≥ 20 mV, CEPWRMD = 01
tEN_CMP
Comparator enable time
Comparator and reference
1.5
CEON = 0 → 1, VIN+, VIN- from pins,
Overdrive ≥ 20 mV, CEPWRMD = 10
100
CEON = 0 → 1, CEREFLX = 10, CERSx = 10 or 11,
tEN_CMP_VREF
ladder and reference voltage CEREF0 = CEREF1 = 0x0F,
350
1500
µs
V
enable time
Overdrive ≥ 20 mV
VIN ×
VIN ×
(n + 0.5) (n + 1)
/ 32 / 32
VIN ×
(n + 1.5)
/ 32
Reference voltage for a
given tap
VIN = reference into resistor ladder,
n = 0 to 31
VCE_REF
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5.12.11 FRAM Controller
Table 5-34 lists the characteristics of the FRAM.
Table 5-34. FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
Read and write endurance
MIN
TYP
MAX UNIT
1015
100
40
cycles
TJ = 25°C
TJ = 70°C
TJ = 85°C
tRetention
Data retention duration
years
10
(1)
IWRITE
IERASE
tWRITE
Current to write into FRAM
Erase current
IREAD
nA
nA
ns
N/A(2)
(3)
Write time
tREAD
(4)
(4)
Read time, NWAITSx = 0
Read time, NWAITSx = 1
1 / fSYSTEM
2 / fSYSTEM
tREAD
ns
(1) Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read
current IREAD is included in the active mode current consumption numbers IAM,FRAM
(2) N/A = not applicable. FRAM does not require a special erase sequence.
(3) Writing into FRAM is as fast as reading.
.
(4) The maximum read (and write) speed is specified by fSYSTEM using the appropriate wait state settings (NWAITSx).
5.12.12 Emulation and Debug
Table 5-35 lists the characteristics of the JTAG and Spy-Bi-Wire interface.
Table 5-35. JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
PARAMETER
MIN
TYP
MAX UNIT
CONDITIONS
2.2 V, 3.0 V
2.2 V, 3.0 V
2.2 V, 3.0 V
IJTAG
Supply current adder when JTAG active (but not clocked)
Spy-Bi-Wire input frequency
40
100
μA
fSBW
0
10 MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
0.04
15
110
100
μs
μs
μs
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge)(1)
tSBW, En
tSBW,Rst
2.2 V, 3.0 V
Spy-Bi-Wire return to normal operation time
TCK input frequency, 4-wire JTAG(2)
15
0
2.2 V
3.0 V
16 MHz
16 MHz
fTCK
0
Rinternal
Internal pulldown resistance on TEST
2.2 V, 3.0 V
20
35
50
kΩ
TCLK/MCLK frequency during JTAG access, no FRAM access
fTCLK
16 MHz
(limited by fSYSTEM
)
tTCLK,Low/High
fTCLK,FRAM
TCLK low or high clock pulse duration, no FRAM access
25
4
ns
MHz
ns
TCLK/MCLK frequency during JTAG access, including FRAM access
(limited by fSYSTEM with no FRAM wait states)
tTCLK,FRAM,Low/High TCLK low or high clock pulse duration, including FRAM accesses
100
(1) Tools that access the Spy-Bi-Wire and BSL interfaces must wait for the tSBW,En time after the first transition of the TEST/SBWTCK pin
(low to high), before the second transition of the pin (high to low) during the entry sequence.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
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6 Detailed Description
6.1 Overview
The Texas Instruments MSP430FR597x(1) and MSP430FR587x(1) family of ultra-low-power
microcontrollers consists of several devices featuring different sets of peripherals. The architecture,
combined with seven low-power modes is optimized to achieve extended battery life for example in
portable measurement applications. The devices features a powerful 16-bit RISC CPU, 16-bit registers,
and constant generators that contribute to maximum code efficiency. The devices are microcontroller
configurations with up to five 16-bit timers, a comparator, eUSCIs that support UART, SPI, and I2C, a
hardware multiplier, an AES accelerator, DMA, an RTC module with alarm capabilities, up to 52 I/O pins,
and a high-performance 12-bit ADC.
6.2 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data. CPUxV2 can also operate on address-word data (20-bit).
58
Detailed Description
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6.3 Operating Modes
The device has one active mode and seven software selectable low-power modes of operation (see 表 6-1). An interrupt event can wake up the
device from low-power modes LPM0 to LPM4, service the request, and restore back to the low-power mode on return from the interrupt program.
Low-power modes LPM3.5 and LPM4.5 disable the core supply to minimize power consumption.
表 6-1. Operating Modes
MODE
AM
LPM0
LPM1
CPU Off
16 MHz
LPM2
LPM3
LPM4
LPM3.5
LPM4.5
Active,
Shutdown
Without
SVS
Shutdown
With SVS
(2)
Active
103
FRAM Off
CPU Off
Standby
Standby
Off
RTC Only
(1)
(3)
(3)
Maximum system clock
16 MHz
16 MHz
50 kHz
0.9 µA
6 µs
50 kHz
0.4 µA
7 µs
0
50 kHz
0.35 µA
250 µs
0
Typical current consumption,
25°C
75 µA at
1 MHz
40 µA at
1 MHz
65 µA/MHz
N/A
0.3 µA
7 µs
0.2 µA
250 µs
0.02 µA
1000 µs
µA/MHz
Typical wake-up time
instant.
6 µs
LF
RTC
I/O
LF
RTC
I/O
_
I/O
Comp
RTC
I/O
_
I/O
Wake-up events
N/A
all
all
Comp
Comp
CPU
on
off
off
off
off
off
off
off
reset
off
reset
off
standby (or off
FRAM
on
off(1)
off
off
(1)
)
High-frequency peripherals
Low-frequency peripherals
Unclocked peripherals(5)
MCLK
available
available
available
on
available
available
available
off
available
available
available
off
off
available
available
off
off
available
available
off
off
off
reset
RTC
reset
off
reset
reset
reset
off
(4)
(4)
(4)
available
off
(6)
(6)
(6)
SMCLK
opt.
opt.
opt.
off
off
off
off
off
ACLK
on
on
on
on
on
off
off
off
(7)
(7)
Full retention
SVS
yes
yes
yes
yes
optional(8)
yes
yes
no
no
(9)
(10)
always
always
always
always
always
always
optional(8)
optional(8)
optional(8)
on
off
Brownout
always
always
always
always
always
(1) FRAM disabled in FRAM controller
(2) Disabling the FRAM through the FRAM controller decreases the LPM current consumption, but the wake-up time can increase. If the wakeup is for FRAM access (for example, to fetch an
interrupt vector), wake-up time is increased. If the wakeup is for an operation that does not access FRAM (for example, DMA transfer to RAM), wake-up time is not increased.
(3) All clocks disabled
(4) See 节 6.3.2, which describes the use of peripherals in LPM3 and LPM4.
(5) "Unclocked peripherals" are peripherals that do not require a clock source to operate; for example, the comparator and REF, or the eUSCI when operated as an SPI slave.
(6) Controlled by SMCLKOFF
(7) Using the RAM Controller, the RAM can be completely powered down to save leakage; however, all data is lost.
(8) Activated SVS (SVSHE = 1) results in higher current consumption. SVS not included in typical current consumption.
(9) SVSHE = 1
(10) SVSHE = 0
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6.3.1 Peripherals in Low-Power Modes
Peripherals can be in different states that affect which power mode the device can enter. The states
depend on the operational modes of the peripherals (see 表 6-2). The states are:
•
•
•
A peripheral is in a "high-frequency state" if it requires or uses a clock with a "high" frequency of more
than 50 kHz.
A peripheral is in a "low-frequency state" if it requires or uses a clock with a "low" frequency of 50 kHz
or less.
A peripheral is in an "unclocked state" if it does not require or use an internal clock.
If the CPU requests a power mode that does not support the current state of all active peripherals, the
device does not enter the requested power mode. The device instead enters a power mode that still
supports the current state of the peripherals, except if an external clock is used. If an external clock is
used, the application must use the correct frequency range for the requested power mode.
表 6-2. Peripheral States
PERIPHERAL
WDT
DMA(4)
IN HIGH-FREQUENCY STATE(1)
Clocked by SMCLK
Not applicable
IN LOW-FREQUENCY STATE(2)
Clocked by ACLK
IN UNCLOCKED STATE(3)
Not applicable
Not applicable
Waiting for a trigger
Not applicable
RTC_C
Not applicable
Clocked by LFXT
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Timer_A TAx
Timer_B TBx
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
Waiting for first edge of START bit.
Not applicable
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
eUSCI_Ax in
UART mode
Clocked by SMCLK
Clocked by SMCLK
Clocked by ACLK
Clocked by ACLK
eUSCI_Ax in SPI
master mode
eUSCI_Ax in SPI
slave mode
eUSCI_Bx in I2C
master mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
Not applicable
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
eUSCI_Bx in I2C
slave mode
Waiting for START condition or
clocked by external clock ≤50 kHz
Clocked by external clock >50 kHz
Clocked by SMCLK
Clocked by external clock ≤50 kHz
Clocked by ACLK
eUSCI_Bx in SPI
master mode
Not applicable
eUSCI_Bx in SPI
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
ADC12_B
REF_A
COMP_E
CRC(5)
MPY(5)
AES(5)
Clocked by SMCLK or by MODOSC
Not applicable
Clocked by ACLK
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Waiting for a trigger
Always
Not applicable
Always
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
(1) Peripherals are in a state that requires or uses a clock with a "high" frequency of more than 50 kHz.
(2) Peripherals are in a state that requires or uses a clock with a "low" frequency of 50 kHz or less.
(3) Peripherals are in a state that does not require or does not use an internal clock.
(4) The DMA always transfers data in active mode but can wait for a trigger in any low-power mode. A DMA trigger during a low-power
mode causes a temporary transition into active mode for the time of the transfer.
(5) This peripheral operates during active mode only and delays the transition into a low-power mode until its operation is completed.
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6.3.2 Idle Currents of Peripherals in LPM3 and LPM4
Most peripherals can be activated to be operational in LPM3 if clocked by ACLK. Some modules are even
operational in LPM4 because they do not require a clock to operate (for example, the comparator).
Activating a peripheral in LPM3 or LPM4 increases the current consumption due to its active supply
current contribution but also due to an additional idle current. To limit the idle current adder, certain
peripherals are group together. To achieve optimal current consumption, try to use modules within one
group and to limit the number of groups with active modules. 表 6-3 lists the grouping. Modules not listed
in this table are either already included in the standard LPM3 current consumption specifications or cannot
be used in LPM3 or LPM4.
The idle current adder is very small at room temperature (25°C) but increases at high temperatures
(85°C); see the IIDLE current parameters in Section 5.7 for details.
表 6-3. Peripheral Groups
Group A
Timer TA0
Timer TA1
Comparator
ADC12_B
REF_A
Group B
Timer TA2
Timer B0
Group C
Timer TA3
eUSCI_A1
eUSCI_A0
eUSCI_B0
eUSCI_B1
6.4 Interrupt Vector Table and Signatures
The interrupt vectors, the power-up start address, and signatures are in the address range 0FFFFh to
0FF80h. 表 6-4 summarizes the content of this address range.
The power-up start address or reset vector is at 0FFFFh to 0FFFEh. It contains the 16-bit address pointing
to the start address of the application program.
The interrupt vectors start at 0FFFDh extending to lower addresses. Each vector contains the 16-bit
address of the appropriate interrupt-handler instruction sequence.
The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as BSL password (if
enabled by the corresponding signature)
The signatures are at 0FF80h extending to higher addresses. Signatures are evaluated during device
start-up. Starting from address 0FF88h extending to higher addresses a JTAG password can
programmed. The password can extend into the interrupt vector locations using the interrupt vector
addresses as additional bits for the password.
See the chapter System Resets, Interrupts, and Operating Modes, System Control Module (SYS) in the
MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for details.
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PRIORITY
表 6-4. Interrupt Sources, Flags, Vectors, and Signatures
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
System Reset
Power-up, Brownout, Supply
Supervisor
External Reset RST
Watchdog time-out (watchdog
mode)
WDT, FRCTL MPU, CS, PMM
password violation
FRAM uncorrectable bit error
detection
SVSHIFG
PMMRSTIFG
WDTIFG
WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
UBDIFG
Reset
0FFFEh
Highest
ACCTEIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
PMMPORIFG, PMMBORIFG
FRAM access time error
MPU segment violation
Software POR, BOR
(1) (2)
(SYSRSTIV)
VMAIFG
JMBNIFG, JMBOUTIFG
CBDIFG, UBDIFG
System NMI
Vacant memory access
JTAG mailbox
FRAM bit error detection
MPU segment violation
(Non)maskable
(Non)maskable
0FFFCh
0FFFAh
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
(1) (3)
(SYSSNIV)
User NMI
External NMI
Oscillator Fault
NMIIFG, OFIFG
(1) (3)
(SYSUNIV)
Comparator_E interrupt flags
Comparator_E
Timer_B TB0
Maskable
Maskable
0FFF8h
0FFF6h
(1)
(CEIV)
TB0CCR0.CCIFG
TB0CCR1.CCIFG to TB0CCR6.CCIFG,
TB0CTL.TBIFG
Timer_B TB0
Maskable
0FFF4h
(TB0IV)(1)
Watchdog Timer
(Interval Timer Mode)
WDTIFG
Maskable
Maskable
0FFF2h
0FFF0h
Reserved
Reserved
UCA0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA0IFG:UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
eUSCI_A0 Receive or Transmit
Maskable
Maskable
Maskable
0FFEEh
0FFECh
0FFEAh
(UCA0IV)(1)
UCB0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB0IFG: UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,
UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,
UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB0IV)(1)
eUSCI_B0 Receive or Transmit
ADC12IFG0 to ADC12IFG31
ADC12LOIFG, ADC12INIFG, ADC12HIIFG,
ADC12RDYIFG, ADC12OVIFG, ADC12TOVIFG
ADC12_B
(1) (4)
(ADC12IV)
Timer_A TA0
Timer_A TA0
TA0CCR0.CCIFG
Maskable
Maskable
0FFE8h
0FFE6h
TA0CCR1.CCIFG to TA0CCR2.CCIFG,
TA0CTL.TAIFG
(TA0IV)(1)
UCA1IFG:UCRXIFG, UCTXIFG (SPI mode)
UCA1IFG:UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
eUSCI_A1 receive or transmit
Maskable
0FFE4h
(UCA1IV)(1)
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space
(3) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(4) Only on devices with ADC, otherwise reserved.
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MSP430FR5872, MSP430FR58721, MSP430FR5870
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ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
表 6-4. Interrupt Sources, Flags, Vectors, and Signatures (continued)
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
UCB1IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB1IFG: UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,
UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,
UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB1IV)(1)
eUSCI_B1 receive or transmit
(Reserved on MSP430FR592x)
Maskable
0FFE2h
DMA0CTL.DMAIFG, DMA1CTL.DMAIFG,
DMA2CTL.DMAIFG
DMA
Maskable
Maskable
Maskable
0FFE0h
0FFDEh
0FFDCh
(DMAIV)(1)
Timer_A TA1
Timer_A TA1
TA1CCR0.CCIFG
TA1CCR1.CCIFG to TA1CCR2.CCIFG,
TA1CTL.TAIFG
(TA1IV)(1)
P1IFG.0 to P1IFG.7
(P1IV)(1)
I/O Port P1
Maskable
Maskable
0FFDAh
0FFD8h
Timer_A TA2
TA2CCR0.CCIFG
TA2CCR1.CCIFG
TA2CTL.TAIFG
(TA2IV)(1)
Timer_A TA2
Maskable
0FFD6h
P2IFG.0 to P2IFG.3
I/O Port P2
Maskable
Maskable
0FFD4h
0FFD2h
(1)
(P2IV)
Timer_A TA3
TA3CCR0.CCIFG
TA3CCR1.CCIFG
TA3CTL.TAIFG
(TA3IV)(1)
Timer_A TA3
I/O Port P3
Maskable
0FFD0h
0FFCEh
P3IFG.0 to P3IFG.7
Maskable
Maskable
(1)
(P3IV)
P4IFG.2 to P4IFG.7
I/O Port P4
Reserved
0FFCCh
0FFCAh
(1)
(P4IV)
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG, RTCOFIFG
RTC_C
AES
Maskable
Maskable
0FFC8h
(1)
(RTCIV)
AESRDYIFG
0FFC6h
0FFC4h
⋮
Lowest
(5)
Reserved
Reserved
0FF8Ch
0FF8Ah
0FF88h
0FF86h
0FF84h
0FF82h
0FF80h
(5)
IP Encapsulation Signature2
(5) (7)
IP Encapsulation Signature1
BSL Signature2
BSL Signature1
JTAG Signature2
JTAG Signature1
(6)
Signatures
(5) May contain a JTAG password required to enable JTAG access to the device.
(6) Signatures are evaluated during device start-up. See the System Resets, Interrupts, and Operating Modes, System Control Module
(SYS) chapter in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for details.
(7) Must not contain 0AAAAh if used as JTAG password.
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6.5 Bootloader (BSL)
The BSL enables programming of the FRAM or RAM using a UART serial interface (FRxxxx devices) or
an I2C interface (FRxxxx1 devices). Access to the device memory through the BSL is protected by an
user-defined password. Use of the BSL requires four pins as shown in 表 6-5. BSL entry requires a
specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For complete description of
the features of the BSL and its implementation, see MSP430 FRAM Device Bootloader (BSL) User's
Guide
.
表 6-5. BSL Pin Requirements and Functions
DEVICE SIGNAL
RST/NMI/SBWTDIO
TEST/SBWTCK
BSL_TX
BSL FUNCTION
Entry sequence signal
Entry sequence signal
Devices with UART BSL (FRxxxx): Data transmit
Devices with UART BSL (FRxxxx): Data receive
Devices with I2C BSL (FRxxxx1): Data
Devices with I2C BSL (FRxxxx1): Clock
Power supply
BSL_RX
BSL_DAT
BSL_CLK
VCC
VSS
Ground supply
6.6 JTAG Operation
6.6.1 JTAG Standard Interface
The MSP430 family supports the standard JTAG interface, which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. 表 6-6 lists the JTAG pin requirements. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools
User's Guide. For a complete description of the features of the JTAG interface and its implementation, see
MSP430 Programming With the JTAG Interface.
表 6-6. JTAG Pin Requirements and Functions
DEVICE SIGNAL
PJ.3/TCK
DIRECTION
FUNCTION
JTAG clock input
JTAG state control
JTAG data input, TCLK input
JTAG data output
Enable JTAG pins
External reset
IN
IN
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
IN
OUT
IN
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
IN
Power supply
VSS
Ground supply
6.6.2 Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the 2-wire Spy-Bi-Wire interface.
Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. 表 6-7
lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User's Guide.
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
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ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
表 6-7. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
DIRECTION
IN
FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input/output
Power supply
IN, OUT
VSS
Ground supply
6.7 FRAM
The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. Features of the FRAM include:
•
•
•
•
Ultra-low-power ultra-fast-write nonvolatile memory
Byte and word access capability
Programmable and automated wait-state generation
Error correction coding (ECC)
注
Wait States
For MCLK frequencies > 8 MHz, wait states must be configured following the flow described
in the "Wait State Control" section of the "FRAM Controller (FRCTRL)" chapter in the
MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.
For important software design information regarding FRAM including but not limited to partitioning the
memory layout according to application-specific code, constant, and data space requirements, the use of
FRAM to optimize application energy consumption, and the use of the Memory Protection Unit (MPU) to
maximize application robustness by protecting the program code against unintended write accesses, see
MSP430™ FRAM Technology – How To and Best Practices
6.8 RAM
The RAM is made up of one sector. The sector can be completely powered down in LPM3 and LPM4 to
save leakage; however, all data is lost during shutdown.
6.9 Tiny RAM
Twenty-six bytes of Tiny RAM are provided in addition to the complete RAM (see 表 6-36). This memory is
always available even in LPM3 and LPM4, while the complete RAM can be powered down in LPM3 and
LPM4. Tiny RAM can be used to hold data or a very small stack when the complete RAM is powered
down in LPM3 and LPM4. Tiny RAM is not available in LPMx.5.
6.10 Memory Protection Unit (MPU) Including IP Encapsulation
The FRAM can be protected by the MPU from inadvertent CPU execution and read or write access.
Features of the MPU include:
•
IP encapsulation with programmable boundaries (prevents reads from "outside" like JTAG or non-IP
software) in steps of 1KB.
•
•
•
Main memory partitioning that can be configured in up to three segments in steps of 1KB.
The access rights for each main and information memory segment can be individually selected.
Access violation flags with interrupt capability for easy servicing of access violations.
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6.11 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430FR58xx,
MSP430FR59xx, and MSP430FR6xx Family User's Guide.
6.11.1 Digital I/O
There are up to nine 8-bit I/O ports implemented:
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Programmable pullup or pulldown on all ports.
Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for all pins of
ports P1 to P4.
•
•
•
Read and write access to port control registers is supported by all instructions.
Ports can be accessed byte-wise or word-wise in pairs.
Capacitive touch functionality is supported on all pins of ports P1 to P7, P9, and PJ.
注
Configuration of Digital I/Os After BOR Reset
To prevent any cross-currents during start-up of the device, all port pins are high-impedance
with Schmitt triggers and their module functions disabled. To enable the I/O functionality after
a BOR reset, the ports must be configured first and then the LOCKLPM5 bit must be cleared.
For details see the "Digital I/O" chapter, section "Configuration After Reset" in the
MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.
6.11.2 Oscillator and Clock System (CS)
The clock system includes support for a 32-kHz watch-crystal oscillator XT1 (LF), an internal very-low-
power low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a
high-frequency crystal oscillator XT2 (HF). The clock system module is designed to meet the requirements
of both low system cost and low power consumption. A fail-safe mechanism exists for all crystal sources.
The clock system module provides the following clock signals:
•
Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (LFXT1), the internal low-frequency
oscillator (VLO), or a digital external low frequency (<50 kHz) clock source.
•
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced from a high-frequency
crystal (HFXT2), the internal DCO, a 32-kHz watch crystal (LFXT1), the internal VLO, or a digital
external clock source.
•
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources made available to MCLK.
6.11.3 Power-Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device . The PMM
also includes the supply voltage supervisor (SVS) and brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power on and power off. The
SVS circuitry detects if the supply voltage drops below a safe level. SVS circuitry is available on the
primary and core supplies.
6.11.4 Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication
as well as signed and unsigned multiply-and-accumulate operations.
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MSP430FR5872, MSP430FR58721, MSP430FR5870
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6.11.5 Real-Time Clock (RTC_C)
The RTC_C module contains an integrated real-time clock (RTC) with the following features implemented:
•
•
Calendar mode with leap year correction
General-purpose counter mode
The internal calendar compensates for months with fewer than 31 days and includes leap year correction.
The RTC_C also supports flexible alarm functions and offset-calibration hardware. RTC operation is
available in LPM3.5 modes to minimize power consumption.
6.11.6 Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart after a software
problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function
is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals. 表 6-8 lists the clocks that the WDT_A module can use.
表 6-8. WDT_A Clocks
NORMAL OPERATION
WDTSSEL
(WATCHDOG AND INTERVAL TIMER MODE)
00
01
10
11
SMCLK
ACLK
VLOCLK
LFMODOSC
6.11.7 System Module (SYS)
The SYS module handles many of the system functions within the device. These system functions include
power-on reset and power-up clear handling, NMI source selection and management, reset interrupt
vector generators, bootloader entry mechanisms, and configuration management (device descriptors).
Also included is a data exchange mechanism using JTAG called a JTAG mailbox that can be used in the
application. 表 6-9 lists the SYS module interrupt vector registers.
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表 6-9. System Module Interrupt Vector Registers
INTERRUPT VECTOR
ADDRESS
INTERRUPT EVENT
VALUE
PRIORITY
REGISTER
No interrupt pending
Brownout (BOR)
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
Highest
RSTIFG RST/NMI (BOR)
PMMSWBOR software BOR (BOR)
LPMx.5 wakeup (BOR)
Security violation (BOR)
Reserved
SVSHIFG SVSH event (BOR)
Reserved
Reserved
PMMSWPOR software POR (POR)
WDTIFG watchdog time-out (PUC)
WDTPW password violation (PUC)
FRCTLPW password violation (PUC)
Uncorrectable FRAM bit error detection (PUC)
Peripheral area fetch (PUC)
PMMPW PMM password violation (PUC)
MPUPW MPU password violation (PUC)
CSPW CS password violation (PUC)
SYSRSTIV, System Reset
019Eh
MPUSEGPIFG encapsulated IP memory segment violation
(PUC)
26h
MPUSEGIIFG information memory segment violation (PUC)
MPUSEG1IFG segment 1 memory violation (PUC)
MPUSEG2IFG segment 2 memory violation (PUC)
MPUSEG3IFG segment 3 memory violation (PUC)
ACCTEIFG access time error (PUC)
Reserved
28h
2Ah
2Ch
2Eh
30h
32h to 3Eh
00h
Lowest
Highest
No interrupt pending
Reserved
02h
Uncorrectable FRAM bit error detection
Reserved
04h
06h
MPUSEGPIFG encapsulated IP memory segment violation
MPUSEGIIFG information memory segment violation
MPUSEG1IFG segment 1 memory violation
MPUSEG2IFG segment 2 memory violation
MPUSEG3IFG segment 3 memory violation
VMAIFG vacant memory access
JMBINIFG JTAG mailbox input
JMBOUTIFG JTAG mailbox output
Correctable FRAM bit error detection
Reserved
08h
0Ah
0Ch
SYSSNIV, System NMI
019Ch
0Eh
10h
12h
14h
16h
18h
1Ah to 1Eh
00h
Lowest
Highest
No interrupt pending
NMIIFG NMI pin
02h
OFIFG oscillator fault
04h
SYSUNIV, User NMI
019Ah
Reserved
06h
Reserved
08h
Reserved
0Ah to 1Eh
Lowest
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MSP430FR5872, MSP430FR58721, MSP430FR5870
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6.11.8 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC12_B conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral. 表 6-10 lists the available DMA triggers.
(1)
表 6-10. DMA Trigger Assignments
TRIGGER
CHANNEL 0
DMAREQ
CHANNEL 1
DMAREQ
CHANNEL 2
DMAREQ
0
1
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2 CCR0 CCIFG
TA3 CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2 CCR0 CCIFG
TA3 CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2 CCR0 CCIFG
TA3 CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
Reserved
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Reserved
Reserved
Reserved
AES Trigger 0(2)
AES Trigger 1(2)
AES Trigger 2(2)
UCA0RXIFG
AES Trigger 0(2)
AES Trigger 1(2)
AES Trigger 2(2)
UCA0RXIFG
AES Trigger 0(2)
AES Trigger 1(2)
AES Trigger 2(2)
UCA0RXIFG
UCA0TXIFG
UCA0TXIFG
UCA0TXIFG
UCA1RXIFG
UCA1RXIFG
UCA1RXIFG
UCA1TXIFG
UCA1TXIFG
UCA1TXIFG
UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)
UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)
UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)
18
19
UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)
UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)
UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)
20
21
22
23
UCB0RXIFG1 (I2C)
UCB0TXIFG1 (I2C)
UCB0RXIFG2 (I2C)
UCB0TXIFG2 (I2C)
UCB0RXIFG1 (I2C)
UCB0TXIFG1 (I2C)
UCB0RXIFG2 (I2C)
UCB0TXIFG2 (I2C)
UCB0RXIFG1 (I2C)
UCB0TXIFG1 (I2C)
UCB0RXIFG2 (I2C)
UCB0TXIFG2 (I2C)
UCB1RXIFG (SPI)
UCB1RXIFG0 (I2C)
UCB1RXIFG (SPI)
UCB1RXIFG0 (I2C)
UCB1RXIFG (SPI)
UCB1RXIFG0 (I2C)
24
25
26
UCB1TXIFG (SPI)
UCB1TXIFG0 (I2C)
UCB1TXIFG (SPI)
UCB1TXIFG0 (I2C)
UCB1TXIFG (SPI)
UCB1TXIFG0 (I2C)
ADC12 end of
conversion(3)
ADC12 end of conversion(3) ADC12 end of conversion(3)
27
28
29
30
31
Reserved
Reserved
MPY ready
DMA2IFG
DMAE0
Reserved
Reserved
MPY ready
DMA0IFG
DMAE0
Reserved
Reserved
MPY ready
DMA1IFG
DMAE0
(1) If a reserved trigger source is selected, no trigger is generated.
(2) Only on devices with AES. Reserved on devices without AES.
(3) Only on devices with ADC. Reserved on devices without ADC.
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6.11.9 Enhanced Universal Serial Communication Interface (eUSCI)
The eUSCI modules are used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols
such as UART, enhanced UART with automatic baud-rate detection, and IrDA.
The eUSCI_An module provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
The eUSCI_Bn module provides support for SPI (3 or 4 pin) and I2C.
Two eUSCI_A modules and two eUSCI_B modules are implemented.
6.11.10 Timer_A TA0, Timer_A TA1
TA0 and TA1 are 16-bit timers/counters (Timer_A type) with three capture/compare registers each. TA0
and TA1 can support multiple capture/compares, PWM outputs, and interval timing (see 表 6-11 and 表 6-
12). TA0 and TA1 have extensive interrupt capabilities. Interrupts may be generated from the counter on
overflow conditions and from each of the capture/compare registers.
表 6-11. Timer_A TA0 Signal Connections
MODULE
OUTPUT
SIGNAL
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
MODULE
BLOCK
DEVICE OUTPUT
SIGNAL
INPUT PORT PIN
OUTPUT PORT PIN
P1.2 or P7.0
TA0CLK
ACLK (internal)
SMCLK (internal)
TA0CLK
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
CCR0
N/A
TA0
N/A
P1.2 or P7.0
P1.5
TA0.0
P1.5
P7.1
P7.1
TA0.0
TA0.0
DVSS
DVCC
VCC
P1.0
P1.6
P7.2
P1.0 or P1.6 or
P7.2
TA0.1
CCI1A
COUT (internal)
DVSS
CCI1B
GND
VCC
CCR1
CCR2
TA1
TA2
TA0.1
TA0.2
(1)
ADC12 (internal)
ADC12SHSx = {1}
DVCC
P1.1 or P1.7 or
P7.3
TA0.2
CCI2A
P1.1
ACLK (internal)
DVSS
CCI2B
GND
VCC
P1.7
P7.3
DVCC
(1) Only on devices with ADC
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
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表 6-12. Timer_A TA1 Signal Connections
MODULE
OUTPUT
SIGNAL
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
MODULE
BLOCK
DEVICE OUTPUT
SIGNAL
INPUT PORT PIN
OUTPUT PORT PIN
P1.1 or P4.4
TA1CLK
ACLK (internal)
SMCLK (internal)
TA1CLK
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
CCR0
N/A
TA0
N/A
P1.1 or P4.4
P1.4 or P4.5
TA1.0
P1.4
P4.5
DVSS
TA1.0
DVSS
DVCC
VCC
P1.2
P4.6
P3.3
P1.2 or P3.3 or
P4.6
TA1.1
CCI1A
COUT (internal)
DVSS
CCI1B
GND
VCC
CCR1
CCR2
TA1
TA2
TA1.1
TA1.2
(1)
ADC12 (internal)
ADC12SHSx = {4}
DVCC
P1.3 or P4.7
TA1.2
CCI2A
CCI2B
GND
VCC
P1.3
P4.7
ACLK (internal)
DVSS
DVCC
(1) Only on devices with ADC
6.11.11 Timer_A TA2
TA2 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers each and with internal
connections only. TA2 can support multiple capture/compares, PWM outputs, and interval timing (see 表
6-13). TA2 has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow
conditions and from each of the capture/compare registers.
表 6-13. Timer_A TA2 Signal Connections
MODULE OUTPUT
DEVICE INPUT SIGNAL
MODULE INPUT NAME
MODULE BLOCK
DEVICE OUTPUT SIGNAL
SIGNAL
COUT (internal)
ACLK (internal)
SMCLK (internal)
TACLK
ACLK
Timer
N/A
SMCLK
From Capacitive Touch
I/O 0 (internal)
INCLK
CCI0A
TA3 CCR0 output
(internal)
TA3 CCI0A input
ACLK (internal)
DVSS
CCI0B
GND
VCC
CCR0
CCR1
TA0
TA1
DVCC
(1)
From Capacitive Touch
I/O 0 (internal)
ADC12 (internal)
CCI1A
ADC12SHSx = {5}
COUT (internal)
DVSS
CCI1B
GND
VCC
DVCC
(1) Only on devices with ADC
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6.11.12 Timer_A TA3
TA3 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers each and with internal
connections only. TA3 can support multiple capture/compares, PWM outputs, and interval timing (see 表
6-14). TA3 has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow
conditions and from each of the capture/compare registers.
表 6-14. Timer_A TA3 Signal Connections
MODULE OUTPUT
DEVICE INPUT SIGNAL
MODULE INPUT NAME
MODULE BLOCK
DEVICE OUTPUT SIGNAL
SIGNAL
COUT (internal)
ACLK (internal)
SMCLK (internal)
TACLK
ACLK
Timer
N/A
SMCLK
From Capacitive Touch
I/O 1 (internal)
INCLK
CCI0A
TA2 CCR0 output
(internal)
TA2 CCI0A input
ACLK (internal)
DVSS
CCI0B
GND
VCC
CCR0
CCR1
TA0
TA1
DVCC
(1)
From Capacitive Touch
I/O 1 (internal)
ADC12 (internal)
CCI1A
ADC12SHSx = {6}
COUT (internal)
DVSS
CCI1B
GND
DVCC
VCC
DVSS
CCI2A
P3.0
P3.0 (Note: Not available for
FR592x(1) 64-pin package
devices)
DVSS (FR592x(1) 64‑pin
package)
CCI2B
CCR2
CCR3
CCR4
TA2
TA3
TA4
DVSS
DVCC
DVSS
GND
VCC
CCI3A
P3.1
P3.1 (Note: Not available for
FR592x(1) 64-pin package
devices)
DVSS (FR592x(1) 64‑pin
package)
CCI3B
DVSS
DVCC
DVSS
GND
VCC
CCI4A
P3.2
P3.2 (Note: Not available for
FR592x(1) 64-pin package
devices)
DVSS (FR592x(1) 64‑pin
package)
CCI4B
DVSS
DVCC
GND
VCC
(1) Only on devices with ADC.
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
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6.11.13 Timer_B TB0
TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers each. TB0 can support
multiple capture/compares, PWM outputs, and interval timing (see 表 6-15). TB0 has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
表 6-15. Timer_B TB0 Signal Connections
MODULE
OUTPUT
SIGNAL
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
MODULE
BLOCK
DEVICE OUTPUT
SIGNAL
INPUT PORT PIN
OUTPUT PORT PIN
P2.0 or P3.3 or
P5.7
TB0CLK
TBCLK
ACLK (internal)
ACLK
Timer
N/A
N/A
SMCLK (internal)
SMCLK
P2.0 or P3.3 or
P5.7
TB0CLK
INCLK
P3.4
P6.4
TB0.0
TB0.0
CCI0A
CCI0B
P3.4
P6.4
(1)
CCR0
CCR1
TB0
TB1
TB0.0
TB0.1
ADC12 (internal)
DVSS
GND
ADC12SHSx = {2}
DVCC
TB0.1
VCC
P3.5 or P6.5
P3.6 or P6.6
CCI1A
CCI1B
P3.5
P6.5
COUT (internal)
(1)
ADC12 (internal)
DVSS
GND
ADC12SHSx = {3}
DVCC
TB0.2
ACLK (internal)
DVSS
VCC
CCI2A
CCI2B
GND
P3.6
P6.6
CCR2
CCR3
CCR4
CCR5
CCR6
TB2
TB3
TB4
TB5
TB6
TB0.2
TB0.3
TB0.4
TB0.5
TB0.6
DVCC
VCC
DVSS
CCI3A
CCI3B
GND
P3.7
P2.2
P2.1
P2.0
TB0.3
DVSS
P3.7
P2.2
P2.1
P2.0
DVCC
VCC
DVSS
CCI4A
CCI4B
GND
TB0.4
DVSS
DVCC
VCC
DVSS
CCI5A
CCI5B
GND
TB0.5
DVSS
DVCC
VCC
DVSS
CCI6A
CCI6B
GND
TB0.6
DVSS
DVCC
VCC
(1) Only on devices with ADC
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MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
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6.11.14 ADC12_B
The ADC12_B module supports fast 12-bit analog-to-digital conversions with differential and single-ended
inputs. The module implements a 12-bit SAR core, sample select control, reference generator and a
conversion result buffer. A window comparator with a lower and upper limits allows CPU-independent
result monitoring with three window comparator interrupt flags.
表 6-16 summarizes the available external trigger sources.
表 6-17 lists the available multiplexing between internal and external analog inputs.
表 6-16. ADC12_B Trigger Signal Connections
ADC12SHSx
CONNECTED TRIGGER
SOURCE
BINARY
DECIMAL
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
Software (ADC12SC)
Timer_A TA0 CCR1 output
Timer_B TB0 CCR0 output
Timer_B TB0 CCR1 output
Timer_A TA1 CCR1 output
Timer_A TA2 CCR1 output
Timer_A TA3 CCR1 output
Reserved (DVSS)
表 6-17. ADC12_B External and Internal Signal Mapping
EXTERNAL
(CONTROL BIT = 0)
INTERNAL
CONTROL BIT
(CONTROL BIT = 1)
Battery monitor
Temperature sensor
N/A(1)
ADC12BATMAP
ADC12TCMAP
ADC12CH0MAP
ADC12CH1MAP
ADC12CH2MAP
ADC12CH3MAP
A31
A30
A29
A28
A27
A26
N/A(1)
N/A(1)
N/A(1)
(1) N/A: No internal signal available on this device.
6.11.15 Comparator_E
The primary function of the Comparator_E module is to support precision slope analog-to-digital
conversions, battery voltage supervision, and monitoring of external analog signals.
6.11.16 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 signature is based on the CRC-CCITT standard.
6.11.17 CRC32
The CRC32 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC32 signature is based on the ISO 3309 standard.
6.11.18 AES256 Accelerator
The AES accelerator module performs encryption and decryption of 128-bit data with 128-, 192-, or 256-
bit keys according to the advanced encryption standard (AES) (FIPS PUB 197) in hardware.
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MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
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6.11.19 True Random Seed
The Device Descriptor Info (TLV) (see 节 6.12) contains a 128-bit true random seed that can be used to
implement a deterministic random-number generator.
6.11.20 Shared Reference (REF_A)
The REF_A module is responsible for generation of all critical reference voltages that can be used by the
various analog peripherals in the device.
6.11.21 Embedded Emulation
6.11.21.1 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The S version of the EEM has the following features:
•
•
•
•
•
Three hardware triggers or breakpoints on memory access
One hardware trigger or breakpoint on CPU register write access
Up to four hardware triggers that can be combined to form complex triggers or breakpoints
One cycle counter
Clock control on module level
6.11.21.2 EnergyTrace++ Technology
The devices implement circuitry to support EnergyTrace++ technology. The EnergyTrace++ technology
lets you observe information about the internal states of the microcontroller. These states include the CPU
Program Counter (PC), the ON or OFF status of the peripherals and the system clocks (regardless of the
clock source), and the low-power mode currently in use. These states can always be read by a debug
tool, even when the microcontroller sleeps in LPMx.5 modes.
The activity of the following modules can be observed:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MPY is calculating.
WDT is counting.
RTC is counting.
ADC: a sequence, sample, or conversion is active.
REF: REFBG or REFGEN active and BG in static mode.
COMP is on.
AES is encrypting or decrypting.
eUSCI_A0 is transferring (receiving or transmitting) data.
eUSCI_A1 is transferring (receiving or transmitting) data.
eUSCI_B0 is transferring (receiving or transmitting) data.
eUSCI_B1 is transferring (receiving or transmitting) data.
TB0 is counting.
TA0 is counting.
TA1 is counting.
TA2 is counting.
TA3 is counting.
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6.11.22 Input/Output Diagrams
6.11.22.1 Digital I/O Functionality Port P1 to P7 and P9
The port pins provide the following features:
•
•
•
Interrupt and wakeup from LPMx.5 capability for ports P1 to P4
Capacitive touch functionality (see 节 6.11.22.2)
Up to three digital module input and/or output functions
图 6-1 shows the features and the corresponding control logic (besides the Capacitive Touch logic). 图 6-1
is applicable for all port pins P1.0 to P9.7, unless a dedicated diagram is available in the following
sections. The module functions provided per pin and whether the direction is controlled by the module or
by the port direction register for the selected secondary function are described in the following pin function
tables.
PxREN.y
Pad Logic
0 0
0 1
1 0
1 1
PxDIR.y
From module 1(A)
From module 2(A)
From module 3(A)
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
PxOUT.y
From module 1
From module 2
From module 3
Px.y/Mod1/Mod2/Mod3
PxSEL1.y
PxSEL0.y
PxIN.y
To module 1(B)
To module 2(B)
To module 3(B)
A. The direction is either controlled by connected module or by the corresponding PxDIR.y bit. See pin function tables.
B. The inputs from several pins towards a module are ORed together.
NOTE: Functional representation only.
图 6-1. General Port Pin Diagram
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6.11.22.2 Capacitive Touch Functionality on Port P1 to P7, P9, and PJ
图 6-2 shows the the capacitive touch functionality that is available on all port pins. The capacitive touch
functionality is controlled using the capacitive touch I/O control registers CAPTIO0CTL and CAPTIO1CTL
as described in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family
User's Guide. The capacitive touch functionality is not shown in the other pin diagrams.
Analog Enable
PxREN.y
Capacitive Touch Enable 0
Capacitive Touch Enable 1
DVSS
DVCC
0
1
1
Direction Control
PxOUT.y
0
1
Output Signal
Px.y
Input Signal
D
Q
EN
Capacitive Touch Signal 0
Capacitive Touch Signal 1
NOTE: Functional representation only.
图 6-2. Capacitive Touch I/O Functionality
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6.11.22.3 Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger
图 6-3 shows the port diagram. 表 6-18 summarizes the selection of the pin functions.
To ADC
From ADC
To Comparator
From Comparator
CEPD.x
Pad Logic
P1REN.x
0 0
0 1
1 0
1 1
P1DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P1OUT.x
DVSS
DVSS
P1.0/TA0.1/DMAE0/RTCCLK/
A0/C0/VREF-/VeREF-
DVSS
P1.1/TA0.2/TA1CLK/COUT/
A1/C1/VREF+/VeREF+
P1SEL1.x
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P1.3/TA1.2/A3/C3
P1SEL0.x
P1IN.x
Bus
Keeper
NOTE: Functional representation only.
图 6-3. Port P1 (P1.0 to P1.3) Diagram
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MSP430FR5872, MSP430FR58721, MSP430FR5870
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ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
表 6-18. Port P1 (P1.0 to P1.3) Pin Functions
(1)
CONTROL BITS OR SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/
VREF-/VeREF-
0
P1.0 (I/O)
TA0.CCI1A
TA0.1
I: 0; O: 1
0
0
0
0
1
1
0
1
DMAE0
RTCCLK(2)
0
1
(3) (4)
A0, C0, VREF-, VeREF-
P1.1 (I/O)
X
1
0
1
0
P1.1/TA0.2/TA1CLK/COUT/A1/C1/
VREF+/VeREF+
1
2
3
I: 0; O: 1
TA0.CCI2A
TA0.2
0
0
1
1
0
1
TA1CLK
COUT(5)
0
1
(3) (4)
A1, C1, VREF+, VeREF+
P1.2 (I/O)
X
1
0
1
0
P1.2/TA1.1/TA0CLK/COUT/A2/C2
I: 0; O: 1
TA1.CCI1A
TA1.1
0
0
1
1
0
1
TA0CLK
COUT(5)
0
1
(3) (4)
A2, C2
X
1
0
1
0
P1.3/TA1.2/A3/C3
P1.3 (I/O)
TA1.CCI2A
TA1.2
I: 0; O: 1
0
1
0
1
X
0
1
N/A
1
1
0
1
Internally tied to DVSS
(3) (4)
A3, C3
(1) X = Don't care
(2) Do not use this pin as RTCCLK output if the DMAE0 functionality is used on any other pin. Select an alternative RTCCLK output pin.
(3) Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(4) Setting the CEPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPD.x bit.
(5) Do not use this pin as COUT output if the TA1CLK functionality is used on any other pin. Select an alternative COUT output pin.
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79
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产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
6.11.22.4 Port P1 (P1.4 to P1.7) Input/Output With Schmitt Trigger
For the port diagram, see 图 6-1. 表 6-19 summarizes the selection of the pin functions.
表 6-19. Port P1 (P1.4 to P1.7) Pin Functions
(1)
CONTROL BITS OR SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.4/UCB0CLK/UCA0STE/TA1.0
4
P1.4 (I/O)
UCB0CLK
UCA0STE
TA1.CCI0A
TA1.0
I: 0; O: 1
0
0
1
0
1
0
(2)
X
(3)
X
0
1
1
1
P1.5/UCB0STE/UCA0CLK/TA0.0
P1.6/UCB0SIMO/UCB0SDA/TA0.1
5
6
P1.5 (I/O)
UCB0STE
UCA0CLK
TA0.CCI0A
TA0.0
I: 0; O: 1
0
0
1
0
1
0
(2)
X
(3)
X
0
1
1
1
P1.6 (I/O)
I: 0; O: 1
0
0
0
1
(2)
UCB0SIMO/UCB0SDA
N/A
X
0
1
1
0
1
Internally tied to DVSS
TA0.CCI1A
1
0
1
TA0.1
P1.7/UCB0SOMI/UCB0SCL/TA0.2
7
P1.7 (I/O)
I: 0; O: 1
0
0
0
1
(2)
UCB0SOMI/UCB0SCL
N/A
X
0
1
0
1
1
1
0
1
Internally tied to DVSS
TA0.CCI2A
TA0.2
(1) X = Don't care
(2) Direction controlled by eUSCI_B0 module.
(3) Direction controlled by eUSCI_A0 module.
80
Detailed Description
版权 © 2015–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
6.11.22.5 Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
For the port diagram, see 图 6-1. 表 6-20 summarizes the selection of the pin functions.
表 6-20. Port P2 (P2.0 to P2.3) Pin Functions
(1)
CONTROL BITS OR SIGNALS
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL1.x
P2SEL0.x
P2.0/UCA0SIMO/UCA0TXD/TB0.6/
TB0CLK
0
P2.0 (I/O)
I: 0; O: 1
0
0
0
1
(2)
UCA0SIMO/UCA0TXD
TB0.CCI6B
TB0.6
X
0
1
1
0
1
1
TB0CLK
0
1
Internally tied to DVSS
P2.1 (I/O)
P2.1/UCA0SOMI/UCA0RXD/TB0.5/
DMAE0
1
2
3
I: 0; O: 1
0
0
0
1
(2)
UCA0SOMI/UCA0RXD
TB0.CCI5B
TB0.5
X
0
1
1
0
1
1
DMA0E
0
1
Internally tied to DVSS
P2.2 (I/O)
P2.2/UCA0CLK/TB0.4/RTCCLK
I: 0; O: 1
0
0
0
1
(2)
UCA0CLK
X
TB0.CCI4B
TB0.4
0
1
1
0
1
1
N/A
0
1
RTCCLK
P2.3/UCA0STE/TB0OUTH
P2.3 (I/O)
I: 0; O: 1
0
0
0
1
(2)
UCA0STE
X
TB0OUTH
0
1
0
1
1
1
0
1
Internally tied to DVSS
N/A
Internally tied to DVSS
(1) X = Don't care
(2) Direction controlled by eUSCI_A0 module.
版权 © 2015–2018, Texas Instruments Incorporated
Detailed Description
81
提交文档反馈意见
产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
6.11.22.6 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
For the port diagram, see 图 6-1. 表 6-21 and 表 6-22 summarize the selection of the pin functions.
表 6-21. Port P3 (P3.0 to P3.3) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P3.x)
P3.0/UCB1CLK
x
FUNCTION
P3DIR.x
P3SEL1.x
P3SEL0.x
0
P3.0 (I/O)
UCB1CLK
I: 0; O: 1
0
0
0
1
(2)
X
TA3.CCI2B (Note: not available for
FR592x(1) 64-pin package devices)
0
1
1
0
TA3.2
Internally tied to DVSS (for FR292x(1) 64-pin
package devices)
N/A
0
1
1
1
Internally tied to DVSS
P3.1 (I/O)
P3.1/UCB1SIMO/UCB1SDA
1
2
3
I: 0; O: 1
0
0
0
1
(2)
UCB1SIMO/UCB1SDA
X
TA3.CCI3B (Note: not available for
FR592x(1) 64-pin package devices)
0
1
1
0
TA3.3
Internally tied to DVSS (for FR592x(1) 64-pin
package devices)
N/A
0
1
1
1
Internally tied to DVSS
P3.2 (I/O)
P3.2/UCB1SOMI/UCB1SCL
I: 0; O: 1
0
0
0
1
(2)
UCB1SOMI/UCB1SCL
X
TA3.CCI4B (Note: not available for
FR592x(1) 64-pin package devices)
0
1
1
0
TA3.4
Internally tied to DVSS (for FR592x(1) 64-pin
package devices)
0
1
0
0
1
0
1
1
P3.3/TA1.1/TB0CLK
P3.3 (I/O)
I: 0; O: 1
N/A
0
1
0
1
0
1
Internally tied to DVSS
TA1.CCI1A
TA1.1
1
1
0
1
TB0CLK
Internally tied to DVSS
(1) X = Don't care
(2) Direction controlled by eUSCI_B1 module.
82
Detailed Description
版权 © 2015–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
表 6-22. Port P3 (P3.4 to P3.7) Pin Functions
(1)
CONTROL BITS OR SIGNALS
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x
P3SEL1.x
P3SEL0.x
P3.4/UCA1SIMO/UCA1TXD/TB0.0
P3.5/UCA1SOMI/UCA1RXD/TB0.1
P3.6/UCA1CLK/TB0.2
4
P3.4 (I/O)
I: 0; O: 1
0
0
0
1
(2)
UCA1SIMO/UCA1TXD
TB0CCI0A
TB0.0
X
0
1
1
0
1
1
N/A
0
1
Internally tied to DVSS
P3.5 (I/O)
5
6
7
I: 0; O: 1
0
0
0
1
(2)
UCA1SOMI/UCA1RXD
TB0CCI1A
TB0.1
X
0
1
1
0
1
1
N/A
0
1
Internally tied to DVSS
P3.6 (I/O)
I: 0; O: 1
0
0
0
1
(2)
UCA1CLK
X
TB0CCI2A
TB0.2
0
1
1
0
1
1
N/A
0
1
Internally tied to DVSS
P3.7 (I/O)
P3.7/UCA1STE/TB0.3
I: 0; O: 1
0
0
0
1
(2)
UCA1STE
X
TB0CCI3B
TB0.3
0
1
0
1
1
1
0
1
N/A
Internally tied to DVSS
(1) X = Don't care
(2) Direction controlled by eUSCI_A1 module.
版权 © 2015–2018, Texas Instruments Incorporated
Detailed Description
83
提交文档反馈意见
产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
6.11.22.7 Port P4 (P4.2 to P4.7) Input/Output With Schmitt Trigger
For the port diagram, see 图 6-1. 表 6-23 and 表 6-24 summarize the selection of the pin functions.
表 6-23. Port P4 (P4.2 and P4.3) Pin Functions
(1)
CONTROL BITS OR SIGNALS
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x
P4SEL1.x
P4SEL0.x
P4.2/UCA0SIMO/UCA0TXD/UCB1CLK
2
P4.2 (I/O)
I: 0; O: 1
0
0
1
0
1
0
(2)
UCA0SIMO/UCA0TXD
UCB1CLK
X
(3)
X
N/A
0
1
1
1
Internally tied to DVSS
P4.3 (I/O)
P4.3/UCA0SOMI/UCA0RXD/UCB1STE
3
I: 0; O: 1
0
0
1
0
1
0
(2)
UCA0SOMI/UCA0RXD
UCB1STE
X
(3)
X
N/A
0
1
1
1
Internally tied to DVSS
(1) X = Don't care
(2) Direction controlled by eUSCI_A0 module.
(3) Direction controlled by eUSCI_B1 module.
84
Detailed Description
版权 © 2015–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
表 6-24. Port P4 (P4.4 to P4.7) Pin Functions
(1)
CONTROL BITS OR SIGNALS
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x
P4SEL1.x
P4SEL0.x
P4.4/UCB1STE/TA1CLK
4
P4.4 (I/O)
N/A
I: 0; O: 1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Internally tied to DVSS
UCB1STE
1
(2)
X
TA1CLK
0
Internally tied to DVSS
P4.5 (I/O)
1
P4.5/UCB1CLK/TA1.0
5
6
7
I: 0; O: 1
N/A
0
1
Internally tied to DVSS
UCB1CLK
(2)
X
TA1CCI0A
0
TA1.0
1
P4.6/UCB1SIMO/UCB1SDA/TA1.1
P4.7/UCB1SOMI/UCB1SCL/TA1.2
P4.6 (I/O)
I: 0; O: 1
N/A
0
1
Internally tied to DVSS
UCB1SIMO/UCB1SDA
TA1CCI1A
(2)
X
0
TA1.1
1
P4.7 (I/O)
I: 0; O: 1
N/A
0
1
Internally tied to DVSS
UCB1SOMI/UCB1SCL
TA1CCI2A
(2)
X
0
1
TA1.2
(1) X = Don't care
(2) Direction controlled by eUSCI_B1 module.
版权 © 2015–2018, Texas Instruments Incorporated
Detailed Description
85
提交文档反馈意见
产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
6.11.22.8 Port P5 (P5.4 to P5.7) Input/Output With Schmitt Trigger
For the port diagram, see 图 6-1. 表 6-25 summarizes the selection of the pin functions.
表 6-25. Port P5 (P5.4 to P5.7) Pin Functions
(1)
CONTROL BITS OR SIGNALS
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL1.x
P5SEL0.x
P5.4/UCA1SIMO/UCA1TXD
4
P5.4 (I/O)
I: 0; O: 1
0
0
0
1
(2)
UCA1SIMO/UCA1TXD
N/A
X
0
1
1
0
1
Internally tied to DVSS
N/A
1
0
1
Internally tied to DVSS
P5.5 (I/O)
P5.5/UCA1SOMI/UCA1RXD
5
6
7
I: 0; O: 1
0
0
0
1
(2)
UCA1SOMI/UCA1RXD
N/A
X
0
1
1
0
1
Internally tied to DVSS
N/A
1
0
1
Internally tied to DVSS
P5.6 (I/O)
P5.6/UCA1CLK
I: 0; O: 1
0
0
0
1
(2)
UCA1CLK
X
N/A
0
1
1
0
1
Internally tied to DVSS
N/A
1
0
1
Internally tied to DVSS
P5.7 (I/O)
P5.7/UCA1STE/TB0CLK
I: 0; O: 1
0
0
0
1
(2)
UCA1STE
X
N/A
0
1
0
1
1
1
0
1
Internally tied to DVSS
TB0CLK
Internally tied to DVSS
(1) X = Don't care
(2) Direction controlled by eUSCI_A1 module.
86
Detailed Description
版权 © 2015–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
6.11.22.9 Port P6 (P6.0 to P6.6) Input/Output With Schmitt Trigger
图 6-4 shows the port diagram. 表 6-26 and 表 6-27 summarize the selection of the pin functions.
Pad Logic
P6REN.x
0 0
0 1
1 0
1 1
P6DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P6OUT.x
From module 1
From module 2
DVSS
P6.0
P6.1
P6.2/COUT
P6.3
P6SEL1.x
P6.4/TB0.0
P6.5/TB0.1
P6.6/TB0.2
P6SEL0.x
P6IN.x
Bus
Keeper
To module 1(A)
To module 2(A)
NOTE: Functional representation only.
图 6-4. Port P6 (P6.0 to P6.6) Diagram
版权 © 2015–2018, Texas Instruments Incorporated
Detailed Description
87
提交文档反馈意见
产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
表 6-26. Port P6 (P6.0 to P6.2) Pin Functions
(1)
CONTROL BITS OR SIGNALS
PIN NAME (P6.x)
x
FUNCTION
P6DIR.x
P6SEL1.x
P6SEL0.x
P6.0
0
P6.0 (I/O)
N/A
I: 0; O: 1
0
0
0
0
1
1
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
N/A
X
1
0
1
0
P6.1
1
2
P6.1 (I/O)
I: 0; O: 1
N/A
0
0
1
1
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
N/A
X
1
0
1
0
P6.2/COUT
P6.2 (I/O)
I: 0; O: 1
N/A
0
1
0
1
X
0
1
COUT
N/A
1
1
0
1
Internally tied to DVSS
N/A
(1) X = Don't care
88
Detailed Description
版权 © 2015–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
表 6-27. Port P6 (P6.3 to P6.6) Pin Functions
(1)
CONTROL BITS OR SIGNALS
PIN NAME (P6.x)
x
FUNCTION
P6DIR.x
P6SEL1.x
P6SEL0.x
P6.3
3
P6.3 (I/O)
N/A
I: 0; O: 1
0
0
0
0
1
1
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
N/A
X
1
0
1
0
P6.4/TB0.0
P6.5/TB0.1
P6.6/TB0.2
4
5
6
P6.4 (I/O)
I: 0; O: 1
TB0CCI0B
0
0
1
1
0
TB0.0
1
N/A
0
Internally tied to DVSS
1
N/A
X
1
0
1
0
P6.5 (I/O)
I: 0; O: 1
TB0CCI1A
0
0
1
1
0
TB0.1
1
N/A
0
Internally tied to DVSS
1
N/A
X
1
0
1
0
P6.6 (I/O)
I: 0; O: 1
TB0CCI2A
0
1
0
1
X
0
1
TB0.2
N/A
1
1
0
1
Internally tied to DVSS
N/A
(1) X = Don't care
版权 © 2015–2018, Texas Instruments Incorporated
Detailed Description
89
提交文档反馈意见
产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
6.11.22.10 Port P7 (P7.0 to P7.4) Input/Output With Schmitt Trigger
For the port diagram, see 图 6-1. 表 6-28 and 表 6-29 summarize the selection of the pin functions.
表 6-28. Port P7 (P7.0 to P7.3) Pin Functions
(1)
CONTROL BITS OR SIGNALS
PIN NAME (P7.x)
P7.0/TA0CLK
x
FUNCTION
P7DIR.x
P7SEL1.x
P7SEL0.x
0
P7.0 (I/O)
TA0CLK
I: 0; O: 1
0
0
0
0
1
1
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
N/A
0
1
0
0
1
0
1
Internally tied to DVSS
1
P7.1/TA0.0/ACLK
1
2
3
P7.1 (I/O)
I: 0; O: 1
TA0CCI0B
0
TA0.0
1
N/A
0
1
0
Internally tied to DVSS
1
N/A
0
1
0
0
1
0
1
ACLK
1
P7.2/TA0.1
P7.2 (I/O)
I: 0; O: 1
TA0CCI1A
0
TA0.1
1
N/A
0
1
0
Internally tied to DVSS
1
N/A
0
1
0
0
1
0
1
N/A
1
P7.3/TA0.2
P7.3 (I/O)
I: 0; O: 1
TA0CCI2A
0
1
0
1
0
1
TA0.2
N/A
1
1
0
1
Internally tied to DVSS
N/A
Internally tied to DVSS
(1) X = Don't care
表 6-29. Port P7 (P7.4) Pin Functions
(1)
CONTROL BITS OR SIGNALS
PIN NAME (P7.x)
x
FUNCTION
P7DIR.x
P7SEL1.x
P7SEL0.x
P7.4/SMCLK
4
P7.4 (I/O)
N/A
I: 0; O: 1
0
0
0
1
0
1
0
1
0
1
1
1
Internally tied to DVSS
N/A
0
1
Internally tied to DVSS
N/A
SMCLK
(1) X = Don't care
90
Detailed Description
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MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
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ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
6.11.22.11 Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
图 6-5 shows the port diagram. 表 6-30 summarizes the selection of the pin functions.
To ADC
From ADC
To Comparator
From Comparator
CEPD.x
Pad Logic
P9REN.x
P9DIR.x
0 0
0 1
1 0
1 1
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P9OUT.x
DVSS
DVSS
P9.4/A12/C12
P9.5/A13/C13
P9.6/A14/C14
P9.7/A15/C15
DVSS
P9SEL1.x
P9SEL0.x
P9IN.x
Bus
Keeper
NOTE: Functional representation only.
图 6-5. Port P9 (P9.4 to P9.7) Diagram
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Detailed Description
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产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
表 6-30. Port P9 (P9.4 to P9.7) Pin Functions
(1)
CONTROL BITS OR SIGNALS
PIN NAME (P9.x)
P9.4/A12/C12
x
FUNCTION
P9DIR.x
P9SEL1.x
P9SEL0.x
4
P9.4 (I/O)
N/A
I: 0; O: 1
0
0
0
0
1
1
0
Internally tied to DVSS
N/A
1
0
Internally tied to DVSS
1
(2) (3)
A12/C12
X
1
0
1
0
P9.5/A13/C13
P9.6/A14/C14
P9.7/A15/C15
5
6
7
P9.5 (I/O)
I: 0; O: 1
N/A
0
0
1
1
0
Internally tied to DVSS
N/A
1
0
Internally tied to DVSS
1
(2) (3)
A13/C13
X
1
0
1
0
P9.6 (I/O)
I: 0; O: 1
N/A
0
0
1
1
0
Internally tied to DVSS
N/A
1
0
Internally tied to DVSS
1
(2) (3)
A14/C14
X
1
0
1
0
P9.7 (I/O)
I: 0; O: 1
N/A
0
1
0
1
X
0
1
Internally tied to DVSS
N/A
1
1
0
1
Internally tied to DVSS
(2) (3)
A15/C15
(1) X = Don't care
(2) Setting P9SEL1.x and P9SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(3) Setting the CEPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPD.x bit.
92
Detailed Description
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提交文档反馈意见
产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
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ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
6.11.22.12 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
图 6-6 and 图 6-7 show the port diagrams. 表 6-31 summarizes the selection of the pin functions.
Pad Logic
To LFXT XIN
PJREN.4
0 0
0 1
1 0
1 1
PJDIR.4
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
PJOUT.4
DVSS
DVSS
DVSS
PJ.4/LFXIN
PJSEL1.4
PJSEL0.4
PJIN.4
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 6-6. Port PJ (PJ.4) Diagram
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Detailed Description
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产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
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Pad Logic
To LFXT XOUT
PJSEL0.4
PJSEL1.4
LFXTBYPASS
PJREN.5
0 0
0 1
1 0
1 1
PJDIR.5
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
PJOUT.5
DVSS
DVSS
PJ.5/LFXOUT
DVSS
PJSEL1.5
PJSEL0.5
PJIN.5
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 6-7. Port PJ (PJ.5) Diagram
94
Detailed Description
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提交文档反馈意见
产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
表 6-31. Port PJ (PJ.4 and PJ.5) Pin Functions
(1)
CONTROL BITS OR SIGNALS
PIN NAME (PJ.x)
x
FUNCTION
PJDIR.x
PJSEL1.5
PJSEL0.5
PJSEL1.4
PJSEL0.4 LFXTBYPASS
PJ.4/LFXIN
4
PJ.4 (I/O)
I: 0; O: 1
X
X
0
0
X
N/A
0
1
X
X
1
X
X
Internally tied to DVSS
(2)
LFXIN crystal mode
X
X
X
X
X
X
0
0
0
1
X
0
1
X
0
1
X
1
1
0
1
(2)
LFXIN bypass mode
PJ.5/LFXOUT
5
0
0
1(3)
0
PJ.5 (I/O)
I: 0; O: 1
0
0
X
X
0
(4)
(4)
N/A
0
See
See
X
X
0
1(3)
0
(4)
(4)
Internally tied to DVSS
1
See
See
X
X
1(3)
0
LFXOUT crystal mode
X
X
X
0
1
(2)
(1) X = Don't care
(2) Setting PJSEL1.4 = 0 and PJSEL0.4 = 1 causes the general-purpose I/O to be disabled. When LFXTBYPASS = 0, PJ.4 and PJ.5 are
configured for crystal operation and PJSEL1.5 and PJSEL0.5 are don't care. When LFXTBYPASS = 1, PJ.4 is configured for bypass
operation and PJ.5 is configured as general-purpose I/O.
(3) When PJ.4 is configured in bypass mode, PJ.5 is configured as general-purpose I/O.
(4) With PJSEL0.5 = 1 or PJSEL1.5 =1 the general-purpose I/O functionality is disabled. No input function is available. Configured as
output, the pin is actively pulled to zero.
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Detailed Description
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产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
6.11.22.13 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
图 6-8 and 图 6-9 show the port diagrams. 表 6-32 summarizes the selection of the pin functions.
Pad Logic
To HFXT XIN
PJREN.6
0 0
0 1
1 0
1 1
PJDIR.6
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
PJOUT.6
DVSS
DVSS
DVSS
PJ.6/HFXIN
PJSEL1.6
PJSEL0.6
PJIN.6
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 6-8. Port PJ (PJ.6) Diagram
96
Detailed Description
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提交文档反馈意见
产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
Pad Logic
To HFXT XOUT
PJSEL0.6
PJSEL1.6
HFXTBYPASS
PJREN.7
0 0
PJDIR.7
0 1
1 0
1 1
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
PJOUT.7
DVSS
DVSS
DVSS
PJ.7/HFXOUT
PJSEL1.7
PJSEL0.7
PJIN.7
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 6-9. Port PJ (PJ.7) Diagram
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Detailed Description
97
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产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
表 6-32. Port PJ (PJ.6 and PJ.7) Pin Functions
(1)
CONTROL BITS OR SIGNALS
PIN NAME (PJ.x)
x
FUNCTION
PJ.6 (I/O)
PJDIR.x
PJSEL1.7
PJSEL0.7
PJSEL1.6
PJSEL0.6 HFXTBYPASS
PJ.6/HFXIN
6
I: 0; O: 1
X
X
0
0
X
N/A
0
1
X
X
1
X
X
Internally tied to DVSS
HFXIN crystal mode(2)
HFXIN bypass mode(2)
X
X
X
X
X
X
0
0
0
1
X
0
1
X
0
1
X
0
1
1
0
1
PJ.7/HFXOUT
7
0
0
1(3)
0
PJ.7 (I/O)
N/A
I: 0; O: 1
0
0
X
X
0
(4)
(4)
0
See
See
X
X
0
1(3)
0
(4)
(4)
Internally tied to DVSS
HFXOUT crystal mode(2)
1
See
See
X
X
1
1(3)
0
X
X
X
(1) X = Don't care
(2) Setting PJSEL1.6 = 0 and PJSEL0.6 = 1 causes the general-purpose I/O to be disabled. When HFXTBYPASS = 0, PJ.6 and PJ.7 are
configured for crystal operation and PJSEL1.6 and PJSEL0.7 are don't care. When HFXTBYPASS = 1, PJ.6 is configured for bypass
operation and PJ.7 is configured as general-purpose I/O.
(3) When PJ.6 is configured in bypass mode, PJ.7 is configured as general-purpose I/O.
(4) With PJSEL0.7 = 1 or PJSEL1.7 = 1 the general-purpose I/O functionality is disabled. No input function is available. Configured as
output, the pin is actively pulled to zero.
98
Detailed Description
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提交文档反馈意见
产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
6.11.22.14 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt
Trigger
图 6-10 shows the port diagram. 表 6-33 summarizes the selection of the pin functions.
Pad Logic
DVSS
JTAG enable
From JTAG
From JTAG
PJREN.x
0 0
0 1
1 0
1 1
PJDIR.x
1
0
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
PJOUT.x
From module 1
1
0
From Status Register (SR)
DVSS
PJ.0/TDO/TB0OUTH/
SMCLK SRSCG1
PJ.1/TDI/TCLK/MCLK/
SRSCG0
PJ.2/TMS/ACLK/
SROSCOFF
PJSEL1.x
PJSEL0.x
PJIN.x
PJ.3/TCK/COUT/
SRCPUOFF
Bus
Keeper
EN
D
To modules
and JTAG
NOTE: Functional representation only.
图 6-10. Port PJ (PJ.0 to PJ.3) Diagram
版权 © 2015–2018, Texas Instruments Incorporated
Detailed Description
99
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产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
表 6-33. Port PJ (PJ.0 to PJ.3) Pin Functions
(1)
CONTROL BITS OR SIGNALS
PIN NAME (PJ.x)
x
FUNCTION
PJDIR.x
PJSEL1.x
PJSEL0.x
(2)
PJ.0/TDO/TB0OUTH/
SMCLK/SRSCG1
0
PJ.0 (I/O)
I: 0; O: 1
0
0
(3)
TDO
X
X
X
TB0OUTH
SMCLK(4)
N/A
0
0
1
1
1
0
1
1
0
CPU Status Register Bit SCG1
N/A
1
0
Internally tied to DVSS
1
(2)
PJ.1/TDI/TCLK/MCLK/
SRSCG0
1
2
3
PJ.1 (I/O)
I: 0; O: 1
0
0
(3) (5)
TDI/TCLK
X
X
X
N/A
0
0
1
1
1
0
1
MCLK
1
N/A
0
CPU Status Register Bit SCG0
N/A
1
0
Internally tied to DVSS
1
(2)
PJ.2/TMS/ACLK/
SROSCOFF
PJ.2 (I/O)
I: 0; O: 1
0
0
(3) (5)
TMS
X
X
X
N/A
0
0
1
1
1
0
1
ACLK
1
N/A
0
CPU Status Register Bit OSCOFF
N/A
1
0
Internally tied to DVSS
1
(2)
PJ.3/TCK/COUT/
SRCPUOFF
PJ.3 (I/O)
I: 0; O: 1
0
0
(3) (5)
TCK
X
0
1
0
1
0
1
X
X
N/A
0
1
1
1
0
1
COUT
N/A
CPU Status Register Bit CPUOFF
N/A
Internally tied to DVSS
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module. JTAG mode selection is made by the SYS module or by the Spy-Bi-Wire 4-wire
entry sequence. Neither PJSEL1.x and PJSEL0.x nor CEPD.x bits have an effect in these cases.
(4) Do not use this pin as SMCLK output if the TB0OUTH functionality is used on any other pin. Select an alternative SMCLK output pin.
(5) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
100
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MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
6.12 Device Descriptors (TLV)
表 6-34 summarizes the Device IDs. 表 6-35 list the contents of the device descriptor tag-length-value
(TLV) structure.
表 6-34. Device ID
DEVICE ID
DEVICE
PACKAGE
At 01A05h
82h
At 01A04h
5Bh
MSP430FR5970
PM and RGC
PM and RGC
PM and RGC
DGG
MSP430FR5972(1)
82h
5Dh
82h
61h
MSP430FR5922(1)
82h
62h
MSP430FR5870
PM and RGC
PM and RGC
82h
5Eh
MSP430FR5872(1)
82h
60h
(1)
表 6-35. Device Descriptor Table
MSP430FRxxxx (UART BSL)
MSP430FRxxxx1 (I2C BSL)
DESCRIPTION
ADDRESS
01A00h
01A01h
01A02h
01A03h
01A04h
01A05h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Bh
01A0Ch
01A0Dh
01A0Eh
01A0Fh
01A10h
01A11h
01A12h
01A13h
VALUE
06h
ADDRESS
VALUE
06h
Info length
01A00h
01A01h
01A02h
01A03h
01A04h
01A05h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Bh
01A0Ch
01A0Dh
01A0Eh
01A0Fh
01A10h
01A11h
01A12h
01A13h
CRC length
06h
06h
Per unit
Per unit
Per unit
Per unit
CRC value
Info Block
Device ID
Device ID
See 表 6-34.
See 表 6-34.
Hardware revision
Firmware revision
Die record tag
Die record length
Per unit
Per unit
08h
Per unit
Per unit
08h
0Ah
0Ah
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Lot/wafer ID
Die Record
Die X position
Die Y position
Test results
(1) NA = Not applicable, Per unit = content can differ from device to device
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MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
表 6-35. Device Descriptor Table (1) (continued)
MSP430FRxxxx (UART BSL)
MSP430FRxxxx1 (I2C BSL)
DESCRIPTION
ADDRESS
01A14h
01A15h
01A16h
01A17h
01A18h
01A19h
01A1Ah
01A1Bh
01A1Ch
01A1Dh
01A1Eh
01A1Fh
01A20h
01A21h
01A22h
01A23h
01A24h
01A25h
01A26h
01A27h
01A28h
01A29h
01A2Ah
01A2Bh
01A2Ch
01A2Dh
VALUE
11h
ADDRESS
01A14h
01A15h
01A16h
01A17h
01A18h
01A19h
01A1Ah
01A1Bh
01A1Ch
01A1Dh
01A1Eh
01A1Fh
01A20h
01A21h
01A22h
01A23h
01A24h
01A25h
01A26h
01A27h
01A28h
01A29h
01A2Ah
01A2Bh
01A2Ch
01A2Dh
VALUE
11h
ADC12B calibration tag
ADC12B calibration length
10h
10h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
12h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
12h
ADC gain factor(2)
ADC offset(3)
ADC 1.2-V reference
Temperature sensor 30°C
ADC12B
Calibration
ADC 1.2-V reference
Temperature sensor 85°C
ADC 2.0-V reference
Temperature sensor 30°C
ADC 2.0-V reference
Temperature sensor 85°C
ADC 2.5-V reference
Temperature sensor 30°C
ADC 2.5-V reference
Temperature sensor 85°C
REF calibration tag
REF calibration length
06h
06h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
REF 1.2-V reference
REF 2.0-V reference
REF 2.5-V reference
REF Calibration
(2) ADC gain: The gain correction factor is measured using the internal voltage reference with REFOUT = 0. Other settings (for example,
with REFOUT = 1) can result in different correction factors.
(3) ADC offset: The offset correction factor is measured using the internal 2.5-V reference.
102
Detailed Description
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
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ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
表 6-35. Device Descriptor Table (1) (continued)
MSP430FRxxxx (UART BSL)
MSP430FRxxxx1 (I2C BSL)
DESCRIPTION
ADDRESS
01A2Eh
01A2Fh
01A30h
01A31h
01A32h
01A33h
01A34h
01A35h
01A36h
01A37h
01A38h
01A39h
01A3Ah
01A3Bh
01A3Ch
01A3Dh
01A3Eh
01A3Fh
01A40h
01A41h
01A42h
01A43h
VALUE
15h
ADDRESS
01A2Eh
01A2Fh
01A30h
01A31h
01A32h
01A33h
01A34h
01A35h
01A36h
01A37h
01A38h
01A39h
01A3Ah
01A3Bh
01A3Ch
01A3Dh
01A3Eh
01A3Fh
01A40h
01A41h
01A42h
01A43h
VALUE
15h
128-bit random number tag
Random number length
10h
10h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
1Ch
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
1Ch
Random Number
128-bit random number(4)
BSL tag
BSL length
02h
02h
BSL Configuration
BSL interface
00h
01h
BSL interface configuration
00h
48h
(4) 128-bit random number: The random number is generated during production test using the CryptGenRandom() function from Microsoft®.
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
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6.13 Memory
表 6-36 summarizes the memory map for all devices.
表 6-36. Memory Organization(1)
MSP430FR5972(1)
MSP430FR5922(1)
MSP430FR5872(1)
MSP430FR5970
MSP430FR5870
Memory (FRAM)
Main: interrupt vectors and
signatures
Main: code memory
63KB
00FFFFh to 00FF80h
013FFFh to 004400h
32KB
00FFFFh to 00FF80h
00FF7Fh to 008000h
Total Size
Sect 1
2KB
2KB
RAM
0023FFh to 001C00h
0023FFh to 001C00h
Device Descriptor Info (TLV)
(FRAM)
256 bytes
001AFFh to 001A00h
256 bytes
001AFFh to 001A00h
128 bytes
0019FFh to 001980h
128 bytes
0019FFh to 001980h
Info A
Info B
Info C
Info D
BSL 3
BSL 2
BSL 1
BSL 0
Size
128 bytes
00197Fh to 001900h
128 bytes
00197Fh to 001900h
Information memory (FRAM)
128 bytes
0018FFh to 001880h
128 bytes
0018FFh to 001880h
128 bytes
00187Fh to 001800h
128 bytes
00187Fh to 001800h
512 bytes
0017FFh to 001600h
512 bytes
0017FFh to 001600h
512 bytes
0015FFh to 001400h
512 bytes
0015FFh to 001400h
Bootloader (BSL) memory (ROM)
512 bytes
0013FFh to 001200h
512 bytes
0013FFh to 001200h
512 bytes
0011FFh to 001000h
512 bytes
0011FFh to 001000h
4KB
4KB
Peripherals
Tiny RAM
000FFFh to 000020h
000FFFh to 000020h
26 bytes
000001Fh to 000006h
26 bytes
000001Fh to 000006h
Size
Reserved
6 bytes
000005h to 000000h
6 bytes
000005h to 000000h
Size
(Read Only)(2)
(1) All address space not listed is considered vacant memory.
(2) Read as: D032h at 00h (Opcode: BIS.W LPM4, SR), 00F0h at 02h (Opcode: BIS.W LPM4, SR), 3FFFh at 04h (Opcode: JMP$)
104
Detailed Description
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MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
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ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
6.13.1 Peripheral File Map
表 6-37 lists the base address and offset range for the registers of supported peripheral modules.
表 6-37. Peripherals
OFFSET ADDRESS
MODULE NAME
BASE ADDRESS
RANGE
Special Functions (see 表 6-38)
PMM (see 表 6-39)
0100h
0120h
0140h
0150h
0158h
015Ch
0160h
0180h
01B0h
0200h
0220h
0240h
0260h
0280h
0320h
0340h
0380h
03C0h
0400h
0430h
0440h
0470h
04A0h
04C0h
0500h
0510h
0520h
0530h
05A0h
05C0h
05E0h
0640h
0680h
0800h
08C0h
0980h
09C0h
000h to 01Fh
000h to 01Fh
000h to 00Fh
000h to 007h
000h to 001h
000h to 001h
000h to 00Fh
000h to 01Fh
000h to 001h
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 02Fh
000h to 02Fh
000h to 02Fh
000h to 02Fh
000h to 00Fh
000h to 02Fh
000h to 00Fh
000h to 01Fh
000h to 02Fh
000h to 00Fh
000h to 00Fh
000h to 00Fh
000h to 00Fh
000h to 00Fh
000h to 01Fh
000h to 01Fh
000h to 02Fh
000h to 02Fh
000h to 09Fh
000h to 00Fh
000h to 02Fh
000h to 00Fh
FRAM Control (see 表 6-40)
CRC16 (see 表 6-41)
RAM Controller (see 表 6-42)
Watchdog (see 表 6-43)
CS (see 表 6-44)
SYS (see 表 6-45)
Shared Reference (see 表 6-46)
Port P1, P2 (see 表 6-47)
Port P3, P4 (see 表 6-48)
Port P5, P6 (see 表 6-49)
Port P7 (see 表 6-50)
Port P9 (see 表 6-51)
Port PJ (see 表 6-52)
Timer_A TA0 (see 表 6-53)
Timer_A TA1 (see 表 6-54)
Timer_B TB0 (see 表 6-55)
Timer_A TA2 (see 表 6-56)
Capacitive Touch I/O 0 (see 表 6-57)
Timer_A TA3 (see 表 6-58)
Capacitive Touch I/O 1 (see 表 6-59)
Real-Time Clock (RTC_C) (see 表 6-60)
32-Bit Hardware Multiplier (see 表 6-61)
DMA General Control (see 表 6-62)
DMA Channel 0 (see 表 6-62)
DMA Channel 1 (see 表 6-62)
DMA Channel 2 (see 表 6-62)
MPU Control (see 表 6-63)
eUSCI_A0 (see 表 6-64)
eUSCI_A1 (see 表 6-65)
eUSCI_B0 (see 表 6-66)
eUSCI_B1 (see 表 6-67)
ADC12_B (see 表 6-68)
Comparator_E (see 表 6-69)
CRC32 (see 表 6-70)
AES (see 表 6-71)
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
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表 6-38. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
SFRIE1
OFFSET
SFR interrupt enable
SFR interrupt flag
00h
02h
04h
SFRIFG1
SFR reset pin control
SFRRPCR
表 6-39. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
OFFSET
OFFSET
PMM control 0
PMM interrupt flags
PM5 control 0
PMMCTL0
PMMIFG
00h
0Ah
10h
PM5CTL0
表 6-40. FRAM Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
FRCTL0
FRAM control 0
General control 0
General control 1
00h
04h
06h
GCCTL0
GCCTL1
表 6-41. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
CRC data input
CRCDI
00h
02h
04h
06h
CRC data input reverse byte
CRC initialization and result
CRC result reverse byte
CRCDIRB
CRCINIRES
CRCRESR
表 6-42. RAM Controller Registers (Base Address: 0158h)
REGISTER DESCRIPTION
REGISTER
RCCTL0
OFFSET
OFFSET
OFFSET
RAM controller control 0
Watchdog timer control
00h
00h
表 6-43. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
REGISTER
WDTCTL
表 6-44. CS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
CS control 0
CS control 1
CS control 2
CS control 3
CS control 4
CS control 5
CS control 6
CSCTL0
CSCTL1
CSCTL2
CSCTL3
CSCTL4
CSCTL5
CSCTL6
00h
02h
04h
06h
08h
0Ah
0Ch
表 6-45. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
06h
JTAG mailbox control
SYSJMBC
106
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
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ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
表 6-45. SYS Registers (Base Address: 0180h) (continued)
REGISTER DESCRIPTION
REGISTER
SYSJMBI0
OFFSET
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
User NMI vector generator
08h
0Ah
0Ch
0Eh
1Ah
1Ch
1Eh
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSUNIV
System NMI vector generator
Reset vector generator
SYSSNIV
SYSRSTIV
表 6-46. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
REGISTER
REFCTL
OFFSET
OFFSET
Shared reference control
00h
表 6-47. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
Port P1 input
P1IN
00h
02h
04h
06h
0Ah
0Ch
0Eh
16h
18h
1Ah
1Ch
01h
03h
05h
07h
0Bh
0Dh
17h
1Eh
19h
1Bh
1Dh
Port P1 output
P1OUT
P1DIR
P1REN
Port P1 direction
Port P1 resistor enable
Port P1 selection 0
Port P1 selection 1
Port P1 interrupt vector word
P1SEL0
P1SEL1
P1IV
Port P1 complement selection
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
P1SELC
P1IES
P1IE
P1IFG
P2IN
Port P2 output
P2OUT
P2DIR
P2REN
P2SEL0
P2SEL1
P2SELC
P2IV
Port P2 direction
Port P2 resistor enable
Port P2 selection 0
Port P2 selection 1
Port P2 complement selection
Port P2 interrupt vector word
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
P2IES
P2IE
P2IFG
表 6-48. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
02h
04h
06h
0Ah
0Ch
0Eh
Port P3 output
P3OUT
P3DIR
P3REN
Port P3 direction
Port P3 resistor enable
Port P3 selection 0
Port P3 selection 1
Port P3 interrupt vector word
P3SEL0
P3SEL1
P3IV
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MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
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表 6-48. Port P3, P4 Registers (Base Address: 0220h) (continued)
REGISTER DESCRIPTION
Port P3 complement selection
REGISTER
P3SELC
OFFSET
16h
18h
1Ah
1Ch
01h
03h
05h
07h
0Bh
0Dh
17h
1Eh
19h
1Bh
1Dh
Port P3 interrupt edge select
Port P3 interrupt enable
Port P3 interrupt flag
Port P4 input
P3IES
P3IE
P3IFG
P4IN
Port P4 output
P4OUT
P4DIR
P4REN
P4SEL0
P4SEL1
P4SELC
P4IV
Port P4 direction
Port P4 resistor enable
Port P4 selection 0
Port P4 selection 1
Port P4 complement selection
Port P4 interrupt vector word
Port P4 interrupt edge select
Port P4 interrupt enable
Port P4 interrupt flag
P4IES
P4IE
P4IFG
表 6-49. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
02h
04h
06h
0Ah
0Ch
0Eh
16h
18h
1Ah
1Ch
01h
03h
05h
07h
0Bh
0Dh
17h
1Eh
19h
1Bh
1Dh
Port P5 output
Port P5 direction
Port P5 resistor enable
Port P5 selection 0
Port P5 selection 1
Reserved
P5OUT
P5DIR
P5REN
P5SEL0
P5SEL1
Port P5 complement selection
Reserved
P5SELC
Reserved
Reserved
Port P6 input
P6IN
Port P6 output
Port P6 direction
Port P6 resistor enable
Port P6 selection 0
Port P6 selection 1
Port P6 complement selection
Reserved
P6OUT
P6DIR
P6REN
P6SEL0
P6SEL1
P6SELC
Reserved
Reserved
Reserved
表 6-50. Port P7 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 input
P7IN
00h
02h
04h
06h
Port P7 output
P7OUT
P7DIR
P7REN
Port P7 direction
Port P7 resistor enable
108
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
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表 6-50. Port P7 Registers (Base Address: 0260h) (continued)
REGISTER DESCRIPTION
REGISTER
P7SEL0
OFFSET
Port P7 selection 0
Port P7 selection 1
Reserved
0Ah
0Ch
0Eh
16h
18h
1Ah
1Ch
P7SEL1
Port P7 complement selection
Reserved
P7SELC
Reserved
Reserved
表 6-51. Port P9 Registers (Base Address: 0280h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P9 input
P9IN
00h
02h
04h
06h
0Ah
0Ch
0Eh
16h
18h
1Ah
1Ch
Port P9 output
Port P9 direction
Port P9 resistor enable
Port P9 selection 0
Port P9 selection 1
Reserved
P9OUT
P9DIR
P9REN
P9SEL0
P9SEL1
Port P9 complement selection
Reserved
P9SELC
Reserved
Reserved
表 6-52. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
02h
04h
06h
0Ah
0Ch
16h
Port PJ output
PJOUT
PJDIR
PJREN
Port PJ direction
Port PJ resistor enable
Port PJ selection 0
Port PJ selection 1
Port PJ complement selection
PJSEL0
PJSEL1
PJSELC
表 6-53. Timer_A TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
TA0CTL
OFFSET
TA0 control
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA0 counter
TA0CCTL0
TA0CCTL1
TA0CCTL2
TA0R
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA0 expansion 0
TA0CCR0
TA0CCR1
TA0CCR2
TA0EX0
TA0 interrupt vector
TA0IV
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
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表 6-54. Timer_A TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
TA1CTL
OFFSET
TA1 control
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA1 counter
TA1CCTL0
TA1CCTL1
TA1CCTL2
TA1R
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA1 expansion 0
TA1CCR0
TA1CCR1
TA1CCR2
TA1EX0
TA1 interrupt vector
TA1IV
表 6-55. Timer_B TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
TB0CTL
OFFSET
TB0 control
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Capture/compare control 3
Capture/compare control 4
Capture/compare control 5
Capture/compare control 6
TB0 counter
TB0CCTL0
TB0CCTL1
TB0CCTL2
TB0CCTL3
TB0CCTL4
TB0CCTL5
TB0CCTL6
TB0R
Capture/compare 0
TB0CCR0
TB0CCR1
TB0CCR2
TB0CCR3
TB0CCR4
TB0CCR5
TB0CCR6
TB0EX0
Capture/compare 1
Capture/compare 2
Capture/compare 3
Capture/compare 4
Capture/compare 5
Capture/compare 6
TB0 expansion 0
TB0 interrupt vector
TB0IV
表 6-56. Timer_A TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
TA2CTL
OFFSET
TA2 control
00h
02h
04h
10h
12h
14h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
TA2 counter
TA2CCTL0
TA2CCTL1
TA2R
Capture/compare 0
Capture/compare 1
TA2 expansion 0
TA2CCR0
TA2CCR1
TA2EX0
TA2IV
TA2 interrupt vector
表 6-57. Capacitive Touch I/O 0 Registers (Base Address: 0430h)
REGISTER DESCRIPTION
Capacitive touch I/O 0 control
REGISTER
CAPTIO0CTL
OFFSET
0Eh
110
Detailed Description
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MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
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ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
表 6-58. Timer_A TA3 Registers (Base Address: 0440h)
REGISTER DESCRIPTION
REGISTER
TA3CTL
OFFSET
TA3 control
00h
02h
04h
06h
08h
0Ah
10h
12h
14h
16h
18h
1Ah
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Capture/compare control 3
Capture/compare control 4
TA3 counter
TA3CCTL0
TA3CCTL1
TA3CCTL2
TA3CCTL3
TA3CCTL4
TA3R
Capture/compare 0
Capture/compare 1
Capture/compare 2
Capture/compare 3
Capture/compare 4
TA3 expansion 0
TA3CCR0
TA3CCR1
TA3CCR2
TA3CCR3
TA3CCR4
TA3EX0
TA3 interrupt vector
TA3IV
表 6-59. Capacitive Touch I/O 1 Registers (Base Address: 0470h)
REGISTER DESCRIPTION
REGISTER
CAPTIO1CTL
OFFSET
OFFSET
Capacitive touch I/O 1 control
0Eh
表 6-60. RTC_C Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
RTCCTL0
RTC control 0
00h
01h
02h
03h
04h
06h
08h
0Ah
0Ch
0Dh
0Eh
10h
11h
12h
13h
14h
15h
16h
18h
19h
1Ah
1Bh
1Ch
1Eh
RTC password
RTCPWD
RTC control 1
RTCCTL1
RTC control 3
RTCCTL3
RTC offset calibration
RTC temperature compensation
RTC prescaler 0 control
RTC prescaler 1 control
RTC prescaler 0
RTCOCAL
RTCTCMP
RTCPS0CTL
RTCPS1CTL
RTCPS0
RTC prescaler 1
RTCPS1
RTC interrupt vector word
RTC seconds/counter 1
RTC minutes/counter 2
RTC hours/counter 3
RTC day of week/counter 4
RTC days
RTCIV
RTCSEC/RTCNT1
RTCMIN/RTCNT2
RTCHOUR/RTCNT3
RTCDOW/RTCNT4
RTCDAY
RTC month
RTCMON
RTC year
RTCYEAR
RTC alarm minutes
RTC alarm hours
RTCAMIN
RTCAHOUR
RTCADOW
RTCADAY
RTC alarm day of week
RTC alarm days
Binary-to-BCD conversion
BCD-to-binary conversion
BIN2BCD
BCD2BIN
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表 6-61. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
16-bit operand 1 – signed multiply
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
MPYS
MAC
MACS
OP2
16 × 16 result low word
RESLO
RESHI
16 × 16 result high word
16 × 16 sum extension
SUMEXT
MPY32L
MPY32H
MPYS32L
MPYS32H
MAC32L
MAC32H
MACS32L
MACS32H
OP2L
32-bit operand 1 – multiply low word
32-bit operand 1 – multiply high word
32-bit operand 1 – signed multiply low word
32-bit operand 1 – signed multiply high word
32-bit operand 1 – multiply accumulate low word
32-bit operand 1 – multiply accumulate high word
32-bit operand 1 – signed multiply accumulate low word
32-bit operand 1 – signed multiply accumulate high word
32-bit operand 2 – low word
32-bit operand 2 – high word
OP2H
32 × 32 result 0 – least significant word
32 × 32 result 1
RES0
RES1
32 × 32 result 2
RES2
32 × 32 result 3 – most significant word
MPY32 control 0
RES3
MPY32CTL0
表 6-62. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTION
REGISTER
DMA0CTL
OFFSET
DMA channel 0 control
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
DMA channel 0 source address low
DMA channel 0 source address high
DMA channel 0 destination address low
DMA channel 0 destination address high
DMA channel 0 transfer size
DMA0SAL
DMA0SAH
DMA0DAL
DMA0DAH
DMA0SZ
DMA channel 1 control
DMA1CTL
DMA1SAL
DMA1SAH
DMA1DAL
DMA1DAH
DMA1SZ
DMA channel 1 source address low
DMA channel 1 source address high
DMA channel 1 destination address low
DMA channel 1 destination address high
DMA channel 1 transfer size
DMA channel 2 control
DMA2CTL
DMA2SAL
DMA2SAH
DMA2DAL
DMA2DAH
DMA2SZ
DMA channel 2 source address low
DMA channel 2 source address high
DMA channel 2 destination address low
DMA channel 2 destination address high
DMA channel 2 transfer size
DMA module control 0
DMACTL0
DMACTL1
DMA module control 1
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表 6-62. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h) (continued)
REGISTER DESCRIPTION
REGISTER
DMACTL2
OFFSET
DMA module control 2
DMA module control 3
DMA module control 4
DMA interrupt vector
04h
06h
08h
0Eh
DMACTL3
DMACTL4
DMAIV
表 6-63. MPU Control Registers (Base Address: 05A0h)
REGISTER DESCRIPTION
REGISTER
MPUCTL0
OFFSET
MPU control 0
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
MPU control 1
MPUCTL1
MPU Segmentation Border 2
MPU Segmentation Border 1
MPU access management
MPU IP control 0
MPUSEGB2
MPUSEGB1
MPUSAM
MPUIPC0
MPU IP Encapsulation Segment Border 2
MPU IP Encapsulation Segment Border 1
MPUIPSEGB2
MPUIPSEGB1
表 6-64. eUSCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
UCA0CTLW0
OFFSET
eUSCI_A control word 0
eUSCI _A control word 1
eUSCI_A baud rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
UCA0CTLW1
UCA0BR0
eUSCI_A baud rate 1
UCA0BR1
eUSCI_A modulation control
eUSCI_A status word
UCA0MCTLW
UCA0STATW
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
UCA0IRTCTL
UCA0IRRCTL
UCA0IE
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
UCA0IFG
UCA0IV
表 6-65. eUSCI_A1 Registers (Base Address:05E0h)
REGISTER DESCRIPTION
REGISTER
UCA1CTLW0
OFFSET
eUSCI_A control word 0
eUSCI _A control word 1
eUSCI_A baud rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
UCA1CTLW1
UCA1BR0
eUSCI_A baud rate 1
UCA1BR1
eUSCI_A modulation control
eUSCI_A status word
UCA1MCTLW
UCA1STATW
UCA1RXBUF
UCA1TXBUF
UCA1ABCTL
UCA1IRTCTL
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
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表 6-65. eUSCI_A1 Registers (Base Address:05E0h) (continued)
REGISTER DESCRIPTION
eUSCI_A IrDA receive control
REGISTER
UCA1IRRCTL
OFFSET
13h
1Ah
1Ch
1Eh
eUSCI_A interrupt enable
eUSCI_A interrupt flags
UCA1IE
UCA1IFG
UCA1IV
eUSCI_A interrupt vector word
表 6-66. eUSCI_B0 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
UCB0CTLW0
OFFSET
eUSCI_B control word 0
eUSCI_B control word 1
eUSCI_B bit rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Ah
2Ch
2Eh
UCB0CTLW1
UCB0BR0
eUSCI_B bit rate 1
UCB0BR1
eUSCI_B status word
UCB0STATW
UCB0TBCNT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA0
UCB0I2COA1
UCB0I2COA2
UCB0I2COA3
UCB0ADDRX
UCB0ADDMASK
UCB0I2CSA
UCB0IE
eUSCI_B byte counter threshold
eUSCI_B receive buffer
eUSCI_B transmit buffer
eUSCI_B I2C own address 0
eUSCI_B I2C own address 1
eUSCI_B I2C own address 2
eUSCI_B I2C own address 3
eUSCI_B received address
eUSCI_B address mask
eUSCI_B I2C slave address
eUSCI_B interrupt enable
eUSCI_B interrupt flags
eUSCI_B interrupt vector word
UCB0IFG
UCB0IV
表 6-67. eUSCI_B1 Registers (Base Address: 0680h)
REGISTER DESCRIPTION
REGISTER
UCB1CTLW0
OFFSET
eUSCI_B control word 0
eUSCI_B control word 1
eUSCI_B bit rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Ah
2Ch
2Eh
UCB1CTLW1
UCB1BR0
eUSCI_B bit rate 1
UCB1BR1
eUSCI_B status word
UCB1STATW
UCB1TBCNT
UCB1RXBUF
UCB1TXBUF
UCB1I2COA0
UCB1I2COA1
UCB1I2COA2
UCB1I2COA3
UCB1ADDRX
UCB1ADDMASK
UCB1I2CSA
UCB1IE
eUSCI_B byte counter threshold
eUSCI_B receive buffer
eUSCI_B transmit buffer
eUSCI_B I2C own address 0
eUSCI_B I2C own address 1
eUSCI_B I2C own address 2
eUSCI_B I2C own address 3
eUSCI_B received address
eUSCI_B address mask
eUSCI_B I2C slave address
eUSCI_B interrupt enable
eUSCI_B interrupt flags
eUSCI_B interrupt vector word
UCB1IFG
UCB1IV
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MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
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ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
表 6-68. ADC12_B Registers (Base Address: 0800h)
REGISTER DESCRIPTION
REGISTER
ADC12CTL0
OFFSET
ADC12_B control 0
ADC12_B control 1
ADC12_B control 2
ADC12_B control 3
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
36h
38h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
4Eh
50h
52h
54h
56h
58h
5Ah
5Ch
5Eh
60h
62h
ADC12CTL1
ADC12CTL2
ADC12CTL3
ADC12_B window comparator low threshold
ADC12_B window comparator high threshold
ADC12_B interrupt flag 0
ADC12LO
ADC12HI
ADC12IFGR0
ADC12IFGR1
ADC12IFGR2
ADC12IER0
ADC12_B interrupt flag 1
ADC12_B interrupt flag 2
ADC12_B interrupt enable 0
ADC12_B Interrupt Enable 1
ADC12_B interrupt enable 2
ADC12_B interrupt vector
ADC12IER1
ADC12IER2
ADC12IV
ADC12_B memory control 0
ADC12_B memory control 1
ADC12_B memory control 2
ADC12_B memory control 3
ADC12_B memory control 4
ADC12_B memory control 5
ADC12_B memory control 6
ADC12_B memory control 7
ADC12_B memory control 8
ADC12_B memory control 9
ADC12_B memory control 10
ADC12_B memory control 11
ADC12_B memory control 12
ADC12_B memory control 13
ADC12_B memory control 14
ADC12_B memory control 15
ADC12_B memory control 16
ADC12_B memory control 17
ADC12_B memory control 18
ADC12_B memory control 19
ADC12_B memory control 20
ADC12_B memory control 21
ADC12_B memory control 22
ADC12_B memory control 23
ADC12_B memory control 24
ADC12_B memory control 25
ADC12_B memory control 26
ADC12_B memory control 27
ADC12_B memory control 28
ADC12_B memory control 29
ADC12_B memory control 30
ADC12_B memory control 31
ADC12_B memory 0
ADC12MCTL0
ADC12MCTL1
ADC12MCTL2
ADC12MCTL3
ADC12MCTL4
ADC12MCTL5
ADC12MCTL6
ADC12MCTL7
ADC12MCTL8
ADC12MCTL9
ADC12MCTL10
ADC12MCTL11
ADC12MCTL12
ADC12MCTL13
ADC12MCTL14
ADC12MCTL15
ADC12MCTL16
ADC12MCTL17
ADC12MCTL18
ADC12MCTL19
ADC12MCTL20
ADC12MCTL21
ADC12MCTL22
ADC12MCTL23
ADC12MCTL24
ADC12MCTL25
ADC12MCTL26
ADC12MCTL27
ADC12MCTL28
ADC12MCTL29
ADC12MCTL30
ADC12MCTL31
ADC12MEM0
ADC12MEM1
ADC12_B memory 1
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
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表 6-68. ADC12_B Registers (Base Address: 0800h) (continued)
REGISTER DESCRIPTION
REGISTER
ADC12MEM2
OFFSET
ADC12_B memory 2
ADC12_B memory 3
ADC12_B memory 4
ADC12_B memory 5
ADC12_B memory 6
ADC12_B memory 7
ADC12_B memory 8
ADC12_B memory 9
ADC12_B memory 10
ADC12_B memory 11
ADC12_B memory 12
ADC12_B memory 13
ADC12_B memory 14
ADC12_B memory 15
ADC12_B memory 16
ADC12_B memory 17
ADC12_B memory 18
ADC12_B memory 19
ADC12_B memory 20
ADC12_B memory 21
ADC12_B memory 22
ADC12_B memory 23
ADC12_B memory 24
ADC12_B memory 25
ADC12_B memory 26
ADC12_B memory 27
ADC12_B memory 28
ADC12_B memory 29
ADC12_B memory 30
ADC12_B memory 31
64h
66h
68h
6Ah
6Ch
6Eh
70h
72h
74h
76h
78h
7Ah
7Ch
7Eh
80h
82h
84h
86h
88h
8Ah
8Ch
8Eh
90h
92h
94h
96h
98h
9Ah
9Ch
9Eh
ADC12MEM3
ADC12MEM4
ADC12MEM5
ADC12MEM6
ADC12MEM7
ADC12MEM8
ADC12MEM9
ADC12MEM10
ADC12MEM11
ADC12MEM12
ADC12MEM13
ADC12MEM14
ADC12MEM15
ADC12MEM16
ADC12MEM17
ADC12MEM18
ADC12MEM19
ADC12MEM20
ADC12MEM21
ADC12MEM22
ADC12MEM23
ADC12MEM24
ADC12MEM25
ADC12MEM26
ADC12MEM27
ADC12MEM28
ADC12MEM29
ADC12MEM30
ADC12MEM31
表 6-69. Comparator_E Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
CECTL0
OFFSET
Comparator control 0
Comparator control 1
Comparator control 2
Comparator control 3
Comparator interrupt
00h
02h
04h
06h
0Ch
0Eh
CECTL1
CECTL2
CECTL3
CEINT
Comparator interrupt vector word
CEIV
表 6-70. CRC32 Registers (Base Address: 0980h)
REGISTER DESCRIPTION
REGISTER
CRC32DIW0
OFFSET
CRC32 data input
00h
02h
04h
06h
08h
Reserved
Reserved
CRC32 data input reverse
CRC32 initialization and result word 0
CRC32DIRBW0
CRC32INIRESW0
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
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ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
表 6-70. CRC32 Registers (Base Address: 0980h) (continued)
REGISTER DESCRIPTION
REGISTER
CRC32INIRESW1
CRC32RESRW1
CRC32RESRW1
CRC16DIW0
OFFSET
CRC32 initialization and result word 1
CRC32 result reverse word 1
CRC32 result reverse word 0
CRC16 data input
Reserved
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
Reserved
CRC16 data input reverse
CRC16 initialization and result word 0
Reserved
CRC16DIRBW0
CRC16INIRESW0
Reserved
CRC16 result reverse word 0
Reserved
CRC16RESRW1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
表 6-71. AES Accelerator Registers (Base Address: 09C0h)
REGISTER DESCRIPTION
REGISTER
AESACTL0
OFFSET
AES accelerator control 0
Reserved
00h
02h
AES accelerator status
AES accelerator key
AES accelerator data in
AES accelerator data out
AESASTAT
AESAKEY
AESADIN
04h
06h
008h
00Ah
00Ch
00Eh
AESADOUT
AESAXDIN
AESAXIN
AES accelerator XORed data in
AES accelerator XORed data in (no trigger)
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
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6.14 Identification
6.14.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings. For links to the errata sheets for the devices in this
data sheet, see 节 8.4.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Hardware Revision" entries in 节 6.12.
6.14.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings. For links to the errata sheets for the devices in this data sheet, see
节 8.4.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Device ID" entries in 节 6.12.
6.14.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
detail in MSP430 Programming With the JTAG Interface.
118
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MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
7 Applications, Implementation, and Layout
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7.1 Device Connection and Layout Fundamentals
This section describes the recommended guidelines when designing with the MSP430. These guidelines
are to make sure that the device has proper connections for powering, programming, debugging, and
optimum analog performance.
7.1.1 Power Supply Decoupling and Bulk Capacitors
TI recommends connecting a combination of a 1-µF plus a 100-nF low-ESR ceramic decoupling capacitor
to each AVCC and DVCC pin. Higher-value capacitors may be used but can impact supply rail ramp-up
time. Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a
few millimeters). Additionally, TI recommends separated grounds with a single-point connection for better
noise isolation from digital to analog circuits on the board and to achieve high analog accuracy.
DVCC
Digital
Power Supply
Decoupling
+
1 µF
100 nF
100 nF
DVSS
AVCC
Analog
Power Supply
Decoupling
+
1 µF
AVSS
图 7-1. Power Supply Decoupling
7.1.2 External Oscillator
Depending on the device variant (see Section 3), the device can support a low-frequency crystal (32 kHz)
on the LFXT pins, a high-frequency crystal on the HFXT pins, or both. External bypass capacitors for the
crystal oscillator pins are required.
It is also possible to apply digital clock signals to the LFXIN and HFXIN input pins that meet the
specifications of the respective oscillator if the appropriate LFXTBYPASS or HFXTBYPASS mode is
selected. In this case, the associated LFXOUT and HFXOUT pins can be used for other purposes. If they
are left unused, they must be terminated according to Section 4.6.
图 7-2 shows a typical connection diagram.
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LFXIN
or
LFXOUT
or
HFXIN
HFXOUT
CL1
CL2
图 7-2. Typical Crystal Connection
See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal
oscillator with the MSP430 devices.
7.1.3 JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or
MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the
connections also support the MSP-GANG production programmers, thus providing an easy way to
program prototype boards, if desired. 图 7-3 shows the connections between the 14-pin JTAG connector
and the target device required to support in-system programming and debugging for 4-wire JTAG
communication. 图 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are
identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSP-
FET430UIF interface modules and MSP-GANG have a VCC-sense feature that, if used, requires an
alternate connection (pin 4 instead of pin 2). The VCC-sense feature senses the local VCC present on the
target board (that is, a battery or other local power supply) and adjusts the output signals accordingly. 图
7-3 and 图 7-4 show a jumper block that supports both scenarios of supplying VCC to the target board. If
this flexibility is not required, the desired VCC connections may be hard-wired to eliminate the jumper
block. Pins 2 and 4 must not be connected at the same time.
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User's
Guide.
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MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
J2 (see Note A)
AVCC/DVCC
R1
47 kW
JTAG
RST/NMI/SBWTDIO
VCC TOOL
TDO/TDI
TDO/TDI
TDI
2
1
3
VCC TARGET
TDI
4
TMS
TCK
TMS
6
5
TEST
8
7
TCK
GND
RST
10
12
14
9
11
13
TEST/SBWTCK
AVSS/DVSS
C1
2.2 nF
(see Note B)
Copyright © 2016, Texas Instruments Incorporated
A. If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,
make connection J2.
B. The upper limit for C1 is 2.2 nF when using current TI tools.
图 7-3. Signal Connections for 4-Wire JTAG Communication
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MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
J2 (see Note A)
AVCC/DVCC
R1
47 kΩ
(See Note B)
JTAG
VCC TOOL
TDO/TDI
2
1
3
5
7
9
RST/NMI/SBWTDIO
VCC TARGET
4
6
TCK
GND
8
10
12
14
11
13
TEST/SBWTCK
AVSS/DVSS
C1
2.2 nF
(See Note B)
Copyright © 2016, Texas Instruments Incorporated
A. Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the
debug or programming adapter.
B. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with
the device. The upper limit for C1 is 2.2 nF when using current TI tools.
图 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
7.1.4 Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the special function
register (SFR) SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is
edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the
external NMI. When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either
pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.
If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an
external 47-kΩ pullup resistor to the RST/NMI pin with a 10-nF pulldown capacitor. The pulldown capacitor
should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire
JTAG mode with TI tools like FET interfaces or GANG programmers.
See the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for more information
on the referenced control registers and bits.
7.1.5 Unused Pins
For details on the connection of unused pins, see Section 4.6.
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MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
7.1.6 General Layout Recommendations
•
Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430
32-kHz Crystal Oscillators for recommended layout guidelines.
•
•
Proper bypass capacitors on DVCC, AVCC, and reference pins if used.
Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital
switching signals such as PWM or JTAG signals away from the oscillator circuit.
•
Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See MSP430 System-Level ESD Considerations for guidelines.
7.1.7 Do's and Don'ts
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up,
power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the
limits specified in Section 5.1. Exceeding the specified limits may cause malfunction of the device
including erroneous writes to RAM and FRAM.
7.2 Peripheral- and Interface-Specific Design Information
7.2.1 ADC12_B Peripheral
7.2.1.1 Partial Schematic
图 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The
internal reference module has a maximum drive current as specified in the IO(VREF+) specification of the
REF module.
AVSS
VREF+/VEREF+
Using an
External
Positive
Reference
+
470 nF
10 µF
VEREF-
Using an
External
+
Negative
Reference
10 µF
470 nF
图 7-5. ADC12_B Grounding and Noise Considerations
7.2.1.2 Design Requirements
As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should
be followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with
other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset
voltages that can add to or subtract from the reference or input voltages of the ADC. The general
guidelines in 节 7.1.1 combined with the connections shown in 节 7.2.1.1 prevent this.
In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital
switching or switching power supplies can corrupt the conversion result. TI recommends a noise-free
design using separate analog and digital ground planes with a single-point connection to achieve high
accuracy.
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MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are
selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage
enters the device. In this case, the 10-µF capacitor is used to buffer the reference pin and filter any low-
frequency ripple. A 470-nF bypass capacitor is used to filter out any high-frequency noise.
7.2.1.3 Detailed Design Procedure
For additional design information, see Designing With the MSP430FR58xx, FR59xx, FR68xx, and FR69xx
ADC.
7.2.1.4 Layout Guidelines
Components that are shown in the partial schematic (see 图 7-5) should be placed as close as possible to
the respective device pins. Avoid long traces, because they add additional parasitic capacitance,
inductance, and resistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),
because the high-frequency switching can be coupled into the analog signal.
If differential mode is used for the ADC12_B, the analog differential input signals must be routed close
together to minimize the effect of noise on the resulting signal.
124
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MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
8 器件和文档支持
8.1 入门和后续步骤
要获得有助于您开发工作的 MSP430™系列器件、工具和库相关信息，请访问入门页面。
8.2 器件命名规则
为了标示产品开发周期所处的阶段，TI 为所有 MSP MCU 器件的部件号分配了前缀。每个 MSP MCU 商用
系列产品成员都具有以下两个前缀之一：MSP 或 XMS。这些前缀代表了产品开发的发展阶段，即从工程原
型 (XMS) 直到完全合格的生产器件 (MSP)。
XMS - 实验器件，不一定代表最终器件的电气规格
MSP - 完全合格的生产器件
XMS 器件在供货时附带如下免责声明：
“开发中的产品用于内部评估用途。”
MSP 器件的特性已经全部明确，并且器件的质量和可靠性已经完全论证。TI 的标准保修证书对该器件适
用。
预测显示原型器件 (XMS) 的故障率大于标准生产器件。由于这些器件的预计最终使用故障率尚不确定，德
州仪器 (TI) 建议不要将它们用于任何生产系统。请仅使用合格的生产器件。
TI 器件的命名规则还包括一个带有器件系列名称的后缀。此后缀表示温度范围、封装类型和配送形式。图 8-
1 提供了解读完整器件名称的图例。
MSP 430 FR
5
9721
I
RGC
R
Feature Set
Processor Family
Distribution Format
Packaging
MCU Platform
Memory Type
Temperature Range
Series
AES
Optional: BSL
FRAM
Oscillators
Processor Family
MSP = Mixed Signal Processor
XMS = Experimental Silicon
MCU Platform
Memory Type
Series
430 = TI’s 16-bit MSP430 Low-Power Microcontroller Platform
FR = FRAM
5 = FRAM 5 Series up to 16 MHz without LCD
Feature Set
AES
9 = AES
8 = No AES 2 = LFXT
Oscillators
7 = HFXT and LFXT 2 = 64
0 = 32
FRAM (KB) Optional: BSL
1 = I2C
No value = UART
Temperature Range I = –40°C to 85°C
Packaging
http://www.ti.com/packaging
Distribution Format T = Small reel
R = Large reel
No markings = Tube or tray
图 8-1. 器件命名规则
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产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
8.3 工具与软件
所有 MSP 微控制器均受多种软件和硬件开发工具的支持。相关工具由 TI 以及多家第三方供应商提供。可从
低功耗 MCU 开发套件和软件获取全部信息。
表 8-1 列出了 MSP430FR235x 和 MSP430FR215x 微控制器所 了 MSP430FR597x(1)、MSP430FR592x
(1) 和 MSP430FR587x(1) MCU 的调试特性。关于可用特性的详细信息，请参见《适用于 MSP430 的 Code
Composer Studio 用户指南 》。
表 8-1. 硬件调试 特性
四线制
JTAG
两线制
JTAG
状态序列发生
器
LPMx.5 调试支 EnergyTrace++
MSP430 架构
断点
范围断点
有
时钟控制
是
跟踪缓冲器
否
持
技术
MSP430Xv2
有
有
3
否
有
有
设计套件与评估模块
MSP430FR6989 LaunchPad 开发套件
MSP-EXP430FR6989
LaunchPad
开发套件是适用于
MSP40FR6989 微控制器 (MCU) 的易用型评估模块 (EVM)。它包含在超低功耗 MSP430FRx
FRAM 微控制器平台上进行开发所需的全部资源，包括一个用于编程、调试和能量测量的板载
仿真。
MSP-TS430PM64F - MSP430 64 引脚 FRAM 目标插接板 MSP-TS430PZ5X100 是独立的 ZIF 插接目标
板，用于通过 JTAG 接口或 Spy-Bi-Wire（双线制 JTAG）协议对 MSP430 MCU 进行在线编
程和调试。
MSP-FET430U64F - MSP430 64 引脚 FRAM TS 板和 MSP-FET 包 MSP-FET430U64F 包由 MSP-FET
仿真器和一款独立的 64 引脚 ZIF 插接目标板，适用于通过 JTAG 接口或 Spy-Bi-Wire（双线
制 JTAG）协议对 MSP430 MCU 系统进行在线编程和调试。该 TS 开发板支持采用 64 引脚
LQFP 封装（TI 封装代码：PM）的 MSP430FR6972 FRAM 器件。
软件
MSP430Ware™ 软件 MSP430Ware 软件集合了所有 MSP430 器件的代码示例、数据表以及其他设计资
源，打包提供给用户。除了提供已有 MSP430 MCU 设计资源的完整集合外，MSP430Ware
软件还包含名为 MSP 驱动程序库的高级 API。借助该库可以轻松地对 MSP430 硬件进行编
程。MSP430Ware 软件以 CCS 组件或独立软件包两种形式提供。
MSP430FR592x、MSP430FR5x7x、MSP430FR6x2x、MSP430FR6x7x 代码示例
置各集成外设的每个 MSP 器件均具备相应的 C 代码示例。
根据不同应用需求配
电容式触摸软件库 可在 MSP430 MCU 启用电容触控功能的免费 C 代码库。MSP430 MCU 库版本 采用 多
种电容触控实现方法，包括 RO 和 RC 方法。
MSP 驱动程序库 MSP 驱动程序库的抽象 API 提供易用的函数调用，无需直接操纵 MSP430 硬件的位与字
节。完整的文档通过具有帮助意义的 API 指南交付，其中包括有关每个函数调用和经过验证的
参数的详细信息。开发人员可使用驱动程序库函数以尽可能低的费用编写全部项目。
MSP EnergyTrace™ 技术 适用于 MSP430 微控制器的 EnergyTrace 技术是基于电能的代码分析工具，适
用于测量和显示应用的电能系统配置并帮助优化应用以实现超低功耗。
ULP（超低功耗）Advisor ULP Advisor™软件是一款辅助工具，旨在指导开发人员编写更为高效的代码，
从而充分利用 MSP430 和 MSP432 微控制器 独特 功能。ULP Advisor 的目标人群是微控制器
的资深开发者和开发新手，可以根据详尽的 ULP 检验表检查代码，以便最大限度地减少应用
程序的能耗。在编译时，ULP Advisor 提供通知和备注，以标识代码中可以进一步优化的区
域，进而实现更低功耗。
126
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产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
IEC60730 软件包 IEC60730 MSP430 软件包经过专门开发，用于协助客户达到 IEC 60730-1:2010（家用
及类似用途的自动化电气控制 - 第 1 部分：一般要求）B 类产品的要求。其中涵盖家用电器、
电弧检测器、电源转换器、电动工具、电动自行车及其他诸多产品。IEC60730 MSP430 软件
包可以嵌入在 MSP430 MCU 中 运行的客户应用， 从而帮助客户简化其消费类器件在功能安
全方面遵循 IEC 60730-1:2010 B 类规范的认证工作。
适用于 MSP 的定点数学运算库 MSP IQmath 和 Qmath 库是为 C 语言开发者提供的一套经过高度优化的
高精度数学运算函数集合，能够将浮点算法无缝嵌入 MSP430 和 MSP432 器件的定点代码
中。这些例程通常用于计算密集型实时 应用， 而优化的执行速度、高精度以及超低能耗通常
是影响这些实时应用的关键因素。与使用浮点数学算法编写的同等代码相比，使用 IQmath 和
Qmath 库可以大幅提高执行速度并显著降低能耗。
适用于 MSP430 的浮点数学运算库
TI
在低功耗和低成本微控制器领域锐意创新，为您提供
MSPMATHLIB。这是标量函数的浮点数学运算库，能够充分利用 MSP 器件的智能外设，其速
度最高可为标准 MSP430 数学函数的 26 倍。Mathlib 能够轻松集成到您的设计中。该运算库
免费使用并集成在 Code Composer Studio IDE 和 IAR Embedded Workbench IDE 中。
开发工具
适用于 MSP 微控制器的 Code Composer Studio™ 集成开发环境 Code Composer Studio (CCS) 集成开
发环境 (IDE) 支持所有 MSP 微控制器器件。CCS 包含一整套用于开发和调试嵌入式 应用的
嵌入式软件实用程序。CCS 包含了优化的 C/C++ 编译器、源代码编辑器、项目构建环境、调
试器、描述器以及其他众多 功能。
命令行编程器 MSP Flasher 是一款基于 shell 的开源接口，可使用 JTAG 或 Spy-Bi-Wire (SBW) 通信通过
FET 编程器或 eZ430 对 MSP 微控制器进行编程。MSP Flasher 可用于将二进制文件（.txt 或
.hex 文件）直接下载到 MSP 微控制器，而无需使用 IDE。
MSP MCU 编程器和调试器 MSP-FET 是一款强大的仿真开发工具（通常称为调试探针），可帮助用户在
MSP 低功耗微控制器 (MCU) 中快速开发应用。创建 MCU 软件通常需要将生成的二进制程序
下载到 MSP 器件中，从而进行验证和调试。
MSP-GANG 生产编程器 MSP Gang 编程器是一款 MSP430 或 MSP432 器件编程器，可同时对多达八个
完全相同的 MSP430 或 MSP432 闪存或 FRAM 器件进行编程。MSP Gang 编程器可使用标
准的 RS-232 或 USB 连接与主机 PC 相连并提供灵活的编程选项，允许用户完全自定义流
程。
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127
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产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
8.4 文档支持
以下文档介绍了 MSP430FR597x(1)、MSP430FR592x(1) 和 MSP430FR587x(1) MCU。www.ti.com.cn 网
站上提供了这些文档的副本。
接收文档更新通知
要接收文档更新通知（包括芯片勘误表），请转至 ti.com.cn 上您的器件对应的产品文件夹（关于产品文件
夹的链接，请参见节 8.5）。请单击右上角的“通知我”按钮。点击注册后，即可收到产品信息更改每周摘要
（如有）。有关更改的详细信息，请查阅已修订文档的修订历史记录。
勘误
《MSP430FR5972 器件勘误表》 描述了功能技术规格的已知例外情况。
《MSP430FR59721 器件勘误表》 描述了功能技术规格的已知例外情况。
《MSP430FR5922 器件勘误表》 描述了功能技术规格的已知例外情况。
《MSP430FR59221 器件勘误表》 描述了功能技术规格的已知例外情况。
《MSP430FR5970 器件勘误表》 描述了功能技术规格的已知例外情况。
《MSP430FR5872 器件勘误表》 描述了功能技术规格的已知例外情况。
《MSP430FR58721 器件勘误表》 描述了功能技术规格的已知例外情况。
《MSP430FR5870 器件勘误表》 描述了功能技术规格的已知例外情况。
用户指南
《MSP430FR58xx、MSP430FR59xx 和 MSP430FR6xx 系列用户指南》 详细介绍了该器件系列提供的模
块和外设。
《MSP430 FRAM 器件引导加载程序 (BSL) 用户指南》 MSP430 MCU 上的引导加载程序 (BSL) 允许用户
在原型设计、投产和维护等各阶段与 MSP430 MCU 中的嵌入式存储器进行通信。可编程存储
器（FRAM 存储器）和数据存储器 (RAM) 均可按要求予以修改。
《通过 JTAG 接口对 MSP430 进行编程》 此文档介绍了使用 JTAG 通信端口擦除、编程和验证基于
MSP430 闪存和 FRAM 的微控制器系列的存储器模块所需的功能。此外，该文档还介绍了如
何编程所有 MSP430 器件上均具备的 JTAG 访问安全保险丝。此文档介绍了使用标准四线制
JTAG 接口和两线制 JTAG 接口（也称为 Spy-Bi-Wire (SBW)）的器件访问。
《MSP430 硬件工具用户指南》 此手册介绍了 TI MSP-FET430 闪存仿真工具 (FET) 的硬件。FET 是针对
MSP430
超低功耗微控制器的程序开发工具。文中对提供的接口类型，即并行端口接口和
USB 接口进行了说明。
应用报告
《MSP-EXP430FR5969 中的 EEMBC ULPBench 入门》 本入门指南旨在介绍获取 ULPMark™-CP评分
的相关内容，具体方式是将嵌入式微处理器基准协会 (EEMBC) ULPBench™和
EnergyMonitor MSP430FR5969 微控制器 (MCU) 搭配使用。本文档使用 MSP-
与
EXP430FR5969 LaunchPad 开发套件作为执行基准测试的目标评估模块 (EVM)。ULPBench
是一种 EEMBC 基准，提供了测量 MCU 超低功耗性能的行业标准方法。
128
器件和文档支持
版权 © 2015–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
《MSP430 FRAM 技术 – 指南及最佳实践》 FRAM 是一种非易失性存储器技术， 其运行方式类与 SRAM
类似，支持众多新型应用程序，同时改变了固件设计方式。本应用报告从嵌入式软件开发角度
概述了在 MSP430 中使用 FRAM 技术的方法和最佳实践。其中讨论了如何根据应用特定的代
码、常量和数据空间要求来实施存储器布局，如何使用 FRAM 来优化应用程序能耗以及如何
使用存储器保护单元 (MPU) 为程序代码提供意外写访问保护，从而最大程度提高应用的稳健
性。
《MSP430 32kHz 晶体振荡器》 对于稳定的晶体振荡器，选择合适的晶振、正确的负载电路和适当的电路
板布局布线至关重要。该应用报告总结了晶体振荡器的功能，介绍了用于选择合适的晶体以实
现 MSP430 超低功耗运行的参数。此外，还给出了正确电路板布局的提示和示例。此外，为
了确保振荡器在大规模生产后能够稳定运行，还可能需要进行一些振荡器测试，该文档中提供
了有关这些测试的详细信息。
《MSP430 系统级 ESD 注意事项》
随着硅晶技术向更低电压方向发展以及设计具有成本效益的超低功耗
组件的需求的出现，系统级 ESD 要求变得越来越苛刻。该应用报告介绍了三个不同的 ESD 主
题，旨在帮助电路板设计人员和 OEM 理解并设计出稳健耐用的系统级设计。
8.5 相关链接
表 8-2 列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品
的快速链接。
表 8-2. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
MSP430FR5972
MSP430FR59721
MSP430FR5970
MSP430FR5922
MSP430FR59221
MSP430FR5872
MSP430FR58721
MSP430FR5870
8.6 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术
规范，并且不一定反映 TI 的观点；请参见 TI 的 《使用条款》。
TI E2E™ 社区
TI 的工程师交流 (E2E) 社区. 此社区的创建目的是为了促进工程师之间协作。在 e2e.ti.com 中，您可以提
问、共享知识、拓展思路，在同领域工程师的帮助下解决问题。
TI 嵌入式处理器维基网页
德州仪器 (TI) 嵌入式处理器维基网页。此网站的建立是为了帮助开发人员熟悉德州仪器 (TI) 的嵌入式处理
器，并且也为了促进与这些器件相关的硬件和软件的总体知识的创新和增长。
版权 © 2015–2018, Texas Instruments Incorporated
器件和文档支持
129
提交文档反馈意见
产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
www.ti.com.cn
8.7 商标
EnergyTrace++, MSP430, MSP430Ware, EnergyTrace, ULP Advisor, 适用于 MSP 微控制器的 Code
Composer Studio, E2E are trademarks of Texas Instruments.
ULPMark, ULPBench are trademarks of Embedded Microprocessor Benchmark Consortium.
Microsoft is a registered trademark of Microsoft Corporation.
All other trademarks are the property of their respective owners.
8.8 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
8.9 出口管制提示
接收方同意：如果美国或其他适用法律限制或禁止将通过非披露义务的披露方获得的任何产品或技术数据
（其中包括软件）（见美国、欧盟和其他出口管理条例之定义）、或者其他适用国家条例限制的任何受管制
产品或此项技术的任何直接产品出口或再出口至任何目的地，那么在没有事先获得美国商务部和其他相关政
府机构授权的情况下，接收方不得在知情的情况下，以直接或间接的方式将其出口。
8.10 术语表
TI 术语表
这份术语表列出并解释术语、缩写和定义。
130
器件和文档支持
版权 © 2015–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com.cn
ZHCSET8C –APRIL 2015–REVISED AUGUST 2018
9 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通
知，且不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015–2018, Texas Instruments Incorporated
机械、封装和可订购信息
131
提交文档反馈意见
产品主页链接: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430FR5870IPMR
MSP430FR5870IRGCR
MSP430FR58721IPMR
MSP430FR58721IRGCR
MSP430FR5872IPMR
MSP430FR5872IRGCR
MSP430FR59221IG56R
MSP430FR59221IPMR
MSP430FR59221IRGCR
MSP430FR5922IG56R
MSP430FR5922IPM
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
VQFN
LQFP
VQFN
LQFP
VQFN
TSSOP
LQFP
VQFN
TSSOP
LQFP
LQFP
VQFN
LQFP
VQFN
LQFP
LQFP
VQFN
LQFP
LQFP
PM
RGC
PM
64
64
64
64
64
64
56
64
64
56
64
64
64
64
64
64
64
64
64
64
1000 RoHS & Green
2000 RoHS & Green
1000 RoHS & Green
2000 RoHS & Green
1000 RoHS & Green
2000 RoHS & Green
2000 RoHS & Green
1000 RoHS & Green
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
FR5870
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
FR5870
FR58721
FR58721
FR5872
FR5872
FR59221
FR59221
FR59221
FR5922
FR5922
FR5922
FR5922
FR5970
FR5970
FR59721
FR59721
FR59721
FR5972
FR5972
RGC
PM
RGC
DGG
PM
RGC
DGG
PM
160
RoHS & Green
MSP430FR5922IPMR
MSP430FR5922IRGCR
MSP430FR5970IPMR
MSP430FR5970IRGCR
MSP430FR59721IPM
MSP430FR59721IPMR
MSP430FR59721IRGCR
MSP430FR5972IPM
PM
1000 RoHS & Green
2000 RoHS & Green
1000 RoHS & Green
2000 RoHS & Green
RGC
PM
RGC
PM
160
RoHS & Green
PM
1000 RoHS & Green
2000 RoHS & Green
RGC
PM
160
RoHS & Green
MSP430FR5972IPMR
PM
1000 RoHS & Green
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2023
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430FR5972IRGCR
ACTIVE
VQFN
RGC
64
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
FR5972
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430FR5870IPMR
MSP430FR58721IPMR
MSP430FR5872IPMR
LQFP
LQFP
LQFP
PM
PM
64
64
64
56
56
64
64
64
64
1000
1000
1000
2000
2000
1000
1000
1000
1000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
24.4
24.4
24.4
24.4
24.4
24.4
24.4
24.4
24.4
13.0
13.0
13.0
8.6
13.0
13.0
13.0
15.6
15.6
13.0
13.0
13.0
13.0
2.1
2.1
2.1
1.8
1.8
2.1
2.1
2.1
2.1
16.0
16.0
16.0
12.0
12.0
16.0
16.0
16.0
16.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
Q2
Q2
Q2
Q1
Q1
Q2
Q2
Q2
Q2
PM
MSP430FR59221IG56R TSSOP
MSP430FR5922IG56R TSSOP
DGG
DGG
PM
8.6
MSP430FR5922IPMR
MSP430FR5970IPMR
MSP430FR59721IPMR
MSP430FR5972IPMR
LQFP
LQFP
LQFP
LQFP
13.0
13.0
13.0
13.0
PM
PM
PM
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430FR5870IPMR
MSP430FR58721IPMR
MSP430FR5872IPMR
MSP430FR59221IG56R
MSP430FR5922IG56R
MSP430FR5922IPMR
MSP430FR5970IPMR
MSP430FR59721IPMR
MSP430FR5972IPMR
LQFP
LQFP
LQFP
TSSOP
TSSOP
LQFP
LQFP
LQFP
LQFP
PM
PM
64
64
64
56
56
64
64
64
64
1000
1000
1000
2000
2000
1000
1000
1000
1000
336.6
336.6
336.6
350.0
350.0
336.6
336.6
336.6
336.6
336.6
336.6
336.6
350.0
350.0
336.6
336.6
336.6
336.6
41.3
41.3
41.3
43.0
43.0
41.3
41.3
41.3
41.3
PM
DGG
DGG
PM
PM
PM
PM
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
MSP430FR5922IPM
PM
LQFP
64
160
8 X 20
150
315 135.9 7620 15.2
13.1
13
Pack Materials-Page 3
PACKAGE OUTLINE
DGG0056A
TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
2
0
0
SMALL OUTLINE PACKAGE
C
8.3
7.9
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
54X 0.5
56
1
14.1
13.9
NOTE 3
2X
13.5
28
B
29
0.27
0.17
6.2
6.0
56X
1.2 MAX
0.08
C A
B
(0.15) TYP
0.25
GAGE PLANE
0 - 8
SEE DETAIL A
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4222167/A 07/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05)
TYP
SYMM
28
29
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222167/A 07/2015
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05) TYP
SYMM
28
29
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4222167/A 07/2015
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PM0064A
LQFP - 1.6 mm max height
SCALE 1.400
PLASTIC QUAD FLATPACK
10.2
9.8
B
NOTE 3
64
49
PIN 1 ID
1
48
10.2
9.8
12.2
TYP
11.8
NOTE 3
33
16
32
17
A
0.27
0.17
64X
60X 0.5
4X 7.5
0.08
C A B
C
(0.13) TYP
SEATING PLANE
0.08
SEE DETAIL A
0.25
GAGE PLANE
(1.4)
1.6 MAX
0.05 MIN
0.75
0.45
0 -7
DETAIL
SCALE: 14
A
DETAIL A
TYPICAL
4215162/A 03/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MS-026.
www.ti.com
EXAMPLE BOARD LAYOUT
PM0064A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
49
64
64X (1.5)
1
48
64X (0.3)
SYMM
(11.4)
60X (0.5)
(R0.05) TYP
33
16
17
32
(11.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
0.05 MAX
ALL AROUND
EXPOSED METAL
METAL
0.05 MIN
ALL AROUND
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4215162/A 03/2017
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).
www.ti.com
EXAMPLE STENCIL DESIGN
PM0064A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
64
49
64X (1.5)
1
48
64X (0.3)
SYMM
(11.4)
60X (0.5)
(R0.05) TYP
16
33
17
32
(11.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:8X
4215162/A 03/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RGC 64
9 x 9, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224597/A
www.ti.com
PACKAGE OUTLINE
RGC0064B
VQFN - 1 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
9.15
8.85
A
B
PIN 1 INDEX AREA
9.15
8.85
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2X 7.5
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
17
32
16
33
65
SYMM
2X 7.5
4.25 0.1
60X
0.5
1
48
0.30
0.18
64X
49
64
PIN 1 ID
0.1
C A B
0.5
0.3
64X
0.05
4219010/A 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGC0064B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.25)
SEE SOLDER MASK
DETAIL
SYMM
64X (0.6)
49
64
64X (0.24)
1
48
60X (0.5)
(R0.05) TYP
(1.18) TYP
(8.8)
65
SYMM
(0.695) TYP
(
0.2) TYP
VIA
33
16
32
17
(0.695) TYP
(1.18) TYP
(8.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219010/A 10/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGC0064B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
64X (0.6)
64
49
64X (0.24)
1
48
60X (0.5)
(R0.05) TYP
9X ( 1.19)
65
SYMM
(8.8)
(1.39)
33
16
17
32
(1.39)
(8.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 65
71% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219010/A 10/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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