MSP430FR5994IZVWR [TI]
具有 256KB FRAM、8KB SRAM、LEA、AES、12 位 ADC、比较器、DMA、UART/SPI/I2C 和计时器的 16MHz MCU | ZVW | 87 | -40 to 85;
| 型号： | MSP430FR5994IZVWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 256KB FRAM、8KB SRAM、LEA、AES、12 位 ADC、比较器、DMA、UART/SPI/I2C 和计时器的 16MHz MCU | ZVW | 87 | -40 to 85 静态存储器 比较器 |
| 文件： | 总175页 (文件大小：3487K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Reference
Design
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
MSP430FR599x、MSP430FR596x 混合信号微控制器
1 器件概述
1.1 特性
1
• 嵌入式微控制器
• 多功能输入/输出端口
– 高达 16MHz 时钟频率的 16 位 RISC 架构
– 高达 256KB 的铁电随机存取存储器 (FRAM)
– 超低功耗写入
– 所有引脚支持电容触控功能，无需使用外部组件
– 可每位、每字节和每字访问（成对访问）
– 所有端口上，从 LPM 中的边沿可选唤醒
– 所有端口上可编程上拉和下拉
– 125ns 每个字的快速写入（4ms 内写入
64KB）
• 代码安全性和加密
– 灵活分配存储器中的数据和应用程序代码
– 1015 写入周期持久性
– 128 位或 256 位高级加密标准 (AES) 安全加密和
解密协处理器
– 抗辐射和非磁性
– 3.6V 至 1.8V 的宽电源电压范围（最低电源电压
受限于 SVS 电平，请参阅 SVS 规格）
– 针对随机数生成算法的随机数种子
– IP 封装防止对存储器进行外部访问
• 增强型串行通信
• 经优化的超低功耗模式
– 多达四个 eUSCI_A 串行通信端口
– 工作模式：118μA/MHz
– 支持自动波特率侦测的通用异步收发器
– 待机模式下的 VLO (LPM3)：500nA
(UART)
– 待机模式下的实时时钟 (RTC) (LPM3.5)：350nA
– IrDA 编码和解码
(1)
– 多达四个 eUSCI_B 串行通信端口
– 支持多从设备寻址的 I2C
– 关断电流 (LPM4.5)：45nA
• 针对信号处理的低功耗加速器 (LEA)（仅限
MSP430FR599x）
– 硬件通用异步收发器 (UART) 或 I2C 自举程序
(BSL)
• 灵活时钟系统
– 独立于 CPU 运行
– 与 CPU 共享 4KB RAM
– 具有 10 个可选厂家调整频率的定频数控振荡器
– 256 点高效复变快速傅立叶变换 (FFT)：
(DCO)
运算速度比 Arm® Cortex®-M0+ 内核快多达 40
倍
– 低功率低频内部时钟源 (VLO)
– 32kHz 晶振 (LFXT)
– 高频晶振 (HFXT)
• 智能数字外设
– 32 位硬件乘法器 (MPY)
– 6 通道内部直接存储器访问 (DMA)
– 具备日历和报警功能的 RTC
– 六个 16 位定时器，每个定时器具有多达七个捕
捉/比较寄存器
• 开发工具和软件（另请参阅 工具与软件）
– 开发套件（MSP-EXP430FR5994 LaunchPad™
开发套件和 MSP‑TS430PN80B 目标插接板）
– MSP430Ware™ 软件，适用于 MSP430™微控
制器
– 32 位和 16 位循环冗余校验 (CRC)
• 高性能模拟
• 器件比较 汇总了可用的器件型号和封装选项
• 要获得完整的模块说明，请参见
《MSP430FR58xx、MSP430FR59xx 和
MSP430FR6xx 系列用户指南》
– 16 通道模拟比较器
– 12 位模数转换器 (ADC)，具有窗口比较器、内部
基准和采样保持功能以及多达 20 条外部输入通
道
(1) RTC 由 3.7pF 晶振计时。
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASE54
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
1.2 应用
•
•
•
电网基础设施
工厂自动化与控制
楼宇自动化
•
•
便携式医疗和健身器材
可穿戴电子产品
1.3 说明
MSP430FR599x 微控制器 (MCU) 借助用于数字信号处理的独特低能耗加速器 (LEA) 将低功耗和性能提高到
新水平。该加速器提供 40 倍于 Arm® Cortex®-M0+ MCU 的性能，可以协助开发人员使用复变函数（例如
FFT、有限脉冲响应 (FIR) 和矩阵乘法）有效处理数据。免费提供的 DSP 库无需求助 DSP 专家即可实施。
此外，此类器件还具备高达 256KB 的 FRAM 统一标准存储器，能够为高级 应用提供更多空间， 并且为实
现无线固件更新提供更高灵活性。
MSP 超低功耗 (ULP) FRAM 微控制器平台将独特的嵌入式 FRAM 和全面的超低功耗系统架构相结合，从而
使系统设计人员在低能耗条件下提升性能。FRAM 技术将 RAM 的低能耗快速写入、灵活性和耐用性与闪存
的非易失性相结合。
MSP430FR599x MCU 由一款广泛的硬件和软件生态系统进行支持，提供参考设计和代码示例，协助用户快
速开展设计。MSP430FR599x 的开发套件包括 MSP-EXP430FR5994 LaunchPad™ 开发套件和 MSP-
TS430PN80B 80 引脚目标开发板。此外，TI 免费提供 MSP430Ware™ 软件。该软件以 Code Composer
Studio™IDE 桌面和云端版本组件的形式在 TI 资源管理器内部提供。
器件信息(1)(2)
封装
器件型号
MSP430FR5994IZVW
MSP430FR5994IPN
MSP430FR5994IPM
MSP430FR5994IRGZ
封装尺寸(3)
6mm x 6mm
12mm x 12mm
10mm x 10mm
7mm x 7mm
NFBGA (87)
LQFP (80)
LQFP (64)
VQFN (48)
(1) 要获得所有可用器件的最新部件、封装和订购信息，请参见封装选项附录（节 9）或浏览 TI 网站
www.ti.com.cn。
(2) 有关提供的所有器件变型的对比，请参见Section 3。
(3) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参见机械数据（节 9）。
2
器件概述
版权 © 2016–2018, Texas Instruments Incorporated
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
1.4 功能框图
图 1-1 显示了器件的功能方框图。
P1.x, P2.x P3.x, P4.x P5.x, P6.x P7.x, P8.x
2x8 2x8 2x8
PJ.x
2x8
1x8
LFXIN,
HFXIN
LFXOUT,
HFXOUT
Capacitive Touch I/O 0, Capacitive Touch I/O 1
ADC12_B
I/O Ports
P1, P2
2x8 I/Os
I/O Ports
P3, P4
2x8 I/Os
I/O Ports
P5, P6
2x8 I/Os
I/O Ports
P7, P8
2x8 I/Os
I/O Port
PJ
1x8 I/Os
REF_A
MCLK
ACLK
Comp_E
(up to 16
standard
inputs,
up to 8
differential
inputs)
Clock
System
(up to 16
inputs)
Voltage
Reference
SMCLK
PA PC
1x16 I/Os 1x16 I/Os 1x16 I/Os
PB
PD
1x16 I/Os
DMA
Controller
Channel
6
MAB
MDB
Bus
Control
Logic
CPUXV2
incl. 16
Registers
MPU
IP Encap
CRC16
RAM
AES256
TA2(int)
Power
Mgmt
TA3(int)
Timer_A
2 CC
CRC-16-
CCITT
FRCTL_A
256KB
128KB
4KB + 4KB
Security
Encryption,
Decryption
(128, 256)
Watchdog
MPY32
LDO
SVS
Brownout
CRC32
Registers
EEM
(S: 3+1)
Tiny RAM
22B
CRC-32-
ISO-3309
MDB
MAB
JTAG
Interface
Spy-Bi-Wire
TB0
TA0
TA1
TA4
eUSCI_A0
eUSCI_B0
eUSCI_B1
eUSCI_B2
eUSCI_B3
(I2C,
eUSCI_A1
eUSCI_A2
eUSCI_A3
(UART,
IrDA,
SPI)
LEA
Subsystem
Timer_B
7 CC
Registers
(int, ext)
Timer_A
3 CC
Registers
(int, ext)
Timer_A
3 CC
Registers
(int, ext)
Timer_A
2 CC
Registers
(int, ext)
RTC_C
SPI)
LPM3.5 Domain
Copyright © 2016, Texas Instruments Incorporated
A. 该器件具备 8KB RAM，其中 4KB RAM 与 LEA 子系统共享。CPU 的优先级高于 LEA 子系统。
B. 仅 MSP430FR599x MCU 提供 LEA 子系统。
图 1-1. 功能框图
版权 © 2016–2018, Texas Instruments Incorporated
器件概述
3
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
内容
1
器件概述.................................................... 1
1.1 特性 ................................................... 1
1.2 应用 ................................................... 2
1.3 说明 ................................................... 2
1.4 功能框图 .............................................. 3
修订历史记录............................................... 5
Device Comparison ..................................... 6
3.1 Related Products ..................................... 7
Terminal Configuration and Functions.............. 8
4.1 Pin Diagrams ......................................... 8
4.2 Pin Attributes ........................................ 13
4.3 Signal Descriptions.................................. 19
4.4 Pin Multiplexing ..................................... 26
4.5 Buffer Types......................................... 26
4.6 Connection of Unused Pins ......................... 26
Specifications ........................................... 27
5.1 Absolute Maximum Ratings......................... 27
5.2 ESD Ratings ........................................ 27
5.3 Recommended Operating Conditions............... 28
6.1 Overview ............................................ 65
6.2 CPU ................................................. 65
6.3
Low-Energy Accelerator (LEA) for Signal
Processing (MSP430FR599x Only)................. 65
6.4 Operating Modes .................................... 66
6.5 Interrupt Vector Table and Signatures .............. 68
6.6 Bootloader (BSL).................................... 71
6.7 JTAG Operation ..................................... 72
6.8 FRAM Controller A (FRCTL_A) ..................... 73
6.9 RAM ................................................ 73
2
3
4
6.10 Tiny RAM............................................ 73
6.11 Memory Protection Unit (MPU) Including IP
Encapsulation ....................................... 73
6.12 Peripherals .......................................... 74
6.13 Input/Output Diagrams .............................. 85
6.14 Device Descriptors (TLV) .......................... 123
6.15 Memory Map ....................................... 126
6.16 Identification........................................ 144
Applications, Implementation, and Layout ...... 145
5
7
8
7.1
Device Connection and Layout Fundamentals .... 145
Peripheral- and Interface-Specific Design
5.4
5.5
5.6
5.7
5.8
5.9
Active Mode Supply Current Into VCC Excluding
External Current..................................... 29
Typical Characteristics, Active Mode Supply
7.2
Information ......................................... 149
器件和文档支持......................................... 151
8.1 入门和下一步....................................... 151
8.2 器件命名规则....................................... 151
8.3 工具与软件 ......................................... 152
8.4 文档支持 ........................................... 154
8.5 相关链接 ........................................... 155
8.6 社区资源 ........................................... 155
8.7 商标 ................................................ 155
8.8 静电放电警告....................................... 155
8.9 出口管制提示....................................... 155
8.10 术语表.............................................. 155
机械、封装和可订购信息 .............................. 156
Currents ............................................. 30
Low-Power Mode (LPM0, LPM1) Supply Currents
Into VCC Excluding External Current ................ 30
Low-Power Mode (LPM2, LPM3, LPM4) Supply
Currents (Into VCC) Excluding External Current .... 31
Low-Power Mode (LPMx.5) Supply Currents (Into
VCC) Excluding External Current.................... 33
Typical Characteristics, Low-Power Mode Supply
Currents ............................................. 34
5.10 Typical Characteristics, Current Consumption per
Module .............................................. 35
5.11 Thermal Packaging Characteristics ................ 35
5.12 Timing and Switching Characteristics............... 36
Detailed Description ................................... 65
9
6
4
内容
版权 © 2016–2018, Texas Instruments Incorporated
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
2 修订历史记录
Changes from February 1, 2017 to August 30, 2018
Page
•
•
•
Updated Section 3.1, Related Products ........................................................................................... 7
Added note (1) to 表 5-2, SVS..................................................................................................... 36
Corrected the value of P6SEL1.x (changed from 0 to 1) for the N/A and DVSS rows on P6.5, P6.6, and P6.7 in
表 6-32, Port P6 (P6.0 to P6.7) Pin Functions ................................................................................. 108
Changed capacitor value from 4.7 µF to 470 nF in 图 7-5, ADC12_B Grounding and Noise Considerations ........ 149
Changed capacitor value from 4.7 µF to 470 nF in the last paragraph of 节 7.2.1.2, Design Requirements ......... 150
更新了节 8.2器件命名规则 中的文本和图....................................................................................... 151
•
•
•
Copyright © 2016–2018, Texas Instruments Incorporated
修订历史记录
5
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
3 Device Comparison
Table 3-1 summarizes the available family members.
Table 3-1. Device Comparison(1)(2)
eUSCI
FRAM
(KB)
SRAM
(KB)
CLOCK
SYSTEM
DEVICE
LEA
ADC12_B
Comp_E
Timer_A(3)
Timer_B(4)
AES
BSL
I/Os
PACKAGE
A(5)
B(6)
80 PN (LQFP)
87 ZVW (NFBGA)
20 ext, 2 int ch.
4
4
68
DCO
HFXT
LFXT
3, 3(7)
MSP430FR5994
256
128
256
128
256
8
8
8
8
8
Yes
16 ch.
7
Yes
UART
17 ext, 2 int ch.
16 ext, 2 int ch.
2, 2,2(8)
3
2
3
1
54
40
64 PM (LQFP)
48 RGZ (VQFN)
80 PN (LQFP)
87 ZVW (NFBGA)
20 ext, 2 int ch.
4
4
68
DCO
HFXT
LFXT
3, 3(7)
MSP430FR5992
MSP430FR5964
MSP430FR5962
MSP430FR59941
Yes
No
16 ch.
16 ch.
16 ch.
16 ch.
7
7
7
7
Yes
Yes
Yes
Yes
UART
UART
UART
I2C
17 ext, 2 int ch.
16 ext, 2 int ch.
2, 2,2(8)
3
2
3
1
54
40
64 PM (LQFP)
48 RGZ (VQFN)
80 PN (LQFP)
87 ZVW (NFBGA)
20 ext, 2 int ch.
4
4
68
DCO
HFXT
LFXT
3, 3(7)
17 ext, 2 int ch.
16 ext, 2 int ch.
2, 2,2(8)
3
2
3
1
54
40
64 PM (LQFP)
48 RGZ (VQFN)
80 PN (LQFP)
87 ZVW (NFBGA)
20 ext, 2 int ch.
4
4
68
DCO
HFXT
LFXT
3, 3(7)
No
17 ext, 2 int ch.
16 ext, 2 int ch.
2, 2,2(8)
3
2
3
1
54
40
64 PM (LQFP)
48 RGZ (VQFN)
80 PN (LQFP)
87 ZVW (NFBGA)
20 ext, 2 int ch.
4
4
68
DCO
HFXT
LFXT
3, 3(7)
Yes
17 ext, 2 int ch.
16 ext, 2 int ch.
2, 2,2(8)
3
2
3
1
54
40
64 PM (LQFP)
48 RGZ (VQFN)
(1) For the most current package and ordering information, see the Package Option Addendum in 节 9, or see the TI website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 capture/compare registers and PWM output generators and the second instantiation
having 5 capture/compare registers and PWM output generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 capture/compare registers and PWM output generators and the second instantiation
having 5 capture/compare registers and PWM output generators, respectively.
(5) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
(6) eUSCI_B supports I2C with multiple slave addresses and SPI.
(7) Timers TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
(8) Timers TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any), whereas Timer TA4 provides internal and external capture/compare inputs and
internal and external PWM outputs (Note: TA4 in the RGZ package provide only internal capture/compare inputs and only internal PWM outputs.).
6
Device Comparison
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
3.1 Related Products
For information about other devices in this family of products or related products, see the following links.
TI 16-bit and 32-bit microcontrollers High-performance, low-power solutions to enable the autonomous
future
Products for MSP430 ultra-low-power sensing and measurement microcontrollers One platform.
One ecosystem. Endless possibilities.
Products for MSP430 ultrasonic and performance sensing microcontrollers Ultra-low-power single-
chip MCUs with integrated sensing peripherals
Companion products for MSP430FR5994 Review products that are frequently purchased or used with
this product.
Reference designs for MSP430FR5994 The TI Designs Reference Design Library is a robust reference
design library that spans analog, embedded processor, and connectivity. Created by TI
experts to help you jump start your system design, all TI Designs include schematic or block
diagrams, BOMs, and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.
Copyright © 2016–2018, Texas Instruments Incorporated
Device Comparison
7
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
4 Terminal Configuration and Functions
4.1 Pin Diagrams
Figure 4-1 shows the bottom view of the pinout of the 87-pin ZVW package, and Figure 4-2 shows the top
view of the pinout.
DVCC1
L10
DGND
L1
P2.1
L3
P8.1
L4
P3.5
L5
P1.6
L6
P5.0
L7
P5.3
L8
P2.0
L2
DVSS1
L9
DGND
L11
DVCC3 DGND
K1 K2
P8.2
K4
P3.4
K5
P2.2
K3
P1.7
K6
P5.1
K7
P5.2
K8
P4.6 DGND P2.4
K9 K10 K11
DVSS3 RST
P5.4 P2.3
J1
J2
J10
J11
HFIN
H11
P2.6
H1
TST
H2
P8.3
H4
P3.6
H5
P3.7
H6
P4.4
H7
P4.5
H8
P5.5
H10
P4.2
G1
P4.3
G2
P2.5
G4
P5.7
G8
P5.6
G10
HFOUT
G11
P4.0
F1
P7.7
F2
P4.1
F4
P6.4
F8
P6.5
F10
P2.7
F11
P7.4
E1
P7.5
E2
P7.6
E4
P6.6
E8
AVSS3
E10
LFIN
E11
LFOUT
D11
P7.2
D1
PJ.3
D2
P7.3
D4
P8.0
D5
P4.7
D6
P6.1
D7
P6.0
D8
AVSS2
D10
PJ.1
C1
PJ.2
C2
P6.7
C10
AVSS1
C11
PJ.0
B1
P1.5
B4
P7.1
B5
AVCC1
B11
P1.4
B3
P6.3
B6
P3.2
B7
P3.1
B8
P1.2 AGND
B9
B10
DGND DVSS2
P1.3
A4
P7.0
A5
DVCC2
A3
P6.2
A6
P3.3
A7
P3.0
A8
P1.1
A9
P1.0 AGND
A10 A11
A1
A2
NOTE: On devices with UART BSL: P2.0 is BSLTX, P2.1 is BSLRX
NOTE: On devices with I2C BSL: P1.6 is BSLSDA, P1.7 is BSLSCL
Figure 4-1. 87-Pin ZVW Package (Bottom View)
8
Terminal Configuration and Functions
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
DVCC1
L10
P5.3
L8
P5.0
L7
P1.6
L6
P3.5
L5
P8.1
L4
P2.1
L3
DGND
L1
DGND
L11
DVSS1
L9
P2.0
L2
P3.4
K5
P8.2
K4
DGND DVCC3
K2 K1
P2.4 DGND P4.6
P5.2
K8
P5.1
K7
P1.7
K6
P2.2
K3
K11
K10
K9
P2.3
J11
RST DVSS3
P5.4
J10
J2
J1
HFIN
H11
P3.6
H5
P8.3
H4
TST
H2
P2.6
H1
P5.5
H10
P4.5
H8
P4.4
H7
P3.7
H6
P2.5
G4
P4.3
G2
P4.2
G1
P5.6
G10
P5.7
G8
HFOUT
G11
P4.1
F4
P7.7
F2
P4.0
F1
P6.5
F10
P6.4
F8
P2.7
F11
P7.6
E4
P7.5
E2
P7.4
E1
AVSS3
E10
P6.6
E8
LFIN
E11
LFOUT
D11
P8.0
D5
P7.3
D4
PJ.3
D2
P7.2
D1
AVSS2
D10
P6.0
D8
P6.1
D7
P4.7
D6
PJ.2
C2
PJ.1
C1
P6.7
C10
AVSS1
C11
AVCC1
B11
P7.1
B5
P1.5
B4
PJ.0
BL1
AGND P1.2
P3.1
B8
P3.2
B7
P6.3
B6
P1.4
B3
B10
B9
P7.0
A5
P1.3
A4
DVSS2 DGND
AGND P1.0
A11 A10
P1.1
A9
P3.0
A8
P3.3
A7
P6.2
A6
DVCC2
A3
A2
A1
Figure 4-2. 87-Pin ZVW Package (Top View)
Copyright © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
9
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
Figure 4-3 shows the pinout of the 80-pin PN package.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P3.0/A12/C12
DVSS1
2
P4.6
3
P4.5
4
P4.4/TB0.5
P5.3/UCB1STE
P5.2/UCB1CLK/T
5
P3.1/A13/C13
6
A4CLK
P3.2/A14/C14
P5.1/UCB1SOMI/UCB1SCL
P5.0/UCB1SIMO/UCB1SDA
7
P3.3/A15/C15
P6.0/UC
P6.1/UC
A3T
XD/UC
8
A3SIM
O
A3R
XD/UC
9
P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
A3SO
MI
P6.2/UCA3CLK
P6.3/UCA3STE
P4.7
10
11
12
13
14
15
16
17
18
19
20
P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P3.7/TB0.6
P3.6/TB0.5
P7.0/UCB2SIMO/UCB2SDA
P7.1/UCB2SOMI/UCB2SCL
P8.0
P3.5/TB0.4/COUT
P3.4/TB0.3/SMCLK
P8.3
P1.3/TA1.2/UCB0STE/A3/C3
P1.4/TB0.1/UCA0STE/A4/C4
P1.5/TB0.2/UCA0CLK/A5/C5
DVSS2
P8.2
P8.1
P2.2/TB0.2/UCB0CLK
P2.1/TB0.0/UCA0RXD/UCA0SOMI
P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
DVCC2
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NOTE: On devices with UART BSL: P2.0 is BSLTX, P2.1 is BSLRX
NOTE: On devices with I2C BSL: P1.6 is BSLSDA, P1.7 is BSLSCL
Figure 4-3. 80-Pin PN Package (Top View)
10
Terminal Configuration and Functions
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
Figure 4-4 shows the pinout of the 64-pin PM package.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P3.0/A12/C12
DVSS1
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P4.6
P4.5
P4.4/TB0.5
P5.3/UCB1STE
P5.2/UCB1CLK/T
P3.1/A13/C13
P3.2/A14/C14
A4CLK
P5.1/UCB1SOMI/UCB1SCL
P5.0/UCB1SIMO/UCB1SDA
P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P3.7/TB0.6
P3.3/A15/C15
P4.7
P7.0/UCB2SIMO/UCB2SDA
P7.1/UCB2SOMI/UCB2SCL
P8.0
10
11
12
13
14
15
16
P1.3/TA1.2/UCB0STE/A3/C3
P1.4/TB0.1/UCA0STE/A4/C4
P1.5/TB0.2/UCA0CLK/A5/C5
DVSS2
P3.6/TB0.5
P3.5/TB0.4/COUT
P3.4/TB0.3/SMCLK
P2.2/TB0.2/UCB0CLK
DVCC2
P2.1/TB0.0/UCA0RXD/UCA0SOMI
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NOTE: On devices with UART BSL: P2.0 is BSLTX, P2.1 is BSLRX
NOTE: On devices with I2C BSL: P1.6 is BSLSDA, P1.7 is BSLSCL
Figure 4-4. 64-Pin PM Package (Top View)
Copyright © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
11
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
Figure 4-5 shows the pinout of the 48-pin RGZ package.
48 47 46 45 44 43 42 41 40 39 38 37
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P3.0/A12/C12
1
2
36 DVSS1
35 P4.6
3
34 P4.5
4
33 P4.4/TB0.5
P3.1/A13/C13
5
32 P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
31 P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
30 P3.7/TB0.6
P3.2/A14/C14
6
P3.3/A15/C15
7
P4.7
8
29 P3.6/TB0.5
P1.3/TA1.2/UCB0STE/A3/C3
P1.4/TB0.1/UCA0STE/A4/C4
P1.5/TB0.2/UCA0CLK/A5/C5
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6
9
28 P3.5/TB0.4/COUT
10
11
12
27 P3.4/TB0.3/SMCLK
26 P2.2/TB0.2/UCB0CLK
25 P2.1/TB0.0/UCA0RXD/UCA0SOMI
13 14 15 16 17 18 19 20 21 22 23 24
NOTE: TI recommends connecting the QFN thermal pad to VSS
.
NOTE: On devices with UART BSL: P2.0 is BSLTX, P2.1 is BSLRX
NOTE: On devices with I2C BSL: P1.6 is BSLSDA, P1.7 is BSLSCL
Figure 4-5. 48-Pin RGZ Package (Top View)
12
Terminal Configuration and Functions
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
4.2 Pin Attributes
Table 4-1 summarizes the attributes of the pins.
Table 4-1. Pin Attributes
PIN NUMBER(1)
BUFFER
TYPE(5)
POWER
RESET STATE
AFTER BOR(7)
SIGNAL NAME(2) (3) SIGNAL TYPE(4)
SOURCE(6)
PN
PM
RGZ
ZVW
P1.0
I/O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
OFF
TA0.1
DMAE0
RTCCLK
A0
I/O
–
I
–
O
–
1
1
1
A10
I
–
C0
I
Analog
–
VREF-
VeREF-
P1.1
O
Analog
–
I
Analog
–
I/O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
TA0.2
TA1CLK
COUT
A1
I/O
–
I
–
O
–
2
2
2
A9
I
–
C1
I
Analog
–
VREF+
VeREF+
P1.2
O
Analog
–
I
Analog
–
I/O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
TA1.1
TA0CLK
COUT
A2
I/O
–
I
–
3
3
3
B9
O
–
I
–
C2
I
Analog
–
OFF
–
P3.0
I/O
LVCMOS
Analog
4
5
6
7
8
4
5
6
7
–
4
5
6
7
–
A8
B8
B7
A7
D8
A12
I
C12
I
I/O
I
Analog
–
P3.1
LVCMOS
Analog
–
A13
–
C13
I
Analog
–
P3.2
I/O
I
LVCMOS
Analog
OFF
–
A14
C14
I
Analog
–
P3.3
I/O
I
LVCMOS
Analog
OFF
–
A15
C15
I
Analog
–
P6.0
I/O
O
I/O
LVCMOS
LVCMOS
LVCMOS
OFF
–
UCA3TXD
UCA3SIMO
–
(1) N/A = not available
(2) The signal that is listed first for each pin is the reset default pin name.
(3) To determine the pin mux encodings for each pin, see 节 6.13.
(4) Signal Types: I = Input, O = Output, I/O = Input or Output.
(5) Buffer Types: LVCMOS, Analog, or Power (see Table 4-3 for details)
(6) The power source shown in this table is the I/O power source, which may differ from the module power source.
(7) Reset States:
OFF = High impedance with Schmitt-trigger input and pullup or pulldown (if available) disabled
N/A = Not applicable
Copyright © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
13
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
Table 4-1. Pin Attributes (continued)
PIN NUMBER(1)
BUFFER
TYPE(5)
POWER
RESET STATE
AFTER BOR(7)
SIGNAL NAME(2) (3) SIGNAL TYPE(4)
SOURCE(6)
PN
PM
RGZ
ZVW
P6.1
I/O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
–
OFF
9
–
–
D7
UCA3RXD
UCA3SOMI
P6.2
–
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
OFF
–
10
–
–
A6
UCA3CLK
P6.3
OFF
–
11
12
–
8
–
8
B6
D6
UCA3STE
P4.7
OFF
OFF
–
P7.0
13
9
–
A5
UCB2SIMO
UCB2SDA
P7.1
–
OFF
–
14
15
10
11
–
–
B5
D5
UCB2SOMI
UCB2SCL
P8.0
–
OFF
OFF
–
P1.3
TA1.2
UCB0STE
A3
16
17
18
12
13
14
9
A4
B3
B4
–
–
C3
I
Analog
–
P1.4
I/O
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
TB0.1
UCA0STE
A4
10
11
–
–
C4
I
Analog
–
P1.5
I/O
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
TB0.2
UCA0CLK
A5
–
–
C5
I
Analog
–
19
20
15
16
–
–
A2
A3
DVSS2
DVCC2
PJ.0
P
Power
N/A
N/A
OFF
–
P
Power
–
I/O
O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
TDO
TB0OUTH
SMCLK
SRSCG1
C6
I
–
21
22
17
18
12
13
B1
O
–
O
–
I
–
PJ.1
I/O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
TDI
TCLK
I
–
C1
MCLK
SRSCG0
C7
O
–
O
–
I
–
14
Terminal Configuration and Functions
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
Table 4-1. Pin Attributes (continued)
PIN NUMBER(1)
BUFFER
TYPE(5)
POWER
RESET STATE
AFTER BOR(7)
SIGNAL NAME(2) (3) SIGNAL TYPE(4)
SOURCE(6)
PN
PM
RGZ
ZVW
PJ.2
I/O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
–
OFF
–
TMS
23
19
14
C2
ACLK
SROSCOFF
C8
O
O
I
–
–
–
PJ.3
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
TCK
24
20
15
D2
SRCPUOFF
C9
O
I
–
–
P7.2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
25
26
21
22
–
–
D1
D4
UCB2CLK
P7.3
OFF
–
UCB2STE
TA4.1
P7.4
–
OFF
–
27
23
–
E1
TA4.0
A16
–
P7.5
I/O
I
LVCMOS
Analog
OFF
–
28
29
30
31
32
33
34
–
–
–
–
E2
E4
F2
F1
F4
G1
G2
A17
P7.6
I/O
I
LVCMOS
Analog
OFF
–
A18
P7.7
I/O
I
LVCMOS
Analog
OFF
–
–
–
A19
P4.0
I/O
I
LVCMOS
Analog
OFF
–
24
25
26
27
16
17
18
19
A8
P4.1
I/O
I
LVCMOS
Analog
OFF
–
A9
P4.2
I/O
I
LVCMOS
Analog
OFF
–
A10
P4.3
I/O
I
LVCMOS
Analog
OFF
–
A11
P2.5
I/O
I/O
O
I/O
I/O
O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Power
OFF
–
TB0.0
UCA1TXD
UCA1SIMO
P2.6
35
36
28
29
20
21
G4
H1
–
–
OFF
–
TB0.1
UCA1RXD
UCA1SOMI
TEST
SBWTCK
RST
–
I/O
I
–
OFF
–
37
38
30
31
22
23
H2
J2
I
I
OFF
–
NMI
I
SBWTDIO
DVSS3
DVCC3
I/O
P
–
39
40
–
–
–
–
J1
N/A
N/A
K1
P
Power
–
Copyright © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
15
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
Table 4-1. Pin Attributes (continued)
PIN NUMBER(1)
BUFFER
TYPE(5)
POWER
RESET STATE
AFTER BOR(7)
SIGNAL NAME(2) (3) SIGNAL TYPE(4)
SOURCE(6)
PN
PM
RGZ
ZVW
P2.0
I/O
I/O
O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
OFF
TB0.6
–
UCA0TXD
BSLTX
UCA0SIMO
TB0CLK
ACLK
–
41
32
24
L2
O
–
I/O
I
–
–
–
O
P2.1
I/O
I/O
I
OFF
–
TB0.0
42
43
33
34
25
26
L3
K3
UCA0RXD
BSLRX
UCA0SOMI
P2.2
–
I
–
I/O
I/O
O
–
OFF
–
TB0.2
UCB0CLK
P8.1
I/O
I/O
I/O
I/O
I/O
I/O
O
–
44
45
46
–
–
–
–
–
–
L4
K4
H4
OFF
OFF
OFF
OFF
–
P8.2
P8.3
P3.4
47
48
35
36
27
28
K5
L5
TB0.3
SMCLK
P3.5
–
I/O
I/O
O
OFF
–
TB0.4
COUT
–
P3.6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OFF
–
49
50
37
38
29
30
H5
H6
TB0.5
P3.7
OFF
–
TB0.6
P1.6
OFF
–
TB0.3
UCB0SIMO
UCB0SDA
BSLSDA
TA0.0
–
51
52
39
40
31
32
L6
–
–
–
P1.7
OFF
–
TB0.4
UCB0SOMI
UCB0SCL
BSLSCL
TA1.0
–
K6
–
–
–
P5.0
OFF
–
53
54
41
42
–
–
L7
K7
UCB1SIMO
UCB1SDA
P5.1
–
OFF
–
UCB1SOMI
UCB1SCL
–
16
Terminal Configuration and Functions
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
Table 4-1. Pin Attributes (continued)
PIN NUMBER(1)
BUFFER
TYPE(5)
POWER
RESET STATE
AFTER BOR(7)
SIGNAL NAME(2) (3) SIGNAL TYPE(4)
SOURCE(6)
PN
PM
RGZ
ZVW
P5.2
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Power
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
–
OFF
–
55
43
–
K8
UCB1CLK
TA4CLK
P5.3
–
I/O
I/O
I/O
I/O
I/O
I/O
P
OFF
–
56
57
44
45
–
L8
UCB1STE
P4.4
OFF
–
33
H7
TB0.5
58
59
60
61
62
46
47
48
49
50
34
35
36
37
38
H8
K9
P4.5
OFF
OFF
N/A
N/A
OFF
OFF
–
P4.6
L9
DVSS1
DVCC1
P2.7
L10
F11
P
Power
–
I/O
I/O
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
P2.3
TA0.0
63
64
51
52
39
40
J11
UCA1STE
A6
–
–
C10
I
Analog
–
P2.4
I/O
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
OFF
–
TA1.0
K11
UCA1CLK
A7
–
–
C11
I
Analog
–
P5.4
I/O
O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
OFF
–
UCA2TXD
UCA2SIMO
TB0OUTH
P5.5
65
66
67
53
54
55
–
–
–
J10
H10
G10
I/O
I
–
–
I/O
I
OFF
–
UCA2RXD
UCA2SOMI
ACLK
I/O
O
–
–
P5.6
I/O
I/O
I/O
O
OFF
–
UCA2CLK
TA4.0
–
SMCLK
P5.7
–
I/O
I/O
I/O
O
OFF
–
UCA2STE
TA4.1
68
69
56
–
–
–
G8
F8
–
MCLK
–
P6.4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OFF
–
UCB3SIMO
UCB3SDA
P6.5
–
OFF
–
70
71
–
–
–
–
F10
E8
UCB3SOMI
UCB3SCL
P6.6
–
OFF
–
UCB3CLK
Copyright © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
17
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
Table 4-1. Pin Attributes (continued)
PIN NUMBER(1)
BUFFER
TYPE(5)
POWER
RESET STATE
AFTER BOR(7)
SIGNAL NAME(2) (3) SIGNAL TYPE(4)
SOURCE(6)
PN
72
73
74
PM
RGZ
ZVW
C10
E10
H11
P6.7
I/O
I/O
P
LVCMOS
LVCMOS
Power
DVCC
OFF
–
–
–
UCB3STE
AVSS3
PJ.6
DVCC
57
58
41
42
–
N/A
–
I/O
I
LVCMOS
Analog
LVCMOS
Analog
Power
DVCC
HFXIN
PJ.7
DVCC
–
I/O
O
P
DVCC
OFF
–
75
76
77
59
60
61
43
44
45
G11
D10
E11
HFXOUT
AVSS2
PJ.4
DVCC
–
N/A
OFF
–
I/O
I
LVCMOS
Analog
LVCMOS
Analog
Power
DVCC
LFXIN
PJ.5
DVCC
I/O
O
P
DVCC
OFF
–
78
62
46
D11
LFXOUT
AVSS1
AVCC1
DGND
AGND
AGND
DGND
DGND
DGND
DGND
QFN Pad
DVCC
79
80
–
63
64
–
47
48
–
C11
B11
A1
–
–
–
–
–
–
–
–
–
–
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
P
Power
P
Power
–
–
–
A11
B10
K2
P
Power
–
–
–
P
Power
–
–
–
P
Power
–
–
–
K10
L1
P
Power
–
–
–
P
Power
–
–
–
L11
–
P
Power
–
–
Pad
P
Power
18
Terminal Configuration and Functions
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
4.3 Signal Descriptions
Table 4-2 describes the signals for all device variants and package options.
Table 4-2. Signal Descriptions
PIN NO.(1)
SIGNAL
NAME
PIN
FUNCTION
DESCRIPTION
TYPE(2)
ZVW
A10
A9
PN
1
PM
1
RGZ
1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I
I
ADC analog input A0
ADC analog input A1
ADC analog input A2
ADC analog input A3
ADC analog input A4
ADC analog input A5
ADC analog input A6
ADC analog input A7
ADC analog input A8
ADC analog input A9
2
2
2
B9
3
3
3
I
A4
16
17
18
63
64
31
32
33
34
4
12
13
14
51
52
24
25
26
27
4
9
I
B3
10
11
39
40
16
17
18
19
4
I
B4
I
J11
K11
F1
I
I
I
F4
I
A10
G1
G2
A8
I
ADC analog input A10
A11
I
ADC analog input A11
ADC
A12
I
ADC analog input A12
A13
B8
5
5
5
I
ADC analog input A13
A14
B7
6
6
6
I
ADC analog input A14
A15
A7
7
7
7
I
ADC analog input A15
A16
E1
27
28
29
30
2
23
–
–
I
ADC analog input A16
A17
E2
–
I
ADC analog input A17
A18
E4
–
–
I
ADC analog input A18
A19
F2
–
–
I
ADC analog input A19
VREF+
VREF-
VeREF+
A9
2
2
O
O
I
Output of positive reference voltage
Output of negative reference voltage
Input for an external positive reference voltage to the ADC
A10
A9
1
1
1
2
2
2
Input for an external negative reference voltage to the
ADC
VeREF-
A10
1
1
1
I
BSLSCL
BSLSDA
BSLRX
BSLTX
K6
L6
L3
L2
52
51
42
41
40
39
33
32
32
31
25
24
I/O
I/O
I
I2C BSL clock
I2C BSL data
BSL (I2C)
UART BSL receive
UART BSL transmit
BSL (UART)
O
23
41
66
19
32
54
C2
H10
14
24
ACLK
O
ACLK output
HFXIN
H11
G11
E11
D11
74
75
77
78
58
59
61
62
42
43
45
46
I
Input for high-frequency crystal oscillator HFXT
Output for high-frequency crystal oscillator HFXT
Input for low-frequency crystal oscillator LFXT
Output of low-frequency crystal oscillator LFXT
HFXOUT
LFXIN
O
I
Clock
LFXOUT
O
C1
G8
22
68
18
56
MCLK
13
O
MCLK output
21
47
67
17
35
55
B1
G10
12
27
SMCLK
O
SMCLK output
(1) N/A = not available
(2) I = input, O = output, P = power
Copyright © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
19
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
Table 4-2. Signal Descriptions (continued)
PIN NO.(1)
SIGNAL
NAME
PIN
FUNCTION
DESCRIPTION
TYPE(2)
ZVW
A10
A9
PN
1
PM
1
RGZ
1
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Comparator input C0
Comparator input C1
Comparator input C2
Comparator input C3
Comparator input C4
Comparator input C5
Comparator input C6
Comparator input C7
Comparator input C8
Comparator input C9
Comparator input C10
Comparator input C11
Comparator input C12
Comparator input C13
Comparator input C14
Comparator input C15
2
2
2
B9
3
3
3
A4
16
17
18
21
22
23
24
63
64
4
12
13
14
17
18
19
20
51
52
4
9
B3
10
11
12
13
14
15
39
40
4
B4
B1
C1
C2
D2
J11
K11
A8
Comparator
C10
C11
C12
C13
C14
C15
B8
5
5
5
B7
6
6
6
A7
7
7
7
2
3
48
2
3
36
2
3
28
A9
B9
COUT
O
Comparator output
DMA
DMAE0
SBWTCK
SBWTDIO
SRCPUOFF
SROSCOFF
SRSCG0
SRSCG1
TCK
A10
H2
J2
1
1
1
I
I
External DMA trigger
37
38
24
23
22
21
24
22
22
21
37
23
30
31
20
19
18
17
20
18
18
17
30
19
22
23
15
14
13
12
15
13
13
12
22
14
Spy-Bi-Wire input clock
I/O
O
O
O
O
I
Spy-Bi-Wire data input/output
D2
C2
C1
B1
D2
C1
C1
B1
H2
C2
Low-power debug: CPU Status register bit CPUOFF
Low-power debug: CPU Status register bit OSCOFF
Low-power debug: CPU Status register bit SCG0
Low-power debug: CPU Status register bit SCG1
Test clock
Debug
TCLK
I
Test clock input
TDI
I
Test data input
TDO
O
I
Test data output port
TEST
Test mode pin – select digital I/O on JTAG pins
Test mode select
TMS
I
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
A10
A9
B9
A4
B3
B4
L6
1
1
1
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
2
2
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
3
3
3
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
16
17
18
51
52
12
13
14
39
40
9
GPIO
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
10
11
31
32
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
K6
20
Terminal Configuration and Functions
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
FUNCTION
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
Table 4-2. Signal Descriptions (continued)
PIN NO.(1)
SIGNAL
NAME
PIN
DESCRIPTION
TYPE(2)
ZVW
PN
PM
RGZ
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P2.0
L2
41
32
24
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
L3
K3
J11
K11
G4
H1
F11
A8
B8
B7
A7
K5
L5
42
43
63
64
35
36
62
4
33
34
51
52
28
29
50
4
25
26
39
40
20
21
38
4
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
GPIO
GPIO
GPIO
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
5
5
5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
6
6
6
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
7
7
7
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
47
48
49
50
31
32
33
34
57
58
59
12
35
36
37
38
24
25
26
27
45
46
47
8
27
28
29
30
16
17
18
19
33
34
35
8
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
H5
H6
F1
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
F4
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
G1
G2
H7
H8
K9
D6
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
Copyright © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
21
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
Table 4-2. Signal Descriptions (continued)
PIN NO.(1)
SIGNAL
NAME
PIN
FUNCTION
DESCRIPTION
TYPE(2)
ZVW
PN
PM
RGZ
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P5.0
L7
53
41
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
K7
K8
54
55
56
65
66
67
68
8
42
43
44
53
54
55
56
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
L8
GPIO
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
J10
H10
G10
G8
D8
D7
A6
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
9
–
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
10
11
69
70
71
72
13
14
25
26
27
28
29
30
–
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
B6
–
GPIO
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
F8
–
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
F10
E8
–
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
–
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
C10
A5
–
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
9
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
B5
10
21
22
23
–
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
D1
D4
E1
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
GPIO
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
E2
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
E4
–
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
F2
–
22
Terminal Configuration and Functions
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
FUNCTION
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
Table 4-2. Signal Descriptions (continued)
PIN NO.(1)
SIGNAL
NAME
PIN
DESCRIPTION
TYPE(2)
ZVW
PN
PM
RGZ
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P8.0
D5
15
11
–
I/O
I/O
I/O
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P8.1
P8.2
P8.3
L4
K4
H4
44
45
46
–
–
–
–
–
–
GPIO
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
PJ.0
B1
C1
21
22
23
24
77
78
74
75
52
51
54
53
14
13
70
69
17
18
19
20
61
62
58
59
40
39
42
41
10
9
12
13
14
15
45
46
42
43
32
31
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
I2C clock – eUSCI_B0 I2C mode
I2C data – eUSCI_B0 I2C mode
I2C clock – eUSCI_B1 I2C mode
I2C data – eUSCI_B1 I2C mode
I2C clock – eUSCI_B2 I2C mode
I2C data – eUSCI_B2 I2C mode
I2C clock – eUSCI_B3 I2C mode
I2C data – eUSCI_B3 I2C mode
PJ.1
PJ.2
C2
PJ.3
D2
GPIO
PJ.4
E11
D11
H11
G11
K6
PJ.5
PJ.6
PJ.7
UCB0SCL
UCB0SDA
UCB1SCL
UCB1SDA
UCB2SCL
UCB2SDA
UCB3SCL
UCB3SDA
L6
K7
L7
–
I2C
B5
–
A5
–
F10
F8
–
–
–
–
B10
A11
AGND
–
–
–
P
Analog ground
AVCC1
AVSS1
AVSS2
AVSS3
B11
C11
D10
E10
80
79
76
73
64
63
60
57
48
47
44
41
P
P
P
P
Analog power supply
Analog ground supply
Analog ground supply
Analog ground supply
A1
K2
DGND
K10
L1
–
–
–
P
Digital ground
Power
L11
DVCC1
DVCC2
DVCC3
DVSS1
DVSS2
DVSS3
L10
A3
K1
L9
61
20
40
60
19
39
49
16
–
37
–
P
P
P
P
P
P
Digital power supply
Digital power supply
–
Digital power supply
48
15
–
36
–
Digital ground supply
A2
J1
Digital ground supply
–
Digital ground supply
QFN package exposed thermal pad. TI recommends
QFN Pad
RTCCLK
–
–
1
–
1
Pad
1
P
connection to VSS
.
RTC clock calibration output (not available on
MSP430FR5x5x devices)
RTC
A10
O
Copyright © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
23
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
Table 4-2. Signal Descriptions (continued)
PIN NO.(1)
SIGNAL
NAME
PIN
FUNCTION
DESCRIPTION
TYPE(2)
ZVW
PN
PM
RGZ
Clock signal input – eUSCI_A0 SPI slave mode
Clock signal output – eUSCI_A0 SPI master mode
UCA0CLK
B4
18
14
11
I/O
UCA0SIMO
UCA0SOMI
UCA0STE
L2
L3
B3
41
42
17
32
33
13
24
25
10
I/O
I/O
I/O
Slave in/master out – eUSCI_A0 SPI mode
Slave out/master in – eUSCI_A0 SPI mode
Slave transmit enable – eUSCI_A0 SPI mode
Clock signal input – eUSCI_A1 SPI slave mode
Clock signal output – eUSCI_A1 SPI master mode
UCA1CLK
K11
64
52
40
I/O
UCA1SIMO
UCA1SOMI
UCA1STE
G4
H1
35
36
63
28
29
51
20
21
39
I/O
I/O
I/O
Slave in/master out – eUSCI_A1 SPI mode
Slave out/master in – eUSCI_A1 SPI mode
Slave transmit enable – eUSCI_A1 SPI mode
J11
Clock signal input – eUSCI_A2 SPI slave mode
Clock signal output – eUSCI_A2 SPI master mode
UCA2CLK
G10
67
55
–
I/O
UCA2SIMO
UCA2SOMI
UCA2STE
J10
H10
G8
65
66
68
53
54
56
–
–
–
I/O
I/O
I/O
Slave in/master out – eUSCI_A2 SPI mode
Slave out/master in – eUSCI_A2 SPI mode
Slave transmit enable – eUSCI_A2 SPI mode
Clock signal input – eUSCI_A3 SPI slave mode
Clock signal output – eUSCI_A3 SPI master mode
UCA3CLK
A6
10
–
–
I/O
UCA3SIMO
UCA3SOMI
UCA3STE
D8
D7
B6
8
9
–
–
–
–
–
–
I/O
I/O
I/O
Slave in/master out – eUSCI_A3 SPI mode
Slave out/master in – eUSCI_A3 SPI mode
Slave transmit enable – eUSCI_A3 SPI mode
11
SPI
Clock signal input – eUSCI_B0 SPI slave mode
Clock signal output – eUSCI_B0 SPI master mode
UCB0CLK
K3
43
34
26
I/O
UCB0SIMO
UCB0SOMI
UCB0STE
L6
K6
A4
51
52
16
39
40
12
31
32
9
I/O
I/O
I/O
Slave in/master out – eUSCI_B0 SPI mode
Slave out/master in – eUSCI_B0 SPI mode
Slave transmit enable – eUSCI_B0 SPI mode
Clock signal input – eUSCI_B1 SPI slave mode
Clock signal output – eUSCI_B1 SPI master mode
UCB1CLK
K8
55
43
–
I/O
UCB1SIMO
UCB1SOMI
UCB1STE
L7
K7
L8
53
54
56
41
42
44
–
–
–
I/O
I/O
I/O
Slave in/master out – eUSCI_B1 SPI mode
Slave out/master in – eUSCI_B1 SPI mode
Slave transmit enable – eUSCI_B1 SPI mode
Clock signal input – eUSCI_B2 SPI slave mode
Clock signal output – eUSCI_B2 SPI master mode
UCB2CLK
D1
25
21
–
I/O
UCB2SIMO
UCB2SOMI
UCB2STE
A5
B5
D4
13
14
26
9
–
–
–
I/O
I/O
I/O
Slave in/master out – eUSCI_B2 SPI mode
Slave out/master in – eUSCI_B2 SPI mode
Slave transmit enable – eUSCI_B2 SPI mode
10
22
Clock signal input – eUSCI_B3 SPI slave mode
Clock signal output – eUSCI_B3 SPI master mode
UCB3CLK
E8
71
–
–
I/O
UCB3SIMO
UCB3SOMI
UCB3STE
NMI
F8
F10
C10
J2
69
70
72
38
38
–
–
–
–
I/O
I/O
I/O
I
Slave in/master out – eUSCI_B3 SPI mode
Slave out/master in – eUSCI_B3 SPI mode
Slave transmit enable – eUSCI_B3 SPI mode
Nonmaskable interrupt input
–
–
31
31
23
23
System
RST
J2
I
Reset input active low
24
Terminal Configuration and Functions
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
FUNCTION
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
Table 4-2. Signal Descriptions (continued)
PIN NO.(1)
SIGNAL
NAME
PIN
DESCRIPTION
TYPE(2)
ZVW
L6
PN
51
63
1
PM
39
51
1
RGZ
31
39
1
TA0.0
I/O
I/O
I/O
I/O
I
TA0 CCR0 capture: CCI0A input, compare: Out0
TA0 CCR0 capture: CCI0B input, compare: Out0
TA0 CCR1 capture: CCI1A input, compare: Out1
TA0 CCR2 capture: CCI2A input, compare: Out2
TA0 input clock
TA0.0
TA0.1
TA0.2
TA0CLK
TA1.0
TA1.0
TA1.1
TA1.2
TA1CLK
TA4.0
TA4.0
TA4.1
TA4.1
TA4CLK
TB0.0
TB0.0
TB0.1
TB0.1
TB0.2
TB0.2
TB0.3
TB0.3
TB0.4
TB0.4
TB0.5
TB0.5
TB0.6
TB0.6
TB0CLK
J11
A10
A9
B9
K6
K11
B9
A4
A9
E1
G10
D4
G8
K8
G4
L3
2
2
2
3
3
3
52
64
3
40
52
3
32
40
3
I/O
I/O
I/O
I/O
I
TA1 CCR0 capture: CCI0A input, compare: Out0
TA1 CCR0 capture: CCI0B input, compare: Out0
TA1 CCR1 capture: CCI1A input, compare: Out1
TA1 CCR2 capture: CCI2A input, compare: Out2
TA1 input clock
16
2
12
2
9
2
27
67
26
68
55
35
42
17
36
18
43
47
51
48
52
49
57
41
50
41
23
55
22
56
43
28
33
13
29
14
34
35
39
36
40
37
45
32
38
32
–
I/O
I/O
I/O
I/O
I
TA4 CCR0 capture: CCI0B input, compare: Out0
TA4 CCR0 capture: CCI0A input, compare: Out0
TA4CCR1 capture: CCI1B input, compare: Out1
TA4 CCR1 capture: CCI1A input, compare: Out1
TA4 input clock
–
–
–
–
20
25
10
21
11
26
27
31
28
32
29
33
24
30
24
I/O
I/O
I/O
O
TB0 CCR0 capture: CCI0B input, compare: Out0
TB0 CCR0 capture: CCI0A input, compare: Out0
TB0 CCR1 capture: CCI1A input, compare: Out1
TB0 CCR1 compare: Out1
Timer
B3
H1
B4
K3
K5
L6
I/O
O
TB0 CCR2 capture: CCI2A input, compare: Out2
TB0 CCR2 compare: Out2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
TB0 CCR3 capture: CCI3A input, compare: Out3
TB0 CCR3 capture: CCI3B input, compare: Out3
TB0 CCR4 capture: CCI4A input, compare: Out4
TB0 CCR4 capture: CCI4B input, compare: Out4
TB0 CCR5 capture: CCI5A input, compare: Out5
TB0CCR5 capture: CCI5B input, compare: Out5
TB0 CCR6 capture: CCI6B input, compare: Out6
TB0 CCR6 capture: CCI6A input, compare: Out6
TB0 clock input
L5
K6
H5
H7
L2
H6
L2
B1
J10
21
65
17
53
TB0OUTH
12
I
Switch all PWM outputs high impedance input – TB0
UCA0RXD
UCA0TXD
UCA1RXD
UCA1TXD
UCA2RXD
UCA2TXD
UCA3RXD
UCA3TXD
L3
L2
42
41
36
35
66
65
9
33
32
29
28
54
53
–
25
24
21
20
–
I
O
I
Receive data – eUSCI_A0 UART mode
Transmit data – eUSCI_A0 UART mode
Receive data – eUSCI_A1 UART mode
Transmit data – eUSCI_A1 UART mode
Receive data – eUSCI_A2 UART mode
Transmit data – eUSCI_A2 UART mode
Receive data – eUSCI_A3 UART mode
Transmit data – eUSCI_A3 UART mode
H1
G4
H10
J10
D7
D8
O
I
UART
–
O
I
–
8
–
–
O
Copyright © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
25
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
4.4 Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and schematics of the
multiplexed ports, see 节 6.13.
4.5 Buffer Types
Table 4-3 describes the buffer types that are referenced in Table 4-1.
Table 4-3. Buffer Type
NOMINAL
OUTPUT
DRIVE
BUFFER TYPE
(STANDARD)
NOMINAL
VOLTAGE
PU OR PD
STRENGTH
(µA)(1)
HYSTERESIS
PU OR PD(1)
COMMENTS
STRENGTH
(mA)(1)
See analog modules in
Specifications for details
Analog(2)
LVCMOS
3.0 V
3.0 V
No
N/A
N/A
N/A
See Typical
Yes(3)
Programmable See Digital I/Os Characteristics
– Outputs
Power
SVS enables hysteresis on
DVCC
3.0 V
3.0 V
0 V
No
No
No
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(DVCC)(4)
Power
(AVCC)(4)
Power (DVSS
and AVSS)(4)
(1) N/A = not applicable
(2) This is a switch, not a buffer.
(3) Only for input pins
(4) This is supply input, not a buffer.
4.6 Connection of Unused Pins
Table 4-4 lists the correct termination of all unused pins.
Table 4-4. Connection of Unused Pins(1)
PIN
POTENTIAL
DVCC
COMMENT
AVCC
AVSS
DVSS
Px.0 to Px.7
RST/NMI
Open
Switched to port function, output direction (PxDIR.n = 1)
47-kΩ pullup or internal pullup selected with 10-nF (2.2 nF(2)) pulldown
DVCC or VCC
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK
The JTAG pins are shared with general-purpose I/O function (PJ.x). If not being used, these should
be switched to port function, output direction. When used as JTAG pins, these pins should remain
open.
Open
Open
TEST
This pin always has an internal pulldown enabled.
(1) For any unused pin with a secondary function that is shared with general-purpose I/O, follow the guidelines for the Px.0 to Px.7 pins.
(2) The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG
mode with TI tools like FET interfaces or GANG programmers.
26
Terminal Configuration and Functions
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
5 Specifications
5.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
4.1
UNIT
V
Voltage applied at DVCC and AVCC pins to VSS
Voltage difference between DVCC and AVCC pins(2)
–0.3
±0.3
V
VCC + 0.3 V
(4.1 V Max)
(3)
Voltage applied to any pin
–0.3
–40
V
Diode current at any device pin
±2
mA
°C
(4)
Storage temperature, Tstg
125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device including erroneous
writes to RAM and FRAM.
(3) All voltages referenced to VSS
.
(4) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD) Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
Copyright © 2016–2018, Texas Instruments Incorporated
Specifications
27
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
MAX UNIT
5.3 Recommended Operating Conditions
TYP data are based on VCC = 3.0 V and TA = 25°C, unless otherwise noted
MIN NOM
VCC
VSS
TA
Supply voltage range applied at all DVCC and AVCC pins(1) (2) (3)
Supply voltage applied at all DVSS and AVSS pins.
Operating free-air temperature
1.8(4)
3.6
V
V
0
–40
–40
85
85
°C
°C
µF
TJ
Operating junction temperature
Capacitor value at DVCC(5)
CDVCC
1–20%
No FRAM wait states
(NWAITSx = 0)
0
0
8(7)
fSYSTEM
Processor frequency (maximum MCLK frequency)(6)
MHz
With FRAM wait states
(NWAITSx = 1)(8)
16(9)
fACLK
Maximum ACLK frequency
Maximum SMCLK frequency
50 kHz
16(9) MHz
fSMCLK
(1) TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up, power down, and device
operation, the voltage difference between AVCC and DVCC must not exceed the limits specified under Absolute Maximum Ratings.
Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
(2) Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR
resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for
capacitor CDVCC should limit the slopes accordingly.
(3) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(4) The minimum supply voltage is defined by the supervisor SVS levels. See the PMM SVS threshold parameters for the exact values.
(5) For each supply pin pair (DVCC and DVSS, AVCC and AVSS), place a low-ESR ceramic capacitor of 100 nF (minimum) as close as
possible (within a few millimeters) to the respective pin pairs.
(6) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(7) DCO settings and HF cyrstals with a typical value less than or equal to the specified MAX value are permitted.
(8) Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always excecuted
without wait states.
(9) DCO settings and HF cyrstals with a typical value less than or equal to the specified MAX value are permitted. If a clock sources with a
higher typical value is used, the clock must be divided in the clock system.
28
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
5.4 Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted)(1)(2) (see Figure 5-1)
FREQUENCY (fMCLK = fSMCLK
)
1 MHz
0 WAIT
STATES
4 MHz
0 WAIT
STATES
8 MHz
0 WAIT
STATES
(NWAITSx = 0)
12 MHz
1 WAIT STATE 1 WAIT STATE
(NWAITSx = 1) (NWAITSx = 1)
16 MHz
EXECUTION
MEMORY
PARAMETER
VCC
UNIT
(NWAITSx = 0)
(NWAITSx = 0)
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
IAM, FRAM_UNI
FRAM
3.0 V
3.0 V
225
665
1275
1550
1970
µA
µA
(Unified memory)(3)
FRAM
0% cache hit
ratio
IAM, FRAM(0%)(4)
420
275
220
192
125
1455
855
650
535
255
2850
1650
1240
1015
450
2330
1770
1490
1290
670
3000
2265
1880
1620
790
(5)
FRAM
50% cache hit
ratio
IAM, FRAM(50%)(4)
3.0 V
3.0 V
3.0 V
3.0 V
µA
µA
µA
µA
(5)
FRAM
66% cache hit
ratio
IAM, FRAM(66%)(4)
(5)
FRAM
75% cache hit
ratio
IAM, FRAM(75%)(4)
261
182
1170
1490
1870
1313
(5)
FRAM
100% cache hit
ratio
IAM, FRAM(100%(4)
(5)
(6) (5)
IAM, RAM
RAM
RAM
3.0 V
3.0 V
140
90
325
280
590
540
880
830
1070
1020
µA
µA
(7) (5)
IAM, RAM only
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Characterized with program executing typical data processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO= 24 MHz and
fMCLK = fSMCLK = fDCO / 2.
At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency
(fMCLK,eff) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by the number of wait
states or the cache hit ratio.
The following equation can be used to compute fMCLK,eff
:
fMCLK,eff = fMCLK / [wait states × (1 – cache hit ratio) + 1]
For example, with 1 wait state and 75% cache hit ratio fMCKL,eff = fMCLK / [1 × (1 – 0.75) + 1] = fMCLK / 1.25.
(3) Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM.
(4) Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit
ratio represents number cache accesess divided by the total number of FRAM accesses. For example, a 75% ratio implies three of
every four accesses is from cache, and the remaining are FRAM accesses.
(5) See Figure 5-1 for typical curves. The characteristic equation shown in the graph is computed using the least squares method for best
linear fit using the typical data shown in Section 5.4.
(6) Program and data reside entirely in RAM. All execution is from RAM.
(7) Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
Copyright © 2016–2018, Texas Instruments Incorporated
Specifications
29
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
5.5 Typical Characteristics, Active Mode Supply Currents
3000
I(AM,0%)
I(AM,50%)
I(AM,66%)
I(AM,75%)
I(AM,100%)
I(AM,RAM)
2500
2000
1500
1000
500
I(AM,75%) [µA] = 118 × f [MHz] + 74
0
1
2
3
4
5
6
7
8
fMCLK, MCLK Frequency (MHz)
Figure 5-1. Typical Active Mode Supply Currents, No Wait States
5.6 Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
(2)
over recommended operating free-air temperature (unless otherwise noted)(1)
FREQUENCY (fSMCLK
8 MHz
)
PARAMETER
VCC
1 MHz
TYP
4 MHz
TYP
12 MHz
TYP
16 MHz
TYP
UNIT
MAX
135
67
MAX
TYP
165
175
130
130
MAX
MAX
MAX
290
2.2 V
3.0 V
2.2 V
3.0 V
75
85
40
40
105
115
65
240
250
215
215
220
240
195
195
ILPM0
µA
µA
ILPM1
65
222
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Current for watchdog timer clocked by SMCLK included.
fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO at specified frequency - except for 12 MHz: here fDCO=24MHz and fSMCLK = fDCO / 2.
30
Specifications
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
5.7 Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External
Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 5-2
and Figure 5-3)
–40°C
25°C
60°C
85°C
PARAMETER
VCC
UNIT
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
(3)
Low-power mode 2, 12-pF crystal(2)
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
0.8
0.8
0.6
0.6
0.5
0.5
0.8
0.8
0.5
1.3
1.3
1.2
1.2
1.0
1.0
1.0
1.0
0.7
4.1
4.1
4.0
4.0
3.8
3.8
2.2
2.2
2.1
10.8
10.8
10.7
10.7
10.5
10.5
4.5
ILPM2,XT12
ILPM2,XT3.7
ILPM2,VLO
ILPM3,XT12
μA
(4)
2.7
25
(5)
Low-power mode 2, 3.7-pF crystal(2)
μA
(4)
Low-power mode 2, VLO, includes
SVS(6)
μA
2.4
1.5
24.5
9.9
Low-power mode 3, 12-pF crystal,
μA
(3) (7)
includes SVS(2)
4.5
Low-power mode 3, 3.7-pF crystal,
4.4
(5) (8)
ILPM3,XT3.7
excludes SVS(2)
μA
3.0 V
0.5
0.7
2.1
4.4
(also see Figure 5-2)
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
0.4
0.4
0.5
0.5
1.9
1.9
1.4
1.4
1.9
1.9
4.2
4.2
2.6
2.6
4.3
4.3
Low-power mode 3, VLO, excludes
SVS(9)
ILPM3,VLO
μA
μA
μA
1.2
1.1
1.2
9.5
7.9
9.5
0.36
0.36
0.5
0.47
0.47
0.6
Low-power mode 3, VLO, excludes SVS,
RAM powered down completely(9)
ILPM3,VLO, RAMoff
ILPM4,SVS
Low-power mode 4, includes SVS(10)
0.5
0.6
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Not applicable for devices with HF crystal oscillator only.
(3) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5 pF load.
(4) Low-power mode 2, crystal oscillator test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are
chosen to closely match the required 3.7-pF load.
(6) Low-power mode 2, VLO test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout and SVS included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
(7) Low-power mode 3, 12-pF crystal including SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution and due to additional idle
current. See the idle currents specified for the respective peripheral groups.
(8) Low-power mode 3, 3.7-pF crystal excluding SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE =
0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution and due to additional idle
current. See the idle currents specified for the respective peripheral groups.
(9) Low-power mode 3, VLO excluding SVS test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). RAM disabled (RCCTL0 = 5A55h). Current for
brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution and due to additional idle
current. See the idle currents specified for the respective peripheral groups.
(10) Low-power mode 4 including SVS test conditions:
Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution and due to additional idle
current. See the idle currents specified for the respective peripheral groups.
Copyright © 2016–2018, Texas Instruments Incorporated
Specifications
31
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External
Current (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 5-2
and Figure 5-3)
–40°C
25°C
60°C
85°C
PARAMETER
VCC
UNIT
TYP
MAX
TYP
MAX
1.1
TYP
MAX
TYP
MAX
2.2 V
3.0 V
2.2 V
3.0 V
0.3
0.3
0.3
0.3
0.4
0.4
1.7
1.7
1.2
1.2
4.0
4.0
2.5
2.5
ILPM4
Low-power mode 4, excludes SVS(11)
μA
9.3
0.37
0.37
Low-power mode 4, excludes SVS, RAM
powered down completely(11)
ILPM4,RAMoff
μA
1.0
7.8
1.6
Additional idle current if one or more
modules from Group A (see 表 6-3) are
activated in LPM3 or LPM4
IIDLE,GroupA
IIDLE,GroupB
IIDLE,GroupC
3.0 V
3.0 V
3.0 V
0.02
0.02
0.02
0.3
0.35
0.38
μA
μA
μA
Additional idle current if one or more
modules from Group B (see 表 6-3) are
activated in LPM3 or LPM4
2.1
2.3
Additional idle current if one or more
modules from Group C (see 表 6-3) are
activated in LPM3 or LPM4
(11) Low-power mode 4 excluding SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). RAM disabled (RCCTL0 = 5A55h).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution and due to additional idle
current. See the idle currents specified for the respective peripheral groups.
32
Specifications
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
5.8 Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (see Figure 5-4
and Figure 5-5)
–40°C
25°C
60°C
85°C
PARAMETER
VCC
UNIT
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
0.45
0.45
0.3
0.5
0.5
0.55
0.55
0.4
0.75
0.75
0.65
0.65
0.4
Low-power mode 3.5, 12-pF crystal
ILPM3.5,XT12
ILPM3.5,XT3.7
ILPM4.5,SVS
ILPM4.5
μA
(3) (4)
including SVS(2)
0.72
1.65
0.35
0.35
0.25
0.25
0.045
0.045
Low-power mode 3.5, 3.7-pF crystal
μA
(5) (6)
excluding SVS(2)
0.3
0.4
0.23
0.23
0.035
0.035
0.28
0.28
0.075
0.075
Low-power mode 4.5, including SVS(7)
Low-power mode 4.5, excluding SVS(8)
μA
0.42
0.4
0.75
0.55
0.15
0.15
μA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Not applicable for devices with HF crystal oscillator only.
(3) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5 pF load.
(4) Low-power mode 3.5, 1-pF crystal including SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1; CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are
chosen to closely match the required 3.7-pF load.
(6) Low-power mode 3.5, 3.7-pF crystal excluding SVS test conditions:
Current for RTC clocked by XT1 included.Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1; CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(7) Low-power mode 4.5 including SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1; CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
(8) Low-power mode 4.5 excluding SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1; CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Copyright © 2016–2018, Texas Instruments Incorporated
Specifications
33
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
5.9 Typical Characteristics, Low-Power Mode Supply Currents
3.5
3
2.5
2
3.0 V, SVS off
2.2 V, SVS off
3.0 V, SVS on
2.2 V, SVS on
3.0 V, SVS off
2.2 V, SVS off
3.0 V, SVS on
2.2 V, SVS on
3
2.5
2
1.5
1
1.5
1
0.5
0
0.5
-40
-20
0
20
Temperature (°C)
Figure 5-2. LPM3 Supply Current vs Temperature
40
60
80
100
-40
-20
0
20
Temperature (°C)
Figure 5-3. LPM4 Supply Current vs Temperature
40
60
80
100
0.65
0.5
2.2 V, SVS Off
3.0 V, SVS Off
2.2 V, SVS off
3.0 V, SVS off
2.2 V, SVS on
3.0 V, SVS on
0.45
0.4
0.6
0.55
0.5
0.35
0.3
0.45
0.4
0.25
0.2
0.35
0.3
0.15
0.1
0.25
0.2
0.05
0
-40
-20
0
20
40
60
80
100
-40
-20
0
20
Temperature (°C)
Figure 5-5. LPM4.5 Supply Current vs Temperature
40
60
80
100
Temperature (°C)
Figure 5-4. LPM3.5 Supply Current vs Temperature
34
Specifications
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
5.10 Typical Characteristics, Current Consumption per Module(1)
MODULE
Timer_A
TEST CONDITIONS
REFERENCE CLOCK
Module input clock
MIN
TYP
3
MAX
UNIT
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
nA
Timer_B
eUSCI_A
eUSCI_A
eUSCI_B
eUSCI_B
RTC_C
MPY
Module input clock
Module input clock
Module input clock
Module input clock
Module input clock
32 kHz
5
UART mode
6.3
4
SPI mode
SPI mode
4
I2C mode, 100 kbaud
4
100
28
3.3
3.3
86
66
Only from start to end of operation
Only from start to end of operation
Only from start to end of operation
256 Point Complex FFT, Data = nonzero
256 Point Complex FFT, Data = zero
MCLK
μA/MHz
μA/MHz
μA/MHz
CRC16
MCLK
CRC32
MCLK
LEA
MCLK
µA/MHz
(1) For other module currents not listed here, see the module-specific parameter sections.
5.11 Thermal Packaging Characteristics
THERMAL METRIC(1) (2)
PACKAGE
VALUE
27.5
12.5
4.4
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA
Junction-to-ambient thermal resistance, still air
Junction-to-case (top) thermal resistance
RθJC(TOP)
RθJB
Junction-to-board thermal resistance
QFN-48 (RGZ)
ΨJB
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
Junction-to-case (bottom) thermal resistance
Junction-to-ambient thermal resistance, still air
Junction-to-case (top) thermal resistance
4.4
ΨJT
0.2
RθJC(BOTTOM)
RθJA
0.8
53.2
14.3
24.7
24.4
0.6
RθJC(TOP)
RθJB
Junction-to-board thermal resistance
QFP-64 (PM)
QFP-80 (PN)
BGA-87 (ZVW)
ΨJB
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
Junction-to-ambient thermal resistance, still air
Junction-to-case (top) thermal resistance
ΨJT
RθJA
47.9
13.0
22.5
22.2
0.6
RθJC(TOP)
RθJB
Junction-to-board thermal resistance
ΨJB
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
Junction-to-ambient thermal resistance, still air
Junction-to-case (top) thermal resistance
ΨJT
RθJA
60.6
18.1
31.8
30.1
0.7
RθJC(TOP)
RθJB
Junction-to-board thermal resistance
ΨJB
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
ΨJT
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (RθJC) value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC
standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
版权 © 2016–2018, Texas Instruments Incorporated
Specifications
35
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
5.12 Timing and Switching Characteristics
5.12.1 Power Supply Sequencing
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up,
power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the
limits specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the
device including erroneous writes to RAM and FRAM.
表 5-1 lists the power ramp requirements.
表 5-1. Brownout and Device Reset Power Ramp Requirements
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VVCC_BOR– Brownout power-down level(1)
VVCC_BOR+ Brownout power-up level(1)
TEST CONDITIONS
MIN
0.73
0.79
MAX UNIT
| dDVCC/dt | < 3 V/s
| dDVCC/dt | < 3 V/s(2)
1.66
1.75
V
V
(1) Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR
resets, the supply voltage must change by less than 0.05 volts per microsecond (±0.05 V/µs). Following the data sheet recommendation
for capacitor CDVCC should limit the slopes accordingly.
(2) The brownout levels are measured with a slowly changing supply.
表 5-2 lists the supply voltage supervisor characteristics.
表 5-2. SVS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
170
MAX UNIT
ISVSH,LPM
VSVSH-
SVSH current consumption, low power modes
SVSH power-down level(1)
SVSH power-up level(1)
300
1.85
1.99
150
10
nA
V
1.75
1.77
40
1.80
1.88
VSVSH+
V
VSVSH_hys
tPD,SVSH, AM
SVSH hysteresis
mV
µs
SVSH propagation delay, active mode
dVVcc/dt = –10 mV/µs
(1) For additional information, see the Dynamic Voltage Scaling Power Solution for MSP430 Devices With Single-Channel LDO Reference
Design.
5.12.2 Reset Timing
表 5-3 lists the input requirements of the reset pin.
表 5-3. Reset Input
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC
MIN
MAX UNIT
t(RST)
(1) Not applicable if RST/NMI pin configured as NMI.
External reset pulse duration on RST(1)
2.2 V, 3.0 V
2
µs
36
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
5.12.3 Clock Specifications
LFXTCLK (see Table 5-4) is a low-frequency oscillator that can be used either with low-frequency 32768-
Hz watch crystals, standard crystals, resonators, or external clock sources in the 50 kHz or below range.
When in bypass mode, LFXTCLK can be driven with an external square-wave signal.
Table 5-4. Low-Frequency Crystal Oscillator, LFXT(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
180
TA = 25°C, CL,eff = 3.7 pF, ESR ≈ 44 kΩ
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {1},
TA = 25°C, CL,eff = 6 pF, ESR ≈ 40 kΩ
185
225
IVCC.LFXT
Current consumption
3.0 V
nA
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {2},
TA = 25°C, CL,eff = 9 pF, ESR ≈ 40 kΩ
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF, ESR ≈ 40 kΩ
330
LFXT oscillator crystal
frequency
fLFXT
LFXTBYPASS = 0
32768
Hz
Measured at ACLK,
fLFXT = 32768 Hz
DCLFXT
fLFXT,SW
DCLFXT, SW
LFXT oscillator duty cycle
30%
70%
LFXT oscillator logic-level
square-wave input frequency
LFXTBYPASS = 1(2) (3)
10.5 32.768
50 kHz
70%
LFXT oscillator logic-level
square-wave input duty cycle
LFXTBYPASS = 1
30%
210
300
2
LFXTBYPASS = 0, LFXTDRIVE = {1},
fLFXT = 32768 Hz, CL,eff = 6 pF
Oscillation allowance for
LF crystals(4)
OALFXT
kΩ
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32768 Hz, CL,eff = 12.5 pF
Integrated load capacitance at
LFXIN terminal(5) (6)
CLFXIN
pF
pF
Integrated load capacitance at
LFXOUT terminal(5) (6)
CLFXOUT
2
(1) To improve EMI on the LFXT oscillator, the following guidelines should be observed.
•
•
•
•
•
•
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins LFXIN and LFXOUT.
Avoid running PCB traces underneath or adjacent to the LFXIN and LFXOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator LFXIN and LFXOUT pins.
If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this datasheet. Duty cycle requirements are defined by DCLFXT, SW
.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
•
•
•
•
For LFXTDRIVE = {0}, CL,eff = 3.7 pF
For LFXTDRIVE = {1}, CL,eff = 6 pF
For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 9 pF
For LFXTDRIVE = {3}, 9 pF ≤ CL,eff ≤ 12.5 pF
(5) This represents all the parasitic capacitance present at the LFXIN and LFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN × COUT / (CIN + COUT), where CIN and COUT are the
total capacitance at the LFXIN and LFXOUT terminals, respectively.
(6) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds
additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance
of the selected crystal is met.
Copyright © 2016–2018, Texas Instruments Incorporated
Specifications
37
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
Table 5-4. Low-Frequency Crystal Oscillator, LFXT(1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 32768 Hz
LFXTBYPASS = 0, LFXTDRIVE = {0},
TA = 25°C, CL,eff = 3.7 pF,
3.0 V
800
tSTART,LFXT
Start-up time(7)
ms
fOSC = 32768 Hz
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF
3.0 V
1000
fFault,LFXT
Oscillator fault frequency(8) (9)
0
3500
Hz
(7) Includes startup counter of 1024 clock cycles.
(8) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specification may set the
flag. A static condition or stuck at fault condition will set the flag.
(9) Measured with logic-level input frequency but also applies to operation with crystals.
HFXTCLK (see Table 5-5) is a high-frequency oscillator that can be used with standard crystals or
resonators in the 4‑MHz to 24-MHz range. When in bypass mode, HFXTCLK can be driven with an
external square-wave signal.
Table 5-5. High-Frequency Crystal Oscillator, HFXT(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0,
HFFREQ = 1(2), TA = 25°C,
75
CL,eff = 18 pF, typical ESR, Cshunt
fOSC = 8 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 1, TA = 25°C,
CL,eff = 18 pF, typical ESR, Cshunt
120
190
250
HFXT oscillator crystal current
HF mode at typical ESR
IDVCC.HFXT
3.0 V
μA
fOSC = 16 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 2,
HFFREQ = 2, TA = 25°C
CL,eff = 18 pF, typical ESR, Cshunt
fOSC = 24 MHz
HFXTBYPASS = 0, HFXTDRIVE = 3,
HFFREQ = 3, TA = 25°C
CL,eff = 18 pF, typical ESR, Cshunt
(2) (3)
HFXTBYPASS = 0, HFFREQ = 1
HFXTBYPASS = 0, HFFREQ = 2
HFXTBYPASS = 0, HFFREQ = 3
4
8.01
8
HFXT oscillator crystal
frequency, crystal mode
(3)
(3)
fHFXT
16 MHz
24
16.01
Measured at SMCLK,
fHFXT = 16 MHz
DCHFXT
HFXT oscillator duty cycle.
40%
50%
60%
4
HFXTBYPASS = 1, HFFREQ = 0(4) (3)
HFXTBYPASS = 1, HFFREQ = 1(4) (3)
HFXTBYPASS = 1, HFFREQ = 2(4) (3)
HFXTBYPASS = 1, HFFREQ = 3(4) (3)
0.9
4.01
HFXT oscillator logic-level
square-wave input frequency,
bypass mode
8
fHFXT,SW
MHz
16
8.01
16.01
24
HFXT oscillator logic-level
square-wave input duty cycle
DCHFXT, SW
HFXTBYPASS = 1
40%
60%
(1) To improve EMI on the HFXT oscillator the following guidelines should be observed.
•
•
•
•
•
•
Keep the traces between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins HFXIN and HFXOUT.
Avoid running PCB traces underneath or adjacent to the HFXIN and HFXOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator HFXIN and HFXOUT pins.
If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) HFFREQ = {0} is not supported for HFXT crystal mode of operation.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this datasheet. Duty cycle requirements are defined by DCHFXT, SW
.
38
Specifications
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
Table 5-5. High-Frequency Crystal Oscillator, HFXT(1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
HFXTBYPASS = 0, HFXTDRIVE = 0,
HFFREQ = 1(2)
,
450
fHFXT,HF = 4 MHz, CL,eff = 16 pF
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 1
fHFXT,HF = 8 MHz, CL,eff = 16 pF
320
200
200
1.6
Oscillation allowance for
HFXT crystals(5)
OAHFXT
Ω
HFXTBYPASS = 0, HFXTDRIVE = 2,
HFFREQ = 2
fHFXT,HF = 16 MHz, CL,eff = 16 pF
HFXTBYPASS = 0, HFXTDRIVE = 3,
HFFREQ = 3
fHFXT,HF = 24 MHz, CL,eff = 16 pF
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0,
HFFREQ = 1, TA = 25°C, CL,eff = 16 pF
tSTART,HFXT
Startup time(6)
3.0 V
ms
pF
fOSC = 24 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 3,
HFFREQ = 3, TA = 25°C, CL,eff = 16 pF
0.6
Integrated load capacitance at
HFXIN terminaI(7) (8)
CHFXIN
CHFXOUT
fFault,HFXT
2
2
Integrated load capacitance at
HFXOUT terminaI(7) (8)
Oscillator fault frequency(9) (10)
pF
0
800 kHz
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(6) Includes startup counter of 1024 clock cycles.
(7) This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN × COUT / (CIN + COUT), where CIN and COUT is the
total capacitance at the HFXIN and HFXOUT terminals, respectively.
(8) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF. The PCB adds
additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance
of the selected crystal is met.
(9) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX might set the flag. A static
condition or stuck at fault condition will set the flag.
(10) Measured with logic-level input frequency but also applies to operation with crystals.
Copyright © 2016–2018, Texas Instruments Incorporated
Specifications
39
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
The DCO (see Table 5-6) is an internal digitally controlled oscillator (DCO) with selectable frequencies.
Table 5-6. DCO
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 0,
DCORSEL = 1, DCOFSEL = 0
DCO frequency range
1 MHz, trimmed
fDCO1
1
±3.5%
MHz
DCO frequency range
2.7 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 1
fDCO2.7
fDCO3.5
fDCO4
2.667 ±3.5%
3.5 ±3.5%
MHz
MHz
MHz
DCO frequency range
3.5 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 2
DCO frequency range
4 MHz, trimmed
Measured at SMCLK, divide by 1
DCORSEL = 0, DCOFSEL = 3
4
±3.5%
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 4,
DCORSEL = 1, DCOFSEL = 1
DCO frequency range
5.3 MHz, trimmed
fDCO5.3
fDCO7
fDCO8
5.333 ±3.5%
MHz
MHz
MHz
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 5,
DCORSEL = 1, DCOFSEL = 2
DCO frequency range
7 MHz, trimmed
7
8
±3.5%
±3.5%
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 6,
DCORSEL = 1, DCOFSEL = 3
DCO frequency range
8 MHz, trimmed
DCO frequency range
16 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 1, DCOFSEL = 4
fDCO16
fDCO21
fDCO24
16 ±3.5%
21 ±3.5%
24 ±3.5%
MHz
MHz
MHz
DCO frequency range
21 MHz, trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 5
DCO frequency range
24 MHz, trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 6
Measured at SMCLK, divide by 1,
No external divide, all DCORSEL and
DCOFSEL settings except DCORSEL = 1
with DCOFSEL = 5, and DCORSEL = 1 with
DCOFSEL = 6
fDCO,DC
Duty cycle
48%
50%
52%
3
Based on fsignal = 10 kHz and DCO used for
12-bit SAR ADC sampling source. This
achieves greather than 74-dB SNR due to
jitter (that is, limited by ADC performance).
tDCO, JITTER
DCO jitter
2
ns
dfDCO/dT
DCO temperature drift(1)
3.0 V
0.01
%/ºC
(1) Calculated using the box method: (MAX(–40°C to 85ºC) - MIN(–40°C to 85ºC)) / MIN(–40°C to 85ºC) / (85ºC - (-40ºC))
40
Specifications
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
The VLO is an internal very-low-power low-frequency oscillator with 10-kHz typical frequency (see
Table 5-7).
Table 5-7. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
100
9.4
MAX UNIT
nA
IVLO
Current consumption
(1)
fVLO
VLO frequency
Measured at ACLK
6
14 kHz
%/°C
dfVLO/dT
VLO frequency temperature drift
Measured at ACLK(2)
Measured at ACLK(3)
Measured at ACLK
0.2
dfVLO/dVCC VLO frequency supply voltage drift
fVLO,DC Duty cycle
0.7
%/V
40%
50%
60%
(1) VLO frequency may decrease in LPM3 or LPM4 mode. The typical ratio of VLO freuqencies (LPM3/4 to AM) is 85%.
(2) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(3) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
The module oscillator (MODOSC) is an internal low-power oscillator with 5-MHz typical frequency (see
Table 5-8).
Table 5-8. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Enabled
MIN
TYP
25
MAX UNIT
IMODOSC
Current consumption
μA
fMODOSC
MODOSC frequency
MODOSC frequency temperature drift(1)
4.0
4.8
5.4
MHz
%/℃
%/V
fMODOSC/dT
0.08
1.4
fMODOSC/dVCC MODOSC frequency supply voltage drift(2)
DCMODOSC Duty cycle
Measured at SMCLK, divide by 1
40%
50%
60%
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
版权 © 2016–2018, Texas Instruments Incorporated
Specifications
41
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
5.12.4 Wake-up Characteristics
Table 5-9 lists the wake-up times.
Table 5-9. Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-6 and
Figure 5-7)
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX UNIT
(Additional) wake-up time to activate the FRAM
in AM if previously disabled by the FRAM
controller or from an LPM if immediate
activation is selected for wakeup
tWAKE-UP FRAM
6
10
μs
400 ns +
1.5 / fDCO
tWAKE-UP LPM0
Wake-up time from LPM0 to active mode(1)
2.2 V, 3.0 V
tWAKE-UP LPM1
tWAKE-UP LPM2
Wake-up time from LPM1 to active mode(1)
Wake-up time from LPM2 to active mode(1)
2.2 V, 3.0 V
2.2 V, 3.0 V
6
6
μs
μs
6.6 +
9.6 +
tWAKE-UP LPM3
Wake-up time from LPM3 to active mode(1)
2.2 V, 3.0 V
2.2 V, 3.0 V
μs
μs
2.0 / fDCO 2.5 / fDCO
6.6 + 9.6 +
2.0 / fDCO 2.5 / fDCO
tWAKE-UP LPM4
Wake-up time from LPM4 to active mode(1)
Wake-up time from LPM3.5 to active mode(2)
tWAKE-UP LPM3.5
2.2 V, 3.0 V
2.2 V, 3.0 V
2.2 V, 3.0 V
250
250
0.4
350
350
0.8
μs
μs
SVSHE = 1
SVSHE = 0
tWAKE-UP LPM4.5
Wake-up time from LPM4.5 to active mode(2)
ms
Wake-up time from a RST pin triggered reset to
active mode(2)
tWAKE-UP-RST
tWAKE-UP-BOR
2.2 V, 3.0 V
2.2 V, 3.0 V
300
0.5
403
1
μs
(2)
Wake-up time from power-up to active mode
ms
(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first
externally observable MCLK clock edge with MCLKREQEN = 1. This time includes the activation of the FRAM during wake up. With
MCLKREQEN = 0, the externally observable MCLK clock is gated one additional cycle.
(2) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
5.12.4.1 Typical Characteristics, Average LPM Currents vs Wake-up Frequency
5000
LPM0
LPM1
LPM2,XT12
LPM3,XT12
1000
LPM3.5,XT12
100
10
1
0.1
0.001
0.01
0.1
1
10
100
1000
10000
100000
Wake-up Frequency (Hz)
NOTE: The average wake-up current does not include the energy required in active mode; for example, for an interrupt
service routine (ISR) or to reconfigure the device.
Figure 5-6. Average LPM Currents vs Wake-up Frequency at 25°C
42
Specifications
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
5000
LPM0
LPM1
LPM2,XT12
LPM3,XT12
LPM3.5,XT12
1000
100
10
1
0.1
0.001
0.01
0.1
1
10
100
1000
10000
100000
Wake-up Frequency (Hz)
NOTE: The average wake-up current does not include the energy required in active mode; for example, for an ISR or to
reconfigure the device.
Figure 5-7. Average LPM Currents vs Wake-up Frequency at 85°C
Table 5-10 lists the typical charge required to wake up from LPM or reset.
Table 5-10. Typical Wake-up Charge(1)
TEST
CONDITIONS
PARAMETER
MIN
TYP
16.5
3.8
21
MAX UNIT
nAs
Charge used for activating the FRAM in AM or during wake-up
from LPM0 if previously disabled by the FRAM controller.
QWAKE-UP FRAM
QWAKE-UP LPM0
QWAKE-UP LPM1
QWAKE-UP LPM2
QWAKE-UP LPM3
Charge used for wake-up from LPM0 to active mode (with
FRAM active)
nAs
Charge used for wake-up from LPM1 to active mode (with
FRAM active)
nAs
Charge used for wake-up from LPM2 to active mode (with
FRAM active)
22
nAs
Charge used for wake-up from LPM3 to active mode (with
FRAM active)
25
nAs
Charge used for wake-up from LPM4 to active mode (with
FRAM active)
Charge used for wake-up from LPM3.5 to active mode(2)
QWAKE-UP LPM4
QWAKE-UP LPM3.5
QWAKE-UP LPM4.5
25
nAs
nAs
121
123
121
SVSHE = 1
SVSHE = 0
Charge used for wake-up from LPM4.5 to active mode(2)
nAs
nAs
Charge used for reset from RST or BOR event to active
mode(2)
QWAKE-UP-RESET
102
(1) Charge used during the wake-up time from a given low-power mode to active mode. This does not include the energy required in active
mode (for example, for an ISR).
(2) Charge required until start of user code. This does not include the energy required to reconfigure the device.
版权 © 2016–2018, Texas Instruments Incorporated
Specifications
43
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
5.12.5 Digital I/Os
Table 5-11 lists the characteristics of the digital inputs.
Table 5-11. Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
1.2
TYP
MAX UNIT
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
1.65
V
VIT+
VIT–
Vhys
Positive-going input threshold voltage
1.65
0.55
0.75
0.44
0.60
2.25
1.00
V
Negative-going input threshold voltage
1.35
0.98
V
Input voltage hysteresis (VIT+ – VIT–
Pullup or pulldown resistor
)
1.30
For pullup: VIN = VSS
,
RPull
CI,dig
CI,ana
20
35
3
50
kΩ
pF
pF
For pulldown: VIN = VCC
Input capacitance, digital only port pins
VIN = VSS or VCC
Input capacitance, port pins with shared
analog functions(1)
VIN = VSS or VCC
5
2.2 V,
3.0 V
(2)(3)
Ilkg(Px.y)
t(int)
High-impedance input leakage current
See
–20
20
2
+20
nA
ns
µs
External interrupt timing (external trigger
pulse duration to set interrupt flag)(4)
Ports with interrupt capability (see 节 2.2 V,
1.4 and Table 4-2)
3.0 V
2.2 V,
3.0 V
t(RST)
External reset pulse duration on RST(5)
(1) If the port pins PJ.4/LFXIN and PJ.5/LFXOUT are used as digital I/Os, they are connected by a 4-pF capacitor and a 35-MΩ resistor in
series. At frequencies of approximately 1 kHz and lower, the 4-pF capacitor can add to the pin capacitance of PJ.4/LFXIN and/or
PJ.5/LFXOUT.
(2) The input leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
(3) The input leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
(4) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int)
.
(5) Not applicable if RST/NMI pin configured as NMI .
44
Specifications
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
Table 5-12 lists the characteristics of the digital outputs.
Table 5-12. Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA(1)
VCC
MIN
VCC – 0.25
VCC – 0.60
VCC – 0.25
VCC – 0.60
VSS
TYP
MAX UNIT
VCC
2.2 V
I(OHmax) = –3 mA(2)
I(OHmax) = –2 mA(1)
I(OHmax) = –6 mA(2)
I(OLmax) = 1 mA(1)
I(OLmax) = 3 mA(2)
I(OLmax) = 2 mA(1)
I(OLmax) = 6 mA(2)
VCC
High-level output voltage
(see Figure 5-10 and Figure 5-11)
VOH
V
VCC
3.0 V
2.2 V
3.0 V
VCC
VSS + 0.25
VSS
VSS + 0.60
VSS + 0.25
VSS + 0.60
Low-level output voltage
(see Figure 5-8 and Figure 5-9)
VOL
V
VSS
VSS
2.2 V
3.0 V
2.2 V
16
(4) (5)
fPx.y
Port output frequency (with load)(3) CL = 20 pF, RL
MHz
MHz
16
ACLK, MCLK, or SMCLK at
configured output port,
CL = 20 pF(5)
16
fPort_CLK Clock output frequency(3)
3.0 V
16
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
4
3
4
3
6
4
6
4
15
15
15
15
15
15
15
15
Port output rise time, digital only
port pins
trise,dig
CL = 20 pF
CL = 20 pF
CL = 20 pF
CL = 20 pF
ns
ns
ns
ns
Port output fall time, digital only port
tfall,dig
pins
Port output rise time, port pins with
trise,ana
shared analog functions
Port output fall time, port pins with
tfall,ana
shared analog functions
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
(3) The port can output frequencies at least up to the specified limit, and it might support higher frequencies.
(4) A resistive divider with 2 × R1 and R1 = 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the
divider. CL = 20 pF is connected from the output to VSS
.
(5) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Copyright © 2016–2018, Texas Instruments Incorporated
Specifications
45
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
5.12.5.1 Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
15
10
5
30
20
10
0
25°C
85°C
25°C
85°C
P1.1
P1.1
0
0
0.5
1
1.5
2
0
0.5
1
1.5
2
2.5
3
Low-Level Output Voltage (V)
Low-Level Output Voltage (V)
C001
C001
VCC = 2.2 V
VCC = 3.0 V
Figure 5-8. Typical Low-Level Output Current vs
Low-Level Output Voltage
Figure 5-9. Typical Low-Level Output Current vs
Low-Level Output Voltage
0
0
25°C
85°C
25°C
85°C
-5
-10
-15
-10
-20
-30
P1.1
2
P1.1
0
0.5
1
1.5
0
0.5
1
1.5
2
2.5
3
High-Level Output Voltage (V)
High-Level Output Voltage (V)
C001
C001
VCC = 2.2 V
VCC = 3.0 V
Figure 5-10. Typical High-Level Output Current vs
High-Level Output Voltage
Figure 5-11. Typical High-Level Output Current vs
High-Level Output Voltage
46
Specifications
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
Table 5-13 lists the supported oscillation frequencies on the digital I/Os.
Table 5-13. Pin-Oscillator Frequency, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Px.y, CL = 10 pF(1)
Px.y, CL = 20 pF(1)
VCC
3.0 V
3.0 V
MIN
TYP
1200
650
MAX UNIT
kHz
Pin-oscillator frequency
(see Figure 5-12 and Figure 5-13)
foPx.y
kHz
(1) CL is the external load capacitance connected from the output to VSS and includes all parasitic effects such as PCB traces.
5.12.5.2 Typical Characteristics, Pin-Oscillator Frequency
2000
2000
Best Fit
25°C
Best Fit
25°C
85°C
85°C
1000
1000
800
700
800
700
600
500
600
500
400
300
400
300
200
200
100
100
10
VCC = 2.2 V
20
30 40 50 60 7080 100
CL, Load Capacitance (pF)
200
10
VCC = 3.0 V
20
30 40 50 60 7080 100
CL, Load Capacitance (pF)
200
One output active at a time.
One output active at a time.
Figure 5-12. Typical Oscillation Frequency vs
Load Capacitance
Figure 5-13. Typical Oscillation Frequency vs
Load Capacitance
版权 © 2016–2018, Texas Instruments Incorporated
Specifications
47
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
5.12.6 LEA (Low-Energy Accelerator) (MSP430FR599x Only)
The LEA module is a hardware engine designed for operations that involve vector-based signal
processing. Table 5-14 lists the performance characteristics of the LEA module.
Table 5-14. Low Energy Accelerator Performance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Frequency for specified
performance
fLEA
MCLK
16
MHz
LEA subsystem energy on Complex FFT 128-point Q.15 with
fast Fourier transform random data in LEA-RAM
VCore = 3 V,
MCLK = 16 MHz
W_LEA_FFT
W_LEA_FIR
350
2.6
nJ
µJ
LEA subsystem energy on Real FIR on random Q.31 data with VCore = 3 V,
finite impulse response
128 taps on 24 points
MCLK = 16 MHz
On 32 Q.31 elements with random
value out of LEA-RAM with linear
address increment
LEA subsystem energy on
additions
VCore = 3 V,
MCLK = 16 MHz
W_LEA_ADD
6.6
nJ
5.12.7 Timer_A and Timer_B
Timer_A and Timer_B are 16-bit timers and counters with multiple capture/compare registers. Table 5-15
lists the Timer_A characteristics, and Table 5-16 lists the Timer_B characteristics.
Table 5-15. Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK or ACLK,
fTA
Timer_A input clock frequency
External: TACLK,
2.2 V, 3.0 V
16 MHz
Duty cycle = 50% ±10%
All capture inputs, minimum pulse duration required
for capture
tTA,cap
Timer_A capture timing
2.2 V, 3.0 V
20
ns
Table 5-16. Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK or ACLK,
fTB
Timer_B input clock frequency
External: TBCLK,
2.2 V, 3.0 V
16 MHz
Duty cycle = 50% ±10%
All capture inputs, minimum pulse duration required
for capture
tTB,cap
Timer_B capture timing
2.2 V, 3.0 V
20
ns
48
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
5.12.8 eUSCI
The enhanced universal serial communication interface (eUSCI) supports multiple serial communication
modes with one hardware module. The eUSCI_A module supports UART and SPI modes. The eUSCI_B
module supports I2C and SPI modes.
Table 5-17 lists the UART clock frequencies.
Table 5-17. eUSCI (UART Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
Internal: SMCLK or ACLK,
External: UCLK,
feUSCI
eUSCI input clock frequency
16 MHz
Duty cycle = 50% ±10%
fBITCLK
BITCLK clock frequency (equals baud rate in MBaud)
4
MHz
Table 5-18 lists the UART operating characteristics.
Table 5-18. eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UCGLITx = 0
VCC
MIN
5
MAX UNIT
30
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
20
35
50
90
ns
tt
UART receive deglitch time(1)
2.2 V, 3.0 V
160
220
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. Thus the selected deglitch
time can limit the maximum useable baud rate. To ensure that pulses are correctly recognized, their duration should exceed the
maximum specification of the deglitch time.
Copyright © 2016–2018, Texas Instruments Incorporated
Specifications
49
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
Table 5-19 lists the SPI master mode clock frequencies.
Table 5-19. eUSCI (SPI Master Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Internal: SMCLK or ACLK,
Duty cycle = 50% ±10%
MIN
MAX UNIT
feUSCI eUSCI input clock frequency
16
MHz
Table 5-20 lists the SPI master mode operating characteristics.
Table 5-20. eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
STE lead time, STE active to clock
UCSTEM = 1, UCMODEx = 01 or 10
1
UCxCLK
cycles
STE lag time, Last clock to STE
inactive
UCSTEM = 1, UCMODEx = 01 or 10
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 0, UCMODEx = 01 or 10
1
STE access time, STE active to
SIMO data out
2.2 V,
3.0 V
60
80
ns
ns
STE disable time, STE inactive to
SOMI high impedance
2.2 V,
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
40
40
0
tSU,MI
SOMI input data setup time
SOMI input data hold time
SIMO output data valid time(2)
SIMO output data hold time(3)
ns
ns
ns
ns
tHD,MI
0
11
10
UCLK edge to SIMO valid,
CL = 20 pF
tVALID,MO
0
0
tHD,MO
CL = 20 pF
(1) fUCxCLK = 1/2 tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)
)
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-14 and Figure 5-15.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-
14 and Figure 5-15.
50
Specifications
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
UCMODEx = 01
tSTE,LEAD
tSTE,LAG
STE
UCMODEx = 10
CKPL = 0
1/fUCxCLK
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
SIMO
tHD,MO
tVALID,MO
tSTE,ACC
tSTE,DIS
Figure 5-14. SPI Master Mode, CKPH = 0
UCMODEx = 01
STE
tSTE,LEAD
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
SIMO
tHD,MO
tVALID,MO
tSTE,DIS
tSTE,ACC
Figure 5-15. SPI Master Mode, CKPH = 1
Copyright © 2016–2018, Texas Instruments Incorporated
Specifications
51
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
Table 5-21 lists the SPI slave mode operating characteristics.
Table 5-21. eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
45
40
2
MAX UNIT
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
tSU,SI
STE lead time, STE active to clock
ns
STE lag time, Last clock to STE inactive
ns
3
45
ns
40
STE access time, STE active to SOMI data out
50
ns
45
STE disable time, STE inactive to SOMI high
impedance
4
4
7
7
SIMO input data setup time
SIMO input data hold time
SOMI output data valid time(2)
SOMI output data hold time(3)
ns
ns
tHD,SI
35
ns
35
UCLK edge to SOMI valid,
CL = 20 pF
tVALID,SO
0
0
tHD,SO
CL = 20 pF
ns
(1) fUCxCLK = 1/2 tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)
)
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-16 and Figure 5-17.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-16
and Figure 5-17.
52
Specifications
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
UCMODEx = 01
tSTE,LEAD
tSTE,LAG
STE
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tSU,SI
tLOW/HIGH
tLOW/HIGH
tHD,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 5-16. SPI Slave Mode, CKPH = 0
UCMODEx = 01
UCMODEx = 10
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 5-17. SPI Slave Mode, CKPH = 1
Copyright © 2016–2018, Texas Instruments Incorporated
Specifications
53
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
Table 5-22 lists the I2C mode operating characteristics.
Table 5-22. eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK or ACLK,
External: UCLK,
feUSCI
eUSCI input clock frequency
16 MHz
Duty cycle = 50% ±10%
fSCL
SCL clock frequency
2.2 V, 3.0 V
2.2 V, 3.0 V
0
4.0
0.6
4.7
0.6
0
400 kHz
µs
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
2.2 V, 3.0 V
µs
tHD,DAT
tSU,DAT
Data hold time
Data setup time
2.2 V, 3.0 V
2.2 V, 3.0 V
ns
ns
100
4.0
0.6
50
fSCL = 100 kHz
fSCL > 100 kHz
UCGLITx = 0
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
UCCLTOx = 1
UCCLTOx = 2
UCCLTOx = 3
tSU,STO
Setup time for STOP
2.2 V, 3.0 V
µs
250
25
125
ns
Pulse duration of spikes suppressed by
input filter
tSP
2.2 V, 3.0 V
12.5
6.3
62.5
31.5
27
30
33
tTIMEOUT
Clock low time-out
2.2 V, 3.0 V
ms
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-18. I2C Mode Timing
54
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
5.12.9 ADC12_B
The ADC12_B module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit
SAR core, sample select control, and up to 32 independent conversion-and-control buffers. The
conversion-and-control buffer allows up to 32 independent analog-to-digital converter (ADC) samples to be
converted and stored without any CPU intervention.
Table 5-23 lists the power supply and input range conditions.
Table 5-23. 12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN NOM
MAX UNIT
V(Ax)
Analog input voltage range(1)
All ADC12 analog input pins Ax
0
AVCC
199
V
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 0,
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
145
I(ADC12_B)
single-ended
mode
Operating supply current into
µA
AVCC plus DVCC terminals(2)(3) REFON = 0, ADC12SHTx = 0,
ADC12DIV = 0
140
175
170
85
190
245
230
125
120
165
160
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 1,
I(ADC12_B)
differential
mode
Operating supply current into
µA
µA
µA
AVCC plus DVCC terminals(2) (3) REFON = 0, ADC12SHTx= 0,
ADC12DIV = 0
I(ADC12_B)
fADC12CLK = MODCLK / 4, ADC12ON = 1,
ADC12PWRMD = 1, ADC12DIF = 0,
Operating supply current into
single-ended
low-power
mode
AVCC plus DVCC terminals(2) (3) REFON = 0, ADC12SHTx = 0,
ADC12DIV = 0
83
fADC12CLK = MODCLK / 4, ADC12ON = 1,
ADC12PWRMD = 1, ADC12DIF = 1,
110
109
I(ADC12_B)
differential low-
power mode
Operating supply current into
AVCC plus DVCC terminals(2) (3) REFON = 0, ADC12SHTx= 0,
ADC12DIV = 0
Only one terminal Ax can be selected at
one time
CI
RI
Input capacitance
2.2 V
10
15
pF
>2 V
<2 V
0.5
1
4
Input MUX ON-resistance
0 V ≤ V(Ax) ≤ AVCC
kΩ
10
(1) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
(2) The internal reference supply current is not included in current consumption parameter I(ADC12_B)
.
(3) Approximately 60% (typical) of the total current into the AVCC and DVCC terminals is from AVCC.
Copyright © 2016–2018, Texas Instruments Incorporated
Specifications
55
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
Table 5-24 lists the timing parameters.
Table 5-24. 12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
For specified performance of ADC12 linearity parameters
with ADC12PWRMD = 0.
If ADC12PWRMD = 1, the maximum is 1/4 of the value
shown here.
Frequency for specified
performance
fADC12CLK
0.45
5.4 MHz
Frequency for reduced
performance
fADC12OSC Internal oscillator(1)
fADC12CLK
Linearity parameters have reduced performance
32.768
4.8
kHz
ADC12DIV = 0, fADC12CLK = fADC12OSC from MODCLK
4
5.4 MHz
REFON = 0, Internal oscillator,
fADC12CLK = fADC12OSC from MODCLK, ADC12WINC = 0
2.6
3.5
µs
tCONVERT
Conversion time
External fADC12CLK from ACLK, MCLK, or SMCLK,
(2)
ADC12SSEL ≠ 0
Turnon settling time of the
ADC
(3)
tADC12ON
tADC12OFF
See
100
ns
ns
Time ADC must be off before tADC12OFF must be met to make sure that tADC12ON time
it can be turned on again
100
1
holds
All pulse sample mode
(ADC12SHP = 1) and extended
sample mode (ADC12SHP = 0)
with buffered reference
(ADC12VRSEL = 0x1, 0x3, 0x5,
0x7, 0x9, 0xB, 0xD, 0xF)
RS = 400 Ω, RI = 4 kΩ,
tSample
Sampling time
µs
CI = 15 pF, Cpext= 8 pF(4)
Extended sample mode
(ADC12SHP = 0) with
unbuffered reference
(ADC12VRSEL = 0x0, 0x2, 0x4,
0x6, 0xC, 0xE)
(5)
(1) The ADC12OSC is sourced directly from MODOSC inside the UCS.
(2) 14 × 1 / fADC12CLK. If ADC12WINC = 1 then 15 × 1 / fADC12CLK
(3) The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
(4) Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB: tsample = ln(2n+2) x (RS + RI) x (CI + Cpext), where n = ADC
resolution = 12, RS= external source resistance, Cpext = external parasitic capacitance.
(5) 6 × 1 / fADC12CLK
56
Specifications
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
Table 5-25 lists the linearity parameters.
Table 5-25. 12-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Integral linearity error (INL) for
differential input
±1.8
LSB
±2.2
With external voltage reference (ADC12VRSEL = 0x2,
0x3, 0x4, 0x14, 0x15), 1.2 V ≤ (VR+ – VR–) ≤ AVCC
EI
Integral linearity error (INL) for
single-ended inputs
With external voltage reference (ADC12VRSEL = 0x2,
0x3, 0x4, 0x14, 0x15)
ED
EO
Differential linearity error (DNL)
–0.99
+1.0
±1.5
LSB
mV
ADC12VRSEL = 0x1 without TLV calibration,
TLV calibration data can be used to improve the
(1) (2)
Offset error
±0.5
(3)
parameter
With internal voltage reference VREF = 2.5 V
(ADC12VRSEL = 0x1, 0x7, 0x9, 0xB, or 0xD)
±0.2%
±0.2%
±1.7%
±2.5%
With internal voltage reference VREF = 1.2 V
(ADC12VRSEL = 0x1, 0x7, 0x9, 0xB, or 0xD)
With external voltage reference without internal buffer
(ADC12VRSEL = 0x2 or 0x4) without TLV calibration,
VR+ = 2.5 V, VR– = AVSS
EG
Gain error
±1
±2
±3
LSB
With external voltage reference with internal buffer
(ADC12VRSEL = 0x3),
±27
VR+ = 2.5 V, VR– = AVSS
With internal voltage reference VREF = 2.5 V
(ADC12VRSEL = 0x1, 0x7, 0x9, 0xB, or 0xD)
±0.2%
±0.2%
±1.8%
With internal voltage reference VREF = 1.2 V
(ADC12VRSEL = 0x1, 0x7, 0x9, 0xB, or 0xD)
±2.6%
With external voltage reference without internal buffer
(ADC12VRSEL = 0x2 or 0x4) without TLV calibration,
VR+ = 2.5 V, VR– = AVSS
ET
Total unadjusted error
±1
±1
±5
LSB
With external voltage reference with internal buffer
(ADC12VRSEL = 0x3),
±28
VR+ = 2.5 V, VR– = AVSS
(1) Offset is measured as the input voltage (at which ADC output transitions from 0 to 1) minus 0.5 LSB.
(2) Offset increases as IR drop increases when VR– is AVSS.
(3) For details, see the Device Descriptor Table section in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx
Family User's Guide.
Copyright © 2016–2018, Texas Instruments Incorporated
Specifications
57
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
Table 5-26 lists the dynamic performance characteristics when using an external reference.
Table 5-26. 12-Bit ADC, Dynamic Performance With External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Resolution Number of no missing code output-code bits
12
bits
Signal-to-noise with differential inputs
SNR
VR+ = 2.5 V, VR– = AVSS
VR+ = 2.5 V, VR– = AVSS
VR+ = 2.5 V, VR– = AVSS
VR+ = 2.5 V, VR– = AVSS
71
70
dB
Signal-to-noise with single-ended inputs
Effective number of bits with differential inputs(1)
Effective number of bits with single-ended inputs(1)
ENOB
11.4
11.1
bits
Reduced performance with fADC12CLK
from ACLK LFXT 32.768 kHz,
VR+ = 2.5 V, VR– = AVSS
Effective number of bits with 32.768-kHz clock
10.9
(reduced performance)(1)
(1) ENOB = (SINAD – 1.76) / 6.02
Table 5-27 lists the dynamic performance characteristics when using an internal reference.
Table 5-27. 12-Bit ADC, Dynamic Performance With Internal Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Resolution Number of no missing code output code bits
12
bits
Signal-to-noise with differential inputs
SNR
VR+ = 2.5 V, VR– = AVSS
VR+ = 2.5 V, VR– = AVSS
VR+ = 2.5 V, VR– = AVSS
VR+ = 2.5 V, VR– = AVSS
70
69
dB
Signal-to-noise with single-ended inputs
Effective number of bits with differential inputs(1)
Effective number of bits with single-ended inputs(1)
ENOB
11.4
11.0
bits
Reduced performance with fADC12CLK
from ACLK LFXT 32.768 kHz,
VR+ = 2.5 V, VR– = AVSS
Effective number of bits with 32.768-kHz clock
10.9
(reduced performance)(1)
(1) ENOB = (SINAD – 1.76) / 6.02
58
Specifications
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
Table 5-28 lists the temperature sensor and built-in V1/2 characteristics.
Table 5-28. 12-Bit ADC, Temperature Sensor and Built-In V1/2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Temperature sensor voltage(1)(2) (see
Figure 5-19)
TEST CONDITIONS
MIN
TYP
700
2.5
MAX UNIT
ADC12ON = 1, ADC12TCMAP = 1,
TA = 0°C
VSENSOR
mV
mV/°C
µs
(2)
TCSENSOR
tSENSOR(sample)
See
ADC12ON = 1, ADC12TCMAP = 1
Sample time required if ADCTCMAP = 1 and
channel (MAX – 1) is selected(3)
ADC12ON = 1, ADC12TCMAP = 1,
Error of conversion result ≤ 1 LSB
30
AVCC voltage divider for ADC12BATMAP = 1
on MAX input channel
V1/2
ADC12ON = 1, ADC12BATMAP = 1
47.5%
50% 52.5%
38 72
IV 1/2
Current for battery monitor during sample time ADC12ON = 1, ADC12BATMAP = 1
µA
µs
Sample time required if ADC12BATMAP = 1
ADC12ON = 1, ADC12BATMAP = 1
and channel MAX is selected(4)
tV 1/2 (sample)
1.7
(1) The temperature sensor offset can be as much as ±30°C. TI recommends a single-point calibration to minimize the offset error of the
built-in temperature sensor.
(2) The device descriptor structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference voltage
levels. The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature, °C) + VSENSOR, where TCSENSOR and VSENSOR can
be computed from the calibration values for higher accuracy.
(3) The typical equivalent impedance of the sensor is 250 kΩ. The sample time required includes the sensor on time (tSENSOR(on)).
(4) The on time (tV1/2(on)) is included in the sampling time (tV1/2(sample)); no additional on time is needed.
950
900
850
800
750
700
650
600
550
500
–40
–20
0
20
40
60
80
Ambient Temperature (°C)
Figure 5-19. Typical Temperature Sensor Voltage
Copyright © 2016–2018, Texas Instruments Incorporated
Specifications
59
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
Table 5-29 lists the external reference characteristics.
Table 5-29. 12-Bit ADC, External Reference(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
1.2 AVCC
1.2
MAX UNIT
Positive external reference voltage input VeREF+ or
VeREF- based on ADC12VRSEL bit
VR+
VR–
VR+ > VR–
V
Negative external reference voltage input VeREF+
or VeREF- based on ADC12VRSEL bit
VR+ > VR–
VR+ > VR–
0
V
V
VR+ – VR– Differential external reference voltage input
1.2 AVCC
±10
1.2 V ≤ VeREF+≤ VAVCC, VeREF- = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 1h,
ADC12DIF = 0, ADC12PWRMD = 0
IVeREF+
IVeREF-
,
Static input current singled-ended input mode
Static input current differential input mode
µA
µA
1.2 V ≤ VeREF+≤ VAVCC , VeREF- = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 8h,
ADC12DIF = 0, ADC12PWRMD = 01
±2.5
±20
±5
1.2 V ≤ VeREF+≤ VAVCC, VeREF- = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 1h,
ADC12DIF = 1, , ADC12PWRMD = 0
IVeREF+
IVeREF-
,
1.2 V ≤ VeREF+≤ VAVCC , VeREF- = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 8h,
ADC12DIF = 1, , ADC12PWRMD = 1
IVeREF+
IVeREF+
CVeREF+/-
Peak input current with single-ended input
Peak input current with differential input
Capacitance at VeREF+ or VeREF- terminal
0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 0
0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 1
1.5
mA
mA
µF
3
(2)
See
10
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2) Two decoupling capacitors, 10 µF and 470 nF, should be connected to VeREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_B. Also see the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx
Family User's Guide.
60
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
5.12.10 Reference
The reference module (REF) generates all of the critical reference voltages that can be used by various
analog peripherals in a given device. The heart of the reference system is the bandgap from which all
other references are derived by unity or noninverting gain stages. The REFGEN subsystem consists of the
bandgap, the bandgap bias, and the noninverting buffer stage, which generates the three primary voltage
reference available in the system (1.2 V, 2.0 V, and 2.5 V).
Table 5-30 lists the operating characteristics of the built-in reference.
Table 5-30. REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
REFVSEL = {2} for 2.5 V, REFON = 1
REFVSEL = {1} for 2.0 V, REFON = 1
REFVSEL = {0} for 1.2 V, REFON = 1
From 0.1 Hz to 10 Hz, REFVSEL = {0}
VCC
MIN
TYP
2.5 ±1.5%
2.0 ±1.5%
1.2 ±1.8%
MAX UNIT
2.7 V
2.2 V
1.8 V
Positive built-in reference
voltage output
VREF+
V
(1)
Noise
RMS noise at VREF
30
130
µV
VREF ADC BUF_INT buffer TA = 25°C , ADC on, REFVSEL = {0},
VOS_BUF_INT
–16
–16
+16
mV
offset(2)
REFON = 1, REFOUT = 0
VREF ADC BUF_EXT
buffer offset(3)
TA = 25°C, REFVSEL = {0} , REFOUT = 1,
REFON = 1 or ADC on
VOS_BUF_EXT
AVCC(min)
IREF+
+16
mV
V
REFVSEL = {0} for 1.2 V
REFVSEL = {1} for 2.0 V
REFVSEL = {2} for 2.5 V
1.8
2.2
2.7
AVCC minimum voltage,
Positive built-in reference
active
Operating supply current
into AVCC terminal(4)
REFON = 1
3 V
19
247
26
400
µA
ADC on, REFOUT = 0, REFVSEL = {0, 1, 2},
ADC12PWRMD = 0,
ADC on, REFOUT = 1, REFVSEL = {0, 1, 2},
ADC12PWRMD = 0
1053
153
1820
240
Operating supply current
into AVCC terminal(4)
ADC on, REFOUT = 0, REFVSEL = {0, 1, 2},
ADC12PWRMD = 1
IREF+_ADC_BUF
3 V
µA
µA
ADC on, REFOUT = 1, REFVSEL = {0, 1, 2},
ADC12PWRMD = 1
581
1030
1890
ADC OFF, REFON = 1, REFOUT = 1,
REFVSEL = {0, 1, 2}
1105
REFVSEL = {0, 1, 2},
AVCC = AVCC(min) for each reference level,
REFON = REFOUT = 1
VREF maximum load
current, VREF+ terminal
IO(VREF+)
–1000
10
REFVSEL = {0, 1, 2},
ΔVout/
ΔIo(VREF+)
Load-current regulation,
VREF+ terminal
IO(VREF+) = +10 µA or –1000 µA
AVCC = AVCC(min) for each reference level,
REFON = REFOUT = 1
1500 µV/mA
Capacitance at VREF+ and
VREF- terminals
CVREF+/-
REFON = REFOUT = 1
0
100
pF
Temperature coefficient of
built-in reference
REFVSEL = {0, 1, 2}, REFON = REFOUT = 1,
TA = –40°C to 85°C(5)
TCREF+
24
100
3.0
50 ppm/K
400 µV/V
mV/V
Power supply rejection ratio AVCC = AVCC(min) to AVCC(max), TA = 25°C,
(DC)
PSRR_DC
PSRR_AC
REFVSEL = {0, 1, 2}, REFON = REFOUT = 1
Power supply rejection ratio
(AC)
dAVCC= 0.1 V at 1 kHz
(1) Internal reference noise affects ADC performance when ADC uses internal reference. See Designing With the MSP430FR58xx, FR59xx,
FR68xx, and FR69xx ADC for details on optimizing ADC performance for your application with the choice of internal or external
reference.
(2) Buffer offset affects ADC gain error and thus total unadjusted error.
(3) Buffer offset affects ADC gain error and thus total unadjusted error.
(4) The internal reference current is supplied through the AVCC terminal.
(5) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
Copyright © 2016–2018, Texas Instruments Incorporated
Specifications
61
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
Table 5-30. REF, Built-In Reference (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
AVCC = AVCC(min) to AVCC(max)
REFVSEL = {0, 1, 2}, REFON = 0 → 1
AVCC = AVCC(min) to AVCC(max)
REFVSEL = {0, 1, 2}, REFON = 1 (internal note
should be for buf_int REFOUT=0 or buf_ext=1 )
VCC
MIN
TYP
MAX UNIT
Settling time of reference
voltage(6)
,
tSETTLE
40
80
µs
,
Settling time of ADC
Tbuf_settle
0.4
2
µs
reference voltage buffer(6)
(6) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
5.12.11 Comparator
The COMP_E module supports precision slope analog-to-digital conversions, supply voltage supervision,
and monitoring of external analog signals. Table 5-31 lists the comparator characteristics.
Table 5-31. Comparator_E
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
CEPWRMD = 00, CEON = 1,
CERSx = 00 (fast)
12
16
CEPWRMD = 01, CEON = 1,
CERSx = 00 (medium)
Comparator operating
supply current into
AVCC, excludes
10
14
µA
0.3
2.2 V,
3.0 V
IAVCC_COMP
CEPWRMD = 10, CEON = 1,
CERSx = 00 (slow), TA = 30°C
0.1
reference resistor ladder
CEPWRMD = 10, CEON = 1,
CERSx = 00 (slow), TA = 85°C
0.3
31
1.3
38
Quiescent current of
Comparator and resistor
IAVCC_COMP_REF ladder into AVCC,
including REF module
current
CEREFACC = 0
CEPWRMD = 10,
CEREFLx = 01,
2.2 V,
3.0 V
µA
19
CERSx = 10,
CEON = 1, REFON = 0
CEREFACC = 1
16
CERSx = 11, CEREFLx = 01,
CEREFACC = 0
1.8 V
2.2 V
2.7 V
1.8 V
2.2 V
2.7 V
1.152
1.92
2.40
1.10
1.90
2.35
0
1.2
2.0
2.5
1.2
2.0
2.5
1.248
2.08
CERSx = 11, CEREFLx = 10,
CEREFACC = 0
CERSx = 11, CEREFLx = 11,
CEREFACC = 0
2.60
V
VREF
Reference voltage level
CERSx = 11, CEREFLx = 01,
CEREFACC = 1
1.245
CERSx = 11, CEREFLx = 10,
CEREFACC = 1
2.08
2.60
CERSx = 11, CEREFLx = 11,
CEREFACC = 1
Common mode input
range
VIC
VCC – 1
16
V
CEPWRMD = 00
–16
–12
–37
VOFFSET
Input offset voltage
CEPWRMD = 01
12 mV
37
CEPWRMD = 10
CEPWRMD = 00 or CEPWRMD = 01
CEPWRMD = 10
10
10
1
CIN
Input capacitance
pF
On (switch closed)
Off (switch open)
3
kΩ
RSIN
Series input resistance
50
MΩ
CEPWRMD = 00
193
230
5
330
400
15
ns
µs
Propagation delay,
response time
CEF = 0,
Overdrive ≥ 20 mV
tPD
CEPWRMD = 01
CEPWRMD = 10
62
Specifications
Copyright © 2016–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
Table 5-31. Comparator_E (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
700
1.0
2.0
4.0
0.9
0.9
15
MAX UNIT
CEFDLY = 00
1000
1.9
3.7
7.7
1.5
1.5
65
ns
CEPWRMD = 00 or 01,
CEF = 1,
Overdrive ≥ 20 mV
CEFDLY = 01
CEFDLY = 10
CEFDLY = 11
CEPWRMD = 00
Propagation delay with
filter active
tPD,filter
µs
CEON = 0 → 1,
tEN_CMP
Comparator enable time VIN+ and VIN– from pins, CEPWRMD = 01
µs
µs
Overdrive ≥ 20 mV
CEPWRMD = 10
Comparator and
CEON = 0 → 1, CEREFLX = 10,
reference ladder and
CERSx = 10 or 11,
tEN_CMP_VREF
120
220
reference voltage enable
CEREF0 = CEREF1 = 0x0F, REFON = 0
time
Comparator and
reference ladder enable CERSx = 10, REFON = 1,
time CEREF0 = CEREF1 = 0x0F
CEON = 0 → 1, CEREFLX = 10,
tEN_CMP_RL
10
30
µs
V
VIN
(n + 0.5) (n + 1) (n + 1.5)
/ 32 / 32 / 32
×
VIN
×
VIN ×
Reference voltage for a VIN = reference into resistor ladder
given tap (n = 0 to 31)
VCE_REF
5.12.12 FRAM
FRAM is a nonvolatile memory that reads and writes like standard SRAM. The FRAM can be read in a
similar fashion to SRAM and needs no special requirements. Similarly, any writes to unprotected
segments can be written in the same fashion as SRAM.
Table 5-32 lists the operating characteristics of the FRAM.
Table 5-32. FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
1015
100
40
TYP
MAX UNIT
Read and write endurance
cycles
TJ = 25°C
tRetention
Data retention duration
TJ = 70°C
TJ = 85°C
years
10
(1)
IWRITE
IERASE
tWRITE
Current to write into FRAM
Erase current
IREAD
nA
nA
ns
n/a(2)
(3)
Write time
tREAD
(4)
(4)
NWAITSx = 0
NWAITSx = 1
1 / fSYSTEM
2 / fSYSTEM
tREAD
Read time
ns
(1) Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read
current (IREAD) is included in the active mode current consumption, IAM,FRAM
(2) FRAM does not require a special erase sequence.
(3) Writing into FRAM is as fast as reading.
.
(4) The maximum read (and write) speed is specified by fSYSTEM using the appropriate wait state settings (NWAITSx).
版权 © 2016–2018, Texas Instruments Incorporated
Specifications
63
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
5.12.13 Emulation and Debug
The MSP family supports the standard JTAG interface, which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/Os. The TEST/SBWTCK pin is used
to enable the connection of external development tools with the device through Spy-Bi-Wire or JTAG
debug protocols. The connection is usually enabled when the TEST/SBWTCK is high. When the
connection is enabled, the device enters a debug mode. In the debug mode, the times for entry to and
wake up from low-power modes may be different compared to normal operation. Pay careful attention to
the real-time behavior when using low-power modes with the device connected to a development tool.
Table 5-33 lists the JTAG and Spy-Bi-Wire interface characteristics.
Table 5-33. JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX UNIT
IJTAG
Supply current adder when JTAG active (but not clocked)
Spy-Bi-Wire input frequency
2.2 V, 3.0 V
2.2 V, 3.0 V
2.2 V, 3.0 V
40
100
10
μA
MHz
μs
fSBW
0
tSBW,Low
Spy-Bi-Wire low clock pulse duration
0.04
15
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge)(1)
tSBW, En
tSBW,Rst
2.2 V, 3.0 V
110
μs
μs
Spy-Bi-Wire return to normal operation time
TCK input frequency, 4-wire JTAG(2)
15
0
100
16
2.2 V
3.0 V
fTCK
MHz
0
16
Rinternal
Internal pulldown resistance on TEST
2.2 V, 3.0 V
20
35
50
kΩ
MHz
ns
TCLK and MCLK frequency during JTAG access, no FRAM
fTCLK
16
25
access (limited by fSYSTEM
)
tTCLK,Low/High
fTCLK,FRAM
tTCLK,FRAM,Low/High
TCLK low or high clock pulse duration, no FRAM access
TCLK and MCLK frequency during JTAG access, including
FRAM access (limited by fSYSTEM with no FRAM wait states)
4
MHz
ns
TCLK low or high clock pulse duration, including FRAM accesses
100
(1) Tools that access the Spy-Bi-Wire and the BSL interfaces must wait for the tSBW,En time after the first transition of the TEST/SBWTCK
pin (low to high), before the second transition of the pin (high to low) during the entry sequence.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
64
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6 Detailed Description
6.1 Overview
The TI MSP430FR59xx family of ultra-low-power microcontrollers consists of several devices featuring
different sets of peripherals. The architecture, combined with seven low-power modes, is optimized to
achieve extended battery life for example in portable measurement applications. The devices features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency.
The device is an MSP430FR59xx family device with Low-Energy Accelerator (LEA) (available only on the
MSP430FR599x MCUs), up to six 16-bit timers, up to eight eUSCIs that support UART, SPI, and I2C, a
comparator, a hardware multiplier, an AES accelerator, a 6-channel DMA, an RTC module with alarm
capabilities, up to 67 I/O pins, and a high-performance 12-bit ADC.
6.2 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses. The peripherals can be
managed with all instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data.
6.3 Low-Energy Accelerator (LEA) for Signal Processing (MSP430FR599x Only)
The LEA module is a hardware engine designed for operations that involve vector-based signal
processing, such as FIR, IIR, and FFT. The subsystem offers fast performance and low energy
consumption when performing vector-based digital signal processing computations; for performance
benchmarks comparing the LEA module to using the CPU or other processors, see Benchmarking the
Signal Processing Capabilities of the Low-Energy Accelerator on MSP MCUs.
The LEA module requires MCLK to be operational; therefore, the subsystem can run only in active mode
or LPM0 (see 表 6-1). While the LEA module is running, the LEA data operations are performed on a
shared 4KB of RAM out of the 8KB of total RAM (see 表 6-41). This shared RAM can also be used by the
regular application. The MSP CPU and the LEA module can run simultaneously and independently unless
they access the same system RAM.
Direct access to LEA registers is not supported, and TI recommends using the optimized Digital Signal
Processing (DSP) Library for MSP Microcontrollers for the operations that the LEA module supports.
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
65
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
6.4 Operating Modes
The MCU has one active mode and seven software selectable low-power modes of operation. An interrupt event can wake up the device from low-
power modes LPM0 through LPM4, service the request, and restore back to the low-power mode on return from the interrupt program. Low-power
modes LPM3.5 and LPM4.5 disable the core supply to minimize power consumption.
表 6-1. Operating Modes
AM
LPM0
LPM1
LPM2
LPM3
LPM4
OFF
LPM3.5
LPM4.5
ACTIVE,
FRAM
MODE
SHUTDOWN
SHUTDOWN
ACTIVE
16 MHz
120 µA/MHz 65 µA/MHz
N/A
CPU OFF(2)
CPU OFF
STANDBY
STANDBY
RTC ONLY
WITH SVS
WITHOUT SVS
OFF(1)
Maximum system clock
16 MHz
92 µA at 1 MHz
Instant
16 MHz
40 µA at 1 MHz
6 µs
50 kHz
1.0 µA
6 µs
50 kHz
0.7 µA
7 µs
0(3)
0.5 µA
7 µs
50 kHz
0.45 µA
250 µs
0(3)
Typical current consumption,
TA = 25°C
0.3 µA
250 µs
0.07 µA
400 µs
Typical wake-up time
LF
RTC
I/O
LF
RTC
I/O
I/O
Comp
RTC
I/O
Wake-up events
N/A
All
All
I/O
Comp
Comp
CPU
On
On
Off
Off
Off
Off
Off
Off
Off
Off
Off
Reset
Reset
Reset
Reset
LEA (MSP430FR599x only)
On(4)
Off
Standby
FRAM
On
Off(1)
Off
Off
Off
Off
Off
Off
Off
Off
(or off(1)
)
High-frequency
peripherals(5)
Available
Available
Available
Off
Reset
Reset
Low-frequency peripherals(5)
Unclocked peripherals(5)
Available
Available
On
Available
Available
Available
Available
Off
Available
Available
Off
Available(6)
Available(6)
Off
Off
Available(6)
Off
RTC
Reset
Off
Reset
Reset
Off
MCLK
On(4)
Off
SMCLK
Optional(7)
Optional(7)
Optional(7)
Off
Off
Off
Off
Off
ACLK
On
On
On
On
On
Off
Off
Off
Full retention
SVS
Yes
Yes
Yes
Yes
Optional(8)
Yes
Optional(8)
Yes
optional(8)
No
Optional(8)
No
Always
Always
Always
Always
Always
Always
On(9)
Off(10)
Brownout
Always
Always
Always
Always
Always
(1) FRAM disabled in FRAM controller A
(2) Disabling the FRAM through the FRAM controller A allows the application to lower the LPM current consumption but the wake-up time increases when FRAM is accessed (for example, to
fetch an interrupt vector). For a wake up that does not access FRAM (for example, a DMA transfer to RAM) the wake-up time is not increased.
(3) All clocks disabled
(4) Only while the LEA module is performing the task enabled by CPU during AM. The LEA module cannot be enabled in LPM0.
(5) See 节 6.4.1 for a detailed description of high-frequency, low-frequency, and unclocked peripherals.
(6) See 节 6.4.2, which describes the use of peripherals in LPM3 and LPM4.
(7) Controlled by SMCLKOFF
(8) Activate SVS (SVSHE = 1) results in higher current consumption. SVS is not included in typical current consumption.
(9) SVSHE = 1
(10) SVSHE = 0
66
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.4.1 Peripherals in Low-Power Modes
Peripherals can be in different states that impact the achievable power modes of the device. The states
depend on the operational modes of the peripherals (see 表 6-2). The states are:
•
•
•
A peripheral is in a high-frequency state if it requires or uses a clock with a "high" frequency of more
than 50 kHz.
A peripheral is in a low-frequency state if it requires or uses a clock with a "low" frequency of 50 kHz or
less.
A peripheral is in an unclocked state if it does not require or use an internal clock.
If the CPU requests a power mode that does not support the current state of all active peripherals, the
device does not enter the requested power mode, but it does enter a power mode that still supports the
current state of the peripherals, except if an external clock is used. If an external clock is used, the
application must use the correct frequency range for the requested power mode.
表 6-2. Peripheral States
PERIPHERAL
WDT
DMA(4)
IN HIGH-FREQUENCY STATE(1)
Clocked by SMCLK
Not applicable
IN LOW-FREQUENCY STATE(2)
Clocked by ACLK
IN UNCLOCKED STATE(3)
Not applicable
Not applicable
Waiting for a trigger
Not applicable
RTC_C
Not applicable
Clocked by LFXT
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Timer_A TAx
Timer_B TBx
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
Waiting for first edge of START bit.
Not applicable
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
eUSCI_Ax in
UART mode
Clocked by SMCLK
Clocked by SMCLK
Clocked by ACLK
Clocked by ACLK
eUSCI_Ax in SPI
master mode
eUSCI_Ax in SPI
slave mode
eUSCI_Bx in I2C
master mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
Not applicable
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
eUSCI_Bx in I2C
slave mode
Waiting for START condition or
clocked by external clock ≤50 kHz
Clocked by external clock >50 kHz
Clocked by SMCLK
Clocked by external clock ≤50 kHz
Clocked by ACLK
eUSCI_Bx in SPI
master mode
Not applicable
eUSCI_Bx in SPI
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
ADC12_B
REF_A
COMP_E
CRC(5)
MPY(5)
AES(5)
Clocked by SMCLK or by MODOSC
Not applicable
Clocked by ACLK
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Waiting for a trigger
Always
Not applicable
Always
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
(1) Peripherals are in a state that requires or uses a clock with a "high" frequency of more than 50 kHz
(2) Peripherals are in a state that requires or uses a clock with a "low" frequency of 50 kHz or less.
(3) Peripherals are in a state that does not require or does not use an internal clock.
(4) The DMA always transfers data in active mode but can wait for a trigger in any low-power mode. A DMA trigger during a low-power
mode causes a temporary transition into active mode for the time of the transfer.
(5) This peripheral operates during active mode only and will delay the transition into a low-power mode until its operation is completed.
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
67
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
6.4.2 Idle Currents of Peripherals in LPM3 and LPM4
Most peripherals can be operational in LPM3 if clocked by ACLK. Some modules are operational in LPM4,
because they do not require a clock to operate (for example, the comparator). Activating a peripheral in
LPM3 or LPM4 increases the current consumption due to its active supply current contribution but also
due to an additional idle current. To reduce the idle current adder, certain peripherals are grouped
together (see 表 6-3). To achieve optimal current consumption, use modules within one group and limit the
number of groups with active modules. Modules not listed in 表 6-3 are either already included in the
standard LPM3 current consumption or cannot be used in LPM3 or LPM4.
The idle current adder is very small at room temperature (25°C) but increases at high temperatures
(85°C). See the IIDLE current parameters in Section 5 for details.
表 6-3. Peripheral Groups
GROUP A
Timer TA1
Timer TA2
Timer TB0
eUSCI_A0
eUSCI_A1
eUSCI_B0
GROUP B
Timer TA0
Timer TA3
Comparator
ADC12_B
REF_A
GROUP C
Timer TA4
eUSCI_A2
eUSCI_A3
eUSCI_B1
eUSCI_B2
eUSCI_B3
6.5 Interrupt Vector Table and Signatures
The interrupt vectors, the power-up start address and signatures are in the address range 0FFFFh to
0FF80h. 图 6-1 summarizes the content of this address range.
0FFFFh
Reset Vector
BSL Password
Interrupt
Vectors
0FFE0h
JTAG Password
Reserved
0FF88h
0FF80h
Signatures
图 6-1. Interrupt Vectors, Signatures and Passwords
The power-up start address or reset vector is at 0FFFFh to 0FFFEh. This location contains a 16-bit
address pointing to the start address of the application program.
The interrupt vectors start at 0FFFDh and extend to lower addresses. Each vector contains the 16-bit
address of the appropriate interrupt-handler instruction sequence. 表 6-4 shows the device specific
interrupt vector locations.
The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as BSL password (if
enabled by the corresponding signature).
68
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
The signatures are at 0FF80h and extend to higher addresses. Signatures are evaluated during device
start-up. 表 6-5 lists the device-specific signature locations.
A JTAG password can be programmed starting at address 0FF88h and extending to higher addresses.
The password can extend into the interrupt vector locations using the interrupt vector addresses as
additional bits for the password. The length of the JTAG password depends on the JTAG signature.
See the System Resets, Interrupts, and Operating Modes, System Control Module (SYS) chapter in the
MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for details.
表 6-4. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
System Reset
Power up, brownout, supply
supervisor
External reset RST
Watchdog time-out (watchdog
mode)
WDT, FRCTL MPU, CS,
PMM password violation
FRAM uncorrectable bit error
detection
SVSHIFG
PMMRSTIFG
WDTIFG
WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
UBDIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
Reset
0FFFEh
Highest
PMMPORIFG, PMMBORIFG
MPU segment violation
Software POR, BOR
(SYSRSTIV)(1) (2)
System NMI
Vacant memory access
JTAG mailbox
FRAM access time error
FRAM write protection error
FRAM bit error detection
MPU segment violation
VMAIFG
JMBINIFG, JMBOUTIFG
ACCTEIFG, WPIFG
(Non)maskable
(Non)maskable
0FFFCh
0FFFAh
CBDIFG, UBDIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
(SYSSNIV)(1) (3)
User NMI
External NMI
Oscillator fault
NMIIFG, OFIFG
(SYSUNIV)(1) (3)
CEIFG, CEIIFG
(CEIV)(1)
Comparator_E
TB0
Maskable
Maskable
0FFF8h
0FFF6h
TB0CCR0.CCIFG
TB0CCR1.CCIFG ... TB0CCR6.CCIFG,
TB0CTL.TBIFG
TB0
Maskable
Maskable
0FFF4h
0FFF2h
(TB0IV)(1)
Watchdog timer (interval timer
mode)
WDTIFG
UCA0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA0IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
eUSCI_A0 receive or transmit
Maskable
Maskable
0FFF0h
0FFEEh
(UCA0IV)(1)
UCB0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB0IFG: UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,
UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,
UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB0IV)(1)
eUSCI_B0 receive or transmit
ADC12IFG0 to ADC12IFG31
ADC12LOIFG, ADC12INIFG, ADC12HIIFG,
ADC12RDYIFG, ADC21OVIFG, ADC12TOVIFG
(ADC12IV)(1) (4)
ADC12_B
TA0
Maskable
Maskable
0FFECh
0FFEAh
TA0CCR0.CCIFG
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from peripheral space.
(3) (Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it.
(4) Only on devices with ADC, otherwise reserved.
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
69
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
PRIORITY
表 6-4. Interrupt Sources, Flags, and Vectors (continued)
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
TA0CCR1.CCIFG, TA0CCR2.CCIFG,
TA0CTL.TAIFG
TA0
Maskable
0FFE8h
0FFE6h
(TA0IV)(1)
UCA1IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA1IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
eUSCI_A1 receive or transmit
Maskable
(UCA1IV)(1)
DMA0CTL.DMAIFG, DMA1CTL.DMAIFG,
DMA2CTL.DMAIFG
DMA
TA1
TA1
Maskable
Maskable
Maskable
0FFE4h
0FFE2h
0FFE0h
(DMAIV)(1)
TA1CCR0.CCIFG
TA1CCR1.CCIFG, TA1CCR2.CCIFG,
TA1CTL.TAIFG
(TA1IV)(1)
P1IFG.0 to P1IFG.7
(P1IV)(1)
I/O port P1
TA2
Maskable
Maskable
0FFDEh
0FFDCh
TA2CCR0.CCIFG
TA2CCR1.CCIFG
TA2CTL.TAIFG
(TA2IV)(1)
TA2
Maskable
0FFDAh
P2IFG.0 to P2IFG.7
(P2IV)(1)
I/O port P2
TA3
Maskable
Maskable
0FFD8h
0FFD6h
TA3CCR0.CCIFG
TA3CCR1.CCIFG
TA3CTL.TAIFG
(TA3IV)(1)
TA3
Maskable
0FFD4h
P3IFG.0 to P3IFG.7
(P3IV)(1)
I/O port P3
I/O port P4
Maskable
Maskable
0FFD2h
0FFD0h
P4IFG.0 to P4IFG.2
(P4IV)(1)
RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG,
RT1PSIFG, RTCOFIFG
RTC_C
Maskable
0FFCEh
(RTCIV)(1)
AES
TA4
AESRDYIFG
Maskable
Maskable
0FFCCh
0FFCAh
TA4CCR0.CCIFG
TA4CCR1.CCIFG
TA4CTL.TAIFG
(TA4IV)(1)
TA4
Maskable
0FFC8h
P5IFG.0 to P5IFG.2
(P5IV)(1)
I/O port P5
I/O port P6
Maskable
Maskable
0FFC6h
0FFC4h
P6IFG.0 to P6IFG.2
(P6IV)(1)
UCA2IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA2IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
eUSCI_A2 receive or transmit
eUSCI_A3 receive or transmit
Maskable
Maskable
0FFC2h
0FFC0h
(UCA2IV)(1)
UCA3IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA3IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
(UCA3IV)(1)
UCB1IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB1IFG: UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,
UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,
UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB1IV)(1)
eUSCI_B1 receive or transmit
Maskable
0FFBEh
70
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
表 6-4. Interrupt Sources, Flags, and Vectors (continued)
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
UCB2IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB2IFG: UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,
UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,
UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB2IV)(1)
eUSCI_B2 receive or transmit
eUSCI_B3 receive or transmit
Maskable
Maskable
0FFBCh
0FFBAh
UCB3IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB3IFG: UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,
UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,
UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB3IV)(1)
P7IFG.0 to P7IFG.2
(P7IV)(1)
I/O port P7
I/O port P8
Maskable
Maskable
Maskable
0FFB8h
0FFB6h
0FFB4h
P6IFG.0 to P6IFG.2
(P8IV)(1)
CMDIFG, SDIIFG, OORIFG,TIFG, COVLIFG
LEAIV(1)
LEA (MSP430FR599x only)
Lowest
表 6-5. Signatures
SIGNATURE
IP Encapsulation Signature 2
IP Encapsulation Signature 1(1)
BSL Signature 2
WORD ADDRESS
0FF8Ah
0FF88h
0FF86h
BSL Signature 1
0FF84h
JTAG Signature 2
0FF82h
JTAG Signature 1
0FF80h
(1) Must not contain 0AAAAh if used as the JTAG password.
6.6 Bootloader (BSL)
The BSL can program the FRAM or RAM using a UART serial interface (FRxxxx devices) or an I2C
interface (FRxxxx1 devices). Access to the device memory through the BSL is protected by an user-
defined password. 表 6-6 lists the pins that are required to use the BSL. BSL entry requires a specific
entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For a complete description of the
features of the BSL and its implementation, see the MSP430 FRAM Device Bootloader (BSL) User's
Guide. Visit Bootloader (BSL) for MSP low-power microcontrollers for more information.
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
71
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-6. BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
Entry sequence signal
RST/NMI/SBWTDIO
TEST/SBWTCK
P2.0
Entry sequence signal
Devices with UART BSL (FRxxxx): Data transmit
Devices with UART BSL (FRxxxx): Data receive
Devices with I2C BSL (FRxxxx1): Data
Devices with I2C BSL (FRxxxx1): Clock
Power supply
P2.1
P1.6
P1.7
DVCC
DVSS
Ground supply
6.7 JTAG Operation
6.7.1 JTAG Standard Interface
The MSP family supports the standard JTAG interface, which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP development tools and device programmers. 表 6-7 lists the JTAG pin requirements. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools
User's Guide. For a complete description of the features of the JTAG interface and its implementation, see
MSP430 Programming With the JTAG Interface.
表 6-7. JTAG Pin Requirements and Functions
DEVICE SIGNAL
PJ.3/TCK
DIRECTION
FUNCTION
JTAG clock input
JTAG state control
JTAG data input, TCLK input
JTAG data output
Enable JTAG pins
External reset
IN
IN
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
IN
OUT
IN
TEST/SBWTCK
RST/NMI/SBWTDIO
DVCC
IN
Power supply
DVSS
Ground supply
6.7.2 Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP family supports the two wire Spy-Bi-Wire interface.
Spy-Bi-Wire can be used to interface with MSP development tools and device programmers. The Spy-Bi-
Wire interface pin requirements are shown in 表 6-8. For further details on interfacing to development tools
and device programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of
the features of the JTAG interface and its implementation, see MSP430 Programming With the JTAG
Interface.
表 6-8. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
DVCC
DIRECTION
IN
FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input and output
Power supply
IN, OUT
DVSS
Ground supply
72
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.8 FRAM Controller A (FRCTL_A)
The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in system by the
CPU (also see 表 6-45 for control and configuration registers). Features of the FRAM include:
•
•
•
•
Ultra-low-power ultra-fast-write nonvolatile memory
Byte and word access capability
Programmable wait state generation
Error correction coding (ECC)
注
Wait States
For MCLK frequencies > 8 MHz, wait states must be configured following the flow described
in the "Wait State Control" section of the FRAM Controller A (FRCTRL_A) chapter in the
MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.
For important software design information regarding FRAM including but not limited to partitioning the
memory layout according to application-specific code, constant, and data space requirements, the use of
FRAM to optimize application energy consumption, and the use of the Memory Protection Unit (MPU) to
maximize application robustness by protecting the program code against unintended write accesses, see
MSP430™ FRAM Technology – How To and Best Practices.
6.9 RAM
The RAM is made up of three sectors: Sector 0 = 2KB, Sector 1 = 2KB, and Sector 2 = 4KB (shared with
the LEA module). Each sector can be individually powered down in LPM3 and LPM4 to save leakage.
Data is lost when sectors are powered down in LPM3 and LPM4. See 表 6-47 for control and configuration
registers.
6.10 Tiny RAM
Tiny RAM provides 22 bytes of RAM in addition to the complete RAM (see 表 6-41). This memory is
always available, even in LPM3 and LPM4, while the complete RAM can be powered down in LPM3 and
LPM4. Tiny RAM can be used to hold data or a very small stack when the complete RAM is powered
down in LPM3 and LPM4. No memory is available in LPMx.5.
6.11 Memory Protection Unit (MPU) Including IP Encapsulation
The FRAM can be protected by the MPU from inadvertent CPU execution, read access, or write access.
See 表 6-67 for control and configuration registers. Features of the MPU include:
•
IP encapsulation with programmable boundaries in steps of 1KB (prevents reads from "outside"; for
example, through JTAG or by non-IP software).
•
•
•
Main memory partitioning is programmable up to three segments in steps of 1KB.
Access rights of each segment can be individually selected (main and information memory).
Access violation flags with interrupt capability for easy servicing of access violations.
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
73
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
6.12 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. The peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430FR58xx,
MSP430FR59xx, and MSP430FR6xx Family User's Guide.
6.12.1 Digital I/O
Up to nine 8-bit I/O ports are implemented (see 表 6-52 through 表 6-56 for control and configuration
registers):
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Programmable pullup or pulldown on all ports.
Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for all pins of
ports P1 to P8.
•
•
•
•
Read and write access to port control registers is supported by all instructions.
Ports can be accessed byte-wise or word-wise in pairs.
All pins of ports P1 to P8, and PJ support capacitive touch functionality.
No cross-currents during start-up.
注
Configuration of Digital I/Os After BOR Reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance
with Schmitt triggers and their module functions disabled. To enable the I/O functionality after
a BOR reset, first configure the ports and then clear the LOCKLPM5 bit. For details, see the
Configuration After Reset section of the Digital I/O chapter in the MSP430FR58xx,
MSP430FR59xx, and MSP430FR6xx Family User's Guide.
6.12.2 Oscillator and Clock System (CS)
The clock system includes support for a 32-kHz watch-crystal oscillator XT1 (LF), an internal very-low-
power low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a
high-frequency crystal oscillator XT2 (HF). The clock system module is designed to meet the requirements
of both low system cost and low power consumption. A fail-safe mechanism exists for all crystal sources.
See 表 6-49 for control and configuration registers.
The clock system module provides the following clock signals:
•
Auxiliary clock (ACLK). ACLK can be sourced from a 32-kHz watch crystal (LFXT1), the internal VLO,
or a digital external low-frequency (<50 kHz) clock source.
•
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced from a high-frequency
crystal (HFXT2), the internal DCO, a 32-kHz watch crystal (LFXT1), the internal VLO, or a digital
external clock source.
•
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources made available to MCLK.
6.12.3 Power-Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM
also includes supply voltage supervisor (SVS) and brownout protection. The brownout circuit provides the
proper internal reset signal to the device during power on and power off. The SVS circuitry detects if the
supply voltage drops below a safe level and below a user-selectable level. SVS circuitry is available on the
primary and core supplies. See 表 6-44 for control and configuration registers.
74
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.12.4 Hardware Multiplier (MPY)
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed multiplication, unsigned
multiplication, signed multiply-and-accumulate, and unsigned multiply-and-accumulate operations. See 表
6-65 for control and configuration registers.
6.12.5 Real-Time Clock (RTC_C)
The RTC_C module contains an integrated real-time clock (RTC) with the following features:
•
•
Calendar mode with leap year correction
General-purpose counter mode
The internal calendar compensates for months with fewer than 31 days and includes leap year correction.
The RTC_C also supports flexible alarm functions and offset-calibration hardware. RTC operation is
available in LPM3.5 modes to minimize power consumption. See 表 6-64 for control and configuration
registers.
6.12.6 Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart if a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not
needed in an application, the module can be configured as an interval timer and can generate interrupts at
selected time intervals. 表 6-9 lists the clocks that can source WDT_A. See 表 6-48 for control and
configuration registers.
表 6-9. WDT_A Clocks
NORMAL OPERATION
WDTSSEL
(WATCHDOG AND INTERVAL TIMER MODE)
00
01
10
11
SMCLK
ACLK
VLOCLK
LFMODCLK
6.12.7 System Module (SYS)
The SYS module manages many of the system functions within the device. These include power-on reset
(POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector
generators (see 表 6-10), bootloader (BSL) entry mechanisms, and configuration management (device
descriptors). The SYS module also includes a data exchange mechanism through JTAG called a JTAG
mailbox that can be used in the application. See 表 6-50 for control and configuration registers.
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
75
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-10. System Module Interrupt Vector Registers
INTERRUPT VECTOR
ADDRESS
INTERRUPT EVENT
VALUE
PRIORITY
REGISTER
No interrupt pending
Brownout (BOR)
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
Highest
RSTIFG RST/NMI (BOR)
PMMSWBOR software BOR (BOR)
LPMx.5 wake up (BOR)
Security violation (BOR)
Reserved
SVSHIFG SVSH event (BOR)
Reserved
Reserved
PMMSWPOR software POR (POR)
WDTIFG watchdog timeout (PUC)
WDTPW password violation (PUC)
FRCTLPW password violation (PUC)
Uncorrectable FRAM bit error detection (PUC)
Peripheral area fetch (PUC)
PMMPW PMM password violation (PUC)
MPUPW MPU password violation (PUC)
CSPW CS password violation (PUC)
SYSRSTIV, System Reset
019Eh
MPUSEGIPIFG encapsulated IP memory segment violation
(PUC)
26h
MPUSEGIIFG information memory segment violation (PUC)
MPUSEG1IFG segment 1 memory violation (PUC)
MPUSEG2IFG segment 2 memory violation (PUC)
MPUSEG3IFG segment 3 memory violation (PUC)
Reserved
28h
2Ah
2Ch
2Eh
30h to 3Eh
00h
Lowest
Highest
No interrupt pending
Reserved
02h
Uncorrectable FRAM bit error detection
FRAM access time error
04h
06h
MPUSEGIPIFG encapsulated IP memory segment violation
MPUSEGIIFG information memory segment violation
MPUSEG1IFG segment 1 memory violation
MPUSEG2IFG segment 2 memory violation
MPUSEG3IFG segment 3 memory violation
VMAIFG vacant memory access
08h
0Ah
0Ch
0Eh
10h
SYSSNIV, System NMI
019Ch
12h
JMBINIFG JTAG mailbox input
14h
JMBOUTIFG JTAG mailbox output
Correctable FRAM bit error detection
FRAM write protection detection
16h
18h
1Ah
1Ch
1Eh
LEA time-out fault(1)
LEA command fault(1)
Lowest
(1) Reserved on MSP430FR596x.
76 Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
表 6-10. System Module Interrupt Vector Registers (continued)
INTERRUPT VECTOR
ADDRESS
INTERRUPT EVENT
VALUE
PRIORITY
REGISTER
No interrupt pending
NMIIFG NMI pin
OFIFG oscillator fault
Reserved
00h
02h
Highest
04h
SYSUNIV, User NMI
019Ah
06h
Reserved
08h
Reserved
0Ah to 1Eh
Lowest
6.12.8 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC12_B conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral. See 表 6-66 for control and configuration registers.
表 6-11 lists the available DMA triggers.
表 6-11. DMA Trigger Assignments(1)
TRIGGER
CHANNEL 0
DMAREQ
CHANNEL 1
DMAREQ
CHANNEL 2
DMAREQ
CHANNEL 3
DMAREQ
CHANNEL 4
DMAREQ
CHANNEL 5
DMAREQ
0
1
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA3CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
TA4CCR0 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA3CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
TA4CCR0 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA3CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
TA4CCR0 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA3CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
TA4CCR0 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA3CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
TA4CCR0 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA3CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
TA4CCR0 CCIFG
Reserved
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
AES Trigger 0
AES Trigger 1
AES Trigger 2
UCA0RXIFG
AES Trigger 0
AES Trigger 1
AES Trigger 2
UCA0RXIFG
AES Trigger 0
AES Trigger 1
AES Trigger 2
UCA0RXIFG
AES Trigger 0
AES Trigger 1
AES Trigger 2
UCA2RXIFG
AES Trigger 0
AES Trigger 1
AES Trigger 2
UCA2RXIFG
AES Trigger 0
AES Trigger 1
AES Trigger 2
UCA2RXIFG
UCA0TXIFG
UCA0TXIFG
UCA0TXIFG
UCA2TXIFG
UCA2TXIFG
UCA2TXIFG
UCA1RXIFG
UCA1RXIFG
UCA1RXIFG
UCA3RXIFG
UCA3RXIFG
UCA3RXIFG
UCA1TXIFG
UCA1TXIFG
UCA1TXIFG
UCA3TXIFG
UCA3TXIFG
UCA3TXIFG
UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)
UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)
UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)
UCB1RXIFG (SPI)
UCB1RXIFG0 (I2C)
UCB2RXIFG (SPI)
UCB2RXIFG0 (I2C)
UCB3RXIFG (SPI)
UCB3RXIFG0 (I2C)
18
19
UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)
UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)
UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)
UCB1TXIFG (SPI)
UCB1TXIFG0 (I2C)
UCB2TXIFG (SPI)
UCB2TXIFG0 (I2C)
UCB3TXIFG (SPI)
UCB3TXIFG0 (I2C)
UCB0RXIFG1 (I2C)
UCB0TXIFG1 (I2C)
UCB0RXIFG2 (I2C)
UCB0TXIFG2 (I2C)
UCB0RXIFG3 (I2C)
UCB0TXIFG3 (I2C)
UCB0RXIFG1 (I2C)
UCB0TXIFG1 (I2C)
UCB0RXIFG2 (I2C)
UCB0TXIFG2 (I2C)
UCB0RXIFG3 (I2C)
UCB0TXIFG3 (I2C)
UCB0RXIFG1 (I2C)
UCB0TXIFG1 (I2C)
UCB0RXIFG2 (I2C)
UCB0TXIFG2 (I2C)
UCB0RXIFG3 (I2C)
UCB0TXIFG3 (I2C)
UCB1RXIFG1 (I2C)
UCB1TXIFG1 (I2C)
UCB1RXIFG2 (I2C)
UCB1TXIFG2 (I2C)
UCB1RXIFG3 (I2C)
UCB1TXIFG3 (I2C)
UCB2RXIFG1 (I2C)
UCB2TXIFG1 (I2C)
UCB2RXIFG2 (I2C)
UCB2TXIFG2 (I2C)
UCB2RXIFG3 (I2C)
UCB2TXIFG3 (I2C)
UCB3RXIFG1 (I2C)
UCB3TXIFG1 (I2C)
UCB3RXIFG2 (I2C)
UCB3TXIFG2 (I2C)
UCB3RXIFG3 (I2C)
UCB3TXIFG3 (I2C)
20
21
22
23
24
25
ADC12 end of
conversion
LEA ready(2)
ADC12 end of
conversion
LEA ready(2)
ADC12 end of
conversion
LEA ready(2)
ADC12 end of
conversion
LEA ready(2)
ADC12 end of
conversion
LEA ready(2)
ADC12 end of
conversion
LEA ready(2)
26
27
(1) If a reserved trigger source is selected, no trigger is generated.
(2) Reserved on MSP430FR596x.
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
77
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-11. DMA Trigger Assignments(1) (continued)
TRIGGER
CHANNEL 0
Reserved
MPY ready
DMA2IFG
DMAE0
CHANNEL 1
Reserved
MPY ready
DMA0IFG
DMAE0
CHANNEL 2
Reserved
MPY ready
DMA1IFG
DMAE0
CHANNEL 3
Reserved
MPY ready
DMA5IFG
DMAE0
CHANNEL 4
Reserved
MPY ready
DMA3IFG
DMAE0
CHANNEL 5
Reserved
MPY ready
DMA4IFG
DMAE0
28
29
30
31
6.12.9 Enhanced Universal Serial Communication Interface (eUSCI)
The eUSCI modules are used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3 pin or 4 pin) and I2C, and asynchronous communication
protocols such as UART, enhanced UART with automatic baud-rate detection, and IrDA.
The eUSCI_An module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, and IrDA.
The eUSCI_Bn module provides support for SPI (3 pin or 4 pin) and I2C.
Up to four eUSCI_A modules and up to four eUSCI_B modules are implemented. See 表 6-68 through 表
6-75 for control and configuration registers.
6.12.10 TA0, TA1, and TA4
TA0, TA1, and TA4 are 16-bit timers and counters (Timer_A type) with three (TA0 and TA1) or two (TA4)
capture/compare registers each. Each timer can support multiple captures or compares, PWM outputs,
and interval timing (see 表 6-12, 表 6-13, and 表 6-14). Each timer has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers. See 表 6-57, 表 6-58, and 表 6-76 for control and configuration registers.
表 6-12. TA0 Signal Connections
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
MODULE
BLOCK
INPUT PORT PIN
OUTPUT PORT PIN
P1.2
TA0CLK
ACLK (internal)
SMCLK (internal)
TA0CLK
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
CCR0
N/A
TA0
N/A
P1.2
P1.6
P2.3
TA0.0
P1.6
P2.3
TA0.0
TA0.0
DVSS
DVCC
VCC
P1.0
P1.1
TA0.1
CCI1A
P1.0
ADC12(internal)(1)
ADC12SHSx = {1}
COUT (internal)
CCI1B
CCR1
CCR2
TA1
TA2
TA0.1
TA0.2
DVSS
DVCC
GND
VCC
TA0.2
CCI2A
CCI2B
GND
VCC
P1.1
ACLK (internal)
DVSS
DVCC
(1) Only on devices with ADC
78
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
表 6-13. TA1 Signal Connections
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
MODULE
BLOCK
INPUT PORT PIN
OUTPUT PORT PIN
P1.1
TA1CLK
ACLK (internal)
SMCLK (internal)
TA1CLK
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
CCR0
N/A
TA0
N/A
P1.1
P1.7
P2.4
TA1.0
P1.7
P2.4
TA1.0
TA1.0
DVSS
DVCC
VCC
P1.2
P1.3
TA1.1
CCI1A
P1.2
ADC12(internal)(1)
ADC12SHSx = {4}
COUT (internal)
CCI1B
CCR1
CCR2
TA1
TA2
TA1.1
TA1.2
DVSS
DVCC
GND
VCC
TA1.2
CCI2A
CCI2B
GND
VCC
P1.3
ACLK (internal)
DVSS
DVCC
(1) Only on devices with ADC
表 6-14. TA4 Signal Connections
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
DEVICE INPUT
MODULE INPUT
MODULE
BLOCK
INPUT PORT PIN
OUTPUT PORT PIN
SIGNAL
SIGNAL
P5.2
TA4CLK
ACLK (internal)
SMCLK (internal)
TA4CLK
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
CCR0
N/A
TA0
N/A
P5.2
P5.6
P7.4
TA4.0
TA4.0
TA4.0
DVSS
DVCC
VCC
P5.7
P7.3
TA4.1
CCI1A
ADC12(internal)(1)
ADC12SHSx = {7}
TA4.1
CCI1B
CCR1
TA1
TA4.1
DVSS
DVCC
GND
VCC
(1) Only on devices with ADC
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
79
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
6.12.11 TA2 and TA3
TA2 and TA3 are 16-bit timers and counters (Timer_A type) with two capture/compare registers each and
with internal connections only. Each timer can support multiple captures or compares, PWM outputs, and
interval timing (see 表 6-15 and 表 6-16). Each timer has extensive interrupt capabilities. Interrupts may be
generated from the counter on overflow conditions and from each of the capture/compare registers. See
表 6-60 and 表 6-62 for control and configuration registers.
表 6-15. TA2 Signal Connections
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
DEVICE INPUT SIGNAL
MODULE INPUT NAME
MODULE BLOCK
COUT (internal)
ACLK (internal)
SMCLK (internal)
TACLK
ACLK
Timer
N/A
TA0
TA1
SMCLK
From Capacitive Touch
I/O 0 (internal)
INCLK
CCI0A
TA3 CCR0 output
(internal)
TA3 CCI0A input
ACLK (internal)
DVSS
CCI0B
GND
VCC
CCR0
CCR1
DVCC
From Capacitive Touch
I/O 0 (internal)
ADC12(internal)(1)
ADC12SHSx = {5}
CCI1A
COUT (internal)
DVSS
CCI1B
GND
VCC
DVCC
(1) Only on devices with ADC
表 6-16. TA3 Signal Connections
MODULE OUTPUT
DEVICE OUTPUT
SIGNAL
DEVICE INPUT SIGNAL
MODULE INPUT NAME
MODULE BLOCK
SIGNAL
COUT (internal)
ACLK (internal)
SMCLK (internal)
TACLK
ACLK
Timer
N/A
SMCLK
From Capacitive Touch
I/O 1 (internal)
INCLK
CCI0A
TA2 CCR0 output
(internal)
TA2 CCI0A input
ACLK (internal)
DVSS
CCI0B
GND
VCC
CCR0
CCR1
TA0
TA1
DVCC
From Capacitive Touch
I/O 1 (internal)
ADC12(internal)(1)
ADC12SHSx = {6}
CCI1A
COUT (internal)
DVSS
CCI1B
GND
VCC
DVCC
(1) Only on devices with ADC
80
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.12.12 TB0
TB0 is a 16-bit timer and counter (Timer_B type) with seven capture/compare registers. TB0 can support
multiple captures or compares, PWM outputs, and interval timing (see 表 6-17). TB0 has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers. See 表 6-59 for control and configuration registers.
表 6-17. TB0 Signal Connections
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
MODULE
BLOCK
INPUT PORT PIN
OUTPUT PORT PIN
P2.0
TB0CLK
ACLK (internal)
SMCLK (internal)
TB0CLK
TBCLK
ACLK
Timer
CCR0
N/A
N/A
SMCLK
INCLK
CCI0A
CCI0B
P2.0
P2.1
P2.5
TB0.0
P2.1
P2.5
TB0.0
ADC12 (internal)(1)
ADC12SHSx = {2}
TB0
TB0.0
DVSS
GND
DVCC
TB0.1
VCC
P1.4
P1.5
CCI1A
CCI1B
P1.4
P2.6
COUT (internal)
ADC12 (internal)(1)
ADC12SHSx = {3}
CCR1
TB1
TB0.1
DVSS
GND
DVCC
TB0.2
VCC
CCI2A
CCI2B
GND
P1.5
P2.2
ACLK (internal)
DVSS
CCR2
CCR3
CCR4
CCR5
CCR6
TB2
TB3
TB4
TB5
TB6
TB0.2
TB0.3
TB0.4
TB0.5
TB0.6
DVCC
TB0.3
VCC
P3.4
P1.6
CCI3A
CCI3B
GND
P3.4
P1.6
TB0.3
DVSS
DVCC
TB0.4
VCC
P3.5
P1.7
CCI4A
CCI4B
GND
P3.5
P1.7
TB0.4
DVSS
DVCC
TB0.5
VCC
P3.6
P4.4
CCI5A
CCI5B
GND
P3.6
P4.4
TB0.5
DVSS
DVCC
TB0.6
VCC
P3.7
P2.0
CCI6A
CCI6B
GND
P3.7
P2.0
TB0.6
DVSS
DVCC
VCC
(1) Only on devices with ADC
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
81
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
6.12.13 ADC12_B
The ADC12_B module supports fast 12-bit analog-to-digital conversions with differential and single-ended
inputs. The module implements a 12-bit SAR core, sample select control, a reference generator, and a
conversion result buffer. A window comparator with lower and upper limits allows CPU-independent result
monitoring with three window comparator interrupt flags. See 表 6-77 for control and configuration
registers.
表 6-18 summarizes the available external trigger sources.
表 6-19 lists the available multiplexing between internal and external analog inputs.
表 6-18. ADC12_B Trigger Signal Connections
ADC12SHSx
CONNECTED TRIGGER
SOURCE
BINARY
DECIMAL
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
Software (ADC12SC)
TA0 CCR1 output
TB0 CCR0 output
TB0 CCR1 output
TA1 CCR1 output
TA2 CCR1 output
TA3 CCR1 output
TA4 CCR1 output
表 6-19. ADC12_B External and Internal Signal Mapping
CONTROL BIT IN ADC12CTL3
EXTERNAL ADC INPUT
(CONTROL BIT = 0)
INTERNAL ADC INPUT
REGISTER
(CONTROL BIT = 1)
Battery monitor
Temperature sensor
N/A(1)
ADC12BATMAP
ADC12TCMAP
ADC12CH0MAP
ADC12CH1MAP
ADC12CH2MAP
ADC12CH3MAP
A31
A30
A29
A28
A27
A26
N/A(1)
N/A(1)
N/A(1)
(1) N/A = No internal signal is available on this device.
6.12.14 Comparator_E
The primary function of the Comparator_E module is to support precision slope analog-to-digital
conversions, battery voltage supervision, and monitoring of external analog signals. See 表 6-78 for
control and configuration registers.
6.12.15 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard. See 表
6-46 for control and configuration registers.
6.12.16 CRC32
The CRC32 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC32 signature is based on the ISO 3309 standard. See 表 6-79 for
control and configuration registers.
82
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.12.17 AES256 Accelerator
The AES accelerator module performs encryption and decryption of 128-bit data with 128-, 192-, or 256-
bit keys according to the Advanced Encryption Standard (AES) (FIPS PUB 197) in hardware. See 表 6-80
for control and configuration registers.
6.12.18 True Random Seed
The Device Descriptor Information (TLV) section contains a 128-bit true random seed that can be used to
implement a deterministic random number generator.
6.12.19 Shared Reference (REF)
The REF module generates all critical reference voltages that can be used by the various analog
peripherals in the device.
6.12.20 Embedded Emulation
6.12.20.1 Embedded Emulation Module (EEM) (S Version)
The EEM supports real-time in-system debugging. The S version of the EEM has the following features:
•
•
•
•
•
Three hardware triggers or breakpoints on memory access
One hardware trigger or breakpoint on CPU register write access
Up to four hardware triggers can be combined to form complex triggers or breakpoints
One cycle counter
Clock control on module level
6.12.20.2 EnergyTrace++ Technology
The devices implement circuitry to support EnergyTrace++ technology. The EnergyTrace++ technology
allows you to observe information about the internal states of the microcontroller. These states include the
CPU program counter (PC), the ON or OFF status of the peripherals and the system clocks (regardless of
the clock source), and the low-power mode currently in use. These states can always be read by a debug
tool, even when the microcontroller sleeps in LPMx.5 modes.
The activity of the following modules can be observed:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
LEA is running (MSP430FR599x only).
MPY is calculating.
WDT is counting.
RTC is counting.
ADC: a sequence, sample, or conversion is active.
REF: REFBG or REFGEN active and BG in static mode.
COMP is on.
AES is encrypting or decrypting.
eUSCI_A0 is transferring (receiving or transmitting) data.
eUSCI_A1 is transferring (receiving or transmitting) data.
eUSCI_A2 is transferring (receiving or transmitting) data.
eUSCI_A3 is transferring (receiving or transmitting) data.
eUSCI_B0 is transferring (receiving or transmitting) data.
eUSCI_B1 is transferring (receiving or transmitting) data.
eUSCI_B2 is transferring (receiving or transmitting) data.
eUSCI_B3 is transferring (receiving or transmitting) data.
TB0 is counting.
TA0 is counting.
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
83
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
•
•
•
•
TA1 is counting.
TA2 is counting.
TA3 is counting.
TA4 is counting.
84
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.13 Input/Output Diagrams
6.13.1 Capacitive Touch Functionality on Ports P1 to P8, and PJ
All port pins provide the Capacitive Touch functionality (see 图 6-2). The Capacitive Touch functionality is
controlled using the Capacitive Touch I/O control registers CAPTIO0CTL and CAPTIO1CTL as described
in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide. The Capacitive Touch
functionality is not shown in the individual pin schematics in the following sections.
Analog Enable
PxREN.y
Capacitive Touch Enable 0
Capacitive Touch Enable 1
DVSS
DVCC
0
1
1
Direction Control
PxOUT.y
0
1
Output Signal
Px.y
Input Signal
D
Q
EN
Capacitive Touch Signal 0
Capacitive Touch Signal 1
NOTE: Functional representation only.
图 6-2. Capacitive Touch Functionality on Ports
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
85
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
6.13.2 Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
图 6-3 shows the port diagram. 表 6-20 summarizes the selection of the pin functions.
Pad Logic
(ADC) Reference
(P1.0, P1.1)
To ADC
From ADC
To Comparator
From Comparator
CBPD.x
P1REN.x
0 0
0 1
1 0
1 1
P1DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P1OUT.x
From module 1
From module 2
DVSS
P1.0/TA0.1/DMAE0/RTCCLK/
A0/C0/VREF-/VeREF-
P1.1/TA0.2/TA1CLK/COUT/
A1/C1VREF+/VeREF+
P1SEL1.x
P1SEL0.x
P1IN.x
P1.2/TA1.1/TA0CLK/COUT/A2/C2
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 6-3. Port P1 (P1.0 to P1.2) Diagram
86
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
表 6-20. Port P1 (P1.0 to P1.2) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.0 (I/O)
TA0.CCI1A
TA0.1
I: 0; O: 1
0
0
0
0
1
1
0
1
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/
VREF-/VeREF-
0
DMAE0
RTCCLK(2)
0
1
A0, C0, VREF-, VeREF-(3)(4)
X
1
0
1
0
P1.1 (I/O)
I: 0; O: 1
TA0.CCI2A
TA0.2
0
0
1
1
0
1
P1.1/TA0.2/TA1CLK/COUT/A1/C1/
VREF+/VeREF+
1
2
TA1CLK
COUT(5)
A1, C1, VREF+, VeREF+(3)(4)
0
1
X
1
0
1
0
P1.2 (I/O)
I: 0; O: 1
TA1.CCI1A
TA1.1
0
1
0
1
X
0
1
P1.2/TA1.1/TA0CLK/COUT/A2/C2
(1) X = Don't care
TA0CLK
COUT(5)
A2, C2(3)(4)
1
1
0
1
(2) Do not use this pin as RTCCLK output if the DMAE0 functionality is used on any other pin. Select an alternate RTCCLK output pin.
(3) Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(4) Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.
(5) Do not use this pin as COUT output if the TA1CLK functionality is used on any other pin. Select an alternate COUT output pin.
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
87
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
6.13.3 Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
图 6-4 shows the port diagram. 表 6-21 summarizes the selection of the pin functions.
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CBPD.x
P1REN.x
0 0
0 1
1 0
1 1
P1DIR.x
DVSS
DVCC
0
1
From module 2
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P1OUT.x
From module 1
From module 2
DVSS
P1.3/TA1.2/UCB0STE/A3/C3
P1.4/TB0.1/UCA0STE/A4/C4
P1.5/TB0.2/UCA0CLK/A5/C5
P1SEL1.x
P1SEL0.x
P1IN.x
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 6-4. Port P1 (P1.3 to P1.5) Diagram
88
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
表 6-21. Port P1 (P1.3 to P1.5) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.3 (I/O)
TA1.CCI2A
TA1.2
I: 0; O: 1
0
0
0
0
1
P1.3/TA1.2/UCB0STE/A3/C3
P1.4/TB0.1/UCA0STE/A4/C4
3
1
X(2)
UCB0STE
A3, C3(3)(4)
P1.4 (I/O)
TB0.CCI1A
TB0.1
1
1
0
0
1
0
X
I: 0; O: 1
0
0
1
4
5
1
X(5)
UCA0STE
A4, C4(3)(4)
P1.5(I/O)
TB0.CCI2A
TB0.2
1
1
0
0
1
0
X
I: 0; O: 1
0
0
1
P1.5/TB0.2/UCA0CLK/A5/C5
(1) X = Don't care
1
UCA0CLK
A5, C5(3)(4)
X(5)
X
1
1
0
1
(2) Direction controlled by eUSCI_B0 module.
(3) Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(4) Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.
(5) Direction controlled by eUSCI_A0 module.
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
89
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
6.13.4 Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
图 6-5 shows the port diagram. 表 6-22 summarizes the selection of the pin functions.
Pad Logic
P1REN.x
0 0
0 1
1 0
1 1
P1DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
From module 2
1
0 0
0 1
1 0
1 1
P1OUT.x
From module 1
From module 2
From module 3
P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
P1SEL1.x
P1SEL0.x
P1IN.x
EN
D
To modules
NOTE: Functional representation only.
图 6-5. Port P1 (P1.6 and P1.7) Diagram
表 6-22. Port P1 (P1.6 and P1.7) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.6 (I/O)
TB0.CCI3B
TB0.3
I: 0; O: 1
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1
X(2)
P1.6/TB0.3/UCB0SIMO/UCB0SDA/ TA0.0
6
UCB0SIMO/UCB0SDA
TA0.CCI0A
TA0.0
0
1
P1.7 (I/O)
I: 0; O: 1
TB0.CCI4B
TB0.4
0
1
X(3)
P1.7/TB0.4/UCB0SOMI/UCB0SCL/ TA1.0
(1) X = Don't care
7
UCB0SOMI/UCB0SCL
TA1.CCI0A
TA1.0
0
1
(2) Direction controlled by eUSCI_B0 module.
(3) Direction controlled by eUSCI_A0 module.
90
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.13.5 Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
图 6-6 shows the port diagram. 表 6-23 summarizes the selection of the pin functions.
Pad Logic
P2REN.x
0 0
0 1
1 0
1 1
P2DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
From module 2
1
0 0
0 1
1 0
1 1
P2OUT.x
From module 1
From module 2
From module 3
P2.0/TB0.6/UCA0TXD/UCA0SIMO/
TB0CLK/ACLK
P2.1/TB0.0/UCA0RXD/UCA0SOMI/
TB0.0
P2.2/TB0.2/UCB0CLK
P2SEL1.x
P2SEL0.x
P2IN.x
EN
D
To modules
NOTE: Functional representation only.
图 6-6. Port P2 (P2.0 to P2.2) Diagram
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
91
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-23. Port P2 (P2.0 to P2.2) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL1.x
P2SEL0.x
P2.0 (I/O)
TB0.CCI6B
TB0.6
I: 0; O: 1
0
0
0
0
1
1
0
X
1
0
1
0
1
1
X(2)
P2.0/TB0.6/UCA0TXD/UCA0SIMO/
TB0CLK/ACLK
0
UCA0TXD/UCA0SIMO
TB0CLK
ACLK(3)
0
1
P2.1 (I/O)
I: 0; O: 1
TB0.CCI0A
TB0.0
0
P2.1/TB0.0/UCA0RXD/UCA0SOMI
1
2
1
X(2)
UCA0RXD/UCA0SOMI
P2.2 (I/O)
1
0
0
0
I: 0; O: 1
N/A
0
0
1
1
1
0
1
TB0.2
1
P2.2/TB0.2/UCB0CLK
(1) X = Don't care
(4)
UCB0CLK
N/A
X
0
1
Internally tied to DVSS
(2) Direction controlled by eUSCI_A0 module.
(3) Do not use this pin as ACLK output if the TB0CLK functionality is used on any other pin. Select an alternate ACLK output pin.
(4) Direction controlled by eUSCI_B0 module.
92
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.13.6 Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
图 6-7 shows the port diagram. 表 6-24 summarizes the selection of the pin functions.
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CBPD.x
P2REN.x
0 0
0 1
1 0
1 1
P2DIR.x
DVSS
DVCC
0
1
From module 2
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P2OUT.x
From module 1
From module 2
DVSS
P2.3/TA0.0/UCA1STE/A6/C10
P2.4/TA1.0/UCA1CLK/A7/C11
P2SEL1.x
P2SEL0.x
P2IN.x
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 6-7. Port P2 (P2.3 and P2.4) Diagram
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
93
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-24. Port P2 (P2.3 and P2.4) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL1.x
P2SEL0.x
P2.3 (I/O)
TA0.CCI0B
TA0.0
I: 0; O: 1
0
0
0
0
1
P2.3/TA0.0/UCA1STE/A6/C10
3
1
(2)
UCA1STE
A6, C10(3)(4)
P2.4 (I/O)
TA1.CCI0B
TA1.0
X
1
1
0
0
1
0
X
I: 0; O: 1
0
0
1
P2.4/TA1.0/UCA1CLK/A7/C11
(1) X = Don't care
4
1
(2)
UCA1CLK
A7, C11(3)(4)
X
1
1
0
1
X
(2) Direction controlled by eUSCI_A1 module.
(3) Setting P2SEL1.x and P2SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(4) Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.
94
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.13.7 Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
图 6-8 shows the port diagram. 表 6-25 summarizes the selection of the pin functions.
Pad Logic
P2REN.x
0 0
0 1
1 0
1 1
P2DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
From module 2
1
0 0
0 1
1 0
1 1
P2OUT.x
From module 1
From module 2
DVSS
P2.5/TB0.0/UCA1TXD/UCA1SIMO
P2.6/TB0.1/UCA1RXD/UCA1SOMI
P2SEL1.x
P2SEL0.x
P2IN.x
EN
D
To modules
NOTE: Functional representation only.
图 6-8. Port P2 (P2.5 and P2.6) Diagram
表 6-25. Port P2 (P2.5 and P2.6) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL1.x
P2SEL0.x
P2.5(I/O)
TB0.CCI0B
TB0.0
I: 0; O: 1
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1
X(2)
P2.5/TB0.0/UCA1TXD/UCA1SIMO
5
UCA1TXD/UCA1SIMO
N/A
0
Internally tied to DVSS
1
P2.6(I/O)
I: 0; O: 1
N/A
0
1
X(2)
TB0.1
P2.6/TB0.1/UCA1RXD/UCA1SOMI
(1) X = Don't care
6
UCA1RXD/UCA1SOMI
N/A
0
Internally tied to DVSS
1
(2) Direction controlled by eUSCI_A1 module.
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
95
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
6.13.8 Port P2 (P2.7) Input/Output With Schmitt Trigger
图 6-9 shows the port diagram. 表 6-26 summarizes the selection of the pin functions.
Pad Logic
P2REN.x
0 0
0 1
1 0
1 1
P2DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P2OUT.x
DVSS
DVSS
P2.7
DVSS
P2SEL1.x
P2SEL0.x
P2IN.x
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 6-9. Port P2 (P2.7) Diagram
表 6-26. Port P2 (P2.7) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL1.x
P2SEL0.x
P2.7(I/O)
N/A
I: 0; O: 1
0
0
0
1
0
1
0
1
1
P2.7
7
Internally tied to DVSS
N/A
X
Internally tied to DVSS
(1) X = Don't care
96
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.13.9 Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
图 6-10 shows the port diagram. 表 6-27 summarizes the selection of the pin functions.
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CBPD.x
P3REN.x
0 0
0 1
1 0
1 1
P3DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P3OUT.x
DVSS
DVSS
DVSS
P3.0/A12/C12
P3.1/A13/C13
P3.2/A14/C14
P3.3/A15/C15
P3SEL1.x
P3SEL0.x
P3IN.x
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 6-10. Port P3 (P3.0 to P3.3) Diagram
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
97
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-27. Port P3 (P3.0 to P3.3) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x
P3SEL1.x
P3SEL0.x
P3.0 (I/O)
N/A
I: 0; O: 1
0
0
0
0
1
1
0
Internally tied to DVSS
N/A
1
P3.0/A12/C12
0
0
Internally tied to DVSS
A12/C12(2)(3)
P3.1 (I/O)
1
X
1
0
1
0
I: 0; O: 1
N/A
0
0
1
1
0
Internally tied to DVSS
N/A
1
P3.1/A13/C13
P3.2/A14/C14
1
2
3
0
Internally tied to DVSS
A13/C13(2)(3)
P3.2 (I/O)
1
X
1
0
1
0
I: 0; O: 1
N/A
0
0
1
1
0
Internally tied to DVSS
N/A
1
0
Internally tied to DVSS
A14/C14(2)(3)
P3.3 (I/O)
1
X
1
0
1
0
I: 0; O: 1
N/A
0
1
0
1
X
0
1
Internally tied to DVSS
N/A
P3.3/A15/C15
1
1
0
1
Internally tied to DVSS
A15/C15(2)(3)
(1) X = Don't care
(2) Setting P3SEL1.x and P3SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(3) Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.
98
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.13.10 Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger
图 6-11 shows the port diagram. 表 6-28 summarizes the selection of the pin functions.
Pad Logic
P3REN.x
0 0
0 1
1 0
1 1
P3DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P3OUT.x
From module 1
From module 2
From module 3
P3.4/TB0.3/SMCLK
P3.5/TB0.4/CBOUT
P3.6/TB0.5
P3SEL1.x
P3.7/TB0.6
P3SEL0.x
P3IN.x
EN
D
To modules
NOTE: Functional representation only.
图 6-11. Port P3 (P3.4 to P3.7) Diagram
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
99
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-28. Port P3 (P3.4 to P3.7) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x
P3SEL1.x
P3SEL0.x
P3.4 (I/O)
TB0.CCI3A
TB0.3
I: 0; O: 1
0
0
0
0
1
P3.4/TB0.3/SMCLK
4
1
N/A
0
1
0
0
X
0
1
SMCLK
P3.5 (I/O)
TB0.CCI4A
TB0.4
1
I: 0; O: 1
0
P3.5/TB0.4/COUT
5
6
7
1
N/A
0
1
0
0
X
0
1
COUT
1
P3.6 (I/O)
TB0.CCI5A
TB0.5
I: 0; O: 1
0
P3.6/TB0.5
1
N/A
0
1
0
0
X
0
1
Internally tied to DVSS
P3.7 (I/O)
1
I: 0; O: 1
TB0.CCI6A
0
1
0
1
P3.7/TB0.6
TB0.6
N/A
1
X
Internally tied to DVSS
(1) X = Don't care
100
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.13.11 Port P4 (P4.0 to P4.3) Input/Output With Schmitt Trigger
图 6-12 shows the port diagram. 表 6-29 summarizes the selection of the pin functions.
Pad Logic
To ADC
From ADC
P4REN.x
0 0
0 1
1 0
1 1
P4DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P4OUT.x
DVSS
DVSS
P4.0/A8
P4.1/A9
P4.2/A10
P4.3/A11
DVSS
P4SEL1.x
P4SEL0.x
P4IN.x
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 6-12. Port P4 (P4.0 to P4.3) Diagram
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
101
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-29. Port P4 (P4.0 to P4.3) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x
P4SEL1.x
P4SEL0.x
P4.0 (I/O)
N/A
I: 0; O: 1
0
0
0
0
1
1
0
Internally tied to DVSS
1
P4.0/A8
0
N/A
0
Internally tied to DVSS
1
A8(2)
X
1
0
1
0
P4.1 (I/O)
I: 0; O: 1
N/A
0
0
1
1
0
Internally tied to DVSS
1
P4.1/A9
1
2
3
N/A
0
Internally tied to DVSS
1
A9(2)
X
1
0
1
0
P4.2 (I/O)
I: 0; O: 1
N/A
0
0
1
1
0
Internally tied to DVSS
1
P4.2/A10
N/A
0
Internally tied to DVSS
1
A10(2)
X
1
0
1
0
P4.3 (I/O)
I: 0; O: 1
N/A
0
1
0
1
X
0
1
Internally tied to DVSS
N/A
P4.3/A11
1
1
0
1
Internally tied to DVSS
A11(2)
(1) X = Don't care
(2) Setting P4SEL1.x and P4SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
102
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.13.12 Port P4 (P4.4 to P4.7) Input/Output With Schmitt Trigger
图 6-13 shows the port diagram. 表 6-30 summarizes the selection of the pin functions.
Pad Logic
P4REN.x
0 0
0 1
1 0
1 1
P4DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P4OUT.x
From module 1
DVSS
DVSS
P4.4/TB0.5
P4.5
P4.6
P4SEL1.x
P4.7
P4SEL0.x
P4IN.x
EN
D
To modules
NOTE: Functional representation only.
图 6-13. Port P4 (P4.4 to P4.7) Diagram
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
103
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-30. Port P4 (P4.4 to P4.7) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x
P4SEL1.x
P4SEL0.x
P4.4 (I/O)
TB0.CCI5B
TB0.5
I: 0; O: 1
0
0
0
0
1
P4.4/TB0.5
4
1
N/A
0
1
0
0
X
0
1
Internally tied to DVSS
1
P4.5 (I/O)
I: 0; O: 1
N/A
0
P4.5
P4.6
5
6
7
Internally tied to DVSS
1
N/A
0
1
0
0
X
0
1
Internally tied to DVSS
P4.6 (I/O)
1
I: 0; O: 1
N/A
0
Internally tied to DVSS
N/A
1
0
1
0
0
X
0
1
Internally tied to DVSS
P4.7 (I/O)
1
I: 0; O: 1
N/A
0
1
0
1
P4.7
Internally tied to DVSS
N/A
1
X
Internally tied to DVSS
(1) X = Don't care
104
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.13.13 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
图 6-14 shows the port diagram. 表 6-31 summarizes the selection of the pin functions.
Pad Logic
P5REN.x
0 0
0 1
1 0
1 1
P5DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P5OUT.x
From module 1
DVSS
DVSS
P5.0/UCB1SIMO/UCB1SDA
P5.1/UCB1SOMI/UCB1SCL
P5.2/UCB1CLK/TA4CLK
P5SEL1.x
P5.3/UCB1STE
P5SEL0.x
P5IN.x
P5.4/UCA2TXD/UCA2SIMO/TB0OUTH
P5.5/UCA2RXD/UCA2SOMI/ACLK
P5.6/UCA2CLK/TA4.0/SMCLK
P5.7/UCA2STE/TA4.1/MCLK
EN
D
To modules
NOTE: Functional representation only.
图 6-14. Port P5 (P5.0 to P5.7) Diagram
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
105
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-31. Port P5 (P5.0 to P5.7) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL1.x
P5SEL0.x
P5.0 (I/O)
I: 0; O: 1
X(2)
0
0
0
1
UCB1SIMO/UCB1SDA
N/A
P5.0/UCB1SIMO/UCB1SDA
0
0
1
X
Internally tied to DVSS
P5.1 (I/O)
1
I: 0; O: 1
X(2)
0
0
0
1
UCB1SOMI/UCB1SCL
N/A
P5.1/UCB1SOMI/UCB1SCL
P5.2/UCB1CLK/TA4CLK
P5.3/UCB1STE
1
2
3
4
0
1
X
Internally tied to DVSS
P5.2 (I/O)
1
I: 0; O: 1
X(2)
0
0
0
1
UCB1CLK
TA4CLK
0
1
1
0
1
Internally tied to DVSS
N/A
1
0
Internally tied to DVSS
P5.3 (I/O)
1
I: 0; O: 1
X(2)
0
0
0
1
UCB1STE
N/A
0
1
1
Internally tied to DVSS
P5.4 (I/O)
1
I: 0; O: 1
X(3)
0
0
0
1
UCA2TXD/UCA2SIMO
N/A
0
P5.4/UCA2TXD/UCA2SIMO/TB
0OUTH
1
1
0
1
Internally tied to DVSS
TB0OUTH
1
0
Internally tied to DVSS
P5.5 (I/O)
1
I: 0; O: 1
X(3)
0
0
0
1
UCA2RXD/UCA2SOMI
N/A
0
P5.5/UCA2RXD/UCA2SOMI/AC
LK
5
6
7
0
1
1
1
Internally tied to DVSS
N/A
1
0
ACLK
1
P5.6 (I/O)
I: 0; O: 1
X(3)
0
0
0
1
UCA2CLK
TA4.CCI0A
TA4.0
0
P5.6/UCA2CLK/TA4.0/SMCLK
1
1
0
1
1
N/A
0
SMCLK
1
P5.7 (I/O)
I: 0; O: 1
X(3)
0
0
0
1
UCA2STE
TA4.CCI1A
TA4.1
0
P5.7/UCA2STE/TA4.1/MCLK
(1) X = Don't care
1
1
0
1
1
NA
0
MCLK
1
(2) Direction controlled by eUSCI_B0 module.
(3) Direction controlled by eUSCI_A2 module.
106
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.13.14 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
图 6-15 shows the port diagram. 表 6-32 summarizes the selection of the pin functions.
Pad Logic
P6REN.x
0 0
0 1
1 0
1 1
P6DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P6OUT.x
From module 1
DVSS
DVSS
P6.0/UCA3TXD/UCA3SIMO
P6.1/UCA3RXD/UCA3SOMI
P6.2/UCA3CLK
P6SEL1.x
P6.3/UCA3STE
P6SEL0.x
P6IN.x
P6.4/UCB3SIMO/UCB3SDA
P6.5/UCB3SOMI/UCB3SCL
P6.6/UCB3CLK
P6.7/UCB3STE
EN
D
To modules
NOTE: Functional representation only.
图 6-15. Port P6 (P6.0 to P6.7) Diagram
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
107
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-32. Port P6 (P6.0 to P6.7) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P6.x)
x
FUNCTION
P6DIR.x
P6SEL1.x
P6SEL0.x
P6.0 (I/O)
I: 0; O: 1
X(2)
0
0
0
1
UCA3TXD/UCA3SIMO
N/A
P6.0/UCA3TXD/UCA3SIMO
0
0
1
X
Internally tied to DVSS
P6.1 (I/O)
1
I: 0; O: 1
X(2)
0
0
0
1
UCA3RXD/UCA3SOMI
N/A
P6.1/UCA3RXD/UCA3SOMI
P6.2/UCA3CLK
1
2
3
4
5
6
7
0
1
X
Internally tied to DVSS
P6.2 (I/O)
1
I: 0; O: 1
X(2)
0
0
0
1
UCA3CLK
N/A
0
1
X
Internally tied to DVSS
P6.3 (I/O)
1
I: 0; O: 1
X(2)
0
0
0
1
UCA3STE
P6.3/UCA3STE
N/A
0
1
X
Internally tied to DVSS
P6.4 (I/O)
1
I: 0; O: 1
X(3)
0
0
0
1
UCB3SIMO/UCB3SDA
N/A
P6.4/UCB3SIMO/UCB3SDA
P6.5/UCB3SOMI/UCB3SCL
P6.6/UCB3CLK
0
1
X
Internally tied to DVSS
P6.5 (I/O)
1
I: 0; O: 1
X(3)
0
0
0
1
UCB3SOMI/UCB3SCL
N/A
0
1
X
Internally tied to DVSS
P6.6 (I/O)
1
I: 0; O: 1
X(3)
0
0
0
1
UCB3CLK
N/A
0
1
X
Internally tied to DVSS
P6.7 (I/O)
1
I: 0; O: 1
X(3)
0
0
0
1
UCB3STE
P6.7/UCB3STE
N/A
0
1
X
Internally tied to DVSS
1
(1) X = Don't care
(2) Direction controlled by eUSCI_A3 module.
(3) Direction controlled by eUSCI_B3 module.
108
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.13.15 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
图 6-16 shows the port diagram. 表 6-33 summarizes the selection of the pin functions.
Pad Logic
P7REN.x
0 0
0 1
1 0
1 1
P7DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P7OUT.x
From module 1
DVSS
DVSS
P7.0/UCB2SIMO/UCB2SDA
P7.1/UCB2SOMI/UCB2SCL
P7.2/UCB2CLK
P7SEL1.x
P7.3/UCB2STE/TA4.1
P7SEL0.x
P7IN.x
EN
D
To modules
NOTE: Functional representation only.
图 6-16. Port P7 (P7.0 to P7.3) Diagram
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
109
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-33. Port P7 (P7.0 to P7.3) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P7.x)
x
FUNCTION
P7DIR.x
P7SEL1.x
P7SEL0.x
P7.0 (I/O)
I: 0; O: 1
X(2)
0
0
0
1
UCB2SIMO/UCB2SDA
N/A
P7.0/UCB2SIMO/UCB2SDA
0
0
1
X
Internally tied to DVSS
P7.1 (I/O)
1
I: 0; O: 1
X(2)
0
0
0
1
UCB2SOMI/UCB2SCL
N/A
P7.1/UCB2SOMI/UCB2SCL
P7.2/UCB2CLK
1
2
0
1
X
Internally tied to DVSS
P7.2 (I/O)
1
I: 0; O: 1
X(2)
0
0
0
1
UCB2CLK
N/A
0
1
X
Internally tied to DVSS
P7.3 (I/O)
1
I: 0; O: 1
X(2)
0
0
0
1
UCB2STE
TA4.CCI1B
0
P7.3/UCB2STE/TA4.1
(1) X = Don't care
3
1
1
0
1
TA4.1
1
N/A
0
Internally tied to DVSS
1
(2) Direction controlled by eUSCI_B2 module.
110
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.13.16 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
图 6-17 shows the port diagram. 表 6-34 summarizes the selection of the pin functions.
Pad Logic
To ADC
From ADC
P7REN.x
0 0
0 1
1 0
1 1
P7DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P7OUT.x
DVSS
DVSS
P7.4/TA4.0/A16
P7.5/A17
P7.6/A18
DVSS
P7SEL1.x
P7.7/A19
P7SEL0.x
P4IN.x
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 6-17. Port P7 (P7.3 to P7.7) Diagram
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
111
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-34. Port P7 (P7.3 to P7.7) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P7.x)
x
FUNCTION
P7DIR.x
P7SEL1.x
P7SEL0.x
P7.4 (I/O)
N/A
I: 0; O: 1
0
0
0
0
1
1
0
Internally tied to DVSS
1
P7.4/TA4.0/A16
4
TA4.CCI0B
0
TA4.0
1
A16(2)
X
1
0
1
0
P7.5 (I/O)
I: 0; O: 1
N/A
0
0
1
1
0
Internally tied to DVSS
1
P7.5/A17
P7.6/A18
5
6
7
N/A
0
Internally tied to DVSS
1
A17(2)
X
1
0
1
0
P7.6 (I/O)
I: 0; O: 1
N/A
0
0
1
1
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
A18(2)
1
X
1
0
1
0
P7.7 (I/O)
I: 0; O: 1
N/A
0
1
0
1
X
0
1
Internally tied to DVSS
N/A
P7.7/A19
1
1
0
1
Internally tied to DVSS
A19(2)
(1) X = Don't care
(2) Setting P7SEL1.x and P7SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
112
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.13.17 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
图 6-18 shows the port diagram. 表 6-35 summarizes the selection of the pin functions.
Pad Logic
P8REN.x
0 0
0 1
1 0
1 1
P8DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P8OUT.x
From module 1
DVSS
DVSS
P8.0
P8.1
P8.2
P8.3
P8SEL1.x
P8SEL0.x
P8IN.x
EN
D
To modules
NOTE: Functional representation only.
图 6-18. Port P8 (P8.0 to P8.3) Diagram
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
113
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-35. Port P8 (P8.0 to P8.3) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P8.x)
x
FUNCTION
P8DIR.x
P8SEL1.x
P8SEL0.x
P8.0(I/O)
N/A
I: 0; O: 1
0
0
0
0
1
P8.0
P8.1
P8.2
P8.3
0
Internally tied to DVSS
1
N/A
0
1
0
0
X
0
1
Internally tied to DVSS
1
P8.1 (I/O)
I: 0; O: 1
N/A
0
1
2
3
Internally tied to DVSS
1
N/A
0
1
0
0
X
0
1
Internally tied to DVSS
P8.2 (I/O)
1
I: 0; O: 1
N/A
0
Internally tied to DVSS
N/A
1
0
1
0
0
X
0
1
Internally tied to DVSS
P8.3 (I/O)
1
I: 0; O: 1
N/A
0
1
0
1
Internally tied to DVSS
N/A
1
X
Internally tied to DVSS
(1) X = Don't care
114
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.13.18 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
图 6-19 and 图 6-20 show the port diagrams. 表 6-36 summarizes the selection of the pin functions.
Pad Logic
To LFXT XIN
PJREN.4
0 0
0 1
1 0
1 1
PJDIR.4
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
PJOUT.4
DVSS
DVSS
DVSS
PJ.4/LFXIN
PJSEL1.4
PJSEL0.4
PJIN.4
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 6-19. Port PJ (PJ.4) Diagram
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
115
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
Pad Logic
To LFXT XOUT
PJSEL0.4
PJSEL1.4
LFXTBYPASS
PJREN.5
0 0
0 1
1 0
1 1
PJDIR.5
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
PJOUT.5
DVSS
DVSS
DVSS
PJ.5/LFXOUT
PJSEL1.5
PJSEL0.5
PJIN.5
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 6-20. Port PJ (PJ.5) Diagram
116
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
表 6-36. Port PJ (PJ.4 and PJ.5) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (PJ.x)
x
FUNCTION
PJ.4 (I/O)
LFXT
BYPASS
PJDIR.x
PJSEL1.5
PJSEL0.5
PJSEL1.4
PJSEL0.4
I: 0; O: 1
X
X
0
0
X
N/A
0
1
X
X
1
X
X
PJ.4/LFXIN
4
Internally tied to DVSS
LFXIN crystal mode(2)
LFXIN bypass mode(2)
X
X
X
X
X
X
0
0
0
1
X
0
1
X
0
1
X
0
1
1
0
1
0
0
1(3)
0
PJ.5 (I/O)
N/A
I: 0; O: 1
0
0
X
X
0
(4)
(4)
0
See
See
X
X
0
PJ.5/LFXOUT
5
1(3)
0
(4)
(4)
Internally tied to DVSS
LFXOUT crystal mode(2)
1
See
See
X
X
1
1(3)
0
X
X
X
(1) X = Don't care
(2) If PJSEL1.4 = 0 and PJSEL0.4 = 1, the general-purpose I/O is disabled. When LFXTBYPASS = 0, PJ.4 and PJ.5 are configured for
crystal operation and PJSEL1.5 and PJSEL0.5 are don't care. When LFXTBYPASS = 1, PJ.4 is configured for bypass operation and
PJ.5 is configured as general-purpose I/O.
(3) When PJ.4 is configured in bypass mode, PJ.5 is configured as general-purpose I/O.
(4) If PJSEL0.5 = 1 or PJSEL1.5 = 1, the general-purpose I/O functionality is disabled. No input function is available. Configured as output,
the pin is actively pulled to zero.
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
117
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
6.13.19 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
图 6-21 and 图 6-22 show the port diagrams. 表 6-37 summarizes the selection of the pin functions.
Pad Logic
To HFXT XIN
PJREN.6
0 0
0 1
1 0
1 1
PJDIR.6
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
PJOUT.6
DVSS
DVSS
DVSS
PJ.6/HFXIN
PJSEL1.6
PJSEL0.6
PJIN.6
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 6-21. Port PJ (PJ.6) Diagram
118
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
Pad Logic
To HFXT XOUT
PJSEL0.6
PJSEL1.6
HFXTBYPASS
PJREN.7
0 0
PJDIR.7
0 1
1 0
1 1
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
PJOUT.7
DVSS
DVSS
DVSS
PJ.7/HFXOUT
PJSEL1.7
PJSEL0.7
PJIN.7
Bus
Keeper
EN
D
To modules
NOTE: Functional representation only.
图 6-22. Port PJ (PJ.7) Diagram
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
119
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-37. Port PJ (PJ.6 and PJ.7) Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (PJ.x)
x
FUNCTION
PJ.6 (I/O)
PJDIR.x
PJSEL1.7
PJSEL0.7
PJSEL1.6
PJSEL0.6 HFXTBYPASS
I: 0; O: 1
X
X
0
0
X
N/A
0
1
X
X
1
X
X
PJ.6/HFXIN
6
Internally tied to DVSS
HFXIN crystal mode(2)
HFXIN bypass mode(2)
X
X
X
X
X
X
0
0
0
1
X
0
1
X
0
1
X
0
1
1
0
1
0
0
1(4)
0
PJ.7 (I/O)(3)
I: 0; O: 1
0
0
X
X
0
(3)
(3)
N/A
0
See
See
X
X
0
PJ.7/HFXOUT
7
1(4)
0
(3)
(3)
Internally tied to DVSS
HFXOUT crystal mode(2)
1
See
See
X
X
1
1(4)
0
X
X
X
(1) X = Don't care
(2) Setting PJSEL1.6 = 0 and PJSEL0.6 = 1 causes the general-purpose I/O to be disabled. When HFXTBYPASS = 0, PJ.6 and PJ.7 are
configured for crystal operation and PJSEL1.6 and PJSEL0.7 are do not care. When HFXTBYPASS = 1, PJ.6 is configured for bypass
operation and PJ.7 is configured as general-purpose I/O.
(3) With PJSEL0.7 = 1 or PJSEL1.7 =1 the general-purpose I/O functionality is disabled. No input function is available. Configured as output
the pin is actively pulled to zero.
(4) When PJ.6 is configured in bypass mode, PJ.7 is configured as general-purpose I/O.
120
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.13.20 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With
Schmitt Trigger
图 6-23 shows the port diagram. 表 6-38 summarizes the selection of the pin functions.
To Comparator
From Comparator
Pad Logic
CBPD.x
JTAG enable
From JTAG
From JTAG
PJREN.x
0 0
0 1
1 0
1 1
PJDIR.x
1
0
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
PJOUT.x
From module 1
1
0
From Status Register (SR)
DVSS
PJ.0/TDO/TB0OUTH/SMCLK/
SRSCG1/C6
PJ.1/TDI/TCLK/MCLK/
SRSCG0/C7
PJ.2/TMS/ACLK/
SROSCOFF/C8
PJ.3/TCK/
PJSEL1.x
PJSEL0.x
PJIN.x
Bus
Keeper
EN
D
SRCPUOFF/C9
To modules
and JTAG
NOTE: Functional representation only.
图 6-23. Port PJ (PJ.0 to PJ.3) Diagram
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
121
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-38. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (PJ.x)
x
FUNCTION
PJDIR.x
PJSEL1.x
PJSEL0.x
CEPDx (Cx)
PJ.0 (I/O)(2)
TDO(3)
I: 0; O: 1
0
0
0
0
X
X
X
TB0OUTH
SMCLK(4)
N/A
0
0
1
1
1
0
1
0
0
0
1
PJ.0/TDO/TB0OUTH/
SMCLK/SRSCG1/C6
0
0
CPU Status Register Bit SCG1
1
N/A
0
Internally tied to DVSS
1
C6(5)
PJ.1 (I/O)(2)
TDI/TCLK(3) (6)
X
X
0
X
0
1
0
0
I: 0; O: 1
X
X
X
N/A
0
0
1
1
1
0
1
0
0
0
MCLK
1
PJ.1/TDI/TCLK/MCLK/
SRSCG0/C7
1
2
3
N/A
0
CPU Status Register Bit SCG0
1
N/A
0
Internally tied to DVSS
1
C7(5)
PJ.2 (I/O)(2)
TMS(3) (6)
X
X
0
X
0
1
0
0
I: 0; O: 1
X
X
X
N/A
0
0
1
1
1
0
1
0
0
0
ACLK
1
PJ.2/TMS/ACLK/
SROSCOFF/C8
N/A
0
CPU Status Register Bit OSCOFF
1
N/A
0
Internally tied to DVSS
1
C8(5)
PJ.3 (I/O)(2)
TCK(3) (6)
X
X
0
X
0
1
0
0
I: 0; O: 1
X
0
1
0
1
0
1
X
X
X
N/A
0
1
1
0
0
0
Internally tied to DVSS
PJ.3/TCK/SRCPUOFF/C9
N/A
CPU Status Register Bit CPUOFF
N/A
1
1
0
1
Internally tied to DVSS
C9(5)
X
X
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module. JTAG mode selection is made through the SYS module or by the Spy-Bi-Wire four-
wire entry sequence. Neither PJSEL1.x and PJSEL0.x nor CEPDx bits have an effect in these cases.
(4) Do not use this pin as SMCLK output if the TB0OUTH functionality is used on any other pin. Select an alternate SMCLK output pin.
(5) Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables The output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.
(6) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
122
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.14 Device Descriptors (TLV)
表 6-40 lists the contents of the device descriptor tag-length-value (TLV) structure for MSP430FR59xx(1)
devices including AES. 表 6-39 summarizes the Device IDs of the MSP430FR59xx(1) devices.
表 6-39. Device IDs
DEVICE ID
DEVICE
PACKAGE
01A05h
0x82
01A04h
0xA1
0xA2
0xA3
0xA4
0xA6
MSP430FR5994
MSP430FR59941
MSP430FR5992
MSP430FR5964
MSP430FR5962
ZVW, PN, PM, and RGZ
ZVW, PN, PM, and RGZ
ZVW, PN, PM, and RGZ
ZVW, PN, PM, and RGZ
ZVW, PN, PM, and RGZ
0x82
0x82
0x82
0x82
表 6-40. Device Descriptor Table(1)
MSP430FR59xx (UART BSL)
MSP430FR59941 (I2C BSL)
DESCRIPTION
ADDRESS
01A00h
01A01h
01A02h
01A03h
01A04h
01A05h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Bh
01A0Ch
01A0Dh
01A0Eh
01A0Fh
01A10h
01A11h
01A12h
01A13h
VALUE
06h
ADDRESS
01A00h
01A01h
01A02h
01A03h
VALUE
06h
Info Length
CRC Length
06h
06h
Per unit
Per unit
Per unit
Per unit
CRC Value
Device ID
Info Block
See 表 6-39
01A04h
See 表 6-39
Hardware Revision
Firmware Revision
Die Record Tag
Per unit
Per unit
08h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Bh
01A0Ch
01A0Dh
01A0Eh
01A0Fh
01A10h
01A11h
01A12h
01A13h
Per unit
Per unit
08h
Die Record length
0Ah
0Ah
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Lot/Wafer ID
Die Record
Die X Position
Die Y Position
Test Results
(1) NA = Not applicable, Per unit = content can differ among individual units
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
123
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-40. Device Descriptor Table(1) (continued)
MSP430FR59xx (UART BSL)
MSP430FR59941 (I2C BSL)
DESCRIPTION
ADDRESS
01A14h
01A15h
01A16h
01A17h
01A18h
01A19h
01A1Ah
01A1Bh
01A1Ch
01A1Dh
01A1Eh
01A1Fh
01A20h
01A21h
01A22h
01A23h
01A24h
01A25h
01A26h
01A27h
01A28h
01A29h
01A2Ah
01A2Bh
01A2Ch
01A2Dh
VALUE
11h
ADDRESS
01A14h
01A15h
01A16h
01A17h
01A18h
01A19h
01A1Ah
01A1Bh
01A1Ch
01A1Dh
01A1Eh
01A1Fh
01A20h
01A21h
01A22h
01A23h
01A24h
01A25h
01A26h
01A27h
01A28h
01A29h
01A2Ah
01A2Bh
01A2Ch
01A2Dh
VALUE
11h
ADC12 Calibration Tag
ADC12 Calibration Length
ADC Gain Factor(2)
10h
10h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
12h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
12h
ADC Offset(3)
ADC 1.2-V Reference
Temperature Sensor 30°C
ADC 1.2-V Reference
Temperature Sensor 85°C
ADC12 Calibration
ADC 2.0-V Reference
Temperature Sensor 30°C
ADC 2.0-V Reference
Temperature Sensor 85°C
ADC 2.5-V Reference
Temperature Sensor 30°C
ADC 2.5-V Reference
Temperature Sensor 85°C
REF Calibration Tag
REF Calibration Length
06h
06h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
REF 1.2-V Reference
REF 2.0-V Reference
REF 2.5-V Reference
REF Calibration
(2) ADC Gain: the gain correction factor is measured at room temperature using a 2.5-V external voltage reference without internal buffer
(ADC12VRSEL = 0x2, 0x4, or 0xE). Other settings (for example, using internal reference) can result in different correction factors.
(3) ADC Offset: the offset correction factor is measured at room temperature using ADC12VRSEL= 0x2 or 0x4, an external reference, VR+
external 2.5 V, VR– = AVSS.
=
124
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
表 6-40. Device Descriptor Table(1) (continued)
MSP430FR59xx (UART BSL)
MSP430FR59941 (I2C BSL)
DESCRIPTION
ADDRESS
01A2Eh
01A2Fh
01A30h
01A31h
01A32h
01A33h
01A34h
01A35h
01A36h
01A37h
01A38h
01A39h
01A3Ah
01A3Bh
01A3Ch
01A3Dh
01A3Eh
01A3Fh
01A40h
01A41h
01A42h
01A43h
VALUE
15h
ADDRESS
01A2Eh
01A2Fh
01A30h
01A31h
01A32h
01A33h
01A34h
01A35h
01A36h
01A37h
01A38h
01A39h
01A3Ah
01A3Bh
01A3Ch
01A3Dh
01A3Eh
01A3Fh
01A40h
01A41h
01A42h
01A43h
VALUE
15h
128-Bit Random Number Tag
Random Number Length
10h
10h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
1Ch
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
1Ch
Random Number
128-Bit Random Number(4)
BSL Tag
BSL Length
02h
02h
BSL Configuration
BSL Interface
00h
01h
BSL Interface Configuration
00h
48h
(4) 128-Bit Random Number: The random number is generated during production test using Microsoft's CryptGenRandom() function.
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
125
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
6.15 Memory Map
表 6-41 summarizes the memory map for all device variants.
表 6-41. Memory Organization(1)
MSP430FR5994, MSP430FR5964
MSP430FR5992, MSP430FR5962
Memory (FRAM)
256KB
128KB
Main: interrupt vectors and signatures
Main: code memory
Total size
00FFFFh to 00FF80h
043FFFh to 004000h
00FFFFh to 00FF80h
0023FFFh to 004000h
RAM
4KB
4KB
(shared with LEA on MSP430FR599x)
003BFFh to 002C00h
003BFFh to 002C00h
4KB
4KB
RAM
002BFFh to 001C00h
002BFFh to 001C00h
256 bytes
001AFFh to 001A00h
256 bytes
001AFFh to 001A00h
Device descriptor (TLV) (FRAM)
128 bytes
0019FFh to 001980h
128 bytes
0019FFh to 001980h
Info A
Info B
Info C
Info D
BSL 3
BSL 2
BSL 1
BSL 0
Size
128 bytes
00197Fh to 001900h
128 bytes
00197Fh to 001900h
Information memory (FRAM)
128 bytes
0018FFh to 001880h
128 bytes
0018FFh to 001880h
128 bytes
00187Fh to 001800h
128 bytes
00187Fh to 001800h
512 bytes
0017FFh to 001600h
512 bytes
0017FFh to 001600h
512 bytes
0015FFh to 001400h
512 bytes
0015FFh to 001400h
Bootloader (BSL) memory (ROM)
512 bytes
0013FFh to 001200h
512 bytes
0013FFh to 001200h
512 bytes
0011FFh to 001000h
512 bytes
0011FFh to 001000h
4KB
4KB
Peripherals
Tiny RAM
Reserved
000FFFh to 000020h
000FFFh to 000020h
22 bytes
000001Fh to 00000Ah
22 bytes
000001Fh to 00000Ah
Size
10 bytes
000009h to 000000h
10 bytes
000009h to 000000h
Size
(1) All address space not listed is considered vacant memory.
126
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
6.15.1 Peripheral File Map
表 6-42 lists the base address and offset range for the supported module registers. For complete module
register descriptions, see the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.
表 6-42. Peripherals
OFFSET ADDRESS
MODULE NAME
BASE ADDRESS
RANGE
Special Functions (see 表 6-43)
PMM (see 表 6-44)
0100h
0120h
0140h
0150h
0158h
015Ch
0160h
0180h
01B0h
0200h
0220h
0240h
0260h
0320h
0340h
0380h
03C0h
0400h
0430h
0440h
0470h
04A0h
04C0h
0500h
0510h
0520h
0530h
0540h
0550h
0560h
05A0h
05C0h
05E0h
0600h
0620h
0640h
0680h
06C0h
0700h
07C0h
0800h
08C0h
000h to 01Fh
000h to 01Fh
000h to 00Fh
000h to 007h
000h to 00Fh
000h to 001h
000h to 00Fh
000h to 01Fh
000h to 001h
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 02Fh
000h to 02Fh
000h to 02Fh
000h to 02Fh
000h to 00Fh
000h to 02Fh
000h to 00Fh
000h to 01Fh
000h to 02Fh
000h to 00Fh
000h to 00Fh
000h to 00Fh
000h to 00Fh
000h to 00Fh
000h to 00Fh
000h to 00Fh
000h to 00Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 02Fh
000h to 02Fh
000h to 02Fh
000h to 02Fh
000h to 02Fh
000h to 09Fh
000h to 00Fh
FRAM Controller A (see 表 6-45)
CRC16 (see 表 6-46)
RAM Controller (see 表 6-47)
Watchdog (see 表 6-48)
CS (see 表 6-49)
SYS (see 表 6-50)
Shared Reference (see 表 6-51)
Port P1, P2 (see 表 6-52)
Port P3, P4 (see 表 6-53)
Port P5, P6 (see 表 6-54)
Port P7, P8 (see 表 6-55)
Port PJ (see 表 6-56)
TA0 (see 表 6-57)
TA1 (see 表 6-58)
TB0 (see 表 6-59)
TA2 (see 表 6-60)
Capacitive Touch I/O 0 (see 表 6-61)
TA3 (see 表 6-62)
Capacitive Touch I/O 1 (see 表 6-63)
Real-Time Clock (RTC_C) (see 表 6-64)
32-Bit Hardware Multiplier (see 表 6-65)
DMA General Control (see 表 6-66)
DMA Channel 0 (see 表 6-66)
DMA Channel 1 (see 表 6-66)
DMA Channel 2 (see 表 6-66)
DMA Channel 3 (see 表 6-66)
DMA Channel 4 (see 表 6-66)
DMA Channel 5 (see 表 6-66)
MPU Control (see 表 6-67)
eUSCI_A0 (see 表 6-68)
eUSCI_A1 (see 表 6-69)
eUSCI_A2 (see 表 6-70)
eUSCI_A3 (see 表 6-71)
eUSCI_B0 (see 表 6-72)
eUSCI_B1 (see 表 6-73)
eUSCI_B2 (see 表 6-74)
eUSCI_B3 (see 表 6-75)
TA4 (see 表 6-76)
ADC12_B (see 表 6-77)
Comparator_E (see 表 6-78)
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
127
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-42. Peripherals (continued)
OFFSET ADDRESS
RANGE
MODULE NAME
BASE ADDRESS
CRC32 (see 表 6-79)
AES (see 表 6-80)
LEA(1) (MSP430FR599x only)
0980h
09C0h
0A80h
000h to 02Fh
000h to 00Fh
000h to 07Fh
(1) Direct access to LEA registers is not supported, and TI recommends using the optimized Digital Signal
Processing (DSP) Library for MSP Microcontrollers for the operations that the LEA module supports.
表 6-43. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
ACRONYM
SFRIE1
OFFSET
SFR interrupt enable
SFR interrupt flag
00h
02h
04h
SFRIFG1
SFR reset pin control
SFRRPCR
表 6-44. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
PMM control 0
PMM interrupt flags
PM5 control 0
PMMCTL0
PMMIFG
00h
0Ah
10h
PM5CTL0
表 6-45. FRAM Controller A (FRCTL_A) Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
ACRONYM
FRCTL0
OFFSET
FRAM control 0
General control 0
General control 1
00h
04h
06h
GCCTL0
GCCTL1
表 6-46. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
ACRONYM
CRC16DI
OFFSET
CRC data input
00h
02h
04h
06h
CRC data input reverse byte
CRC initialization and result
CRC result reverse byte
CRCDIRB
CRCINIRES
CRCRESR
表 6-47. RAM Controller Registers (Base Address: 0158h)
REGISTER DESCRIPTION
ACRONYM
RCCTL0
OFFSET
OFFSET
RAM controller control 0
Watchdog timer control
00h
00h
表 6-48. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
ACRONYM
WDTCTL
128
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
表 6-49. CS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
ACRONYM
CSCTL0
OFFSET
CS control 0
CS control 1
CS control 2
CS control 3
CS control 4
CS control 5
CS control 6
00h
02h
04h
06h
08h
0Ah
0Ch
CSCTL1
CSCTL2
CSCTL3
CSCTL4
CSCTL5
CSCTL6
表 6-50. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
System control
SYSCTL
00h
06h
08h
0Ah
0Ch
0Eh
1Ah
1Ch
1Eh
JTAG mailbox control
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
User NMI vector generator
System NMI vector generator
Reset vector generator
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSUNIV
SYSSNIV
SYSRSTIV
表 6-51. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
ACRONYM
REFCTL
OFFSET
Shared reference control
00h
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
129
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-52. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
Port P1 input
P1IN
00h
02h
04h
06h
0Ah
0Ch
0Eh
16h
18h
1Ah
1Ch
01h
03h
05h
07h
0Bh
0Dh
17h
1Eh
19h
1Bh
1Dh
Port P1 output
P1OUT
P1DIR
P1REN
Port P1 direction
Port P1 resistor enable
Port P1 selection 0
Port P1 selection 1
Port P1 interrupt vector word
P1SEL0
P1SEL1
P1IV
Port P1 complement selection
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
P1SELC
P1IES
P1IE
P1IFG
P2IN
Port P2 output
P2OUT
P2DIR
P2REN
P2SEL0
P2SEL1
P2SELC
P2IV
Port P2 direction
Port P2 resistor enable
Port P2 selection 0
Port P2 selection 1
Port P2 complement selection
Port P2 interrupt vector word
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
P2IES
P2IE
P2IFG
表 6-53. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
Port P3 input
P3IN
00h
02h
04h
06h
0Ah
0Ch
0Eh
16h
18h
1Ah
1Ch
01h
03h
05h
07h
0Bh
0Dh
17h
1Eh
19h
1Bh
1Dh
Port P3 output
P3OUT
P3DIR
P3REN
Port P3 direction
Port P3 resistor enable
Port P3 selection 0
P3SEL0
P3SEL1
P3IV
Port P3 selection 1
Port P3 interrupt vector word
Port P3 complement selection
Port P3 interrupt edge select
Port P3 interrupt enable
Port P3 interrupt flag
Port P4 input
P3SELC
P3IES
P3IE
P3IFG
P4IN
Port P4 output
P4OUT
P4DIR
P4REN
P4SEL0
P4SEL1
P4SELC
P4IV
Port P4 direction
Port P4 resistor enable
Port P4 selection 0
Port P4 selection 1
Port P4 complement selection
Port P4 interrupt vector word
Port P4 interrupt edge select
Port P4 interrupt enable
Port P4 interrupt flag
P4IES
P4IE
P4IFG
130
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
表 6-54. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
Port P5 input
P5IN
00h
02h
04h
06h
0Ah
0Ch
0Eh
16h
18h
1Ah
1Ch
01h
03h
05h
07h
0Bh
0Dh
17h
1Eh
19h
1Bh
1Dh
Port P5 output
P5OUT
P5DIR
P5REN
Port P5 direction
Port P5 resistor enable
Port P5 selection 0
Port P5 selection 1
Port P5 interrupt vector word
P5SEL0
P5SEL1
P5IV
Port P5 complement selection
Port P5 interrupt edge select
Port P5 interrupt enable
Port P5 interrupt flag
Port P6 input
P5SELC
P5IES
P5IE
P5IFG
P6IN
Port P6 output
P6OUT
P6DIR
P6REN
P6SEL0
P6SEL1
P6SELC
P6IV
Port P6 direction
Port P6 resistor enable
Port P6 selection 0
Port P6 selection 1
Port P6 complement selection
Port P6 interrupt vector word
Port P6 interrupt edge select
Port P6 interrupt enable
Port P6 interrupt flag
P6IES
P6IE
P6IFG
表 6-55. Port P7, P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
Port P7 input
P7IN
00h
02h
04h
06h
0Ah
0Ch
0Eh
16h
18h
1Ah
1Ch
01h
03h
05h
07h
0Bh
0Dh
17h
1Eh
19h
1Bh
1Dh
Port P7 output
P7OUT
P7DIR
P7REN
Port P7 direction
Port P7 resistor enable
Port P7 selection 0
P7SEL0
P7SEL1
P7IV
Port P7 selection 1
Port P7 interrupt vector word
Port P7 complement selection
Port P7 interrupt edge select
Port P7 interrupt enable
Port P7 interrupt flag
Port P8 input
P7SELC
P7IES
P7IE
P7IFG
P8IN
Port P8 output
P8OUT
P8DIR
P8REN
P8SEL0
P8SEL1
P8SELC
P8IV
Port P8 direction
Port P8 resistor enable
Port P8 selection 0
Port P8 selection 1
Port P8 complement selection
Port P8 interrupt vector word
Port P8 interrupt edge select
Port P8 interrupt enable
Port P8 interrupt flag
P8IES
P8IE
P8IFG
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
131
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-56. Port PJ Registers (Base Address: 0320h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
Port PJ input
PJIN
00h
02h
04h
06h
0Ah
0Ch
16h
Port PJ output
PJOUT
PJDIR
PJREN
Port PJ direction
Port PJ resistor enable
Port PJ selection 0
Port PJ selection 1
PJSEL0
PJSEL1
PJSELC
Port PJ complement selection
表 6-57. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
TA0 control
TA0CTL
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA0 counter
TA0CCTL0
TA0CCTL1
TA0CCTL2
TA0R
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA0 expansion 0
TA0CCR0
TA0CCR1
TA0CCR2
TA0EX0
TA0 interrupt vector
TA0IV
表 6-58. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
TA1 control
TA1CTL
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA1 counter
TA1CCTL0
TA1CCTL1
TA1CCTL2
TA1R
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA1 expansion 0
TA1CCR0
TA1CCR1
TA1CCR2
TA1EX0
TA1 interrupt vector
TA1IV
132
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
表 6-59. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
ACRONYM
TB0CTL
OFFSET
TB0 control
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Capture/compare control 3
Capture/compare control 4
Capture/compare control 5
Capture/compare control 6
TB0 counter
TB0CCTL0
TB0CCTL1
TB0CCTL2
TB0CCTL3
TB0CCTL4
TB0CCTL5
TB0CCTL6
TB0R
Capture/compare 0
TB0CCR0
TB0CCR1
TB0CCR2
TB0CCR3
TB0CCR4
TB0CCR5
TB0CCR6
TB0EX0
Capture/compare 1
Capture/compare 2
Capture/compare 3
Capture/compare 4
Capture/compare 5
Capture/compare 6
TB0 expansion 0
TB0 interrupt vector
TB0IV
表 6-60. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
TA2 control
TA2CTL
TA2CCTL0
TA2CCTL1
TA2R
00h
02h
04h
10h
12h
14h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
TA2 counter
Capture/compare 0
Capture/compare 1
TA2 expansion 0
TA2CCR0
TA2CCR1
TA2EX0
TA2IV
TA2 interrupt vector
表 6-61. Capacitive Touch I/O 0 Registers (Base Address: 0430h)
REGISTER DESCRIPTION
Capacitive Touch I/O 0 control
ACRONYM
CAPTIO0CTL
OFFSET
OFFSET
0Eh
表 6-62. TA3 Registers (Base Address: 0440h)
REGISTER DESCRIPTION
ACRONYM
TA3 control
TA3CTL
TA3CCTL0
TA3CCTL1
TA3R
00h
02h
04h
10h
12h
14h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
TA3 counter
Capture/compare 0
Capture/compare 1
TA3 expansion 0
TA3CCR0
TA3CCR1
TA3EX0
TA3IV
TA3 interrupt vector
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
133
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-63. Capacitive Touch I/O 1 Registers (Base Address: 0470h)
REGISTER DESCRIPTION
ACRONYM
CAPTIO1CTL
OFFSET
Capacitive Touch I/O 1 control
0Eh
表 6-64. RTC_C Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
ACRONYM
RTCCTL0
OFFSET
RTC control 0
00h
01h
02h
03h
04h
06h
08h
0Ah
0Ch
0Dh
0Eh
10h
11h
12h
13h
14h
15h
16h
18h
19h
1Ah
1Bh
1Ch
1Eh
RTC password
RTCPWD
RTC control 1
RTCCTL1
RTC control 3
RTCCTL3
RTC offset calibration
RTC temperature compensation
RTC prescaler 0 control
RTC prescaler 1 control
RTC prescaler 0
RTCOCAL
RTCTCMP
RTCPS0CTL
RTCPS1CTL
RTCPS0
RTC prescaler 1
RTCPS1
RTC interrupt vector word
RTC seconds/counter 1
RTC minutes/counter 2
RTC hours/counter 3
RTC day of week/counter 4
RTC days
RTCIV
RTCSEC/RTCNT1
RTCMIN/RTCNT2
RTCHOUR/RTCNT3
RTCDOW/RTCNT4
RTCDAY
RTC month
RTCMON
RTC year
RTCYEAR
RTC alarm minutes
RTC alarm hours
RTCAMIN
RTCAHOUR
RTCADOW
RTCADAY
RTC alarm day of week
RTC alarm days
Binary-to-BCD conversion
BCD-to-binary conversion
BIN2BCD
BCD2BIN
134
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
表 6-65. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
16-bit operand 1 – multiply
MPY
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
16-bit operand 1 – signed multiply
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
MPYS
MAC
MACS
OP2
16 × 16 result low word
RESLO
RESHI
16 × 16 result high word
16 × 16 sum extension
SUMEXT
MPY32L
MPY32H
MPYS32L
MPYS32H
MAC32L
MAC32H
MACS32L
MACS32H
OP2L
32-bit operand 1 – multiply low word
32-bit operand 1 – multiply high word
32-bit operand 1 – signed multiply low word
32-bit operand 1 – signed multiply high word
32-bit operand 1 – multiply accumulate low word
32-bit operand 1 – multiply accumulate high word
32-bit operand 1 – signed multiply accumulate low word
32-bit operand 1 – signed multiply accumulate high word
32-bit operand 2 – low word
32-bit operand 2 – high word
OP2H
32 × 32 result 0 – least significant word
32 × 32 result 1
RES0
RES1
32 × 32 result 2
RES2
32 × 32 result 3 – most significant word
MPY32 control 0
RES3
MPY32CTL0
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
135
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-66. DMA Registers (Base Address DMA General Control: 0500h,
Channel 0: 0510h, Channel 1: 0520h, Channel 2: 0530h,
Channel 3: 0540h, Channel 4: 0550h, Channel 5: 0560h)
REGISTER DESCRIPTION
ACRONYM
DMA0CTL
OFFSET
DMA channel 0 control
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Eh
DMA channel 0 source address low
DMA channel 0 source address high
DMA channel 0 destination address low
DMA channel 0 destination address high
DMA channel 0 transfer size
DMA0SAL
DMA0SAH
DMA0DAL
DMA0DAH
DMA0SZ
DMA channel 1 control
DMA1CTL
DMA1SAL
DMA1SAH
DMA1DAL
DMA1DAH
DMA1SZ
DMA channel 1 source address low
DMA channel 1 source address high
DMA channel 1 destination address low
DMA channel 1 destination address high
DMA channel 1 transfer size
DMA channel 2 control
DMA2CTL
DMA2SAL
DMA2SAH
DMA2DAL
DMA2DAH
DMA2SZ
DMA channel 2 source address low
DMA channel 2 source address high
DMA channel 2 destination address low
DMA channel 2 destination address high
DMA channel 2 transfer size
DMA channel 3 control
DMA3CTL
DMA3SAL
DMA3SAH
DMA3DAL
DMA3DAH
DMA3SZ
DMA channel 3 source address low
DMA channel 3 source address high
DMA channel 3 destination address low
DMA channel 3 destination address high
DMA channel 3 transfer size
DMA channel 4 control
DMA4CTL
DMA4SAL
DMA4SAH
DMA4DAL
DMA4DAH
DMA4SZ
DMA channel 4 source address low
DMA channel 4 source address high
DMA channel 4 destination address low
DMA channel 4 destination address high
DMA channel 4 transfer size
DMA channel 5 control
DMA5CTL
DMA5SAL
DMA5SAH
DMA5DAL
DMA5DAH
DMA5SZ
DMA channel 5 source address low
DMA channel 5 source address high
DMA channel 5 destination address low
DMA channel 5 destination address high
DMA channel 5 transfer size
DMA module control 0
DMACTL0
DMACTL1
DMACTL2
DMACTL3
DMACTL4
DMAIV
DMA module control 1
DMA module control 2
DMA module control 3
DMA module control 4
DMA interrupt vector
136
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
表 6-67. MPU Control Registers (Base Address: 05A0h)
REGISTER DESCRIPTION
ACRONYM
MPUCTL0
OFFSET
MPU control 0
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
MPU control 1
MPUCTL1
MPU segmentation border 2
MPU segmentation border 1
MPU access management
MPU IP control 0
MPUSEGB2
MPUSEGB1
MPUSAM
MPUIPC0
MPU IP encapsulation segment border 2
MPU IP encapsulation segment border 1
MPUIPSEGB2
MPUIPSEGB1
表 6-68. eUSCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
ACRONYM
UCA0CTLW0
OFFSET
eUSCI_A control word 0
eUSCI _A control word 1
eUSCI_A baud rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
UCA0CTLW1
UCA0BR0
eUSCI_A baud rate 1
UCA0BR1
eUSCI_A modulation control
eUSCI_A status word
UCA0MCTLW
UCA0STATW
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
UCA0IRTCTL
UCA0IRRCTL
UCA0IE
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
UCA0IFG
UCA0IV
表 6-69. eUSCI_A1 Registers (Base Address:05E0h)
REGISTER DESCRIPTION
ACRONYM
UCA1CTLW0
OFFSET
eUSCI_A control word 0
eUSCI _A control word 1
eUSCI_A baud rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
UCA1CTLW1
UCA1BR0
eUSCI_A baud rate 1
UCA1BR1
eUSCI_A modulation control
eUSCI_A status word
UCA1MCTLW
UCA1STATW
UCA1RXBUF
UCA1TXBUF
UCA1ABCTL
UCA1IRTCTL
UCA1IRRCTL
UCA1IE
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
UCA1IFG
UCA1IV
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
137
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-70. eUSCI_A2 Registers (Base Address:0600h)
REGISTER DESCRIPTION
ACRONYM
UCA2CTLW0
OFFSET
eUSCI_A control word 0
eUSCI _A control word 1
eUSCI_A baud rate 0
eUSCI_A baud rate 1
eUSCI_A modulation control
eUSCI_A status word
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
UCA2CTLW1
UCA2BR0
UCA2BR1
UCA2MCTLW
UCA2STATW
UCA2RXBUF
UCA2TXBUF
UCA2ABCTL
UCA2IRTCTL
UCA2IRRCTL
UCA2IE
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
UCA2IFG
eUSCI_A interrupt vector word
UCA2IV
表 6-71. eUSCI_A3 Registers (Base Address:0620h)
REGISTER DESCRIPTION
ACRONYM
UCA3CTLW0
OFFSET
eUSCI_A control word 0
eUSCI _A control word 1
eUSCI_A baud rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
UCA3CTLW1
UCA3BR0
eUSCI_A baud rate 1
UCA3BR1
eUSCI_A modulation control
eUSCI_A status word
UCA3MCTLW
UCA3STATW
UCA3RXBUF
UCA3TXBUF
UCA3ABCTL
UCA3IRTCTL
UCA3IRRCTL
UCA3IE
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
UCA3IFG
UCA3IV
138
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
表 6-72. eUSCI_B0 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
ACRONYM
UCB0CTLW0
OFFSET
eUSCI_B control word 0
eUSCI_B control word 1
eUSCI_B bit rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Ah
2Ch
2Eh
UCB0CTLW1
UCB0BR0
eUSCI_B bit rate 1
UCB0BR1
eUSCI_B status word
UCB0STATW
UCB0TBCNT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA0
UCB0I2COA1
UCB0I2COA2
UCB0I2COA3
UCB0ADDRX
UCB0ADDMASK
UCB0I2CSA
UCB0IE
eUSCI_B byte counter threshold
eUSCI_B receive buffer
eUSCI_B transmit buffer
eUSCI_B I2C own address 0
eUSCI_B I2C own address 1
eUSCI_B I2C own address 2
eUSCI_B I2C own address 3
eUSCI_B received address
eUSCI_B address mask
eUSCI I2C slave address
eUSCI interrupt enable
eUSCI interrupt flags
UCB0IFG
eUSCI interrupt vector word
UCB0IV
表 6-73. eUSCI_B1 Registers (Base Address: 0680h)
REGISTER DESCRIPTION
ACRONYM
UCB1CTLW0
OFFSET
eUSCI_B control word 0
eUSCI_B control word 1
eUSCI_B bit rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Ah
2Ch
2Eh
UCB1CTLW1
UCB1BR0
eUSCI_B bit rate 1
UCB1BR1
eUSCI_B status word
UCB1STATW
UCB1TBCNT
UCB1RXBUF
UCB1TXBUF
UCB1I2COA0
UCB1I2COA1
UCB1I2COA2
UCB1I2COA3
UCB1ADDRX
UCB1ADDMASK
UCB1I2CSA
UCB1IE
eUSCI_B byte counter threshold
eUSCI_B receive buffer
eUSCI_B transmit buffer
eUSCI_B I2C own address 0
eUSCI_B I2C own address 1
eUSCI_B I2C own address 2
eUSCI_B I2C own address 3
eUSCI_B received address
eUSCI_B address mask
eUSCI I2C slave address
eUSCI interrupt enable
eUSCI interrupt flags
UCB1IFG
eUSCI interrupt vector word
UCB1IV
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
139
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-74. eUSCI_B2 Registers (Base Address: 06C0h)
REGISTER DESCRIPTION
ACRONYM
UCB2CTLW0
OFFSET
eUSCI_B control word 0
eUSCI_B control word 1
eUSCI_B bit rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Ah
2Ch
2Eh
UCB2CTLW1
UCB2BR0
eUSCI_B bit rate 1
UCB2BR1
eUSCI_B status word
UCB2STATW
UCB2TBCNT
UCB2RXBUF
UCB2TXBUF
UCB2I2COA0
UCB2I2COA1
UCB2I2COA2
UCB2I2COA3
UCB2ADDRX
UCB2ADDMASK
UCB2I2CSA
UCB2IE
eUSCI_B byte counter threshold
eUSCI_B receive buffer
eUSCI_B transmit buffer
eUSCI_B I2C own address 0
eUSCI_B I2C own address 1
eUSCI_B I2C own address 2
eUSCI_B I2C own address 3
eUSCI_B received address
eUSCI_B address mask
eUSCI I2C slave address
eUSCI interrupt enable
eUSCI interrupt flags
UCB2IFG
eUSCI interrupt vector word
UCB2IV
表 6-75. eUSCI_B3 Registers (Base Address: 0700h)
REGISTER DESCRIPTION
ACRONYM
UCB3CTLW0
OFFSET
eUSCI_B control word 0
eUSCI_B control word 1
eUSCI_B bit rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Ah
2Ch
2Eh
UCB3CTLW1
UCB3BR0
eUSCI_B bit rate 1
UCB3BR1
eUSCI_B status word
UCB3STATW
UCB3TBCNT
UCB3RXBUF
UCB3TXBUF
UCB3I2COA0
UCB3I2COA1
UCB3I2COA2
UCB3I2COA3
UCB3ADDRX
UCB3ADDMASK
UCB3I2CSA
UCB3IE
eUSCI_B byte counter threshold
eUSCI_B receive buffer
eUSCI_B transmit buffer
eUSCI_B I2C own address 0
eUSCI_B I2C own address 1
eUSCI_B I2C own address 2
eUSCI_B I2C own address 3
eUSCI_B received address
eUSCI_B address mask
eUSCI I2C slave address
eUSCI interrupt enable
eUSCI interrupt flags
UCB3IFG
eUSCI interrupt vector word
UCB3IV
140
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
表 6-76. TA4 Registers (Base Address: 07C0h)
REGISTER DESCRIPTION
ACRONYM
TA4CTL
OFFSET
TA4 control
00h
02h
04h
10h
12h
14h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
TA4 counter
TA4CCTL0
TA4CCTL1
TA4R
Capture/compare 0
Capture/compare 1
TA4 expansion 0
TA4CCR0
TA4CCR1
TA4EX0
TA4IV
TA4 interrupt vector
表 6-77. ADC12_B Registers (Base Address: 0800h)
REGISTER DESCRIPTION
ACRONYM
ADC12CTL0
OFFSET
ADC12_B control 0
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
36h
38h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
ADC12_B control 1
ADC12CTL1
ADC12_B control 2
ADC12CTL2
ADC12_B control 3
ADC12CTL3
ADC12_B window comparator low threshold register
ADC12_B window comparator high threshold register
ADC12_B interrupt flag register 0
ADC12_B interrupt flag register 1
ADC12_B interrupt flag register 2
ADC12_B interrupt enable register 0
ADC12_B interrupt enable register 1
ADC12_B interrupt enable register 2
ADC12_B interrupt vector
ADC12LO
ADC12HI
ADC12IFGR0
ADC12IFGR1
ADC12IFGR2
ADC12IER0
ADC12IER1
ADC12IER2
ADC12IV
ADC12_B memory control 0
ADC12_B memory control 1
ADC12_B memory control 2
ADC12_B memory control 3
ADC12_B memory control 4
ADC12_B memory control 5
ADC12_B memory control 6
ADC12_B memory control 7
ADC12_B memory control 8
ADC12_B memory control 9
ADC12_B memory control 10
ADC12_B memory control 11
ADC12_B memory control 12
ADC12_B memory control 13
ADC12_B memory control 14
ADC12_B memory control 15
ADC12_B memory control 16
ADC12_B memory control 17
ADC12_B memory control 18
ADC12_B memory control 19
ADC12_B memory control 20
ADC12_B memory control 21
ADC12_B memory control 22
ADC12MCTL0
ADC12MCTL1
ADC12MCTL2
ADC12MCTL3
ADC12MCTL4
ADC12MCTL5
ADC12MCTL6
ADC12MCTL7
ADC12MCTL8
ADC12MCTL9
ADC12MCTL10
ADC12MCTL11
ADC12MCTL12
ADC12MCTL13
ADC12MCTL14
ADC12MCTL15
ADC12MCTL16
ADC12MCTL17
ADC12MCTL18
ADC12MCTL19
ADC12MCTL20
ADC12MCTL21
ADC12MCTL22
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
141
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
表 6-77. ADC12_B Registers (Base Address: 0800h) (continued)
REGISTER DESCRIPTION
ADC12_B memory control 23
ACRONYM
ADC12MCTL23
OFFSET
4Eh
50h
52h
54h
56h
58h
5Ah
5Ch
5Eh
60h
62h
64h
66h
68h
6Ah
6Ch
6Eh
70h
72h
74h
76h
78h
7Ah
7Ch
7Eh
80h
82h
84h
86h
88h
8Ah
8Ch
8Eh
90h
92h
94h
96h
98h
9Ah
9Ch
9Eh
ADC12_B memory control 24
ADC12_B memory control 25
ADC12_B memory control 26
ADC12_B memory control 27
ADC12_B memory control 28
ADC12_B memory control 29
ADC12_B memory control 30
ADC12_B memory control 31
ADC12_B memory 0
ADC12MCTL24
ADC12MCTL25
ADC12MCTL26
ADC12MCTL27
ADC12MCTL28
ADC12MCTL29
ADC12MCTL30
ADC12MCTL31
ADC12MEM0
ADC12MEM1
ADC12MEM2
ADC12MEM3
ADC12MEM4
ADC12MEM5
ADC12MEM6
ADC12MEM7
ADC12MEM8
ADC12MEM9
ADC12MEM10
ADC12MEM11
ADC12MEM12
ADC12MEM13
ADC12MEM14
ADC12MEM15
ADC12MEM16
ADC12MEM17
ADC12MEM18
ADC12MEM19
ADC12MEM20
ADC12MEM21
ADC12MEM22
ADC12MEM23
ADC12MEM24
ADC12MEM25
ADC12MEM26
ADC12MEM27
ADC12MEM28
ADC12MEM29
ADC12MEM30
ADC12MEM31
ADC12_B memory 1
ADC12_B memory 2
ADC12_B memory 3
ADC12_B memory 4
ADC12_B memory 5
ADC12_B memory 6
ADC12_B memory 7
ADC12_B memory 8
ADC12_B memory 9
ADC12_B memory 10
ADC12_B memory 11
ADC12_B memory 12
ADC12_B memory 13
ADC12_B memory 14
ADC12_B memory 15
ADC12_B memory 16
ADC12_B memory 17
ADC12_B memory 18
ADC12_B memory 19
ADC12_B memory 20
ADC12_B memory 21
ADC12_B memory 22
ADC12_B memory 23
ADC12_B memory 24
ADC12_B memory 25
ADC12_B memory 26
ADC12_B memory 27
ADC12_B memory 28
ADC12_B memory 29
ADC12_B memory 30
ADC12_B memory 31
142
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
表 6-78. Comparator_E Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
ACRONYM
CECTL0
OFFSET
Comparator_E control 0
Comparator_E control 1
Comparator_E control 2
Comparator_E control 3
Comparator_E interrupt
00h
02h
04h
06h
0Ch
0Eh
CECTL1
CECTL2
CECTL3
CEINT
Comparator_E interrupt vector word
CEIV
表 6-79. CRC32 Registers (Base Address: 0980h)
REGISTER DESCRIPTION
ACRONYM
CRC32DIW0
OFFSET
CRC32 data input
Reserved
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
Reserved
CRC32 data input reverse
CRC32 initialization and result word 0
CRC32 initialization and result word 1
CRC32 result reverse word 1
CRC32 result reverse word 0
CRC16 data input
Reserved
CRC32DIRBW0
CRC32INIRESW0
CRC32INIRESW1
CRC32RESRW1
CRC32RESRW1
CRC16DIW0
Reserved
CRC16 data input reverse
CRC16 initialization and result word 0
Reserved
CRC16DIRBW0
CRC16INIRESW0
Reserved
CRC16 result reverse word 0
Reserved
CRC16RESRW0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
表 6-80. AES Accelerator Registers (Base Address: 09C0h)
REGISTER DESCRIPTION
ACRONYM
AESACTL0
OFFSET
AES accelerator control 0
Reserved
00h
02h
AES accelerator status
AES accelerator key
AES accelerator data in
AES accelerator data out
AESASTAT
AESAKEY
AESADIN
04h
06h
008h
00Ah
00Ch
00Eh
AESADOUT
AESAXDIN
AESAXIN
AES accelerator XORed data in
AES accelerator XORed data in (no trigger)
版权 © 2016–2018, Texas Instruments Incorporated
Detailed Description
143
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
6.16 Identification
6.16.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings. For links to all of the errata sheets for the devices
in this data sheet, see 节 8.4.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the Hardware Revision entry in 节 6.14.
6.16.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings. For links to all of the errata sheets for the devices in this data
sheet, see 节 8.4.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the Device ID entry in 节 6.14.
6.16.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
detail in MSP430 Programming With the JTAG Interface.
144
Detailed Description
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
7 Applications, Implementation, and Layout
注
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
7.1 Device Connection and Layout Fundamentals
This section discusses the recommended guidelines when designing with the MSP MCU. These
guidelines are to make sure that the device has proper connections for powering, programming,
debugging, and optimum analog performance.
7.1.1 Power Supply Decoupling and Bulk Capacitors
TI recommends connecting a combination of a 1-µF plus a 100-nF low-ESR ceramic decoupling capacitor
to each AVCC and DVCC pin. Higher-value capacitors may be used but can impact supply rail ramp-up
time. Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a
few millimeters). Additionally, TI recommends separated grounds with a single-point connection for better
noise isolation from digital to analog circuits on the board and to achieve high analog accuracy.
DVCC
Digital Power
Supply Decoupling
+
DVSS
AVCC
1 µF
100 nF
Analog Power
Supply Decoupling
+
AVSS
1 µF
100 nF
图 7-1. Power Supply Decoupling
7.1.2 External Oscillator
Depending on the device variant (see Section 3), the device can support a low-frequency crystal (32 kHz)
on the LFXT pins, a high-frequency crystal on the HFXT pins, or both. External bypass capacitors for the
crystal oscillator pins are required.
It is also possible to apply digital clock signals to the LFXIN and HFXIN input pins that meet the
specifications of the respective oscillator if the appropriate LFXTBYPASS or HFXTBYPASS mode is
selected. In this case, the associated LFXOUT and HFXOUT pins can be used for other purposes. If they
are left unused, they must be terminated according to Section 4.6.
图 7-2 shows a typical connection diagram.
版权 © 2016–2018, Texas Instruments Incorporated
Applications, Implementation, and Layout
145
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
LFXIN
or
LFXOUT
or
HFXIN
HFXOUT
CL1
CL2
图 7-2. Typical Crystal Connection
See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal
oscillator with the MSP MCUs.
7.1.3 JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or
MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the
connections also support the MSP-GANG production programmers, thus providing an easy way to
program prototype boards, if desired. 图 7-3 shows the connections between the 14-pin JTAG connector
and the target device required to support in-system programming and debugging for 4-wire JTAG
communication. 图 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are
identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSP-
FET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an
alternate connection (pin 4 instead of pin 2). The VCC-sense feature senses the local VCC present on the
target board (that is, a battery or other local power supply) and adjusts the output signals accordingly. 图
7-3 and 图 7-4 show a jumper block that supports both scenarios of supplying VCC to the target board. If
this flexibility is not required, the desired VCC connections may be hard-wired to eliminate the jumper
block. Pins 2 and 4 must not be connected at the same time.
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User’s
Guide.
146
Applications, Implementation, and Layout
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
J2 (see Note A)
AVCC/DVCC
R1
47 kW
JTAG
RST/NMI/SBWTDIO
VCC TOOL
TDO/TDI
TDI
TDO/TDI
TDI
2
1
VCC TARGET
4
3
TMS
TMS
6
5
7
TEST
TCK
8
TCK
GND
RST
10
12
14
9
11
13
TEST/SBWTCK
AVSS/DVSS
C1
2.2 nF
(see Note B)
Copyright © 2016, Texas Instruments Incorporated
A. If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,
make connection J2.
B. The upper limit for C1 is 2.2 nF when using current TI tools.
图 7-3. Signal Connections for 4-Wire JTAG Communication
版权 © 2016–2018, Texas Instruments Incorporated
Applications, Implementation, and Layout
147
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
J2 (see Note A)
AVCC/DVCC
R1
47 kΩ
See Note B
JTAG
VCC TOOL
TDO/TDI
2
4
6
8
1
3
5
7
RST/NMI/SBWTDIO
VCC TARGET
TCK
GND
10
12
14
9
11
13
TEST/SBWTCK
AVSS/DVSS
C1
2.2 nF
See Note B
Copyright © 2016, Texas Instruments Incorporated
A. Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the
debug or programming adapter.
B. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with
the device. The upper limit for C1 is 2.2 nF when using current TI tools.
图 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
7.1.4 Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the SFRRPCR
register.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is
edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the
external NMI. When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either
pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.
If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an
external 47-kΩ pullup resistor to the RST/NMI pin with a 10-nF pulldown capacitor. The pulldown capacitor
should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire
JTAG mode with TI tools like FET interfaces or GANG programmers.
See the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide for
more information on the referenced control registers and bits.
7.1.5 Unused Pins
For details on the connection of unused pins, see Section 4.6.
148
Applications, Implementation, and Layout
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
7.1.6 General Layout Recommendations
•
Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430
32-kHz Crystal Oscillators for recommended layout guidelines.
•
•
Proper bypass capacitors on DVCC, AVCC, and reference pins if used.
Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital
switching signals such as PWM or JTAG signals away from the oscillator circuit.
•
•
See Circuit Board Layout Techniques for a detailed discussion of PCB layout considerations. This
document is written primarily about op amps, but the guidelines are generally applicable for all mixed-
signal applications.
Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See MSP430 System-Level ESD Considerations for guidelines.
7.1.7 Do's and Don'ts
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up,
power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the
limits specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the
device, including erroneous writes to RAM and FRAM.
7.2 Peripheral- and Interface-Specific Design Information
7.2.1 ADC12_B Peripheral
7.2.1.1 Partial Schematic
图 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The
internal reference module has a maximum drive current as specified in the IO(VREF+) parameter of the REF
module.
AVSS
VREF+/VEREF+
Using an
External
Positive
Reference
+
470 nF
10 µF
VEREF-
Using an
External
+
Negative
Reference
10 µF
470 nF
图 7-5. ADC12_B Grounding and Noise Considerations
7.2.1.2 Design Requirements
As with any high-resolution ADC, the appropriate printed-circuit-board layout and grounding techniques
should be followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with
other analog or digital circuitry. If care is not taken, this current can generate small, unwanted offset
voltages that can add to or subtract from the reference or input voltages of the ADC. The general
guidelines in 节 7.1.1, combined with the connections shown in 节 7.2.1.1, prevent these offsets.
版权 © 2016–2018, Texas Instruments Incorporated
Applications, Implementation, and Layout
149
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital
switching or switching power supplies can corrupt the conversion result. TI recommends a noise-free
design using separate analog and digital ground planes with a single-point connection to achieve high
accuracy.
The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are
selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage
enters the device. In this case, the 10-µF capacitor is used to buffer the reference pin and filter any low-
frequency ripple. A 470-nF bypass capacitor filters out any high-frequency noise.
7.2.1.3 Detailed Design Procedure
For additional design information, see Designing With the MSP430FR58xx, FR59xx, FR68xx, and FR69xx
ADC.
7.2.1.4 Layout Guidelines
Components that are shown in the partial schematic (see 图 7-5) should be placed as close as possible to
the respective device pins. Avoid long traces, because they add additional parasitic capacitance,
inductance, and resistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),
because the high-frequency switching can be coupled into the analog signal.
If differential mode is used for the ADC12_B, the analog differential input signals must be routed closely
together to minimize the effect of noise on the resulting signal.
150
Applications, Implementation, and Layout
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
8 器件和文档支持
8.1 入门和下一步
有关 MSP 系列微控制器以及开发协助工具和库的更多信息，请访问入门页面。
8.2 器件命名规则
为了标示产品开发周期所处的阶段，TI 为所有 MSP MCU 器件的部件号分配了前缀。每个 MSP MCU 商用
系列产品成员都具有以下两个前缀之一：MSP 或 XMS。这些前缀代表了产品开发的发展阶段，即从工程原
型 (XMS) 直到完全合格的生产器件 (MSP)。
XMS - 实验器件，不一定代表最终器件的电气规格
MSP - 完全合格的生产器件
XMS 器件在供货时附带如下免责声明：
“开发中的产品用于内部评估用途。”
MSP 器件的特性已经全部明确，并且器件的质量和可靠性已经完全论证。TI 的标准保修证书对该器件适
用。
预测显示原型器件 (XMS) 的故障率大于标准生产器件。由于这些器件的预计最终使用故障率尚不确定，德
州仪器 (TI) 建议不要将它们用于任何生产系统。请仅使用合格的生产器件。
TI 器件的命名规则还包括一个带有器件系列名称的后缀。此后缀表示温度范围、封装类型和配送形式。图 8-
1 提供了解读完整器件名称的图例。
MSP
430
FR
5
9941
I
RGC
R
Feature Set
Processor Family
Distribution Format
Platform
Memory Type
Packaging
Temperature Range
Series
AES
Oscillators, LEA
Optional: BSL
FRAM
Processor Family
Platform
MSP = Mixed Signal Processor
XMS = Experimental Silicon
430 = TI’s 16-bit MSP430 Low-Power Microcontroller Platform
MemoryType
Series
FR = FRAM
5 = Up to 16 MHz without LCD
Feature Set
First Digit: AES Second Digit: Oscillators, LEA Third Digit: FRAM (KB) Optional Fourth Digit: BSL
9 = AES
9 = HFXT/LFXT and LEA
6 = HFXT/LFXT
4 = 256
2 = 128
1 = I2C
No value = UART
Temperature Range I = –40°C to 85°C
Packaging
www.ti.com/packaging
Distribution Format
T = Small reel
R = Large reel
No markings = Tube or tray
图 8-1. 器件命名规则
版权 © 2016–2018, Texas Instruments Incorporated
器件和文档支持
151
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
8.3 工具与软件
所有 MSP 微控制器均受多种软件和硬件开发工具的支持。相关工具由 TI 以及多家第三方供应商提供。可从
低功耗 MCU 开发套件和软件获取全部信息。
有关可用硬件特性的详细信息，请参见 ™《适用于 MSP430 的 Code Composer Studio 用户 指南》。表 8-
1 列出了 MSP430FR235x 和 MSP430FR215x 微控制器所 MSP430FR599x 和 MSP430FR596x MCU 硬件
支持的调试特性。
表 8-1. 调试 特性
4 线
JTAG
2 线
JTAG
断点
(N)
状态序列发生
器
LPMx.5 调试支 EnergyTrace++ 技
MSP 架构
范围断点
有
时钟控制
是
跟踪缓冲器
否
持
术
MSP430Xv2
有
有
3
否
有
有
EnergyTrace™技术可用于 Code Composer Studio 6.0 及更高版本。它需要专用的调试器电路，而新一代
板载 eZ-FET 闪存仿真工具和新一代独立 MSP-FET JTAG 仿真器支持这种电路。有关详细信息，请参见以
下文档：
《MSP430 高级功耗优化：ULP Advisor™ 和 EnergyTrace™ 技术》
《使用 Code Composer Studio 与增强型仿真模块 (EEM) 进行高级调试》
《MSP430 硬件工具用户指南》
设计套件与评估模块
™MSP430FR5994 LaunchPad 开发套件
MSP-EXP430FR5994
LaunchPad
开发套件是适用于
MSP430FR5994 微控制器 (MCU) 的易用型评估模块 (EVM)。它包含在超低功耗 MSP430FRx
FRAM 微控制器平台上进行开发所需的全部资源，包括一个用于编程、调试和能量测量的调试
探针。
适用于 MSP430F599x MCU 的 80 引脚目标开发板和 MSP-FET 编程器包 目标插接板可利用 JTAG 轻松实
现器件编程和调试。板上还配有用于原型设计的排针引脚。目标插接板可单独订购，也可以与
JTAG 编程器和调试器一起作为套件订购。
适用于 MSP430F599x MCU 的 80 引脚目标开发板 MSP-TS430PN80B 是一款独立的 80 引脚 ZIF 插接目
标板，适用于通过 JTAG 接口或 Spy Bi-Wire（双线制 JTAG）协议对 MSP430 MCU 系统内
置器件进行编程和调试。
软件
MSP430Ware™ 软件 MSP430Ware 软件集合了所有 MSP430 器件的代码示例、数据表以及其他设计资
源，打包提供给用户。除了提供已有 MSP430 MCU 设计资源的完整集合外，MSP430Ware
软件还包含名为 MSP 驱动程序库的高级 API。借助该库可以轻松地对 MSP430 硬件进行编
程。MSP430Ware 软件以 CCS 组件或独立软件包两种形式提供。
MSP430FR599x、MSP430FR596x 代码示例 根据不同应用需求配置各集成外设的每个 MSP 器件均具备相
应的 C 代码示例。
电容式触摸软件库 可在 MSP430 MCU 启用电容触控功能的免费 C 代码库。该代码库 采用 多种电容触控
实现方法，包括 RO 和 RC 方法。除了完整的 C 代码库，还提供了硬件设计注意事项，简单
指导如何在任何基于 MSP430 的应用中加入电容触控功能。
MSP EnergyTrace 技术 适用于 MSP430 微控制器的 EnergyTrace 技术是基于电能的代码分析工具，适用
于测量和显示应用的电能系统配置并帮助优化应用以实现超低功耗。
152
器件和文档支持
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
MSP 驱动程序库 驱动程序库的抽象化 API 通过提供易于使用的函数调用使您不再拘泥于 MSP430 硬件的
细节。完整的文档通过具有帮助意义的 API 指南交付，其中包括有关每个函数调用和经过验证
的参数的详细信息。开发人员可使用驱动程序库函数以尽可能低的费用编写全部项目。
数字信号处理库
该德州仪器 (TI) 数字信号处理库是一组经高度优化的函数，可针对 MSP430™
和
MSP432 微控制器对定点数 功耗™特性。该功能集通常 用于 要求完成实时密集处理转换，从
而以最低能耗实现高精度的应用。对于定点数学，该库可最大程度地利用 MSP 系列的固有硬
件，从而获得极大的性能增益。
适用于 MSP 超低功耗微控制器的 FRAM 嵌入式软件实用程序 FRAM 实用程序旨在作为不断扩充的嵌入式
软件实用程序集合，其中的实用程序充分利用 FRAM 的超低功耗和近乎无限次的写入寿命。
这些实用程序适用于 MSP430FRxx FRAM 微控制器并提供示例代码协助应用程序开发。其中
的实用程序包含功耗计算实用程序 (CTPL)。CTPL 是一种实用程序 API 集，能够确保方便使
用 LPMx.5 低功耗模式和强大的关断模式；该关断模式使得应用程序在检测到掉电时保存并恢
复重要系统组件。
开发工具
适用于 MSP 微控制器的 Code Composer Studio 集成开发环境 Code Composer Studio 是一种集成开发
环境 (IDE)，支持所有 MSP 微控制器。Code Composer Studio 包含一整套开发和调试嵌入式
应用 的嵌入式软件实用程序的工具。它包含了优化的 C/C++ 编译器、源代码编辑器、项目构
建环境、调试器、描述器以及其他多种 功能。
适用于 TI 微控制器的 Uniflash 独立闪存工具 CCS Uniflash 是一款独立工具，用于对 TI MCU 中的片上闪
存以及 Sitara 处理器的板载闪存进行编程。Uniflash 具有 GUI、命令行和脚本接口。CCS
UniFlash 免费提供。
MSP MCU 编程器和调试器 MSP-FET 是一款强大的仿真开发工具（通常称为调试探针），可允许用户在
MSP 低功耗微控制器 (MCU) 上快速进行应用开发。创建 MCU 软件通常需要将生成的二进制
程序下载到 MSP 器件，以进行验证和调试。MSP-FET 在主机和目标 MSP 间提供调试通信通
道。
MSP-GANG 生产编程器 MSP Gang 编程器是一款 MSP430 或 MSP432 器件编程器，可同时对多达八个完
全相同的 MSP430 或 MSP432 闪存或 FRAM 器件进行编程。MSP Gang 编程器可使用标准
的 RS-232 或 USB 连接与主机 PC 相连并提供灵活的编程选项，允许用户完全自定义流程。
MSP Gang 编程器配有扩展板“Gang 分离器”，可在 MSP Gang 编程器和多个目标器件间实现
互连。
版权 © 2016–2018, Texas Instruments Incorporated
器件和文档支持
153
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
8.4 文档支持
以下文档介绍 MSP430FR599x 和 MSP430FR596x MCU。www.ti.com.cn 网站上提供了这些文档的副本。
接收文档更新通知
要接收文档更新通知（包括芯片勘误表），请转至 ti.com.cn 上您的器件对应的产品文件夹（关于产品文件
夹的链接，请参见节 8.5）。请单击右上角的“通知我”按钮。点击注册后，即可收到产品信息更改每周摘要
（如有）。有关更改的详细信息，请查阅已修订文档的修订历史记录。
勘误
《MSP430FR5994 器件勘误表》 描述了功能技术规格的已知例外情况。
《MSP430FR59941 器件勘误表》 描述了功能技术规格的已知例外情况。
《MSP430FR5992 器件勘误表》 描述了功能技术规格的已知例外情况。
《MSP430FR5964 器件勘误表》 描述了功能技术规格的已知例外情况。
《MSP430FR5962 器件勘误表》 描述了功能技术规格的已知例外情况。
用户指南
《MSP430FR58xx、MSP430FR59xx 和 MSP430FR6xx 系列用户指南》 该器件系列提供的所有模块和外
设的详细 说明 。
《MSP430 FRAM 器件引导加载程序 (BSL) 用户指南》 MSP430 MCU 上的引导加载程序 (BSL) 允许用户
在原型设计、投产和维护等各阶段与 MSP430 MCU 中的嵌入式存储器进行通信。可编程存储
器 (FRAM) 和数据存储器 (RAM) 均可按要求予以修改。
《通过 JTAG 接口对 MSP430 进行编程》 此文档介绍了使用 JTAG 通信端口擦除、编程和验证基于
MSP430 闪存和 FRAM 的微控制器系列的存储器模块所需的功能。此外，该文档还介绍了如
何编程所有 MSP430 器件上均具备的 JTAG 访问安全保险丝。此文档介绍了使用标准四线制
JTAG 接口和两线制 JTAG 接口（也称为 Spy-Bi-Wire (SBW)）的器件访问。
《MSP430 硬件工具用户指南》 此手册介绍了 TI MSP-FET430 闪存仿真工具 (FET) 的硬件。FET 是针对
MSP430
超低功耗微控制器的程序开发工具。文中对提供的接口类型，即并行端口接口和
USB 接口进行了说明。
应用报告
《MSP430 32kHz 晶体振荡器》 选择合适的晶体、正确的负载电路和适当的电路板布局是实现稳定的晶体
振荡器的关键。该应用报告总结了晶体振荡器的功能，介绍了用于选择合适的晶体以实现
MSP430 超低功耗运行的参数。此外，还给出了正确电路板布局的提示和示例。此外，为了确
保振荡器在大规模生产后能够稳定运行，还可能需要进行一些振荡器测试，该文档中提供了有
关这些测试的详细信息。
《MSP430 系统级 ESD 注意事项》 随着硅晶技术向更低电压方向发展以及设计具有成本效益的超低功耗组
件的需求的出现，系统级 ESD 要求变得越来越苛刻。本应用报告解决了三大不同的 ESD 主
题，帮助电路板设计人员和 OEM 了解并设计强大的系统级设计：(1) 组件级 ESD 测试和系统
级 ESD 测试；(2) 实现不同水平的系统级 ESD 保护的通用设计指南；(3) 系统高效 ESD 设计
(SEED) 简介。
154
器件和文档支持
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com.cn
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
8.5 相关链接
表 8-2 列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品
的快速链接。
表 8-2. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
MSP430FR5994
MSP430FR59941
MSP430FR5992
MSP430FR5964
MSP430FR5962
8.6 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术
规范，并且不一定反映 TI 的观点；请参见 TI 的 《使用条款》。
TI E2E™ 社区
TI 的工程师交流 (E2E) 社区. 此社区的创建目的是为了促进工程师之间协作。在 e2e.ti.com 中，您可以提
问、共享知识、拓展思路，在同领域工程师的帮助下解决问题。
TI 嵌入式处理器维基网页
德州仪器 (TI) 嵌入式处理器维基网页。此网站的建立是为了帮助开发人员熟悉德州仪器 (TI) 的嵌入式处理
器，并且也为了促进与这些器件相关的硬件和软件的总体知识的创新和增长。
8.7 商标
LaunchPad, MSP430Ware, MSP430, Code Composer Studio, EnergyTrace, 功耗, E2E are trademarks of
Texas Instruments.
Arm, Cortex are registered trademarks of Arm Limited.
LaunchPad, MSP430Ware, MSP430, Code Composer Studio, EnergyTrace, are trademarks of ~ Texas
Instruments.
All other trademarks are the property of their respective owners.
8.8 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
8.9 出口管制提示
接收方同意：如果美国或其他适用法律限制或禁止将通过非披露义务的披露方获得的任何产品或技术数据
（其中包括软件）（见美国、欧盟和其他出口管理条例之定义）、或者其他适用国家条例限制的任何受管制
产品或此项技术的任何直接产品出口或再出口至任何目的地，那么在没有事先获得美国商务部和其他相关政
府机构授权的情况下，接收方不得在知情的情况下，以直接或间接的方式将其出口。
8.10 术语表
TI 术语表
这份术语表列出并解释术语、缩写和定义。
版权 © 2016–2018, Texas Instruments Incorporated
器件和文档支持
155
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
ZHCSF37C –MARCH 2016–REVISED AUGUST 2018
www.ti.com.cn
9 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通
知，且不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
156
机械、封装和可订购信息
版权 © 2016–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430FR5962IPMR
MSP430FR5962IPNR
MSP430FR5962IRGZR
MSP430FR5962IZVWR
MSP430FR5964IPMR
MSP430FR5964IPNR
MSP430FR5964IRGZR
MSP430FR5964IZVWR
MSP430FR5992IPMR
MSP430FR5992IPNR
MSP430FR5992IRGZR
MSP430FR5992IZVWR
MSP430FR59941IPM
MSP430FR59941IPMR
MSP430FR59941IPN
MSP430FR59941IPNR
MSP430FR59941IRGZR
MSP430FR59941IRGZT
MSP430FR59941IZVW
MSP430FR59941IZVWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
PM
PN
64
80
48
87
64
80
48
87
64
80
48
87
64
64
80
80
48
48
87
87
1000 RoHS & Green
1000 RoHS & Green
2500 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
2500 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
2500 RoHS & Green
1000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
FR5962
NIPDAU
NIPDAU
SNAGCU
NIPDAU
NIPDAU
NIPDAU
SNAGCU
NIPDAU
NIPDAU
NIPDAU
SNAGCU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
SNAGCU
SNAGCU
FR5962
FR5962
FR5962
FR5964
FR5964
FR5964
FR5964
FR5992
FR5992
FR5992
FR5992
FR59941
FR59941
FR59941
FR59941
FR59941
FR59941
FR59941
FR59941
VQFN
NFBGA
LQFP
RGZ
ZVW
PM
LQFP
PN
VQFN
NFBGA
LQFP
RGZ
ZVW
PM
LQFP
PN
VQFN
NFBGA
LQFP
RGZ
ZVW
PM
160
1000 RoHS & Green
119 RoHS & Green
RoHS & Green
LQFP
PM
LQFP
PN
LQFP
PN
1000 RoHS & Green
2500 RoHS & Green
VQFN
VQFN
NFBGA
NFBGA
RGZ
RGZ
ZVW
ZVW
250
250
RoHS & Green
RoHS & Green
1000 RoHS & Green
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430FR5994IPM
MSP430FR5994IPMR
MSP430FR5994IPN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
PM
PM
64
64
80
80
48
48
87
87
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
FR5994
1000 RoHS & Green
119 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
SNAGCU
SNAGCU
FR5994
FR5994
FR5994
FR5994
FR5994
FR5994
FR5994
LQFP
PN
MSP430FR5994IPNR
MSP430FR5994IRGZR
MSP430FR5994IRGZT
MSP430FR5994IZVW
MSP430FR5994IZVWR
LQFP
PN
1000 RoHS & Green
2500 RoHS & Green
VQFN
VQFN
NFBGA
NFBGA
RGZ
RGZ
ZVW
ZVW
250
250
RoHS & Green
RoHS & Green
1000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430FR5962IPMR
MSP430FR5962IPNR
MSP430FR5962IRGZR
LQFP
LQFP
VQFN
PM
PN
64
80
48
87
64
80
48
87
64
80
48
87
64
80
48
87
1000
1000
2500
1000
1000
1000
2500
1000
1000
1000
2500
1000
1000
1000
250
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
180.0
330.0
24.4
24.4
16.4
16.4
24.4
24.4
16.4
16.4
24.4
24.4
16.4
16.4
24.4
24.4
16.4
16.4
13.0
16.0
7.3
13.0
16.0
7.3
2.1
2.0
1.1
1.5
2.1
2.0
1.1
1.5
2.1
2.0
1.1
1.5
2.1
2.0
1.1
1.5
16.0
24.0
12.0
12.0
16.0
24.0
12.0
12.0
16.0
24.0
12.0
12.0
16.0
24.0
12.0
12.0
24.0
24.0
16.0
16.0
24.0
24.0
16.0
16.0
24.0
24.0
16.0
16.0
24.0
24.0
16.0
16.0
Q2
Q2
Q2
Q1
Q2
Q2
Q2
Q1
Q2
Q2
Q2
Q1
Q2
Q2
Q2
Q1
RGZ
ZVW
PM
MSP430FR5962IZVWR NFBGA
6.3
6.3
MSP430FR5964IPMR
MSP430FR5964IPNR
MSP430FR5964IRGZR
LQFP
LQFP
VQFN
13.0
16.0
7.3
13.0
16.0
7.3
PN
RGZ
ZVW
PM
MSP430FR5964IZVWR NFBGA
6.3
6.3
MSP430FR5992IPMR
MSP430FR5992IPNR
MSP430FR5992IRGZR
LQFP
LQFP
VQFN
13.0
16.0
7.3
13.0
16.0
7.3
PN
RGZ
ZVW
PM
MSP430FR5992IZVWR NFBGA
6.3
6.3
MSP430FR59941IPMR
MSP430FR59941IPNR
LQFP
LQFP
13.0
16.0
7.3
13.0
16.0
7.3
PN
MSP430FR59941IRGZT VQFN
MSP430FR59941IZVWR NFBGA
RGZ
ZVW
1000
6.3
6.3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430FR5994IPMR
MSP430FR5994IPNR
MSP430FR5994IRGZR
MSP430FR5994IRGZT
LQFP
LQFP
VQFN
VQFN
PM
PN
64
80
48
48
87
1000
1000
2500
250
330.0
330.0
330.0
180.0
330.0
24.4
24.4
16.4
16.4
16.4
13.0
16.0
7.3
13.0
16.0
7.3
2.1
2.0
1.1
1.1
1.5
16.0
24.0
12.0
12.0
12.0
24.0
24.0
16.0
16.0
16.0
Q2
Q2
Q2
Q2
Q1
RGZ
RGZ
ZVW
7.3
7.3
MSP430FR5994IZVWR NFBGA
1000
6.3
6.3
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430FR5962IPMR
MSP430FR5962IPNR
MSP430FR5962IRGZR
MSP430FR5962IZVWR
MSP430FR5964IPMR
MSP430FR5964IPNR
MSP430FR5964IRGZR
MSP430FR5964IZVWR
MSP430FR5992IPMR
MSP430FR5992IPNR
MSP430FR5992IRGZR
MSP430FR5992IZVWR
MSP430FR59941IPMR
MSP430FR59941IPNR
MSP430FR59941IRGZT
MSP430FR59941IZVWR
MSP430FR5994IPMR
MSP430FR5994IPNR
LQFP
LQFP
VQFN
NFBGA
LQFP
LQFP
VQFN
NFBGA
LQFP
LQFP
VQFN
NFBGA
LQFP
LQFP
VQFN
NFBGA
LQFP
LQFP
PM
PN
64
80
48
87
64
80
48
87
64
80
48
87
64
80
48
87
64
80
1000
1000
2500
1000
1000
1000
2500
1000
1000
1000
2500
1000
1000
1000
250
336.6
367.0
367.0
336.6
336.6
367.0
367.0
336.6
336.6
367.0
367.0
336.6
336.6
367.0
210.0
336.6
336.6
367.0
336.6
367.0
367.0
336.6
336.6
367.0
367.0
336.6
336.6
367.0
367.0
336.6
336.6
367.0
185.0
336.6
336.6
367.0
41.3
55.0
38.0
31.8
41.3
55.0
38.0
31.8
41.3
55.0
38.0
31.8
41.3
55.0
35.0
31.8
41.3
55.0
RGZ
ZVW
PM
PN
RGZ
ZVW
PM
PN
RGZ
ZVW
PM
PN
RGZ
ZVW
PM
1000
1000
1000
PN
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430FR5994IRGZR
MSP430FR5994IRGZT
MSP430FR5994IZVWR
VQFN
VQFN
RGZ
RGZ
ZVW
48
48
87
2500
250
367.0
210.0
336.6
367.0
185.0
336.6
38.0
35.0
31.8
NFBGA
1000
Pack Materials-Page 4
PACKAGE OUTLINE
PM0064A
LQFP - 1.6 mm max height
SCALE 1.400
PLASTIC QUAD FLATPACK
10.2
9.8
B
NOTE 3
64
49
PIN 1 ID
1
48
10.2
9.8
12.2
TYP
11.8
NOTE 3
33
16
32
17
A
0.27
0.17
64X
60X 0.5
4X 7.5
0.08
C A B
C
(0.13) TYP
SEATING PLANE
0.08
SEE DETAIL A
0.25
GAGE PLANE
(1.4)
1.6 MAX
0.05 MIN
0.75
0.45
0 -7
DETAIL
SCALE: 14
A
DETAIL A
TYPICAL
4215162/A 03/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MS-026.
www.ti.com
EXAMPLE BOARD LAYOUT
PM0064A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
49
64
64X (1.5)
1
48
64X (0.3)
SYMM
(11.4)
60X (0.5)
(R0.05) TYP
33
16
17
32
(11.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
0.05 MAX
ALL AROUND
EXPOSED METAL
METAL
0.05 MIN
ALL AROUND
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4215162/A 03/2017
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).
www.ti.com
EXAMPLE STENCIL DESIGN
PM0064A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
64
49
64X (1.5)
1
48
64X (0.3)
SYMM
(11.4)
60X (0.5)
(R0.05) TYP
16
33
17
32
(11.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:8X
4215162/A 03/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
A
7.1
6.9
B
(0.1) TYP
7.1
6.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
PIN 1 INDEX AREA
(0.45) TYP
CHAMFERED LEAD
CORNER LEAD OPTION
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 5.5
5.15±0.1
(0.2) TYP
13
24
44X 0.5
12
25
SEE SIDE WALL
DETAIL
SYMM
2X
5.5
1
36
0.30
0.18
PIN1 ID
(OPTIONAL)
48X
48
37
SYMM
0.1
C A B
C
0.5
0.3
48X
0.05
SEE LEAD OPTION
4219044/D 02/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
5.15)
SYMM
(
48X (0.6)
37
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(1.26)
2X
(1.065)
(R0.05)
TYP
25
12
21X (Ø0.2) VIA
TYP
24
13
2X (1.065)
2X (1.26)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219044/D 02/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
SYMM
(
1.06)
37
48X (0.6)
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(0.63)
2X
(1.26)
(R0.05)
TYP
25
12
24
13
2X
(1.26)
2X (0.63)
2X (5.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 15X
4219044/D 02/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
PN0080A
LQFP - 1.6 mm max height
SCALE 1.250
PLASTIC QUAD FLATPACK
12.2
11.8
B
PIN 1 ID
A
80
61
1
60
12.2
11.8
14.2
TYP
13.8
20
41
40
21
76X 0.5
0.27
80X
0.17
4X 9.5
0.08
C A B
1.6 MAX
C
(0.13) TYP
SEATING PLANE
0.08
SEE DETAIL A
0.25
GAGE PLANE
(1.4)
0.05 MIN
0.75
0.45
0 -7
DETAIL
SCALE: 14
A
DETAIL A
TYPICAL
4215166/A 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MS-026.
www.ti.com
EXAMPLE BOARD LAYOUT
PN0080A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
80
61
80X (1.5)
1
60
80X (0.3)
SYMM
(13.4)
76X (0.5)
(R0.05) TYP
20
41
21
40
(13.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
0.05 MAX
ALL AROUND
EXPOSED METAL
METAL
0.05 MIN
ALL AROUND
EXPOSED METAL
SOLDER MASK
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4215166/A 08/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
6. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).
www.ti.com
EXAMPLE STENCIL DESIGN
PN0080A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
80
61
80X (1.5)
1
60
80X (0.3)
SYMM
(13.4)
76X (0.5)
(R0.05) TYP
20
41
21
40
(13.4)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:6X
4215166/A 08/2022
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明