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MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

用于水计量应用的 MSP430FR604x(1)、MSP430FR603x(1)、超声波

感应 MSP430™ 微控制器

1 器件概述

1.1 特性

1

• 具有超低功耗的一流超声波水流量测量

– 差分飞行时间 (dTOF) 精度小于 25ps

– 高精度时间测量分辨率小于 5ps

– 能够检测低流速（<1 升/小时）

• 经优化的超低功耗模式

– 工作模式：大约 120µA/MHz

– 待机模式下的实时时钟 (RTC) (LPM3.5)：450nA

(1)

– 关断电流 (LPM4.5)：30nA

• 铁电随机存取存储器 (FRAM)

– 高达 256KB 的非易失性存储器

– 超低功耗写入

– 在每秒测量一次的频率下总体电流消耗大约为

3µA

• 符合并超出 ISO 4064、OIML R49 和 EN 1434 精

度标准

• 能够直接与标准超声波传感器（高达 2.5MHz）连接

• 集成模拟前端 – 超声波感应解决方案 (USS)

– 125ns 每个字的快速写入（4ms 内写入 64KB）

– 统一标准存储器 = 单个空间内的程序 + 数据 + 存

储

– 10¹⁵写入周期持久性

– 抗辐射和非磁性

– 可在不同频率下生成脉冲的可编程脉冲生成

(PPG)

– 具有低阻抗 (4Ω) 输出驱动器的集成物理接口

(PHY)，可控制输入和输出通道

• 智能数字外设

– 具有高达 8Msps 输出数据速率的高性能高速 12

位 Σ-Δ ADC (SDHS)

– 具有 –6.5dB 至 30.8dB 增益的可编程增益放大器

– 32 位硬件乘法器 (MPY)

– 6 通道内部直接存储器访问 (DMA)

– 具备日历和报警功能的 RTC

– 六个 16 位定时器，每个定时器具有多达七个捕

捉/比较寄存器

(PGA)

– 输出范围为 68MHz 至 80MHz 的高性能锁相环

(PLL)

– 32 位和 16 位循环冗余校验 (CRC)

• 高性能模拟

• 计量测试接口 (MTIF)

– 脉冲发生器和脉冲计数器

– 高达 1016 次脉冲/秒 (p/s) 的脉冲率

– 计数容量高达 65535（16 位）

– 在 LPM3.5 下以 200nA（典型值）运行

• 低能耗加速器 (LEA)

– 16 通道模拟比较器

– 12 位 SAR ADC，具有窗口比较器、内部基准和

采样保持功能以及多达 16 条外部输入通道

– 具有高达 264 段对比度控制的集成 LCD 驱动器

• 多功能输入/输出端口

– 独立于 CPU 运行

– 与 CPU 共享 4KB RAM

– 可每位、每字节和每字访问（成对访问）

– 所有端口上，从 LPM 中的边沿可选唤醒

– 所有端口上可编程上拉和下拉

– 256 点高效复变 FFT：

比 Arm^®Cortex^®-M0+ 内核快多达 40 倍

• 代码安全性和加密

• 嵌入式微控制器

– 128 位或 256 位高级加密标准 (AES) 安全加密和

解密协处理器

– 高达 16MHz 时钟频率的 16 位 RISC 架构

– 3.6V 至 1.8V 的宽电源电压范围（最低电源电压

受限于 SVS 电平，请参阅 SVS 规格）

– 针对随机数生成算法的随机数种子

– IP 封装防止对存储器进行外部访问

– FRAM 可提供固有安全性优势

(1) RTC 由 3.7pF 晶振生成。

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLASEB7

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

• 增强型串行通信

– 高频晶振 (HFXT)

– 多达四个 eUSCI_A 串行通信端口

• 开发工具和软件（另请参阅工具和软件）

– 超声波感应设计中心图形用户界面

– 超声波感应软件库

– 支持自动波特率侦测的通用异步收发器

(UART)

– IrDA 编码和解码

– EVM430-FR6047 水表评估模块板

– 多达两个 eUSCI_B 串行通信端口

– 支持多从设备寻址的 I²C

– 用于 100 引脚封装的 MSP-TS430PZ100E 目标

插座板

– 硬件通用异步收发器 (UART) 或 I²C 自举程序

– 采用 EnergyTrace++ 技术的免费专业开发环境

– 用于 MSP430™ 微控制器的 MSP430Ware™

• 器件比较汇总了可用的器件型号和封装选项

(BSL)

• 灵活时钟系统

– 具有 10 个可选厂家调整频率的定频数控振荡器

• 要获得完整的模块说明，请参见

《MSP430FR58xx、MSP430FR59xx 和

MSP430FR6xx 系列用户指南》

(DCO)

– 低功率低频内部时钟源 (VLO)

– 32kHz 晶振 (LFXT)

1.2 应用

•

超声波智能水表

•

液位感应

漏水检测

超声波智能热量计

1.3 说明

德州仪器 (TI) MSP430FR604x 和 MSP430FR603x 系列超声波感应和测量 SoC 是针对水表和热量计进行了

优化的强大且高度集成的微控制器 (MCU)。MSP430FR604x MCU 具有集成的超声波感应解决方案 (USS)

模块，该模块可在多种流速条件下提供高精度。USS 模块高度集成，需要的外部组件极少，因而有助于实现

超低功耗计量并降低系统成本。MSP430FR604x 和 MSP430FR603x MCU 采用集成式低功耗加速器

(LEA)，可实现基于高速 ADC 的信号采集以及后续优化数字信号处理，为电池供电型计量应用提供了一款理

想的超低功耗、高精度计量解决方案。

USS 模块包括可编程脉冲发生器 (PPG) 和具有低阻抗输出驱动器的物理接口 (PHY)，以实现最佳传感器激

励和准确的阻抗匹配，从而在零流量漂移 (ZFD) 方面达到最佳效果。该模块还包含可编程增益放大器 (PGA)

和高速 12 位 8Msps Σ-Δ ADC (SDHS)，便于通过行业标准超声波传感器实现精确的信号采集。

此外，MSP430FR604x 和 MSP430FR603x MCU 还集成了其他外设，可提高系统在计量方面的集成度。这

些器件还具有计量测试接口 (MTIF) 模块，能够通过脉冲生成来指示仪表测量的流量。MSP430FR604x 和

MSP430FR603x MCU 还具有片上 8 通道多路复用器 LCD 驱动器、RTC、12 位 SAR ADC、模拟比较器、

高级加密加速器 (AES256) 和循环冗余校验 (CRC) 模块。

MSP430FR604x 和 MSP430FR603x MCU 由一款广泛的硬件和软件生态系统提供支持，随附参考设计和代

码示例，以便用户快速开展设计。开发套件包括 MSP-TS430PZ100E 100 引脚目标开发板和 EVM430-

FR6047 超声波水流量计 EVM。TI 还提供免费软件，包括超声波感应设计中心、超声波感应软件库和

MSP430Ware™ 软件。

TI 的 MSP430 超低功耗 (ULP) FRAM 微控制器平台将独特的嵌入式 FRAM 和全面的超低功耗系统架构相

结合，从而使系统设计人员能够在降低能耗的同时提升性能。FRAM 技术将 RAM 的低能耗快速写入、灵活

性和耐用性与闪存的非易失性相结合。

2

器件概述

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

器件信息⁽¹⁾⁽²⁾

封装

器件型号

封装尺寸⁽³⁾

MSP430FR6047IPZ

MSP430FR60471IPZ

MSP430FR6045IPZ

MSP430FR6037IPZ

MSP430FR60371IPZ

MSP430FR6035IPZ

LQFP (100)

14mm x 14mm

(1) 要获得所有可用器件的最新部件、封装和订购信息，请参见封装选项附录（节 9）或浏览 TI 网站

www.ti.com。

(2) 有关提供的所有器件变型的对比，请参见节 3。

(3) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参见机械数据（节 9）。

1.4 功能框图

图 1-1 和图 1-2 显示了器件的功能框图。

P1.x, P2.x P3.x, P4.x P5.x, P6.x P7.x, P8.x

P9.x

1x8

PJ.x

2x8

1x8

LFXIN,

HFXIN

LFXOUT,

HFXOUT

ADC12_B

I/O Ports

P1, P2

2x8 I/Os

I/O Ports

P3, P4

2x8 I/Os

I/O Ports

P5, P6

2x8 I/Os

I/O Ports

P7, P8

2x8 I/Os

I/O Ports

P9

1x8 I/Os

I/O Port

PJ

1x8 I/Os

REF_A

MCLK

ACLK

Comp_E

(up to 16

standard

inputs,

up to 8

differential

inputs)

Clock

System

(up to 16

inputs)

Voltage

Reference

SMCLK

PA PC

1x16 I/Os 1x16 I/Os 1x16 I/Os

PB

PD

1x16 I/Os

PD

1x8 I/Os

DMA

Controller

Channel

6

MAB

MDB

Bus

Control

Logic

CPUXV2

Including

16 Registers

MPU

IP Encap

CRC16

LCD_C

Power

Manage-

ment

RAM

AES256

TA2

TA3

CRC-16-

CCITT

(up to

264 Seg:

static,

4KB + 4KB

Security

Encryption,

Decryption

(128, 256)

Timer_A Timer_A

2 CC 2 CC

Registers Registers

Watchdog

Timer

FRCTL_A

256KB

128KB

MPY32

CRC32

LDO

SVS

Brownout

2 to 8 mux)

EEM

(S: 3+1)

(int)

Tiny RAM

22B

CRC-32-

ISO-3309

MDB

MAB

JTAG

Interface

Spy-Bi-Wire

TB0

TA0

TA1

TA4

eUSCI_A0

eUSCI_B0

USS

Subsystem

LEA

Subsystem

eUSCI_A1

eUSCI_A2

eUSCI_A3

(UART,

IrDA,

SPI)

eUSCI_B1

(I²C,

SPI)

Timer_B

7 CC

Registers

(int, ext)

Timer_A

3 CC

Registers

(int, ext)

Timer_A

3 CC

Registers

(int, ext)

Timer_A

2 CC

Registers

(int, ext)

RTC_C

MTIF

LPM3.5 Domain

MTIF_PIN_EN

MTIF_OUT_IN

CHx_IN, CHx_OUT USSXTIN, USSXTOUT, USSXT_BOUT

NOTE: 该器件具备 8KB RAM，其中 4KB RAM 与 LEA 子系统共享。

图 1-1. MSP430FR604x 功能框图

器件概述

3

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

P1.x, P2.x P3.x, P4.x P5.x, P6.x P7.x, P8.x

P9.x

1x8

PJ.x

1x8

2x8

LFXIN,

HFXIN

LFXOUT,

HFXOUT

ADC12_B

I/O Ports

P1, P2

2x8 I/Os

I/O Ports

P3, P4

2x8 I/Os

I/O Ports

P5, P6

2x8 I/Os

I/O Ports

P7, P8

2x8 I/Os

I/O Ports

P9

1x8 I/Os

I/O Port

PJ

1x8 I/Os

REF_A

MCLK

ACLK

Comp_E

(up to 16

standard

inputs,

up to 8

differential

inputs)

Clock

System

(up to 16

inputs)

Voltage

Reference

SMCLK

PA PC

1x16 I/Os 1x16 I/Os 1x16 I/Os

PB

PD

1x16 I/Os

PD

1x8 I/Os

DMA

Controller

Channel

6

MAB

MDB

Bus

Control

Logic

CPUXV2

incl. 16

Registers

MPU

IP Encap

CRC16

LCD_C

RAM

AES256

TA2

TA3

Power

Mgmt

CRC-16-

CCITT

(up to

264 Seg:

static,

FRCTL_A

256KB

128KB

4KB + 4KB

Security

Encryption,

Decryption

(128, 256)

Timer_A Timer_A

2 CC 2 CC

Registers Registers

Watchdog

MPY32

LDO

SVS

Brownout

CRC32

2 to 8 mux)

EEM

(S: 3+1)

(int)

Tiny RAM

22B

CRC-32-

ISO-3309

MDB

MAB

JTAG

Interface

Spy-Bi-Wire

TB0

TA0

TA1

TA4

eUSCI_A0

eUSCI_B0

LEA

eUSCI_A1

eUSCI_A2

eUSCI_A3

(UART,

IrDA,

SPI)

eUSCI_B1

(I2C,

SPI)

Sub

System

Timer_B

7 CC

Registers

(int, ext)

Timer_A

3 CC

Registers

(int, ext)

Timer_A

3 CC

Registers

(int, ext)

Timer_A

2 CC

Registers

(int, ext)

RTC_C

MTIF

LPM3.5 Domain

MTIF_PIN_EN

MTIF_OUT_IN

NOTE: 该器件具备 8KB RAM，其中 4KB RAM 与 LEA 子系统共享。

图 1-2. MSP430FR603x 功能框图

4

器件概述

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

内容

1

器件概述.................................................... 1

5.13 Timing and Switching Characteristics ............... 39

Detailed Description ................................... 72

6.1 Overview ............................................ 72

6.2 CPU ................................................. 72

1.1 特性 ................................................... 1

1.2 应用 ................................................... 2

1.3 说明 ................................................... 2

1.4 功能框图 .............................................. 3

修订历史记录............................................... 6

Device Comparison ..................................... 7

3.1 Related Products ..................................... 8

Terminal Configuration and Functions.............. 9

4.1 Pin Diagram .......................................... 9

4.2 Pin Attributes ........................................ 11

4.3 Signal Descriptions.................................. 19

4.4 Pin Multiplexing ..................................... 28

4.5 Buffer Type.......................................... 28

4.6 Connection of Unused Pins ......................... 28

Specifications ........................................... 29

5.1 Absolute Maximum Ratings ........................ 29

5.2 ESD Ratings ........................................ 29

5.3 Recommended Operating Conditions............... 30

6

6.3

Ultrasonic Sensing Solution (USS) Module ......... 72

6.4

Low-Energy Accelerator (LEA) for Signal

2

3

Processing .......................................... 73

6.5 Operating Modes .................................... 74

6.6 Interrupt Vector Table and Signatures .............. 77

6.7 Bootloader (BSL).................................... 80

6.8 JTAG Operation ..................................... 81

6.9 FRAM Controller A (FRCTL_A) ..................... 82

6.10 RAM ................................................ 82

4

6.11 Tiny RAM............................................ 82

6.12 Memory Protection Unit (MPU) Including IP

Encapsulation ....................................... 82

5

6.13 Peripherals .......................................... 83

6.14 Input/Output Diagrams .............................. 95

6.15 Device Descriptors (TLV) .......................... 140

6.16 Memory Map ....................................... 143

6.17 Identification........................................ 166

Applications, Implementation, and Layout ...... 167

5.4

5.5

5.6

5.7

5.8

5.9

Active Mode Supply Current Into V_CCExcluding

External Current .................................... 31

Typical Characteristics, Active Mode Supply

7

8

Currents ............................................. 32

Low-Power Mode (LPM0, LPM1) Supply Currents

Into V_CCExcluding External Current ................ 32

Low-Power Mode (LPM2, LPM3, LPM4) Supply

Currents (Into V_CC) Excluding External Current .... 33

Low-Power Mode With LCD Supply Currents (Into

V_CC) Excluding External Current.................... 35

Low-Power Mode (LPMx.5) Supply Currents (Into

V_CC) Excluding External Current.................... 36

7.1

Device Connection and Layout Fundamentals .... 167

Peripheral- and Interface-Specific Design

7.2

Information ......................................... 173

器件和文档支持......................................... 176

8.1 入门和下一步....................................... 176

8.2 器件命名规则....................................... 176

8.3 工具和软件 ......................................... 177

8.4 文档支持 ........................................... 178

8.5 相关链接 ........................................... 179

8.6 商标 ................................................ 179

8.7 静电放电警告....................................... 179

8.8 Export Control Notice .............................. 180

8.9 Glossary............................................ 180

机械、封装和可订购信息 .............................. 180

5.10 Typical Characteristics, Low-Power Mode Supply

Currents ............................................. 37

5.11 Typical Characteristics, Current Consumption per

Module .............................................. 38

5.12 Thermal Resistance Characteristics for 100-Pin

LQFP (PZ) Package ................................ 38

9

内容

5

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

2 修订历史记录

Changes from December 16, 2017 to September 25, 2018

Page

•

Updated 节 3.1, Related Products ................................................................................................. 8

Added note (1) to 表 5-2, SVS..................................................................................................... 39

Changed capacitor value from 4.7 µF to 470 nF in 图 7-10, ADC12_B Grounding and Noise Considerations....... 173

Changed capacitor value from 4.7 µF to 470 nF in the last paragraph of 节 7.2.1.2, Design Requirements ......... 174

更新了节 8.2器件命名规则中的文本和图....................................................................................... 176

6

修订历史记录

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

TI 16-bit and 32-bit microcontrollers High-performance, low-power solutions to enable the autonomous

future

Products for MSP430 ultra-low-power sensing and measurement microcontrollers One platform.

One ecosystem. Endless possibilities.

Products for MSP430 ultrasonic and performance sensing microcontrollers Ultra-low-power single-

chip MCUs with integrated sensing peripherals

Companion products for MSP430FR6047 Review products that are frequently purchased or used with

this product.

Reference designs for MSP430FR6047 The TI Designs Reference Design Library is a robust reference

design library that spans analog, embedded processor, and connectivity. Created by TI

experts to help you jump start your system design, all TI Designs include schematic or block

diagrams, BOMs, and design files to speed your time to market. Search and download

designs at ti.com/tidesigns.

8

Device Comparison

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

4 Terminal Configuration and Functions

4.1 Pin Diagram

图 4-1 and 图 4-2 show the pinouts of the 100-pin PZ packages.

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

P2.2/COUT/UCA0CLK/A14/C14

P2.3/TA0.0/UCA0STE/A15/C15

P1.0/UCA1CLK/TA1.0/A0/C0/VREF-/VeREF-

P1.1/UCA1STE/TA4.0/A1/C1/VREF+/VeREF+

AVSS2

1

75 DVSS3

2

74 R33/LCDCAP

3

73 P6.3/R23

4

72 P6.2/R13/LCDREF

5

71 P6.1/R03

PJ.4/LFXIN

6

70 P7.3/UCA2STE/TB0.1/COM7/LCDS33

69 P7.2/UCA2CLK/TB0.0/COM6/LCDS34

68 P7.1/UCA2SOMI/UCA2RXD/SMCLK/COM5/LCDS35

67 P7.0/UCA2SIMO/UCA2TXD/ACLK/COM4/LCDS36

66 P6.7/COM3/LCDS37

PJ.5/LFXOUT

7

AVSS3

8

PJ.6/HFXIN

9

PJ.7/HFXOUT

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

AVSS4

65 P6.6/COM2/LCDS38

P1.4/TB0.4/UCB0STE/A2/C2

P1.5/TB0.5/UCB0CLK/A3/C3

P1.6/UCB0SIMO/UCB0SDA/A4/C4

P1.7/USSTRG/UCB0SOMI/UCB0SCL/A5/C5

P2.0/UCA0SIMO/UCA0TXD/A6/C6

P2.1/UCA0SOMI/UCA0RXD/A7/C7

P1.2/UCA1SIMO/UCA1TXD/A8/C8

P1.3/UCA1SOMI/UCA1RXD/A9/C9

TEST/SBWTCK

64 P6.5/COM1

MSP430FR604xPZ

63 P6.4/COM0

62 P6.0/COUT/LCDS0

61 P5.7/UCB1STE/LCDS1

60 P5.6/UCB1SOMI/UCB1SCL/LCDS2

59 P5.5/TA0CLK/UCB1SIMO/UCB1SDA/LCDS3

58 P5.4/UCB1CLK/LCDS4

57 P5.3/UCA2STE/LCDS5

56 P5.2/UCA2CLK/LCDS6

55 P5.1/UCA2SOMI/UCA2RXD/LCDS7

54 P5.0/UCA2SIMO/UCA2TXD/LCDS8

53 P4.7/DMAE0/LCDS9

RST /NMI/SBWTDIO

PJ.0/TDO/ACLK/SRSCG1/DMAE0/C10

PJ.1/TDI/TCLK/SMCLK/SRSCG0/TA4CLK/C11

PJ.2/TMS/MCLK/SROSCOFF/TB0OUTH/C12

PJ.3/TCK/RTCCLK/SRCPUOFF/TB0.6/C13

52 DVCC2

51 DVSS2

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

On devices with UART BSL: P2.0 is BSLTX, P2.1 is BSLRX

On devices with I²C BSL: P1.6 is BSLSDA, P1.7 is BSLSCL

图 4-1. MSP430FR604x 100-Pin PZ Package (Top View)

Terminal Configuration and Functions

9

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

P2.2/COUT/UCA0CLK/A14/C14

P2.3/TA0.0/UCA0STE/A15/C15

P1.0/UCA1CLK/TA1.0/A0/C0/VREF-/VeREF-

P1.1/UCA1STE/TA4.0/A1/C1/VREF+/VeREF+

AVSS2

1

75 DVSS3

2

74 R33/LCDCAP

73 P6.3/R23

3

4

72 P6.2/R13/LCDREF

71 P6.1/R03

5

PJ.4/LFXIN

6

70 P7.3/UCA2STE/TB0.1/COM7/LCDS33

69 P7.2/UCA2CLK/TB0.0/COM6/LCDS34

68 P7.1/UCA2SOMI/UCA2RXD/SMCLK/COM5/LCDS35

67 P7.0/UCA2SIMO/UCA2TXD/ACLK/COM4/LCDS36

66 P6.7/COM3/LCDS37

PJ.5/LFXOUT

7

AVSS3

8

PJ.6/HFXIN

9

PJ.7/HFXOUT

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

AVSS4

65 P6.6/COM2/LCDS38

P1.4/TB0.4/UCB0STE/A2/C2

P1.5/TB0.5/UCB0CLK/A3/C3

P1.6/UCB0SIMO/UCB0SDA/A4/C4

P1.7/UCB0SOMI/UCB0SCL/A5/C5

P2.0/UCA0SIMO/UCA0TXD/A6/C6

P2.1/UCA0SOMI/UCA0RXD/A7/C7

P1.2/UCA1SIMO/UCA1TXD/A8/C8

P1.3/UCA1SOMI/UCA1RXD/A9/C9

TEST/SBWTCK

64 P6.5/COM1

MSP430FR603xPZ

63 P6.4/COM0

62 P6.0/COUT/LCDS0

61 P5.7/UCB1STE/LCDS1

60 P5.6/UCB1SOMI/UCB1SCL/LCDS2

59 P5.5/TA0CLK/UCB1SIMO/UCB1SDA/LCDS3

58 P5.4/UCB1CLK/LCDS4

57 P5.3/UCA2STE/LCDS5

56 P5.2/UCA2CLK/LCDS6

RST /NMI/SBWTDIO

55 P5.1/UCA2SOMI/UCA2RXD/LCDS7

54 P5.0/UCA2SIMO/UCA2TXD/LCDS8

53 P4.7/DMAE0/LCDS9

PJ.0/TDO/ACLK/SRSCG1/DMAE0/C10

PJ.1/TDI/TCLK/SMCLK/SRSCG0/TA4CLK/C11

PJ.2/TMS/MCLK/SROSCOFF/TB0OUTH/C12

PJ.3/TCK/RTCCLK/SRCPUOFF/TB0.6/C13

52 DVCC2

51 DVSS2

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

DNC = Do Not Connect

On devices with UART BSL: P2.0 is BSLTX, P2.1 is BSLRX

On devices with I²C BSL: P1.6 is BSLSDA, P1.7 is BSLSCL

图 4-2. MSP430FR603x 100-Pin PZ Package (Top View)

10

Terminal Configuration and Functions

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

4.2 Pin Attributes

表 4-1 lists the attributes of each pin.

表 4-1. Pin Attributes

RESET STATE

AFTER BOR⁽⁶⁾

PIN NUMBER

SIGNAL NAME^{(1) (2)}

P2.2

SIGNAL TYPE⁽³⁾

BUFFER TYPE⁽⁴⁾

POWER SOURCE⁽⁵⁾

I/O

O

I/O

I

LVCMOS

Analog

DVCC

–

OFF

COUT

UCA0CLK

A14

–

1

–

C14

I

Analog

–

P2.3

I/O

I

LVCMOS

Analog

OFF

–

TA0.0

UCA0STE

A15

2

3

–

C15

I

Analog

–

P1.0

I/O

I

LVCMOS

Analog

OFF

–

UCA1CLK

TA1.0

A0

–

C0

I

Analog

–

VREF-

VeREF-

P1.1

O

I

Analog

–

Analog

–

I/O

I

LVCMOS

Analog

OFF

–

UCA1STE

TA4.0

A1

–

4

–

C1

I

Analog

–

VREF+

VeREF+

AVSS2

PJ.4

O

I

Analog

–

Analog

–

5

6

P

Power

N/A

OFF

–

I/O

I

LVCMOS

Analog

DVCC

–

LFXIN

PJ.5

I/O

O

P

LVCMOS

Analog

OFF

–

7

8

9

LFXOUT

AVSS3

PJ.6

Power

N/A

–

I/O

I

LVCMOS

Analog

DVCC

–

HFXIN

PJ.7

–

I/O

O

P

LVCMOS

Analog

OFF

–

10

11

HFXOUT

AVSS4

Power

N/A

(1) The signal that is listed first for each pin is the reset default pin name.

(2) To determine the pin mux encodings for each pin, see 节 6.14.

(3) Signal Types: I = Input, O = Output, I/O = Input or Output.

(4) Buffer Types: LVCMOS, Analog, or Power (see 表 4-3 for details)

(5) The power source shown in this table is the I/O power source, which may differ from the module power source.

(6) Reset States:

OFF = High impedance with Schmitt-trigger input and pullup or pulldown (if available) disabled

PU = Pullup is enabled

PD = Pulldown is enabled

N/A = Not applicable

Terminal Configuration and Functions

11

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 4-1. Pin Attributes (continued)

RESET STATE

PIN NUMBER

SIGNAL NAME^{(1) (2)}

P1.4

SIGNAL TYPE⁽³⁾

BUFFER TYPE⁽⁴⁾

POWER SOURCE⁽⁵⁾

AFTER BOR⁽⁶⁾

I/O

I

LVCMOS

Analog

DVCC

OFF

TB0.4

UCB0STE

A2

–

12

–

C2

I

Analog

–

P1.5

I/O

I

LVCMOS

Analog

OFF

–

TB0.5

UCB0CLK

A3

13

14

–

C3

I

Analog

–

P1.6

I/O

I

LVCMOS

Analog

OFF

–

UCB0SIMO

UCB0SDA

A4

–

C4

I

Analog

–

P1.7

I/O

I

LVCMOS

Analog

OFF

–

USSTRG

UCB0SOMI

UCB0SCL

A5

I/O

I

–

15

–

C5

I

Analog

–

P2.0

I/O

O

I/O

I

LVCMOS

Analog

OFF

–

UCA0TXD

UCA0SIMO

A6

16

17

18

19

–

C6

I

Analog

–

P2.1

I/O

I

LVCMOS

Analog

OFF

–

UCA0RXD

UCA0SOMI

A7

I/O

I

–

C7

I

Analog

–

P1.2

I/O

O

I/O

I

LVCMOS

Analog

OFF

–

UCA1TXD

UCA1SIMO

A8

–

C8

I

Analog

–

P1.3

I/O

I

LVCMOS

Analog

OFF

–

UCA1RXD

UCA1SOMI

A9

I/O

I

–

C9

I

Analog

–

TEST

I

LVCMOS

PD

–

20

21

SBWTCK

RST

I

I/O

I

PU

–

NMI

SBWTDIO

I/O

–

12

Terminal Configuration and Functions

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

PIN NUMBER

表 4-1. Pin Attributes (continued)

RESET STATE

AFTER BOR⁽⁶⁾

SIGNAL NAME^{(1) (2)}

PJ.0

SIGNAL TYPE⁽³⁾

BUFFER TYPE⁽⁴⁾

POWER SOURCE⁽⁵⁾

I/O

O

I

LVCMOS

Analog

DVCC

–

OFF

TDO

–

ACLK

SRSCG1

DMAE0

C10

–

22

–

I

–

PJ.1

I/O

I

LVCMOS

Analog

OFF

TDI

–

TCLK

SMCLK

SRSCG0

TA4CLK

C11

I

–

23

O

I

–

I

–

PJ.2

I/O

I

LVCMOS

Analog

OFF

–

TMS

MCLK

SROSCOFF

TB0OUTH

C12

O

I

–

24

25

–

I

–

PJ.3

I/O

I

LVCMOS

Analog

OFF

–

TCK

RTCCLK

SRCPUOFF

TB0.6

C13

O

I/O

I

–

26

27

DVSS1

DVCC1

P2.4

P

Power

N/A

OFF

–

P

Power

–

I/O

I

LVCMOS

Analog

DVCC

TA0CLK

TB0CLK

TA1CLK

S32

28

I

–

I

–

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

–

P2.5

LVCMOS

Analog

OFF

–

29

30

31

32

33

TA4.0

S31

–

P2.6

LVCMOS

Analog

OFF

–

TA4.1

S30

–

P3.0

LVCMOS

Analog

OFF

–

TB0.0

S29

–

P3.1

LVCMOS

Analog

OFF

–

TB0.1

S28

–

P3.2

LVCMOS

Analog

OFF

–

TB0.2

S27

–

Terminal Configuration and Functions

13

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 4-1. Pin Attributes (continued)

RESET STATE

PIN NUMBER

SIGNAL NAME^{(1) (2)}

P3.3

SIGNAL TYPE⁽³⁾

BUFFER TYPE⁽⁴⁾

POWER SOURCE⁽⁵⁾

AFTER BOR⁽⁶⁾

I/O

O

LVCMOS

Analog

DVCC

OFF

34

TB0.3

S26

–

P3.4

I/O

I

LVCMOS

Analog

OFF

35

36

37

38

39

40

41

42

43

44

45

46

TB0OUTH

S25

–

O

–

P3.5

I/O

O

LVCMOS

Analog

OFF

TB0.4

S24

–

P3.6

I/O

O

LVCMOS

Analog

OFF

TB0.5

S23

–

P3.7

I/O

O

LVCMOS

Analog

OFF

TB0.6

S22

–

OFF

–

P2.7

I/O

O

LVCMOS

Analog

TA0.0

S21

–

P9.0

I/O

O

LVCMOS

Analog

OFF

–

TA1.0

S20

–

P9.1

I/O

O

LVCMOS

Analog

OFF

–

SMCLK

S19

O

–

P9.2

I/O

O

LVCMOS

Analog

OFF

–

MCLK

S18

O

–

P9.3

I/O

O

LVCMOS

Analog

OFF

–

ACLK

S17

O

–

P4.0

I/O

O

LVCMOS

Analog

OFF

–

RTCCLK

S16

O

–

P4.1

I/O

O

LVCMOS

Analog

OFF

–

UCA0CLK

S15

–

P4.2

I/O

O

LVCMOS

Analog

OFF

–

UCA0STE

S14

–

P4.3

I/O

O

LVCMOS

Analog

OFF

–

UCA0TXD

UCA0SIMO

S13

47

48

I/O

O

–

P4.4

I/O

I

LVCMOS

Analog

OFF

–

UCA0RXD

UCA0SOMI

S12

I/O

O

–

14

Terminal Configuration and Functions

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 4-1. Pin Attributes (continued)

RESET STATE

AFTER BOR⁽⁶⁾

PIN NUMBER

SIGNAL NAME^{(1) (2)}

P4.5

SIGNAL TYPE⁽³⁾

BUFFER TYPE⁽⁴⁾

POWER SOURCE⁽⁵⁾

I/O

I

LVCMOS

Analog

DVCC

–

OFF

TA0CLK

TA1CLK

S11

–

49

I

O

–

P4.6

I/O

I

LVCMOS

Analog

OFF

–

TB0CLK

TA4CLK

S10

50

I

–

O

–

51

52

DVSS2

DVCC2

P4.7

P

Power

N/A

OFF

–

P

Power

–

I/O

I

LVCMOS

Analog

DVCC

53

DMAE0

S9

O

–

P5.0

I/O

O

LVCMOS

Analog

OFF

–

UCA2TXD

UCA2SIMO

S8

54

I/O

O

–

P5.1

I/O

I

LVCMOS

Analog

OFF

–

UCA2RXD

UCA2SOMI

S7

55

I/O

O

–

P5.2

I/O

O

LVCMOS

Analog

OFF

–

56

57

58

UCA2CLK

S6

–

P5.3

I/O

O

LVCMOS

Analog

OFF

–

UCA2STE

S5

–

P5.4

I/O

O

LVCMOS

Analog

OFF

–

UCB1CLK

S4

–

P5.5

I/O

I

LVCMOS

Analog

OFF

–

TA0CLK

UCB1SIMO

UCB1SDA

S3

59

I/O

O

–

P5.6

I/O

O

LVCMOS

Analog

OFF

–

UCB1SOMI

UCB1SCL

S2

60

61

–

P5.7

I/O

O

LVCMOS

Analog

OFF

–

UCB1STE

S1

–

P6.0

I/O

I

LVCMOS

Analog

OFF

–

62

63

COUT

S0

O

–

P6.4

I/O

O

LVCMOS

Analog

OFF

–

COM0

Terminal Configuration and Functions

15

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 4-1. Pin Attributes (continued)

RESET STATE

PIN NUMBER

SIGNAL NAME^{(1) (2)}

P6.5

SIGNAL TYPE⁽³⁾

BUFFER TYPE⁽⁴⁾

POWER SOURCE⁽⁵⁾

AFTER BOR⁽⁶⁾

I/O

O

LVCMOS

Analog

DVCC

-

OFF

64

COM1

P6.6

–

I/O

O

LVCMOS

Analog

OFF

65

66

COM2

S38

–

O

Analog

–

P6.7

I/O

O

LVCMOS

Analog

OFF

COM3

S37

–

O

Analog

–

P7.0

I/O

O

LVCMOS

Analog

OFF

UCA2TXD

UCA2SIMO

ACLK

–

I/O

O

–

67

68

–

COM4

S36

O

–

O

Analog

–

P7.1

I/O

I

LVCMOS

Analog

OFF

UCA2RXD

UCA2SOMI

SMCLK

COM5

S35

–

I/O

O

–

O

–

O

Analog

–

P7.2

I/O

O

LVCMOS

Analog

OFF

–

UCA2CLK

TB0.0

COM6

S34

69

70

–

O

Analog

–

P7.3

I/O

O

LVCMOS

Analog

OFF

–

UCA2STE

TB0.1

COM7

S33

–

O

Analog

–

P6.1

I/O

I

LVCMOS

Analog

OFF

–

71

72

R03

P6.2

LVCMOS

Analog

OFF

–

R13

LCDREF

P6.3

Analog

–

I/O

P

LVCMOS

Analog

DVCC

–

OFF

–

73

74

R23

R33

Analog

-

LCDCAP

DVSS3

DVCC3

P7.4

Analog

–

75

76

Power

N/A

OFF

–

P

Power

–

I/O

I

LVCMOS

DVCC

77

78

TA0.1

MTIF_OUT_IN

P7.5

–

OFF

–

TA1.1

MTIF_PIN_EN

–

16

Terminal Configuration and Functions

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 4-1. Pin Attributes (continued)

RESET STATE

AFTER BOR⁽⁶⁾

PIN NUMBER

SIGNAL NAME^{(1) (2)}

P8.0

SIGNAL TYPE⁽³⁾

BUFFER TYPE⁽⁴⁾

POWER SOURCE⁽⁵⁾

I/O

I

LVCMOS

Analog

DVCC

PVCC

–

OFF

UCA3STE

TB0.2

–

79

DMAE0

P8.1

–

I/O

I

OFF

–

UCA3CLK

TB0.3

80

81

82

83

84

–

TB0OUTH

P8.2

–

I/O

O

OFF

–

UCA3RXD

UCA3SOMI

MCLK

I/O

O

–

P8.3

I/O

O

OFF

–

UCA3TXD

UCA3SIMO

RTCCLK

P7.6

I/O

O

–

I/O

I

OFF

–

TA4.1

DMAE0

COUT

–

O

–

P7.7

I/O

I

OFF

–

TA0.2

TB0OUTH

COUT

–

O

–

85

86

87

88

89

90

91

CH1_IN

CH1_OUT

PVSS

I

–

O

Analog

–

P

Power

N/A

–

PVCC

P

Power

–

PVSS

P

Power

–

CH0_OUT

CH0_IN

P8.4

O

Analog

PVCC

DVCC

I

Analog

–

I/O

I

LVCMOS

Analog

OFF

–

UCB1CLK

TA1.2

92

93

94

95

–

A10

–

P8.5

I/O

I

LVCMOS

Analog

OFF

–

UCB1SIMO

UCB1SDA

A11

–

P8.6

I/O

I

LVCMOS

Analog

OFF

–

UCB1SOMI

UCB1SCL

A12

–

P8.7

I/O

I

LVCMOS

Analog

OFF

–

UCB1STE

USSXT_BOUT

A13

–

Terminal Configuration and Functions

17

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 4-1. Pin Attributes (continued)

RESET STATE

PIN NUMBER

SIGNAL NAME^{(1) (2)}

AVSS5

USSXTIN⁽⁷⁾

USSXTOUT⁽⁷⁾

AVSS1

SIGNAL TYPE⁽³⁾

BUFFER TYPE⁽⁴⁾

POWER SOURCE⁽⁵⁾

AFTER BOR⁽⁶⁾

96

97

P

I

Power

Analog

Power

–

1.5V

–

N/A

–

98

O

P

–

99

N/A

100

AVCC1

–

(7) Do not connect USSXTIN and USSXTOUT pins to AVCC nor to DVCC. USSXTIN does not support bypass mode, so do not drive an

external clock on the USSXTIN pin.

18

Terminal Configuration and Functions

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4.3 Signal Descriptions

表 4-2 describes the signals.

表 4-2. Signal Descriptions

NO.

FUNCTION

SIGNAL NAME

A0

PIN TYPE⁽¹⁾

DESCRIPTION

PZ

3

I

ADC analog input A0

ADC analog input A1

ADC analog input A2

ADC analog input A3

ADC analog input A4

ADC analog input A5

ADC analog input A6

ADC analog input A7

ADC analog input A8

ADC analog input A9

ADC analog input A10

ADC analog input A11

ADC analog input A12

ADC analog input A13

ADC analog input A14

ADC analog input A15

A1

4

A2

12

13

14

15

16

17

18

19

92

93

94

95

1

I

A3

I

A4

I

A5

I

A6

I

A7

I

A8

I

A9

I

ADC

A10

A11

A12

A13

A14

A15

VREF+

VREF-

VeREF+

VeREF-

I

2

I

4

O

I

Output of positive reference voltage

3

Output of negative reference voltage

4

Input for an external positive reference voltage to the ADC

Input for an external negative reference voltage to the ADC

3

I

22, 43,

67

ACLK

O

ACLK output

HFXIN

9

10

6

I

Input for high-frequency crystal oscillator HFXT

Output for high-frequency crystal oscillator HFXT

Input for low-frequency crystal oscillator LFXT

Output of low-frequency crystal oscillator LFXT

HFXOUT

LFXIN

O

I

Clock

LFXOUT

7

O

24, 42,

81

MCLK

O

MCLK output

23, 41,

68

SMCLK

SMCLK output

(1) I = input, O = output, P = power

Terminal Configuration and Functions

19

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表 4-2. Signal Descriptions (continued)

NO.

FUNCTION

SIGNAL NAME

C0

PIN TYPE⁽¹⁾

DESCRIPTION

PZ

3

I

Comparator input C0

Comparator input C1

Comparator input C2

Comparator input C3

Comparator input C4

Comparator input C5

Comparator input C6

Comparator input C7

Comparator input C8

Comparator input C9

Comparator input C10

Comparator input C11

Comparator input C12

Comparator input C13

Comparator input C14

Comparator input C15

C1

4

C2

12

13

14

15

16

17

18

19

22

23

24

25

1

C3

C4

C5

C6

C7

C8

Comparator

C9

C10

C11

C12

C13

C14

C15

2

1, 83,

84

COUT

O

I

Comparator output

22, 79,

83

DMA

DMAE0

External DMA trigger

SBWTCK

SBWTDIO

SRCPUOFF

SROSCOFF

SRSCG0

SRSCG1

TCK

20

21

25

24

23

22

25

23

22

20

24

3

I

Spy-Bi-Wire input clock

I/O

O

Spy-Bi-Wire data input/output

Low-power debug: CPU Status register bit CPUOFF

Low-power debug: CPU Status register bit OSCOFF

Low-power debug: CPU Status register bit SCG0

Low-power debug: CPU Status register bit SCG1

Test clock

O

Debug

I

TCLK

I

Test clock input

TDI

I

Test data input

TDO

O

Test data output port

TEST

I

Test mode pin, selects digital I/O on JTAG pins

Test mode select

TMS

I

P1.0

I/O

General-purpose digital I/O with port interrupt and wakeup from LPMx.5

P1.1

4

P1.2

18

19

12

13

14

15

P1.3

GPIO Port 1

P1.4

P1.5

P1.6

P1.7

20

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FUNCTION

表 4-2. Signal Descriptions (continued)

NO.

SIGNAL NAME

P2.0

PIN TYPE⁽¹⁾

DESCRIPTION

PZ

16

17

1

I/O

General-purpose digital I/O with port interrupt and wakeup from LPMx.5

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

P4.0

P4.1

P4.2

P4.3

P4.4

P4.5

P4.6

P4.7

P5.0

P5.1

P5.2

P5.3

P5.4

P5.5

P5.6

P5.7

P6.0

P6.1

P6.2

P6.3

P6.4

P6.5

P6.6

P6.7

2

GPIO Port 2

GPIO Port 3

GPIO Port 4

GPIO Port 5

GPIO Port 6

28

29

30

39

31

32

33

34

35

36

37

38

44

45

46

47

48

49

50

53

54

55

56

57

58

59

60

61

62

71

72

73

63

64

65

66

Terminal Configuration and Functions

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表 4-2. Signal Descriptions (continued)

NO.

FUNCTION

SIGNAL NAME

P7.0

PIN TYPE⁽¹⁾

DESCRIPTION

PZ

67

68

69

70

77

78

83

84

79

80

81

82

92

93

94

95

40

41

42

43

22

23

24

25

6

I/O

General-purpose digital I/O with port interrupt and wakeup from LPMx.5

General-purpose digital I/O

P7.1

P7.2

P7.3

GPIO Port 7

P7.4

P7.5

P7.6

P7.7

P8.0

P8.1

P8.2

P8.3

GPIO Port 8

GPIO Port 9

GPIO Port J

I²C

P8.4

P8.5

P8.6

P8.7

P9.0

P9.1

P9.2

P9.3

PJ.0

PJ.1

General-purpose digital I/O

PJ.2

General-purpose digital I/O

PJ.3

General-purpose digital I/O

PJ.4

General-purpose digital I/O

PJ.5

7

General-purpose digital I/O

PJ.6

9

General-purpose digital I/O

PJ.7

10

15

14

94, 60

93, 59

General-purpose digital I/O

UCB0SCL

UCB0SDA

UCB1SCL

UCB1SDA

I²C clock for eUSCI_B0 I²C mode

I²C data for eUSCI_B0 I²C mode

I²C clock for eUSCI_B1 I²C mode

I²C data for eUSCI_B1 I²C mode

22

Terminal Configuration and Functions

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FUNCTION

表 4-2. Signal Descriptions (continued)

NO.

SIGNAL NAME

COM0

PIN TYPE⁽¹⁾

DESCRIPTION

PZ

63

64

65

66

67

68

69

70

O

LCD common output COM0 for LCD backplane

LCD common output COM1 for LCD backplane

LCD common output COM2 for LCD backplane

LCD common output COM3 for LCD backplane

LCD common output COM4 for LCD backplane

LCD common output COM5 for LCD backplane

LCD common output COM6 for LCD backplane

LCD common output COM7 for LCD backplane

COM1

COM2

COM3

COM4

COM5

COM6

COM7

LCD capacitor connection

CAUTION: LCDCAP/R33 must be connected to DVSS if not used.

LCDCAP

74

I/O

LCDREF

R03

72

71

72

73

I

External reference voltage input for regulated LCD voltage

Input/output port of lowest analog LCD voltage (V5)

I/O

R13

Input/output port of third most positive analog LCD voltage (V3 or V4)

Input/output port of second most positive analog LCD voltage (V2)

R23

Input/output port of most positive analog LCD voltage (V1)

CAUTION: LCDCAP/R33 must be connected to DVSS if not used.

R33

74

I/O

S0

62

61

60

59

58

57

56

55

54

53

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

O

LCD segment output

S1

S2

S3

S4

S5

S6

LCD

S7

S8

S9

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

S23

S24

S25

S26

S27

S28

S29

Terminal Configuration and Functions

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表 4-2. Signal Descriptions (continued)

NO.

FUNCTION

SIGNAL NAME

S30

PIN TYPE⁽¹⁾

DESCRIPTION

PZ

30

29

28

70

69

68

67

66

65

78

77

100

99

5

O

I

LCD segment output

S31

S32

S33

LCD (continued)

S34

S35

S36

S37

S38

MTIF_PIN_EN

MTIF_OUT_IN

AVCC1

AVSS1

AVSS2

AVSS3

AVSS4

AVSS5

DVCC1

DVCC2

DVCC3

DVSS1

DVSS2

DVSS3

PVCC

PVSS

Meter test interface pin enable

Meter test interface input and output

Analog power supply

Analog ground supply

Digital power supply

MTIF

I/O

P

8

11

96

27

52

76

26

51

75

88

87, 89

Power

Digital power supply

Digital ground supply

USS power supply

USS ground supply

25, 44,

82

RTC

RTCCLK

O

RTC clock calibration output

24

Terminal Configuration and Functions

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FUNCTION

表 4-2. Signal Descriptions (continued)

NO.

SIGNAL NAME

PIN TYPE⁽¹⁾

DESCRIPTION

PZ

Clock signal input for eUSCI_A0 SPI slave mode

Clock signal output for eUSCI_A0 SPI master mode

UCA0CLK

1, 45

I/O

UCA0SIMO

UCA0SOMI

UCA0STE

16, 47

17, 48

2, 46

I/O

Slave in/master out for eUSCI_A0 SPI mode

Slave out/master in for eUSCI_A0 SPI mode

Slave transmit enable for eUSCI_A0 SPI mode

Clock signal input for eUSCI_A1 SPI slave mode

Clock signal output for eUSCI_A1 SPI master mode

UCA1CLK

3

I/O

UCA1SIMO

UCA1SOMI

UCA1STE

18

19

4

I/O

Slave in/master out for eUSCI_A1 SPI mode

Slave out/master in for eUSCI_A1 SPI mode

Slave transmit enable for eUSCI_A1 SPI mode

Clock signal input for eUSCI_A2 SPI slave mode

Clock signal output for eUSCI_A2 SPI master mode

UCA2CLK

69, 56

I/O

UCA2SIMO

UCA2SOMI

UCA2STE

67, 54

68, 55

70, 57

I/O

Slave in/master out for eUSCI_A2 SPI mode

Slave out/master in for eUSCI_A2 SPI mode

Slave transmit enable for eUSCI_A2 SPI mode

SPI

Clock signal input for eUSCI_A3 SPI slave mode

Clock signal output for eUSCI_A3 SPI master mode

UCA3CLK

80

I/O

UCA3SIMO

UCA3SOMI

UCA3STE

82

81

79

I/O

Slave in/master out for eUSCI_A3 SPI mode

Slave out/master in for eUSCI_A3 SPI mode

Slave transmit enable for eUSCI_A3 SPI mode

Clock signal input for eUSCI_B0 SPI slave mode

Clock signal output for eUSCI_B0 SPI master mode

UCB0CLK

13

I/O

UCB0SIMO

UCB0SOMI

UCB0STE

14

15

12

I/O

Slave in/master out for eUSCI_B0 SPI mode

Slave out/master in for eUSCI_B0 SPI mode

Slave transmit enable for eUSCI_B0 SPI mode

Clock signal input for eUSCI_B1 SPI slave mode

Clock signal output for eUSCI_B1 SPI master mode

UCB1CLK

92, 58

I/O

UCB1SIMO

UCB1SOMI

UCB1STE

NMI

93, 59

94, 60

95, 61

21

I/O

I

Slave in/master out for eUSCI_B1 SPI mode

Slave out/master in for eUSCI_B1 SPI mode

Slave transmit enable for eUSCI_B1 SPI mode

Nonmaskable interrupt input

System

RST

21

I/O

Reset input active low

Terminal Configuration and Functions

25

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表 4-2. Signal Descriptions (continued)

NO.

FUNCTION

SIGNAL NAME

TA0.0

PIN TYPE⁽¹⁾

DESCRIPTION

PZ

2

I/O

TA0 CCR0 capture: CCI0A input, compare: Out0

TA0 CCR0 capture: CCI0B input, compare: Out0

TA0 CCR1 capture: CCI1A input, compare: Out1

TA0 CCR2 capture: CCI2A input, compare: Out2

TA0.0

TA0.1

TA0.2

39

77

84

28, 49,

59

TA0CLK

I

TA0 input clock

TA1.0

TA1.1

TA1.2

TA1CLK

TA4.0

TA4.1

TA4CLK

TB0.0

TB0.1

TB0.2

TB0.3

TB0.4

TB0.5

TB0.6

TB0CLK

3

40

I/O

I

TA1 CCR0 capture: CCI0A input, compare: Out0

TA1 CCR0 capture: CCI0B input, compare: Out0

TA1 CCR1 capture: CCI1A input, compare: Out1

TA1 CCR2 capture: CCI2A input, compare: Out2

TA1 input clock

78

92

28, 49

4

I/O

I

TA4 CCR0 capture: CCI0A input, compare: Out0

TA4 CCR0 capture: CCI0B input, compare: Out0

TA4CCR1 capture: CCI1B input, compare: Out1

TA4 CCR1 capture: CCI1A input, compare: Out1

TA4 input clock

29

30

83

23, 50

31

Timer

I/O

O

TB0 CCR0 capture: CCI0B input, compare: Out0

TB0 CCR0 capture: CCI0A input, compare: Out0

TB0 CCR1 capture: CCI1A input, compare: Out1

TB0 CCR1 compare: Out1

69

32

70

33

I/O

O

TB0 CCR2 capture: CCI2A input, compare: Out2

TB0 CCR2 compare: Out2

79

34

I/O

I

TB0 CCR3 capture: CCI3A input, compare: Out3

TB0 CCR3 capture: CCI3B input, compare: Out3

TB0 CCR4 capture: CCI4A input, compare: Out4

TB0 CCR4 capture: CCI4B input, compare: Out4

TB0 CCR5 capture: CCI5A input, compare: Out5

TB0CCR5 capture: CCI5B input, compare: Out5

TB0 CCR6 capture: CCI6B input, compare: Out6

TB0 CCR6 capture: CCI6A input, compare: Out6

TB0 clock input

80

12

36

13

37

25

38

28, 50

24, 35,

80, 84

TB0OUTH

I

Switch all PWM outputs high impedance input – TB0

UCA0RXD

UCA0TXD

UCA1RXD

UCA1TXD

UCA2RXD

UCA2TXD

UCA3RXD

UCA3TXD

17, 48

16, 47

19

I

O

I

Receive data for eUSCI_A0 UART mode

Transmit data for eUSCI_A0 UART mode

Receive data for eUSCI_A1 UART mode

Transmit data for eUSCI_A1 UART mode

Receive data for eUSCI_A2 UART mode

Transmit data for eUSCI_A2 UART mode

Receive data for eUSCI_A3 UART mode

Transmit data for eUSCI_A3 UART mode

18

O

I

UART

68, 55

67, 54

81

O

I

82

O

26

Terminal Configuration and Functions

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FUNCTION

表 4-2. Signal Descriptions (continued)

NO.

SIGNAL NAME

PIN TYPE⁽¹⁾

DESCRIPTION

PZ

15

97

98

95

91

90

85

86

USSTRG

I

USS trigger

USSXTIN

USSXTOUT

USSXT_BOUT

CH0_IN

Input for crystal or resonator of oscillator USSXT

Output for crystal or resonator of oscillator USSXT

Buffered output clock of USSXT

USS channel 0 RX

O

I

USS

CH0_OUT

CH1_IN

I/O

I

USS channel 0 TX

USS channel 1 RX

CH1_OUT

I/O

USS channel 1 TX

Terminal Configuration and Functions

27

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4.4 Pin Multiplexing

Pin multiplexing for these devices is controlled by both register settings and operating modes (for

example, if the device is in test mode). For details of the settings for each pin and diagrams of the

multiplexed ports, see 节 6.14.

4.5 Buffer Type

表 4-3 describes the buffer types that are referenced in 表 4-1.

表 4-3. Buffer Type

NOMINAL

OUTPUT

DRIVE

STRENGTH

(mA)

PULLUP (PU)

OR

PULLDOWN (PD)

BUFFER TYPE

(STANDARD)

NOMINAL

VOLTAGE

PU OR PD

STRENGTH

(µA)

OTHER

CHARACTERISTICS

HYSTERESIS

See analog modules in 节 5

for details.

Analog⁽¹⁾

LVCMOS

3.0 V

N

Y⁽²⁾

N

N/A

Programmable

N/A

See 节 5.13.5.

N/A

See 节 5.13.5.

N/A

Power

SVS enables hysteresis on

DVCC.

(DVCC)⁽³⁾

Power

3.0 V

0 V

N

N/A

(AVCC)⁽³⁾

Power

(PVCC)⁽³⁾

Power (DVSS

and AVSS)⁽³⁾

(1) This is a switch, not a buffer.

(2) Only for input pins

(3) This is supply input, not a buffer.

4.6 Connection of Unused Pins

表 4-4 lists the correct termination of unused pins.

表 4-4. Connection of Unused Pins⁽¹⁾

POTENTIAL

DV_CC

COMMENT

AVCC

PVCC

AVSS

PVSS

DV_CC

DV_SS

CHx_IN,

CHx_OUT

DV_SS

USSXTIN

DV_SS

Open

Do not connect to DVCC, AVCC, or PVCC

USSXTOUT

Px.0 to Px.7

Switched to port function, output direction (PxDIR.n = 1)

RST/NMI/SBWTD

IO

DV_CCor V_CC

47-kΩ pullup or internal pullup selected with 10-nF (2.2-nF⁽²⁾) pulldown

PJ.0/TDO

PJ.1/TDI

PJ.2/TMS

PJ.3/TCK

The JTAG pins are shared with general-purpose I/O function (PJ.x). If these pins are not used, set

them to port function, output direction. If used as JTAG pins, leave them open.

Open

TEST

This pin always has an internal pulldown enabled.

(1) For any unused pin with a secondary function that is shared with general-purpose I/O, follow the guidelines for the Px.0 to Px.7 pins.

(2) The pulldown capacitor must not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG

mode with TI tools like FET interfaces or GANG programmers.

28

Terminal Configuration and Functions

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5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

4.1

UNIT

At DVCC and AVCC pins

V_CC

Supply voltage⁽²⁾

V

At DVCC, AVCC, and PVCC pins

4.1

Voltage difference between DVCC and AVCC pins⁽³⁾

Voltage difference among DVCC, AVCC, and PVCC pins⁽³⁾

Applied to CHx_IN

±0.3

1.65

1.8

V

–0.3

Applied to CHx_IN with a duty cycle of 10% over 1 ms

V_I

Input voltage⁽²⁾

V

Applied to USSXTIN (USSXTOUT)

1.5

V_CC+ 0.3 V

(4.1 V Max)

Applied to any other pin

–0.3

Diode current at any device pin

±2

mA

°C

(4)

T_stg

Storage temperature

–40

125

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Voltages are referenced to V_SS

.

(3) Voltage differences between DVCC and AVCC that exceed the specified limits can cause malfunction of the device including erroneous

writes to RAM and FRAM.

(4) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

5.2 ESD Ratings

VALUE

UNIT

Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)(all except CHx_OUT

terminals)

±1000

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

±250

±1000

±250

Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)(on CHx_OUT

terminals)

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±1000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V

may actually have higher performance.

Specifications

29

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MAX UNIT

5.3 Recommended Operating Conditions

TYP data are based on V_CC= 3.0 V and T_A= 25°C (unless otherwise noted)

MIN NOM

V_CC

V_SS

T_A

Supply voltage range applied at all DVCC and AVCC pins^{(1) (2) (3) (4)}

Supply voltage range applied at PVCC pin⁽¹⁾

Supply voltage applied at all DVSS, AVSS, and PVSS pins

Operating free-air temperature

1.8⁽⁵⁾

2.2

0

3.6

V

–40

85

°C

µF

C_DVCC

Capacitor value at DVCC⁽⁶⁾

1 – 20%

No FRAM wait states

(NWAITSx = 0)

0

8⁽⁸⁾

f_SYSTEM

Processor frequency (maximum MCLK frequency)⁽⁷⁾

With FRAM wait states

(NWAITSx = 1)⁽⁹⁾

MHz

0

16⁽¹⁰⁾

f_LEA

LEA processor frequency

Maximum ACLK frequency

Maximum SMCLK frequency

f_ACLK

f_SMCLK

50 kHz

16⁽¹⁰⁾MHz

(1) TI recommends powering the AVCC, DVCC, PVCC pins from the same source. At a minimum, during power up, power down, and

device operation, the voltage difference among AVCC, DVCC, PVCC must not exceed the limits specified in Absolute Maximum

Ratings. Exceeding the specified limits can cause malfunction of the device including erroneous writes to RAM and FRAM.

(2) Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR

resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the recommendation for capacitor

C_DVCCshould limit the slopes accordingly.

(3) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.

(4) The USS module must be disabled if AVCC and DVCC are lower than 2.2 V.

(5) The minimum supply voltage is defined by the supervisor SVS levels. See the PMM SVS threshold parameters for the exact values.

(6) As a decoupling capacitor for each supply pin pair (DVCC and DVSS or AVCC and AVSS), place a low-ESR 100-nF (minimum) ceramic

capacitor as close as possible (within a few millimeters) to the respective pin pairs. For the PVCC and PVSS pair, place a low-ESR 22-

µF (minimum) ceramic capacitor as close as possible (within a few millimeters) to the pin pair.

(7) Modules may have a different maximum input clock specification. See the specification of each module in this data sheet.

(8) DCO settings and HF crystals with a typical value less than or equal to the specified MAX value are permitted.

(9) Wait states occur only on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always excecuted

without wait states.

(10) DCO settings and HF crystals with a typical value less than or equal to the specified MAX value are permitted. If a clock source with a

higher typical value is used, the clock must be divided in the clock system.

30

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5.4 Active Mode Supply Current Into V_CCExcluding External Current

(2)

over recommended operating free-air temperature (unless otherwise noted)⁽¹⁾

FREQUENCY (f_MCLK= f_SMCLK

)

1 MHz

0 WAIT

STATES

4 MHz

0 WAIT

STATES

8 MHz

0 WAIT

STATES

12 MHz

1 WAIT STATE 1 WAIT STATE

(NWAITSx = 1) (NWAITSx = 1)

16 MHz

EXECUTION

MEMORY

PARAMETER

V_CC

UNIT

(NWAITSx = 0)

TYP

MAX

TYP

MAX

TYP

MAX

TYP

MAX

TYP

MAX

I_{AM, FRAM_UNI}

FRAM

3.0 V

225

665

1275

1550

1970

µA

(Unified memory)⁽³⁾

FRAM

0% cache hit

ratio

I_{AM, FRAM}(0%)⁽⁴⁾

420

275

220

192

125

1455

855

650

535

237

2850

1650

1240

1015

450

2330

1770

1490

1290

670

3000

2265

1880

1620

790

(5)

FRAM

50% cache hit

ratio

I_{AM, FRAM}(50%)⁽⁴⁾

I_{AM, FRAM}(66%)⁽⁴⁾

I_{AM, FRAM}(75%)⁽⁴⁾

3.0 V

1022

1888

1443

1170

2041

1735

1490

2606

2197

1870

µA

(5)

FRAM

66% cache hit

ratio

(5)

FRAM

75% cache hit

ratio

261

182

FRAM

100% cache hit

ratio

I_{AM, FRAM}(100%)⁽⁴⁾

(5)

(6) (5)

I_{AM, RAM}

RAM

3.0 V

140

90

323

292

590

540

880

830

1070

1020

µA

(7) (5)

I_{AM, RAM only}

1313

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) Characterized with program executing typical data processing.

f_ACLK= 32768 Hz, f_MCLK= f_SMCLK= f_DCOat specified frequency, except for 12 MHz. For 12 MHz, f_DCO= 24 MHz and

f_MCLK= f_SMCLK= f_DCO/2.

At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency

(f_MCLK,eff) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by the number of wait

states or the cache hit ratio.

The following equation can be used to compute f_MCLK,eff

:

f_MCLK,eff= f_MCLK/ [wait states × (1 – cache hit ratio) + 1]

For example, with 1 wait state and 75% cache hit ratio, f_MCKL,eff= f_MCLK/ [1 × (1 – 0.75) + 1] = f_MCLK/ 1.25.

(3) Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM.

(4) Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit

ratio represents number cache accesess divided by the total number of FRAM accesses. For example, a 75% ratio implies three of

every four accesses is from cache, and the remaining are FRAM accesses.

(5) See for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best linear fit

using the typical data shown in Section 5.4.

(6) Program and data reside entirely in RAM. All execution is from RAM.

(7) Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.

Specifications

31

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5.5 Typical Characteristics, Active Mode Supply Currents

3000

I(AM,0%)

I(AM,50%)

2500

I(AM,66%)

I(AM,75%)

I(AM,75%)[µA] ~ 120 × f[MHz] + 68

2000

1500

1000

500

0

I(AM,100%)

I(AM,RAMonly)

0

1

2

3

4

5

6

7

8

9

MCLK Frequency (MHz)

A. I_{(AM,cache hit ratio)}: Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-

to-miss ratio as specified. Cache hit ratio represents number cache accesses divided by the total number of FRAM

accesses. For example, a 75% ratio implies three of every four accesses is from cache, and the remaining are FRAM

accesses.

B. I_(AM,RAMonly): Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.

图 5-1. Typical Active Mode Supply Currents, No Wait States

5.6 Low-Power Mode (LPM0, LPM1) Supply Currents Into V_CCExcluding External Current

(2)

over recommended operating free-air temperature (unless otherwise noted)⁽¹⁾

FREQUENCY (f_SMCLK

8 MHz

)

PARAMETER

V_CC

1 MHz

TYP

4 MHz

TYP

12 MHz

TYP

16 MHz

TYP

UNIT

MAX

148

70

MAX

TYP

180

190

136

MAX

316

2.2 V

3.0 V

2.2 V

3.0 V

80

95

40

115

125

70

276

286

230

235

250

265

205

210

I_LPM0

µA

178

245

340

I_LPM1

70

250

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) Current for watchdog timer clocked by SMCLK included.

f_ACLK= 32768 Hz, f_MCLK= 0 MHz, f_SMCLK= f_DCOat specified frequency, except for 12 MHz. For 12 MHz, f_DCO= 24 MHz and

f_MCLK= f_SMCLK= f_DCO/ 2.

32

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ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

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5.7 Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into V_CC) Excluding External

Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see 图 5-2 and 图

5-3)

TEMPERATURE

PARAMETER

–40°C

TYP

25°C

TYP

60°C

TYP

85°C

TYP

UNIT

V_CC

MAX

2.2 V

3 V

0.8

0.6

0.5

0.8

1.3

1.2

1.0

4.1

4.0

3.8

2.2

10.8

10.7

10.5

4.5

Low-power mode 2, 12‑pF

I_LPM2,XT12

I_LPM2,XT3.7

I_LPM2,VLO

μA

crystal^{(1) (2) (3)}

2.2 V

3 V

Low-power mode 2, 3.7‑pF

crystal^{(1) (4) (3)}

2.2 V

3 V

Low-power mode 2, VLO,

includes SVS⁽⁵⁾

Low-power mode 3, 12‑pF

2.2 V

1.1

10.1

I_LPM3,XT12

crystal, includes SVS^{(1) (2)}

μA

(6)

3 V

2.2 V

3 V

0.8

0.5

1.0

0.7

2.2

2.1

4.5

4.4

Low-power mode 3, 3.7‑pF

9.8

9.6

I_LPM3,XT3.7

crystal, excludes SVS^{(1) (4)}

μA

(7)

2.2 V

3 V

0.4

0.5

1.2

1.1

1.9

1.4

4.2

2.6

Low-power mode 3,

I_LPM3,VLO

VLO, excludes SVS⁽⁸⁾

Low-power mode 3,

VLO, excludes SVS, RAM

powered-down

2.2 V

0.36

0.47

2.9

8.2

9.7

I_LPM3,VLO,

RAMoff

μA

3 V

0.36

0.47

1.4

2.6

completely⁽⁸⁾

2.2 V

3 V

0.5

0.6

1.2

1.9

4.3

Low-power mode 4,

includes SVS⁽⁹⁾

I_LPM4,SVS

0.8

(1) Not applicable for devices with HF crystal oscillator only.

(2) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are

chosen to closely match the required 12.5‑pF load.

(3) Low-power mode 2, crystal oscillator test conditions:

Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included.

CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2), f_XT1= 32768 Hz, f_ACLK= f_XT1, f_MCLK= f_SMCLK= 0 MHz

(4) Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are

chosen to closely match the required 3.7‑pF load.

(5) Low-power mode 2, VLO test conditions:

Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout and SVS included.

CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2), f_XT1= 0 Hz, f_ACLK= f_VLO, f_MCLK= f_SMCLK= 0 MHz

(6) Low-power mode 3, 12‑pF crystal including SVS test conditions:

Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3), f_XT1= 32768 Hz, f_ACLK= f_XT1, f_MCLK= f_SMCLK= 0 MHz

Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional

idle current. Refer to the idle currents specified for the respective peripheral groups.

(7) Low-power mode 3, 3.7‑pF crystal excluding SVS test conditions:

Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE =

0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3), f_XT1= 32768 Hz, f_ACLK= f_XT1, f_MCLK= f_SMCLK= 0 MHz

Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional

idle current. Refer to the idle currents specified for the respective peripheral groups.

(8) Low-power mode 3, VLO excluding SVS test conditions:

Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). RAM disabled (RCCTL0 = 5A55h). Current for

brownout included. SVS disabled (SVSHE = 0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3), f_XT1= 0 Hz, f_ACLK= f_VLO, f_MCLK= f_SMCLK= 0 MHz

Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional

idle current. Refer to the idle currents specified for the respective peripheral groups.

(9) Low-power mode 4 including SVS test conditions:

Current for brownout and SVS included (SVSHE = 1).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4), f_XT1= 0 Hz, f_ACLK= 0 Hz, f_MCLK= f_SMCLK= 0 MHz

Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional

idle current. Refer to the idle currents specified for the respective peripheral groups.

Specifications

33

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Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into V_CC) Excluding External

Current (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see 图 5-2 and 图

5-3)

TEMPERATURE

PARAMETER

–40°C

TYP

25°C

TYP

60°C

TYP

85°C

TYP

UNIT

μA

V_CC

MAX

2.2 V

3 V

0.3

0.4

1.1

1.7

1.2

4.0

2.5

9.4

Low-power mode 4,

excludes SVS⁽¹⁰⁾

I_LPM4

Low-power mode 4,

excludes SVS, RAM

powered-down

2.2 V

0.37

1.0

2.8

8

I_LPM4,RAMoff

μA

3 V

0.3

0.37

0.02

1.2

2.5

completely⁽¹⁰⁾

Additional idle current if

one or more modules from

Group A (see 表 6-3) are

activated in LPM3 or LPM4

I_IDLE,GroupA

I_IDLE,GroupB

I_IDLE,GroupC

0.3

μA

Additional idle current if

one or more modules from

Group B (see 表 6-3) are

activated in LPM3 or LPM4

3 V

0.02

0.35

0.38

Additional idle current if

one or more modules from

Group C (see 表 6-3) are

activated in LPM3 or LPM4

(10) Low-power mode 4 excluding SVS test conditions:

Current for brownout included. SVS disabled (SVSHE = 0). RAM disabled (RCCTL0 = 5A55h).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4), f_XT1= 0 Hz, f_ACLK= 0 Hz, f_MCLK= f_SMCLK= 0 MHz

Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional

idle current. Refer to the idle currents specified for the respective peripheral groups.

34

Specifications

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5.8 Low-Power Mode With LCD Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEMPERATURE (T_A)

PARAMETER

V_CC

–40°C

TYP

25°C

TYP

60°C

TYP

85°C

TYP

UNIT

MAX

Low-power mode 3 (LPM3)

current,12 pF crystal, LCD

4-mux mode, external

I_LPM3,XT12

LCD,

ext. bias

3.0 V

0.9

1.1

2.5

5.1

µA

biasing, excludes SVS^{(1) (2)}

Low-power mode 3 (LPM3)

current,12 pF crystal, LCD

4-mux mode, internal

I_LPM3,XT12

LCD,

int. bias

3.0 V

1.3

1.4

2.0

2.2

4.5

4.9

12.5

µA

biasing, charge pump

disabled, excludes SVS⁽¹⁾

(3)

Low-power mode 3 (LPM3)

current,12 pF crystal, LCD

4-mux mode, internal

biasing, charge pump

enabled, 1/3 bias, excludes

SVS^{(1) (4)}

2.2 V

3.0 V

3.6

3.4

4

5.1

4.9

8.1

µA

I_LPM3,XT12

LCD,CP

3.7

(1) Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE =

0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),

f_XT1= 32768 Hz, f_ACLK= f_XT1, f_MCLK= f_SMCLK= 0 MHz

Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional

idle current - idle current of Group containing LCD module already included. Refer to the idle currents specified for the respective

peripheral groups.

(2) LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump

disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (f_LCD= 32768 Hz / 32 / 4 = 256 Hz)

Current through external resistors not included (voltage levels are supplied by test equipment).

Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.

(3) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump

disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (f_LCD= 32768 Hz / 32 / 4 = 256 Hz)

Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.

(4) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump

enabled), VLCDx = 1000 (V_LCD= 3 V typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (f_LCD= 32768 Hz / 32 / 4 = 256 Hz)

Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.

Specifications

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5.9 Low-Power Mode (LPMx.5) Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see 图 5-4 and 图

5-5)

TEMPERTURE (T_A)

PARAMETER

V_CC

–40°C

TYP

25°C

TYP

60°C

TYP

85°C

TYP MAX

UNIT

MAX

Low-power mode 3.5,

I_LPM3.5,XT1212‑pF crystal including

SVS^{(1) (2) (3)}

2.2 V

3.0 V

2.2 V

3.0 V

0.45

0.3

0.5

0.55

0.4

0.75

0.65

μA

Low-power mode 3.5,

I_LPM3.5,XT3.73.7‑pF crystal excluding

SVS^{(1) (4) (5)}

0.35

0.3

0.4

2.2 V

3.0 V

2.2 V

3.0 V

0.23

0.2

0.28

0.4

Low-power mode 4.5,

I_LPM4.5,SVS

μA

including SVS⁽⁶⁾

0.035

0.045

0.075

0.15

Low-power mode 4.5,

I_LPM4.5

excluding SVS⁽⁷⁾

(1) Not applicable for devices with HF crystal oscillator only.

(2) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are

chosen to closely match the required 12.5‑pF load.

(3) Low-power mode 3.5, 1‑pF crystal including SVS test conditions:

Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

f_XT1= 32768 Hz, f_ACLK= f_XT1, f_MCLK= f_SMCLK= 0 MHz

(4) Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are

chosen to closely match the required 3.7‑pF load.

(5) Low-power mode 3.5, 3.7‑pF crystal excluding SVS test conditions:

Current for RTC clocked by XT1 included.Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

f_XT1= 32768 Hz, f_ACLK= f_XT1, f_MCLK= f_SMCLK= 0 MHz

(6) Low-power mode 4.5 including SVS test conditions:

Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

f_XT1= 0 Hz, f_ACLK= 0 Hz, f_MCLK= f_SMCLK= 0 MHz

(7) Low-power mode 4.5 excluding SVS test conditions:

Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

f_XT1= 0 Hz, f_ACLK= 0 Hz, f_MCLK= f_SMCLK= 0 MHz

36

Specifications

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5.10 Typical Characteristics, Low-Power Mode Supply Currents

3

2.5

2

3

2.5

2

3.0 V, SVS off

2.2 V, SVS off

3.0 V, SVS on

2.2 V, SVS on

3.0 V, SVS off

2.2 V, SVS off

3.0 V, SVS on

2.2 V, SVS on

1.5

1

1.5

1

0.5

0

0.5

0

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature (°C)

图 5-2. LPM3 Supply Current (I_LPM3,XT3.7) vs Temperature

Temperature (°C)

图 5-3. LPM4 Supply Current (I_LPM4,SVS) vs Temperature

0.7

3.0 V, SVS off

2.2 V, SVS off

0.6

2.2 V, SVS off

0.6

3.0 V, SVS on

2.2 V, SVS on

0.5

0.4

0.3

0.2

0.1

0

0.4

0.3

0.2

0.1

0

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature (°C)

图 5-4. LPM3.5 Supply Current (I_LPM3.5,XT3.7) vs Temperature

Temperature (°C)

图 5-5. LPM4.5 Supply Current (I_LPM4.5) vs Temperature

Specifications

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5.11 Typical Characteristics, Current Consumption per Module⁽¹⁾

MODULE

Timer_A

TEST CONDITIONS

REFERENCE CLOCK

Module input clock

MIN

TYP

2.5

3.8

6.3

4.4

100

28

MAX

UNIT

μA/MHz

Timer_B

Module input clock

UART mode

SPI mode

7.0

4.8

eUSCI_A

Module input clock

μA/MHz

eUSCI_B

I²C mode, 100 kbaud

RTC_C

MPY

32 kHz

MCLK

nA

Only from start to end of operation

256-point complex FFT, data = nonzero

256-point complex FFT, data = zero

μA/MHz

CRC16

CRC32

3.3

86

68

LEA

MCLK

LFXT

µA/MHz

µA

66

Generator and counter are enabled at 256 Hz, no

terminal activity, pulse rate = 15 pulses

MTIF

0.20

(1) For other module currents not listed here, see the module-specific parameter sections.

5.12 Thermal Resistance Characteristics for 100-Pin LQFP (PZ) Package⁽¹⁾

THERMAL METRIC⁽²⁾

Junction-to-ambient thermal resistance, still air

Junction-to-case (top) thermal resistance

VALUE⁽³⁾

UNIT

°C/W

Rθ_JA

57.6

Rθ_JC(TOP)

Rθ_JB

14.9

Junction-to-board thermal resistance

35.6

Ψ_JB

Junction-to-board thermal characterization parameter

Junction-to-top thermal characterization parameter

Junction-to-case (bottom) thermal resistance

35.0

Ψ_JT

0.6

Rθ_JC(BOTTOM)

N/A

(1) N/A = not applicable

(2) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(3) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (Rθ_JC) value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC

standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

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5.13 Timing and Switching Characteristics

5.13.1 Power Supply Sequencing

TI recommends powering the AVCC, DVCC, and PVCC pins from the same source. At a minimum, during

power up, power down, and device operation, the voltage difference among AVCC, DVCC, and PVCC

must not exceed the limits specified in Section 5.1. Exceeding the specified limits can cause malfunction

of the device including erroneous writes to RAM and FRAM.

表 5-1 lists the power ramp requirements for brownout and power up.

表 5-1. Brownout and Device Reset Power Ramp Requirements

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Brownout power-down level⁽¹⁾

Brownout power-up level⁽¹⁾

TEST CONDITIONS

| dDV_CC/d_t| < 3 V/s

| dDV_CC/d_t| < 3 V/s⁽²⁾

MIN

0.7

MAX UNIT

V_{VCC_BOR–}

V_{VCC_BOR+}

1.66

1.68

V

0.79

(1) Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR

resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the recommendation for capacitor

C_DVCCshould limit the slopes accordingly.

(2) The brownout levels are measured with a slowly changing supply.

表 5-2 lists the characteristics of the SVS.

表 5-2. SVS

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

170

MAX UNIT

I_SVSH,LPM

V_SVSH–

SVS_Hcurrent consumption, low-power modes

SVS_Hpower-down level⁽¹⁾

SVS_Hpower-up level⁽¹⁾

300

1.85

1.99

120

10

nA

V

1.75

1.77

40

1.80

1.88

V_SVSH+

V

V_{SVSH_hys}

t_{PD,SVSH, AM}

SVS_Hhysteresis

mV

µs

SVS_Hpropagation delay, active mode

dV_Vcc/dt = –10 mV/µs

(1) For additional information, see the Dynamic Voltage Scaling Power Solution for MSP430 Devices With Single-Channel LDO Reference

Design.

Specifications

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5.13.2 Reset Timing

表 5-3 lists the requirements for the reset input.

表 5-3. Reset Input

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

t_(RST)External reset pulse duration on RST⁽¹⁾

V_CC

MIN

TYP

MAX UNIT

2.2 V, 3.0 V

2

µs

(1) Not applicable if the RST/NMI pin is configured as NMI.

5.13.3 Clock Specifications

Table 5-4 lists the characteristics of the low-frequency oscillator.

Table 5-4. Low-Frequency Crystal Oscillator, LFXT

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

f_OSC= 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {0},

180

T_A= 25°C, C_L,eff= 3.7 pF, ESR ≈ 44 kΩ

f_OSC= 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {1},

T_A= 25°C, C_L,eff= 6 pF, ESR ≈ 40 kΩ

185

225

I_VCC.LFXT

Current consumption

3.0 V

nA

f_OSC= 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {2},

T_A= 25°C, C_L,eff= 9 pF, ESR ≈ 40 kΩ

f_OSC= 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {3},

T_A= 25°C, C_L,eff= 12.5 pF, ESR ≈ 40 kΩ

330

LFXT oscillator crystal

frequency

f_LFXT

LFXTBYPASS = 0

32768

Hz

Measured at ACLK,

f_LFXT= 32768 Hz

DC_LFXT

f_LFXT,SW

DC_{LFXT, SW}

LFXT oscillator duty cycle

30%

70%

LFXT oscillator logic-level

square-wave input frequency

LFXTBYPASS = 1^{(2) (3)}

10.5 32.768

50 kHz

70%

LFXT oscillator logic-level

square-wave input duty cycle

LFXTBYPASS = 1

30%

210

300

LFXTBYPASS = 0, LFXTDRIVE = {1},

f_LFXT= 32768 Hz, C_L,eff= 6 pF

Oscillation allowance for

LF crystals⁽⁴⁾

OA_LFXT

kΩ

LFXTBYPASS = 0, LFXTDRIVE = {3},

f_LFXT= 32768 Hz, C_L,eff= 12.5 pF

(1) To improve EMI on the LFXT oscillator, observe the following guidelines:

•

Keep the trace between the device and the crystal as short as possible.

Design a good ground plane around the oscillator pins.

Prevent crosstalk from other clock or data lines into oscillator pins LFXIN and LFXOUT.

Avoid running PCB traces underneath or adjacent to the LFXIN and LFXOUT pins.

Use assembly materials and processes that avoid any parasitic load on the oscillator LFXIN and LFXOUT pins.

If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.

(2) When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics

defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DC_{LFXT, SW}

.

(3) Maximum frequency of operation of the entire device cannot be exceeded.

(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the

LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following

guidelines, but should be evaluated based on the actual crystal selected for the application:

•

For LFXTDRIVE = {0}, C_L,eff= 3.7 pF

For LFXTDRIVE = {1}, C_L,eff= 6 pF

For LFXTDRIVE = {2}, 6 pF ≤ C_L,eff≤ 9 pF

For LFXTDRIVE = {3}, 9 pF ≤ C_L,eff≤ 12.5 pF

40

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Table 5-4. Low-Frequency Crystal Oscillator, LFXT (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Integrated load capacitance at

LFXIN terminal^{(5) (6)}

C_LFXIN

2

pF

Integrated load capacitance at

LFXOUT terminal^{(5) (6)}

C_LFXOUT

2

pF

f_OSC= 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {0},

T_A= 25°C, C_L,eff= 3.7 pF

3.0 V

800

t_START,LFXT

Start-up time⁽⁷⁾

ms

f_OSC= 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {3},

T_A= 25°C, C_L,eff= 12.5 pF

1000

f_Fault,LFXT

Oscillator fault frequency^{(8) (9)}

0

3500

Hz

(5) This represents all the parasitic capacitance present at the LFXIN and LFXOUT terminals, respectively, including parasitic bond and

package capacitance. The effective load capacitance, C_L,effcan be computed as C_IN× C_OUT/ (C_IN+ C_OUT), where C_INand C_OUTis the

total capacitance at the LFXIN and LFXOUT terminals, respectively.

(6) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended

effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds

additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance

of the selected crystal is met.

(7) Includes start-up counter of 1024 clock cycles.

(8) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications may set the

flag. A static condition or stuck at fault condition will set the flag.

(9) Measured with logic-level input frequency but also applies to operation with crystals.

Table 5-5 lists the characteristics of the high-frequency oscillator.

Table 5-5. High-Frequency Crystal Oscillator, HFXT

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

f_OSC= 4 MHz,

HFXTBYPASS = 0, HFXTDRIVE = 0,

HFFREQ = 1⁽²⁾

V_CC

MIN

TYP

MAX UNIT

,

75

T_A= 25°C, C_L,eff= 18 pF,

typical ESR, C_shunt

f_OSC= 8 MHz,

HFXTBYPASS = 0, HFXTDRIVE = 1,

HFFREQ = 1,

T_A= 25°C, C_L,eff= 18 pF,

typical ESR, C_shunt

120

190

250

HFXT oscillator crystal current HF

mode at typical ESR

I_DVCC.HFXT

3.0 V

μA

f_OSC= 16 MHz,

HFXTBYPASS = 0, HFXTDRIVE = 2,

HFFREQ = 2,

T_A= 25°C, C_L,eff= 18 pF,

typical ESR, C_shunt

f_OSC= 24 MHz

HFXTBYPASS = 0, HFXTDRIVE = 3,

HFFREQ = 3,

T_A= 25°C, C_L,eff= 18 pF,

typical ESR, C_shunt

HFXTBYPASS = 0, HFFREQ = 1^{(2) (3)}

HFXTBYPASS = 0, HFFREQ = 2⁽³⁾

HFXTBYPASS = 0, HFFREQ = 3⁽³⁾

4

8.01

8

HFXT oscillator crystal frequency,

crystal mode

f_HFXT

16 MHz

24

16.01

(1) To improve EMI on the HFXT oscillator the following guidelines should be observed.

•

Keep the traces between the device and the crystal as short as possible.

Design a good ground plane around the oscillator pins.

Prevent crosstalk from other clock or data lines into oscillator pins HFXIN and HFXOUT.

Avoid running PCB traces underneath or adjacent to the HFXIN and HFXOUT pins.

Use assembly materials and processes that avoid any parasitic load on the oscillator LFXIN and LFXOUT pins.

If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.

(2) HFFREQ = {0} is not supported for HFXT crystal mode of operation.

(3) Maximum frequency of operation of the entire device cannot be exceeded.

Specifications

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Table 5-5. High-Frequency Crystal Oscillator, HFXT (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

40%

0.9

TYP

MAX UNIT

DC_HFXT

HFXT oscillator duty cycle

Measured at SMCLK, f_HFXT= 16 MHz

HFXTBYPASS = 1, HFFREQ = 0^{(4) (3)}

HFXTBYPASS = 1, HFFREQ = 1^{(4) (3)}

HFXTBYPASS = 1, HFFREQ = 2^{(4) (3)}

HFXTBYPASS = 1, HFFREQ = 3^{(4) (3)}

50%

60%

4

HFXT oscillator logic-level

square-wave input frequency,

bypass mode

4.01

8.01

16.01

8

f_HFXT,SW

MHz

16

24

DC_HFXT,

SW

HFXT oscillator logic-level

square-wave input duty cycle

HFXTBYPASS = 1

40%

60%

HFXTBYPASS = 0, HFXTDRIVE = 0,

HFFREQ = 1⁽²⁾

f_HFXT,HF= 4 MHz, C_L,eff= 16 pF

,

450

320

200

HFXTBYPASS = 0, HFXTDRIVE = 1,

HFFREQ = 1,

f_HFXT,HF= 8 MHz, C_L,eff= 16 pF

Oscillation allowance for

HFXT crystals⁽⁵⁾

OA_HFXT

Ω

HFXTBYPASS = 0, HFXTDRIVE = 2,

HFFREQ = 2,

f_HFXT,HF= 16 MHz, C_L,eff= 16 pF

HFXTBYPASS = 0, HFXTDRIVE = 3,

HFFREQ = 3,

f_HFXT,HF= 24 MHz, C_L,eff= 16 pF

f_OSC= 4 MHz,

HFXTBYPASS = 0, HFXTDRIVE = 0,

HFFREQ = 1,

T_A= 25°C, C_L,eff= 16 pF

3.0 V

1.6

0.6

t_START,HFXTStart-up time⁽⁶⁾

ms

pF

f_OSC= 24 MHz,

HFXTBYPASS = 0, HFXTDRIVE = 3,

HFFREQ = 3,

T_A= 25°C, C_L,eff= 16 pF

Integrated load capacitance at

C_HFXIN

2

HFXIN terminaI^{(7) (8)}

Integrated load capacitance at

HFXOUT terminaI^{(7) (8)}

Oscillator fault frequency^{(9) (10)}

C_HFXOUT

f_Fault,HFXT

pF

0

800 kHz

(4) When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics

defined in the Schmitt-trigger Inputs section of this datasheet. Duty cycle requirements are defined by DC_{HFXT, SW}

(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.

(6) Includes start-up counter of 1024 clock cycles.

.

(7) This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bond and

package capacitance. The effective load capacitance, C_L,effcan be computed as C_IN× C_OUT/ (C_IN+ C_OUT), where C_INand C_OUTis the

total capacitance at the HFXIN and HFXOUT terminals, respectively.

(8) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended

effective load capacitance values supported are 14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF. The PCB adds

additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance

of the selected crystal is met.

(9) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications might set the

flag. A static condition or stuck at fault condition will set the flag.

(10) Measured with logic-level input frequency but also applies to operation with crystals.

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Table 5-6 lists the characteristics of the DCO.

Table 5-6. DCO

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Measured at SMCLK, divide by 1,

DCORSEL = 0, DCOFSEL = 0,

DCORSEL = 1, DCOFSEL = 0

DCO frequency range

1 MHz, trimmed

f_DCO1

1

±3.5%

MHz

DCO frequency range

2.7 MHz, trimmed

Measured at SMCLK, divide by 1,

DCORSEL = 0, DCOFSEL = 1

f_DCO2.7

f_DCO3.5

f_DCO4

2.667

3.5

4

±3.5%

MHz

DCO frequency range

3.5 MHz, trimmed

Measured at SMCLK, divide by 1,

DCORSEL = 0, DCOFSEL = 2

DCO frequency range

4 MHz, trimmed

Measured at SMCLK, divide by 1,

DCORSEL = 0, DCOFSEL = 3

Measured at SMCLK, divide by 1,

DCORSEL = 0, DCOFSEL = 4,

DCORSEL = 1, DCOFSEL = 1

DCO frequency range

5.3 MHz, trimmed

f_DCO5.3

f_DCO7

f_DCO8

5.333

±3.5%

MHz

Measured at SMCLK, divide by 1,

DCORSEL = 0, DCOFSEL = 5,

DCORSEL = 1, DCOFSEL = 2

DCO frequency range

7 MHz, trimmed

7

8

Measured at SMCLK, divide by 1,

DCORSEL = 0, DCOFSEL = 6,

DCORSEL = 1, DCOFSEL = 3

DCO frequency range

8 MHz, trimmed

DCO frequency range

16 MHz, trimmed

Measured at SMCLK, divide by 1,

DCORSEL = 1, DCOFSEL = 4

f_DCO16

f_DCO21

f_DCO24

16 ±3.5%⁽¹⁾

21 ±3.5%⁽¹⁾

24 ±3.5%⁽¹⁾

MHz

DCO frequency range

21 MHz, trimmed

Measured at SMCLK, divide by 2,

DCORSEL = 1, DCOFSEL = 5

DCO frequency range

24 MHz, trimmed

Measured at SMCLK, divide by 2,

DCORSEL = 1, DCOFSEL = 6

Measured at SMCLK, divide by 1,

No external divide, all DCORSEL and

DCOFSEL settings except

f_DCO,DC

Duty cycle

48%

50%

52%

DCORSEL = 1, DCOFSEL = 5 and

DCORSEL = 1, DCOFSEL = 6

Based on f_signal= 10 kHz and DCO

used for 12-bit SAR ADC sampling

source. This achieves >74-dB SNR

due to jitter; that is, limited by ADC

performance.

t_{DCO, JITTER}

DCO jitter

2

3

ns

df_DCO/dT

DCO temperature drift⁽²⁾

3.0 V

0.01

%/ºC

(1) After a wakeup from LPM1, LPM2, LPM3, or LPM4, the DCO frequency f_DCOmight exceed the specified frequency range for a few clock

cycles by up to 5% before settling to the specified steady state frequency range.

(2) Calculated using the box method: (MAX(–40°C to 85ºC) – MIN(–40°C to 85ºC)) / MIN(–40°C to 85ºC) / (85ºC – (–40ºC))

Specifications

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Table 5-7 lists the characteristics of the VLO.

Table 5-7. Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Current consumption

VLO frequency

TEST CONDITIONS

MIN

TYP

100

9.4

MAX UNIT

I_VLO

nA

f_VLO

Measured at ACLK

6

14

kHz

%/°C

%/V

df_VLO/d_T

VLO frequency temperature drift

Measured at ACLK⁽¹⁾

Measured at ACLK⁽²⁾

Measured at ACLK

0.2

df_VLO/dV_CCVLO frequency supply voltage drift

f_VLO,DCDuty cycle

0.7

40%

50%

60%

(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

Table 5-8 lists the characteristics of the MODOSC.

Table 5-8. Module Oscillator (MODOSC)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Current consumption

TEST CONDITIONS

Enabled

MIN

TYP

25

MAX UNIT

I_MODOSC

μA

f_MODOSC

MODOSC frequency

MODOSC frequency temperature drift⁽¹⁾

4.0

4.8

5.4

MHz

%/℃

%/V

f_MODOSC/dT

0.08

1.4

f_MODOSC/dV_CCMODOSC frequency supply voltage drift⁽²⁾

Measured at SMCLK,

divide by 1

DC_MODOSCDuty cycle

40%

50%

60%

(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

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5.13.4 Wake-up Characteristics

Table 5-9 lists the times required to wake up from LPM or reset.

Table 5-9. Wake-up Times From Low-Power Modes and Reset

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEST

CONDITIONS

PARAMETER

V_CC

MIN

TYP

MAX UNIT

(Additional) wake-up time to activate the

FRAM in AM if previously disabled by the

FRAM controller or from an LPM if immediate

activation is selected for wakeup

t_{WAKE-UP FRAM}

6

10

μs

400 +

1.5 / f_DCO

t_{WAKE-UP LPM0}

Wake-up time from LPM0 to active mode⁽¹⁾

2.2 V, 3.0 V

ns

t_{WAKE-UP LPM1}

t_{WAKE-UP LPM2}

Wake-up time from LPM1 to active mode⁽¹⁾

Wake-up time from LPM2 to active mode⁽¹⁾

2.2 V, 3.0 V

6

μs

6.6 +

2.0/f_DCO

9.6 +

2.5/f_DCO

t_{WAKE-UP LPM3}

Wake-up time from LPM3 to active mode⁽¹⁾

Wake-up time from LPM4 to active mode⁽¹⁾

2.2 V, 3.0 V

μs

6.6 +

2.0 / f_DCO

9.6 +

2.5 / f_DCO

t_{WAKE-UP LPM4}

t_{WAKE-UP LPM3.5}Wake-up time from LPM3.5 to active mode⁽²⁾

t_{WAKE-UP LPM4.5}Wake-up time from LPM4.5 to active mode⁽²⁾

2.2 V, 3.0 V

350

0.4

450

0.8

μs

SVSHE = 1

SVSHE = 0

ms

Wake-up time from a RST pin triggered reset

t_WAKE-UP-RST

2.2 V, 3.0 V

480

0.5

596

1

μs

to active mode⁽²⁾

Wake-up time from power-up to active

t_WAKE-UP-BOR

ms

mode⁽²⁾

(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first

externally observable MCLK clock edge with MCLKREQEN = 1. This time includes the activation of the FRAM during wakeup. With

MCLKREQEN = 0, the externally observable MCLK clock is gated one additional cycle.

(2) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first

instruction of the user program is executed.

Specifications

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MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

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Table 5-10 lists the typical charges used during wakeup.

Table 5-10. Typical Wake-up Charges

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

TEST

CONDITIONS

PARAMETER

MIN

TYP

16.5

3.8

21

MAX UNIT

nAs

Charge used for activating the FRAM in AM or during wakeup

from LPM0 if previously disabled by the FRAM controller.

Q_{WAKE-UP FRAM}

Q_{WAKE-UP LPM0}

Q_{WAKE-UP LPM1}

Q_{WAKE-UP LPM2}

Q_{WAKE-UP LPM3}

Charge used to wake up from LPM0 to active mode (with

FRAM active)

nAs

Charge used to wake up from LPM1 to active mode (with

FRAM active)

nAs

Charge used to wake up from LPM2 to active mode (with

FRAM active)

22

nAs

Charge used to wake up from LPM3 to active mode (with

FRAM active)

28

nAs

Charge used to wake up from LPM4 to active mode (with

FRAM active)

Charge used to wake up from LPM3.5 to active mode⁽²⁾

Q_{WAKE-UP LPM4}

Q_{WAKE-UP LPM3.5}

Q_{WAKE-UP LPM4.5}

28

nAs

170

173

171

SVSHE = 1

SVSHE = 0

Charge used to wake up from LPM4.5 to active mode⁽²⁾

nAs

Charge used for reset from RST or BOR event to active

mode⁽²⁾

Q_{WAKE-UP-RESET}

148

(1) Charge used during the wake-up time from a given low-power mode to active mode. This does not include the energy required in active

mode (for example, for an interrupt service routine).

(2) Charge required until start of user code. This does not include the energy required to reconfigure the device.

46

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MSP430FR6035

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MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

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5.13.4.1 Typical Characteristics, Average LPM Currents vs Wake-up Frequency

图 5-6 shows the average LPM currents vs wake-up frequency at 25°C.

10000.00

LPM0

LPM1

LPM2,XT12

1000.00

LPM3,XT12

LPM3.5,XT12

100.00

10.00

1.00

0.10

0.001

0.01

0.1

1

10

100

1000

10000

100000

Wake-up Frequency (Hz)

NOTE: The average wake-up current does not include the energy required in active mode; for example, for an interrupt

service routine or to reconfigure the device.

图 5-6. Average LPM Currents vs Wake-up Frequency at 25°C

图 5-7 shows the average LPM currents vs wake-up frequency at 85°C.

10000.00

LPM0

LPM1

LPM2,XT12

1000.00

LPM3,XT12

LPM3.5,XT12

100.00

10.00

1.00

0.10

0.001

0.01

0.1

1

10

100

1000

10000

100000

Wake-up Frequency (Hz)

NOTE: The average wake-up current does not include the energy required in active mode; for example, for an interrupt

service routine or to reconfigure the device.

图 5-7. Average LPM Currents vs Wake-up Frequency at 85°C

Specifications

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

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5.13.5 Digital I/Os

Table 5-11 lists the characteristics of the digital inputs.

Table 5-11. Digital Inputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

1.2

TYP

MAX UNIT

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

1.65

V

V_IT+

V_IT–

V_hys

Positive-going input threshold voltage

1.65

0.55

0.75

0.44

0.60

2.25

1.00

V

Negative-going input threshold voltage

1.35

0.98

V

Input voltage hysteresis (V_IT+– V_IT–

Pullup or pulldown resistor

)

1.30

For pullup: V_IN= V_SS

For pulldown: V_IN= V_CC

R_Pull

C_I,dig

C_I,ana

20

35

3

50

kΩ

pF

Input capacitance, digital only port pins

V_IN= V_SSor V_CC

Input capacitance, port pins with shared analog

functions⁽¹⁾

V_IN= V_SSor V_CC

5

2.2 V,

3.0 V

(2)(3)

I_lkg(Px.y)High-impedance input leakage current

See

–20

20

2

+20

nA

ns

µs

Ports with interrupt

capability (see 节 1.4 and

节 4.3).

External interrupt timing (external trigger pulse

2.2 V,

3.0 V

t_(int)

duration to set interrupt flag)⁽⁴⁾

2.2 V,

3.0 V

(5)

t_(RST)

External reset pulse duration on RST

(1) If the port pins PJ.4/LFXIN and PJ.5/LFXOUT are used as digital I/Os, they are connected by a 4-pF capacitor and a 35-MΩ resistor in

series. At frequencies of approximately 1 kHz and lower, the 4-pF capacitor can add to the pin capacitance of PJ.4/LFXIN and/or

PJ.5/LFXOUT.

(2) The input leakage current is measured with V_SSor V_CCapplied to the corresponding pins, unless otherwise noted.

(3) The input leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is

disabled.

(4) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t_(int)is met. It might be set by trigger signals

shorter than t_(int)

.

(5) Not applicable if RST/NMI pin configured as NMI

48

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MSP430FR6035

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MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

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Table 5-12 lists the characteristics of the digital outputs.

Table 5-12. Digital Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_(OHmax)= –1 mA⁽¹⁾

V_CC

MIN

TYP

MAX UNIT

V_CC

–

V_CC

0.25

2.2 V

V_CC

–

I_(OHmax)= –3 mA⁽²⁾

I_(OHmax)= –2 mA⁽¹⁾

I_(OHmax)= –6 mA⁽²⁾

I_(OLmax)= 1 mA⁽¹⁾

I_(OLmax)= 3 mA⁽²⁾

I_(OLmax)= 2 mA⁽¹⁾

I_(OLmax)= 6 mA⁽²⁾

V_CC

0.60

High-level output voltage

(see 图 5-10 and 图 5-11)

V_OH

V

V_CC

–

V_CC

0.25

3.0 V

2.2 V

3.0 V

V_CC

–

V_CC

0.60

V_SS

+

V_SS

0.25

V_SS

+

0.60

Low-level output voltage

(see 图 5-8 and 图 5-9)

V_OL

V

V_SS

+

0.25

V_SS

+

0.60

2.2 V

3.0 V

2.2 V

16

Port output frequency (with load)⁽³⁾

Clock output frequency⁽³⁾

C_L= 20 pF, R_L

MHz

(4) (5)

f_Px.y

ACLK, MCLK, or SMCLK at

configured output port,

C_L= 20 pF⁽⁵⁾

f_{Port_CLK}

3.0 V

16

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

4

3

4

3

6

4

6

4

15

t_rise,dig

Port output rise time, digital only port pins

Port output fall time, digital only port pins

C_L= 20 pF

ns

t_fall,dig

Port output rise time, port pins with shared

analog functions

t_rise,ana

Port output fall time, port pins with shared

analog functions

t_fall,ana

(1) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop

specified.

(2) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage

drop specified.

(3) The port can output frequencies at least up to the specified limit, and the port might support higher frequencies.

(4) A resistive divider with 2 × R1 and R1 = 1.6 kΩ between V_CCand V_SSis used as load. The output is connected to the center tap of the

divider. C_L= 20 pF is connected from the output to V_SS

.

(5) The output voltage reaches at least 10% and 90% V_CCat the specified toggle frequency.

Specifications

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

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5.13.5.1 Typical Characteristics, Digital Outputs

15

30

20

10

0

25°C

85°C

10

5

P1.1

0

0.5

1

1.5

2

0

0.5

1

1.5

2

2.5

3

Low-Level Output Voltage (V)

C001

V_CC= 2.2 V

V_CC= 3.0 V

图 5-8. Typical Low-Level Output Current vs

图 5-9. Typical Low-Level Output Current vs

Low-Level Output Voltage

0

25°C

85°C

25°C

85°C

-5

-10

-20

-30

-10

P1.1

-15

0

0.5

1

1.5

2

0

0.5

1

1.5

2

2.5

3

High-Level Output Voltage (V)

C001

V_CC= 2.2 V

图 5-10. Typical High-Level Output Current vs

V_CC= 3.0 V

图 5-11. Typical High-Level Output Current vs

High-Level Output Voltage

50

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

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5.13.6 LEA

Table 5-13 lists the characteristics of the LEA.

Table 5-13. Low-Energy Accelerator (LEA) Performance

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Frequency for specified

performance

f_LEA

MCLK

16

MHz

LEA subsystem energy on fast Complex FFT 128 pt. Q.15 with

Fourier transform random data in LEA-RAM

V_CORE= 3 V,

MCLK = 16 MHz

W_LEA_FFT

W_LEA_FIR

350

2.6

nJ

µJ

LEA subsystem energy on finite Real FIR on random Q.31 data with

V_CORE= 3 V,

MCLK = 16 MHz

impulse response

128 taps on 24 points

On 32 Q.31 elements with random

value out of LEA-RAM with linear

address increment

LEA subsystem energy on

additions

V_CORE= 3 V,

MCLK = 16 MHz

W_LEA_ADD

6.6

nJ

5.13.7 Timer_A and Timer_B

Table 5-14 lists the characteristics of Timer_A.

Table 5-14. Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK or ACLK,

External: TACLK,

f_TA

Timer_A input clock frequency

2.2 V, 3.0 V

16 MHz

Duty cycle = 50% ±10%

All capture inputs, minimum pulse

duration required for capture

t_TA,cap

Timer_A capture timing

2.2 V, 3.0 V

20

ns

Table 5-15 lists the characteristics of Timer_B.

Table 5-15. Timer_B

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK or ACLK,

External: TBCLK,

f_TB

Timer_B input clock frequency

2.2 V, 3.0 V

16 MHz

Duty cycle = 50% ±10%

All capture inputs, minimum pulse

duration required for capture

t_TB,cap

Timer_B capture timing

2.2 V, 3.0 V

20

ns

Specifications

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MSP430FR6035

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MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

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5.13.8 eUSCI

Table 5-16 lists the supported clock frequencies of the eUSCI in UART mode.

Table 5-16. eUSCI (UART Mode) Clock Frequency

PARAMETER

CONDITIONS

MIN

MAX

UNIT

Internal: SMCLK or ACLK,

External: UCLK,

Duty cycle = 50% ±10%

f_eUSCI

eUSCI input clock frequency

16

4

MHz

BITCLK clock frequency

(equals baud rate in MBaud)

f_BITCLK

MHz

Table 5-17 lists the switching characteristics of the eUSCI in UART mode.

Table 5-17. eUSCI (UART Mode) Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

UCGLITx = 0

V_CC

MIN

5

TYP

MAX UNIT

30

UCGLITx = 1

UCGLITx = 2

UCGLITx = 3

20

35

50

90

ns

t_t

UART receive deglitch time⁽¹⁾

2.2 V, 3.0 V

160

220

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. Thus the selected deglitch

time can limit the maximum useable baud rate. To ensure that pulses are correctly recognized, their duration should exceed the

maximum specification of the deglitch time.

Table 5-18 lists the supported clock frequency of the eUSCI in SPI master mode.

Table 5-18. eUSCI (SPI Master Mode) Clock Frequency

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Internal: SMCLK or ACLK,

Duty cycle = 50% ±10%

f_eUSCI

eUSCI input clock frequency

16

MHz

52

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MSP430FR6035

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MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

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Table 5-19 lists the switching characteristics of the eUSCI in SPI master mode.

Table 5-19. eUSCI (SPI Master Mode) Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX

UNIT

STE lead time, STE active to

clock

t_STE,LEAD

t_STE,LAG

t_STE,ACC

t_STE,DIS

UCSTEM = 1, UCMODEx = 01 or 10

1

UCxCLK

cycles

STE lag time, Last clock to STE

inactive

UCSTEM = 1, UCMODEx = 01 or 10

UCSTEM = 0, UCMODEx = 01 or 10

1

STE access time, STE active to

SIMO data out

2.2 V, 3.0 V

60

80

ns

STE disable time, STE inactive to

SOMI high impedance

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

40

0

t_SU,MI

SOMI input data setup time

SOMI input data hold time

SIMO output data valid time⁽²⁾

SIMO output data hold time⁽³⁾

ns

t_HD,MI

0

11

10

UCLK edge to SIMO valid,

C_L= 20 pF

t_VALID,MO

0

t_HD,MO

C_L= 20 pF

(1) f_UCxCLK= 1/2 t_LO/HIwith t_LO/HI= max(t_{VALID,MO(eUSCI)}+ t_SU,SI(Slave), t_SU,MI(eUSCI)+ t_{VALID,SO(Slave)}).

For the slave parameters t_SU,SI(Slave)and t_{VALID,SO(Slave)}, see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams

in 图 5-12 and 图 5-13.

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in 图 5-12

and 图 5-13.

Specifications

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MSP430FR6035

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ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

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UCMODEx = 01

t_STE,LEAD

t_STE,LAG

STE

UCMODEx = 10

CKPL = 0

1/f_UCxCLK

UCLK

CKPL = 1

t_LOW/HIGH

t_SU,MI

t_HD,MI

SOMI

SIMO

t_HD,MO

t_VALID,MO

t_STE,ACC

t_STE,DIS

图 5-12. SPI Master Mode, CKPH = 0

UCMODEx = 01

STE

t_STE,LEAD

t_STE,LAG

UCMODEx = 10

1/f_UCxCLK

CKPL = 0

UCLK

CKPL = 1

t_LOW/HIGH

t_HD,MI

t_SU,MI

SOMI

SIMO

t_HD,MO

t_VALID,MO

t_STE,DIS

t_STE,ACC

图 5-13. SPI Master Mode, CKPH = 1

54

Specifications

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MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

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Table 5-20 lists the switching characteristics of the eUSCI in SPI slave mode.

Table 5-20. eUSCI (SPI Slave Mode) Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

45

40

2

MAX UNIT

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

t_STE,LEAD

t_STE,LAG

t_STE,ACC

t_STE,DIS

t_SU,SI

STE lead time, STE active to clock

ns

STE lag time, Last clock to STE inactive

ns

3

45

ns

40

STE access time, STE active to SOMI data out

50

ns

45

STE disable time, STE inactive to SOMI high

impedance

4

7

SIMO input data setup time

SIMO input data hold time

SOMI output data valid time⁽²⁾

SOMI output data hold time⁽³⁾

ns

t_HD,SI

35

ns

35

UCLK edge to SOMI valid,

C_L= 20 pF

t_VALID,SO

0

t_HD,SO

C_L= 20 pF

ns

(1) f_UCxCLK= 1/2 t_LO/HIwith t_LO/HI≥ max(t_{VALID,MO(Master)}+ t_SU,SI(eUSCI), t_{SU,MI(Master)}+ t_{VALID,SO(eUSCI)}

)

For the master parameters t_{SU,MI(Master)}and t_{VALID,MO(Master)}, see the SPI parameters of the attached master.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams

in 图 5-14 and 图 5-15.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in 图 5-14 and

图 5-15.

Specifications

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MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

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UCMODEx = 01

t_STE,LEAD

t_STE,LAG

STE

UCMODEx = 10

1/f_UCxCLK

CKPL = 0

UCLK

CKPL = 1

t_SU,SI

t_LOW/HIGH

t_HD,SI

SIMO

t_HD,SO

t_VALID,SO

t_STE,ACC

t_STE,DIS

SOMI

图 5-14. SPI Slave Mode, CKPH = 0

UCMODEx = 01

UCMODEx = 10

t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

UCLK

CKPL = 1

t_LOW/HIGH

t_HD,SI

t_SU,SI

SIMO

t_HD,SO

t_VALID,SO

t_STE,ACC

t_STE,DIS

SOMI

图 5-15. SPI Slave Mode, CKPH = 1

56

Specifications

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MSP430FR6037, MSP430FR60371, MSP430FR6035

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Table 5-21 lists the switching characteristics of the eUSCI in I²C mode.

Table 5-21. eUSCI (I²C Mode) Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see 图 5-16)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK or ACLK,

External: UCLK,

f_eUSCI

eUSCI input clock frequency

16 MHz

Duty cycle = 50% ±10%

f_SCL

SCL clock frequency

2.2 V, 3.0 V

0

4.0

0.6

4.7

0.6

0

400 kHz

µs

f_SCL= 100 kHz

f_SCL> 100 kHz

f_SCL= 100 kHz

f_SCL> 100 kHz

t_HD,STA

Hold time (repeated) START

t_SU,STA

Setup time for a repeated START

2.2 V, 3.0 V

µs

t_HD,DAT

t_SU,DAT

Data hold time

Data setup time

2.2 V, 3.0 V

ns

100

4.0

0.6

4.7

1.3

50

f_SCL= 100 kHz

f_SCL> 100 kHz

f_SCL= 100 kHz

f_SCL> 100 kHz

UCGLITx = 0

UCGLITx = 1

UCGLITx = 2

UCGLITx = 3

UCCLTOx = 1

UCCLTOx = 2

UCCLTOx = 3

t_SU,STO

Setup time for STOP

2.2 V, 3.0 V

µs

Bus free time between a STOP and

START condition

t_BUF

us

250

25

125

ns

Pulse duration of spikes suppressed by

input filter

t_SP

2.2 V, 3.0 V

12.5

6.3

62.5

31.5

27

30

33

t_TIMEOUT

Clock low time-out

2.2 V, 3.0 V

ms

t_HD,STA

t_SU,STA

t_HD,STA

t_BUF

SDA

t_LOW

t_HIGH

t_SP

SCL

t_SU,DAT

t_SU,STO

t_HD,DAT

图 5-16. I²C Mode Timing

Specifications

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5.13.9 Segment LCD Controller

Table 5-22 lists the recommended operating conditions for the LCD controller.

Table 5-22. LCD_C Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER

CONDITIONS

MIN

NOM

MAX UNIT

Supply voltage range, charge

pump enabled, V_LCD≤ 3.6 V

LCDCPEN = 1, 0000b < VLCDx ≤ 1111b

(charge pump enabled, V_LCD≤ 3.6 V)

V_{CC,LCD_C,CP en,3.6}

V_{CC,LCD_C,CP en,3.3}

V_{CC,LCD_C,int. bias}

V_{CC,LCD_C,ext. bias}

2.2

3.6

V

Supply voltage range, charge

pump enabled, V_LCD≤ 3.3 V

LCDCPEN = 1, 0000b < VLCDx ≤ 1100b

(charge pump enabled, V_LCD≤ 3.3 V)

2.0

2.4

Supply voltage range, internal

biasing, charge pump disabled

LCDCPEN = 0, VLCDEXT = 0

Supply voltage range, external

biasing, charge pump disabled

Supply voltage range, external

V_{CC,LCD_C,VLCDEXT}

LCD voltage, internal or external LCDCPEN = 0, VLCDEXT = 1

biasing, charge pump disabled

2.0

2.4

3.6

V

External LCD voltage at

V_LCDCAP

LCDCAP, internal or external

biasing, charge pump disabled

LCDCPEN = 0, VLCDEXT = 1

3.6

V

Capacitor value on LCDCAP

when charge pump enabled

LCDCPEN = 1, VLCDx > 0000b (charge

pump enabled)

C_LCDCAP

f_ACLK,in

f_LCD

4.7_–20%

4.7

10_+20%

µF

ACLK input frequency range

30

0

32.768

40 kHz

f_FRAME= (1 / (2 × mux)) × f_LCDwith

mux = 1 (static) to 8

LCD frequency range

1024

Hz

f_FRAME,4mux(MAX) = (1 / (2 × 4)) ×

f_LCD(MAX) = (1 / (2 × 4)) × 1024 Hz

f_FRAME,4mux

LCD frame frequency range

128

f_LCD= 1024 Hz, all common lines equally

loaded

C_Panel

V_R33

Panel capacitance

10000

pF

V

Analog input voltage at R33

LCDCPEN = 0, VLCDEXT = 1

2.4

V_CC+ 0.2

V_R03

2/3 ×

(V_R33

V_R03

+

LCDREXT = 1, LCDEXTBIAS = 1,

LCD2B = 0

V_R23,1/3bias

V_R13,1/3bias

V_R13,1/2bias

Analog input voltage at R23

V_R13

V_R33

V_R23

V_R33

V

–

)

V_R03

+

Analog input voltage at R13 with LCDREXT = 1, LCDEXTBIAS = 1,

1/3 biasing LCD2B = 0

1/3 ×

(V_R33

V_R03

–

)

V_R03

+

Analog input voltage at R13 with LCDREXT = 1, LCDEXTBIAS = 1,

1/2 ×

(V_R33

V_R03

1/2 biasing

LCD2B = 1

–

)

V_R03

Analog input voltage at R03

R0EXT = 1

V_SS

2.4

V

Voltage difference between

V_LCDand R03

V_LCD– V_R03

LCDCPEN = 0, R0EXT = 1

V_CC+ 0.2

1.2

External LCD reference voltage

applied at LCDREF

V_LCDREF

VLCDREFx = 01

0.8

1.0

V

58

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Table 5-23 lists the electrical characteristics the LCD controller.

Table 5-23. LCD_C Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VLCDx = 0000, VLCDEXT = 0

LCDCPEN = 1, VLCDx = 0001b

LCDCPEN = 1, VLCDx = 0010b

LCDCPEN = 1, VLCDx = 0011b

LCDCPEN = 1, VLCDx = 0100b

LCDCPEN = 1, VLCDx = 0101b

LCDCPEN = 1, VLCDx = 0110b

LCDCPEN = 1, VLCDx = 0111b

LCDCPEN = 1, VLCDx = 1000b

LCDCPEN = 1, VLCDx = 1001b

LCDCPEN = 1, VLCDx = 1010b

LCDCPEN = 1, VLCDx = 1011b

LCDCPEN = 1, VLCDx = 1100b

LCDCPEN = 1, VLCDx = 1101b

LCDCPEN = 1, VLCDx = 1110b

LCDCPEN = 1, VLCDx = 1111b

V_CC

MIN

TYP

V_CC

MAX UNIT

V_LCD,0

V_LCD,1

V_LCD,2

V_LCD,3

V_LCD,4

V_LCD,5

V_LCD,6

V_LCD,7

V_LCD,8

V_LCD,9

V_LCD,10

V_LCD,11

V_LCD,12

V_LCD,13

V_LCD,14

V_LCD,15

2.4 V to 3.6 V

2 V to 3.6 V

2.2 V to 3.6 V

2 V to 3.6 V

2.49

2.60

2.66

2.72

2.78

2.84

2.90

2.96

3.02

3.08

3.14

3.20

3.26

3.32

3.38

3.44

2.72

LCD voltage

V

3.32

3.6

LCD voltage with external

reference of 0.8 V

LCDCPEN = 1, VLCDx = 0111b,

VLCDREFx = 01b, V_LCDREF= 0.8 V

2.96 ×

0.8 V

V_LCD,7,0.8

V_LCD,7,1.0

V_LCD,7,1.2

ΔV_LCD

V

LCD voltage with external

reference of 1.0 V

LCDCPEN = 1, VLCDx = 0111b,

VLCDREFx = 01b, V_LCDREF= 1.0 V

2 V to 3.6 V

2.96 ×

1.0 V

V

LCD voltage with external

reference of 1.2 V

LCDCPEN = 1, VLCDx = 0111b,

VLCDREFx = 01b, V_LCDREF= 1.2 V

2.2 V to 3.6 V

2.96 ×

1.2 V

Voltage difference between

consecutive VLCDx settings

ΔV_LCD= V_LCD,x– V_LCD,x–1

with x = 0010b to 1111b

40

50

60

600

100

80

mV

µA

LCDCPEN = 1, VLCDx = 1111b

external, with decoupling capacitor on

DVCC supply ≥1 µF

Peak supply currents due to

charge pump activities

I_CC,Peak,CP

2.2 V

Time to charge C_LCDwhen

discharged

C_LCD= 4.7 µF, LCDCPEN = 0→1,

VLCDx = 1111b

t_LCD,CP,on

I_CP,Load

R_LCD,Seg

R_LCD,COM

2.2 V

500

ms

µA

kΩ

Maximum charge pump load

current

LCDCPEN = 1, VLCDx = 1111b

LCDCPEN = 0, I_LOAD= ±10 µA

LCD driver output impedance,

segment lines

10

LCD driver output impedance,

common lines

Specifications

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5.13.10 ADC12_B

Table 5-24 lists the power and input requirements of the ADC.

Table 5-24. 12-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN NOM

MAX UNIT

V_(Ax)

Analog input voltage range⁽¹⁾

All ADC12 analog input pins Ax

0

AVCC

V

f_ADC12CLK= MODCLK, ADC12ON = 1,

ADC12PWRMD = 0, ADC12DIF = 0,

REFON = 0, ADC12SHTx = 0,

ADC12DIV = 0

3.0 V

2.2 V

145

140

199

I_{(ADC12_B)}

single-ended

mode

Operating supply current into

µA

AVCC and DVCC terminals^{(2) (3)}

f_ADC12CLK= MODCLK, ADC12ON = 1,

ADC12PWRMD = 0, ADC12DIF = 0,

REFON = 0, ADC12SHTx = 0,

ADC12DIV = 0

190

f_ADC12CLK= MODCLK, ADC12ON = 1,

ADC12PWRMD = 0, ADC12DIF = 1,

3.0 V

2.2 V

175

170

245

230

I_{(ADC12_B)}

differential

mode

Operating supply current into

µA

AVCC and DVCC terminals^{(2) (3)}REFON = 0, ADC12SHTx= 0,

ADC12DIV = 0

f_ADC12CLK= MODCLK/4, ADC12ON = 1,

ADC12PWRMD = 1, ADC12DIF = 0,

REFON = 0, ADC12SHTx = 0,

ADC12DIV = 0

3.0 V

2.2 V

85

83

125

120

I_{(ADC12_B)}

Operating supply current into

single-ended

low-power

mode

AVCC and DVCC terminals^{(2) (3)}

f_ADC12CLK= MODCLK/4, ADC12ON = 1,

ADC12PWRMD = 1, ADC12DIF = 0,

REFON = 0, ADC12SHTx = 0,

ADC12DIV = 0

I_{(ADC12_B)}

f_ADC12CLK= MODCLK/4, ADC12ON = 1,

ADC12PWRMD = 1, ADC12DIF = 1,

3.0 V

2.2 V

110

109

165

160

Operating supply current into

differential

low-power

mode

AVCC and DVCC terminals^{(2) (3)}REFON = 0, ADC12SHTx= 0,

ADC12DIV = 0

Only one terminal Ax can be selected at

one time

C_I

R_I

Input capacitance

2.2 V

10

15

pF

>2 V

<2 V

0.5

1

4

Input MUX ON resistance

0 V ≤ V_(Ax)≤ AV_CC

kΩ

10

(1) The analog input voltage range must be within the selected reference voltage range V_R+to V_R–for valid conversion results.

(2) The internal reference supply current is not included in current consumption parameter I(ADC12_B).

(3) Approximately 60% (typical) of the total current into the AVCC and DVCC terminal is from AVCC.

60

Specifications

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Table 5-25 lists the timing requirements of the ADC.

Table 5-25. 12-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

For specified performance of ADC12 linearity parameters with

ADC12PWRMD = 0,

If ADC12PWRMD = 1, the maximum is 1/4 of the value shown

here

Frequency for

f_ADC12CLKspecified

0.45

5.4

MHz

performance

Frequency for

reduced performance

f_ADC12OSCInternal oscillator⁽¹⁾

f_ADC12CLK

Linearity parameters have reduced performance

32.768

4.8

kHz

ADC12DIV = 0, f_ADC12CLK= f_ADC12OSCfrom MODCLK

4

5.4

3.5

MHz

REFON = 0, Internal oscillator, f_ADC12CLK= f_ADC12OSCfrom

MODCLK, ADC12WINC = 0

2.6

t_CONVERT

Conversion time

µs

External f_ADC12CLKfrom ACLK, MCLK, or SMCLK,

ADC12SSEL ≠ 0

(2)

See

Turnon settling time

of the ADC

(3)

t_ADC12ON

See

100

ns

Time ADC must be

t_ADC12OFFoff before can be

turned on again

Note: t_ADC12OFFmust be met to make sure that t_ADC12ONtime

holds.

100

1

All pulse sample mode

(ADC12SHP = 1) and extended

sample mode (ADC12SHP = 0) with

buffered reference

(ADC12VRSEL = 0x1, 0x3, 0x5,

0x7, 0x9, 0xB, 0xD, 0xF)

R_S= 400 Ω, R_I= 4 kΩ,

t_Sample

Sampling time

µs

C_I= 15 pF, C_pext= 8 pF⁽⁴⁾

Extended sample mode

(ADC12SHP = 0) with unbuffered

reference (ADC12VRSEL= 0x0,

0x2, 0x4, 0x6, 0xC, 0xE)

(5)

See

(1) The ADC12OSC is sourced directly from MODOSC in the UCS.

(2) 14 × 1 / f_ADC12CLK. If ADC12WINC = 1 then 15 × 1 / f_ADC12CLK

.

(3) The condition is that the error in a conversion started after t_ADC12ONis less than ±0.5 LSB. The reference and input signal are already

settled.

(4) Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB: t_sample= ln(2ⁿ⁺²) × (R_S+ R_I) × (C_I+ C_pext), where n = ADC

resolution = 12, R_S= external source resistance, C_pext= external parasitic capacitance.

(5) 6 × 1 / f_ADC12CLK

Specifications

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Table 5-26 lists the linearity parameters of the ADC.

Table 5-26. 12-Bit ADC, Linearity Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

With external voltage reference (ADC12VRSEL = 0x2,

0x3, 0x4, 0x14, 0x15),

1.2 V ≤ (V_R+– V_R–) ≤ AV_CC

Integral linearity error (INL) for

differential input

±1.8

LSB

±2.2

E_I

With external voltage reference (ADC12VRSEL = 0x2,

0x3, 0x4, 0x14, 0x15),

1.2 V ≤ (V_R+– V_R–) ≤ AV_CC

Integral linearity error (INL) for

single-ended inputs

With external voltage reference (ADC12VRSEL = 0x2,

0x3, 0x4, 0x14, 0x15),

E_D

E_O

Differential linearity error (DNL)

Offset error^{(1) (2)}

–0.99

+1.0

±1.5

LSB

mV

ADC12VRSEL = 0x1 without TLV calibration,

TLV calibration data can be used to improve the

parameter⁽³⁾

±0.5

With internal voltage reference V_REF= 2.5 V

(ADC12VRSEL = 0x1, 0x7, 0x9, 0xB, or 0xD)

±0.2%

±1.7%

±2.5%

With internal voltage reference V_REF= 1.2 V

(ADC12VRSEL = 0x1, 0x7, 0x9, 0xB, or 0xD)

E_G

Gain error

With external voltage reference without internal buffer

(ADC12VRSEL = 0x2 or 0x4) without TLV calibration,

V_R+= 2.5 V, V_R–= AVSS

±1

±3

LSB

With external voltage reference with internal buffer

(ADC12VRSEL = 0x3), V_R+= 2.5 V, V_R–= AVSS

±2

±0.2%

±27

±1.8%

±2.6%

With internal voltage reference V_REF= 2.5 V

(ADC12VRSEL = 0x1, 0x7, 0x9, 0xB, or 0xD)

With internal voltage reference V_REF= 1.2 V

(ADC12VRSEL = 0x1, 0x7, 0x9, 0xB, or 0xD)

E_T

Total unadjusted error

With external voltage reference without internal buffer

(ADC12VRSEL = 0x2 or 0x4) without TLV calibration,

V_R+= 2.5 V, V_R–= AVSS

±1

±5

LSB

With external voltage reference with internal buffer

(ADC12VRSEL = 0x3), V_R+= 2.5 V, V_R–= AVSS

±28

(1) Offset is measured as the input voltage (at which ADC output transitions from 0 to 1) minus 0.5 LSB.

(2) Offset increases as I_Rdrop increases when V_R–is AVSS.

(3) For details, see the Device Descriptor Table section in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.

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Table 5-27 lists the dynamic performance characteristics of the ADC with an external reference.

Table 5-27. 12-Bit ADC, Dynamic Performance With External Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Resolution Number of no missing code output-code bits

12

bits

Signal-to-noise with differential inputs

SNR

V_R+= 2.5 V, V_R–= AV_SS

71

70

dB

Signal-to-noise with single-ended inputs

V_R+= 2.5 V, V_R–= AV_SS

Effective number of bits with differential inputs⁽¹⁾

Effective number of bits with single-ended inputs⁽¹⁾V_R+= 2.5 V, V_R–= AV_SS

11.4

11.1

ENOB

bits

Reduced performance with f_ADC12CLK

from ACLK LFXT 32.768 kHz,

V_R+= 2.5 V, V_R–= AV_SS

Effective number of bits with 32.768-kHz clock

(reduced performance)⁽¹⁾

10.9

(1) ENOB = (SINAD – 1.76) / 6.02

Table 5-28 lists the dynamic performance characteristics of the ADC with an internal reference.

Table 5-28. 12-Bit ADC, Dynamic Performance With Internal Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Resolution Number of no missing code output-code bits

12

bits

Signal-to-noise with differential inputs

SNR

V_R+= 2.5 V, V_R–= AV_SS

70

69

dB

Signal-to-noise with single-ended inputs

V_R+= 2.5 V, V_R–= AV_SS

Effective number of bits with differential inputs⁽¹⁾

Effective number of bits with single-ended inputs⁽¹⁾V_R+= 2.5 V, V_R–= AV_SS

11.4

11.0

ENOB

bits

Reduced performance with f_ADC12CLK

from ACLK LFXT 32.768 kHz,

V_R+= 2.5 V, V_R–= AV_SS

Effective number of bits with 32.768-kHz clock

(reduced performance)⁽¹⁾

10.9

(1) ENOB = (SINAD – 1.76) / 6.02

Table 5-29 lists the characteristics of the temperature sensor and the V_1/2

.

Table 5-29. 12-Bit ADC, Temperature Sensor and Built-In V_1/2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

ADC12ON = 1, ADC12TCMAP = 1,

T_A= 0°C

V_SENSOR

Temperature sensor voltage^{(1) (2)}

700

2.5

mV

mV/°C

µs

(2)

TC_SENSOR

t_{SENSOR(sample)}

See

ADC12ON = 1, ADC12TCMAP = 1

Sample time required if ADCTCMAP = 1 and

channel (MAX – 1) is selected⁽³⁾

ADC12ON = 1, ADC12TCMAP = 1,

Error of conversion result ≤1 LSB

30

AVCC voltage divider for ADC12BATMAP = 1

on MAX input channel

V_1/2

ADC12ON = 1, ADC12BATMAP = 1

47.5%

50% 52.5%

38 72

I_V1/2

Current for battery monitor during sample time ADC12ON = 1, ADC12BATMAP = 1

µA

µs

Sample time required if ADC12BATMAP = 1

ADC12ON = 1, ADC12BATMAP = 1

and channel MAX is selected⁽⁴⁾

t_{V1/2 (sample)}

1.7

(1) The temperature sensor offset can be as much as ±30°C. TI recommends a single-point calibration to minimize the offset error of the

built-in temperature sensor.

(2) The device descriptor structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference voltage

levels. The sensor voltage can be computed as V_SENSE= TC_SENSOR× (Temperature, °C) + V_SENSOR, where TC_SENSORand V_SENSORcan

be computed from the calibration values for higher accuracy.

(3) The typical equivalent impedance of the sensor is 250 kΩ. The sample time required includes the sensor on-time, t_SENSOR(on)

.

(4) The on-time t_V1/2(on)is included in the sampling time t_V1/2(sample); no additional on time is needed.

Specifications

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Table 5-30 lists the characteristics of the external reference for the ADC.

Table 5-30. 12-Bit ADC, External Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Positive external reference voltage input

VeREF+ or VeREF- based on

ADC12VRSEL bit

V_R+

V_R+> V_R–

1.2

AV_CC

V

Negative external reference voltage input

VeREF+ or VeREF- based on

ADC12VRSEL bit

V_R–

V_R+> V_R–

0

1.2

AV_CC

±10

V

V_R+

V_R–

–

Differential external reference voltage input V_R+> V_R–

1.2

1.2 V ≤ V_eREF+≤ V_AVCC, V_eREF-= 0 V

f_ADC12CLK= 5 MHz, ADC12SHTx = 1h,

ADC12DIF = 0, ADC12PWRMD = 0

I_VeREF+

I_VeREF-

,

Static input current singled-ended input

mode

µA

1.2 V ≤ V_eREF+≤ V_AVCC, V_eREF-= 0 V

f_ADC12CLK= 5 MHz, ADC12SHTx = 8h,

ADC12DIF = 0, ADC12PWRMD = 01

±2.5

±20

±5

1.2 V ≤ V_eREF+≤ V_AVCC, V_eREF-= 0 V

f_ADC12CLK= 5 MHz, ADC12SHTx = 1h,

ADC12DIF = 1, ADC12PWRMD = 0

I_VeREF+

I_VeREF-

Static input current differential input mode

1.2 V ≤ V_eREF+≤ V_AVCC, V_eREF-= 0 V

f_ADC12CLK= 5 MHz, ADC12SHTx = 8h,

ADC12DIF = 1, ADC12PWRMD = 1

I_VeREF+

Peak input current with single-ended input

Peak input current with differential input

0 V ≤ V_eREF+≤ V_AVCC, ADC12DIF = 0

0 V ≤ V_eREF+≤ V_AVCC, ADC12DIF = 1

1.5

3

mA

Capacitance at VeREF+ or VeREF-

terminal

(2)

C_VeREF+/-

See

10

µF

(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance (C_I) is also

the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the

recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.

(2) Connect two decoupling capacitors, 10 µF and 470 nF, from VeREF+ or VeREF– to AVSS to decouple the dynamic current required for

an external reference source if it is used for the ADC12_B. Also see the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family

User's Guide.

950

900

850

800

750

700

650

600

550

500

–40

–20

0

20

40

60

80

Ambient Temperature (°C)

图 5-17. Typical Temperature Sensor Voltage

64

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5.13.11 Reference

Table 5-31 lists the characteristics of the internal reference.

Table 5-31. REF, Built-In Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

2.5 ±1.5%

2.0 ±1.5%

1.2 ±1.8%

MAX UNIT

REFVSEL = {2} for 2.5 V, REFON = 1

REFVSEL = {1} for 2.0 V, REFON = 1

REFVSEL = {0} for 1.2 V, REFON = 1

From 0.1 Hz to 10 Hz, REFVSEL = {0}

2.7 V

2.2 V

1.8 V

Positive built-in reference

voltage output

V_REF+

V

(1)

Noise

RMS noise at VREF

30

130

µV

VREF ADC BUF_INT buffer T_A= 25°C, ADC on, REFVSEL = {0},

offset⁽²⁾

REFON = 1, REFOUT = 0

V_{OS_BUF_INT}

–16

+16

mV

VREF ADC BUF_EXT buffer T_A= 25°C, REFVSEL = {0} , REFOUT = 1,

V_{OS_BUF_EXT}

AV_CC(min)

I_REF+

+16

mV

V

offset⁽³⁾

REFON = 1 or ADC on

REFVSEL = {0} for 1.2 V

REFVSEL = {1} for 2.0 V

REFVSEL = {2} for 2.5 V

1.8

2.2

2.7

AVCC minimum voltage,

Positive built-in reference

active

Operating supply current

into AVCC terminal⁽⁴⁾

REFON = 1

3 V

19

26

µA

ADC ON, REFOUT = 0,

REFVSEL = {0, 1, or 2},

ADC12PWRMD = 0

247

400

ADC ON, REFOUT = 1,

REFVSEL = {0, 1, 2}, ADC12PWRMD = 0

1053

153

1820

240

Operating supply current

into AVCC terminal⁽⁴⁾

I_{REF+_ADC_BUF}

ADC ON, REFOUT = 0,

REFVSEL = {0, 1, 2}, ADC12PWRMD = 1

3 V

µA

ADC ON, REFOUT = 1,

REFVSEL = {0, 1, 2}, ADC12PWRMD = 1

581

1030

1890

ADC OFF, REFON = 1, REFOUT = 1,

REFVSEL = {0, 1, 2}

1105

REFVSEL = {0, 1, 2}, AV_CC= AV_CC(min)for

each reference level,

REFON = REFOUT = 1

VREF maximum load

current, VREF+ terminal

I_O(VREF+)

–1000

+10

REFVSEL = {0, 1, 2},

ΔV_out/ΔI_o

(VREF+)

Load-current regulation,

VREF+ terminal

I_O(VREF+)= +10 µA or –1000 µA,

AV_CC= AV_CC(min)for each reference level,

REFON = REFOUT = 1

1500 µV/mA

Capacitance at VREF+ and

VREF- terminals

C_VREF+/-

REFON = REFOUT = 1

0

100

pF

REFVSEL = {0, 1, 2},

REFON = REFOUT = 1,

T_A= –40°C to 85°C⁽⁵⁾

Temperature coefficient of

built-in reference

TC_REF+

24

50 ppm/K

AV_CC= AV_{CC (min)}to AV_CC(max)

T_A= 25°C, REFVSEL = {0, 1, 2},

REFON = REFOUT = 1

,

Power supply rejection ratio

(DC)

PSRR_DC

100

400

µV/V

Power supply rejection ratio

(AC)

PSRR_AC

t_SETTLE

dAV_CC= 0.1 V at 1 kHz

3.0

40

mV/V

µs

Settling time of reference

voltage⁽⁶⁾

AV_CC= AV_{CC (min)}to AV_CC(max)

REFVSEL = {0, 1, 2}, REFON = 0 → 1

,

80

2

Settling time of ADC

AV_CC= AV_{CC (min)}to AV_CC(max)

REFVSEL = {0, 1, 2}, REFON = 1

,

T_{buf_settle}

0.4

us

reference voltage buffer⁽⁶⁾

(1) Internal reference noise affects ADC performance when ADC uses the internal reference. See Designing With the MSP430FR59xx and

MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external reference.

(2) Buffer offset affects ADC gain error and thus total unadjusted error.

(3) Buffer offset affects ADC gain error and thus total unadjusted error.

(4) The internal reference current is supplied through the AVCC terminal.

(5) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).

(6) The condition is that the error in a conversion started after t_REFONis less than ±0.5 LSB.

Specifications

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5.13.12 Comparator

Table 5-32 lists the characteristics of the comparator.

Table 5-32. Comparator_E

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

CEPWRMD = 00, CEON = 1,

CERSx = 00 (fast)

12

16

CEPWRMD = 01, CEON = 1,

CERSx = 00 (medium)

Comparator operating

10

0.1

0.3

14

µA

0.3

supply current into AVCC,

excludes reference

resistor ladder

I_{AVCC_COMP}

2.2 V, 3.0 V

CEPWRMD = 10, CEON = 1,

CERSx = 00 (slow), T_A= 30°C

CEPWRMD = 10, CEON = 1,

CERSx = 00 (slow), T_A= 85°C

1.3

CEREFLx = 01, CERSx = 10,

REFON = 0, CEON = 1,

CEREFACC = 0

31

16

38

µA

19

Quiescent current of

resistor ladder into AVCC,

including REF module

current

I_{AVCC_COMP_REF}

2.2 V, 3.0 V

CEREFLx = 01, CERSx = 10,

REFON = 0, CEON = 1,

CEREFACC = 1

CERSx = 11, CEREFLx = 01,

CEREFACC = 0

1.8 V

2.2 V

2.7 V

1.8 V

2.2 V

2.7 V

1.152

1.92

2.40

1.10

1.90

2.35

0

1.2

2.0

2.5

1.2

2.0

2.5

1.248

2.08

CERSx = 11, CEREFLx = 10,

CEREFACC = 0

CERSx = 11, CEREFLx = 11,

CEREFACC = 0

2.60

V

V_REF

Reference voltage level

CERSx = 11, CEREFLx = 01,

CEREFACC = 1

1.245

CERSx = 11, CEREFLx = 10,

CEREFACC = 1

2.08

2.60

CERSx = 11, CEREFLx = 11,

CEREFACC = 1

Common-mode input

range

V_IC

V_CC– 1

V

CEPWRMD = 00

CEPWRMD = 01

CEPWRMD = 10

–16

–12

–37

16

12

37

V_OFFSET

Input offset voltage

mV

CEPWRMD = 00 or

CEPWRMD = 01

10

C_IN

Input capacitance

pF

CEPWRMD = 10

ON (switch closed)

OFF (switch open)

10

1

3

kΩ

R_SIN

Series input resistance

50

MΩ

CEPWRMD = 00, CEF = 0,

Overdrive ≥ 20 mV

193

230

5

330

400

15

ns

Propagation delay,

response time

CEPWRMD = 01, CEF = 0,

Overdrive ≥ 20 mV

t_PD

CEPWRMD = 10, CEF = 0,

Overdrive ≥ 20 mV

µs

ns

CEPWRMD = 00 or 01, CEF = 1,

Overdrive ≥ 20 mV, CEFDLY = 00

700

1.0

2.0

4.0

1000

1.9

CEPWRMD = 00 or 01, CEF = 1,

Overdrive ≥ 20 mV, CEFDLY = 01

Propagation delay with

filter active

t_PD,filter

CEPWRMD = 00 or 01, CEF = 1,

Overdrive ≥ 20 mV, CEFDLY = 10

3.7

µs

CEPWRMD = 00 or 01, CEF = 1,

Overdrive ≥ 20 mV, CEFDLY = 11

7.7

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Table 5-32. Comparator_E (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

CEON = 0 → 1, VIN+,

VIN- from pins,

Overdrive ≥ 20 mV,

CEPWRMD = 00

0.9

1.5

CEON = 0 → 1, VIN+,

VIN- from pins,

Overdrive ≥ 20 mV,

CEPWRMD = 01

t_{EN_CMP}

Comparator enable time

0.9

15

1.5

65

µs

CEON = 0 → 1,

VIN+, VIN- from pins,

Overdrive ≥ 20 mV,

CEPWRMD = 10

CEON = 0 → 1, CEREFLX = 10,

CERSx = 10 or 11,

CEREF0 = CEREF1 = 0x0F,

REFON = 0

Comparator and reference

ladder and reference

voltage enable time

t_{EN_CMP_VREF}

t_{EN_CMP_RL}

V_{CE_REF}

120

220

µs

V

CEON = 0 → 1, CEREFLX = 10,

CERSx = 10, REFON = 1,

CEREF0 = CEREF1 = 0x0F

Comparator and reference

ladder enable time

10

30

VIN ×

(n +

0.5)

VIN ×

(n + 1) (n + 1.5)

/ 32 / 32

VIN ×

Reference voltage for a

given tap

VIN = reference into resistor ladder,

n = 0 to 31

/ 32

5.13.13 FRAM

Table 5-33 lists the characteristics of the FRAM.

Table 5-33. FRAM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Read and write endurance

T_J

MIN

10¹⁵

100

40

TYP

MAX UNIT

cycles

25°C

70°C

85°C

t_Retention

Data retention duration

years

10

I_WRITE

I_ERASE

t_WRITE

Current to write into FRAM⁽¹⁾

Erase current⁽²⁾

Write time⁽⁴⁾

I_READ

N/A⁽³⁾

nA

ns

t_READ

NWAITSx = 0

NWAITSx = 1

1 / f_SYSTEM

2 / f_SYSTEM

t_READ

Read time⁽⁵⁾

ns

(1) Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read

current I_READis included in the active mode current consumption, I_AM,FRAM

(2) FRAM does not require a special erase sequence.

(3) N/A = Not applicable

.

(4) Writing into FRAM is as fast as reading.

(5) The maximum read (and write) speed is specified by f_SYSTEMusing the appropriate wait state settings (NWAITSx).

Specifications

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5.13.14 USS

Table 5-34 lists the USS recommended operating conditions.

Table 5-34. USS Recommended Operating Conditions

PARAMETER

TEST CONDITIONS

MIN

2.2

TYP

MAX UNIT

PV_CC

Analog supply voltage at PVCC pins for LDO operation

Analog supply voltage at PVCC pins for USS operation

3.6

V

2.2

Table 5-35 lists the characteristics of the USS LDO.

Table 5-35. USS LDO

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

2.2

TYP

MAX UNIT

V_CC-LDO

V_USS

Analog supply voltage at PVCC pins

USS voltage

3.6

V

0 ≤ I_LOAD≤ I_LOAD,MAX

1.52

1.6

0

1.65

LBHDEL = 0

LBHDEL = 1

LBHDEL = 2

LBHDEL = 3

100

200

300

t_holdoff

Hold off delay on power up

µs

t_time-out

Time-out on transition from OFF to READY

160 +

t_holdoff

Table 5-36 lists the characteristics of the USS crystal.

Table 5-36. USSXTAL

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

N_{phase_osc}Integrated phase noise

f_osc= 4 MHz or 8 MHz, range = 10 kHz to 4 MHz

–74

dBc

FRQ_XTAL

DC_osc

Resonator frequency

Duty cycle

4

8

MHz

35%

65%

f_osc= 4 MHz or 8 MHz, C_L= 18 pF, C_S= 4 pF,

fully settled, ceramic resonator

180

240

I_osc

OSC supply current

Oscillation allowance

µA

f_osc= 4 MHz or 8 MHz, C_L= 12 pF (4 MHz) or

16 pF (8 MHz), C_S= 7 pF, fully settled, crystal resonator

f_osc= 4 MHz, C_L= 18 pF, C_S= 4 pF, ceramic resonator

f_osc= 4 MHz, C_L= 12 pF, C_S= 7 pF, crystal resonator

f_osc= 8 MHz, C_L= 18 pF, C_S= 4 pF, ceramic resonator

f_osc= 8 MHz, C_L= 16 pF, C_S= 7 pF, crystal resonator

f_osc= 4 MHz, crystal resonator

1500

1000

500

350

2.8

A_osc

Ω

4.6

1.9

f_osc= 8 MHz, crystal resonator

1

T_{start_osc}

Start-up time (gate)

ms

f_osc= 4 MHz, ceramic resonator

0.14

0.08

0.17

0.12

f_osc= 8 MHz, ceramic resonator

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Table 5-37 lists the characteristics of the USS HSPLL.

Table 5-37. USS HSPLL

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

4

TYP

MAX UNIT

PLL_CLK_in

PLL_CLK_out

Input clock to HSPLL

Output clock from HSPLL

8

MHz

68

80

Reference clock = PLL_CLK_in,

Sequence: Set USS.CTL.USSPWRUP bit = 1, then

measure the time between PSQ_PLLUP (internal

control signal) is set to 1 and

LOCK_pwr

Lock time from PLL power up

64 cycles

HSPLL.CTL.PLL_LOCK is set to 1

Table 5-38 lists the characteristics of the USS SDHS.

Table 5-38. USS SDHS

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SDHS power domain

supply voltage

V_sdhs

V_sdhs= V_uss

1.52

1.6

1.65

V

Operating supply

current into AVCC and

DVCC

Includes PLL, PGA, SDHS, and DTC,

modulator clock = 80 MHz, output data rate = 8 Msps

I_{sdhs_product}

5.2

mA

f_mod

Modulator clock

68

80

MHz

Frequency at –3-dB

SNR

Modulator clock = 80 MHz, modulator only (no filter is

enabled)

BW_mod

1.5

Bandwidth from 200

kHz to 1.5 MHz, PGA

gain: a gain from the

PGA gain table for the OSR = 20

maximum SNR

Input signal level = 1000 mVpp,

PVCC = 3.0 V, f_mod= 80 MHz,

58.5

57.5

54.5

49

62.5

Bandwidth from 200

kHz to 1.5 MHz, PGA

gain: a gain from the

PGA gain table for the OSR = 20

maximum SNR

Input signal level = 760 mVpp,

PVCC = 2.5 V, f_mod= 80 MHz,

62

57

53

43

Bandwidth from 200

kHz to 1.5 MHz, PGA

gain: a gain from the

PGA gain table for the OSR = 20

maximum SNR

Input signal level = 200 mVpp,

PVCC = 2.5 V, f_mod= 80 MHz,

SNR

Signal-to-noise ratio

dB

Bandwidth from

200kHz to 1.5 MHz,

PGA gain: a gain from PVCC = 2.5 V, f_mod= 80 MHz,

the PGA gain table for OSR = 20

the maximum SNR

Input signal level = 100 mVpp,

Bandwidth from 200

kHz to 1.5 MHz, PGA

gain: a gain from the

Input signal level = 30 mVpp,

PVCC = 2.5 V, f_mod= 80 MHz,

38.5

PGA gain table for the OSR = 20

maximum SNR

TM2 – TM1, AUTOSSDIS = 0, 1% of settled DC level

TM2 – TM1, AUTOSSDIS = 1, 1% of settled DC level

40

8

SDHS settling time

(PGA + modulator)

t_{MOD_Settle}

µs

DROUT_sdhs

Output data rate

Msps

Specifications

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Table 5-39 lists the characteristics of the USS PHY outputs.

Table 5-39. USS PHY Output Stage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

PHY supply voltage

Output impedance of CH0OUT and CH1OUT for

TEST CONDITIONS

MIN

TYP

MAX UNIT

PVCC

R_DSonT

PVCC = V_CC, PVSS = V_SS

2.2

3.6

V

PVCC ≥ 2.5 V

3

Ω

high and low sides (trimmed at 3-V PV_DD

)

Termination impedance of CH0OUT and

CH1OUT toward PVSS (trimmed)

R_Term

DrvM

Ω

High-side to low-side drive mismatch (trimmed)

PVCC ≥ 2.5 V

5%

12.5%

TermM Termination to drive mismatch (trimmed)

PVCC ≥ 2.5 V

f_MAX

Maximum output frequency

PVCC = V_CC(2.5 V to 3.6 V)

PVCC = V_CC

4.5

22

MHz

µF

C_SUPP

R_SUPP

Supply buffering capacitance (low ESR type)

Series resistance to C_SUPP

100

22

PVCC = V_CC

Ω

Table 5-40 lists the characteristics of the USS PHY inputs.

Table 5-40. USS PHY Input Stage, Multiplexer

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

1.8

PVSS –

0.3

V_IN

Input voltage on CH0IN or CH1IN

PVCC = V_CC, PVSS = V_SS

V

Table 5-41 lists the characteristics of the USS PGA.

Table 5-41. USS PGA

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Supply voltage

Gain⁽¹⁾

TEST CONDITIONS

MIN

2.2

–6.5

30

TYP

MAX UNIT

PV_cc

G_N

3.6

V

30.8

dB

V_inr1

V_inr2

Input range

2.2 V ≤ PVCC

2.5 V ≤ PVCC

800 mVpp

1000 mVpp

30

Recommended input

range for maximum

performance

V_inrperf

2.5 V ≤ PVCC

30

800 mVpp

G_tol

Gain tolerance

Full PGA gain range, V_OUT= 600 mV

–1.5

1.5

1.4

dB

Gain drift with

temperature

G_Tdrift

0.0019

dB/℃

G_Vdrift

t_SET

Gain drift with voltage

Gain settling time

Full PGA gain range, V_OUT= 600 mV

Gain setting: from 0 dB to 6 dB, to ±5%

0.15

0.65

dB/V

µs

DC offset (PGA and

SDHS)

DC_offset

DC_drift

Full PGA gain range, measured at SDHS output

5.5

4.7

mV

DC offset drift (PGA

and SDHS)

µV/℃

PGA gain = 0 dB

–41

–37

–19

V_CC= 3 V + 50 mVpp × sin (2π × f_C)

where f_C= 1 MHz, V_IN= ground,

PSRR_AC = 20log(V_OUT/ 50 mV)

AC power supply

rejection ratio

PSRR_AC

PGA gain = 10 dB

PGA gain = 30 dB

dB

(1) See the PGA Gain table in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.

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Table 5-42 lists the characteristics of the USS bias voltage generator.

Table 5-42. USS Bias Voltage Generator

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

EXCBIAS = 0

MIN

TYP

200

MAX

UNIT

EXCBIAS = 1

EXCBIAS = 2

EXCBIAS = 3

BIMP = 0

300

Excitation bias voltage

(coupling capacitors)

V_{exc_bias}

PVCC = V_CC(2.2 V to 3.6 V)

mV

400

600

PVCC = V_CC(2.2 V to 3.6 V)

450

BIMP = 1

850

Impedance of excitation bias

generator

R_VBE

Ω

BIMP = 2

1450

2900

BIMP = 3

PVCC = V_CC(2.2 V to 3.6 V), to 0.1% end value,

R_ET= 200 Ω, C_K+ C_0P= 1 nF, BIMP = 2

t_SBE

Excitation bias settling time

20

µs

PGABIAS = 0

750

800

PGABIAS = 1

PVCC = V_CC(2.2 V to 3.6 V)

PGABIAS = 2

PGA bias voltage (coupling

capacitors)

V_{pga_bias}

mV

900

PGABIAS = 3

950

PVCC = V_CC(2.2 V to 3.6 V)

BIMP = 0

BIMP = 1

BIMP = 2

BIMP = 3

500

900

Impedance of acquisition bias

generator

R_VBA

Ω

1500

2950

PVCC = V_CC(2.2 V to 3.6 V), to 0.1% end value,

R_ET= 200 Ω, C_K+ C_0P= 1 nF, BIMP = 2

t_SBA

Acquisition bias settling time

22

µs

5.13.15 Emulation and Debug

Table 5-43 lists the characteristics of the JTAG and SBW interface.

Table 5-43. JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

V_CC

MIN

TYP

MAX UNIT

100 μA

10 MHz

I_JTAG

Supply current adder when JTAG active (but not clocked)

Spy-Bi-Wire input frequency

2.2 V, 3.0 V

40

f_SBW

0

t_SBW,Low

Spy-Bi-Wire low clock pulse duration

0.04

15

μs

Spy-Bi-Wire enable time (TEST high to acceptance of first clock

edge)⁽¹⁾

t_{SBW, En}

t_SBW,Rst

2.2 V, 3.0 V

110

Spy-Bi-Wire return to normal operation time

TCK input frequency, 4-wire JTAG⁽²⁾

15

0

100

16

2.2 V

3.0 V

f_TCK

MHz

0

16

R_internal

Internal pulldown resistance on TEST

2.2 V, 3.0 V

20

35

50

kΩ

TCLK/MCLK frequency during JTAG access, no FRAM access

f_TCLK

16 MHz

(limited by f_SYSTEM

)

t_{TCLK,Low/High}

f_TCLK,FRAM

TCLK low or high clock pulse duration, no FRAM access

25

4

ns

TCLK/MCLK frequency during JTAG access, including FRAM access

(limited by f_SYSTEMwith no FRAM wait states)

MHz

t_TCLK,FRAM,

Low/High

TCLK low or high clock pulse duration, including FRAM accesses

100

ns

(1) Tools that access the Spy-Bi-Wire and the BSL interfaces must wait for the t_SBW,Entime after the first transition of the TEST/SBWTCK

pin (low to high), before the second transition of the pin (high to low) during the entry sequence.

(2) f_TCKmay be restricted to meet the timing requirements of the module selected.

Specifications

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6 Detailed Description

6.1 Overview

The TI MSP430FR60xx(1) family of ultra-low-power microcontrollers consists of several devices featuring

different sets of peripherals. The architecture, combined with seven low-power modes, is optimized to

achieve extended battery life for example in portable measurement applications. The devices features a

powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code

efficiency.

The device is an MSP430FR6xx family device with Ultrasonic Sensing Solution (USS), Low-Energy

Accelerator (LEA), up to six 16-bit timers, up to six eUSCIs that support UART, SPI, and I²C, a

comparator, a hardware multiplier, an AES accelerator, a 6-channel DMA, an RTC module with alarm

capabilities, up to 76 I/O pins, and a high-performance 12-bit ADC. The MSP430FR60xx(1) devices also

include an LCD module with contrast control for displays with up to 264 segments.

6.2 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All

operations, other than program-flow instructions, are performed as register operations in conjunction with

seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-

register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and

constant generator, respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses. The peripherals can be

managed with all instructions.

The instruction set consists of the original 51 instructions with three formats and seven address modes

and additional instructions for the expanded address range. Each instruction can operate on word and

byte data.

6.3 Ultrasonic Sensing Solution (USS) Module

The USS module provides a high-precision ultrasonic sensing solution. The USS module is a

sophisticated system that consists of six submodules:

•

UUPS (universal USS power supply)

HSPLL (high-speed PLL) with oscillator

ASQ (acquisition sequencer)

PHY (physical interface)

PPG (programmable pulse generator) with low-output-impedance driver

PGA (programmable gain amplifier)

SDHS (sigma-delta high-speed ADC) with DTC (data transfer controller)

The submodules have different roles, and together they enable high-precision data acquisition in

ultrasonic applications. See the dedicated chapter for each submodule in the MSP430FR58xx,

MSP430FR59xx, and MSP430FR6xx Family User's Guide.

The USS module performs complete measurement sequence without CPU involvement to achieve ultra-

low power consumption for ultrasonic metrology. 图 6-1 shows the USS subsystem block diagram. The

USS module has dedicated I/O pins without secondary functions. See the Ultrasonic Sensing Solution

(USS) chapter in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for

details.

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USS Module

USSXT

USSXTOUT

USSXTIN

USSXT_BOUT

MSP430FRxxxx

SAPH

CH0_OUT

CH1_OUT

OSC

PHY

ASQ

PPG

PVSS

PLL_CLK

PLL

PVCC

PVSS

V_OUT

UUPS

HSPLL

SDHS

RAM

(Shared with LEA)

CH0_IN

CH1_IN

PGA

DTC

MOD

Filter

图 6-1. USS Subsystem Block Diagram

6.4 Low-Energy Accelerator (LEA) for Signal Processing

The LEA is a hardware engine designed for operations that involve vector-based signal processing, such

as FIR, IIR, and FFT. The LEA offers fast performance and low energy consumption when performing

vector-based digital signal processing computations. For performance benchmarks comparing LEA to

using the CPU or other processors, see Benchmarking the Signal Processing Capabilities of the Low-

Energy Accelerator.

The LEA requires MCLK to be operational; therefore, LEA operates only in active mode or LPM0. While

the LEA is running, the LEA data operations are performed on a shared 4KB of RAM out of the 8KB of

total RAM (see 表 6-47). This shared RAM can also be used by the regular application. The MSP CPU

and the LEA can run simultaneously and independently unless they access the same system RAM.

Direct access to LEA registers is not supported, and TI offers the optimized Digital Signal Processing

(DSP) Library for MSP Microcontrollers for the operations that the LEA module supports.

Detailed Description

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6.5.1 Peripherals in Low-Power Modes

Peripherals can be in different states that affect the achievable power modes of the device. The states

depend on the operational modes of the peripherals (see 表 6-2). The states are:

•

A peripheral is in a "high-frequency state" if it requires or uses a clock with a "high" frequency of more

than 50 kHz.

A peripheral is in a "low-frequency state" if it requires or uses a clock with a "low" frequency of 50 kHz

or less.

A peripheral is in an "unclocked state" if it does not require or use an internal clock.

If the CPU requests a power mode that does not support the current state of all active peripherals, the

device does not enter the requested power mode, but it does enter a power mode that still supports the

current state of the peripherals, except if an external clock is used. If an external clock is used, the

application must use the correct frequency range for the requested power mode.

表 6-2. Peripheral States

PERIPHERAL

WDT

DMA⁽⁴⁾

RTC_C

LCD_C

IN HIGH-FREQUENCY STATE⁽¹⁾

Clocked by SMCLK

Not applicable

IN LOW-FREQUENCY STATE⁽²⁾

Clocked by ACLK

IN UNCLOCKED STATE⁽³⁾

Not applicable

Waiting for a trigger

Not applicable

Clocked by LFXT

Not applicable

Clocked by ACLK or VLOCLK

Not applicable

Clocked by SMCLK or

clocked by external clock >50 kHz

Clocked by ACLK or

clocked by external clock ≤50 kHz

Timer_A, TAx

Timer_B, TBx

Clocked by external clock ≤50 kHz

Waiting for first edge of START bit

Not applicable

Clocked by SMCLK or

clocked by external clock >50 kHz

Clocked by ACLK or

clocked by external clock ≤50 kHz

eUSCI_Ax in

UART mode

Clocked by SMCLK

Clocked by ACLK

eUSCI_Ax in SPI

master mode

eUSCI_Ax in SPI

slave mode

eUSCI_Bx in I²C

master mode

Clocked by external clock >50 kHz

Clocked by external clock ≤50 kHz

Not applicable

Clocked by SMCLK or

clocked by external clock >50 kHz

Clocked by ACLK or

clocked by external clock ≤50 kHz

eUSCI_Bx in I²C

slave mode

Waiting for START condition or

clocked by external clock ≤50 kHz

Clocked by external clock >50 kHz

Clocked by SMCLK

Clocked by external clock ≤50 kHz

Clocked by ACLK

eUSCI_Bx in SPI

master mode

Not applicable

eUSCI_Bx in SPI

slave mode

Clocked by external clock >50 kHz

Clocked by external clock ≤50 kHz

ADC12_B

REF_A

COMP_E

CRC⁽⁵⁾

MPY⁽⁵⁾

AES⁽⁵⁾

Clocked by SMCLK or by MODOSC

Not applicable

Clocked by ACLK

Not applicable

Waiting for a trigger

Always

Not applicable

Always

Not applicable

(1) Peripherals are in a state that requires or uses a clock with a "high" frequency of more than 50 kHz

(2) Peripherals are in a state that requires or uses a clock with a "low" frequency of 50 kHz or less.

(3) Peripherals are in a state that does not require or does not use an internal clock.

(4) The DMA always transfers data in active mode but can wait for a trigger in any low-power mode. A DMA trigger during a low-power

mode causes a temporary transition into active mode for the time of the transfer.

(5) This peripheral operates during active mode only and will delay the transition into a low-power mode until its operation is completed.

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6.5.2 Idle Currents of Peripherals in LPM3 and LPM4

Most peripherals can be operational in LPM3 if clocked by ACLK. Some modules are operational in LPM4,

because they do not require a clock to operate (for example, the comparator). Activating a peripheral in

LPM3 or LPM4 increases the current consumption due to its active supply current contribution but also

due to an additional idle current. To reduce the idle current adder, certain peripherals are grouped

together. To achieve optimal current consumption, use modules within one group and limit the number of

groups with active modules. 表 6-3 lists the peripheral groups. Modules not listed in this table are either

already included in the standard LPM3 current consumption or cannot be used in LPM3 or LPM4.

The idle current adder is very small at room temperature (25°C) but increases at high temperatures

(85°C); see the I_IDLEcurrent parameters in for details.

表 6-3. Peripheral Groups

GROUP A

Timer TA1

Timer TA2

Timer TB0

eUSCI_A0

eUSCI_A1

eUSCI_B0

GROUP B

Timer TA0

Timer TA3

Comparator

ADC12_B

REF_A

GROUP C

Timer TA4

eUSCI_A2

eUSCI_A3

eUSCI_B1

LCD_C

6.6 Interrupt Vector Table and Signatures

The interrupt vectors, the power-up start address, and signatures are in the address range 0FFFFh to

0FF80h. 图 6-2 summarizes the content of this address range.

0FFFFh

Reset Vector

BSL Password

Interrupt

Vectors

0FFE0h

JTAG Password

Reserved

0FF88h

0FF80h

Signatures

图 6-2. Interrupt Vectors, Signatures and Passwords

The power-up start address or reset vector is at 0FFFFh to 0FFFEh. It contains the 16-bit address pointing

to the start address of the application program.

The interrupt vectors start at 0FFFDh and extend to lower addresses. Each vector contains the 16-bit

address of the appropriate interrupt-handler instruction sequence. 表 6-4 shows the device-specific

interrupt vector locations.

The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as BSL password (if

enabled by the corresponding signature).

Detailed Description

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The signatures start at 0FF80h and extend to higher addresses. Signatures are evaluated during device

start-up. 表 6-5 shows the device-specific signature locations.

A JTAG password can be programmed starting from address 0FF88h and extending to higher addresses.

The password can extend into the interrupt vector locations using the interrupt vector addresses as

additional bits for the password. The length of the JTAG password depends on the JTAG signature.

See the chapter System Resets, Interrupts, and Operating Modes, System Control Module (SYS) in the

MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for details.

表 6-4. Interrupt Sources, Flags, and Vectors

SYSTEM

INTERRUPT

WORD

ADDRESS

INTERRUPT SOURCE

INTERRUPT FLAG

PRIORITY

System Reset

Power up, brownout, supply

supervisor

SVSHIFG

PMMRSTIFG

External reset RST

Watchdog time-out (watchdog

mode)

WDT, FRCTL MPU, CS,

PMM password violation

FRAM uncorrectable bit error

detection

WDTIFG

WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW

UBDIFG

MPUSEG1IFG, MPUSEG2IFG, MPUSEG3IFG

PMMPORIFG, PMMBORIFG

(SYSRSTIV)^{(1) (2)}

Reset

0FFFEh

Highest

MPU segment violation

Software POR, BOR

System NMI

Vacant memory access

JTAG mailbox

FRAM access time error

FRAM write protection error

FRAM bit error detection

MPU segment violation

VMAIFG

JMBINIFG, JMBOUTIFG

ACCTEIFG, WPIFG

(Non)maskable

0FFFCh

0FFFAh

CBDIFG, UBDIFG

MPUSEG1IFG, MPUSEG2IFG, MPUSEG3IFG

(SYSSNIV)^{(1) (3)}

User NMI

External NMI

Oscillator fault

NMIIFG, OFIFG

DACCESSIFG

(SYSUNIV)^{(1) (3)}

LEA RAM access conflict

CEIFG, CEIIFG

(CEIV)⁽¹⁾

Comparator_E

TB0

Maskable

0FFF8h

0FFF6h

TB0CCR0.CCIFG

TB0CCR1.CCIFG to TB0CCR6.CCIFG,

TB0CTL.TBIFG

TB0

Maskable

0FFF4h

0FFF2h

(TB0IV)⁽¹⁾

Watchdog timer (interval timer

mode)

WDTIFG

UCA0IFG: UCRXIFG, UCTXIFG (SPI mode)

UCA0IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG,

UCTXIFG (UART mode)

eUSCI_A0 receive or transmit

Maskable

0FFF0h

0FFEEh

(UCA0IV)⁽¹⁾

UCB0IFG: UCRXIFG, UCTXIFG (SPI mode)

UCB0IFG: UCALIFG, UCNACKIFG, UCSTTIFG,

UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,

UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,

UCTXIFG3, UCCNTIFG, UCBIT9IFG (I²C mode)

(UCB0IV)⁽¹⁾

eUSCI_B0 receive or transmit

ADC12IFG0 to ADC12IFG31

ADC12LOIFG, ADC12INIFG, ADC12HIIFG,

ADC12RDYIFG, ADC21OVIFG, ADC12TOVIFG

(ADC12IV)^{(1) (4)}

ADC12_B

TA0

Maskable

0FFECh

0FFEAh

TA0CCR0.CCIFG

(1) Multiple source flags

(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space.

(3) (Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot disable it.

(4) Only on devices with ADC, otherwise reserved.

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表 6-4. Interrupt Sources, Flags, and Vectors (continued)

SYSTEM

INTERRUPT

WORD

ADDRESS

INTERRUPT SOURCE

INTERRUPT FLAG

PRIORITY

TA0CCR1.CCIFG, TA0CCR2.CCIFG,

TA0CTL.TAIFG

TA0

Maskable

0FFE8h

0FFE6h

(TA0IV)⁽¹⁾

UCA1IFG: UCRXIFG, UCTXIFG (SPI mode)

UCA1IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG,

UCTXIFG (UART mode)

eUSCI_A1 receive or transmit

Maskable

(UCA1IV)⁽¹⁾

DMA0CTL.DMAIFG, DMA1CTL.DMAIFG,

DMA2CTL.DMAIFG

DMA

TA1

Maskable

0FFE4h

0FFE2h

0FFE0h

(DMAIV)⁽¹⁾

TA1CCR0.CCIFG

TA1CCR1.CCIFG, TA1CCR2.CCIFG,

TA1CTL.TAIFG

(TA1IV)⁽¹⁾

P1IFG.0 to P1IFG.7

(P1IV)⁽¹⁾

I/O port P1

TA2

Maskable

0FFDEh

0FFDCh

TA2CCR0.CCIFG

TA2CCR1.CCIFG

TA2CTL.TAIFG

(TA2IV)⁽¹⁾

TA2

Maskable

0FFDAh

P2IFG.0 to P2IFG.7

(P2IV)⁽¹⁾

I/O port P2

TA3

Maskable

0FFD8h

0FFD6h

TA3CCR0.CCIFG

TA3CCR1.CCIFG

TA3CTL.TAIFG

(TA3IV)⁽¹⁾

TA3

Maskable

0FFD4h

0FFD2h

P3IFG.0 to P3IFG.7

(P3IV)⁽¹⁾

I/O port P3

P4IFG.0 to P4IFG.2

(P4IV)⁽¹⁾

LCD_C Interrupt Flags (LCDCIV)⁽¹⁾

I/O port P4

LCD_C

Maskable

0FFD0h

0FFCEh

RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG,

RT1PSIFG, RTCOFIFG

RTC_C

Maskable

0FFCCh

(RTCIV)⁽¹⁾

AES

TA4

AESRDYIFG

Maskable

0FFCAh

0FFC8h

TA4CCR0.CCIFG

TA4CCR1.CCIFG

TA4CTL.TAIFG

(TA4IV)⁽¹⁾

TA4

Maskable

0FFC6h

P5IFG.0 to P5IFG.2

(P5IV)⁽¹⁾

I/O port P5

I/O port P6

Maskable

0FFC4h

0FFC2h

P6IFG.0 to P6IFG.2

(P6IV)⁽¹⁾

UCA2IFG: UCRXIFG, UCTXIFG (SPI mode)

UCA2IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG,

UCTXIFG (UART mode)

eUSCI_A2 receive or transmit

eUSCI_A3 receive or transmit

Maskable

0FFC0h

0FFBEh

(UCA2IV)⁽¹⁾

UCA3IFG: UCRXIFG, UCTXIFG (SPI mode)

UCA3IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG,

UCTXIFG (UART mode)

(UCA3IV)⁽¹⁾

UCB1IFG: UCRXIFG, UCTXIFG (SPI mode)

UCB1IFG: UCALIFG, UCNACKIFG, UCSTTIFG,

UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,

UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,

UCTXIFG3, UCCNTIFG, UCBIT9IFG (I²C mode)

(UCB1IV)⁽¹⁾

eUSCI_B1 receive or transmit

Maskable

0FFBCh

Detailed Description

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PRIORITY

表 6-4. Interrupt Sources, Flags, and Vectors (continued)

SYSTEM

INTERRUPT

WORD

ADDRESS

INTERRUPT SOURCE

I/O Port P7

I/O Port P8

I/O Port P9

LEA

INTERRUPT FLAG

P7IFG.0 to P7IFG.2

(P7IV)⁽¹⁾

Maskable

0FFBAh

0FFB8h

0FFB6h

0FFB4h

0FFB2h

0FFB0h

0FFAEh

P8IFG.0 to P8IFG.2

(P8IV)⁽¹⁾

P9IFG.0 to P9IFG.2

(P9IV)⁽¹⁾

CMDIFG, SDIIFG, OORIFG, TIFG, COVLIFG

(LEAIV)⁽¹⁾

PTMOUT, PREQIG

(IIDX)⁽¹⁾

UUPS

PLLUNLOCK

(IIDX)⁽¹⁾

HSPLL

DATAERR, TAMTO, SEQDN, PNGDN

(IIDX)⁽¹⁾

SAPH

OVF, ACQDONE, SSTRG, DTRDY, WINHI,

SDHS

WINLO

Maskable

0FFACh

Lowest

(IIDX)⁽¹⁾

表 6-5. Signatures

SIGNATURE

IP Encapsulation Signature2

IP Encapsulation Signature1⁽¹⁾

BSL Signature2

WORD ADDRESS

0FF8Ah

0FF88h

0FF86h

BSL Signature1

0FF84h

JTAG Signature2

0FF82h

JTAG Signature1

0FF80h

(1) Must not contain 0AAAAh if used as the JTAG password.

6.7 Bootloader (BSL)

The BSL can program the FRAM or RAM using a UART serial interface (FRxxxx devices) or an I²C

interface (FRxxxx1 devices). Access to the device memory through the BSL is protected by an user-

defined password. 表 6-6 lists the pins that are required for use of the BSL. BSL entry requires a specific

entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For a complete description of the

features of the BSL and its implementation, see the MSP430 FRAM Device Bootloader (BSL) User's

Guide. More information on the BSL can be found at www.ti.com/tool/mspbsl.

表 6-6. BSL Pin Requirements and Functions

DEVICE SIGNAL

BSL FUNCTION

Entry sequence signal

RST/NMI/SBWTDIO

TEST/SBWTCK

P2.0

Entry sequence signal

Devices with UART BSL (FRxxxx): Data transmit

Devices with UART BSL (FRxxxx): Data receive

Devices with I²C BSL (FRxxxx1): Data

Devices with I²C BSL (FRxxxx1): Clock

Power supply

P2.1

P1.6

P1.7

VCC

VSS

Ground supply

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6.8 JTAG Operation

6.8.1 JTAG Standard Interface

The MSP family supports the standard JTAG interface, which requires four signals for sending and

receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to

enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with

MSP development tools and device programmers. 表 6-7 lists the JTAG pin requirements. For further

details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools

User's Guide. For a complete description of the features of the JTAG interface and its implementation, see

MSP430 Programming With the JTAG Interface.

表 6-7. JTAG Pin Requirements and Functions

DEVICE SIGNAL

PJ.3/TCK

DIRECTION⁽¹⁾

FUNCTION

JTAG clock input

JTAG state control

JTAG data input, TCLK input

JTAG data output

Enable JTAG pins

External reset

IN

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

IN

OUT

IN

TEST/SBWTCK

RST/NMI/SBWTDIO

DVCC

IN

N/A

Power supply

DVSS

Ground supply

(1) N/A = not applicable

6.8.2 Spy-Bi-Wire (SBW) Interface

In addition to the standard JTAG interface, the MSP family supports the 2-wire SBW interface. SBW can

be used to interface with MSP development tools and device programmers. 表 6-8 lists the SBW interface

pin requirements. For further details on interfacing to development tools and device programmers, see the

MSP430 Hardware Tools User's Guide. For a complete description of the features of the JTAG interface

and its implementation, see MSP430 Programming With the JTAG Interface.

表 6-8. SBW Pin Requirements and Functions

DEVICE SIGNAL

TEST/SBWTCK

RST/NMI/SBWTDIO

DVCC

DIRECTION⁽¹⁾

FUNCTION

Spy-Bi-Wire clock input

Spy-Bi-Wire data input and output

Power supply

IN

IN, OUT

N/A

DVSS

N/A

Ground supply

(1) N/A = not applicable

Detailed Description

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6.9 FRAM Controller A (FRCTL_A)

The FRAM can be programmed through the JTAG port, SBW, the BSL, or in-system by the CPU.

Features of the FRAM include:

•

Ultra-low-power ultra-fast-write nonvolatile memory

Byte and word access capability

Programmable wait state generation

Error correction coding (ECC)

注

Wait States

For MCLK frequencies > 8 MHz, wait states must be configured following the flow described

in the "Wait State Control" section of the FRAM Controller A (FRCTRL_A) chapter in the

MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.

For important software design information regarding FRAM including but not limited to partitioning the

memory layout according to application-specific code, constant, and data space requirements, the use of

FRAM to optimize application energy consumption, and the use of the Memory Protection Unit (MPU) to

maximize application robustness by protecting the program code against unintended write accesses, see

MSP430™ FRAM Technology – How To and Best Practices.

6.10 RAM

The RAM is made up of three sectors: Sector 0 = 2KB, Sector 1 = 2KB, Sector 2 = 4KB (shared with

LEA). Each sector can be individually powered down in LPM3 and LPM4 to save leakage. All data in the

sector is lost when a sector is powered down.

6.11 Tiny RAM

Tiny RAM is 22 bytes of RAM in addition to the complete RAM (see 表 6-47). This memory is always

available, even in LPM3 and LPM4, while the complete RAM can be powered down in LPM3 and LPM4.

Tiny RAM can be used to hold data or a very small stack when the complete RAM is powered down in

LPM3 and LPM4. No memory is available in LPMx.5.

6.12 Memory Protection Unit (MPU) Including IP Encapsulation

The FRAM can be protected by the MPU from inadvertent CPU execution, read access, or write access.

Features of the MPU include:

•

IP encapsulation with programmable boundaries in steps of 1KB (prevents reads from outside the

application; for example, through JTAG or by non-IP software).

•

Main memory partitioning is programmable up to three segments in steps of 1KB.

Access rights of each segment can be individually selected (main and information memory).

Access violation flags with interrupt capability for easy servicing of access violations.

82

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6.13 Peripherals

Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be

controlled using all instructions. For complete module descriptions, see the MSP430FR58xx,

MSP430FR59xx, and MSP430FR6xx Family User's Guide.

6.13.1 Digital I/O

Up to ten 8-bit I/O ports are implemented:

•

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt conditions is possible.

Programmable pullup or pulldown on all ports.

Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input is available for all pins of ports P1 to

P9.

•

Read and write access to port control registers is supported by all instructions.

Ports P1 and P2 (PA), P3 and P4 (PB), P5 and P6 (PC), P7 and P8 (PD), or P9 (PE) can be accessed

byte-wise or word-wise in pairs.

•

No cross currents during start-up.

注

Configuration of Digital I/Os After BOR Reset

To prevent any cross currents during start-up of the device, all port pins are high-impedance

with Schmitt triggers and their module functions disabled. To enable the I/O functionality after

a BOR reset, the ports must be configured first and then the LOCKLPM5 bit must be cleared.

For details, see the Configuration After Reset section of the Digital I/O chapter in the

MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.

6.13.2 Oscillator and Clock System (CS)

The clock system includes support for a 32-kHz watch-crystal oscillator XT1 (LF), an internal very-low-

power low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a

high-frequency crystal oscillator XT2 (HF). The clock system module is designed to meet the requirements

of both low system cost and low power consumption. A fail-safe mechanism exists for all crystal sources.

The clock system module provides the following clock signals:

•

Auxiliary clock (ACLK). ACLK can be sourced from a 32-kHz watch crystal (LFXT1), the internal VLO,

or a digital external low-frequency (<50-kHz) clock source.

•

Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced from a high-frequency

crystal (HFXT2), the internal DCO, a 32-kHz watch crystal (LFXT1), the internal VLO, or a digital

external clock source.

•

Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be

sourced by same sources made available to MCLK.

6.13.3 Power-Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device . The PMM

also includes supply voltage supervisor (SVS) and brownout protection. The brownout circuit provides the

proper internal reset signal to the device during power on and power off. The SVS circuitry detects if the

supply voltage drops below a safe level and below a user-selectable level. SVS circuitry is available on the

primary and core supplies.

Detailed Description

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6.13.4 Hardware Multiplier (MPY)

The multiplication operation is supported by a dedicated peripheral module. The module performs

operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed multiplication, unsigned

multiplication, signed multiply-and-accumulate, and unsigned multiply-and-accumulate operations.

6.13.5 Real-Time Clock (RTC_C)

The RTC_C module contains an integrated real-time clock (RTC) with the following features:

•

Calendar mode with leap year correction

General-purpose counter mode

The internal calendar compensates for months with fewer than 31 days and includes leap year correction.

The RTC_C also supports flexible alarm functions and offset-calibration hardware. RTC operation is

available in LPM3.5 modes to minimize power consumption.

6.13.6 Measurement Test Interface (MTIF)

The MTIF module provides a simple pulse-based test interface that is used to implement consumption

monitoring of "legal relevant data" with high integrity. MTIF consists of the a pulse generator, a pulse

counter, and a pulse interface. MTIF has following features:

•

Independent passwords for generator counter and pulse interface

Pulse rates up to 1016 pulses per second (p/s)

Pulse frame duration from 1/16 s to 16 s

Count capacity up to 65535 (16 bit)

Operating in LPM3.5 with 200 nA

2-pin interface with MTIF_OUT_IN and MTIF_PIN_EN

6.13.7 Watchdog Timer (WDT_A)

The primary function of the WDT_A module is to perform a controlled system restart if a software problem

occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not

needed in an application, the module can be configured as an interval timer and can generate interrupts at

selected time intervals. 表 6-9 lists the clocks that can source the WDT_A module.

表 6-9. WDT_A Clocks

NORMAL OPERATION

WDTSSEL

(WATCHDOG AND INTERVAL TIMER MODE)

00

01

10

11

SMCLK

ACLK

VLOCLK

LFMODCLK

6.13.8 System Module (SYS)

The SYS module manages many system functions within the device. These functions include power-on

reset (POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt

vector generators, bootloader (BSL) entry mechanisms, and configuration management (device

descriptors). The SYS module also includes a data exchange mechanism through JTAG called a JTAG

mailbox that can be used in the application. 表 6-10 lists the SYS module interrupt vector registers.

84

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表 6-10. System Module Interrupt Vector Registers

INTERRUPT VECTOR

ADDRESS

INTERRUPT EVENT

VALUE

PRIORITY

REGISTER

No interrupt pending

Brownout (BOR)

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

18h

1Ah

1Ch

1Eh

20h

22h

24h

Highest

RSTIFG RST/NMI (BOR)

PMMSWBOR software BOR (BOR)

LPMx.5 wakeup (BOR)

Security violation (BOR)

Reserved

SVSHIFG SVSH event (BOR)

Reserved

PMMSWPOR software POR (POR)

WDTIFG watchdog time-out (PUC)

WDTPW password violation (PUC)

FRCTLPW password violation (PUC)

Uncorrectable FRAM bit error detection (PUC)

Peripheral area fetch (PUC)

PMMPW PMM password violation (PUC)

MPUPW MPU password violation (PUC)

CSPW CS password violation (PUC)

SYSRSTIV, System Reset

019Eh

MPUSEGIPIFG encapsulated IP memory segment violation

(PUC)

26h

Reserved

MPUSEG1IFG segment 1 memory violation (PUC)

MPUSEG2IFG segment 2 memory violation (PUC)

MPUSEG3IFG segment 3 memory violation (PUC)

Reserved

28h

2Ah

2Ch

2Eh

30h to 3Eh

00h

Lowest

Highest

No interrupt pending

Reserved

02h

Uncorrectable FRAM bit error detection

FRAM access time error

04h

06h

MPUSEGIPIFG encapsulated IP memory segment violation

Reserved

08h

0Ah

0Ch

0Eh

10h

MPUSEG1IFG segment 1 memory violation

MPUSEG2IFG segment 2 memory violation

MPUSEG3IFG segment 3 memory violation

VMAIFG vacant memory access

JMBINIFG JTAG mailbox input

JMBOUTIFG JTAG mailbox output

Correctable FRAM bit error detection

FRAM Write Protection Detection

LEA time-out fault

SYSSNIV, System NMI

019Ch

12h

14h

16h

18h

1Ah

1Ch

1Eh

LEA command fault

Lowest

Detailed Description

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表 6-10. System Module Interrupt Vector Registers (continued)

INTERRUPT VECTOR

REGISTER

ADDRESS

INTERRUPT EVENT

VALUE

PRIORITY

No interrupt pending

NMIIFG NMI pin

OFIFG oscillator fault

DACCESSIFG

Reserved

00h

02h

Highest

04h

SYSUNIV, User NMI

019Ah

06h

08h

Reserved

0Ah to 1Eh

Lowest

6.13.9 DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU

intervention. For example, the DMA controller can be used to move data from the ADC12_B conversion

memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA

controller reduces system power consumption by allowing the CPU to remain in sleep mode, without

having to awaken to move data to or from a peripheral. 表 6-11 lists the available triggers for the DMA.

表 6-11. DMA Trigger Assignments⁽¹⁾

TRIGGER

CHANNEL 0

DMAREQ

CHANNEL 1

DMAREQ

CHANNEL 2

DMAREQ

CHANNEL 3

DMAREQ

CHANNEL 4

DMAREQ

CHANNEL 5

DMAREQ

0

1

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA3CCR0 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

TA4CCR0 CCIFG

Reserved

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA3CCR0 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

TA4CCR0 CCIFG

Reserved

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA3CCR0 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

TA4CCR0 CCIFG

Reserved

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA3CCR0 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

TA4CCR0 CCIFG

Reserved

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA3CCR0 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

TA4CCR0 CCIFG

Reserved

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA3CCR0 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

TA4CCR0 CCIFG

Reserved

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

AES Trigger 0

AES Trigger 1

AES Trigger 2

UCA0RXIFG

AES Trigger 0

AES Trigger 1

AES Trigger 2

UCA0RXIFG

AES Trigger 0

AES Trigger 1

AES Trigger 2

UCA0RXIFG

AES Trigger 0

AES Trigger 1

AES Trigger 2

UCA2RXIFG

AES Trigger 0

AES Trigger 1

AES Trigger 2

UCA2RXIFG

AES Trigger 0

AES Trigger 1

AES Trigger 2

UCA2RXIFG

UCA0TXIFG

UCA2TXIFG

UCA1RXIFG

UCA3RXIFG

UCA1TXIFG

UCA3TXIFG

UCB0RXIFG (SPI)

UCB0RXIFG0 (I²C)

UCB0RXIFG (SPI)

UCB0RXIFG0 (I²C)

UCB0RXIFG (SPI)

UCB0RXIFG0 (I²C)

UCB1RXIFG (SPI)

UCB1RXIFG0 (I²C)

UCB1RXIFG (SPI)

UCB1RXIFG0 (I²C)

UCB1RXIFG (SPI)

UCB1RXIFG0 (I²C)

18

19

UCB0TXIFG (SPI)

UCB0TXIFG0 (I²C)

UCB0TXIFG (SPI)

UCB0TXIFG0 (I²C)

UCB0TXIFG (SPI)

UCB0TXIFG0 (I²C)

UCB1TXIFG (SPI)

UCB1TXIFG0 (I²C)

UCB1TXIFG (SPI)

UCB1TXIFG0 (I²C)

UCB1TXIFG (SPI)

UCB1TXIFG0 (I²C)

UCB0RXIFG1 (I²C)

UCB0TXIFG1 (I²C)

UCB0RXIFG2 (I²C)

UCB0TXIFG2 (I²C)

UCB0RXIFG3 (I²C)

UCB0TXIFG3 (I²C)

UCB0RXIFG1 (I²C)

UCB0TXIFG1 (I²C)

UCB0RXIFG2 (I²C)

UCB0TXIFG2 (I²C)

UCB0RXIFG3 (I²C)

UCB0TXIFG3 (I²C)

UCB0RXIFG1 (I²C)

UCB0TXIFG1 (I²C)

UCB0RXIFG2 (I²C)

UCB0TXIFG2 (I²C)

UCB0RXIFG3 (I²C)

UCB0TXIFG3 (I²C)

UCB1RXIFG1 (I²C)

UCB1TXIFG1 (I²C)

UCB1RXIFG2 (I²C)

UCB1TXIFG2 (I²C)

UCB1RXIFG3 (I²C)

UCB1TXIFG3 (I²C)

UCB1RXIFG1 (I²C)

UCB1TXIFG1 (I²C)

UCB1RXIFG2 (I²C)

UCB1TXIFG2 (I²C)

UCB1RXIFG3 (I²C)

UCB1TXIFG3 (I²C)

UCB1RXIFG1 (I²C)

UCB1TXIFG1 (I²C)

UCB1RXIFG2 (I²C)

UCB1TXIFG2 (I²C)

UCB1RXIFG3 (I²C)

UCB1TXIFG3 (I²C)

20

21

22

23

24

25

ADC12 end of

conversion

ADC12 end of

conversion

ADC12 end of

conversion

ADC12 end of

conversion

ADC12 end of

conversion

ADC12 end of

conversion

26

27

28

29

LEA ready

Reserved

MPY ready

LEA ready

Reserved

MPY ready

LEA ready

Reserved

MPY ready

LEA ready

Reserved

MPY ready

LEA ready

Reserved

MPY ready

LEA ready

Reserved

MPY ready

(1) If a reserved trigger source is selected, no trigger is generated.

86 Detailed Description

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表 6-11. DMA Trigger Assignments⁽¹⁾(continued)

TRIGGER

CHANNEL 0

DMA2IFG

DMAE0

CHANNEL 1

DMA0IFG

DMAE0

CHANNEL 2

DMA1IFG

DMAE0

CHANNEL 3

DMA5IFG

DMAE0

CHANNEL 4

DMA3IFG

DMAE0

CHANNEL 5

DMA4IFG

DMAE0

30

31

6.13.10 Enhanced Universal Serial Communication Interface (eUSCI)

The eUSCI modules are used for serial data communication. The eUSCI module supports synchronous

communication protocols such as SPI (3- or 4-pin) and I²C, and asynchronous communication protocols

such as UART, enhanced UART with automatic baud-rate detection, and IrDA.

The eUSCI_A0, eUSCI_A1, eUSCI_A2, and eUSCI_A3 modules support SPI (3- or 4-pin), UART,

enhanced UART, and IrDA.

The eUSCI_B0 and eUSCI_B1 modules support SPI (3- or 4-pin) and I²C.

Four eUSCI_A modules and two eUSCI_B modules are implemented.

6.13.11 TA0, TA1, and TA4

TA0, TA1, and TA4 are 16-bit timers and counters (Timer_A type) with three (TA0 and TA1) or two (TA4)

capture/compare registers each. Each timer can support multiple captures or compares, PWM outputs,

and interval timing (see 表 6-12, 表 6-13, and 表 6-14). Each timer has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each capture/compare

register.

表 6-12. TA0 Signal Connections

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

DEVICE INPUT

SIGNAL

MODULE INPUT

SIGNAL

MODULE

BLOCK

INPUT PORT PIN

OUTPUT PORT PIN

P2.4, P4.5, P5.5

TA0CLK

ACLK (internal)

SMCLK (internal)

TA0CLK

TACLK

ACLK

SMCLK

INCLK

CCI0A

CCI0B

GND

Timer

CCR0

N/A

TA0

N/A

P2.4. P4.5, P5.5

P2.3

P2.7

TA0.0

P2.3

P2.7

TA0.0

DVSS

DVCC

V_CC

P7.4

P7.7

TA0.1

CCI1A

P7.4

ADC12(internal)⁽¹⁾

ADC12SHSx = {1}

COUT (internal)

CCI1B

CCR1

CCR2

TA1

TA2

TA0.1

TA0.2

DVSS

DVCC

TA0.2

GND

V_CC

CCI2A

P7.7

UUPS Trigger

(USSPWRUP)

UUPS.CTL.USSPWRU

PSEL = {2}

ACLK (internal)

CCI2B

DVSS

DVCC

GND

V_CC

(1) Only on devices with ADC.

Detailed Description

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表 6-13. TA1 Signal Connections

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

DEVICE INPUT

SIGNAL

MODULE INPUT

SIGNAL

MODULE

BLOCK

INPUT PORT PIN

OUTPUT PORT PIN

P2.4, P4.5

TA1CLK

ACLK (internal)

SMCLK (internal)

TA1CLK

TACLK

ACLK

SMCLK

INCLK

CCI0A

CCI0B

GND

Timer

CCR0

N/A

TA0

N/A

P2.4. P4.5

P1.0

TA1.0

P1.0

P9.0

TA1.0

DVSS

DVCC

V_CC

P7.5

P8.4

TA1.1

CCI1A

P7.5

ADC12(internal)⁽¹⁾

ADC12SHSx = {4}

COUT (internal)

CCI1B

CCR1

CCR2

TA1

TA2

TA1.1

TA1.2

DVSS

DVCC

TA1.2

GND

V_CC

CCI2A

P8.4

ASQ Trigger

(ASQTRIG)

SAPH.ASCTL0.TRIGS

EL= {2}

ACLK (internal)

CCI2B

DVSS

DVCC

GND

V_CC

(1) Only on devices with ADC.

表 6-14. TA4 Signal Connections

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

DEVICE INPUT

MODULE INPUT

MODULE

BLOCK

INPUT PORT PIN

OUTPUT PORT PIN

SIGNAL

PJ.1,P4.6

TA4CLK

ACLK (internal)

SMCLK (internal)

TA4CLK

TA4.0

TACLK

ACLK

SMCLK

INCLK

CCI0A

CCI0B

GND

Timer

CCR0

N/A

TA0

N/A

PJ.1, P4.6

P1.1

P2.5

TA4.0

DVSS

DVCC

V_CC

P7.6

P2.6

TA4.1

CCI1A

CCI1B

P7.6

P2.6

TA4.1

ADC12(internal)⁽¹⁾

ADC12SHSx = {7}

CCR1

TA1

TA4.1

DVSS

DVCC

GND

V_CC

(1) Only on devices with ADC.

88

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MSP430FR6037, MSP430FR60371, MSP430FR6035

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6.13.12 TA2 and TA3

TA2 and TA3 are 16-bit timers and counters (Timer_A type) with two capture/compare registers each and

with internal connections only. Each timer can support multiple captures or compares, PWM outputs, and

interval timing (see 表 6-15 and 表 6-16). Each timer has extensive interrupt capabilities. Interrupts may be

generated from the counter on overflow conditions and from each capture/compare register.

表 6-15. TA2 Signal Connections

MODULE OUTPUT

DEVICE INPUT SIGNAL

MODULE INPUT NAME

MODULE BLOCK

DEVICE OUTPUT SIGNAL

SIGNAL

COUT (internal)

ACLK (internal)

SMCLK (internal)

Reserved

TACLK

ACLK

Timer

N/A

SMCLK

INCLK

TA3 CCR0 output

(internal)

CCI0A

TA3 CCI0A input

ACLK (internal)

DVSS

CCI0B

GND

V_CC

CCR0

CCR1

TA0

TA1

DVCC

ADC12(internal)⁽¹⁾

ADC12SHSx = {5}

Reserved

CCI1A

CCI1B

PPG Trigger (PPGTRIG)

SAPH.PGCTL.TRSEL= {2}

COUT (internal)

DVSS

DVCC

GND

V_CC

(1) Only on devices with ADC

表 6-16. TA3 Signal Connections

MODULE OUTPUT

SIGNAL

DEVICE OUTPUT

SIGNAL

DEVICE INPUT SIGNAL

MODULE INPUT NAME

MODULE BLOCK

COUT (internal)

ACLK (internal)

SMCLK (internal)

Reserved

TACLK

ACLK

Timer

N/A

SMCLK

INCLK

TA2 CCR0 output

(internal)

CCI0A

TA2 CCI0A input

ACLK (internal)

DVSS

CCI0B

GND

V_CC

CCR0

CCR1

TA0

DVCC

ADC12(internal)⁽¹⁾

ADC12SHSx = {6}

Reserved

CCI1A

COUT (internal)

DVSS

CCI1B

GND

V_CC

TA1

DVCC

(1) Only on devices with ADC

Detailed Description

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6.13.13 TB0

TB0 is a 16-bit timer and counter (Timer_B type) with seven capture/compare registers. TB0 can support

multiple captures or compares, PWM outputs, and interval timing (see 表 6-17). TB0 has extensive

interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each

capture/compare register.

表 6-17. TB0 Signal Connections

MODULE

OUTPUT

SIGNAL

DEVICE

OUTPUT

SIGNAL

DEVICE INPUT

SIGNAL

MODULE INPUT

SIGNAL

MODULE

BLOCK

INPUT PORT PIN

OUTPUT PORT PIN

P2.4, P4.6

TB0CLK

ACLK (internal)

SMCLK (internal)

TB0CLK

TBCLK

ACLK

Timer

CCR0

N/A

SMCLK

INCLK

CCI0A

CCI0B

P2.4, P4.6

P7.2

TB0.0

P7.2

P3.0

TB0.0

ADC12 (internal)⁽¹⁾

ADC12SHSx = {2}

TB0

TB0.0

DVSS

GND

DVCC

TB0.1

V_CC

P7.3

P8.0

CCI1A

CCI1B

P7.3

P3.1

COUT (internal)

ADC12 (internal)⁽¹⁾

ADC12SHSx = {3}

CCR1

TB1

TB0.1

DVSS

GND

DVCC

TB0.2

V_CC

CCI2A

CCI2B

GND

P8.0

P3.2

ACLK (internal)

DVSS

CCR2

CCR3

CCR4

CCR5

CCR6

TB2

TB3

TB4

TB5

TB6

TB0.2

TB0.3

TB0.4

TB0.5

TB0.6

DVCC

TB0.3

V_CC

P8.1

P3.3

CCI3A

CCI3B

GND

P8.1

P3.3

TB0.3

DVSS

DVCC

TB0.4

V_CC

P1.4

P3.5

CCI4A

CCI4B

GND

P1.4

P3.5

TB0.4

DVSS

DVCC

TB0.5

V_CC

P1.5

P3.6

CCI5A

CCI5B

GND

P1.5

P3.6

TB0.5

DVSS

DVCC

TB0.6

V_CC

PJ.3

P3.7

CCI6A

CCI6B

GND

PJ.3

P3.7

TB0.6

DVSS

DVCC

V_CC

(1) Only on devices with ADC.

90

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6.13.14 ADC12_B

The ADC12_B module supports fast 12-bit analog-to-digital conversions with differential and single-ended

inputs. The module implements a 12-bit SAR core, sample select control, a reference generator, and a

conversion result buffer. A window comparator with lower and upper limits allows CPU-independent result

monitoring with three window comparator interrupt flags.

表 6-18 lists the external trigger sources.

表 6-19 lists the available multiplexing between internal and external analog inputs.

表 6-18. ADC12_B Trigger Signal Connections

ADC12SHSx

CONNECTED TRIGGER

SOURCE

BINARY

DECIMAL

000

001

010

011

100

101

110

111

0

1

2

3

4

5

6

7

Software (ADC12SC)

TA0 CCR1 output

TB0 CCR0 output

TB0 CCR1 output

TA1 CCR1 output

TA2 CCR1 output

TA3 CCR1 output

TA4 CCR1 output

表 6-19. ADC12_B External and Internal Signal Mapping

CONTROL BIT IN ADC12CTL3

EXTERNAL ADC INPUT

(CONTROL BIT = 0)

INTERNAL ADC INPUT

REGISTER

(CONTROL BIT = 1)

Battery monitor

Temperature sensor

N/A⁽¹⁾

ADC12BATMAP

ADC12TCMAP

ADC12CH0MAP

ADC12CH1MAP

ADC12CH2MAP

ADC12CH3MAP

A31

A30

A29

A28

A27

A26

N/A⁽¹⁾

(1) N/A = No internal signal is available on this device.

Detailed Description

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6.13.15 USS

表 6-20 lists the available UUPS triggers.

表 6-20. UUPS Trigger Signal Connections

UUPS.CTL.USSPWRUPSEL

CONNECTED TRIGGER SOURCE

BINARY

00

01

10

11

Software (UUPS.CTL.USSPWRUP)

RTC (any enabled interrupt events)

TA0 CCR2 output

P1.7

表 6-21 lists the available PPG triggers.

表 6-21. PPG Trigger Signal Connections

SAPH.PGCTL.TRSEL

CONNECTED TRIGGER SOURCE

BINARY

00

01

10

11

Software (SAPH.PPGTRIG.PPGTRIG)

ASQ (Acquisition Sequencer)

TA2 CCR1 output

Reserved

表 6-22 lists the available ASQ triggers.

表 6-22. ASQ Trigger Signal Connections

SAPH.ASCTL0.TRIGSEL

CONNECTED TRIGGER SOURCE

BINARY

00

01

10

11

Software (SAPH.ASQTRIG.ASQTRIG)

PSQ (Power Sequencer)

TA1 CCR2 output

Reserved

6.13.16 Comparator_E

The primary function of the Comparator_E module is to support precision slope analog-to-digital

conversions, battery voltage supervision, and monitoring of external analog signals.

6.13.17 CRC16

The CRC16 module produces a signature based on a sequence of entered data values and can be used

for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.

6.13.18 CRC32

The CRC32 module produces a signature based on a sequence of entered data values and can be used

for data checking purposes. The CRC32 module signature is based on the ISO 3309 standard.

6.13.19 AES256 Accelerator

The AES accelerator module performs encryption and decryption of 128-bit data with 128-, 192-, or 256-

bit keys according to the Advanced Encryption Standard (AES) (FIPS PUB 197) in hardware.

92

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6.13.20 True Random Seed

The device descriptor information (TLV) section contains a 128-bit true random seed that can be used to

implement a deterministic random number generator.

6.13.21 Shared Reference (REF)

The REF module generates critical reference voltages that can be used by the various analog peripherals

in the device.

6.13.22 LCD_C

The LCD_C driver generates the segment and common signals required to drive a liquid crystal display

(LCD). The LCD_C controller has dedicated data memories to hold segment drive information. Common

and segment signals are generated as defined by the mode. Static and 2-mux to 8-mux LCDs are

supported. The module can provide an LCD voltage independent of the supply voltage with its integrated

charge pump. It is possible to control the level of the LCD voltage and thus contrast by software. The

module also provides an automatic blinking capability for individual segments in static, 2-, 3-, and 4-mux

modes.

To reduce system noise, the charge pump can be temporarily disabled. 表 6-23 lists the available

automatic charge pump disable options.

表 6-23. LCD Automatic Charge Pump Disable Bits (LCDCPDISx)

CONTROL BIT

LCDCPDIS0

DESCRIPTION

LCD charge pump disable during ADC12 conversion

0b = LCD charge pump not automatically disabled during conversion.

1b = LCD charge pump automatically disabled during conversion.

LCDCPDIS1 to LCDCPDIS7

No functionality.

6.13.23 Embedded Emulation

6.13.23.1 Embedded Emulation Module (EEM) (S Version)

The EEM supports real-time in-system debugging. The S version of the EEM has the following features:

•

Three hardware triggers or breakpoints on memory access

One hardware trigger or breakpoint on CPU register write access

Up to four hardware triggers that can be combined to form complex triggers or breakpoints

One cycle counter

Clock control on module level

6.13.23.2 EnergyTrace++ Technology

The devices implement circuitry to support EnergyTrace++ technology. The EnergyTrace++ technology

lets the user observe information about the internal states of the microcontroller. These states include the

CPU Program Counter (PC), the on or off status of the peripherals and system clocks (regardless of the

clock source), and the low-power mode currently in use. These states can always be read by a debug

tool, even when the microcontroller sleeps in LPMx.5 modes.

The activity of the following modules can be observed:

•

LEA is running

MPY is calculating.

WDT is counting.

RTC is counting.

ADC: a sequence, sample, or conversion is active.

REF: REFBG or REFGEN active and BG in static mode.

Detailed Description

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•

COMP is on.

AES is encrypting or decrypting.

eUSCI_A0 is transferring (receiving or transmitting) data.

eUSCI_A1 is transferring (receiving or transmitting) data.

eUSCI_A2 is transferring (receiving or transmitting) data.

eUSCI_A3 is transferring (receiving or transmitting) data.

eUSCI_B0 is transferring (receiving or transmitting) data.

eUSCI_B1 is transferring (receiving or transmitting) data.

TB0 is counting.

TA0 is counting.

TA1 is counting.

TA2 is counting.

TA3 is counting.

TA4 is counting.

LCD_C is running.

USS status

94

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6.14 Input/Output Diagrams

6.14.1 Port Function Select Registers (PySEL1 , PySEL0)

Port pins are multiplexed with peripheral module functions as described in the MSP430FR58xx,

MSP430FR59xx, and MSP430FR6xx Family User's Guide. The functions of each port pin are controlled

by its port function select registers, PySEL1 and PySEL0, where y = port number. The bits in the registers

are mapped to the pins in the port. The primary module function, secondary module function, and tertiary

module function of the pins are determined by the configuration of the PySEL1.x and PySEL0.x bits (see

表 6-24). For example, P1SEL1.0 and P1SEL0.0 determine the primary module function, secondary

module function, and tertiary module function of the P1.0 pin, which is in port 1. The module functions may

also require the PxDIR bits to be configured according to the direction needed for the module function.

表 6-24. I/O Function Selection

I/O FUNCTIONS

General-purpose I/O is selected

PySEL1.x

0

1

0

1

0

1

Primary module function is selected

Secondary module function is selected

Tertiary module function is selected

See the port pin function tables in the following sections for the configurations of the function and direction

for each pin.

Detailed Description

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6.14.2 Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger

图 6-3 shows the port diagram. 表 6-25 summarizes the selection of the pin function.

Pad Logic

(ADC) Reference

To ADC

From ADC

To Comparator

From Comparator

CBPD.x

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

module 1 or PxDIR.x

module 2 or PxDIR.x

module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To modules

NOTE: Functional representation only.

图 6-3. Port P1 (P1.0 to P1.1) Diagram

96

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表 6-25. Port P1 (P1.0 to P1.1) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME (P1.x)

x

FUNCTION

P1DIR.x

P1SEL1.x

P1SEL0.x

P1.0 (I/O)

UCA1CLK

TA1.CCI0A

TA1.0

I: 0; O: 1

X⁽²⁾

0

1

P1.0/UCA1CLK/TA1.0/A0/C0/ VREF-

/VeREF-

0

1

0

1

A0, C0, VREF-, VeREF-⁽³⁾⁽⁴⁾

X

1

0

1

0

1

P1.1 (I/O)

I: 0; O: 1

X⁽²⁾

UCA1STE

P1.1/UCA1STE/TA4.0/A1/C1/

VREF+/VeREF+

1

TA4.CCI0A

0

1

0

1

TA4.0

1

A1, C1, VREF+, VeREF+⁽³⁾⁽⁴⁾

X

(1) X = Don't care

(2) Direction controlled by eUSCI_A1 module.

(3) Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

(4) Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module

automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.

Detailed Description

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6.14.3 Port P1 (P1.2 to P1.7) Input/Output With Schmitt Trigger

图 6-4 shows the port diagram. 表 6-26 summarizes the selection of the pin function.

Pad Logic

To ADC

From ADC

To Comparator

From Comparator

CBPD.x

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

module 1 or PxDIR.x

module 2 or PxDIR.x

module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To modules

NOTE: Functional representation only.

图 6-4. Port P1 (P1.2 to P1.7) Diagram

98

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表 6-26. Port P1 (P1.2 to P1.7) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME (P1.x)

x

FUNCTION

P1DIR.x

P1SEL1.x

P1SEL0.x

P1.2 (I/O)

I: 0; O: 1

X⁽²⁾

0

1

UCA1SIMO/UCA1TXD

N/A

P1.2/UCA1SIMO/UCA1TXD/A8/C8

P1.3/UCA1SOMI/UCA1RXD/A9/C9

P1.4/TB0.4/UCB0STE/A2/C2

2

0

1

0

Internally tied to DVSS

A8, C8⁽³⁾⁽⁴⁾

P1.3 (I/O)

1

X

1

0

1

0

1

I: 0; O: 1

X⁽²⁾

UCA1SOMI/UCA1RXD

N/A

3

4

5

6

0

1

0

Internally tied to DVSS

A9, C9⁽³⁾⁽⁴⁾

P1.4 (I/O)

1

X

1

0

1

0

I: 0; O: 1

TB0.CCI4A

TB0.4

0

1

X⁽⁵⁾

UCB0STE

A2, C2⁽³⁾⁽⁴⁾

1

0

1

0

X

P1.5(I/O)

I: 0; O: 1

TB0.CCI5A

TB0.5

0

1

P1.5/TB0.5/UCB0CLK/A3/C3

1

X⁽⁵⁾

UCB0CLK

A3, C3⁽³⁾⁽⁴⁾

1

0

1

0

X

P1.6(I/O)

I: 0; O: 1

N/A

0

1

P1.6/UCB0SIMO/UCB0SDA/A4/C4

Internally tied to DVSS

UCB0SIMO/UCB0SDA

A4, C4⁽³⁾⁽⁴⁾

P1.7(I/O)

1

X⁽⁵⁾

1

0

X

1

0

1

0

1

0

1

X

1

0

1

X

I: 0; O: 1

USSTRG (independent function)

0

P1.7/USSTRG/UCB0SOMI/UCB0SCL/

A5/C5

7

Internally tied to DVSS

UCB0SOMI/UCB0SCL

A5, C5⁽³⁾⁽⁴⁾

1

X⁽⁵⁾

X

(1) X = Don't care

(2) Direction controlled by eUSCI_A1 module.

(3) Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

(4) Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module

automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.

(5) Direction controlled by eUSCI_B0 module.

Detailed Description

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6.14.4 Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger

图 6-5 shows the port diagram. 表 6-27 summarizes the selection of the pin function.

Pad Logic

To ADC

From ADC

To Comparator

From Comparator

CBPD.x

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

module 1 or PxDIR.x

module 2 or PxDIR.x

module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To modules

NOTE: Functional representation only.

图 6-5. Port P2 (P2.0 to P2.3) Diagram

100

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表 6-27. Port P2 (P2.0 to P2.3) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME (P2.x)

x

FUNCTION

P2DIR.x

P2SEL1.x

P2SEL0.x

P2.0 (I/O)

N/A

I: 0; O: 1

0

1

P2.0/UCA0SIMO/UCA0TXD/A6/C6

P2.1/UCA0SOMI/UCA0RXD/A7/C7

P2.2/COUT/UCA0CLK/A14/C14

0

Internally tied to DVSS

UCA0SIMO/UCA0TXD

A6, C6⁽³⁾⁽⁴⁾

P2.1 (I/O)

1

X⁽²⁾

1

0

1

0

X

I: 0; O: 1

N/A

0

1

2

3

Internally tied to DVSS

UCA0SOMI/UCA0RXD

A7, C7⁽³⁾⁽⁴⁾

P2.2 (I/O)

1

X⁽²⁾

1

0

1

0

X

I: 0; O: 1

N/A

0

1

COUT

1

X⁽²⁾

UCA0CLK

A14, C14⁽³⁾⁽⁴⁾

1

0

1

0

X

P2.3(I/O)

I: 0; O: 1

TA0.CCI0A

TA0.0

0

1

X⁽²⁾

0

1

P2.3/TA0.0/UCA0STE/A15/C15

(1) X = Don't care

UCA0STE

A15, C15⁽³⁾⁽⁴⁾

1

0

1

X

(2) Direction controlled by eUSCI_A0 module.

(3) Setting P2SEL1.x and P2SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

(4) Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module

automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.

Detailed Description

101

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

6.14.5 Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger

图 6-6 shows the port diagram. 表 6-28 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

module 1 or PxDIR.x

module 2 or PxDIR.x

module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To modules

NOTE: Functional representation only.

图 6-6. Port P2 (P2.4 to P2.7) Diagram

102

Detailed Description

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 6-28. Port P2 (P2.4 to P2.7) Pin Functions

(1)

CONTROL BITS OR SIGNALS

PIN NAME (P2.x)

x

FUNCTION

P2DIR.x

P2SEL1.x

P2SEL0.x

LCDSz

P2.4 (I/O)

TA0LCK

I: 0; O: 1

0

1

0

1

0

Internally tied to DVSS

TB0LCK

1

0

P2.4/TA0LCK/TB0CLK/TA1CLK/

LCDS32

4

Internally tied to DVSS

TA1LCK

1

0

Internally tied to DVSS

1

(2)

Sz

X

0

X

0

1

0

P2.5 (I/O)

I: 0; O: 1

N/A

0

1

0

1

0

Internally tied to DVSS

TA4.CCI0B

1

0

P2.5/TA4.0/LCDS31

5

6

7

TA4.0

1

N/A

0

Internally tied to DVSS

1

(2)

Sz

X

0

X

0

1

0

P2.6 (I/O)

I: 0; O: 1

N/A

0

1

0

1

0

Internally tied to DVSS

TA4.CCI1B

1

0

P2.6/TA4.1/LCDS30

TA4.1

1

N/A

0

Internally tied to DVSS

1

(2)

Sz

X

0

X

0

1

0

P2.7 (I/O)

I: 0; O: 1

N/A

0

1

0

1

0

1

X

0

1

0

Internally tied to DVSS

TA0.CCI0B

P2.7/TA0.0/LCDS21

(1) X = Don't care

TA0.0

N/A

1

0

1

Internally tied to DVSS

(2)

Sz

X

(2) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节 4.1.

Detailed Description

103

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

6.14.6 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger

图 6-7 shows the port diagram. 表 6-29 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

module 1 or PxDIR.x

module 2 or PxDIR.x

module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To modules

NOTE: Functional representation only.

图 6-7. Port P3 (P3.0 to P3.7) Diagram

104

Detailed Description

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产品主页链接: MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371

MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 6-29. Port P3 (P3.0 to P3.7) Pin Functions

(1)

CONTROL BITS OR SIGNALS

PIN NAME (P3.x)

x

FUNCTION

P3DIR.x

P3SEL1.x

P3SEL0.x

LCDSz

P3.0 (I/O)

N/A

I: 0; O: 1

0

1

0

1

0

Internally tied to DVSS

TB0.CCI0B

1

0

P3.0/TB0.0/LCDS29

P3.1/TB0.1/LCDS28

P3.2/TB0.2/LCDS27

P3.3/TB0.3/LCDS26

P3.4/TB0OUTH/LCDS25

0

TB0.0

1

N/A

0

Internally tied to DVSS

1

(2)

Sz

X

0

X

0

1

0

P3.1 (I/O)

I: 0; O: 1

N/A

0

1

0

1

0

Internally tied to DVSS

1

N/A

0

1

2

3

4

TB0.1

1

N/A

0

Internally tied to DVSS

1

(2)

Sz

X

0

X

0

1

0

P3.2 (I/O)

I: 0; O: 1

N/A

0

1

0

1

0

Internally tied to DVSS

1

N/A

0

TB0.2

1

N/A

0

Internally tied to DVSS

1

(2)

Sz

X

0

X

0

1

0

P3.3 (I/O)

I: 0; O: 1

N/A

0

1

0

1

0

Internally tied to DVSS

TB0.CCI3B

1

0

TB0.3

1

N/A

0

Internally tied to DVSS

1

(2)

Sz

X

0

X

0

1

0

P3.4 (I/O)

I: 0; O: 1

N/A

0

1

0

1

0

1

X

0

1

0

Internally tied to DVSS

TB0OUTH

Internally tied to DVSS

N/A

1

0

1

Internally tied to DVSS

(2)

Sz

X

(1) X = Don't care

(2) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节 4.1.

Detailed Description

105

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 6-29. Port P3 (P3.0 to P3.7) Pin Functions (continued)

(1)

CONTROL BITS OR SIGNALS

PIN NAME (P3.x)

x

FUNCTION

P3DIR.x

P3SEL1.x

P3SEL0.x

LCDSz

P3.5 (I/O)

N/A

I: 0; O: 1

0

1

0

1

0

Internally tied to DVSS

TB0.CCI4B

1

0

P3.5/TB0.4/LCDS24

5

TB0.4

1

N/A

0

Internally tied to DVSS

1

(2)

Sz

X

0

X

0

1

0

P3.6 (I/O)

I: 0; O: 1

N/A

0

1

0

1

0

Internally tied to DVSS

TB0.CCI5B

1

0

P3.6/TB0.5/LCDS23

6

TB0.5

1

N/A

0

Internally tied to DVSS

1

(2)

Sz

X

0

X

0

1

0

P3.7 (I/O)

I: 0; O: 1

N/A

0

1

0

1

0

1

X

0

1

0

Internally tied to DVSS

TB0.CCI6B

P3.7/TB0.6/LCDS22

7

TB0.6

N/A

1

0

1

Internally tied to DVSS

(2)

Sz

X

106

Detailed Description

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

6.14.7 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger

图 6-8 shows the port diagram. 表 6-30 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

module 1 or PxDIR.x

module 2 or PxDIR.x

module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To modules

NOTE: Functional representation only.

图 6-8. Port P4 (P4.0 to P4.7) Diagram

表 6-30. Port P4 (P4.0 to P4.7) Pin Functions

(1)

CONTROL BITS OR SIGNALS

PIN NAME (P4.x)

x

FUNCTION

P4DIR.x

P4SEL1.x

P4SEL0.x

LCDSz

P4.0 (I/O)

N/A

I: 0; O: 1

0

1

0

1

0

1

X

0

1

0

Internally tied to DVSS

N/A

P4.0/RTCCLK/LCDS16

0

RTCCLK

N/A

1

0

1

Internally tied to DVSS

(2)

Sz

X

(1) X = Don't care

(2) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节 4.1.

Detailed Description

107

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产品主页链接: MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371

MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 6-30. Port P4 (P4.0 to P4.7) Pin Functions (continued)

(1)

CONTROL BITS OR SIGNALS

PIN NAME (P4.x)

x

FUNCTION

P4DIR.x

P4SEL1.x

P4SEL0.x

LCDSz

P4.1 (I/O)

UCA0CLK

N/A

I: 0; O: 1

X⁽³⁾

0

1

0

1

0

1

0

P4.1/UCA0CLK/LCDS15

1

Internally tied to DVSS

N/A

1

0

Internally tied to DVSS

1

(2)

Sz

X

0

X

0

1

0

P4.2 (I/O)

I: 0; O: 1

X⁽³⁾

UCA0STE

N/A

0

1

0

1

0

P4.2/UCA0STE/LCDS14

2

3

4

Internally tied to DVSS

N/A

1

0

Internally tied to DVSS

1

(2)

Sz

X

0

X

0

1

0

P4.3 (I/O)

I: 0; O: 1

X⁽³⁾

UCA0SIMO/UCA0TXD

N/A

0

1

0

1

0

P4.3/UCA0SIMO/UCA0TXD/LCDS13

Internally tied to DVSS

N/A

1

0

Internally tied to DVSS

1

(2)

Sz

X

0

X

0

1

0

P4.4 (I/O)

I: 0; O: 1

X⁽³⁾

UCA0SOMI/UCA0RXD

N/A

0

1

0

1

0

P4.4/UCA0SOMI/UCA0RXD/LCDS12

Internally tied to DVSS

N/A

1

0

Internally tied to DVSS

1

(2)

Sz

X

0

X

0

1

0

P4.5 (I/O)

I: 0; O: 1

TA0CLK

0

1

0

1

0

Internally tied to DVSS

TA1CLK

1

0

P4.5/TA0LCK/TA1CLK/LCDS11

5

Internally tied to DVSS

N/A

1

0

Internally tied to DVSS

1

(2)

Sz

X

0

X

0

1

0

P4.6 (I/O)

I: 0; O: 1

TB0CLK

0

1

0

1

0

1

X

0

1

0

Internally tied to DVSS

TA4CLK

P4.6/TB0CLK/TA4CLK/LCDS10

6

Internally tied to DVSS

N/A

1

0

1

Internally tied to DVSS

(2)

Sz

X

(3) Direction controlled by eUSCI_A0 module.

108 Detailed Description

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产品主页链接: MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371

MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 6-30. Port P4 (P4.0 to P4.7) Pin Functions (continued)

(1)

CONTROL BITS OR SIGNALS

PIN NAME (P4.x)

x

FUNCTION

P4DIR.x

P4SEL1.x

P4SEL0.x

LCDSz

P4.7 (I/O)

N/A

I: 0; O: 1

0

1

0

1

0

1

X

0

1

0

Internally tied to DVSS

DMAE0

P4.7/DMAE0/LCDS9

7

Internally tied to DVSS

N/A

1

0

1

Internally tied to DVSS

(2)

Sz

X

Detailed Description

109

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产品主页链接: MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371

MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

6.14.8 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger

图 6-9 shows the port diagram. 表 6-31 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

module 1 or PxDIR.x

module 2 or PxDIR.x

module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To modules

NOTE: Functional representation only.

图 6-9. Port P5 (P5.0 to P5.7) Diagram

表 6-31. Port P5 (P5.0 to P5.7) Pin Functions

(1)

CONTROL BITS OR SIGNALS

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

P5SEL1.x

P5SEL0.x

LCDSz

P5.0 (I/O)

N/A

I: 0; O: 1

0

1

X

1

0

1

X

0

1

Internally tied to DVSS

UCA2SIMO/UCA2TXD

N/A

1

P5.0/UCA2SIMO/UCA2TXD/LCDS8

0

X⁽²⁾

0

Internally tied to DVSS

1

(3)

Sz

X

(1) X = Don't care

(2) Direction controlled by eUSCI_A3 module.

(3) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节 4.1.

110 Detailed Description

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 6-31. Port P5 (P5.0 to P5.7) Pin Functions (continued)

(1)

CONTROL BITS OR SIGNALS

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

P5SEL1.x

P5SEL0.x

LCDSz

P5.1 (I/O)

N/A

I: 0; O: 1

0

1

0

1

0

Internally tied to DVSS

UCA2SOMI/UCA2RXD

N/A

1

X⁽²⁾

P5.1/UCA2SOMI/UCA2RXD/LCDS7

1

0

Internally tied to DVSS

1

(3)

Sz

X

0

X

0

1

0

P5.2 (I/O)

I: 0; O: 1

N/A

0

1

0

1

0

Internally tied to DVSS

UCA2CLK

1

X⁽²⁾

P5.2/UCA2CLK/LCDS6

2

3

4

5

6

N/A

0

Internally tied to DVSS

1

(3)

Sz

X

0

X

0

1

0

P5.3 (I/O)

I: 0; O: 1

N/A

0

1

0

1

0

Internally tied to DVSS

UCA2STE

1

X⁽²⁾

P5.3/UCA2STE/LCDS5

N/A

0

Internally tied to DVSS

1

(3)

Sz

X

0

X

0

1

0

P5.4 (I/O)

I: 0; O: 1

N/A

0

1

0

1

0

Internally tied to DVSS

UCB1CLK

1

X⁽⁴⁾

P5.4/UCB1CLK/LCDS4

N/A

0

Internally tied to DVSS

1

(3)

Sz

X

0

X

0

1

0

P5.5 (I/O)

I: 0; O: 1

TA0CLK

0

1

0

1

0

Internally tied to DVSS

UCB1SIMO/UCB1SDA

N/A

1

X⁽⁴⁾

P5.5/TA0CLK/UCB1SIMO/UCB1SDA

/LCDS3

0

Internally tied to DVSS

1

(3)

Sz

X

0

X

0

1

0

P5.6 (I/O)

I: 0; O: 1

N/A

0

1

X

1

0

1

X

0

1

Internally tied to DVSS

UCB1SOMI/UCB1SCL

N/A

1

P5.6/UCB1SOMI/UCB1SCL/LCDS2

X⁽⁴⁾

0

Internally tied to DVSS

1

(3)

Sz

X

(4) Direction controlled by eUSCI_B1 module.

Detailed Description

111

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产品主页链接: MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371

MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 6-31. Port P5 (P5.0 to P5.7) Pin Functions (continued)

(1)

CONTROL BITS OR SIGNALS

PIN NAME (P5.x)

x

FUNCTION

P5DIR.x

P5SEL1.x

P5SEL0.x

LCDSz

P5.7 (I/O)

N/A

I: 0; O: 1

0

1

X

1

0

1

X

0

1

Internally tied to DVSS

UCB1STE

1

P5.7/UCB1STE/LCDS1

7

X⁽⁴⁾

0

N/A

Internally tied to DVSS

1

(3)

Sz

X

112

Detailed Description

提交文档反馈意见

产品主页链接: MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371

MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

6.14.9 Port P6 (P6.0) Input/Output With Schmitt Trigger

图 6-10 shows the port diagram. 表 6-32 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

module 1 or PxDIR.x

module 2 or PxDIR.x

module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To modules

NOTE: Functional representation only.

图 6-10. Port P6 (P6.0) Diagram

表 6-32. Port P6 (P6.0) Pin Functions

(1)

CONTROL BITS OR SIGNALS

PIN NAME (P6.x)

x

FUNCTION

P6DIR.x

P6SEL1.x

P6SEL0.x

LCDSz

P6.0 (I/O)

I: 0; O: 1

0

N/A

0

1

0

1

0

1

X

0

1

0

Internally tied to DVSS

N/A

P6.0/COUT/LCDS0

0

COUT

N/A

1

0

1

Internally tied to DVSS

(2)

Sz

X

(1) X = Don't care

(2) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节 4.1.

Detailed Description

113

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

6.14.10 Port P6 (P6.1 to P6.5) Input/Output With Schmitt Trigger

图 6-11 shows the port diagram. 表 6-33 summarizes the selection of the pin function.

Pad Logic

To/From LCD

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

module 1 or PxDIR.x

module 2 or PxDIR.x

module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To modules

NOTE: Functional representation only.

图 6-11. Port P6 (P6.1 to P6.5) Diagram

114

Detailed Description

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 6-33. Port P6 (P6.1 to P6.5) Pin Functions

(1)

CONTROL BITS OR SIGNALS

PIN NAME (P6.x)

x

FUNCTION

P6DIR.x

P6SEL1.x

P6SEL0.x

P6.1 (I/O)

N/A

I: 0; O: 1

0

1

0

Internally tied to DVSS

N/A

1

P6.1/R03

1

0

Internally tied to DVSS

1

(2)

R03

X

1

0

1

0

P6.2 (I/O)

I: 0; O: 1

N/A

0

1

0

Internally tied to DVSS

N/A

1

P6.2/R13/LCDREF

2

3

4

5

0

Internally tied to DVSS

1

(2)

R13/LCDREF

X

1

0

1

0

P6.3 (I/O)

I: 0; O: 1

N/A

0

1

0

Internally tied to DVSS

N/A

1

P6.3/R23

0

Internally tied to DVSS

1

(2)

R23

X

1

0

1

0

P6.4 (I/O)

I: 0; O: 1

N/A

0

1

0

Internally tied to DVSS

N/A

1

P6.4/COM0

0

Internally tied to DVSS

1

(2)

COM0

X

1

0

1

0

P6.5 (I/O)

I: 0; O: 1

N/A

0

1

0

1

X

0

1

Internally tied to DVSS

N/A

P6.5/COM1

1

0

1

Internally tied to DVSS

(2)

COM1

(1) X = Don't care

(2) Setting P6SEL1.x and P6SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

Detailed Description

115

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

6.14.11 Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger

图 6-12 shows the port diagram. 表 6-34 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

COMx

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

module 1 or PxDIR.x

module 2 or PxDIR.x

module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To modules

NOTE: Functional representation only.

图 6-12. Port P6 (P6.6 and P6.7) Diagram

116

Detailed Description

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 6-34. Port P6 (P6.6 to P6.7) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P6.x)

x

FUNCTION

P6DIR.x

P6SEL1.x

P6SEL0.x

LCDSz

P6.6(I/O)

N/A

I: 0; O: 1

0

1

0

1

X

0

1

0

Internally tied to DVSS

N/A

P6.6/COM2/LCDS38

6

0

1

0

Internally tied to DVSS

COM2⁽¹⁾

1

X

0

1

0

X

0

(2)

Sz

X

P6.7(I/O)

I: 0; O: 1

N/A

0

1

0

1

X

0

1

0

Internally tied to DVSS

N/A

P6.7/COM3/LCDS37

7

0

1

Internally tied to DVSS

COM3⁽¹⁾

1

X

0

1

0

(2)

Sz

X

(1) Setting P6SEL1.x and P6SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

(2) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节 4.1.

Detailed Description

117

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

6.14.12 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger

图 6-13 shows the port diagram. 表 6-35 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

COMx

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

module 1 or PxDIR.x

module 2 or PxDIR.x

module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To modules

NOTE: Functional representation only.

图 6-13. Port P7 (P7.0 to P7.3) Diagram

118

Detailed Description

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 6-35. Port P7 (P7.0 to P7.3) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P7.x)

x

FUNCTION

P7DIR.x

P7SEL1.x

P7SEL0.x

LCDSz

P7.0(I/O)

I: 0; O: 1

X⁽¹⁾

0

1

0

UCA2SIMO/UCA2TXD

N/A

0

1

0

1

P7.0/UCA2SIMO/UCA2TXD/

ACLK/COM4/LCDS36

0

ACLK

COM4⁽²⁾

1

X

1

X

0

1

0

X

0

1

(3)

Sz

X

P7.1(I/O)

I: 0; O: 1

X⁽¹⁾

0

UCA2SOMI/UCA2RXD

N/A

0

1

0

1

P7.1/UCA2SOMI/UCA2RXD/

SMCLK/COM5/LCDS35

1

2

3

SMCLK

COM5⁽²⁾

1

X

1

X

0

1

0

X

0

1

(3)

Sz

X

P7.2(I/O)

UCA2CLK

TB0.CCI0A

TB0.0

I: 0; O: 1

X⁽¹⁾

0

1

0

1

P7.2/UCA2CLK/TB0.0/COM6/

LCDS34

1

COM6⁽²⁾

X

1

X

0

1

0

X

0

1

(3)

Sz

X

P7.3(I/O)

UCA2STE

TB0.CCI1A

TB0.1

I: 0; O: 1

X⁽¹⁾

0

1

0

1

P7.3/UCA2STE/TB0.1/COM7/

LCDS33

1

COM7⁽²⁾

X

1

X

0

1

0

(3)

Sz

X

(1) Direction controlled by eUSCI_A2 module.

(2) Setting P6SEL1.x and P6SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

(3) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节 4.1.

Detailed Description

119

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

6.14.13 Port P7 (P7.4) Input/Output With Schmitt Trigger

图 6-14 shows the port diagram. 表 6-36 summarizes the selection of the pin function.

ACTIVATE

Pad Logic

MTIF_PIN_EN

1

0

TPOE

1

From MTIF

PxREN.x

0

1

0

0 0

0 1

1 0

1 1

PxDIR.x

DVSS

DVCC

0

1

module 1 or PxDIR.x

Direction

0: Input

1: Output

1

module 2 or PxDIR.x

module 3 or PxDIR.x

1

0

1

0 0

0 1

1 0

1 1

PxOUT.x

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

1

0

PxSEL1.x

PxSEL0.x

PxIN.x

EN

D

Bus

Keeper

To modules

To MTIF

TPIE

NOTE: Functional representation only.

图 6-14. Port P7 (P7.4) Diagram

120

Detailed Description

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 6-36. Port P7 (P7.4) Pin Functions

CONTROL BITS OR SIGNALS

Signal on

PIN NAME (P7.x)

x

FUNCTION

P7SEL

1.x

ACTIVATE

(1)

P7DIR.x

P7SEL0.x

TPOE

TPIE⁽¹⁾

MTIF_PIN_E

(1)

(2)

N pin

P7.4(I/O)

I: 0; O: 1

0

1

0

X

TA0.CCI1A

TA0.1

0

1

0

1

0

1

X

N/A

1

0

1

0

X

Internally tied to DVSS

N/A

P7.4/TA0.1/

MTIF_OUT_IN

4

Internally tied to DVSS

MTIF_IN

MTIF_OUT⁽¹⁾

X

0

1

X

0

X

Internally tied to

DVSS⁽¹⁾

MTIF_OUT⁽¹⁾

X

1

X

1

0

1

(1) See MTIF.TPCTL register

(2) When P7.5 pin is configured as MTIF_PIN_EN (See 表 6-37 for details)

Detailed Description

121

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

6.14.14 Port P7 (P7.5) Input/Output With Schmitt Trigger

图 6-15 shows the port diagram. 表 6-37 summarizes the selection of the pin function.

Pad Logic

ACTIVATE

0

1

0

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

module 1 or PxDIR.x

module 2 or PxDIR.x

module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0

0 0

0 1

1 0

1 1

PxOUT.x

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

EN

D

Bus

Keeper

To modules

MTIF_PIN_EN

NOTE: Functional representation only.

图 6-15. Port P7 (P7.5) Diagram

122

Detailed Description

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 6-37. Port P7 (P7.5) Pin Functions

CONTROL BITS OR SIGNALS

P7SEL1.

PIN NAME (P7.x)

x

FUNCTION

(1)

P7DIR.x

P7SEL0.x

ACTIVATE

x

P7.5(I/O)

TA1.CCI1A

TA1.1

I: 0; O: 1

0

1

0

1

0

1

X

0

1

0

N/A

P7.5/TA1.1/MTIF_PIN_EN

5

0

Internally tied to DVSS

N/A

1

0

1

Internally tied to DVSS

MTIF_PIN_EN

X

(1) See MTIF.TPCTL register

Detailed Description

123

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

6.14.15 Port P7 (P7.6 and P7.7) Input/Output With Schmitt Trigger

图 6-16 shows the port diagram. 表 6-38 summarizes the selection of the pin function.

Pad Logic

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

module 1 or PxDIR.x

module 2 or PxDIR.x

module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

EN

D

To modules

NOTE: Functional representation only.

图 6-16. Port P7 (P7.6 and P7.7) Diagram

124

Detailed Description

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 6-38. Port P7 (P7.6 to P7.7) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P7.x)

x

FUNCTION

P7DIR.x

P7SEL1.x

P7SEL0.x

P7.6(I/O)

TA4.CCI1A

TA4.1

I: 0; O: 1

0

1

P7.6/TA4.1/DMAE0/COUT

6

DMAE0

0

Internally tied to DVSS

1

N/A

0

1

0

1

0

1

COUT

1

P7.7(I/O)

TA0.CCI2A

TA0.2

I: 0; O: 1

0

1

0

1

0

1

P7.7/TA0.2/TB0OUTH/COUT

7

TB0OUTH

Internally tied to DVSS

N/A

1

0

1

COUT

Detailed Description

125

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产品主页链接: MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371

MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

6.14.16 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger

图 6-17 shows the port diagram. 表 6-39 summarizes the selection of the pin function.

Pad Logic

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

module 1 or PxDIR.x

module 2 or PxDIR.x

module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

EN

D

To modules

NOTE: Functional representation only.

图 6-17. Port P8 (P8.0 to P8.3) Diagram

126

Detailed Description

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产品主页链接: MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371

MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 6-39. Port P8 (P8.0 to P8.3) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P8.x)

x

FUNCTION

P8DIR.x

P8SEL1.x

P8SEL0.x

P8.0(I/O)

UCA3STE

TB0.CCI2A

TB0.2

I: 0; O: 1

X⁽¹⁾

0

1

0

P8.0/UCA3STE/TB0.2/DMAE0

0

1

0

1

DMAE0

0

Internally tied to DVSS

P8.1(I/O)

1

I: 0; O: 1

X⁽¹⁾

0

1

UCA3CLK

TB0.CCI3A

TB0.3

0

P8.1/UCA3CLK/TB0.3/TB0OUTH

P8.2/UCA3SOMI/UCA3RXD/MCLK

P8.3/UCA3SIMO/UCA3TXD/RTCCLK

1

2

3

1

0

1

TB0OUTH

0

Internally tied to DVSS

P8.2(I/O)

1

I: 0; O: 1

X⁽¹⁾

0

1

UCA3SOMI/UCA3RXD

N/A

0

1

0

1

MCLK

1

N/A

0

Internally tied to DVSS

P8.3(I/O)

1

I: 0; O: 1

X⁽¹⁾

0

1

/UCA3SIMO/UCA3TXD

N/A

0

1

0

1

RTCCLK

1

N/A

0

Internally tied to DVSS

1

(1) Direction controlled by eUSCI_A3 module.

Detailed Description

127

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

6.14.17 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger

图 6-18 shows the port diagram. 表 6-40 summarizes the selection of the pin function.

Pad Logic

To ADC

From ADC

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

module 1 or PxDIR.x

module 2 or PxDIR.x

module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To modules

NOTE: Functional representation only.

图 6-18. Port P8 (P8.4 to P8.7) Diagram

128

Detailed Description

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产品主页链接: MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371

MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 6-40. Port P8 (P8.4 to P8.7) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P8.x)

x

FUNCTION

P8DIR.x

P8SEL1.x

P8SEL0.x

P8.4(I/O)

UCB1CLK

TA1.CCI2A

TA1.2

I: 0; O: 1

X⁽¹⁾

0

1

P8.4/UCB1CLK/TA1.2/A10

4

0

1

0

1

A10⁽²⁾

X

1

0

1

0

1

P8.5(I/O)

I: 0; O: 1

X⁽¹⁾

UCB1SIMO/UCB1SDA

N/A

P8.5/UCB1SIMO/UCB1SDA/A11

P8.6/UCB1SOMI/UCB1SCL/A12

P8.7/UCB1STE/USSXT_BOUT/A13

5

6

7

0

1

0

Internally tied to DVSS

A11⁽²⁾

1

X

1

0

1

0

1

P8.6(I/O)

I: 0; O: 1

X⁽¹⁾

UCB1SOMI/UCB1SCL

N/A

0

1

0

Internally tied to DVSS

A12⁽²⁾

1

X

1

0

1

0

1

P8.7(I/O)

I: 0; O: 1

X⁽¹⁾

UCB1STE

N/A

0

1

0

1

USSXT_BOUT⁽³⁾

A13⁽²⁾

1

X

(1) Direction controlled by eUSCI_B1 module.

(2) Setting P8SEL1.x and P8SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

(3) USSXTHSPLL.PLLXTLCTL.XTOUTOFF bit must also be set to 0.

Detailed Description

129

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

6.14.18 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger

图 6-19 shows the port diagram. 表 6-41 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

module 1 or PxDIR.x

module 2 or PxDIR.x

module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To modules

NOTE: Functional representation only.

图 6-19. Port P9 (P9.0 to P9.3) Diagram

130

Detailed Description

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 6-41. Port P9 (P9.0 to P9.3) Pin Functions

(1)

CONTROL BITS OR SIGNALS

PIN NAME (P9.x)

x

FUNCTION

P9DIR.x

P9SEL1.x

P9SEL0.x

LCDSz

P9.0 (I/O)

TA1.CCI0B

TA1.0

I: 0; O: 1

0

1

0

1

0

1

N/A

0

P9.0/TA1.0/LCDS20

P9.1/SMCLK/LCDS19

P9.2/MCLK/LCDS18

0

Internally tied to DVSS

N/A

1

0

Internally tied to DVSS

1

(2)

Sz

X

0

X

0

1

0

P9.1 (I/O)

I: 0; O: 1

N/A

0

1

0

1

0

Internally tied to DVSS

1

N/A

0

1

2

3

SMCLK

1

N/A

0

Internally tied to DVSS

1

(2)

Sz

X

0

X

0

1

0

P9.2 (I/O)

I: 0; O: 1

N/A

0

1

0

1

0

Internally tied to DVSS

1

N/A

0

MCLK

1

N/A

0

Internally tied to DVSS

1

(2)

Sz

X

0

X

0

1

0

P9.3 (I/O)

I: 0; O: 1

N/A

0

1

0

1

0

1

X

0

1

0

Internally tied to DVSS

N/A

P9.3/ACLK/LCDS17

(1) X = Don't care

ACLK

N/A

1

0

1

Internally tied to DVSS

(2)

Sz

X

(2) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节 4.1.

Detailed Description

131

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

6.14.19 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With

Schmitt Trigger

图 6-20 shows the port diagram. 表 6-42 summarizes the selection of the pin function.

To Comparator

From Comparator

Pad Logic

CBPD.x

JTAG enable

From JTAG

PJREN.x

0 0

0 1

1 0

1 1

PJDIR.x

module 1 or PxDIR.x

module 2 or PxDIR.x

module 3 or PxDIR.x

1

0

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PJOUT.x

1

0

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

PJSEL1.x

PJSEL0.x

PJIN.x

Bus

Keeper

EN

D

To modules

and JTAG

NOTE: Functional representation only.

图 6-20. Port PJ (PJ.0 to PJ.3) Diagram

132

Detailed Description

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 6-42. Port PJ (PJ.0 to PJ.3) Pin Functions

CONTROL BITS/ SIGNALS⁽¹⁾

PIN NAME (PJ.x)

x

FUNCTION

PJDIR.x

PJSEL1.x

PJSEL0.x

CEPDx (Cx)

PJ.0 (I/O)⁽²⁾

TDO⁽³⁾

N/A

I: 0; O: 1

0

X

0

1

0

1

0

ACLK

N/A

1

PJ.0/TDO/ACLK/SRSCG1/D

MAE0/C10

0

CPU Status Register Bit SCG1

1

DMAE0

0

Internally tied to DVSS

1

C10⁽⁴⁾

PJ.1 (I/O)⁽²⁾

TDI/TCLK^{(3) (5)}

X

0

X

0

1

0

I: 0; O: 1

X

N/A

0

1

0

1

0

SMCLK

1

PJ.1/TDI/TCLK/SMCLK/SRS

CG0/TA4CLK/C11

1

2

3

N/A

0

CPU Status Register Bit SCG0

1

TA4CLK

0

Internally tied to DVSS

1

C11⁽⁴⁾

PJ.2 (I/O)⁽²⁾

TMS^{(3) (5)}

X

0

X

0

1

0

I: 0; O: 1

X

N/A

0

1

0

1

0

MCLK

1

PJ.2/TMS/MCLK/SROSCOF

F/TB0OUTH/C12

N/A

0

CPU Status Register Bit OSCOFF

1

TB0OUTH

0

Internally tied to DVSS

1

C12⁽⁴⁾

PJ.3 (I/O)⁽²⁾

TCK^{(3) (5)}

X

0

X

0

1

0

I: 0; O: 1

X

0

1

0

1

0

1

X

N/A

0

1

0

RTCCLK

PJ.3/TCK/RTCCLK/SRCPU

OFF/TB0.6/C13

N/A

CPU Status Register Bit CPUOFF

TB0.CCI6A

TB0.6

C13⁽⁴⁾

1

0

1

X

(1) X = Don't care

(2) Default condition

(3) The pin direction is controlled by the JTAG module. JTAG mode selection is made through the SYS module or by the Spy-Bi-Wire four-

wire entry sequence. Neither PJSEL1.x and PJSEL0.x nor CEPDx bits have an effect in these cases.

(4) Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module

automatically disables The output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.

(5) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.

Detailed Description

133

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

6.14.20 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger

图 6-21 and 图 6-22 show the port diagrams. 表 6-43 summarizes the selection of the pin function.

Pad Logic

To LFXT XIN

PJREN.4

0 0

0 1

1 0

1 1

PJDIR.4

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PJOUT.4

DVSS

PJ.4/LFXIN

PJSEL1.4

PJSEL0.4

PJIN.4

Bus

Keeper

EN

D

To modules

NOTE: Functional representation only.

图 6-21. Port PJ (PJ.4) Diagram

134

Detailed Description

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

Pad Logic

To LFXT XOUT

PJSEL0.4

PJSEL1.4

LFXTBYPASS

PJREN.5

0 0

0 1

1 0

1 1

PJDIR.5

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PJOUT.5

DVSS

PJ.5/LFXOUT

PJSEL1.5

PJSEL0.5

PJIN.5

Bus

Keeper

EN

D

To modules

NOTE: Functional representation only.

图 6-22. Port PJ (PJ.5) Diagram

Detailed Description

135

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 6-43. Port PJ (PJ.4 and PJ.5) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME (PJ.x)

x

FUNCTION

PJ.4 (I/O)

LFXT

BYPASS

PJDIR.x

PJSEL1.5

PJSEL0.5

PJSEL1.4

PJSEL0.4

I: 0; O: 1

X

0

X

N/A

0

1

X

1

X

PJ.4/LFXIN

4

Internally tied to DVSS

LFXIN crystal mode⁽²⁾

LFXIN bypass mode⁽²⁾

X

0

1

X

0

1

X

0

1

X

0

1

0

1

0

1⁽³⁾

0

PJ.5 (I/O)

N/A

I: 0; O: 1

0

X

0

see⁽⁴⁾

X

0

PJ.5/LFXOUT

5

1⁽³⁾

0

Internally tied to DVSS

LFXOUT crystal mode⁽²⁾

1

see⁽⁴⁾

X

see⁽⁴⁾

X

1

1⁽³⁾

0

X

(1) X = Don't care

(2) If PJSEL1.4 = 0 and PJSEL0.4 = 1, the general-purpose I/O is disabled. When LFXTBYPASS = 0, PJ.4 and PJ.5 are configured for

crystal operation and PJSEL1.5 and PJSEL0.5 are don't care. When LFXTBYPASS = 1, PJ.4 is configured for bypass operation and

PJ.5 is configured as general-purpose I/O.

(3) When PJ.4 is configured in bypass mode, PJ.5 is configured as general-purpose I/O.

(4) If PJSEL0.5 = 1 or PJSEL1.5 = 1, the general-purpose I/O functionality is disabled. No input function is available. Configured as output,

the pin is actively pulled to zero.

136

Detailed Description

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

6.14.21 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger

图 6-23 and 图 6-24 show the port diagrams. 表 6-44 summarizes the selection of the pin function.

Pad Logic

To HFXT XIN

PJREN.6

0 0

0 1

1 0

1 1

PJDIR.6

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PJOUT.6

DVSS

PJ.6/HFXIN

PJSEL1.6

PJSEL0.6

PJIN.6

Bus

Keeper

EN

D

To modules

NOTE: Functional representation only.

图 6-23. Port PJ (PJ.6) Diagram

Detailed Description

137

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

Pad Logic

To HFXT XOUT

PJSEL0.6

PJSEL1.6

HFXTBYPASS

PJREN.7

0 0

0 1

1 0

1 1

PJDIR.7

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PJOUT.7

DVSS

PJ.7/HFXOUT

PJSEL1.7

PJSEL0.7

PJIN.7

Bus

Keeper

EN

D

To modules

NOTE: Functional representation only.

图 6-24. Port PJ (PJ.7) Diagram

138

Detailed Description

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 6-44. Port PJ (PJ.6 and PJ.7) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME (PJ.x)

x

FUNCTION

PJ.6 (I/O)

PJDIR.x

PJSEL1.7

PJSEL0.7

PJSEL1.6

PJSEL0.6 HFXTBYPASS

I: 0; O: 1

X

0

X

N/A

0

1

X

1

X

PJ.6/HFXIN

6

Internally tied to DVSS

HFXIN crystal mode⁽²⁾

HFXIN bypass mode⁽²⁾

X

0

1

X

0

1

X

0

1

X

0

1

0

1

0

1⁽⁴⁾

0

PJ.7 (I/O)⁽³⁾

I: 0; O: 1

0

X

0

(3)

N/A

0

see

X

0

PJ.7/HFXOUT

7

1⁽⁴⁾

0

(3)

Internally tied to DVSS

HFXOUT crystal mode⁽²⁾

1

see

X

1

1⁽⁴⁾

0

X

(1) X = Don't care

(2) Setting PJSEL1.6 = 0 and PJSEL0.6 = 1 causes the general-purpose I/O to be disabled. When HFXTBYPASS = 0, PJ.6 and PJ.7 are

configured for crystal operation and PJSEL1.6 and PJSEL0.7 are do not care. When HFXTBYPASS = 1, PJ.6 is configured for bypass

operation and PJ.7 is configured as general-purpose I/O.

(3) With PJSEL0.7 = 1 or PJSEL1.7 =1 the general-purpose I/O functionality is disabled. No input function is available. Configured as output

the pin is actively pulled to zero.

(4) When PJ.6 is configured in bypass mode, PJ.7 is configured as general-purpose I/O.

Detailed Description

139

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

6.15 Device Descriptors (TLV)

表 6-45 lists the Device IDs.

表 6-45. Device IDs

DEVICE ID

DEVICE

PACKAGE

01A05h

82h

01A04h

EAh

MSP430FR6047

MSP430FR60471

MSP430FR6045

MSP430FR6037

MSP430FR60371

MSP430FR6035

PZ

82h

EEh

82h

EBh

82h

ECh

EFh

82h

EDh

表 6-46 lists the contents of the device descriptor tag-length-value (TLV) structure.

表 6-46. Device Descriptors⁽¹⁾

MSP430FR60xx (UART BSL)

MSP430FR60xx1 (I²C BSL)

DESCRIPTION

ADDRESS

01A00h

01A01h

01A02h

01A03h

01A04h

01A05h

01A06h

01A07h

01A08h

01A09h

01A0Ah

01A0Bh

01A0Ch

01A0Dh

01A0Eh

01A0Fh

01A10h

01A11h

01A12h

01A13h

VALUE

06h

ADDRESS

01A00h

01A01h

01A02h

01A03h

VALUE

06h

Info length

CRC length

06h

Per unit

CRC value

Device ID

Info Block

See 表 6-45.

01A04h

See 表 6-45.

Hardware revision

Firmware revision

Die record tag

Per unit

08h

01A06h

01A07h

01A08h

01A09h

01A0Ah

01A0Bh

01A0Ch

01A0Dh

01A0Eh

01A0Fh

01A10h

01A11h

01A12h

01A13h

Per unit

08h

Die record length

0Ah

Per unit

Lot/wafer ID

Die Record

Die X position

Die Y position

Test results

(1) NA = Not applicable, Per unit = content can differ from device to device

140 Detailed Description

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 6-46. Device Descriptors⁽¹⁾(continued)

MSP430FR60xx (UART BSL)

MSP430FR60xx1 (I²C BSL)

DESCRIPTION

ADDRESS

01A14h

01A15h

01A16h

01A17h

01A18h

01A19h

01A1Ah

01A1Bh

01A1Ch

01A1Dh

01A1Eh

01A1Fh

01A20h

01A21h

01A22h

01A23h

01A24h

01A25h

01A26h

01A27h

01A28h

01A29h

01A2Ah

01A2Bh

01A2Ch

01A2Dh

VALUE

11h

ADDRESS

01A14h

01A15h

01A16h

01A17h

01A18h

01A19h

01A1Ah

01A1Bh

01A1Ch

01A1Dh

01A1Eh

01A1Fh

01A20h

01A21h

01A22h

01A23h

01A24h

01A25h

01A26h

01A27h

01A28h

01A29h

01A2Ah

01A2Bh

01A2Ch

01A2Dh

VALUE

11h

ADC12 calibration tag

ADC12 calibration length

10h

Per unit

12h

Per unit

12h

ADC gain factor⁽²⁾

ADC offset⁽³⁾

ADC 1.2-V reference

temperature sensor 30°C

ADC 1.2-V reference

temperature sensor 85°C

ADC12 Calibration

ADC 2.0-V reference

temperature sensor 30°C

ADC 2.0-V reference

temperature sensor 85°C

ADC 2.5-V reference

temperature sensor 30°C

ADC 2.5-V reference

temperature sensor 85°C

REF calibration tag

REF calibration length

06h

Per unit

REF 1.2-V reference

REF 2.0-V reference

REF 2.5-V reference

REF Calibration

(2) ADC gain: The gain correction factor is measured at room temperature using a 2.5-V external voltage reference without internal buffer

(ADC12VRSEL = 0x2, 0x4, or 0xE). Other settings (for example, using internal reference) can result in different correction factors.

(3) ADC offset: the offset correction factor is measured at room temperature using ADC12VRSEL= 0x2 or 0x4, an external reference, V_R+

external 2.5 V, V_R–= AVSS.

=

Detailed Description

141

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

表 6-46. Device Descriptors⁽¹⁾(continued)

MSP430FR60xx (UART BSL)

MSP430FR60xx1 (I²C BSL)

DESCRIPTION

ADDRESS

01A2Eh

01A2Fh

01A30h

01A31h

01A32h

01A33h

01A34h

01A35h

01A36h

01A37h

01A38h

01A39h

01A3Ah

01A3Bh

01A3Ch

01A3Dh

01A3Eh

01A3Fh

01A40h

01A41h

01A42h

01A43h

VALUE

15h

ADDRESS

01A2Eh

01A2Fh

01A30h

01A31h

01A32h

01A33h

01A34h

01A35h

01A36h

01A37h

01A38h

01A39h

01A3Ah

01A3Bh

01A3Ch

01A3Dh

01A3Eh

01A3Fh

01A40h

01A41h

01A42h

01A43h

VALUE

15h

128-bit random number tag

Random number length

10h

Per unit

1Ch

Per unit

1Ch

Random Number

128-bit random number⁽⁴⁾

BSL tag

BSL length

02h

BSL Configuration

BSL interface

00h

01h

BSL interface configuration

00h

48h

(4) 128-bit random number: The random number is generated during production test using the Microsoft^®CryptGenRandom() function.

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6.16 Memory Map

表 6-47 summarizes the memory organization for all device variants.

表 6-47. Memory Organization⁽¹⁾

MSP430FR6047(1), FR6037(1)

MSP430FR6045, FR6035

Memory (FRAM)

Total Size

256KB

128KB

Main: interrupt vectors and

signatures

00FFFFh to 00FF80h

043FFFh to 004000h

00FFFFh to 00FF80h

0023FFFh to 004000h

Main: code memory

RAM (shared with LEA)

(Sector 2)

Block 0

Size

4KB

(003BFFh to 002C00h)

003BFFh to 002C00h

(003BFFh to 002C00h)

003BFFh to 002C00h

System RAM

4KB

(Sector 1)

(Sector 0)

Main: base location

Main: interrupt vectors

(002BFFh to 002400h)

(0023FFh to 001C00h)

002BFFh to 001C00h

002BFFh to 002B80h

(002BFFh to 002400h)

(0023FFh to 001C00h)

002BFFh to 001C00h

002BFFh to 002B80h

Device descriptor info (TLV)

(FRAM)

Size

256 B

001AFFh to 001A00h

256 B

001AFFh to 001A00h

TI calibration and configuration

(FRAM)

256 B

0019FFh to 001900h

256 B

0019FFh to 001900h

BSL 3

BSL 2

BSL 1

BSL 0

Size

512 B

0017FFh to 001600h

512 B

0017FFh to 001600h

512 B

0015FFh to 001400h

512 B

0015FFh to 001400h

Bootloader (BSL) memory (ROM)

512 B

0013FFh to 001200h

512 B

0013FFh to 001200h

512 B

0011FFh to 001000h

512 B

0011FFh to 001000h

4KB

Peripherals

Tiny RAM

Reserved

000FFFh to 000020h

Size

22 B

000001Fh to 00000Ah

Size

10 B

000009h to 000000h

(1) All address space not listed is considered vacant memory.

Detailed Description

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6.16.1 Peripheral File Map

For complete module register descriptions, see the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx

Family User's Guide. Table 6-48 lists the base and end addresses of the registers for each peripheral.

Table 6-48. Peripherals

MODULE NAME

Special Functions (see Table 6-49)

PMM (see Table 6-50)

BASE ADDRESS

0100h

0120h

0140h

0150h

0158h

015Ch

0160h

0180h

01B0h

0200h

0340h

0380h

03C0h

0400h

0440h

04A0h

04C0h

0500h

05A0h

05C0h

05E0h

0600h

0620h

0640h

0680h

07C0h

0800h

08C0h

0980h

09C0h

0A00h

0A80h

0E00h

0E80h

0EC0h

0EE0h

0F00h

END ADDRESS

011Fh

013Fh

014Fh

0157h

0159h

015Dh

016Fh

019Fh

01B1h

033Fh

036Fh

03AFh

03EFh

042Fh

046Fh

04BFh

04EFh

056Fh

05AFh

05DFh

05FFh

061Fh

063Fh

066Fh

06AFh

07EFh

089Fh

08CFh

09AFh

09CFh

0A5Fh

0AFFh

0E7Fh

0EBFh

0EDFh

0EFFh

0F1Fh

FRAM Control (see Table 6-51)

CRC (see Table 6-52)

RAM Control (see Table 6-53)

Watchdog (see Table 6-54)

CS (see Table 6-55)

SYS (see Table 6-56)

Shared Reference (see Table 6-57)

Digital I/O (see Table 6-58)

TA0 (see Table 6-59)

TA1 (see Table 6-60)

TB0 (see Table 6-61)

TA2 (see Table 6-62)

TA3 (see Table 6-63)

RTC_C (see Table 6-64)

32-Bit Hardware Multiplier (see Table 6-65)

DMA (see Table 6-66)

MPU Control (see Table 6-67)

eUSCI_A0 (see Table 6-68)

eUSCI_A1 (see Table 6-69)

eUSCI_A2 (see Table 6-70)

eUSCI_A3 (see Table 6-71)

eUSCI_B0 (see Table 6-72)

eUSCI_B1 (see Table 6-73)

TA4 (see Table 6-74)

ADC12_B (see Table 6-75)

Comparator E (see Table 6-76)

CRC32 (see Table 6-77)

AES256 (see Table 6-78)

LCD_C (see Table 6-79)

LEA (see Table 6-80)

SAPH⁽¹⁾(see Table 6-81)

SDHS⁽¹⁾(see Table 6-82)

UUPS⁽¹⁾(see Table 6-83)

HSPLL⁽¹⁾(see Table 6-84)

MTIF (see Table 6-85)

(1) Not available in MSP430FR6037, MSP430FR6035, and MSP430FR60371

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Table 6-49. Special Functions Registers

REGISTER DESCRIPTION

ACRONYM

ADDRESS

Interrupt Enable

Interrupt Flag

SFRIE1

0100h

0102h

0104h

SFRIFG1

SFRRPCR

Reset Pin Control

Table 6-50. PMM Registers

REGISTER DESCRIPTION

ACRONYM

PMM Control 0

PMMCTL0

PMMIFG

0120h

012Ah

0130h

PMM Interrupt Flag

Power Mode 5 Control 0

PM5CTL0

Table 6-51. FRAM Control Registers

REGISTER DESCRIPTION

ACRONYM

FRAM Controller A Control 0

General Control 0

FRCTL0

GCCTL0

GCCTL1

0140h

0144h

0146h

General Control 1

Table 6-52. CRC Registers

REGISTER DESCRIPTION

ACRONYM

CRC Data In

CRCDI

0150h

0152h

0154h

0156h

CRC Data In Reverse Byte

CRC Initialization and Result

CRC Result Reverse

CRCDIRB

CRCINIRES

CRCRESR

Table 6-53. RAM Control Registers

REGISTER DESCRIPTION

ACRONYM

ADDRESS

RAM Controller Control 0

RAM Controller Control 1

RCCTL0

RCCTL1

0158h

015Ah

Table 6-54. Watchdog Registers

REGISTER DESCRIPTION

ACRONYM

WDTCTL

ADDRESS

Watchdog Timer Control

015Ch

Table 6-55. CS Registers

REGISTER DESCRIPTION

ACRONYM

Clock System Control 0

Clock System Control 1

Clock System Control 2

Clock System Control 3

Clock System Control 4

Clock System Control 5

Clock System Control 6

CSCTL0

CSCTL1

CSCTL2

CSCTL3

CSCTL4

CSCTL5

CSCTL6

0160h

0162h

0164h

0166h

0168h

016Ah

016Ch

Detailed Description

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Table 6-56. SYS Registers

REGISTER DESCRIPTION

ACRONYM

SYSCTL

ADDRESS

System Control

0180h

0186h

0188h

018Ah

018Ch

018Eh

019Ah

019Ch

019Eh

JTAG Mailbox Control

JTAG Mailbox Input

JTAG Mailbox Output

User NMI Vector Generator

SYSJMBC

SYSJMBI0

SYSJMBI1

SYSJMBO0

SYSJMBO1

SYSUNIV

System NMI Vector Generator

Reset Vector Generator

SYSSNIV

SYSRSTIV

Table 6-57. Shared Reference Registers

REGISTER DESCRIPTION

ACRONYM

REFCTL0

ADDRESS

REF Control 0

01B0h

Table 6-58. Digital I/O Registers

REGISTER DESCRIPTION

ACRONYM

Port A Input

PAIN

0200h

0201h

0202h

0203h

0204h

0205h

0206h

0207h

020Ah

020Bh

020Ch

020Dh

020Eh

0216h

0217h

0218h

0219h

021Ah

021Bh

021Ch

021Dh

Port 1 Input

P1IN

Port 2 Input

P2IN

Port A Output

PAOUT

P1OUT

P2OUT

PADIR

P1DIR

P2DIR

PAREN

P1REN

P2REN

PASEL0

P1SEL0

P2SEL0

PASEL1

P1SEL1

P2SEL1

P1IV

Port 1 Output

Port 2 Output

Port A Direction

Port 1 Direction

Port 2 Direction

Port A Resistor Enable

Port 1 Resistor Enable

Port 2 Resistor Enable

Port A Select 0

Port 1 Select 0

Port 2 Select 0

Port A Select 1

Port 1 Select 1

Port 2 Select 1

Port 1 Interrupt Vector

Port A Complement Select

Port 1 Complement Select

Port 2 Complement Select

Port A Interrupt Edge Select

Port 1 Interrupt Edge Select

Port 2 Interrupt Edge Select

Port A Interrupt Enable

Port 1 Interrupt Enable

Port 2 Interrupt Enable

Port A Interrupt Flag

Port 1 Interrupt Flag

Port 2 Interrupt Flag

PASELC

P1SELC

P2SELC

PAIES

P1IES

P2IES

PAIE

P1IE

P2IE

PAIFG

P1IFG

P2IFG

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Table 6-58. Digital I/O Registers (continued)

REGISTER DESCRIPTION

ACRONYM

ADDRESS

Port 2 Interrupt Vector

Port B Input

P2IV

021Eh

0220h

0221h

0222h

0223h

0224h

0225h

0226h

0227h

022Ah

022Bh

022Ch

022Dh

022Eh

0236h

0237h

0238h

0239h

023Ah

023Bh

023Ch

023Dh

023Eh

0240h

0241h

0242h

0243h

0244h

0245h

0246h

0247h

024Ah

PBIN

Port 3 Input

P3IN

Port 4 Input

P4IN

Port B Output

PBOUT

P3OUT

P4OUT

PBDIR

P3DIR

P4DIR

PBREN

P3REN

P4REN

PBSEL0

P3SEL0

P4SEL0

PBSEL1

P3SEL1

P4SEL1

P3IV

Port 3 Output

Port 4 Output

Port B Direction

Port 3 Direction

Port 4 Direction

Port B Resistor Enable

Port 3 Resistor Enable

Port 4 Resistor Enable

Port B Select 0

Port 3 Select 0

Port 4 Select 0

Port B Select 1

Port 3 Select 1

Port 4 Select 1

Port 3 Interrupt Vector

Port B Complement Select

Port 3 Complement Select

Port 4 Complement Select

Port B Interrupt Edge Select

Port 3 Interrupt Edge Select

Port 4 Interrupt Edge Select

Port B Interrupt Enable

Port 3 Interrupt Enable

Port 4 Interrupt Enable

Port B Interrupt Flag

Port 3 Interrupt Flag

Port 4 Interrupt Flag

Port 4 Interrupt Vector

Port C Input

PBSELC

P3SELC

P4SELC

PBIES

P3IES

P4IES

PBIE

P3IE

P4IE

PBIFG

P3IFG

P4IFG

P4IV

PCIN

Port 5 Input

P5IN

Port 6 Input

P6IN

Port C Output

PCOUT

P5OUT

P6OUT

PCDIR

P5DIR

P6DIR

PCREN

P5REN

P6REN

PCSEL0

P5SEL0

Port 5 Output

Port 6 Output

Port C Direction

Port 5 Direction

Port 6 Direction

Port C Resistor Enable

Port 5 Resistor Enable

Port 6 Resistor Enable

Port C Select 0

Port 5 Select 0

Detailed Description

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Table 6-58. Digital I/O Registers (continued)

REGISTER DESCRIPTION

ACRONYM

P6SEL0

ADDRESS

Port 6 Select 0

024Bh

024Ch

024Dh

024Eh

0256h

0257h

0258h

0259h

025Ah

025Bh

025Ch

025Dh

025Eh

0260h

0261h

0262h

0263h

0264h

0265h

0266h

0267h

026Ah

026Bh

026Ch

026Dh

026Eh

0276h

0277h

0278h

0279h

027Ah

027Bh

027Ch

Port C Select 1

PCSEL1

P5SEL1

P6SEL1

P5IV

Port 5 Select 1

Port 6 Select 1

Port 5 Interrupt Vector

Port C Complement Select

Port 5 Complement Select

Port 6 Complement Select

Port C Interrupt Edge Select

Port 5 Interrupt Edge Select

Port 6 Interrupt Edge Select

Port C Interrupt Enable

Port 5 Interrupt Enable

Port 6 Interrupt Enable

Port C Interrupt Flag

Port 5 Interrupt Flag

Port 6 Interrupt Flag

Port 6 Interrupt Vector

Port D Input

PCSELC

P5SELC

P6SELC

PCIES

P5IES

P6IES

PCIE

P5IE

P6IE

PCIFG

P5IFG

P6IFG

P6IV

PDIN

Port 7 Input

P7IN

Port 8 Input

P8IN

Port D Output

PDOUT

P7OUT

P8OUT

PDDIR

P7DIR

P8DIR

PDREN

P7REN

P8REN

PDSEL0

P7SEL0

P8SEL0

PDSEL1

P7SEL1

P8SEL1

P7IV

Port 7 Output

Port 8 Output

Port D Direction

Port 7 Direction

Port 8 Direction

Port D Resistor Enable

Port 7 Resistor Enable

Port 8 Resistor Enable

Port D Select 0

Port 7 Select 0

Port 8 Select 0

Port D Select 1

Port 7 Select 1

Port 8 Select 1

Port 7 Interrupt Vector

Port D Complement Select

Port 7 Complement Select

Port 8 Complement Select

Port D Interrupt Edge Select

Port 7 Interrupt Edge Select

Port 8 Interrupt Edge Select

Port D Interrupt Enable

Port 7 Interrupt Enable

Port 8 Interrupt Enable

Port D Interrupt Flag

PDSELC

P7SELC

P8SELC

PDIES

P7IES

P8IES

PDIE

P7IE

P8IE

PDIFG

148

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Table 6-58. Digital I/O Registers (continued)

REGISTER DESCRIPTION

ACRONYM

ADDRESS

Port 7 Interrupt Flag

Port 8 Interrupt Flag

Port 8 Interrupt Vector

Port E Input

P7IFG

P8IFG

P8IV

027Ch

027Dh

027Eh

0280h

0282h

0284h

0286h

028Ah

028Ch

028Eh

0296h

0298h

029Ah

029Ch

0320h

0322h

0324h

0326h

032Ah

032Ch

0336h

PEIN

Port 9 Input

P9IN

Port E Output

PEOUT

P9OUT

PEDIR

P9DIR

PEREN

P9REN

PESEL0

P9SEL0

PESEL1

P9SEL1

P9IV

Port 9 Output

Port E Direction

Port 9 Direction

Port E Resistor Enable

Port 9 Resistor Enable

Port E Select 0

Port 9 Select 0

Port E Select 1

Port 9 Select 1

Port 9 Interrupt Vector

Port E Complement Select

Port 9 Complement Select

Port E Interrupt Edge Select

Port 9 Interrupt Edge Select

Port E Interrupt Enable

Port 9 Interrupt Enable

Port E Interrupt Flag

Port 9 Interrupt Flag

Port J Input

PESELC

P9SELC

PEIES

P9IES

PEIE

P9IE

PEIFG

P9IFG

PJIN

Port J Output

PJOUT

PJDIR

PJREN

PJSEL0

PJSEL1

PJSELC

Port J Direction

Port J Resistor Enable

Port J Select 0

Port J Select 1

Port J Complement Select

Detailed Description

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Table 6-59. TA0 Registers

REGISTER DESCRIPTION

ACRONYM

TA0CTL

ADDRESS

Timer_A0 Control

0340h

0342h

0344h

0346h

0350h

0352h

0354h

0356h

0360h

036Eh

Timer_A0 Capture/Compare Control

Timer_A0 Counter

TA0CCTL0

TA0CCTL1

TA0CCTL2

TA0R

Timer_A0 Capture/Compare

Timer_A0 Expansion 0

TA0CCR0

TA0CCR1

TA0CCR2

TA0EX0

Timer_A0 Interrupt Vector

TA0IV

Table 6-60. TA1 Registers

REGISTER DESCRIPTION

ACRONYM

ADDRESS

Timer_A1 Control

TA1CTL

0380h

0382h

0384h

0386h

0390h

0392h

0394h

0396h

03A0h

03AEh

Timer_A1 Capture/Compare Control

Timer_A1 Counter

TA1CCTL0

TA1CCTL1

TA1CCTL2

TA1R

Timer_A1 Capture/Compare

Timer_A1 Expansion 0

TA1CCR0

TA1CCR1

TA1CCR2

TA1EX0

Timer_A1 Interrupt Vector

TA1IV

Table 6-61. TB0 Registers

REGISTER DESCRIPTION

ACRONYM

ADDRESS

Timer_B0 Control

TB0CTL

03C0h

03C2h

03C4h

03C6h

03C8h

03CAh

03CCh

03CEh

03D0h

03D2h

03D4h

03D6h

03D8h

03DAh

03DCh

03DEh

03E0h

03EEh

Timer_B0 Capture/Compare Control

Timer_B0 Counter

TB0CCTL0

TB0CCTL1

TB0CCTL2

TB0CCTL3

TB0CCTL4

TB0CCTL5

TB0CCTL6

TB0R

Timer_B0 Capture/Compare

Timer_B0 Expansion 0

TB0CCR0

TB0CCR1

TB0CCR2

TB0CCR3

TB0CCR4

TB0CCR5

TB0CCR6

TB0EX0

Timer_B0 Interrupt Vector

TB0IV

150

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Table 6-62. TA2 Registers

REGISTER DESCRIPTION

ACRONYM

TA2CTL

ADDRESS

Timer_A2 Control

0400h

0402h

0404h

0410h

0412h

0414h

0420h

042Eh

Timer_A2 Capture/Compare Control

Timer_A2 Counter

TA2CCTL0

TA2CCTL1

TA2R

Timer_A2 Capture/Compare

Timer_A2 Expansion 0

TA2CCR0

TA2CCR1

TA2EX0

TA2IV

Timer_A2 Interrupt Vector

Table 6-63. TA3 Registers

REGISTER DESCRIPTION

ACRONYM

Timer_A3 Control

TA3CTL

TA3CCTL0

TA3CCTL1

TA3R

0440h

0442h

0444h

0450h

0452h

0454h

0460h

046Eh

Timer_A3 Capture/Compare Control

Timer_A3 Counter

Timer_A3 Capture/Compare

Timer_A3 Expansion 0

TA3CCR0

TA3CCR1

TA3EX0

TA3IV

Timer_A3 Interrupt Vector

Table 6-64. RTC_C Registers

REGISTER DESCRIPTION

ACRONYM

Real-Time Clock Control 0

RTCCTL0

RTCCTL13

RTCOCAL

RTCTCMP

RTCPS0CTL

RTCPS1CTL

RTCPS

04A0h

04A2h

04A4h

04A6h

04A8h

04AAh

04ACh

04ADh

04AEh

04B0h

04B2h

04B4h

04B6h

04B8h

04BAh

04BCh

04BEh

Real-Time Clock Control 1, 3

Real-Time Clock Offset Calibration

Real-Time Clock Temperature Compensation

Real-Time Clock Prescale Timer 0 Control

Real-Time Clock Prescale Timer 1 Control

Real-Time Clock Prescale Timer Counter

Prescale Timer 0 Counter Value

Prescale Timer 1 Counter Value

Real-Time Clock Interrupt Vector

Real-Time Clock Seconds and Minutes

Real-Time Clock Hour, Day of Week

Real-Time Clock Date

RT0PS

RT1PS

RTCIV

RTCTIM0

RTCTIM1

RTCDATE

RTCYEAR

RTCAMINHR

RTCADOWDAY

BIN2BCD

BCD2BIN

Real-Time Clock Year

Real-Time Clock Minute and Hour

Real-Time Clock Alarm Day of Week and Day

Binary-to-BCD Conversion

BCD-to-Binary Conversion

Detailed Description

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Table 6-65. 32-Bit Hardware Multiplier Registers

REGISTER DESCRIPTION

16-bit operand one – multiply

ACRONYM

ADDRESS

MPY

04C0h

04C2h

04C4h

04C6h

04C8h

04CAh

04CCh

04CEh

04D0h

04D2h

04D4h

04D6h

04D8h

04DAh

04DCh

04DEh

04E0h

04E2h

04E4h

04E6h

04E8h

04EAh

04ECh

16-bit operand one – signed multiply

16-bit operand one – multiply accumulate

16-bit operand one – signed multiply accumulate

16-bit operand two

MPYS

MAC

MACS

OP2

16x16-bit result low word

RESLO

RESHI

16x16-bit result high word

16x16-bit sum extension

SUMEXT

MPY32L

MPY32H

MPYS32L

MPYS32H

MAC32L

MAC32H

MACS32L

MACS32H

OP2L

32-bit operand 1 – multiply – low word

32-bit operand 1 – multiply – high word

32-bit operand 1 – signed multiply – low word

32-bit operand 1 – signed multiply – high word

32-bit operand 1 – multiply accumulate – low word

32-bit operand 1 – multiply accumulate – high word

32-bit operand 1 – signed multiply accumulate – low word

32-bit operand 1 – signed multiply accumulate – high word

32-bit operand 2 – low word

32-bit operand 2 – high word

OP2H

32x32-bit result 0 – least significant word

32x32-bit result 1

RES0

RES1

32x32-bit result 2

RES2

32x32-bit result 3 – most significant word

MPY32 control 0

RES3

MPY32CTL0

152

Detailed Description

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ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

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Table 6-66. DMA Registers

REGISTER DESCRIPTION

ACRONYM

DMACTL0

ADDRESS

DMA Control 0

0500h

0502h

0504h

0508h

050Eh

0510h

0512h

0516h

051Ah

0520h

0522h

0526h

052Ah

0530h

0532h

0536h

053Ah

0540h

0542h

0546h

054Ah

0550h

0552h

0556h

055Ah

0560h

0562h

0566h

056Ah

DMA Control 1

DMACTL1

DMACTL2

DMACTL4

DMAIV

DMA Control 2

DMA Control 4

DMA Interrupt Vector

DMA Channel 0 Control

DMA0CTL

DMA0SA

DMA0DA

DMA0SZ

DMA1CTL

DMA1SA

DMA1DA

DMA1SZ

DMA2CTL

DMA2SA

DMA2DA

DMA2SZ

DMA3CTL

DMA3SA

DMA3DA

DMA3SZ

DMA4CTL

DMA4SA

DMA4DA

DMA4SZ

DMA5CTL

DMA5SA

DMA5DA

DMA5SZ

DMA Channel 0 Source Address

DMA Channel 0 Destination Address

DMA Channel 0 Transfer Size

DMA Channel 1 Control

DMA Channel 1 Source Address

DMA Channel 1 Destination Address

DMA Channel 1 Transfer Size

DMA Channel 2 Control

DMA Channel 2 Source Address

DMA Channel 2 Destination Address

DMA Channel 2 Transfer Size

DMA Channel 3 Control

DMA Channel 3 Source Address

DMA Channel 3 Destination Address

DMA Channel 3 Transfer Size

DMA Channel 4 Control

DMA Channel 4 Source Address

DMA Channel 4 Destination Address

DMA Channel 4 Transfer Size

DMA Channel 5 Control

DMA Channel 5 Source Address

DMA Channel 5 Destination Address

DMA Channel 5 Transfer Size

Table 6-67. MPU Control Registers

REGISTER DESCRIPTION

ACRONYM

ADDRESS

Memory Protection Unit Control 0

MPUCTL0

05A0h

05A2h

05A4h

05A6h

05A8h

05AAh

05ACh

05AEh

Memory Protection Unit Control 1

MPUCTL1

Memory Protection Unit Segmentation Border 2 Register

Memory Protection Unit Segmentation Border 1 Register

Memory Protection Unit Segmentation Access Management Register

Memory Protection Unit IP Control 0 Register

MPUSEGB2

MPUSEGB1

MPUSAM

MPUIPC0

Memory Protection Unit IP Encapsulation Segment Border 2 Register

Memory Protection Unit IP Encapsulation Segment Border 1 Register

MPUIPSEGB2

MPUIPSEGB1

Detailed Description

153

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ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

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Table 6-68. eUSCI_A0 Registers

REGISTER DESCRIPTION

eUSCI_A0 Control Word Register 0

ACRONYM

UCA0CTLW0

ADDRESS

05C0h

05C2h

05C6h

05C8h

05CAh

05CCh

05CEh

05D0h

05D2h

05DAh

05DCh

05DEh

eUSCI_A0 Control Word Register 1

eUSCI_A0 Baud Rate Control Word

eUSCI_A0 Modulation Control Word

eUSCI_A0 Status Register

UCA0CTLW1

UCA0BRW

UCA0MCTLW

UCA0STATW

UCA0RXBUF

UCA0TXBUF

UCA0ABCTL

UCA0IRCTL

UCA0IE

eUSCI_A0 Receive Buffer

eUSCI_A0 Transmit Buffer

eUSCI_A0 Auto Baud Rate Control

eUSCI_A0 IrDA Control Word

eUSCI_A0 Interrupt Enable

eUSCI_A0 Interrupt Flag

UCA0IFG

eUSCI_A0 Interrupt Vector

UCA0IV

Table 6-69. eUSCI_A1 Registers

REGISTER DESCRIPTION

ACRONYM

ADDRESS

eUSCI_A1 Control Word Register 0

eUSCI_A1 Control Word Register 1

eUSCI_A1 Baud Rate Control Word

eUSCI_A1 Modulation Control Word

eUSCI_A1 Status Register

UCA1CTLW0

UCA1CTLW1

UCA1BRW

UCA1MCTLW

UCA1STATW

UCA1RXBUF

UCA1TXBUF

UCA1ABCTL

UCA1IRCTL

UCA1IE

05E0h

05E2h

05E6h

05E8h

05EAh

05ECh

05EEh

05F0h

05F2h

05FAh

05FCh

05FEh

eUSCI_A1 Receive Buffer

eUSCI_A1 Transmit Buffer

eUSCI_A1 Auto Baud Rate Control

eUSCI_A1 IrDA Control Word

eUSCI_A1 Interrupt Enable

eUSCI_A1 Interrupt Flag

UCA1IFG

eUSCI_A1 Interrupt Vector

UCA1IV

Table 6-70. eUSCI_A2 Registers

REGISTER DESCRIPTION

ACRONYM

ADDRESS

eUSCI_A2 Control Word Register 0

eUSCI_A2 Control Word Register 1

eUSCI_A2 Baud Rate Control Word

eUSCI_A2 Modulation Control Word

eUSCI_A2 Status Register

UCA2CTLW0

UCA2CTLW1

UCA2BRW

UCA2MCTLW

UCA2STATW

UCA2RXBUF

UCA2TXBUF

UCA2ABCTL

UCA2IRCTL

UCA2IE

0600h

0602h

0606h

0608h

060Ah

060Ch

060Eh

0610h

0612h

061Ah

061Ch

061Eh

eUSCI_A2 Receive Buffer

eUSCI_A2 Transmit Buffer

eUSCI_A2 Auto Baud Rate Control

eUSCI_A2 IrDA Control Word

eUSCI_A2 Interrupt Enable

eUSCI_A2 Interrupt Flag

UCA2IFG

eUSCI_A2 Interrupt Vector

UCA2IV

154

Detailed Description

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ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

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Table 6-71. eUSCI_A3 Registers

REGISTER DESCRIPTION

ACRONYM

UCA3CTLW0

ADDRESS

eUSCI_A3 Control Word Register 0

eUSCI_A3 Control Word Register 1

eUSCI_A3 Baud Rate Control Word

eUSCI_A3 Modulation Control Word

eUSCI_A3 Status Register

0620h

0622h

0626h

0628h

062Ah

062Ch

062Eh

0630h

0632h

063Ah

063Ch

063Eh

UCA3CTLW1

UCA3BRW

UCA3MCTLW

UCA3STATW

UCA3RXBUF

UCA3TXBUF

UCA3ABCTL

UCA3IRCTL

UCA3IE

eUSCI_A3 Receive Buffer

eUSCI_A3 Transmit Buffer

eUSCI_A3 Auto Baud Rate Control

eUSCI_A3 IrDA Control Word

eUSCI_A3 Interrupt Enable

eUSCI_A3 Interrupt Flag

UCA3IFG

eUSCI_A3 Interrupt Vector

UCA3IV

Table 6-72. eUSCI_B0 Registers

REGISTER DESCRIPTION

ACRONYM

ADDRESS

eUSCI_B0 Control Word Register 0

eUSCI_B0 Control Word Register 1

eUSCI_B0 Baud Rate Control Word

eUSCI_B0 Status Register

UCB0CTLW0

UCB0CTLW1

UCB0BRW

0640h

0642h

0646h

0648h

064Ah

064Ch

064Eh

0654h

0656h

0658h

065Ah

065Ch

065Eh

0660h

066Ah

066Ch

066Eh

UCB0STATW

UCB0TBCNT

UCB0RXBUF

UCB0TXBUF

UCB0I2COA0

UCB0I2COA1

UCB0I2COA2

UCB0I2COA3

UCB0ADDRX

UCB0ADDMASK

UCB0I2CSA

UCB0IE

eUSCI_B0 Byte Counter Threshold

eUSCI_B0 Receive Buffer

eUSCI_B0 Transmit Buffer

eUSCI_B0 I2C Own Address 0

eUSCI_B0 I2C Own Address 1

eUSCI_B0 I2C Own Address 2

eUSCI_B0 I2C Own Address 3

eUSCI_B0 I2C Received Address

eUSCI_B0 I2C Address Mask

eUSCI_B0 I2C Slave Address

eUSCI_B0 Interrupt Enable

eUSCI_B0 Interrupt Flag

UCB0IFG

eUSCI_B0 Interrupt Vector

UCB0IV

Detailed Description

155

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ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

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Table 6-73. eUSCI_B1 Registers

REGISTER DESCRIPTION

eUSCI_B1 Control Word Register 0

ACRONYM

UCB1CTLW0

ADDRESS

0680h

0682h

0686h

0688h

068Ah

068Ch

068Eh

0694h

0696h

0698h

069Ah

069Ch

069Eh

06A0h

06AAh

06ACh

06AEh

eUSCI_B1 Control Word Register 1

eUSCI_B1 Baud Rate Control Word

eUSCI_B1 Status Register

UCB1CTLW1

UCB1BRW

UCB1STATW

UCB1TBCNT

UCB1RXBUF

UCB1TXBUF

UCB1I2COA0

UCB1I2COA1

UCB1I2COA2

UCB1I2COA3

UCB1ADDRX

UCB1ADDMASK

UCB1I2CSA

UCB1IE

eUSCI_B1 Byte Counter Threshold

eUSCI_B1 Receive Buffer

eUSCI_B1 Transmit Buffer

eUSCI_B1 I2C Own Address 0

eUSCI_B1 I2C Own Address 1

eUSCI_B1 I2C Own Address 2

eUSCI_B1 I2C Own Address 3

eUSCI_B1 I2C Received Address

eUSCI_B1 I2C Address Mask

eUSCI_B1 I2C Slave Address

eUSCI_B1 Interrupt Enable

eUSCI_B1 Interrupt Flag

UCB1IFG

eUSCI_B1 Interrupt Vector

UCB1IV

Table 6-74. TA4 Registers

REGISTER DESCRIPTION

ACRONYM

TA4CTL

ADDRESS

Timer_A4 Control

07C0h

07C2h

07C4h

07D0h

07D2h

07D4h

07E0h

07EEh

Timer_A4 Capture/Compare Control

Timer_A4 Counter

TA4CCTL0

TA4CCTL1

TA4R

Timer_A4 Capture/Compare

Timer_A4 Expansion 0

TA4CCR0

TA4CCR1

TA4EX0

TA4IV

Timer_A4 Interrupt Vector

156

Detailed Description

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Table 6-75. ADC12_B Registers

REGISTER DESCRIPTION

ACRONYM

ADC12CTL0

ADDRESS

ADC12_B Control 0

ADC12_B Control 1

ADC12_B Control 2

ADC12_B Control 3

0800h

0802h

0804h

0806h

0808h

080Ah

080Ch

080Eh

0810h

0812h

0814h

0816h

0818h

0820h

0822h

0824h

0826h

0828h

082Ah

082Ch

082Eh

0830h

0832h

0834h

0836h

0838h

083Ah

083Ch

083Eh

0840h

0842h

0844h

0846h

0848h

084Ah

084Ch

084Eh

0850h

0852h

0854h

0856h

0858h

085Ah

085Ch

085Eh

0860h

0862h

ADC12CTL1

ADC12CTL2

ADC12CTL3

ADC12_B Window Comparator Low Threshold Register

ADC12_B Window Comparator High Threshold Register

ADC12_B Interrupt Flag 0

ADC12LO

ADC12HI

ADC12IFGR0

ADC12IFGR1

ADC12IFGR2

ADC12IER0

ADC12_B Interrupt Flag 1

ADC12_B Interrupt Flag 2

ADC12_B Interrupt Enable 0

ADC12_B Interrupt Enable 1

ADC12_B Interrupt Enable 2

ADC12_B Interrupt Vector

ADC12IER1

ADC12IER2

ADC12IV

ADC12_B Memory Control 0

ADC12_B Memory Control 1

ADC12_B Memory Control 2

ADC12_B Memory Control 3

ADC12_B Memory Control 4

ADC12_B Memory Control 5

ADC12_B Memory Control 6

ADC12_B Memory Control 7

ADC12_B Memory Control 8

ADC12_B Memory Control 9

ADC12_B Memory Control 10

ADC12_B Memory Control 11

ADC12_B Memory Control 12

ADC12_B Memory Control 13

ADC12_B Memory Control 14

ADC12_B Memory Control 15

ADC12_B Memory Control 16

ADC12_B Memory Control 17

ADC12_B Memory Control 18

ADC12_B Memory Control 19

ADC12_B Memory Control 20

ADC12_B Memory Control 21

ADC12_B Memory Control 22

ADC12_B Memory Control 23

ADC12_B Memory Control 24

ADC12_B Memory Control 25

ADC12_B Memory Control 26

ADC12_B Memory Control 27

ADC12_B Memory Control 28

ADC12_B Memory Control 29

ADC12_B Memory Control 30

ADC12_B Memory Control 31

ADC12_B Memory 0

ADC12MCTL0

ADC12MCTL1

ADC12MCTL2

ADC12MCTL3

ADC12MCTL4

ADC12MCTL5

ADC12MCTL6

ADC12MCTL7

ADC12MCTL8

ADC12MCTL9

ADC12MCTL10

ADC12MCTL11

ADC12MCTL12

ADC12MCTL13

ADC12MCTL14

ADC12MCTL15

ADC12MCTL16

ADC12MCTL17

ADC12MCTL18

ADC12MCTL19

ADC12MCTL20

ADC12MCTL21

ADC12MCTL22

ADC12MCTL23

ADC12MCTL24

ADC12MCTL25

ADC12MCTL26

ADC12MCTL27

ADC12MCTL28

ADC12MCTL29

ADC12MCTL30

ADC12MCTL31

ADC12MEM0

ADC12MEM1

ADC12_B Memory 1

Detailed Description

157

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ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

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Table 6-75. ADC12_B Registers (continued)

REGISTER DESCRIPTION

ACRONYM

ADC12MEM2

ADDRESS

ADC12_B Memory 2

ADC12_B Memory 3

ADC12_B Memory 4

ADC12_B Memory 5

ADC12_B Memory 6

ADC12_B Memory 7

ADC12_B Memory 8

ADC12_B Memory 9

ADC12_B Memory 10

ADC12_B Memory 11

ADC12_B Memory 12

ADC12_B Memory 13

ADC12_B Memory 14

ADC12_B Memory 15

ADC12_B Memory 16

ADC12_B Memory 17

ADC12_B Memory 18

ADC12_B Memory 19

ADC12_B Memory 20

ADC12_B Memory 21

ADC12_B Memory 22

ADC12_B Memory 23

ADC12_B Memory 24

ADC12_B Memory 25

ADC12_B Memory 26

ADC12_B Memory 27

ADC12_B Memory 28

ADC12_B Memory 29

ADC12_B Memory 30

ADC12_B Memory 31

0864h

0866h

0868h

086Ah

086Ch

086Eh

0870h

0872h

0874h

0876h

0878h

087Ah

087Ch

087Eh

0880h

0882h

0884h

0886h

0888h

088Ah

088Ch

088Eh

0890h

0892h

0894h

0896h

0898h

089Ah

089Ch

089Eh

ADC12MEM3

ADC12MEM4

ADC12MEM5

ADC12MEM6

ADC12MEM7

ADC12MEM8

ADC12MEM9

ADC12MEM10

ADC12MEM11

ADC12MEM12

ADC12MEM13

ADC12MEM14

ADC12MEM15

ADC12MEM16

ADC12MEM17

ADC12MEM18

ADC12MEM19

ADC12MEM20

ADC12MEM21

ADC12MEM22

ADC12MEM23

ADC12MEM24

ADC12MEM25

ADC12MEM26

ADC12MEM27

ADC12MEM28

ADC12MEM29

ADC12MEM30

ADC12MEM31

158

Detailed Description

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ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

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Table 6-76. Comparator_E Registers

REGISTER DESCRIPTION

ACRONYM

ADDRESS

Comparator Control Register 0

Comparator Control Register 1

Comparator Control Register 2

Comparator Control Register 3

Comparator Interrupt Control

Comparator Interrupt Vector Word

CECTL0

CECTL1

CECTL2

CECTL3

CEINT

08C0h

08C2h

08C4h

08C6h

08CCh

08CEh

CEIV

Table 6-77. CRC32 Registers

REGISTER DESCRIPTION

ACRONYM

ADDRESS

CRC32 Data Input Word 0

CRC32 Data Input Word 1

CRC32 Data In Reverse Word 1

CRC32 Data In Reverse Word 0

CRC32 Initialization and Result Word 0

CRC32 Initialization and Result Word 1

CRC32 Result Reverse Word 1

CRC32 Result Reverse Word 0

CRC16 Data Input

CRC32DIW0

0980h

0982h

0984h

0986h

0988h

098Ah

098Ch

098Eh

0990h

0996h

0998h

099Eh

CRC32DIW1

CRC32DIRBW1

CRC32DIRBW0

CRC32INIRESW0

CRC32INIRESW1

CRC32RESRW1

CRC32RESRW0

CRC16DIW0

CRC16 Data In Reverse

CRC16DIRBW0

CRC16INIRESW0

CRC16RESRW0

CRC16 Init and Result

CRC16 Result Reverse

Table 6-78. AES256 Registers

REGISTER DESCRIPTION

ACRONYM

AESACTL0

ADDRESS

AES Accelerator Control 0

AES Accelerator Control 1

AES Accelerator Status

09C0h

09C2h

09C4h

09C6h

09C8h

09CAh

09CCh

09CEh

AESACTL1

AESASTAT

AESAKEY

AESADIN

AES Accelerator Key

AES Accelerator Data In

AES Accelerator Data Out

AES Accelerator XORed Data In

AESADOUT

AESAXDIN

AESAXIN

Detailed Description

159

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ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

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Table 6-79. LCD_C Registers

REGISTER DESCRIPTION

ACRONYM

LCDCCTL0

ADDRESS

LCD_C control 0

0A00h

0A02h

0A04h

0A06h

0A08h

0A0Ah

0A0Ch

0A0Eh

0A10h

0A12h

0A1Eh

LCD_C control 1

LCDCCTL1

LCD_C blinking control

LCD_C memory control

LCD_C Voltage Control

LCD_C port control 0

LCD_C port control 1

LCDCBLKCTL

LCDCMEMCTL

LCDCVCTL

LCDCPCTL0

LCDCPCTL1

LCDCPCTL2

LCDCPCTL3

LCDCCPCTL

LCDCIV

LCD_C port control 2 (≥256 segments)

LCD_C port control 3 (384 segments)

LCD_C charge pump control

LCD_C interrupt vector

LCDMX = 0 ... 4

LCD memory 1

LCDM1

0A20h

0A21h

0A22h

0A23h

0A24h

0A25h

0A26h

0A27h

0A28h

0A29h

0A2Ah

0A2Bh

0A2Ch

0A2Dh

0A2Eh

0A2Fh

0A30h

0A31h

0A32h

0A33h

0A40h

0A41h

0A42h

0A43h

0A44h

0A45h

0A46h

0A47h

0A48h

0A49h

0A4Ah

0A4Bh

0A4Ch

0A4Dh

0A4Eh

LCD memory 2

LCDM2

LCD memory 3

LCDM3

LCD memory 4

LCDM4

LCD memory 5

LCDM5

LCD memory 6

LCDM6

LCD memory 7

LCDM7

LCD memory 8

LCDM8

LCD memory 9

LCDM9

LCD memory 10

LCDM10

LCD memory 11

LCDM11

LCD memory 12

LCDM12

LCD memory 13

LCDM13

LCD memory 14

LCDM14

LCD memory 15

LCDM15

LCD memory 16

LCDM16

LCD memory 17

LCDM17

LCD memory 18

LCDM18

LCD memory 19

LCDM19

LCD memory 20

LCDM20

LCD blinking memory 1

LCD blinking memory 2

LCD blinking memory 3

LCD blinking memory 4

LCD blinking memory 5

LCD blinking memory 6

LCD blinking memory 7

LCD blinking memory 8

LCD blinking memory 9

LCD blinking memory 10

LCD blinking memory 11

LCD blinking memory 13

LCD blinking memory 14

LCD blinking memory 15

LCDM33_LCDBM1

LCDM34_LCDBM2

LCDM35_LCDBM3

LCDM36_LCDBM4

LCDM37_LCDBM5

LCDM38_LCDBM6

LCDM39_LCDBM7

LCDM40_LCDBM8

LCDM41_LCDBM9

LCDM42_LCDBM10

LCDM43_LCDBM11

LCDM44_LCDBM12

LCDM45_LCDBM13

LCDM46_LCDBM14

LCDM47_LCDBM15

160

Detailed Description

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ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

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Table 6-79. LCD_C Registers (continued)

REGISTER DESCRIPTION

ACRONYM

ADDRESS

LCD blinking memory 16

LCD blinking memory 17

LCD blinking memory 18

LCD blinking memory 19

LCD blinking memory 20

LCDM48_LCDBM16

LCDM49_LCDBM17

LCDM50_LCDBM18

LCDM51_LCDBM19

LCDM52_LCDBM20

0A4Fh

0A50h

0A51h

0A52h

0A53h

LCDMX = 5 ... 8

LCD memory 1

LCD memory 2

LCD memory 3

LCD memory 4

LCD memory 5

LCD memory 6

LCD memory 7

LCD memory 8

LCD memory 9

LCD memory 10

LCD memory 11

LCD memory 12

LCD memory 13

LCD memory 14

LCD memory 15

LCD memory 16

LCD memory 17

LCD memory 18

LCD memory 19

LCD memory 20

LCD memory 21

LCD memory 22

LCD memory 23

LCD memory 24

LCD memory 25

LCD memory 26

LCD memory 27

LCD memory 28

LCD memory 29

LCD memory 30

LCD memory 31

LCD memory 32

LCD memory 33

LCD memory 34

LCD memory 35

LCD memory 36

LCDM1

0A20h

0A21h

0A22h

0A23h

0A24h

0A25h

0A26h

0A27h

0A28h

0A29h

0A2Ah

0A2Bh

0A2Ch

0A2Dh

0A2Eh

0A2Fh

0A30h

0A31h

0A32h

0A33h

0A34h

0A35h

0A36h

0A37h

0A38h

0A39h

0A3Ah

0A3Bh

0A3Ch

0A3Dh

0A3Eh

0A3Fh

0A40h

0A41h

0A42h

0A43h

LCDM2

LCDM3

LCDM4

LCDM5

LCDM6

LCDM7

LCDM8

LCDM9

LCDM10

LCDM11

LCDM12

LCDM13

LCDM14

LCDM15

LCDM16

LCDM17

LCDM18

LCDM19

LCDM20

LCDM21

LCDM22

LCDM23

LCDM24

LCDM25

LCDM26

LCDM27

LCDM28

LCDM29

LCDM30

LCDM31

LCDM32

LCDM33_LCDBM1

LCDM34_LCDBM2

LCDM35_LCDBM3

LCDM36_LCDBM4

Detailed Description

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Table 6-80. LEA Registers

REGISTER DESCRIPTION

ACRONYM

LEACAP

ADDRESS

LEA Capability Register

Configuration Register 0

Configuration Register 1

Configuration Register 2

Memory Bottom Register

Memory Top Register

Code Memory Access

Code Memory Control

LEA Command Status

LEA Source 1 Status

LEA Source 0 Status

LEA Result Status

0A80h

0A84h

0A88h

0A8Ch

0A90h

0A94h

0A98h

0A9Ch

0AA8h

0AACh

0AB0h

0AB4h

0AC0h

0AC4h

0AC8h

0ACCh

0AD0h

0AF0h

0AF4h

0AF8h

0AFCh

LEACNF0

LEACNF1

LEACNF2

LEAMB

LEAMT

LEACMA

LEACMCTL

LEACMDSTAT

LEAS1STAT

LEAS0STAT

LEADSTSTAT

LEAPMCTL

LEAPMDST

LEAPMS1

LEAPMS0

LEAPMCB

LEAIFGSET

LEAIE

PM Control Register

PM Result Register

PM Source 1 Register

PM Source 0 Register

PM Command Buffer

Interrupt Flag and Set

Interrupt Enable

Interrupt Flag and Clear

Interrupt Vector

LEAIFG

LEAIV

162

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Table 6-81. SAPH Registers

REGISTER DESCRIPTION

ACRONYM

SAPHIIDX

ADDRESS

Interrupt Index

0E00h

0E02h

0E04h

0E06h

0E08h

0E0Ah

0E0Ch

0E0Eh

0E10h

0E12h

0E14h

0E16h

0E20h

0E22h

0E24h

0E26h

0E28h

0E2Ah

0E2Ch

0E2Eh

0E30h

0E34h

0E40h

0E42h

0E44h

0E46h

0E48h

0E60h

0E62h

0E64h

0E66h

0E68h

0E6Ah

0E6Eh

0E70h

0E72h

0E74h

0E76h

0E78h

0E7Ah

0E7Ch

0E7Eh

Masked Interrupt Satus

Raw Interrupt Status

Interrupt Mask

SAPHMIS

SAPHRIS

SAPHIMSC

Interrupt Clear

SAPHICR

Interrupt Set

SAPHISR

Module-Descriptor Low Word

SAPHDESCLO

SAPHDESCHI

SAPHKEY

Module-Descriptor High Word

Key

Physical Interface Output Control #0

Physical Interface Output Control #1

Physical Interface Output Function Select

Channel 0 Pull UpTrim

Channel 0 Pull DownTrim

Channel 0 Termination Trim

Channel 1 Pull UpTrim

Channel 1 Pull DownTrim

Channel 1 Termination Trim

Mode Configuration Register

Trim Access Control

SAPHOCTL0

SAPHOCTL1

SAPHOSEL

SAPHCH0PUT

SAPHCH0PDT

SAPHCH0TT

SAPHCH1PUT

SAPHCH1PDT

SAPHCH1TT

SAPHMCNF

SAPHTACTL

SAPHICTL0

SAPHBCTL

Physical Interface Input Control #0

Bias Control

PPG Count

SAPHPGC

Pulse Generator Low Period

Pulse Generator High Period

PPG Control

SAPHPGLPER

SAPHPGHPER

SAPHPGCTL

SAPHPPGTRIG

SAPHASCTL0

SAPHASCTL1

SAPHASQTRIG

SAPHAPOL

PPG Software Trigger

A-SEQ control 0

A-SEQ control 1

ASQ Software Trigger

ASQ ping output polarity

ASQ ping pause level

SAPHAPLEV

SAPHAPHIZ

SAPHATM_A

SAPHATM_B

SAPHATM_C

SAPHATM_D

SAPHATM_E

SAPHATM_F

SAPHTBCTL

SAPHATIMLO

SAPHATIMHI

ASQ ping pause impedance

A-SEQ start to 1st ping

ASQ start to ADC arm

Count for the TIMEMARK C Event

ASQ start to ADC trig

ASQ start to restart

ASQ start to time-out

Time Base Control

Acquisition Timer Low Part

Acquisition Timer High Part

Detailed Description

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Table 6-82. SDHS Registers⁽¹⁾

REGISTER DESCRIPTION

ACRONYM

SDHSIIDX

ADDRESS

Interrupt Index Register

0E80h

0E82h

0E84h

0E86h

0E88h

0E8Ah

0E8Ch

0E8Eh

0E90h

0E92h

0E94h

0E96h

0E98h

0E9Ah

0E9Ch

0E9Eh

0EA2h

0EA4h

0EA6h

0EA8h

Masked Interrupt Status and Clear Register

Raw Interrupt Status

SDHSMIS

SDHSRIS

Interrupt Mask Register

SDHSIMSC

SDHSICR

Interrupt Clear

Interrupt Set Register

SDHSISR

SDHS Descriptor Register L

SDHS Descriptor Register H

SDHS Control Register 0

SDHSDESCLO

SDHSDESCHI

SDHSCTL0

SDHSCTL1

SDHSCTL2

SDHSCTL3

SDHSCTL4

SDHSCTL5

SDHSCTL6

SDHSCTL7

SDHSDT

SDHS Control Register 1

SDHS Control Register 2

SDHS Control Register 3

SDHS Control Register 4

SDHS Control Register 5

SDHS Control Register 6

SDHS Control Register 7

SDHS Data Converstion Register

SDHS Window Comparator High Threshold Register

SDHS Window Comparator Low Threshold Register

DTC destination address

SDHSWINHITH

SDHSWINLOTH

SDHSDTCDA

(1) Not available in MSP430FR6037, MSP430FR6035, and MSP430FR60371

Table 6-83. UUPS Registers⁽¹⁾

REGISTER DESCRIPTION

ACRONYM

UUPSIIDX

ADDRESS

Interrupt Index Register

Masked Interrupt Status

Raw Interrupt Status

Interrupt Mask Register

Interrupt Clear

0EC0h

0EC2h

0EC4h

0EC6h

0EC8h

0ECAh

0ECCh

0ECEh

0ED0h

UUPSMIS

UUPSRIS

UUPSIMSC

UUPSICR

Interrupt Flag Set

UUPSISR

UUPS Descriptor Register L

UUPS Descriptor Register H

UUPS Control

UUPSDESCLO

UUPSDESCHI

UUPSCTL

(1) Not available in MSP430FR6037, MSP430FR6035, and MSP430FR60371

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Table 6-84. HSPLL Registers⁽¹⁾

REGISTER DESCRIPTION

ACRONYM

HSPLLIIDX

ADDRESS

Interrupt Index Register

Masked Interrupt Status

Raw Interrupt Status

Interrupt Mask Register

Interrupt Flag Clear

0EE0h

0EE2h

0EE4h

0EE6h

0EE8h

0EEAh

0EECh

0EEEh

0EF0h

0EF2h

HSPLLMIS

HSPLLRIS

HSPLLIMSC

HSPLLICR

Interrupt Flag Set

HSPLLISR

HSPLL Descriptor Register L

HSPLLDESCLO

HSPLLDESCHI

HSPLLCTL

HSPLL Descriptor Register H

HSPLL Control Register

USSXT Control Register

HSPLLUSSXTLCTL

(1) Not available in MSP430FR6037, MSP430FR6035, and MSP430FR60371

Table 6-85. MTIF Registers

REGISTER DESCRIPTION

Pulse Generator Configuration

Pulse Generator Value

ACRONYM

MTIFPGCNF

ADDRESS

0F00h

0F02h

0F04h

0F06h

0F08h

0F0Ah

0F0Ch

0F0Eh

0F10h

MTIFPGKVAL

MTIFPGCTL

MTIFPGSR

MTIFPCCNF

MTIFPCR

Pulse Generator Control

Pulse Generator Status

Pulse Counter Configuration

Pulse Counter Value

Pulse Counter Control

MTIFPCCTL

MTIFPCSR

MTIFTPCTL

Pulse Counter Status

Measurement Test Port Control

Detailed Description

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6.17 Identification

6.17.1 Revision Identification

The device revision information is shown as part of the top-side marking on the device package. The

device-specific errata sheet describes these markings. For links to the errata sheets for the devices in this

data sheet, see 节 8.4.

The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For

details on this value, see the "Hardware Revision" entries in the Device Descriptor structure (see 节 6.15).

6.17.2 Device Identification

The device type can be identified from the top-side marking on the device package. The device-specific

errata sheet describes these markings. For links to the errata sheets for the devices in this data sheet, see

节 8.4.

A device identification value is also stored in the Device Descriptor structure in the Info Block section. For

details on this value, see the "Device ID" entries in the Device Descriptor structure.

6.17.3 JTAG Identification

Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in

MSP430 Programming With the JTAG Interface.

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7 Applications, Implementation, and Layout

注

Information in the following Applications section is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI's customers are responsible for

determining suitability of components for their purposes. Customers should validate and test

their design implementation to confirm system functionality.

7.1 Device Connection and Layout Fundamentals

This section describes the recommended guidelines when designing with the MSP MCU. These guidelines

are to make sure that the device has proper connections for powering, programming, debugging, and

optimum analog performance.

7.1.1 Power Supply Decoupling and Bulk Capacitors

TI recommends connecting a combination of a 1-µF plus a 100-nF low-ESR ceramic decoupling capacitor

to each AVCC and DVCC pin (see 图 7-1). Higher-value capacitors may be used but can affect supply rail

ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple

(within a few millimeters). Additionally, TI recommends separated grounds with a single-point connection

for better noise isolation from digital to analog circuits on the board and to achieve high analog accuracy.

DVCC

Digital Power

Supply Decoupling

+

DVSS

AVCC

1 µF

100 nF

Analog Power

Supply Decoupling

+

AVSS

1 µF

100 nF

图 7-1. Power Supply Decoupling

For PVCC and PVSS, TI recommends connecting a combination of a 1-µF plus a 22-µF low-ESR ceramic

decoupling capacitor between the PVCC and PVSS pins and a serial 22-Ω resistor to filter low-frequency

noise on the supply line (see 图 7-2).

22 W

PVCC

+

1 nF

22 µF

PVSS

USS module power supply decoupling

图 7-2. Power Supply Decoupling for PVCC and PVSS

7.1.2 External Oscillator (HFXT and LFXT)

Depending on the device variant (see 节 3), the device can support a low-frequency crystal (32 kHz) on

the LFXT pins, a high-frequency crystal on the HFXT pins, or both. External bypass capacitors for the

crystal oscillator pins are required.

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It is also possible to apply digital clock signals to the LFXIN and HFXIN input pins that meet the

specifications of the respective oscillator if the appropriate LFXTBYPASS or HFXTBYPASS mode is

selected. In this case, the associated LFXOUT and HFXOUT pins can be used for other purposes. If they

are left unused, they must be terminated according to 节 4.6.

图 7-3 shows a typical connection diagram.

LFXIN

or

LFXOUT

or

HFXIN

HFXOUT

C_L1

C_L2

图 7-3. Typical Crystal Connection

See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal

oscillator with the MSP MCUs.

7.1.3 USS Oscillator (USSXT)

Depending on the device variant (see 节 3), the device with USS module supports a high-frequency

crystal on the USSXT pins. External bypass capacitors for the crystal oscillator pins are required. Serially

connect a 22-Ω resistor close to the USSXTOUT pin (see 图 7-4). The USSXT does not support bypass

mode, so it is not possible to apply digital clock signals to the USSXTIN pin. Never connect the USSXTIN

pin to a power supply line (AVCC, DVCC, or PVCC). If the USSXT pins are not used, terminate them

according to 节 4.6.

图 7-4 shows a typical connection diagram.

USSXTIN

USSXTOUT

22 W

C_L2

C_L1

图 7-4. Typical Crystal Connection

Consider the following items for the USSXT layout:

•

Keep the trace of USSXTIN and USSXTOUT as short as possible. If one must be longer than the

other, keep USSXTIN shorter, because USSXTIN is more sensitive to EMI.

•

Make the ground shield open ended without making a loop.

Use a ground plane to reduce the impedance of the ground trace.

If USSXT_BOUT is used, keep coupling to USSXTIN and CH0_IN to a minimum.

If USSXT_BOUT is feeding other clock or device inputs, apply a small capacitor (10 pF) as the line

termination load at the end of the line. This avoids reflection artifacts on sensitive inputs (for example,

HFXTIN).

图 7-5 shows the recommended PCB layout.

168

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Plane

Transducer

Interface

Area

Transducer

Interface

Area

Oscillator

Area

CL2

CL1

Oscillator

Area

XTAL

22R

XTAL

22R

Keep-out area for

high currents down

to next GND plane

Keep-out area for

high currents down

to next GND plane

图 7-5. USSXT PCB Layout Recommendation

7.1.4 Transducer Connection to the USS Module

图 7-6 shows a typical connection of two transducers to the USS output and input pins. TI recommends

1% error tolerance for the external termination resistors (Rterm0 and Rterm1) and the AC coupling

capacitors (Cac0 and Cac1). Typical value of the termination resistors is in the range of 150 to 400 Ω, the

AC coupling capacitors are 1 to 2 nF. Actual values should be determined to meet the requirements of

each application.

Rterm0

CH0_OUT

Rterm1

CH1_OUT

T0

T1

Cac0

Cac1

CH1_IN

CH0_IN

图 7-6. Typical Transducer Connection

7.1.5 Charge Pump Control of Input Multiplexer

图 7-7 shows the control logic of the charge pump control of the input multiplexer of CHx_IN. The charge

pump is enabled as long the SAPH_AMCNF.CPEO is high and during the arming of the SDHS. Use the

CPDA bit to control the CP during data acquisition.

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SAPH_ABCTL.CPDA

ASQ.acquisition

ASQ.adc_arming

Charge

pump

enable

en CP

SAPH_AMCNF.CPEO

SDHS.adc_arming

SDHS.acquisition

CH0_IN

CH1_IN

PGA

To SDHS

图 7-7. Control Of Input Multiplexer

7.1.6 JTAG

With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or

MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the

connections also support the MSP-GANG production programmers, thus providing an easy way to

program prototype boards, if desired. 图 7-8 shows the connections between the 14-pin JTAG connector

and the target device required to support in-system programming and debugging for 4-wire JTAG

communication. 图 7-9 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).

The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are

identical. Both can supply V_CCto the target board (through pin 2). In addition, the MSP-FET and MSP-

FET430UIF interface modules and MSP-GANG have a V_CCsense feature that, if used, requires an

alternate connection (pin 4 instead of pin 2). The V_CCsense feature senses the local V_CCpresent on the

target board (that is, a battery or other local power supply) and adjusts the output signals accordingly. 图

7-8 and 图 7-9 show a jumper block that supports both scenarios of supplying V_CCto the target board. If

this flexibility is not required, the desired V_CCconnections may be hard-wired to eliminate the jumper

block. Pins 2 and 4 must not be connected at the same time.

For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User’s

Guide.

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V_CC

Important to connect

MSP430FRxxx

AVCC/DVCC

J1 (see Note A)

J2 (see Note A)

R1

47 kW

JTAG

RST/NMI/SBWTDIO

VCC TOOL

TDO/TDI

TDI

TDO/TDI

TDI

2

1

VCC TARGET

4

3

TMS

6

5

7

TEST

TCK

8

TCK

GND

RST

10

12

14

9

11

13

TEST/SBWTCK

AVSS/DVSS

C1

2.2 nF

(see Note B)

A. If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,

make connection J2.

B. The upper limit for C1 is 2.2 nF when using current TI tools.

图 7-8. Signal Connections for 4-Wire JTAG Communication

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V_CC

Important to connect

MSP430FRxxx

J1 (see Note A)

J2 (see Note A)

AVCC/DVCC

R1

47 kΩ

See Note B

JTAG

VCC TOOL

TDO/TDI

2

1

3

5

7

9

RST/NMI/SBWTDIO

VCC TARGET

4

6

TCK

8

GND

10

12

14

11

13

TEST/SBWTCK

AVSS/DVSS

C1

2.2 nF

See Note B

A. Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the

debug or programming adapter.

B. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during

JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with

the device. The upper limit for C1 is 2.2 nF when using current TI tools.

图 7-9. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)

7.1.7 Reset

The reset pin can be configured as a reset function (default) or as an NMI function in the SFRRPCR

register.

In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing

specifications generates a BOR-type device reset.

Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is

edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the

external NMI. When an external NMI event occurs, the NMIIFG is set.

The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either

pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.

If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an

external 47-kΩ pullup resistor to the RST/NMI pin with a 2.2-nF pulldown capacitor. The pulldown

capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or

in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers.

See the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for more information

on the referenced control registers and bits.

7.1.8 Unused Pins

For details on the connection of unused pins, see 节 4.6.

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7.1.9 General Layout Recommendations

•

Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430

32-kHz Crystal Oscillators for recommended layout guidelines.

•

Proper bypass capacitors on DVCC, AVCC, and reference pins if used.

Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital

switching signals such as PWM or JTAG signals away from the oscillator circuit.

•

Proper ESD level protection should be considered to protect the device from unintended high-voltage

electrostatic discharge. See MSP430 System-Level ESD Considerations for guidelines.

7.1.10 Do's and Don'ts

TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up,

power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the

limits specified in Section 5.1. Exceeding the specified limits may cause malfunction of the device

including erroneous writes to RAM and FRAM.

7.2 Peripheral- and Interface-Specific Design Information

7.2.1 ADC12_B Peripheral

7.2.1.1 Partial Schematic

图 7-10 shows the recommended connections for the reference input pins.

AVSS

VREF+/VEREF+

Using an

External

Positive

Reference

+

470 nF

10 µF

VEREF-

Using an

External

+

Negative

Reference

10 µF

470 nF

图 7-10. ADC12_B Grounding and Noise Considerations

7.2.1.2 Design Requirements

As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should

be followed to eliminate ground loops, unwanted parasitic effects, and noise.

Ground loops are formed when return current from the ADC flows through paths that are common with

other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset

voltages that can add to or subtract from the reference or input voltages of the ADC. The general

guidelines in 节 7.1.1 combined with the connections shown in 图 7-10 prevent these offsets.

In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital

switching or switching power supplies can corrupt the conversion result. A noise-free design using

separate analog and digital ground planes with a single-point connection is recommend to achieve high

accuracy.

图 7-10 shows the recommended decoupling circuit when an external voltage reference is used. The

internal reference module has a maximum drive current as specified in the I_O(VREF+)specification of the

REF module.

Applications, Implementation, and Layout

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are

selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage

enters the device. In this case, the 10-µF capacitor buffers the reference pin and filter any low-frequency

ripple. A 470-nF bypass capacitor filters out any high-frequency noise.

7.2.1.3 Detailed Design Procedure

For additional design information, see Designing With the MSP430FR58xx, FR59xx, FR68xx, and FR69xx

ADC.

7.2.1.4 Layout Guidelines

Component that are shown in the partial schematic (see 图 7-10) should be placed as close as possible to

the respective device pins. Avoid long traces, because they add additional parasitic capacitance,

inductance, and resistance on the signal.

Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),

because the high-frequency switching can be coupled into the analog signal.

If differential mode is used for the ADC12_B, the analog differential input signals must be routed closely

together to minimize the effect of noise on the resulting signal.

7.2.2 LCD_C Peripheral

7.2.2.1 Partial Schematic

Required LCD connections greatly vary by the type of display that is used (static or multiplexed), whether

external or internal biasing is used, and whether the on-chip charge pump is employed. Also, there is a

fair amount of flexibility as to how the segment (Sx) and common (COMx) signals are connected to the

MCU, which can provide unique benefits. Because LCD connections are application-specific, it is difficult

to provide a single one-fits-all schematic. However, for examples and how-to circuit design guidance, see

Designing With MSP430™ MCUs and Segment LCDs.

7.2.2.2 Design Requirements

Due to the flexibility of the LCD_C peripheral module to accommodate various segment-based LCDs,

selecting the correct display for the application in combination with determining specific design

requirements is often an iterative process. TI strongly recommends reviewing the LCD_C peripheral

module chapter in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide and

Designing With MSP430™ MCUs and Segment LCDs during the initial design requirements and decision

process.

7.2.2.3 Detailed Design Procedure

A major component in designing the LCD solution is determining the exact connections between the

LCD_C peripheral module and the display. Two basic design processes can be employed for this step,

although in reality often a balanced co-design approach is recommended:

•

PCB layout-driven design, optimizing signal routing

Software-driven design, focusing on optimizing computational overhead

For a detailed discussion of the design procedure as well as for design information regarding the LCD

controller input voltage selection including internal and external options, contrast control, and bias

generation, see Designing With MSP430™ MCUs and Segment LCDs and the LCD_C Controller chapter

in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.

174

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MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

7.2.2.4 Layout Guidelines

LCD segment (Sx) and common (COMx) signal traces are continuously switching while the LCD is

enabled and should, therefore, be kept away from sensitive analog signals such as ADC inputs to prevent

any noise coupling. TI recommends keeping the LCD signal traces on one side of the PCB grouped

together in a bus-like fashion. A ground plane beneath the LCD traces and guard traces alongside the

LCD traces can provide shielding.

If the internal charge pump of the LCD module is used, place the externally provided capacitor on the

LCDCAP pin as close as possible to the MCU. Connect the capacitor to the device using a short and

direct trace and also have a solid connection to the ground plane that supplies the V_SSpins of the MCU.

For an example layouts and a more in-depth discussion, see Designing With MSP430™ MCUs and

Segment LCDs.

Applications, Implementation, and Layout

175

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产品主页链接: MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371

MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

8 器件和文档支持

8.1 入门和下一步

有关 MSP 系列微控制器以及开发协助工具和库的更多信息，请访问入门页面。

8.2 器件命名规则

为了标示产品开发周期所处的阶段，TI 为所有 MSP MCU 器件的部件号分配了前缀。每个 MSP MCU 商用

系列产品成员都具有以下两个前缀之一：MSP 或 XMS。这些前缀代表了产品开发的发展阶段，即从工程原

型 (XMS) 直到完全合格的生产器件 (MSP)。

XMS - 实验器件，不一定代表最终器件的电气规格

MSP - 完全合格的生产器件

XMS 器件在供货时附带如下免责声明：

“开发中的产品用于内部评估用途。”

MSP 器件的特性已经全部明确，并且器件的质量和可靠性已经完全论证。TI 的标准保修证书对该器件适

用。

预测显示原型器件 (XMS) 的故障率大于标准生产器件。由于这些器件的预计最终使用故障率尚不确定，德

州仪器 (TI) 建议不要将它们用于任何生产系统。请仅使用合格的生产器件。

TI 器件的命名规则还包括一个带有器件系列名称的后缀。此后缀表示温度范围、封装类型和配送形式。图 8-

1 提供了解读完整器件名称的图例。

MSP

430

FR

6

0471

I

PZ

R

Feature Set

Processor Family

Distribution Format

MCU Platform

Packaging

Memory Type

Temperature Range

Series

AES

Oscillators, LEA

Optional: BSL

FRAM

Processor Family

MSP = Mixed-Signal Processor

XMS = Experimental Silicon

MCU Platform

Memory Type

Series

430 = 16-Bit Low-Power Platform

FR = FRAM

6 = FRAM 6 Series up to 16 MHz with LCD

Feature Set

First Digit: Feature Second Digit: Oscillators, LEA Third Digit: FRAM (KB) Optional Fourth Digit: BSL

0 = AES

4 = HFXT + LFXT + LEA + USS

3 = HFXT + LFXT + LEA

2 = HFXT + LFXT

7 = 256

6 = 192

5 = 128

4 = 96

1 = I²C

No value = UART

1 = LFXT

3 = 64

Temperature Range I = –40°C to 85°C

Packaging

http://www.ti.com/packaging

Distribution Format

T = Small reel

R = Large reel

No markings = Tube or tray

图 8-1. 器件命名规则

176

器件和文档支持

提交文档反馈意见

产品主页链接: MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371

MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

8.3 工具和软件

表 8-1 列出了的调试功能。请参阅《适用于 MSP430 的 Code Composer Studio™ IDE 用户指南》，以了

解可用特性的详细信息。有关详细使用信息，请参阅以下文档：

《使用 Code Composer Studio™ IDE 与增强型仿真模块 (EEM) 进行高级调试》

《MSP430™ 高级功耗优化：ULP Advisor™ 软件和 EnergyTrace™ 技术》

表 8-1. 硬件特性

断点

(N)

状态序列发生

器

LPMx.5 调试支

持

MSP 架构

4 线 JTAG 2 线 JTAG

范围断点

有

时钟控制

是

跟踪缓冲器

否

EnergyTrace++

MSP430Xv2

有

3

否

有

设计套件与评估模块

MSP430FR6047 超声波感应评估模块 EVM430-FR6047 评估套件是一款开发平台，可用于评估超声波感

应应用（例如，智能水表）中 MSP430FR6047 的性能。

MSP-TS430PZ100E 100 引脚目标开发板 MSP-TS430PZ100E 是一款独立的 100 引脚 ZIF 插座目标板，

用于通过 JTAG 接口或 Spy Bi-Wire（2 线 JTAG）协议对 MSP430 MCU 系统内置器件进行

编程和调试。

软件

MSP430Ware™ 软件 MSP430Ware 软件集合了所有 MSP430 器件的代码示例、产品说明书以及其他设计

资源，打包提供给用户。除了提供已有 MSP430 设计资源的完整集合外，MSP430Ware 软件

还包含名为 MSP430 驱动程序库的高级 API。借助该库可以轻松地对 MSP430 硬件进行编

程。MSP430Ware 软件以 Code Composer Studio IDE 组件或独立软件包的形式提供。

MSP430FR604x(1)、MSP430FR603x(1) 代码示例根据不同应用需求配置各集成外设的每个 MSP 器件均

具备相应的 C 代码示例。

MSP 驱动程序库驱动程序库的抽象化 API 通过提供易于使用的函数调用使您不再拘泥于 MSP430 硬件的

细节。完整的文档通过具有帮助意义的 API 指南交付，其中包括有关每个函数调用和经过验证

的参数的详细信息。开发人员可以使用驱动程序库功能，以最低开销编写完整项目。

MSP EnergyTrace™ 技术适用于 MSP430 微控制器的 EnergyTrace 技术是基于电能的代码分析工具，适

用于测量和显示应用的电能系统配置并帮助优化应用以实现超低功耗。

ULP（超低功耗）Advisor ULP Advisor™软件是一款辅助工具，旨在指导开发人员编写更为高效的代码，

从而充分利用 MSP430 和 MSP432 微控制器独特的超低功耗功能。ULP Advisor 的目标用户

是微控制器的资深开发者和开发新手，可以根据详尽的 ULP 检验表检查代码，以便以最低的

功耗最大限度地利用应用。在生成时，ULP Advisor 提供通知和备注，以标识代码中可以进一

步优化的区域，进而实现更低的功耗。

适用于 MSP MCU 的定点数学库 MSP IQmath 和 Qmath 库是为 C 语言开发者提供的一套经过高度优化的

高精度数学运算函数集合，能够将浮点算法无缝嵌入 MSP430 和 MSP432 器件的定点代码

中。这些例程通常用于计算密集型实时应用，而优化的执行速度、高精度以及超低能耗通常

是影响这些实时应用的关键因素。与使用浮点数学算法编写的同等代码相比，使用 IQmath 和

Qmath 库可以大幅提高执行速度并显著降低能耗。

适用于 MSP430™ MCU 的浮点数学库

TI

在低功耗和低成本微控制器领域锐意创新，为您提供

MSPMATHLIB。这是标量函数的浮点数学运算库，能够充分利用器件的智能外设，使性能提

升高达 26 倍。Mathlib 能够轻松集成到您的设计中。该运算库免费使用并集成在 Code

Composer Studio 和 IAR IDE 中。如需深入了解该数学运算库及相关基准，请阅读用户指南。

开发工具

适用于 MSP 微控制器的 Code Composer Studio™ 集成开发环境 Code Composer Studio 是一种集成开

发环境 (IDE)，支持所有 MSP 微控制器。Code Composer Studio 包含一整套开发和调试嵌入

式应用的嵌入式软件实用程序的工具。它包含了优化的 C/C++ 编译器、源代码编辑器、项目

构建环境、调试器、描述器以及其他多种功能。直观的 IDE 提供了单个用户界面，有助于完

成应用程序开发流程的每个步骤。熟悉的实用程序和界面可提升用户的入门速度。Code

Composer Studio 将 Eclipse 软件框架的优点和 TI 先进的嵌入式调试功能相结合，为嵌入式开

发人员提供了一种功能丰富的优异开发环境。当 CCS 与 MSP MCU 搭配使用时，可以使用独

特而强大的插件和嵌入式软件实用程序，从而充分利用 MSP 微控制器的功能。

命令行编程器 MSP Flasher 是一款基于 shell 的开源接口，可使用 JTAG 或 Spy-Bi-Wire (SBW) 通信通过

FET 编程器或 eZ430 对 MSP 微控制器进行编程。MSP Flasher 可用于将二进制文件（.txt 或

器件和文档支持

177

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产品主页链接: MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371

MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

.hex 文件）直接下载到 MSP 微控制器，而无需使用 IDE。

MSP MCU 编程器和调试器 MSP-FET 是一款强大的仿真开发工具（通常称为调试探针），可帮助用户在

MSP 低功耗微控制器 (MCU) 中快速开发应用。创建 MCU 软件通常需要将生成的二进制程序

下载到 MSP 器件，以进行验证和调试。MSP-FET 在主机和目标 MSP 间提供调试通信通道。

此外，MSP-FET 还可在计算机的 USB 接口和 MSP UART 间提供反向通道 UART 连接。这

为 MSP 编程器提供了一种在 MSP 和计算机上运行的终端之间进行串行通信的便捷方法。

MSP-FET 还支持使用 BSL 通过 UART 和 I²C 通信协议向 MSP 目标加载程序（通常称为固

件）。

MSP-GANG 生产编程器 MSP Gang 编程器是一款 MSP430 或 MSP432 器件编程器，可同时对多达八个完

全相同的 MSP430 或 MSP432 闪存或 FRAM 器件进行编程。MSP Gang 编程器可使用标准

的 RS-232 或 USB 连接与主机 PC 相连并提供灵活的编程选项，允许用户完全自定义流程。

MSP Gang 编程器配有扩展板，即“Gang 分离器”，可在 MSP Gang 编程器和多个目标器件间

实施互连。提供了八条电缆，用于将扩展板与八个目标器件相连（通过 JTAG 或 SPY-Bi-Wire

连接器）。编程工作可在 PC 或独立设备上完成。PC 端具备基于 DLL 的图形化用户界面。

8.4 文档支持

以下文档对 MSP430FR604x(1)、MSP430FR603x(1)、MCU 进行了介绍。www.ti.com.cn 网站上提供了这

些文档的副本。

接收文档更新通知

要接收文档更新通知（包括芯片勘误表），请转至 ti.com.cn 上您的器件对应的产品文件夹（关于产品文件

夹的链接，请参见节 8.5）。单击右上角的“提醒我”(Alert me) 按钮。点击注册后，即可收到产品信息更改每

周摘要（如有）。有关更改的详细信息，请查阅已修订文档的修订历史记录。

勘误

《MSP430FR6047 器件勘误表》介绍功能规格的已知例外情况。

《MSP430FR60471 器件勘误表》介绍功能规格的已知例外情况。

《MSP430FR6045 器件勘误表》介绍功能规格的已知例外情况。

《MSP430FR6037 器件勘误表》介绍功能规格的已知例外情况。

《MSP430FR60371 器件勘误表》介绍功能规格的已知例外情况。

《MSP430FR6035 器件勘误表》介绍功能规格的已知例外情况。

178

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提交文档反馈意见

产品主页链接: MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371

MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

用户指南

《MSP430FR58xx、MSP430FR59xx 和 MSP430FR6xx 系列用户指南》该器件系列提供的所有模块和外

设的详细说明。

《MSP430™ FRAM 器件引导加载程序 (BSL) 用户指南》 MSP430 微控制器 (MCU) 上的引导加载程序

(BSL) 允许用户在原型设计、最终生产和使用期间与 MSP430 MCU 中的嵌入式存储器进行通

信。可编程存储器（FRAM 存储器）和数据存储器 (RAM) 均可按要求予以修改。

通过 JTAG 接口进行 MSP430™ 编程此文档介绍了使用 JTAG 通信端口擦除、编程和验证基于 MSP430

闪存和 FRAM 的微控制器系列的存储器模块所需的功能。此外，该文档还介绍了如何编程所

有 MSP430 器件上均具备的 JTAG 访问安全保险丝。此文档介绍了使用标准四线制 JTAG 接

口和两线制 JTAG 接口（也称为 Spy-Bi-Wire (SBW)）的器件访问。

《MSP430™ 硬件工具用户指南》此手册介绍了 TI MSP-FET430 闪存仿真工具 (FET) 的硬件。FET 是针

对 MSP430 超低功耗微控制器的程序开发工具。

应用报告

《MSP430™ 32kHz 晶体振荡器》对于稳定的晶体振荡器，选择合适的晶振、正确的负载电路和适当的电

路板布局布线至关重要。该应用报告总结了晶体振荡器的功能，介绍了用于选择合适的晶体以

实现 MSP430 超低功耗运行的参数。此外，还给出了正确电路板布局的提示和示例。此外，

为了确保振荡器在大规模生产后能够稳定运行，还可能需要进行一些振荡器测试，该文档中提

供了有关这些测试的详细信息。

《MSP430™ 系统级 ESD 注意事项》系统级 ESD 对于低电压下的硅晶技术以及经济高效型和超低功耗组

件的需求日益增加。本应用报告解决了三大不同的 ESD 主题，帮助电路板设计人员和 OEM

了解并设计强大的系统级设计：(1) 组件及 ESD 测试和系统级 ESD 测试、二者的差异及组件

级 ESD 标准无法保障系统级稳健性的原因。(2) 不同层级的系统级 ESD 防护常规设计指南，

包括外壳、电缆、PCB 布线以及板载 ESD 保护器件。(3) 系统高效 ESD 设计 (SEED) 简介，

这是一种可实现系统级 ESD 稳健性的板载和片上 ESD 防护协同设计方法，包括示例仿真和测

试结果。另外还介绍了若干实际应用系统级 ESD 保护设计示例及其结果。

8.5 相关链接

表 8-2 列出了快速访问链接。类别包括技术文档、支持和社区资源、工具与软件，以及立即订购快速访问。

表 8-2. 相关链接

器件

产品文件夹

请单击此处

立即订购

请单击此处

技术文档

请单击此处

工具与软件

请单击此处

支持和社区

请单击此处

MSP430FR6047

MSP430FR60471

MSP430FR6045

MSP430FR6037

MSP430FR60371

MSP430FR6035

8.6 商标

MSP430, MSP430Ware, EnergyTrace, ULP Advisor, 适用于 MSP 微控制器的 Code Composer Studio are

trademarks of Texas Instruments.

Arm, Cortex are registered trademarks of Arm Limited.

Microsoft is a registered trademark of Microsoft Corporation.

All other trademarks are the property of their respective owners.

8.7 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

8.8 Export Control Notice

器件和文档支持

179

提交文档反馈意见

产品主页链接: MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371

MSP430FR6035

MSP430FR6047, MSP430FR60471, MSP430FR6045

MSP430FR6037, MSP430FR60371, MSP430FR6035

ZHCSGO9C –JUNE 2017–REVISED SEPTEMBER 2018

www.ti.com.cn

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data

(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any

controlled product restricted by other applicable national regulations, received from disclosing party under

nondisclosure obligations (if any), or any direct product of such technology, to any destination to which

such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior

authorization from U.S. Department of Commerce and other competent Government authorities to the

extent required by those laws.

8.9 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通

知，且不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

180

机械、封装和可订购信息

提交文档反馈意见

产品主页链接: MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371

MSP430FR6035

MECHANICAL DATA

MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996

PZ (S-PQFP-G100)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

75

M

0,08

51

50

76

26

100

0,13 NOM

1

25

12,00 TYP

Gage Plane

14,20

SQ

13,80

0,25

16,20

SQ

0,05 MIN

0°–7°

15,80

1,45

1,35

0,75

0,45

Seating Plane

0,08

1,60 MAX

4040149/B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	MSP430FR60371
厂家：	TEXAS INSTRUMENTS
描述：	具有 256KB FRAM、8KB SRAM、低功耗加速器、LCD、DMA 和 I2C 引导加载程序和 76 个 IO 的 16MHz MCU CD 静态存储器
文件：	总188页 (文件大小：2138K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MSP430FR60371 [TI]

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