MSP430FR6041IPNR_技术文档

MSP430FR6043, MSP430FR60431, MSP430FR6041

MSP430FR5043, MSP430FR50431, MSP430FR5041

ZHCSJA6B –JANUARY 2019 –REVISED DECEMBER 2021

MSP430FR604x、MSP430FR504x 16MHz MCU 高达64KB FRAM，12 位高速8-

MSPS Σ-Δ ADC 和集成传感器AFE

• 低功耗加速器(LEA)

1 特性

– 独立于CPU 运行

• 功耗超低的一流超声波水流和气流测量

– 水

– 与CPU 共享8KB RAM

– 高效的256 点复数FFT：比Arm^®Cortex^®-M0+

内核最多快40 倍

• 在低流速到高流速的情况下以及工作温度范

围内的差分飞行时间(dToF) 精度为±12.5ps

• 可在500:1 的宽动态范围内实现±1% 精度

• 在直径为25mm 的管道上，能够测量的最大

流速为8800 升/小时（40 加仑/分钟）

• 能够检测的最小流速小于1 升/小时（0.005

加仑/分钟）

• 高精度时间测量分辨率小于5ps

• 在每秒获取一组结果的条件下总体电流消耗

大约为3µA

• 嵌入式微控制器

– 时钟频率高达16MHz 的16 位精简指令集计算

机(RISC) 架构

– 宽电源电压范围：1.8V 至3.6V ¹

• 优化的超低功耗模式

– 激活模式：大约120 µA/MHz

– 具有实时时钟(RTC) 的待机模式(LPM3.5)：

450nA ²

– 关断(LPM4.5)：30nA

• 能够支持直径为15mm 至1000mm 的宽管

道尺寸

• 铁电随机存取存储器(FRAM)

– 容量高达64KB 的非易失性存储器

– 超低功耗写入

– 气体

• 在低流速到高流速的情况下以及工作温度范

围内的差分飞行时间(dToF) 精度为±250ps

• 可在流速高达12000 升/小时的条件下实现

±1% 的精度，具有200:1 的宽动态范围

• 能够测量的流速大于25000 升/小时

• 能够检测的最小流速小于3 升/小时

• 高精度时间测量分辨率小于100ps

• 在每秒获取一组结果的条件下总体电流消耗

大约为20µA

– 以125ns/字（4ms 内写入64KB）的速度快速写

入

– 统一的存储器= 程序+ 数据+ 存储都处于同一

存储空间

– 耐写次数达10¹⁵次

– 抗辐射和非磁性

• 智能数字外设

– 32 位硬件乘法器(MPY)

– 6 通道内部DMA

– 带有日历和报警功能的RTC

– 6 个16 位计时器，每个计时器具有多达7 个捕

捉/比较寄存器

• 符合并超出ISO4064、OIML R49、EN 14236 和

EN 1434 精度标准

• 能够直接与标准超声波传感器（高达2.5MHz）连

接

• 集成模拟前端–超声波传感解决方案(USS_A)，

包括

– 32 位和16 位循环冗余校验(CRC)

• 高性能模拟

– 12 通道模拟比较器

– 用于在各种频率下生成多音调脉冲的可编程脉冲

发生器(PPG)

– 用于控制输入和输出通道且具有低阻抗输出驱动

器(4Ω) 的集成PHY

– 具有高达8Msps 输出数据速率的高性能高速12

位模数转换器(SDHS)

– 具有–6.5dB 至30.8dB 增益的可编程增益放大

器(PGA)

– 12 位ADC，具有窗口比较器、内部基准和采样

保持功能以及多达8 条外部输入通道

– 具有高达248 段对比度控制的集成LCD 驱动器

• 多功能输入/输出端口

– 所有引脚均支持电容式触控功能，无需外部组件

– 可按位、字节和字进行访问（成对访问）

– 所有端口均可从LPM 进行边沿可选唤醒

– 所有端口均具有可设定的上拉电阻或下拉电阻

• 代码安全性和加密

– 输出范围为68MHz 至80MHz 的高性能PLL

• 计量测试接口(MTIF)

– 128 位或256 位AES 安全加密和解密协处理器

– 用于随机数生成算法的随机数种子

– IP 封装可保护存储器免遭外部访问

– FRAM 可提供固有安全性优势

– 脉冲发生器和脉冲计数器

– 脉冲率高达1024 次脉冲/秒(p/s)

– 计数容量高达65535（16 位）

– 在LPM3.5 下以200nA（典型值）运行

最低电源电压受限于SVS 电平（请参阅SVS 规格）

RTC 由3.7pF 晶振计时。

1

2

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLASEF5

MSP430FR6043, MSP430FR60431, MSP430FR6041

MSP430FR5043, MSP430FR50431, MSP430FR5041

ZHCSJA6B –JANUARY 2019 –REVISED DECEMBER 2021

www.ti.com.cn

• 增强型串行通信

– 超声波感应设计中心图形用户界面

– 超声波感应软件库

– EVM430-FR6043 燃气表评估模块板

– 用于80 引脚封装的MSP-TS430PN80C 目标插

座板

– 多达4 个eUSCI_A 串行通信端口

• 支持自动波特率检测的UART

• IrDA 编码和解码

– 多达2 个eUSCI_B 串行通信端口

• 支持多从器件寻址的I²C

– 采用EnergyTrace++ 技术的免费专业开发环境

– 用于MSP 微控制器的MSP430Ware^™

• 器件比较汇总了可用的器件型号和封装选项

– 硬件UART 或I²C 引导加载程序(BSL)

• 灵活的时钟系统

2 应用

– 具有10 个可选厂家调整频率的固定频率数控振

荡器(DCO)

– 低功耗低频内部时钟源(VLO)

– 32kHz 晶振(LFXT)

• 超声波智能水表

• 超声波智能燃气表

• 超声波智能热量计

• 流量变送器

– 高频晶振(HFXT)

• 开发工具和软件

3 说明

德州仪器(TI) MSP430FR604x 和MSP430FR504x SoC 属于MSP430 超声波传感微控制器 (MCU) 系列，且功能

强大、集成度高，专为各种工业应用而设计：

• 高分辨率超声波液位感应

• 液体浓度感应

• 高分辨率风速计

• 超声波表面感应

• 超声波泄漏检测

• 氧浓度感应

• 超声波智能燃气表

• 超声波智能水表

这些MCU 提供集成的超声波传感解决方案(USS_A) 模块，该模块可针对多种流速提供高精度测量。USS 模块高

度集成，需要的外部组件极少，因而有助于实现超低功耗计量并降低系统成本。

MSP430FR604x 和 MSP430FR504x 器件采用低功耗加速器 (LEA)，可实现基于 ADC 的高速信号采集以及后续

优化数字信号处理，为电池供电型计量应用提供了一款理想的超低功耗、高精度计量解决方案。

USS_A 模块包括可编程脉冲发生器 (PPG) 和具有低阻抗输出驱动器的物理接口 (PHY)，以实现最佳传感器激励

和准确的阻抗匹配，从而在零流量漂移 (ZFD) 方面达到最佳效果。USS_A 模块还包含可编程增益放大器 (PGA)

和高速12 位8Msps Σ-ΔADC (SDHS)，便于通过行业标准超声波传感器实现精确的信号采集。

此外，MSP430FR604x 和 MSP430FR504x 还集成了其他外设，可提高系统在计量方面的集成度。它具有计量测

试接口 (MTIF) 模块，能够通过脉冲生成来指示仪表测量的流量。它还具有片上 8 通道多路复用器 LCD 驱动器

（仅限 MSP430FR604x）、实时时钟 (RTC)、12 位SAR ADC、模拟比较器、高级加密 (AES256) 模块和循环冗

余校验(CRC) 模块。

MSP430FR604x 和 MSP430FR504x MCU 由广泛的硬件和软件生态系统提供支持，随附参考设计和代码示例，

便于您快速开始设计。开发套件包括 MSP-TS430PN80C 80 引脚目标开发板和 EVM430-FR6043 超声波气流计

EVM。TI 还提供免费软件，包括超声波感应设计中心、超声波感应软件库和MSP430Ware^™软件。

MSP430FR604x 和 MSP430FR504x MCU 系列集成了 TI 的 FRAM（铁电 RAM）和功耗整体超低 MSP 系统架

构，从而使系统设计人员能够在降低能耗的同时提升性能。FRAM 技术兼有 RAM 的低功耗快速写入、灵活性、

耐用性和闪存非易失性等特性。

有关完整的模块说明，请参阅《MSP430FR58xx、MSP430FR59xx 和MSP430FR6xx 系列用户指南》。

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MSP430FR5041

MSP430FR6043, MSP430FR60431, MSP430FR6041

MSP430FR5043, MSP430FR50431, MSP430FR5041

ZHCSJA6B –JANUARY 2019 –REVISED DECEMBER 2021

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器件信息

封装⁽²⁾

器件型号⁽¹⁾

封装尺寸⁽³⁾

12mm x 12mm

10mm x 10mm

9mm x 9mm

MSP430FR6043IPN

MSP430FR60431IPN

MSP430FR6041IPN

MSP430FR5043IPM

MSP430FR50431IPM

MSP430FR5041IPM

MSP430FR5043IRGC

MSP430FR50431IRGC

MSP430FR5041IRGC

LQFP (80)

LQFP (64)

VQFN (64)

9mm x 9mm

(1) 如需获得所有可用器件的最新部件、封装和订购信息，请参阅封装选项附录（节12）或浏览TI 网站www.ti.com.cn。

(2) 有关提供的所有器件变型的对比，请参见节6。

(3) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参阅机械数据（节12 中）。

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MSP430FR5041

MSP430FR6043, MSP430FR60431, MSP430FR6041

MSP430FR5043, MSP430FR50431, MSP430FR5041

ZHCSJA6B –JANUARY 2019 –REVISED DECEMBER 2021

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4 功能方框图

图4-1 给出了功能方框图。

P1.x, P2.x P3.x, P4.x P5.x, P6.x

P7.x

PJ.x

1x8

2x8

1

2x8

LFXIN,

HFXIN

LFXOUT,

HFXOUT

ADC12_B

I/O Ports

P1, P2

2x8 I/Os

I/O Ports

P3, P4

2x8 I/Os

I/O Ports

P5, P6

2x8 I/Os

I/O Ports

P7

1x1 I/Os

I/O Port

PJ

1x8 I/Os

REF_A

MCLK

ACLK

Comp_E

(up to 16

standard

inputs,

up to 8

differential

inputs)

Clock

System

(up to 16

inputs)

Voltage

Reference

SMCLK

PA PC

1x16 I/Os 1x16 I/Os 1x16 I/Os

PB

PD

1x1 I/Os

DMA

Controller

Channel

6

MAB

MDB

Bus

Control

Logic

CPUXV2

incl. 16

Registers

MPU

IP Encap

CRC16

LCD_C

Power

Manage-

ment

RAM

AES256

TA2

TA3

CRC-16-

CCITT

(up to

248 Seg:

static,

FRCTL_A

64 KB

32 KB

4KB + 8KB

Security

Encryption,

Decryption

(128, 256)

Timer_A

2 CC

Timer_A

2 CC

Registers Registers

Watchdog

MPY32

CRC32

LDO

SVS

Brownout

2 to 8 mux)

EEM

(S: 3+1)

(int)

Tiny RAM

22B

CRC-32-

ISO-3309

MDB

MAB

JTAG

Interface

Spy-Bi-Wire

TB0

TA0

TA1

TA4

eUSCI_A0

eUSCI_B0

eUSCI_B1

eUSCI_A1

eUSCI_A2

eUSCI_A3

USS_A

Subsystem

LEA

Subsystem

Timer_B

7 CC

Timer_A

3 CC

Timer_A

3 CC

Timer_A

2 CC

RTC_C

MTIF

(I²C, SPI)

Registers

(int, ext)

Registers

(int, ext)

Registers

(int, ext)

Registers

(int, ext)

(UART,

IrDA, SPI)

LPM3.5 Domain

MTIF_PIN_EN, MTIF_OUT_IN

CHx_IN, CHx_OUT, XPBx, USSXT_BOUT, USSXTOUT, USSXTIN

注意：该器件具备12KB RAM，其中8KB RAM 与LEA 子系统共享。

图4-1. 功能方框图

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Table of Contents

9.1 Overview...................................................................72

9.2 CPU.......................................................................... 72

9.3 Ultrasonic Sensing Solution (USS_A).......................72

9.4 Low-Energy Accelerator (LEA) for Signal

Processing...................................................................73

9.5 Operating Modes...................................................... 74

9.6 Interrupt Vector Table and Signatures.......................77

9.7 Bootloader (BSL)...................................................... 80

9.8 JTAG Operation........................................................ 81

9.9 FRAM Controller A (FRCTL_A)................................ 82

9.10 RAM........................................................................82

9.11 Tiny RAM.................................................................82

9.12 Memory Protection Unit (MPU) Including IP

Encapsulation..............................................................82

9.13 Peripherals..............................................................83

9.14 Input/Output Diagrams............................................95

9.15 Device Descriptors (TLV)......................................146

9.16 Memory Map.........................................................149

9.17 Identification..........................................................169

10 Applications, Implementation, and Layout............. 170

10.1 Device Connection and Layout Fundamentals..... 170

10.2 Peripheral- and Interface-Specific Design

Information................................................................ 176

11 Device and Documentation Support........................178

11.1 Getting Started......................................................178

11.2 Device Nomenclature............................................178

11.3 Tools and Software................................................179

11.4 Documentation Support........................................ 181

11.5 Support Resources............................................... 182

11.6 Trademarks........................................................... 183

11.7 Electrostatic Discharge Caution............................183

11.8 术语表................................................................... 183

11.9 Export Control Notice............................................183

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 2

3 说明................................................................................... 2

4 功能方框图.........................................................................4

5 Revision History.............................................................. 6

6 Device Comparison.........................................................7

6.1 Related Products........................................................ 8

7 Terminal Configuration and Functions..........................9

7.1 Pin Diagrams.............................................................. 9

7.2 Pin Attributes.............................................................11

7.3 Signal Descriptions................................................... 19

7.4 Pin Multiplexing.........................................................28

7.5 Buffer Type................................................................28

7.6 Connection of Unused Pins...................................... 28

8 Specifications................................................................ 29

8.1 Absolute Maximum Ratings...................................... 29

8.2 ESD Ratings............................................................. 29

8.3 Recommended Operating Conditions.......................30

8.4 Active Mode Supply Current Into V_CCExcluding

External Current.......................................................... 31

8.5 Typical Characteristics, Active Mode Supply

Currents.......................................................................32

8.6 Low-Power Mode (LPM0, LPM1) Supply

Currents Into V_CCExcluding External Current............ 32

8.7 Low-Power Mode (LPM2, LPM3, LPM4) Supply

Currents (Into V_CC) Excluding External Current.......... 33

8.8 Low-Power Mode With LCD Supply Currents

(Into V_CC) Excluding External Current.........................34

8.9 Low-Power Mode (LPMx.5) Supply Currents

(Into V_CC) Excluding External Current.........................35

8.10 Typical Characteristics, Low-Power Mode

Supply Currents...........................................................36

8.11 Current Consumption per Module...........................37

8.12 Thermal Resistance Characteristics....................... 37

8.13 Timing and Switching Characteristics..................... 39

9 Detailed Description......................................................72

Information.................................................................. 184

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5 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changed from revision A to revision B

Changes from December 2, 2020 to December 1, 2021

Page

• 更改了文档标题...................................................................................................................................................1

• 在说明中添加了指向应用资源的链接................................................................................................................. 2

• Updated 节11.5, Support Resources ............................................................................................................182

Changed from initial release to revision A

Changes from January 19, 2019 to December 1, 2020

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式。..................................................................................... 1

• Added notes to 节8.12, Thermal Resistance Characteristics ......................................................................... 37

• Added the note that begins "XT1CLK and VLOCLK can be active during LPM4..." in 节9.5, Operating Modes

..........................................................................................................................................................................74

• Added the INTERRUPT VECTOR REGISTER column, moved register names from the INTERRUPT FLAG

column, and corrected interrupt flag names as necessary in 表9-4, Interrupt Sources, Flags, Vectors, and

Signatures ........................................................................................................................................................77

• Corrected the interrupt flag bit numbers for ports P4 to P7 (changed PxIFG.2 to PxIFG.7) in 表9-4, Interrupt

Sources, Flags, and Vectors ............................................................................................................................77

• Corrected a typo in the PySEL0.x column header in 表9-24, I/O Function Selection .....................................95

• Corrected the address range for "Main: interrupt vectors" in 表9-52, Memory Organization ........................149

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6.1 Related Products

For information about other devices in this family of products or related products, see the following links.

TI 16-bit and 32-bit microcontrollers

High-performance, low-power solutions to enable the autonomous future

Products for MSP430 ultra-low-power sensing & measurement MCUs

One platform. One ecosystem. Endless possibilities.

Reference designs

Find reference designs leveraging the best in TI technology to solve your system-level challenges

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7 Terminal Configuration and Functions

7.1 Pin Diagrams

图7-1 shows the pinout of the 80-pin PM package.

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

AVCC1

P2.2/COUT/UCA0CLK/A14/C14

P2.3/TA0.0/UCA0STE/A15/C15

1

2

60 P6.3/COM7/R23

59 DVCC3

3

58 DVSS3

P1.0/UCA1CLK/TA1.0/A0/C0/VREF-/VeREF-

P1.1/UCA1STE/TA4.0/A1/C1/VREF+/VeREF+

AVSS2

4

57 P6.2/TB0CLK/R13/LCDREF/LCDS32

56 P6.1/RTCCLK/R03/LCDS33

55 P7.0/TA1.0/TA1.2/XPB0/LCDS30

54 P6.6/ACLK/COM2/LCDS31

53 P6.5/SMCLK/COM1/LCDS34

52 P6.4/MCLK/COM0

5

6

PJ.4/LFXIN

7

PJ.5/LFXOUT

8

AVSS3

9

MSP430FR6043IPN

MSP430FR60431IPN

MSP430FR6041IPN

PJ.6/HFXIN/USSXT_BOUT

10

11

12

13

14

15

16

17

18

19

20

51 P6.0/TA0CLK/COUT/LCDS0

50 P5.7/TA0.2/UCB1STE/LCDS1

49 P5.6/TB0OUTH/UCB1SOMI/UCB1SCL/LCDS2

48 P5.5/TA4.1/UCB1SIMO/UCB1SDA/LCDS3

47 P5.4/TA0.0/UCB1CLK/TA4.0/LCDS4

46 P5.3/TB0.3/UCA2STE/LCDS5

45 P5.2/TB0.2/UAC2CLK/LCDS6

44 P5.1/TB0.1/UCA2SOMI/UCA2RXD/LCDS7

43 P5.0/TB0.0/UCA2SIMO/UCA2TXD/LCDS8

42 P4.7/DMAE0/LCDS9

PJ.7/HFXOUT

P2.4/TA0CLK/TB0CLK/TA1CLK/LCDS24

P2.6/UCA0SIMO/UCA0TXD/TA1.2/TA1.2C/LCDS23

P2.7/UCA0SOMI/UCA0RXD/TA4.1/TA4.1C/LCDS22

TEST/SBWCLK

RST /NMI/SBWTDIO

PJ.0/UAC2CLK/SRSCG1/DMAE0/C10/TDO

PJ.1/UCA2STE/SRSCG0/TA4CLK/C11/TDI/TCLK

PJ.2/UCA2SIMO/UCA2TXD/SROSCOFF/TB0OUTH/C12/TMS

PJ.3/UCA2SOMI/UCA2RXD/SRCPUOFF/TB0.6/C13/TCK

41 DVSS2

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

A. On devices with UART BSL: P2.0 is BSLTX, P2.1 is BSLRX

B. On devices with I²C BSL: P1.6 is BSLSDA, P1.7 is BSLSCL

图7-1. 80-Pin PN Package (Top View)

图7-2 shows the pinout of the 64-pin PM and 64-pin RGC package.

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MSP430FR5043, MSP430FR50431, MSP430FR5041

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64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

AVCC1

P2.2/COUT/UCA0CLK/A14/C14

P1.0/UCA1CLK/TA1.0/A0/C0/VREF-/VeREF-

P1.1/UCA1STE/TA4.0/A1/C1/VREF+/VeREF+

AVSS2

1

2

3

4

5

6

7

8

9

48 DVSS3

47 P6.2/TB0CLK

46 P7.0/TA1.0/TA1.2/XPB0

45 P6.6/ACLK

44 P6.5/SMCLK

PJ.4/LFXIN

43 P6.4/MCLK

MSP430FR5043IPM

MSP430FR50431IPM

MSP430FR5041IPM

MSP430FR5043IRGC

MSP430FR50431IRGC

MSP430FR5041IRGC

PJ.5/LFXOUT

42 P6.0/TA0CLK/COUT

AVSS3

41 P5.7/TA0.2/UCB1STE

40 P5.6/TB0OUTH/UCB1SOMI/UCB1SCL

39 P5.5/TA4.1/UCB1SIMO/UCB1SDA

38 P5.4/TA0.0/UCB1CLK/TA4.0

37 P5.3/TB0.3/UCA2STE

36 P5.2/TB0.2/UAC2CLK

35 P5.1/TB0.1/UCA2SOMI/UCA2RXD

34 P5.0/TB0.0/UCA2SIMO/UCA2TXD

33 DVSS2

PJ.6/HFXIN/USSXT_BOUT

PJ.7/HFXOUT

10

11

12

13

14

15

16

TEST/SBWCLK

RST /NMI/SBWTDIO

PJ.0/UAC2CLK/SRSCG1/DMAE0/C10/TDO

PJ.1/UCA2STE/SRSCG0/TA4CLK/C11/TDI/TCLK

PJ.2/UCA2SIMO/UCA2TXD/SROSCOFF/TB0OUTH/C12/TMS

PJ.3/UCA2SOMI/UCA2RXD/SRCPUOFF/TB0.6/C13/TCK

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

A. On devices with UART BSL: P2.0 is BSLTX, P2.1 is BSLRX

B. On devices with I²C BSL: P1.6 is BSLSDA, P1.7 is BSLSCL

图7-2. 64-Pin PM or RGC Package (Top View)

10

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MSP430FR5043, MSP430FR50431, MSP430FR5041

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7.2 Pin Attributes

表7-1. Pin Attributes

PIN NUMBER⁽¹⁾

POWER

RESET STATE

AFTER BOR⁽⁷⁾

SIGNAL NAME^{(1) (4)}

SIGNAL TYPE⁽²⁾

BUFFER TYPE⁽³⁾

SOURCE⁽⁵⁾

FR6043,

FR6041

FR5043,

FR5041

1

2

1

2

AVCC1

P

I/O

O

I/O

I

Power

LVCMOS

Analog

N/A

–

P2.2

DVCC

OFF

COUT

UCA0CLK

A14

–

C14

I

Analog

–

P2.3

I/O

I

LVCMOS

Analog

OFF

TA0.0

UCA0STE

A15

–

3

–

C15

I

Analog

–

P1.0

I/O

I

LVCMOS

Analog

OFF

UCA1CLK

TA1.0

A0

–

4

3

–

C0

I

Analog

–

VREF-

VeREF-

P1.1

O

I

Analog

–

Analog

–

I/O

I

LVCMOS

Analog

OFF

UCA1STE

TA4.0

A1

–

5

4

–

C1

I

Analog

–

VREF+

VeREF+

AVSS2

PJ.4

O

I

Analog

–

Analog

–

6

7

5

6

P

Power

N/A

OFF

–

I/O

I

LVCMOS

Analog

DVCC

LFXIN

PJ.5

–

I/O

O

P

LVCMOS

Analog

OFF

8

9

7

8

LFXOUT

AVSS3

PJ.6

–

Power

N/A

–

I/O

I

LVCMOS

Analog

DVCC

–

10

11

9

HFXIN

USSXT_BOUT

PJ.7

O

I/O

O

I/O

I

Analog

–

LVCMOS

Analog

OFF

10

HFXOUT

P2.4

–

LVCMOS

Analog

OFF

TA0CLK

TB0CLK

TA1CLK

S24

–

12

I

–

I

O

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MSP430FR5043, MSP430FR50431, MSP430FR5041

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表7-1. Pin Attributes (continued)

PIN NUMBER⁽¹⁾

POWER

RESET STATE

AFTER BOR⁽⁷⁾

SIGNAL NAME^{(1) (4)}

SIGNAL TYPE⁽²⁾

BUFFER TYPE⁽³⁾

SOURCE⁽⁵⁾

FR6043,

FR6041

FR5043,

FR5041

P2.6

I/O

O

I/O

O

I/O

I

LVCMOS

Analog

DVCC

OFF

UCA0TXD

UCA0SIMO

TA1.2

–

13

–

TA1.2C

S23

–

P2.7

LVCMOS

Analog

OFF

UCA0RXD

UCA0SOMI

TA4.1

–

PD

I/O

O

I

14

–

TA4.1C

S22

TEST

LVCMOS

Analog

15

16

11

12

SBWTCK

RST

I

–

I/O

I

PU

NMI

–

SBWTDIO

PJ.0

I/O

O

I/O

O

I

OFF

TDO

–

UCA2CLK

SRSCG1

DMAE0

C10

17

13

–

I

–

PJ.1

I/O

I

LVCMOS

Analog

OFF

TDI

–

TCLK

I

18

14

UCA2STE

SRSCG0

TA4CLK

C11

I/O

O

I

–

I

–

PJ.2

I/O

I

LVCMOS

Analog

OFF

TMS

–

UCA2TXD

UCA2SIMO

SROSCOFF

TB0OUTH

C12

O

I/O

O

I

19

15

–

I

–

PJ.3

I/O

I

LVCMOS

Analog

OFF

TCK

–

UCA2RXD

UCA2SOMI

SRCPUOFF

TB0.6

I

20

16

I/O

O

I/O

I

C13

12

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MSP430FR6043, MSP430FR60431, MSP430FR6041

MSP430FR5043, MSP430FR50431, MSP430FR5041

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表7-1. Pin Attributes (continued)

PIN NUMBER⁽¹⁾

POWER

RESET STATE

AFTER BOR⁽⁷⁾

SIGNAL NAME^{(1) (4)}

SIGNAL TYPE⁽²⁾

BUFFER TYPE⁽³⁾

SOURCE⁽⁵⁾

FR6043,

FR6041

FR5043,

FR5041

21

22

17

18

DVSS1

DVCC1

P2.5

P

Power

N/A

OFF

–

Power

–

I/O

O

LVCMOS

Analog

DVCC

TA0.2

–

23

24

–

TA4.0

S21

–

P3.0

I/O

O

LVCMOS

Analog

OFF

TB0.0

–

S20

P1.2

I/O

O

LVCMOS

Analog

OFF

UCA1TXD

UCA1SIMO

TA1.0

–

I/O

I

25

19

–

A8

–

C8

I

Analog

–

P1.3

I/O

I

LVCMOS

Analog

OFF

UCA1RXD

UCA1SOMI

TA1.1

–

I/O

I

26

20

–

A9

–

C9

I

Analog

–

P2.0

I/O

O

LVCMOS

Analog

OFF

UCA1CLK

UCA3TXD

UCA3SIMO

S19

–

27

28

29

21

22

23

I/O

O

–

P2.1

I/O

I

LVCMOS

Analog

OFF

UCA1STE

UCA3RXD

UCA3SOMI

S18

–

I/O

O

–

P1.6

I/O

O

LVCMOS

Analog

OFF

UCA3STE

UCB0SIMO

UCB0SDA

S17

–

P1.7

I/O

I

LVCMOS

Analog

OFF

USSTRG

UCA3CLK

UCB0SOMI

UCB0SCL

S16

–

I/O

O

30

24

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MSP430FR6043, MSP430FR60431, MSP430FR6041

MSP430FR5043, MSP430FR50431, MSP430FR5041

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表7-1. Pin Attributes (continued)

PIN NUMBER⁽¹⁾

POWER

RESET STATE

AFTER BOR⁽⁷⁾

SIGNAL NAME^{(1) (4)}

SIGNAL TYPE⁽²⁾

BUFFER TYPE⁽³⁾

SOURCE⁽⁵⁾

FR6043,

FR6041

FR5043,

FR5041

P1.4

I/O

I

LVCMOS

Analog

DVCC

OFF

TB0.4

–

31

25

26

UCA0STE

A2

–

C2

I

Analog

–

P1.5

I/O

I

LVCMOS

Analog

OFF

TB0.5

–

32

UCB0CLK

A3

–

C3

I

Analog

–

P3.1

I/O

I

LVCMOS

Analog

OFF

TA1CLK

TB0.1

–

33

34

27

28

I/O

O

MTIF_OUT_IN

P4.0

–

OFF

RTCCLK

TA4.1

–

O

MTIF_PIN_EN

P4.1

I

–

I/O

I

OFF

UCA0CLK

TB0.4

–

35

29

UCA3RXD

UCA3SOMI

S15

–

I/O

O

–

P4.2

I/O

O

LVCMOS

Analog

OFF

UCA0STE

TB0.5

–

36

30

UCA3SIMO

UCA3TXD

S14

–

O

–

P4.3

I/O

O

LVCMOS

Analog

OFF

UCA0TXD

UCA0SIMO

S13

–

37

38

39

31

32

–

I/O

O

–

P4.4

I/O

I

LVCMOS

Analog

OFF

UCA0RXD

UCA0SOMI

S12

–

I/O

O

–

P4.5

I/O

I

LVCMOS

Analog

OFF

TA0CLK

TA1CLK

S11

–

I

O

14

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MSP430FR6043, MSP430FR60431, MSP430FR6041

MSP430FR5043, MSP430FR50431, MSP430FR5041

ZHCSJA6B –JANUARY 2019 –REVISED DECEMBER 2021

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表7-1. Pin Attributes (continued)

PIN NUMBER⁽¹⁾

POWER

RESET STATE

AFTER BOR⁽⁷⁾

SIGNAL NAME^{(1) (4)}

SIGNAL TYPE⁽²⁾

BUFFER TYPE⁽³⁾

SOURCE⁽⁵⁾

FR6043,

FR6041

FR5043,

FR5041

P4.6

I/O

I

LVCMOS

Analog

DVCC

OFF

TB0CLK

TA4CLK

S10

–

40

–

I

O

–

41

42

33

DVSS2

P4.7

P

Power

N/A

OFF

–

I/O

I

LVCMOS

Analog

DVCC

DMAE0

S9

–

O

P5.0

I/O

O

LVCMOS

Analog

OFF

TB0.0

–

43

44

34

35

UCA2TXD

UCA2SIMO

S8

I/O

O

–

P5.1

I/O

O

LVCMOS

Analog

OFF

TB0.1

–

UCA2RXD

UCA2SOMI

S7

I

I/O

O

–

P5.2

I/O

O

LVCMOS

Analog

OFF

TB0.2

–

45

46

36

37

UCA2CLK

S6

I/O

O

–

P5.3

I/O

O

LVCMOS

Analog

OFF

TB0.3

–

UCA2STE

S5

I/O

O

–

P5.4

I/O

O

LVCMOS

Analog

OFF

TA0.0

–

47

48

49

38

39

40

UCB1CLK

TA4.0

–

S4

O

–

P5.5

I/O

O

LVCMOS

Analog

OFF

TA4.1

–

UCB1SIMO

UCB1SDA

S3

–

P5.6

I/O

I

LVCMOS

Analog

OFF

TB0OUTH

UCB1SOMI

UCB1SCL

S2

–

I/O

O

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MSP430FR5043, MSP430FR50431, MSP430FR5041

ZHCSJA6B –JANUARY 2019 –REVISED DECEMBER 2021

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表7-1. Pin Attributes (continued)

PIN NUMBER⁽¹⁾

POWER

RESET STATE

AFTER BOR⁽⁷⁾

SIGNAL NAME^{(1) (4)}

SIGNAL TYPE⁽²⁾

BUFFER TYPE⁽³⁾

SOURCE⁽⁵⁾

FR6043,

FR6041

FR5043,

FR5041

P5.7

I/O

O

LVCMOS

Analog

DVCC

1.5 V

OFF

TA0.2

UCB1STE

S1

–

50

41

–

P6.0

I/O

I

LVCMOS

Analog

OFF

TA0CLK

COUT

S0

–

51

52

53

42

43

44

I

O

–

P6.4

I/O

O

LVCMOS

Analog

OFF

MCLK

COM0

P6.5

–

O

I/O

O

LVCMOS

Analog

OFF

SMCLK

COM1

S34

–

O

Analog

–

P6.6

I/O

O

LVCMOS

Analog

OFF

ACLK

COM2

S31

–

54

55

56

57

45

46

O

Analog

–

P7.0

I/O

O

LVCMOS

Analog

OFF

TA1.0

TA1.2

XPB0

S30

–

O

Analog

DVCC

-

–

P6.1

I/O

O

LVCMOS

Analog

OFF

RTCCLK

R03

–

I/O

O

S33

Analog

–

P6.2

I/O

I

LVCMOS

Analog

OFF

TB0CLK

R13

–

47

I/O

I

LCDREF

S32

Analog

–

O

Analog

DVCC

–

58

59

48

49

DVSS3

DVCC3

P6.3

P

Power

N/A

OFF

–

P

Power

–

I/O

O

LVCMOS

Analog

DVCC

60

61

COM7

R23

–

-

I/O

O

Analog

R33

Analog

LCDCAP

P6.7

Analog

–

LVCMOS

Analog

OFF

TA0.1

COM4

S29

–

62

–

O

Analog

16

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MSP430FR6043, MSP430FR60431, MSP430FR6041

MSP430FR5043, MSP430FR50431, MSP430FR5041

ZHCSJA6B –JANUARY 2019 –REVISED DECEMBER 2021

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表7-1. Pin Attributes (continued)

PIN NUMBER⁽¹⁾

POWER

RESET STATE

AFTER BOR⁽⁷⁾

SIGNAL NAME^{(1) (4)}

SIGNAL TYPE⁽²⁾

BUFFER TYPE⁽³⁾

SOURCE⁽⁵⁾

FR6043,

FR6041

FR5043,

FR5041

P3.2

I/O

O

LVCMOS

Analog

DVCC

1.5 V

OFF

TA1.1

–

63

64

–

COM5

S28

O

Analog

–

P3.3

I/O

O

LVCMOS

Analog

OFF

MCLK

–

50

TB0.3

I/O

O

XPB1

–

S25

O

Analog

DVCC

PVCC

–

P3.4

I/O

O

LVCMOS

Analog

OFF

SMCLK

COM6

DMAE0

S27

–

65

66

51

52

O

I

LVCMOS

Analog

–

O

–

P3.5

I/O

O

LVCMOS

Analog

OFF

ACLK

–

COM3

COUT

O

LVCMOS

Analog

–

S26

O

–

67

68

69

70

71

72

73

74

53

54

55

56

57

58

59

60

CH1_IN

CH1_OUT

PVSS

I

Analog

–

O

Analog

–

P

Power

N/A

–

PVCC

P

Power

–

PVCC

P

Power

–

PVSS

P

Power

–

CH0_OUT

CH0_IN

P3.6

O

Analog

PVCC

DVCC

–

I

Analog

I/O

O

LVCMOS

Analog

OFF

UCB1SIMO

UCB1SDA

TB0.6

–

75

–

USSXT_BOUT

S35

–

P3.7

I/O

I

LVCMOS

Analog

OFF

UCB1SOMI

UCB1SCL

TB0.2

–

76

–

TB0OUTH

S36

–

O

–

77

78

79

61

62

63

AVSS4

USSXTIN⁽⁶⁾

USSXTOUT⁽⁶⁾

P

Power

N/A

–

I

Analog

1.5 V

–

O

Analog

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MSP430FR6043, MSP430FR60431, MSP430FR6041

MSP430FR5043, MSP430FR50431, MSP430FR5041

ZHCSJA6B –JANUARY 2019 –REVISED DECEMBER 2021

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表7-1. Pin Attributes (continued)

PIN NUMBER⁽¹⁾

POWER

RESET STATE

AFTER BOR⁽⁷⁾

SIGNAL NAME^{(1) (4)}

SIGNAL TYPE⁽²⁾

BUFFER TYPE⁽³⁾

SOURCE⁽⁵⁾

FR6043,

FR6041

FR5043,

FR5041

80

64

AVSS1

P

Power

N/A

–

(1) The signal that is listed first for each pin is the reset default pin name.

(2) Signal Types: I = Input, O = Output, I/O = Input or Output.

(3) Buffer Types: LVCMOS, Analog, or Power (see 表7-3 for details)

(4) To determine the pin mux encodings for each pin, see 节9.14.

(5) The power source shown in this table is the I/O power source, which may differ from the module power source.

(6) Do not connect the USSXTIN and USSXTOUT pins to AVCC or DVCC. USSXTIN does not support bypass mode, so do not drive an

external clock to USSXTIN pin.

(7) Reset States:

OFF = High impedance with Schmitt-trigger input and pullup or pulldown (if available) disabled

PU = Pullup is enabled

PD = Pulldown is enabled

N/A = Not applicable

18

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MSP430FR6043, MSP430FR60431, MSP430FR6041

MSP430FR5043, MSP430FR50431, MSP430FR5041

ZHCSJA6B –JANUARY 2019 –REVISED DECEMBER 2021

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7.3 Signal Descriptions

节7.3 describes the signals for all device variants and package options.

表7-2. Signal Descriptions

PIN NO.⁽¹⁾

PIN TYPE⁽²⁾

DESCRIPTION

64-PIN

80-PIN PN PM OR

RGC

FUNCTION SIGNAL NAME

A0

A1

A2

A3

4

5

3

I

ADC analog input A0

ADC analog input A1

ADC analog input A2

ADC analog input A3

ADC analog input A4

ADC analog input A5

ADC analog input A6

ADC analog input A7

ADC analog input A8

ADC analog input A9

ADC analog input A10

ADC analog input A11

ADC analog input A12

ADC analog input A13

ADC analog input A14

ADC analog input A15

4

31

25

I

32

26

I

AVSS

25

AVSS

19

I

–

A8

I

A9

26

20

I

ADC

AVSS

2

AVSS

2

I

–

I

–

I

–

I

–

A14

I

A15

3

I

–

VREF+

VREF-

VeREF+

VeREF-

ACLK

HFXIN

HFXOUT

5

4

O

I

Output of positive reference voltage

Output of negative reference voltage

Input for an external positive reference voltage to the ADC

Input for an external negative reference voltage to the ADC

ACLK output

4

3

5

4

3

45, 52

9

I

54, 66

10

O

I

Input for high-frequency crystal oscillator HFXT

Output for high-frequency crystal oscillator HFXT

Input for low-frequency crystal oscillator LFXT

Output of low-frequency crystal oscillator LFXT

MCLK output

11

10

O

I

Clock

LFXIN

7

6

LFXOUT

MCLK

8

7

O

52, 64

53, 65

43, 50

44, 51

SMCLK

SMCLK output

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表7-2. Signal Descriptions (continued)

PIN NO.⁽¹⁾

PIN TYPE⁽²⁾

DESCRIPTION

64-PIN

80-PIN PN PM OR

RGC

FUNCTION SIGNAL NAME

C0

4

5

3

4

I

Comparator input C0

Comparator input C1

Comparator input C2

Comparator input C3

Comparator input C4

Comparator input C5

Comparator input C6

Comparator input C7

Comparator input C8

Comparator input C9

Comparator input C10

Comparator input C11

Comparator input C12

Comparator input C13

Comparator input C14

Comparator input C15

Comparator output

C1

C2

31

32

4

25

26

3

I

C3

Not connected

Comparator C8

C9

I

4

3

I

4

3

I

4

3

I

25

26

17

18

19

20

2

19

20

13

14

15

16

2

I

C10

I

C11

I

C12

I

C13

I

C14

I

C15

3

I

–

COUT

2, 51, 66 2, 42, 52

O

I

DMA

DMAE0

SBWTCK

SBWTDIO

SRCPUOFF

SROSCOFF

SRSCG0

SRSCG1

TCK

17, 42, 65

15

13, 51

11

External DMA trigger

Spy-Bi-Wire input clock

I

16

12

I/O

O

I

Spy-Bi-Wire data input/output

20

16

Low-power debug: CPU Status register bit CPUOFF

Low-power debug: CPU Status register bit OSCOFF

Low-power debug: CPU Status register bit SCG0

Low-power debug: CPU Status register bit SCG1

Test clock

19

15

18

14

17

13

Debug

20

16

TCLK

18

14

I

Test clock input

TDI

18

14

I

Test data input

TDO

17

13

O

I

Test data output port

TEST

15

11

Test mode pin –select digital I/O on JTAG pins

Test mode select

TMS

19

15

I

20

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表7-2. Signal Descriptions (continued)

PIN NO.⁽¹⁾

PIN TYPE⁽²⁾

DESCRIPTION

64-PIN

80-PIN PN PM OR

RGC

FUNCTION SIGNAL NAME

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

P1.0

P1.1

P1.2

4

3

I/O

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

5

4

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

25

26

31

32

29

30

27

28

2

19

20

25

26

23

24

21

22

2

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

P1.3

GPIO, P1

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

P1.4

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

P1.5

P1.6

P1.7

P2.0

P2.1

P2.2

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

P2.3

GPIO, P2

3

–

27

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

P2.4

12

23

13

14

24

33

63

64

65

66

75

76

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

P2.5

P2.6

P2.7

P3.0

P3.1

P3.2

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

–

50

51

52

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

P3.3

GPIO, P3

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

P3.4

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

P3.5

P3.6

P3.7

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

–

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

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表7-2. Signal Descriptions (continued)

PIN NO.⁽¹⁾

PIN TYPE⁽²⁾

DESCRIPTION

64-PIN

80-PIN PN PM OR

RGC

FUNCTION SIGNAL NAME

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

P4.0

P4.1

P4.2

34

35

36

37

38

39

40

42

43

44

45

46

47

48

49

50

51

56

57

60

52

53

54

62

55

28

29

30

31

32

I/O

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

P4.3

GPIO, P4

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

P4.4

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

P4.5

P4.6

P4.7

P5.0

P5.1

P5.2

–

34

35

36

37

38

39

40

41

42

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

P5.3

GPIO, P5

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

P5.4

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

P5.5

P5.6

P5.7

P6.0

P6.1

P6.2

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

–

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

47

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

P6.3

GPIO, P6

–

43

44

45

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

P6.4

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

P6.5

P6.6

P6.7

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

–

General-purpose digital I/O with port interrupt and wakeup from

LPMx.5

GPIO, P7

P7.0

46

22

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ZHCSJA6B –JANUARY 2019 –REVISED DECEMBER 2021

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表7-2. Signal Descriptions (continued)

PIN NO.⁽¹⁾

PIN TYPE⁽²⁾

DESCRIPTION

64-PIN

80-PIN PN PM OR

RGC

FUNCTION SIGNAL NAME

PJ.0

PJ.1

PJ.2

17

18

13

14

15

16

6

I/O

O

General-purpose digital I/O

19

General-purpose digital I/O

PJ.3

GPIO, PJ

20

General-purpose digital I/O

PJ.4

7

General-purpose digital I/O

PJ.5

8

7

General-purpose digital I/O

PJ.6

10

9

General-purpose digital I/O

PJ.7

11

10

24

23

40

39

General-purpose digital I/O

I²C clock –eUSCI_B0 I²C mode

UCB0SCL

30

I²C data –eUSCI_B0 I²C mode

UCB0SDA

29

I²C

I²C clock –eUSCI_B1 I²C mode

UCB1SCL

49, 76

48, 75

52

I²C data –eUSCI_B1 I²C mode

UCB1SDA

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

LCD common output COM0 for LCD backplane

LCD common output COM1 for LCD backplane

LCD common output COM2 for LCD backplane

LCD common output COM3 for LCD backplane

LCD common output COM4 for LCD backplane

LCD common output COM5 for LCD backplane

LCD common output COM6 for LCD backplane

LCD common output COM7 for LCD backplane

–

53

O

54

O

66

O

62

O

63

O

65

O

60

O

LCD capacitor connection

CAUTION: LCDCAP/R33 must be connected to DVSS if not

used.

LCD

LCDCAP

61

I/O

–

LCDREF

R03

57

56

I

External reference voltage input for regulated LCD voltage

Input/output port of lowest analog LCD voltage (V5)

–

I/O

Input/output port of third most positive analog LCD voltage (V3

or V4)

R13

R23

57

60

I/O

–

Input/output port of second most positive analog LCD voltage

(V2)

Input/output port of most positive analog LCD voltage (V1)

CAUTION: LCDCAP/R33 must be connected to DVSS if not

used.

R33

61

I/O

–

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表7-2. Signal Descriptions (continued)

PIN NO.⁽¹⁾

PIN TYPE⁽²⁾

DESCRIPTION

64-PIN

80-PIN PN PM OR

RGC

FUNCTION SIGNAL NAME

S0

51

50

49

48

47

46

45

44

43

42

40

39

38

37

36

35

30

29

28

27

24

23

14

13

12

64

66

65

63

62

55

54

57

56

53

75

76

34

33

O

I

LCD segment output 0

LCD segment output 1

LCD segment output 2

LCD segment output 3

LCD segment output 4

LCD segment output 5

LCD segment output 6

LCD segment output 7

LCD segment output 8

LCD segment output 9

LCD segment output 10

LCD segment output 11

LCD segment output 12

LCD segment output 13

LCD segment output 14

LCD segment output 15

LCD segment output 16

LCD segment output 17

LCD segment output 18

LCD segment output 19

LCD segment output 20

LCD segment output 21

LCD segment output 22

LCD segment output 23

LCD segment output 24

LCD segment output 25

LCD segment output 26

LCD segment output 27

LCD segment output 28

LCD segment output 29

LCD segment output 30

LCD segment output 31

LCD segment output 32

LCD segment output 33

LCD segment output 34

LCD segment output 35

LCD segment output 36

–

28

27

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

S11

S12

S13

S14

S15

S16

S17

LCD

S18

S19

S20

S21

S22

S23

S24

S25

S26

S27

S28

S29

S30

S31

S32

S33

S34

S35

S36

MTIF_PIN_EN

MTIF_OUT_IN

Meter test Interface pin enable

Meter test Interface In/Out

MTIF

I/O

24

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表7-2. Signal Descriptions (continued)

PIN NO.⁽¹⁾

PIN TYPE⁽²⁾

DESCRIPTION

64-PIN

80-PIN PN PM OR

RGC

FUNCTION SIGNAL NAME

AVCC1

AVSS1

AVSS2

AVSS3

AVSS4

1

80

1

64

P

O

Analog power supply

Analog ground supply

Digital power supply

Digital ground supply

USS power supply

6

5

9

8

77

61

DVCC1

Power

22

18

DVCC3

59

49

DVSS1

DVSS2

DVSS3

PVCC

21

17

41

33

58

48

70, 71

69, 72

34, 56

56, 57

55, 58

28

PVSS

USS ground supply

RTC

RTCCLK

RTC clock calibration output

Clock signal input –eUSCI_A0 SPI slave mode

Clock signal output –eUSCI_A0 SPI master mode

UCA0CLK

2, 35

2, 29

I/O

UCA0SIMO

UCA0SOMI

UCA0STE

13, 37

14, 38

3, 36

31

32

30

I/O

Slave in/master out –eUSCI_A0 SPI mode

Slave out/master in –eUSCI_A0 SPI mode

Slave transmit enable –eUSCI_A0 SPI mode

Clock signal input –eUSCI_A1 SPI slave mode

Clock signal output –eUSCI_A1 SPI master mode

UCA1CLK

4, 27

3, 21

I/O

UCA1SIMO

UCA1SOMI

UCA1STE

25

26

19

20

I/O

Slave in/master out –eUSCI_A1 SPI mode

Slave out/master in –eUSCI_A1 SPI mode

Slave transmit enable –eUSCI_A1 SPI mode

5, 28

4, 22

Clock signal input –eUSCI_A2 SPI slave mode

Clock signal output –eUSCI_A2 SPI master mode

UCA2CLK

45

36

I/O

UCA2SIMO

UCA2SOMI

UCA2STE

19, 43

20, 44

46

34

35

37

I/O

Slave in/master out –eUSCI_A2 SPI mode

Slave out/master in –eUSCI_A2 SPI mode

Slave transmit enable –eUSCI_A2 SPI mode

SPI

Clock signal input –eUSCI_A3 SPI slave mode

Clock signal output –eUSCI_A3 SPI master mode

UCA3CLK

30

24

I/O

UCA3SIMO

UCA3SOMI

UCA3STE

27, 36

28, 35

29

21, 30

22, 29

23

I/O

Slave in/master out –eUSCI_A3 SPI mode

Slave out/master in –eUSCI_A3 SPI mode

Slave transmit enable –eUSCI_A3 SPI mode

Clock signal input –eUSCI_B0 SPI slave mode

Clock signal output –eUSCI_B0 SPI master mode

UCB0CLK

32

26

I/O

UCB0SIMO

UCB0SOMI

UCB0STE

29

30

31

23

24

25

I/O

Slave in/master out –eUSCI_B0 SPI mode

Slave out/master in –eUSCI_B0 SPI mode

Slave transmit enable –eUSCI_B0 SPI mode

Clock signal input –eUSCI_B1 SPI slave mode

Clock signal output –eUSCI_B1 SPI master mode

UCB1CLK

47

38

I/O

UCB1SIMO

UCB1SOMI

UCB1STE

48, 75

49, 76

50

39

40

41

I/O

Slave in/master out –eUSCI_B1 SPI mode

Slave out/master in –eUSCI_B1 SPI mode

Slave transmit enable –eUSCI_B1 SPI mode

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表7-2. Signal Descriptions (continued)

PIN NO.⁽¹⁾

PIN TYPE⁽²⁾

DESCRIPTION

64-PIN

80-PIN PN PM OR

RGC

FUNCTION SIGNAL NAME

NMI

System

16

12

I

Nonmaskable interrupt input

RST

16

I/O

O

Reset input active low

TA0.0

3

TA0 CCR0 capture: CCI0A input, compare: Out0

TA0 CCR0 capture: CCI0B input, compare: Out0

TA0 CCR1 capture: CCI1A input, compare: Out1

TA0 CCR2 capture: CCI2A input, compare: Out2

TA0 compare: Out2 enabled by COUT

TA0 input clock

–

47

38

TA0.1

Timer_A0

62

–

TA0.2

50

41

TA0.2

TA0CLK

TA1.0

TA1.1

23

–

42

3

12, 39, 51

I

4

I/O

O

TA1 CCR0 capture: CCI0A input, compare: Out0

TA1 CCR0 capture: CCI0B input, compare: Out0

TA1 CCR0 compare: Out0

55

46

19

25

63

I/O

O

TA1 CCR1 capture: CCI1A input, compare: Out1

TA1 CCR1 compare: Out1

–

Timer_A1

TA1.1

26

20

TA1.2

13

I/O

O

TA1 CCR2 capture: CCI2A input, compare: Out2

TA1 CCR2 compare: Out2

–

TA1.2

55

46

TA1.2C

TA1CLK

TA4.0

13

O

TA1 CCR2 compare: Out2 enabled by COUT

TA1 input clock

–

27

4

12, 33, 39

I

5

23

I/O

O

TA4 CCR0 capture: CCI0A input, compare: Out0

TA4 CCR0 capture: CCI0B input, compare: Out0

TA4 CCR0 compare: Out0

TA4.0

–

TA4.0

47

38

TA4.1

14

I/O

O

TA4CCR1 capture: CCI1B input, compare: Out1

TA4 CCR1 capture: CCI1A input, compare: Out1

TA4 CCR1 compare: Out1

–

39

28

Timer_A4

TA4.1

48

TA4.1

34

TA4.1C

TA4CLK

TB0.0

TB0.1

TB0.2

TB0.3

TB0.4

TB0.5

TB0.6

TB0CLK

TB0OUTH

14

O

TA4 CCR1 compare: Out1 enabled by COUT

TA4 input clock

–

14

34

18, 40

43

I

I/O

O

TB0 CCR0 capture: CCI0B input, compare: Out0

TB0 CCR0 capture: CCI0A input, compare: Out0

TB0 CCR1 capture: CCI1A input, compare: Out1

TB0 CCR1 compare: Out1

24

–

27

35

33

44

76

I/O

O

TB0 CCR2 capture: CCI2A input, compare: Out2

TB0 CCR2 compare: Out2

–

36

37

50

25

29

26

30

45

46

I/O

I

TB0 CCR3 capture: CCI3A input, compare: Out3

TB0 CCR3 capture: CCI3B input, compare: Out3

TB0 CCR4 capture: CCI4A input, compare: Out4

TB0 CCR4 capture: CCI4B input, compare: Out4

TB0 CCR5 capture: CCI5A input, compare: Out5

TB0CCR5 capture: CCI5B input, compare: Out5

TB0 CCR6 capture: CCI6B input, compare: Out6

TB0 CCR6 capture: CCI6A input, compare: Out6

TB0 clock input

64

Timer_B0

31

35

32

36

75

–

16

47

20

12, 40,57

19, 49, 76

15

I

Switch all PWM outputs high impedance input –TB0

26

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表7-2. Signal Descriptions (continued)

PIN NO.⁽¹⁾

PIN TYPE⁽²⁾

DESCRIPTION

64-PIN

80-PIN PN PM OR

RGC

FUNCTION SIGNAL NAME

UCA0RXD

UCA0TXD

UCA1RXD

14, 38

13, 37

26

32

31

I

O

I

Receive data –eUSCI_A0 UART mode

Transmit data –eUSCI_A0 UART mode

Receive data –eUSCI_A1 UART mode

Transmit data –eUSCI_A1 UART mode

Receive data –eUSCI_A2 UART mode

Transmit data –eUSCI_A2 UART mode

Receive data –eUSCI_A3 UART mode

Transmit data –eUSCI_A3 UART mode

USS UUPS trigger

20

UCA1TXD

UART

25

19

O

I

UCA2RXD

20, 44

19, 43

28, 35

27, 36

30

16, 35

15, 34

22, 29

21, 30

24

UCA2TXD

UCA3RXD

UCA3TXD

USSTRG

O

I

O

I

USSXTIN

78

62

I

Input for an oscillator USSXT

Output for an oscillator USSXT

Buffered output clock of USSXT

USS Channel 0 RX

USSXTOUT

USSXT_BOUT

79

63

O

I

75, 10

74

9

CH0_IN

USS_A

60

CH0_OUT

73

59

I/O

I

USS Channel 0 TX

CH1_IN

CH1_OUT

XPB0

67

53

USS Channel 1 RX

68

54

I/O

O

USS Channel 1 TX

55

46

External bias output

XPB1

64

50

External bias output

(1) N/A = not available

(2) I = input, O = output, P = power

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7.4 Pin Multiplexing

Pin multiplexing for these devices is controlled by both register settings and operating modes (for example, if the

device is in test mode). For details of the settings for each pin and diagrams of the multiplexed ports, see 节

9.14.

7.5 Buffer Type

表7-3 describes the buffer types that are referenced in 表7-1.

表7-3. Buffer Type

NOMINAL

PULLUP (PU)

OR PULLDOWN

(PD)

OUTPUT DRIVE

STRENGTH

(mA)

BUFFER TYPE

(STANDARD)

NOMINAL

VOLTAGE

PU OR PD

STRENGTH

(µA)

OTHER

CHARACTERISTICS

HYSTERESIS

See analog modules in

Specifications for details

Analog⁽²⁾

3.0 V

N

Y⁽¹⁾

N

N/A

Programmable

N/A

See Typical

Characteristics

–Outputs

See General-

Purpose I/Os

LVCMOS

SVS enables hysteresis on

DVCC

Power (DVCC)⁽³⁾

N/A

Power (AVCC)⁽³⁾

Power (PVCC)⁽³⁾

3.0 V

N

N/A

Power (DVSS

and AVSS)⁽³⁾

0 V

N

N/A

(1) Only for input pins

(2) This is a switch, not a buffer.

(3) This is supply input, not a buffer.

7.6 Connection of Unused Pins

表7-4 lists the correct termination of all unused pins.

表7-4. Connection of Unused Pins

COMMENT

PIN⁽¹⁾

AVCC

PVCC

AVSS

PVSS

POTENTIAL

DV_CC

DV_SS

USS_CHx_IN,

USS_CHx_OUT

DV_SS

USSXTIN

DV_SS

USSXTOUT

Px.0 to Px.7

RST/NMI

DV_SS

Open

Switched to port function, output direction (PxDIR.n = 1)

47-kΩ pullup or internal pullup selected with 10-nF (2.2 nF⁽²⁾) pulldown

DV_CCor V_CC

PJ.0/TDO

PJ.1/TDI

PJ.2/TMS

PJ.3/TCK

The JTAG pins are shared with general-purpose I/O function (PJ.x). If not being used, these should

be switched to port function, output direction. When used as JTAG pins, these pins should remain

open.

Open

TEST

This pin always has an internal pulldown enabled.

(1) For any unused pin with a secondary function that is shared with general-purpose I/O, follow the guidelines for the Px.0 to Px.7 pins.

(2) The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire

JTAG mode with TI tools like FET interfaces or GANG programmers.

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8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

4.1

UNIT

V

Voltage applied at DVCC and AVCC pins to V_SS

Voltage applied at DVCC, AVCC, and PVCC pins to V_SS

Voltage difference between DVCC and AVCC pins⁽²⁾

Voltage difference between DVCC, AVCC, and PVCC pins⁽²⁾

Voltage applied to CHx_IN

4.1

V

±0.3

1.65

1.8

V

–0.3

Voltage applied to CHx_IN (duty cycle of 10% over 1ms)

Voltage applied to USSXTIN (USSXTOUT)

V

1.5

V

V_CC+ 0.3 V

(4.1 V Max)

Voltage applied to any other pin ⁽³⁾

V

–0.3

Diode current at any device pin

±2

mA

°C

(4)

Storage temperature, T_stg

125

–40

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device including erroneous

writes to RAM and FRAM.

(3) All voltages referenced to V_SS

.

(4) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

8.2 ESD Ratings

VALUE

UNIT

Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)(all except CHx_OUT

terminals)

±1000

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

±250

±1000

±250

Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)(on CHx_OUT

terminals)

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±1000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as

±250 V may actually have higher performance.

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MAX UNIT

8.3 Recommended Operating Conditions

TYP data are based on V_CC= 3.0 V and T_A= 25°C (unless otherwise noted)

MIN NOM

V_CC

V_SS

T_A

Supply voltage range applied at all DVCC and AVCC pins ^{(1) (3) (4) (2)}

Supply voltage range applied at PVCC pin⁽¹⁾

1.8⁽⁷⁾

2.2

0

3.6

V

Supply voltage applied at all DVSS, AVSS, and PVSS pins.

Operating free-air temperature

V

-40

85

°C

1 –

20%

C_DVCC

Capacitor value at DVCC⁽⁵⁾

µF

No FRAM wait states

(NWAITSx = 0)

0

8⁽⁹⁾

f_SYSTEM

Processor frequency (maximum MCLK frequency)⁽⁶⁾

With FRAM wait states

(NWAITSx = 1)⁽⁸⁾

MHz

0

16⁽¹⁰⁾

f_LEA

LEA processor frequency

Maximum ACLK frequency

Maximum SMCLK frequency

f_ACLK

f_SMCLK

50 kHz

16⁽¹⁰⁾MHz

(1) TI recommends powering AVCC, DVCC, PVCC pins from the same source. At a minimum, during power up, power down, and device

operation, the voltage difference among AVCC, DVCC, PVCC must not exceed the limits specified under Absolute Maximum Ratings.

Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.

(2) USS module must be disabled if AVCC and DVCC are lower than 2.2 V.

(3) Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR

resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation

for capacitor C_DVCCshould limit the slopes accordingly.

(4) Modules may have a different supply voltage range specification. Refer to the specification of the respective module in this data sheet.

(5) As decoupling capacitor for each supply pin pair of DVCC/ DVSS and AVCC/AVSS, place a low-ESR ceramic capacitor of 100 nF

(minimum) as close as possible (few millimeters) to the respective pin pairs, for PVCC/PVSS pair, place a low-ESR ceramic capacitor

of 22 uF (minimum) as close as possible (few millimeters) to the respective pin pairs.

(6) Modules may have a different maximum input clock specification. See the specification of each module in this data sheet.

(7) The minimum supply voltage is defined by the supervisor SVS levels. See the PMM SVS threshold parameters for the exact values.

(8) Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always

excecuted without wait states.

(9) DCO settings and HF cyrstals with a typical value less than or equal to the specified MAX value are permitted.

(10) DCO settings and HF cyrstals with a typical value less than or equal to the specified MAX value are permitted. If a clock source with a

higher typical value is used, the clock must be divided in the clock system.

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8.4 Active Mode Supply Current Into V_CCExcluding External Current

over recommended operating free-air temperature (unless otherwise noted)^{(1) (2)}

FREQUENCY (f_MCLK= f_SMCLK

)

1 MHz

4 MHz

8 MHz

12 MHz

16 MHz

1 WAIT STATE

(NWAITSx = 1)

EXECUTION

MEMORY

PARAMETER

V_CC

0 WAIT STATES 0 WAIT STATES 0 WAIT STATES 1 WAIT STATE

(NWAITSx = 0) (NWAITSx = 0) (NWAITSx = 0) (NWAITSx = 1)

UNIT

TYP

MAX

TYP

MAX

TYP

MAX

TYP

MAX

TYP

MAX

I_{AM, FRAM_UNI}

FRAM

3.0 V

225

665

1275

1550

1970

µA

(Unified memory)⁽³⁾

FRAM

0% cache hit

ratio

I_{AM, FRAM}(0%)^{(4) (5)}

420

275

220

192

125

1455

855

650

535

237

2850

1650

1240

1015

450

2330

1770

1490

1290

670

3000

2265

1880

1620

790

FRAM

50% cache hit

ratio

I_{AM, FRAM}(50%)^{(4) (5)}

I_{AM, FRAM}(66%)^{(4) (5)}

I_{AM, FRAM}(75%)^{(4) (5)}

I_{AM, FRAM}(100%^{(4) (5)}

3.0 V

1022

1888

1443

1170

2041

1735

1490

2606

2197

1870

µA

FRAM

66% cache hit

ratio

FRAM

75% cache hit

ratio

261

182

FRAM

100% cache hit

ratio

(6) (5)

I_{AM, RAM}

RAM

3.0 V

140

90

323

292

590

540

880

830

1070

1020

µA

(7) (5)

I_{AM, RAM only}

1313

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) Characterized with program executing typical data processing.

f_ACLK= 32768 Hz, f_MCLK= f_SMCLK= f_DCOat specified frequency, except for 12 MHz. For 12 MHz, f_DCO= 24 MHz and

f_MCLK= f_SMCLK= f_DCO/2.

At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency

(f_MCLK,eff) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by the number of wait

states or the cache hit ratio.

The following equation can be used to compute f_MCLK,eff

:

f_MCLK,eff= f_MCLK/ [wait states × (1 –cache hit ratio) + 1]

For example, with 1 wait state and 75% cache hit ratio, f_MCKL,eff= f_MCLK/ [1 × (1 –0.75) + 1] = f_MCLK/ 1.25.

(3) Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM.

(4) Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache

hit ratio represents number cache accesess divided by the total number of FRAM accesses. For example, a 75% ratio implies three of

every four accesses is from cache, and the remaining are FRAM accesses.

(5) See 节8.5 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best

linear fit using the typical data shown in 节8.4.

(6) Program and data reside entirely in RAM. All execution is from RAM.

(7) Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.

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8.5 Typical Characteristics, Active Mode Supply Currents

3000

I(AM,0%)

I(AM,50%)

2500

I(AM,66%)

I(AM,75%)

I(AM,75%)[µA] ~ 120 × f[MHz] + 68

2000

1500

1000

500

0

I(AM,100%)

I(AM,RAMonly)

0

1

2

3

4

5

6

7

8

9

MCLK Frequency (MHz)

A. I_{(AM, cache hit ratio)}: Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as

specified. Cache hit ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 75% ratio

implies three of every four accesses is from cache, and the remaining are FRAM accesses.

B. I_{(AM, RAM only)}: Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.

图8-1. Typical Active Mode Supply Currents, No Wait States

8.6 Low-Power Mode (LPM0, LPM1) Supply Currents Into V_CCExcluding External Current

over recommended operating free-air temperature (unless otherwise noted)^{(1) (2)}

FREQUENCY (f_SMCLK

)

PARAMETER

V_CC

1 MHz

TYP

4 MHz

TYP

8 MHz

12 MHz

TYP

276

16 MHz

TYP

250

UNIT

MAX

148

70

MAX

TYP

180

190

136

MAX

316

2.2 V

3.0 V

2.2 V

3.0 V

80

95

40

115

125

70

I_LPM0

µA

178

245

286

340

265

230

205

I_LPM1

70

235

210

250

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) Current for watchdog timer clocked by SMCLK included.

f_ACLK= 32768 Hz, f_MCLK= 0 MHz, f_SMCLK= f_DCOat specified frequency, except for 12 MHz. For 12 MHz, f_DCO= 24 MHz and

f_MCLK= f_SMCLK= f_DCO/ 2.

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8.7 Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into V_CC) Excluding External

Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEMPERATURE

PARAMETER

25°C

TYP

60°C

TYP

85°C

TYP

UNIT

–40°C

TYP

V_CC

MAX

2.2 V

3 V

0.8

0.6

0.5

0.8

1.3

1.2

1.0

4.1

4.0

3.8

2.2

10.8

10.7

10.5

4.5

Low-power mode 2, 12-pF

crystal^{(1) (3) (4)}

I_LPM2,XT12

I_LPM2,XT3.7

I_LPM2,VLO

μA

2.2 V

3 V

Low-power mode 2, 3.7-pF

crystal^{(1) (2) (4)}

2.2 V

3 V

Low-power mode 2, VLO,

includes SVS⁽⁵⁾

Low-power mode 3, 12-pF

2.2 V

1.1

10.1

I_LPM3,XT12

crystal, includes SVS^{(1) (3)}

μA

(6)

3 V

2.2 V

3 V

0.8

0.5

1.0

0.7

2.2

2.1

4.5

4.4

Low-power mode 3, 3.7-pF

9.8

9.6

I_LPM3,XT3.7

crystal, excludes SVS^{(1) (2)}

μA

(7)

2.2 V

3 V

0.4

0.5

1.2

1.1

1.9

1.4

4.2

2.6

Low-power mode 3,

I_LPM3,VLO

VLO, excludes SVS⁽⁸⁾

Low-power mode 3,

VLO, excludes SVS, RAM

powered-down

2.2 V

0.36

0.47

2.9

8.2

I_LPM3,VLO,

μA

RAMoff

3 V

0.36

0.47

1.4

2.6

completely⁽⁸⁾

2.2 V

3 V

0.5

0.3

0.6

1.2

1.1

1.0

1.9

1.7

1.2

4.3

4.0

2.5

9.7

9.4

8

Low-power mode 4,

includes SVS⁽⁹⁾

I_LPM4,SVS

μA

0.8

2.2 V

3 V

0.4

Low-power mode 4,

excludes SVS⁽¹⁰⁾

I_LPM4

0.4

Low-power mode 4,

excludes SVS, RAM

powered-down

2.2 V

0.37

2.8

I_LPM4,RAMoff

I_IDLE,GroupA

I_IDLE,GroupB

I_IDLE,GroupC

μA

3 V

0.3

0.37

0.02

1.2

2.5

completely⁽¹⁰⁾

Additional idle current if one

or more modules from

Group A (see 表9-3) are

activated in LPM3 or LPM4

0.3

Additional idle current if one

or more modules from

Group B (see 表9-3) are

activated in LPM3 or LPM4

3 V

0.02

0.35

0.38

Additional idle current if one

or more modules from

Group C (see 表9-3) are

activated in LPM3 or LPM4

(1) Not applicable for devices with HF crystal oscillator only.

(2) Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are

chosen to closely match the required 3.7-pF load.

(3) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance

are chosen to closely match the required 12.5-pF load.

(4) Low-power mode 2, crystal oscillator test conditions:

Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included.

CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2), f_XT1= 32768 Hz, f_ACLK= f_XT1, f_MCLK= f_SMCLK= 0 MHz

(5) Low-power mode 2, VLO test conditions:

Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout and SVS included.

CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2), f_XT1= 0 Hz, f_ACLK= f_VLO, f_MCLK= f_SMCLK= 0 MHz

(6) Low-power mode 3, 12-pF crystal including SVS test conditions:

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Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3), f_XT1= 32768 Hz, f_ACLK= f_XT1, f_MCLK= f_SMCLK= 0 MHz

Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to

additional idle current. Refer to the idle currents specified for the respective peripheral groups.

(7) Low-power mode 3, 3.7-pF crystal excluding SVS test conditions:

Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE

= 0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3), f_XT1= 32768 Hz, f_ACLK= f_XT1, f_MCLK= f_SMCLK= 0 MHz

Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to

additional idle current. Refer to the idle currents specified for the respective peripheral groups.

(8) Low-power mode 3, VLO excluding SVS test conditions:

Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). RAM disabled (RCCTL0 = 5A55h). Current for

brownout included. SVS disabled (SVSHE = 0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3), f_XT1= 0 Hz, f_ACLK= f_VLO, f_MCLK= f_SMCLK= 0 MHz

Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to

additional idle current. Refer to the idle currents specified for the respective peripheral groups.

(9) Low-power mode 4 including SVS test conditions:

Current for brownout and SVS included (SVSHE = 1).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4), f_XT1= 0 Hz, f_ACLK= 0 Hz, f_MCLK= f_SMCLK= 0 MHz

Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to

additional idle current. Refer to the idle currents specified for the respective peripheral groups.

(10) Low-power mode 4 excluding SVS test conditions:

Current for brownout included. SVS disabled (SVSHE = 0). RAM disabled (RCCTL0 = 5A55h).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4), f_XT1= 0 Hz, f_ACLK= 0 Hz, f_MCLK= f_SMCLK= 0 MHz

Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to

additional idle current. Refer to the idle currents specified for the respective peripheral groups.

8.8 Low-Power Mode With LCD Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEMPERATURE (T_A)

PARAMETER

V_CC

-40°C

TYP

25°C

TYP

60°C

TYP

85°C

TYP

UNIT

MAX

Low-power mode 3 (LPM3)

current,12 pF crystal, LCD

4-mux mode, external

I_LPM3,XT12

LCD,

ext. bias

3.0 V

0.9

1.1

2.5

5.1

µA

biasing, excludes SVS^{(1) (2)}

Low-power mode 3 (LPM3)

current,12 pF crystal, LCD

4-mux mode, internal

I_LPM3,XT12

LCD,

int. bias

3.0 V

1.3

1.4

2.0

2.2

4.5

4.9

12.5

µA

biasing, charge pump

disabled, excludes SVS⁽¹⁾

(3)

Low-power mode 3 (LPM3)

current,12 pF crystal, LCD

4-mux mode, internal

biasing, charge pump

enabled, 1/3 bias, excludes

SVS^{(1) (4)}

2.2 V

3.0 V

3.6

3.4

4

5.1

4.9

8.1

µA

I_LPM3,XT12

LCD,CP

3.7

(1) Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE

= 0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),

f_XT1= 32768 Hz, f_ACLK= f_XT1, f_MCLK= f_SMCLK= 0 MHz

Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to

additional idle current - idle current of Group containing LCD module already included. Refer to the idle currents specified for the

respective peripheral groups.

(2) LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump

disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (f_LCD= 32768 Hz / 32 / 4 = 256 Hz)

Current through external resistors not included (voltage levels are supplied by test equipment).

Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.

(3) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump

disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (f_LCD= 32768 Hz / 32 / 4 = 256 Hz)

Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.

(4) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump

enabled), VLCDx = 1000 (V_LCD= 3 V typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (f_LCD= 32768 Hz / 32 / 4 = 256 Hz)

34

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Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.

8.9 Low-Power Mode (LPMx.5) Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEMPERTURE (T_A)

PARAMETER

V_CC

25°C

TYP

60°C

TYP

85°C

TYP MAX

UNIT

–40°C

TYP

MAX

Low-power mode 3.5, 12-

2.2 V

3.0 V

2.2 V

3.0 V

0.45

0.3

0.5

0.55

0.4

0.75

0.65

I_LPM3.5,XT12

pF crystal including SVS⁽¹⁾

μA

(3) (4)

Low-power mode 3.5, 3.7-

0.35

I_LPM3.5,XT3.7pF crystal excluding SVS⁽¹⁾

(2) (5)

0.3

0.4

2.2 V

3.0 V

2.2 V

3.0 V

0.23

0.2

0.28

0.4

Low-power mode 4.5,

I_LPM4.5,SVS

μA

including SVS⁽⁶⁾

0.035

0.045

0.075

0.15

Low-power mode 4.5,

I_LPM4.5

excluding SVS⁽⁷⁾

(1) Not applicable for devices with HF crystal oscillator only.

(2) Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are

chosen to closely match the required 3.7-pF load.

(3) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance

are chosen to closely match the required 12.5-pF load.

(4) Low-power mode 3.5, 1-pF crystal including SVS test conditions:

Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

f_XT1= 32768 Hz, f_ACLK= f_XT1, f_MCLK= f_SMCLK= 0 MHz

(5) Low-power mode 3.5, 3.7-pF crystal excluding SVS test conditions:

Current for RTC clocked by XT1 included.Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

f_XT1= 32768 Hz, f_ACLK= f_XT1, f_MCLK= f_SMCLK= 0 MHz

(6) Low-power mode 4.5 including SVS test conditions:

Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

f_XT1= 0 Hz, f_ACLK= 0 Hz, f_MCLK= f_SMCLK= 0 MHz

(7) Low-power mode 4.5 excluding SVS test conditions:

Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

f_XT1= 0 Hz, f_ACLK= 0 Hz, f_MCLK= f_SMCLK= 0 MHz

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8.10 Typical Characteristics, Low-Power Mode Supply Currents

图8-2, 图8-3, 图8-4, and 图8-5 show the supply current vs temperature typical characterstics for selected low-power

modes.

3

2.5

2

3

2.5

2

3.0 V, SVS off

2.2 V, SVS off

3.0 V, SVS on

2.2 V, SVS on

3.0 V, SVS off

2.2 V, SVS off

3.0 V, SVS on

2.2 V, SVS on

1.5

1

1.5

1

0.5

0

0.5

0

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature (°C)

图8-2. LPM3 Supply Current vs Temperature (LPM3,XT3.7)

图8-3. LPM4 Supply Current vs Temperature (LPM4,SVS)

0.7

3.0 V, SVS off

2.2 V, SVS off

0.6

2.2 V, SVS off

0.6

3.0 V, SVS on

2.2 V, SVS on

0.5

0.4

0.3

0.2

0.1

0

0.4

0.3

0.2

0.1

0

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature (°C)

图8-4. LPM3.5 Supply Current vs Temperature (LPM3.5,XT3.7)

图8-5. LPM4.5 Supply Current vs Temperature (LPM4.5)

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8.11 Current Consumption per Module

MODULE⁽¹⁾

Timer_A

Timer_B

eUSCI_A

eUSCI_B

RTC_C

MPY

TEST CONDITIONS

REFERENCE CLOCK

Module input clock

MIN

TYP MAX

UNIT

2.5

3.7

μA/MHz

nA

Module input clock

32 kHz

UART mode

SPI mode

6.3

4.4

100

28

7.0

4.8

I²C mode, 100 kbaud

Only from start to end of operation

256-point complex FFT, data = non-zero

256-point complex FFT, data = zero

MCLK

μA/MHz

CRC16

CRC32

LEA

MCLK

3.3

78

MCLK

70

85 µA/MHz

60 µA/MHz

LEA

MCLK

55

Generator and counter are enabled at 256 Hz, no

terminal activity. Pulse rate:15 pulses

MTIF

LFXT

0.20

µA

(1) For other module currents not listed here, see the module-specific parameter sections.

8.12 Thermal Resistance Characteristics

THERMAL METRIC⁽¹⁾

PACKAGE

VALUE⁽²⁾

53.3

15.2

28.4

28.0

0.7

UNIT

°C/W

Junction-to-ambient thermal resistance, still air

Junction-to-case (top) thermal resistance

Rθ_JA

Rθ_JC(TOP)

Rθ_JB

Junction-to-board thermal resistance

QFP-80 (PN)

Junction-to-board thermal characterization parameter

Junction-to-top thermal characterization parameter

Junction-to-case (bottom) thermal resistance

Junction-to-ambient thermal resistance, still air

Junction-to-case (top) thermal resistance

Ψ_JB

Ψ_JT

N/A⁽³⁾

56.6

16.4

27.8

27.5

0.8

Rθ_JC(BOTTOM)

Rθ_JA

Rθ_JC(TOP)

Rθ_JB

Junction-to-board thermal resistance

QFP-64 (PM)

Junction-to-board thermal characterization parameter

Junction-to-top thermal characterization parameter

Junction-to-case (bottom) thermal resistance

Junction-to-ambient thermal resistance, still air

Junction-to-case (top) thermal resistance

Ψ_JB

Ψ_JT

N/A

Rθ_JC(BOTTOM)

Rθ_JA

24.7

12.3

8.8

Rθ_JC(TOP)

Rθ_JB

Junction-to-board thermal resistance

RGC-64

Junction-to-board thermal characterization parameter

Junction-to-top thermal characterization parameter

Junction-to-case (bottom) thermal resistance

8.7

Ψ_JB

0.1

Ψ_JT

N/A

Rθ_JC(BOTTOM)

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (Rθ_JC) value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC

standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

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(3) N/A = Not applicable

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8.13 Timing and Switching Characteristics

8.13.1 Power Supply Sequencing

TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up, power

down, and device operation, the voltage difference between AVCC and DVCC must not exceed the limits

specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the device

including erroneous writes to RAM and FRAM.

节8.13.1.1 lists the power ramp requirements for brownout and power up.

8.13.1.1 Brownout and Device Reset Power Ramp Requirements

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Brownout power-down level⁽¹⁾

Brownout power-up level⁽¹⁾

TEST CONDITIONS

| dDV_CC/d_t| < 3 V/s

| dDV_CC/d_t| < 3 V/s⁽²⁾

MIN

MAX UNIT

V_{VCC_BOR–}

V_{VCC_BOR+}

0.7

1.66

1.68

V

0.79

(1) Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR

resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation

for capacitor C_DVCCshould limit the slopes accordingly.

(2) The brownout levels are measured with a slowly changing supply.

节8.13.1.2 lists the characteristics of the SVS.

8.13.1.2 SVS

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

I_SVSH,LPM

V_SVSH-

SVS_Hcurrent consumption, low power modes

SVS_Hpower-down level

170

300

1.85

1.99

120

10

nA

V

1.75

1.77

40

1.80

1.88

V_SVSH+

SVS_Hpower-up level

V

V_{SVSH_hys}

t_{PD,SVSH, AM}

SVS_Hhysteresis

mV

µs

SVS_Hpropagation delay, active mode

dV_Vcc/dt = –10 mV/µs

8.13.2 Reset Timing

节8.13.2.1 lists the requirements for the reset input.

8.13.2.1 Reset Input

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

t_(RST)External reset pulse duration on RST ⁽¹⁾

V_CC

MIN

TYP MAX UNIT

2.2 V, 3.0 V

2

µs

(1) Not applicable if RST/NMI pin configured as NMI .

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8.13.3 Clock Specifications

8.13.3.1 Low-Frequency Crystal Oscillator, LFXT

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽⁴⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP MAX UNIT

f_OSC= 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {0},

T_A= 25°C, C_L,eff= 3.7 pF, ESR ≈44 kΩ

I_VCC.LFXT

Current consumption

3.0 V

180

185

225

nA

f_OSC= 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {1},

T_A= 25°C, C_L,eff= 6 pF, ESR ≈40 kΩ

3.0 V

f_OSC= 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {2},

T_A= 25°C, C_L,eff= 9 pF, ESR ≈40 kΩ

f_OSC= 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {3},

T_A= 25°C, C_L,eff= 12.5 pF, ESR ≈40 kΩ

330

nA

Hz

LFXT oscillator crystal

frequency

f_LFXT

LFXTBYPASS = 0

32768

Measured at ACLK,

f_LFXT= 32768 Hz

DC_LFXT

LFXT oscillator duty cycle

30%

10.5

70%

LFXT oscillator logic-level

square-wave input

frequency

f_LFXT,SW

LFXTBYPASS = 1^{(5) (8)}

32.768

50 kHz

LFXT oscillator logic-level

square-wave input duty

cycle

DC_{LFXT, SW}

LFXTBYPASS = 1

30%

70%

LFXTBYPASS = 0, LFXTDRIVE = {1},

f_LFXT= 32768 Hz, C_L,eff= 6 pF

210

300

2

Oscillation allowance for

LF crystals⁽⁹⁾

OA_LFXT

kΩ

LFXTBYPASS = 0, LFXTDRIVE = {3},

f_LFXT= 32768 Hz, C_L,eff= 12.5 pF

Integrated load capacitance

at LFXIN terminal^{(6) (7)}

C_LFXIN

pF

Integrated load capacitance

at LFXOUT terminal^{(6) (7)}

C_LFXOUT

2

f_OSC= 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {0},

T_A= 25°C, C_L,eff= 3.7 pF

3.0 V

800

t_START,LFXT

Start-up time⁽²⁾

ms

Hz

f_OSC= 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {3},

T_A= 25°C, C_L,eff= 12.5 pF

1000

Oscillator fault frequency⁽³⁾

f_Fault,LFXT

0

3500

(1)

(1) Measured with logic-level input frequency but also applies to operation with crystals.

(2) Includes start-up counter of 1024 clock cycles.

(3) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications may set the

flag. A static condition or stuck at fault condition will set the flag.

(4) To improve EMI on the LFXT oscillator, observe the following guidelines:

•

Keep the trace between the device and the crystal as short as possible.

Design a good ground plane around the oscillator pins.

Prevent crosstalk from other clock or data lines into oscillator pins LFXIN and LFXOUT.

Avoid running PCB traces underneath or adjacent to the LFXIN and LFXOUT pins.

Use assembly materials and processes that avoid any parasitic load on the oscillator LFXIN and LFXOUT pins.

If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.

(5) When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics

defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DC_{LFXT, SW}

.

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(6) This represents all the parasitic capacitance present at the LFXIN and LFXOUT terminals, respectively, including parasitic bond and

package capacitance. The effective load capacitance, C_L,effcan be computed as C_IN× C_OUT/ (C_IN+ C_OUT), where C_INand C_OUTis the

total capacitance at the LFXIN and LFXOUT terminals, respectively.

(7) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers.

Recommended effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF.

The PCB adds additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective

load capacitance of the selected crystal is met.

(8) Maximum frequency of operation of the entire device cannot be exceeded.

(9) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the

LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following

guidelines, but should be evaluated based on the actual crystal selected for the application:

•

For LFXTDRIVE = {0}, C_{L,eff f}= 3.7 pF

For LFXTDRIVE = {1}, C_{L,eff f}= 6 pF

For LFXTDRIVE = {2}, 6 pF ≤C_L,eff≤9 pF

For LFXTDRIVE = {3}, 9 pF ≤C_L,eff≤12.5 pF

8.13.3.2 High-Frequency Crystal Oscillator, HFXT

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽⁵⁾

PARAMETER

TEST CONDITIONS

f_OSC= 4 MHz,

HFXTBYPASS = 0, HFXTDRIVE = 0,

HFFREQ = 1⁽⁸⁾

V_CC

MIN

TYP

MAX UNIT

,

75

T_A= 25°C, C_L,eff= 18 pF,

typical ESR, C_shunt

f_OSC= 8 MHz,

HFXTBYPASS = 0, HFXTDRIVE = 1,

HFFREQ = 1,

T_A= 25°C, C_L,eff= 18 pF,

typical ESR, C_shunt

120

190

250

HFXT oscillator crystal current HF

mode at typical ESR

I_DVCC.HFXT

3.0 V

μA

f_OSC= 16 MHz,

HFXTBYPASS = 0, HFXTDRIVE = 2,

HFFREQ = 2,

T_A= 25°C, C_L,eff= 18 pF,

typical ESR, C_shunt

f_OSC= 24 MHz

HFXTBYPASS = 0, HFXTDRIVE = 3,

HFFREQ = 3,

T_A= 25°C, C_L,eff= 18 pF,

typical ESR, C_shunt

HFXTBYPASS = 0, HFFREQ = 1^{(8) (7)}

HFXTBYPASS = 0, HFFREQ = 2⁽⁷⁾

HFXTBYPASS = 0, HFFREQ = 3⁽⁷⁾

Measured at SMCLK, f_HFXT= 16 MHz

HFXTBYPASS = 1, HFFREQ = 0^{(6) (7)}

HFXTBYPASS = 1, HFFREQ = 1^{(6) (7)}

HFXTBYPASS = 1, HFFREQ = 2^{(6) (7)}

HFXTBYPASS = 1, HFFREQ = 3^{(6) (7)}

4

8.01

16.01

40%

0.9

8

HFXT oscillator crystal frequency,

crystal mode

f_HFXT

16 MHz

24

60%

4

DC_HFXT

HFXT oscillator duty cycle

50%

HFXT oscillator logic-level

square-wave input frequency,

bypass mode

4.01

8.01

16.01

8

f_HFXT,SW

MHz

16

24

HFXT oscillator logic-level

square-wave input duty cycle

DC_{HFXT, SW}

HFXTBYPASS = 1

40%

60%

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MAX UNIT

8.13.3.2 High-Frequency Crystal Oscillator, HFXT (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽⁵⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

HFXTBYPASS = 0, HFXTDRIVE = 0,

HFFREQ = 1⁽⁸⁾

,

450

f_HFXT,HF= 4 MHz, C_L,eff= 16 pF

HFXTBYPASS = 0, HFXTDRIVE = 1,

HFFREQ = 1,

f_HFXT,HF= 8 MHz, C_L,eff= 16 pF

320

200

Oscillation allowance for

HFXT crystals⁽⁹⁾

OA_HFXT

Ω

HFXTBYPASS = 0, HFXTDRIVE = 2,

HFFREQ = 2,

f_HFXT,HF= 16 MHz, C_L,eff= 16 pF

HFXTBYPASS = 0, HFXTDRIVE = 3,

HFFREQ = 3,

f_HFXT,HF= 24 MHz, C_L,eff= 16 pF

f_OSC= 4 MHz,

HFXTBYPASS = 0, HFXTDRIVE = 0,

HFFREQ = 1,

T_A= 25°C, C_L,eff= 16 pF

3.0 V

1.6

0.6

t_START,HFXTStart-up time⁽¹⁰⁾

ms

pF

f_OSC= 24 MHz,

HFXTBYPASS = 0, HFXTDRIVE = 3,

HFFREQ = 3,

T_A= 25°C, C_L,eff= 16 pF

Integrated load capacitance at

C_HFXIN

2

HFXIN terminaI^{(1) (2)}

Integrated load capacitance at

HFXOUT terminaI^{(1) (2)}

C_HFXOUT

f_Fault,HFXT

pF

Oscillator fault frequency^{(4) (3)}

0

800 kHz

(1) This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bond and

package capacitance. The effective load capacitance, C_L,effcan be computed as C_IN× C_OUT/ (C_IN+ C_OUT), where C_INand C_OUTis the

total capacitance at the HFXIN and HFXOUT terminals, respectively.

(2) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers.

Recommended effective load capacitance values supported are 14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF. The

PCB adds additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load

capacitance of the selected crystal is met.

(3) Measured with logic-level input frequency but also applies to operation with crystals.

(4) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications might set the

flag. A static condition or stuck at fault condition will set the flag.

(5) To improve EMI on the HFXT oscillator the following guidelines should be observed.

•

Keep the traces between the device and the crystal as short as possible.

Design a good ground plane around the oscillator pins.

Prevent crosstalk from other clock or data lines into oscillator pins HFXIN and HFXOUT.

Avoid running PCB traces underneath or adjacent to the HFXIN and HFXOUT pins.

Use assembly materials and processes that avoid any parasitic load on the oscillator LFXIN and LFXOUT pins.

If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.

(6) When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics

defined in the Schmitt-trigger Inputs section of this datasheet. Duty cycle requirements are defined by DC_{HFXT, SW}

(7) Maximum frequency of operation of the entire device cannot be exceeded.

(8) HFFREQ = {0} is not supported for HFXT crystal mode of operation.

.

(9) Oscillation allowance is based on a safety factor of 5 for recommended crystals.

(10) Includes start-up counter of 1024 clock cycles.

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8.13.3.3 DCO

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Measured at SMCLK, divide by 1,

DCORSEL = 0, DCOFSEL = 0,

DCORSEL = 1, DCOFSEL = 0

DCO frequency range 1 MHz,

trimmed

f_DCO1

1

±3.5%

MHz

DCO frequency range

2.7 MHz, trimmed

Measured at SMCLK, divide by 1,

DCORSEL = 0, DCOFSEL = 1

f_DCO2.7

f_DCO3.5

f_DCO4

2.667

3.5

4

±3.5%

MHz

DCO frequency range

3.5 MHz, trimmed

Measured at SMCLK, divide by 1,

DCORSEL = 0, DCOFSEL = 2

DCO frequency range 4 MHz, Measured at SMCLK, divide by 1,

trimmed

DCORSEL = 0, DCOFSEL = 3

Measured at SMCLK, divide by 1,

DCORSEL = 0, DCOFSEL = 4,

DCORSEL = 1, DCOFSEL = 1

DCO frequency range

5.3 MHz, trimmed

f_DCO5.3

f_DCO7

f_DCO8

5.333

±3.5%

MHz

Measured at SMCLK, divide by 1,

DCORSEL = 0, DCOFSEL = 5,

DCORSEL = 1, DCOFSEL = 2

DCO frequency range 7 MHz,

trimmed

7

8

Measured at SMCLK, divide by 1,

DCORSEL = 0, DCOFSEL = 6,

DCORSEL = 1, DCOFSEL = 3

DCO frequency range 8 MHz,

trimmed

DCO frequency range

16 MHz, trimmed

Measured at SMCLK, divide by 1,

DCORSEL = 1, DCOFSEL = 4

f_DCO16

f_DCO21

f_DCO24

16 ±3.5%⁽²⁾

21 ±3.5%⁽²⁾

24 ±3.5%⁽²⁾

MHz

DCO frequency range

21 MHz, trimmed

Measured at SMCLK, divide by 2,

DCORSEL = 1, DCOFSEL = 5

DCO frequency range

24 MHz, trimmed

Measured at SMCLK, divide by 2,

DCORSEL = 1, DCOFSEL = 6

Measured at SMCLK, divide by 1,

No external divide, all DCORSEL and

DCOFSEL settings except DCORSEL = 1,

DCOFSEL = 5 and DCORSEL = 1,

DCOFSEL = 6

f_DCO,DC

Duty cycle

48%

50%

52%

3

Based on f_signal= 10 kHz and DCO used

for 12-bit SAR ADC sampling source. This

achieves >74-dB SNR due to jitter; that is,

limited by ADC performance.

t_{DCO, JITTER}

DCO jitter

2

ns

df_DCO/dT

DCO temperature drift⁽¹⁾

3.0 V

0.01

%/°C

(1) Calculated using the box method: (MAX(–40°C to 85°C) –MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C –(–40°C))

(2) After a wakeup from LPM1, LPM2, LPM3, or LPM4, the DCO frequency f_DCOmight exceed the specified frequency range for a few

clock cycles by up to 5% before settling to the specified steady state frequency range.

8.13.3.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Current consumption

VLO frequency

TEST CONDITIONS

MIN

TYP

100

9.4

MAX UNIT

I_VLO

nA

f_VLO

Measured at ACLK

6

14

kHz

%/°C

%/V

df_VLO/d_T

df_VLO/dV_CC

f_VLO,DC

VLO frequency temperature drift

VLO frequency supply voltage drift

Duty cycle

Measured at ACLK⁽¹⁾

Measured at ACLK⁽²⁾

Measured at ACLK

0.2

0.7

40%

50%

60%

(1) Calculated using the box method: (MAX(–40°C to 85°C) –MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C –(–40°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) –MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V –1.8 V)

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8.13.3.5 Module Oscillator (MODOSC)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

μA

I_MODOSC

Current consumption

Enabled

25

f_MODOSC

MODOSC frequency

4.0

4.8

5.4 MHz

%/℃

f_MODOSC/dT

MODOSC frequency temperature drift⁽¹⁾

0.08

MODOSC frequency supply voltage

drift⁽²⁾

f_MODOSC/dV_CC

DC_MODOSC

1.4

%/V

Duty cycle (excl. first clock cycle; DC =

t_high× f)

Measured at SMCLK, divide by 1

40%

50%

60%

(1) Calculated using the box method: (MAX(–40°C to 85°C) –MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C –(–40°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) –MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V –1.8 V)

8.13.4 Wake-up Characteristics

8.13.4.1 Wake-up Times From Low-Power Modes and Reset

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEST

CONDITIONS

PARAMETER

V_CC

MIN

TYP

MAX UNIT

(Additional) wake-up time to activate the

FRAM in AM if previously disabled by the

FRAM controller or from an LPM if

immediate activation is selected for

wake up

t_{WAKE-UP FRAM}

6

10

μs

Wake-up time from LPM0 to active

mode⁽¹⁾

400 +

1.5 / f_DCO

t_{WAKE-UP LPM0}

t_{WAKE-UP LPM1}

t_{WAKE-UP LPM2}

t_{WAKE-UP LPM3}

t_{WAKE-UP LPM4}

t_{WAKE-UP LPM3.5}

2.2 V, 3.0 V

ns

Wake-up time from LPM1 to active

mode⁽¹⁾

6

μs

Wake-up time from LPM2 to active

mode⁽¹⁾

Wake-up time from LPM3 to active

mode⁽¹⁾

6.6 + 2.0/

f_DCO

9.6 + 2.5/

f_DCO

Wake-up time from LPM4 to active

mode⁽¹⁾

6.6 +

2.0 / f_DCO

9.6 +

2.5 / f_DCO

Wake-up time from LPM3.5 to active

mode⁽²⁾

350

450

SVSHE = 1

SVSHE = 0

2.2 V, 3.0 V

350

0.4

450

0.8

μs

Wake-up time from LPM4.5 to active

mode⁽²⁾

t_{WAKE-UP LPM4.5}

ms

Wake-up time from a RST pin triggered

reset to active mode⁽²⁾

t_WAKE-UP-RST

t_WAKE-UP-BOR

2.2 V, 3.0 V

480

0.5

596

1

μs

Wake-up time from power-up to active

mode ⁽²⁾

ms

(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first

externally observable MCLK clock edge with MCLKREQEN = 1. This time includes the activation of the FRAM during wake up. With

MCLKREQEN = 0, the externally observable MCLK clock is gated one additional cycle.

(2) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first

instruction of the user program is executed.

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8.13.4.2 Typical Wake-up Charges

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Charge used for activating the FRAM in AM or during wakeup

from LPM0 if previously disabled by the FRAM controller.

Q_{WAKE-UP FRAM}

Q_{WAKE-UP LPM0}

Q_{WAKE-UP LPM1}

Q_{WAKE-UP LPM2}

Q_{WAKE-UP LPM3}

16.5

nAs

Charge used to wake up from LPM0 to active mode (with

FRAM active)

3.8

21

22

28

nAs

Charge used to wake up from LPM1 to active mode (with

FRAM active)

Charge used to wake up from LPM2 to active mode (with

FRAM active)

Charge used to wake up from LPM3 to active mode (with

FRAM active)

Charge used to wake up from LPM4 to active mode (with

FRAM active)

Q_{WAKE-UP LPM4}

Q_{WAKE-UP LPM3.5}

Q_{WAKE-UP LPM4.5}

nAs

Charge used to wake up from LPM3.5 to active mode⁽²⁾

170

173

171

SVSHE = 1

SVSHE = 0

Charge used to wake up from LPM4.5 to active mode⁽²⁾

nAs

Charge used for reset from RST or BOR event to active

mode⁽²⁾

Q_{WAKE-UP-RESET}

148

(1) Charge used during the wake-up time from a given low-power mode to active mode. This does not include the energy required in

active mode (for example, for an interrupt service routine).

(2) Charge required until start of user code. This does not include the energy required to reconfigure the device.

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8.13.4.3 Typical Characteristics, Average LPM Currents vs Wake-up Frequency

10000.00

LPM0

LPM1

LPM2,XT12

1000.00

LPM3,XT12

LPM3.5,XT12

100.00

10.00

1.00

0.10

0.001

0.01

0.1

1

10

100

1000

10000

100000

Wake-up Frequency (Hz)

NOTE: The average wake-up current does not include the energy required in active mode; for example, for an

interrupt service routine or to reconfigure the device.

图8-6. Average LPM Currents vs Wake-up Frequency at 25°C

10000.00

LPM0

LPM1

LPM2,XT12

1000.00

LPM3,XT12

LPM3.5,XT12

100.00

10.00

1.00

0.10

0.001

0.01

0.1

1

10

100

1000

10000

100000

Wake-up Frequency (Hz)

NOTE: The average wake-up current does not include the energy required in active mode; for example, for an

interrupt service routine or to reconfigure the device.

图8-7. Average LPM Currents vs Wake-up Frequency at 85°C

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8.13.5 Digital I/Os

8.13.5.1 Digital Inputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

1.2

1.65

V

V_IT+

V_IT–

V_hys

Positive-going input threshold voltage

1.65

0.55

0.75

0.44

0.60

2.25

1.00

V

1.35

Negative-going input threshold voltage

0.98

V

1.30

Input voltage hysteresis (V_IT+–V_IT–

)

For pullup: V_IN= V_SS

For pulldown: V_IN= V_CC

R_Pull

C_I,dig

C_I,ana

Pullup or pulldown resistor

20

35

3

50

kΩ

pF

nA

Input capacitance, digital only port pins

V_IN= V_SSor V_CC

Input capacitance, port pins with shared analog

functions⁽¹⁾

V_IN= V_SSor V_CC

5

I_lkg(Px.y)High-impedance input leakage current

Refer to notes ⁽²⁾and ⁽³⁾

2.2 V, 3.0 V

+20

–20

20

Ports with interrupt

capability (see block

diagram and terminal

function descriptions).

External interrupt timing (external trigger pulse

t_(int)

ns

µs

duration to set interrupt flag)⁽⁴⁾

t_(RST)

External reset pulse duration on RST ⁽⁵⁾

2

(1) If the port pins PJ.4/LFXIN and PJ.5/LFXOUT are used as digital I/Os, they are connected by a 4-pF capacitor and a 35-MΩ resistor in

series. At frequencies of approximately 1 kHz and lower, the 4-pF capacitor can add to the pin capacitance of PJ.4/LFXIN and/or PJ.5/

LFXOUT.

(2) The input leakage current is measured with V_SSor V_CCapplied to the corresponding pins, unless otherwise noted.

(3) The input leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor

is disabled.

(4) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t_(int)is met. It may be set by trigger signals

shorter than t_(int)

.

(5) Not applicable if RST/NMI pin configured as NMI .

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8.13.5.2 Digital Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

V_CC–

0.25

I_(OHmax)= –1 mA⁽¹⁾

V_CC

2.2 V

V_CC–

0.60

I_(OHmax)= –3 mA⁽²⁾

I_(OHmax)= –2 mA⁽¹⁾

I_(OHmax)= –6 mA⁽²⁾

I_(OLmax)= 1 mA⁽¹⁾

I_(OLmax)= 3 mA⁽²⁾

I_(OLmax)= 2 mA⁽¹⁾

I_(OLmax)= 6 mA⁽²⁾

V_CC

V_OH

High-level output voltage

V

V_CC–

0.25

V_CC

3.0 V

2.2 V

3.0 V

V_CC–

0.60

V_CC

V_SS

+

V_SS

0.25

V_SS

+

0.60

V_OL

Low-level output voltage

V

V_SS

+

0.25

V_SS

+

0.60

2.2 V

3.0 V

2.2 V

16

Port output frequency (with load)⁽⁵⁾

Clock output frequency⁽⁵⁾

C_L= 20 pF, R_L

MHz

(3) (4)

f_Px.y

ACLK, MCLK, or SMCLK at

configured output port,

C_L= 20 pF⁽⁴⁾

f_{Port_CLK}

3.0 V

16

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

4

3

4

3

6

4

6

4

15

t_rise,dig

Port output rise time, digital only port pins

Port output fall time, digital only port pins

C_L= 20 pF

ns

t_fall,dig

Port output rise time, port pins with shared

analog functions

t_rise,ana

Port output fall time, port pins with shared

analog functions

t_fall,ana

(1) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage

drop specified.

(2) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage

drop specified.

(3) A resistive divider with 2 × R1 and R1 = 1.6 kΩbetween V_CCand V_SSis used as load. The output is connected to the center tap of the

divider. C_L= 20 pF is connected from the output to V_SS

.

(4) The output voltage reaches at least 10% and 90% V_CCat the specified toggle frequency.

(5) The port can output frequencies at least up to the specified limit, and the port might support higher frequencies.

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8.13.5.3 Typical Characteristics, Digital Outputs

15

30

20

10

0

25°C

85°C

10

5

P1.1

0

0.5

1

1.5

2

0

0.5

1

1.5

2

2.5

3

Low-Level Output Voltage (V)

C001

V_CC= 2.2 V

V_CC= 3.0 V

图8-8. Typical Low-Level Output Current vs Low-Level Output

图8-9. Typical Low-Level Output Current vs Low-Level Output

Voltage

0

25°C

85°C

-5

-10

-20

P1.1

-15

-30

0

0.5

1

1.5

2

0

0.5

1

1.5

2

2.5

3

High-Level Output Voltage (V)

C001

V_CC= 2.2 V

V_CC= 3.0 V

图8-10. Typical High-Level Output Current vs High-Level

图8-11. Typical High-Level Output Current vs High-Level Output

Output Voltage

Voltage

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8.13.6 LEA

节8.13.6.1 lists the characteristics of the LEA.

8.13.6.1 Low-Energy Accelerator (LEA) Performance

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

Frequency for specified

performance

f_LEA

MCLK

16

350

2.6

MHz

nJ

LEA-SC subsystem energy on Complex FFT 128 pt. Q.15 with

fast fourier transform random data in LEA-RAM

V_CORE= 3 V,

MCLK = 16 MHz

W_LEA_FFT

W_LEA_FIR

LEA-SC subsystem energy on Real FIR on random Q.31 data with

finite impulse response

V_CORE= 3 V,

MCLK = 16 MHz

µJ

128 taps on 24 points

On 32 Q.31 elements with random

value out of LEA-RAM with linear

address increment

LEA-SC subsystem energy on

additions

V_CORE= 3 V,

MCLK = 16 MHz

W_LEA_ADD

6.6

nJ

8.13.7 Timer_A and Timer_B

8.13.7.1 Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK or ACLK,

External: TACLK,

f_TA

Timer_A input clock frequency

2.2 V, 3.0 V

16 MHz

Duty cycle = 50% ±10%

All capture inputs, minimum pulse

duration required for capture

t_TA,cap

Timer_A capture timing

2.2 V, 3.0 V

20

ns

8.13.7.2 Timer_B

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK or ACLK,

External: TBCLK,

f_TB

Timer_B input clock frequency

2.2 V, 3.0 V

16 MHz

Duty cycle = 50% ±10%

All capture inputs, minimum pulse

duration required for capture

t_TB,cap

Timer_B capture timing

2.2 V, 3.0 V

20

ns

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8.13.8 eUSCI

8.13.8.1 eUSCI (UART Mode) Clock Frequency

PARAMETER

CONDITIONS

MIN

MAX

UNIT

Internal: SMCLK or ACLK,

External: UCLK,

f_eUSCI

eUSCI input clock frequency

16

MHz

Duty cycle = 50% ±10%

BITCLK clock frequency

(equals baud rate in MBaud)

f_BITCLK

4

MHz

8.13.8.2 eUSCI (UART Mode) Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

UCGLITx = 0

5

30

UCGLITx = 1

UCGLITx = 2

UCGLITx = 3

20

35

50

90

ns

t_t

UART receive deglitch time⁽¹⁾

2.2 V, 3.0 V

160

220

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. Thus the selected deglitch

time can limit the maximum useable baud rate. To ensure that pulses are correctly recognized, their duration should exceed the

maximum specification of the deglitch time.

8.13.8.3 eUSCI (SPI Master Mode) Clock Frequency

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Internal: SMCLK or ACLK,

Duty cycle = 50% ±10%

f_eUSCI

eUSCI input clock frequency

16

MHz

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8.13.8.4 eUSCI (SPI Master Mode) Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX

UNIT

STE lead time, STE active to

clock

t_STE,LEAD

t_STE,LAG

t_STE,ACC

t_STE,DIS

UCSTEM = 1, UCMODEx = 01 or 10

1

UCxCLK

cycles

STE lag time, Last clock to STE

inactive

UCSTEM = 1, UCMODEx = 01 or 10

UCSTEM = 0, UCMODEx = 01 or 10

1

STE access time, STE active to

SIMO data out

2.2 V, 3.0 V

60

80

ns

STE disable time, STE inactive to

SOMI high impedance

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

40

0

t_SU,MI

SOMI input data setup time

SOMI input data hold time

SIMO output data valid time⁽²⁾

SIMO output data hold time⁽³⁾

ns

t_HD,MI

0

11

10

UCLK edge to SIMO valid,

C_L= 20 pF

t_VALID,MO

0

t_HD,MO

C_L= 20 pF

(1) f_UCxCLK= 1/2 t_LO/HIwith t_LO/HI= max(t_{VALID,MO(eUSCI)}+ t_SU,SI(Slave), t_SU,MI(eUSCI)+ t_{VALID,SO(Slave)}).

For the slave parameters t_SU,SI(Slave)and t_{VALID,SO(Slave)}, see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams

in 图8-12 and 图8-13.

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in

Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams

in 图8-12 and 图8-13.

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8.13.8.5 eUSCI (SPI Master Mode) Timing Diagrams

UCMODEx = 01

t_STE,LEAD

t_STE,LAG

STE

UCMODEx = 10

CKPL = 0

1/f_UCxCLK

UCLK

CKPL = 1

t_LOW/HIGH

t_SU,MI

t_HD,MI

SOMI

SIMO

t_HD,MO

t_VALID,MO

t_STE,ACC

t_STE,DIS

图8-12. SPI Master Mode, CKPH = 0

UCMODEx = 01

STE

t_STE,LEAD

t_STE,LAG

UCMODEx = 10

1/f_UCxCLK

CKPL = 0

UCLK

CKPL = 1

t_LOW/HIGH

t_HD,MI

t_SU,MI

SOMI

SIMO

t_HD,MO

t_VALID,MO

t_STE,DIS

t_STE,ACC

图8-13. SPI Master Mode, CKPH = 1

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8.13.8.6 eUSCI (SPI Slave Mode) Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

45

40

2

MAX UNIT

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

2.2 V

3.0 V

t_STE,LEAD

t_STE,LAG

t_STE,ACC

t_STE,DIS

t_SU,SI

STE lead time, STE active to clock

ns

STE lag time, Last clock to STE inactive

ns

3

45

ns

40

STE access time, STE active to SOMI data out

50

ns

45

STE disable time, STE inactive to SOMI high

impedance

4

7

SIMO input data setup time

SIMO input data hold time

SOMI output data valid time⁽²⁾

SOMI output data hold time⁽³⁾

ns

t_HD,SI

35

ns

35

UCLK edge to SOMI valid,

C_L= 20 pF

t_VALID,SO

0

t_HD,SO

C_L= 20 pF

ns

(1) f_UCxCLK= 1/2 t_LO/HIwith t_LO/HI≥max(t_{VALID,MO(Master)}+ t_SU,SI(eUSCI), t_{SU,MI(Master)}+ t_{VALID,SO(eUSCI)}

)

For the master parameters t_{SU,MI(Master)}and t_{VALID,MO(Master)}, see the SPI parameters of the attached master.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams

in 图8-14 and 图8-15.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in 图8-14

and 图8-15.

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8.13.8.7 eUSCI (SPI Slave Mode) Timing Diagrams

UCMODEx = 01

t_STE,LEAD

t_STE,LAG

STE

UCMODEx = 10

1/f_UCxCLK

CKPL = 0

UCLK

CKPL = 1

t_SU,SI

t_LOW/HIGH

t_HD,SI

SIMO

t_HD,SO

t_VALID,SO

t_STE,ACC

t_STE,DIS

SOMI

图8-14. SPI Slave Mode, CKPH = 0

UCMODEx = 01

UCMODEx = 10

t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

UCLK

CKPL = 1

t_LOW/HIGH

t_HD,SI

t_SU,SI

SIMO

t_HD,SO

t_VALID,SO

t_STE,ACC

t_STE,DIS

SOMI

图8-15. SPI Slave Mode, CKPH = 1

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8.13.8.8 eUSCI (I²C Mode) Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see 图8-16)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK or ACLK,

External: UCLK,

f_eUSCI

eUSCI input clock frequency

16 MHz

Duty cycle = 50% ±10%

f_SCL

SCL clock frequency

2.2 V, 3.0 V

0

4.0

0.6

4.7

0.6

0

400 kHz

µs

f_SCL= 100 kHz

f_SCL> 100 kHz

f_SCL= 100 kHz

f_SCL> 100 kHz

t_HD,STA

Hold time (repeated) START

t_SU,STA

Setup time for a repeated START

2.2 V, 3.0 V

µs

t_HD,DAT

t_SU,DAT

Data hold time

Data setup time

2.2 V, 3.0 V

ns

100

4.0

0.6

4.7

1.3

50

f_SCL= 100 kHz

f_SCL> 100 kHz

f_SCL= 100 kHz

f_SCL> 100 kHz

UCGLITx = 0

UCGLITx = 1

UCGLITx = 2

UCGLITx = 3

UCCLTOx = 1

UCCLTOx = 2

UCCLTOx = 3

t_SU,STO

Setup time for STOP

2.2 V, 3.0 V

µs

Bus free time between a STOP and

START condition

t_BUF

us

250

25

125

ns

62.5

Pulse duration of spikes suppressed by

input filter

t_SP

2.2 V, 3.0 V

12.5

6.3

31.5

27

30

33

t_TIMEOUT

Clock low time-out

ms

8.13.8.9 eUSCI (SPI Slave Mode) Timing Diagrams

t_HD,STA

t_SU,STA

t_HD,STA

t_BUF

SDA

t_LOW

t_HIGH

t_SP

SCL

t_SU,DAT

t_SU,STO

t_HD,DAT

图8-16. I²C Mode Timing

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8.13.9 Segment LCD Controller

8.13.9.1 LCD_C Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER

CONDITIONS

MIN

NOM

MAX UNIT

LCDCPEN = 1,

0000b < VLCDx ≤1111b (charge pump

enabled, V_LCD≤3.6 V)

Supply voltage range, charge

pump enabled, V_LCD≤3.6 V

V_{CC,LCD_C,CP en,3.6}

2.2

3.6

V

LCDCPEN = 1,

0000b < VLCDx ≤1100b (charge pump

enabled, V_LCD≤3.3 V)

Supply voltage range, charge

pump enabled, V_LCD≤3.3 V

V_{CC,LCD_C,CP en,3.3}

2.0

Supply voltage range, internal

biasing, charge pump disabled

V_{CC,LCD_C,int. bias}

V_{CC,LCD_C,ext. bias}

LCDCPEN = 0, VLCDEXT = 0

2.4

3.6

V

Supply voltage range, external

biasing, charge pump disabled

Supply voltage range, external

V_{CC,LCD_C,VLCDEXT}

LCD voltage, internal or external LCDCPEN = 0, VLCDEXT = 1

biasing, charge pump disabled

2.0

2.4

3.6

V

External LCD voltage at

V_LCDCAP

LCDCAP, internal or external

biasing, charge pump disabled

LCDCPEN = 0, VLCDEXT = 1

3.6

V

Capacitor value on LCDCAP

when charge pump enabled

LCDCPEN = 1, VLCDx > 0000b (charge

pump enabled)

C_LCDCAP

f_ACLK,in

f_LCD

4.7_–20%

4.7

10_+20%

µF

ACLK input frequency range

LCD frequency range

30

0

32.768

40 kHz

f_FRAME= (1 / (2 × mux)) × f_LCDwith

mux = 1 (static) to 8

1024

Hz

f_FRAME,4mux(MAX) = (1 / (2 × 4)) ×

f_LCD(MAX) = (1 / (2 × 4)) × 1024 Hz

f_FRAME,4mux

LCD frame frequency range

128

f_LCD= 1024 Hz, all common lines

equally loaded

C_Panel

V_R33

Panel capacitance

10000

pF

V

Analog input voltage at R33

LCDCPEN = 0, VLCDEXT = 1

2.4

V_CC+ 0.2

V_R03

2/3 ×

(V_R33

V_R03

+

LCDREXT = 1, LCDEXTBIAS = 1,

LCD2B = 0

V_R23,1/3bias

Analog input voltage at R23

V_R13

V_R33

V_R23

V_R33

V

–

)

V_R03

+

1/3 ×

(V_R33

V_R03

Analog input voltage at R13 with LCDREXT = 1, LCDEXTBIAS = 1,

1/3 biasing LCD2B = 0

V_R13,1/3bias

V_R03

–

)

V_R03

+

1/2 ×

(V_R33

V_R03

Analog input voltage at R13 with LCDREXT = 1, LCDEXTBIAS = 1,

V_R13,1/2bias

V_R03

1/2 biasing

LCD2B = 1

–

)

V_R03

_LCD–V_R03

V_LCDREF

Analog input voltage at R03

R0EXT = 1

V_SS

2.4

V

Voltage difference between V_LCD

and R03

LCDCPEN = 0, R0EXT = 1

V_CC+ 0.2

1.2

V

External LCD reference voltage

applied at LCDREF

VLCDREFx = 01

0.8

1.0

V

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8.13.9.2 LCD_C Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VLCDx = 0000, VLCDEXT = 0

LCDCPEN = 1, VLCDx = 0001b

LCDCPEN = 1, VLCDx = 0010b

LCDCPEN = 1, VLCDx = 0011b

LCDCPEN = 1, VLCDx = 0100b

LCDCPEN = 1, VLCDx = 0101b

LCDCPEN = 1, VLCDx = 0110b

LCDCPEN = 1, VLCDx = 0111b

LCDCPEN = 1, VLCDx = 1000b

LCDCPEN = 1, VLCDx = 1001b

LCDCPEN = 1, VLCDx = 1010b

LCDCPEN = 1, VLCDx = 1011b

LCDCPEN = 1, VLCDx = 1100b

LCDCPEN = 1, VLCDx = 1101b

LCDCPEN = 1, VLCDx = 1110b

LCDCPEN = 1, VLCDx = 1111b

V_CC

MIN

TYP

V_CC

MAX UNIT

V_LCD,0

V_LCD,1

V_LCD,2

V_LCD,3

V_LCD,4

V_LCD,5

V_LCD,6

V_LCD,7

V_LCD,8

V_LCD,9

V_LCD,10

V_LCD,11

V_LCD,12

V_LCD,13

V_LCD,14

V_LCD,15

2.4 V to 3.6 V

2 V to 3.6 V

2.2 V to 3.6 V

2 V to 3.6 V

2.49

2.60

2.66

2.72

2.78

2.84

2.90

2.96

3.02

3.08

3.14

3.20

3.26

3.32

3.38

3.44

2.72

LCD voltage

V

3.32

3.6

LCD voltage with external

reference of 0.8 V

LCDCPEN = 1, VLCDx = 0111b,

VLCDREFx = 01b, V_LCDREF= 0.8 V

2.96 ×

0.8 V

V_LCD,7,0.8

V_LCD,7,1.0

V_LCD,7,1.2

ΔV_LCD

V

LCD voltage with external

reference of 1.0 V

LCDCPEN = 1, VLCDx = 0111b,

VLCDREFx = 01b, V_LCDREF= 1.0 V

2 V to 3.6 V

2.96 ×

1.0 V

V

LCD voltage with external

reference of 1.2 V

LCDCPEN = 1, VLCDx = 0111b,

VLCDREFx = 01b, V_LCDREF= 1.2 V

2.2 V to 3.6 V

2.96 ×

1.2 V

Voltage difference between

consecutive VLCDx settings

ΔV_LCD= V_LCD,x–V_LCD,x–1

with x = 0010b to 1111b

40

60

600

100

80 mV

LCDCPEN = 1, VLCDx = 1111b

external, with decoupling capacitor on

DVCC supply ≥1 µF

Peak supply currents due to

charge pump activities

I_CC,Peak,CP

2.2 V

µA

Time to charge C_LCDwhen

discharged

C_LCD= 4.7 µF, LCDCPEN = 0→1,

VLCDx = 1111b

t_LCD,CP,on

I_CP,Load

R_LCD,Seg

R_LCD,COM

2.2 V

500

ms

µA

kΩ

Maximum charge pump load

current

LCDCPEN = 1, VLCDx = 1111b

LCDCPEN = 0, I_LOAD= ±10 µA

50

LCD driver output impedance,

segment lines

10

LCD driver output impedance,

common lines

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8.13.10 ADC12_B

8.13.10.1 12-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

3.0 V

2.2 V

MIN

NOM

MAX UNIT

V_(Ax)

Analog input voltage range⁽¹⁾

All ADC12 analog input pins Ax

0

AVCC

V

f_ADC12CLK= MODCLK, ADC12ON = 1,

ADC12PWRMD = 0, ADC12DIF = 0,

REFON = 0, ADC12SHTx = 0,

ADC12DIV = 0

145

199

I_{(ADC12_B)}

Operating supply current into

µA

single-ended

mode

AVCC and DVCC terminals^{(2) (3)}

f_ADC12CLK= MODCLK, ADC12ON = 1,

ADC12PWRMD = 0, ADC12DIF = 0,

REFON = 0, ADC12SHTx = 0,

ADC12DIV = 0

140

190

f_ADC12CLK= MODCLK, ADC12ON = 1,

ADC12PWRMD = 0, ADC12DIF = 1,

3.0 V

2.2 V

175

170

245

230

I_{(ADC12_B)}

Operating supply current into

µA

differential

mode

AVCC and DVCC terminals^{(2) (3)}REFON = 0, ADC12SHTx= 0,

ADC12DIV = 0

f_ADC12CLK= MODCLK/4, ADC12ON = 1,

ADC12PWRMD = 1, ADC12DIF = 0,

REFON = 0, ADC12SHTx = 0,

ADC12DIV = 0

3.0 V

2.2 V

85

83

125

120

I_{(ADC12_B)}

Operating supply current into

single-ended

low-power

mode

AVCC and DVCC terminals^{(2) (3)}

f_ADC12CLK= MODCLK/4, ADC12ON = 1,

ADC12PWRMD = 1, ADC12DIF = 0,

REFON = 0, ADC12SHTx = 0,

ADC12DIV = 0

I_{(ADC12_B)}

f_ADC12CLK= MODCLK/4, ADC12ON = 1,

ADC12PWRMD = 1, ADC12DIF = 1,

3.0 V

2.2 V

110

109

165

160

Operating supply current into

differential

low-power

mode

AVCC and DVCC terminals^{(2) (3)}REFON = 0, ADC12SHTx= 0,

ADC12DIV = 0

Only one terminal Ax can be selected at

one time

C_I

R_I

Input capacitance

2.2 V

10

15

pF

>2 V

<2 V

0.5

1

4

Input MUX ON resistance

0 V ≤V_(Ax)≤AV_CC

kΩ

10

(1) The analog input voltage range must be within the selected reference voltage range V_R+to V_R–for valid conversion results.

(2) The internal reference supply current is not included in current consumption parameter I(ADC12_B).

(3) Approximately 60% (typical) of the total current into the AVCC and DVCC terminal is from AVCC.

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8.13.10.2 12-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

For specified performance of ADC12 linearity parameters with

ADC12PWRMD = 0,

specified performance If ADC12PWRMD = 1, the maximum is 1/4 of the value shown

here

Frequency for

f_ADC12CLK

0.45

5.4 MHz

Frequency for

f_ADC12CLK

f_ADC12OSC

Linearity parameters have reduced performance

reduced performance

32.768

4.8

kHz

Internal oscillator⁽³⁾

ADC12DIV = 0, f_ADC12CLK= f_ADC12OSCfrom MODCLK

4

5.4 MHz

REFON = 0, Internal oscillator, f_ADC12CLK= f_ADC12OSCfrom

MODCLK, ADC12WINC = 0

2.6

3.5

µs

t_CONVERT

Conversion time

External f_ADC12CLKfrom ACLK, MCLK, or SMCLK,

ADC12SSEL ≠0

See ⁽²⁾

Turnon settling time of

the ADC

t_ADC12ON

See ⁽¹⁾

100

ns

Time ADC must be off

before can be turned

on again

Note: t_ADC12OFFmust be met to make sure that t_ADC12ONtime

holds

t_ADC12OFF

100

1

All pulse sample mode

(ADC12SHP = 1) and extended

sample mode (ADC12SHP = 0) with

buffered reference

(ADC12VRSEL = 0x1, 0x3, 0x5,

0x7, 0x9, 0xB, 0xD, 0xF)

µs

R_S= 400 Ω, R_I= 4 kΩ,

t_Sample

Sampling time

C_I= 15 pF, C_pext= 8 pF⁽⁴⁾

Extended sample mode

(ADC12SHP = 0) with unbuffered

reference (ADC12VRSEL= 0x0,

0x2, 0x4, 0x6, 0xC, 0xE)

See ⁽⁵⁾

(1) The condition is that the error in a conversion started after t_ADC12ONis less than ±0.5 LSB. The reference and input signal are already

settled.

(2) 14 × 1 / f_ADC12CLK. If ADC12WINC = 1 then 15 × 1 / f_ADC12CLK

.

(3) The ADC12OSC is sourced directly from MODOSC in the UCS.

(4) Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB: t_sample= ln(2ⁿ⁺²) × (R_S+ R_I) × (C_I+ C_pext), where n = ADC

resolution = 12, R_S= external source resistance, C_pext= external parasitic capacitance.

(5) 6 × 1 / f_ADC12CLK

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8.13.10.3 12-Bit ADC, Linearity Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

With external voltage reference

(ADC12VRSEL = 0x2,0x3, 0x4, 0x14, or 0x15),

1.2 V ≤V_R+–V_R–≤AV_CC

Integral linearity error (INL) for

differential input

±1.8

LSB

E_I

With external voltage reference

(ADC12VRSEL = 0x2,0x3, 0x4, 0x14, or 0x15),

1.2 V ≤V_R+–V_R–≤AV_CC

Integral linearity error (INL) for

single ended inputs

±2.2

+1.0

±1.5

LSB

mV

With external voltage reference

(ADC12VRSEL = 0x2, 0x3, 0x4, 0x14, or 0x15)

E_D

E_O

Differential linearity error (DNL)

Offset error^{(1) (2)}

–0.99

ADC12VRSEL = 0x1 without TLV calibration,

TLV calibration data can be used to improve the

parameter⁽³⁾

±0.5

With internal voltage reference V_REF= 2.5 V

(ADC12VRSEL = 0x1, 0x7, 0x9, 0xB, or 0xD)

±0.2%

±1.7%

±2.5%

With internal voltage reference V_REF= 1.2 V

(ADC12VRSEL = 0x1, 0x7, 0x9, 0xB, or 0xD)

E_G

Gain error

With external voltage reference without internal

buffer (ADC12VRSEL = 0x2 or 0x4) without TLV

calibration, V_R+= 2.5 V, V_R–= AVSS

±1

±3

LSB

With external voltage reference with internal buffer

(ADC12VRSEL = 0x3), V_R+= 2.5 V, V_R–= AVSS

±2

±0.2%

±27

±1.8%

±2.6%

With internal voltage reference V_REF= 2.5 V

(ADC12VRSEL = 0x1, 0x7, 0x9, 0xB, or 0xD)

With internal voltage reference V_REF= 1.2 V

(ADC12VRSEL = 0x1, 0x7, 0x9, 0xB, or 0xD)

E_T

Total unadjusted error

With external voltage reference without internal

buffer (ADC12VRSEL = 0x2 or 0x4) without TLV

calibration, V_R+= 2.5 V, V_R–= AVSS

±1

±5

LSB

With external voltage reference with internal buffer

(ADC12VRSEL = 0x3), V_R+= 2.5 V, V_R–= AVSS

±28

(1) Offset is measured as the input voltage (at which ADC output transitions from 0 to 1) minus 0.5 LSB.

(2) Offset increases as I_Rdrop increases when V_R–is AVSS.

(3) For details, see the Device Descriptor Table section in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's

Guide.

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8.13.10.4 12-Bit ADC, Dynamic Performance With External Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Resolution Number of no missing code output-code bits

12

bits

Signal-to-noise with differential inputs

SNR

V_R+= 2.5 V, V_R–= AV_SS

71

70

dB

Signal-to-noise with single-ended inputs

V_R+= 2.5 V, V_R–= AV_SS

Effective number of bits with differential

inputs⁽¹⁾

11.4

11.1

Effective number of bits with single-ended

V_R+= 2.5 V, V_R–= AV_SS

ENOB

inputs⁽¹⁾

bits

Reduced performance with f_ADC12CLK

from ACLK LFXT 32.768 kHz,

V_R+= 2.5 V, V_R–= AV_SS

Effective number of bits with 32.768-kHz

clock (reduced performance)⁽¹⁾

10.9

(1) ENOB = (SINAD –1.76) / 6.02

8.13.10.5 12-Bit ADC, Dynamic Performance With Internal Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Resolution Number of no missing code output-code bits

12

bits

Signal-to-noise with differential inputs

SNR

V_R+= 2.5 V, V_R–= AV_SS

70

69

dB

Signal-to-noise with single-ended inputs

V_R+= 2.5 V, V_R–= AV_SS

Effective number of bits with differential

inputs⁽¹⁾

11.4

11.0

Effective number of bits with single-ended

V_R+= 2.5 V, V_R–= AV_SS

ENOB

inputs⁽¹⁾

bits

Reduced performance with f_ADC12CLK

from ACLK LFXT 32.768 kHz,

V_R+= 2.5 V, V_R–= AV_SS

Effective number of bits with 32.768-kHz

clock (reduced performance)⁽¹⁾

10.9

(1) ENOB = (SINAD –1.76) / 6.02

8.13.10.6 12-Bit ADC, Temperature Sensor and Built-In V_1/2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Temperature sensor voltage^{(1) (2)}

See ⁽²⁾

TEST CONDITIONS

MIN

TYP MAX UNIT

ADC12ON = 1, ADC12TCMAP = 1,

T_A= 0°C

V_SENSOR

700

2.5

mV

mV/°C

µs

TC_SENSOR

t_{SENSOR(sample)}

ADC12ON = 1, ADC12TCMAP = 1

Sample time required if ADCTCMAP = 1 and ADC12ON = 1, ADC12TCMAP = 1,

channel (MAX –1) is selected⁽³⁾

30

Error of conversion result ≤1 LSB

AVCC voltage divider for ADC12BATMAP = 1

on MAX input channel

V_1/2

ADC12ON = 1, ADC12BATMAP = 1

47.5%

50% 52.5%

I_V1/2

Current for battery monitor during sample time ADC12ON = 1, ADC12BATMAP = 1

38

72

µA

µs

Sample time required if ADC12BATMAP = 1

ADC12ON = 1, ADC12BATMAP = 1

and channel MAX is selected⁽⁴⁾

t_{V1/2 (sample)}

1.7

(1) The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in

temperature sensor.

(2) The device descriptor structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference voltage

levels. The sensor voltage can be computed as V_SENSE= TC_SENSOR× (Temperature, °C) + V_SENSOR, where TC_SENSORand V_SENSOR

can be computed from the calibration values for higher accuracy.

(3) The typical equivalent impedance of the sensor is 250 kΩ. The sample time required includes the sensor-on time, t_SENSOR(on)

.

(4) The on-time t_V1/2(on)is included in the sampling time t_V1/2(sample); no additional on time is needed.

62

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8.13.10.7 12-Bit ADC, External Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Positive external reference voltage input

VeREF+ or VeREF- based on

ADC12VRSEL bit

V_R+

V_R+> V_R–

1.2

AV_CC

V

Negative external reference voltage input

VeREF+ or VeREF- based on

ADC12VRSEL bit

V_R–

V_R+> V_R–

0

1.2

AV_CC

±10

V

V_R+–

V_R–

Differential external reference voltage input V_R+> V_R–

1.2

1.2 V ≤V_eREF+≤V_AVCC, V_eREF-= 0 V

f_ADC12CLK= 5 MHz, ADC12SHTx = 1h,

ADC12DIF = 0, ADC12PWRMD = 0

µA

I_VeREF+

I_VeREF-

,

Static input current singled-ended input

mode

1.2 V ≤V_eREF+≤V_AVCC, V_eREF-= 0 V

f_ADC12CLK= 5 MHz, ADC12SHTx = 8h,

ADC12DIF = 0, ADC12PWRMD = 01

±2.5

±20

±5

µA

1.2 V ≤V_eREF+≤V_AVCC, V_eREF-= 0 V

f_ADC12CLK= 5 MHz, ADC12SHTx = 1h,

ADC12DIF = 1, ADC12PWRMD = 0

I_VeREF+

I_VeREF-

Static input current differential input mode

1.2 V ≤V_eREF+≤V_AVCC, V_eREF-= 0 V

f_ADC12CLK= 5 MHz, ADC12SHTx = 8h,

ADC12DIF = 1, ADC12PWRMD = 1

I_VeREF+

Peak input current with single-ended input

Peak input current with differential input

1.5

3

mA

0 V ≤V_eREF+≤V_AVCC, ADC12DIF = 0

0 V ≤V_eREF+≤V_AVCC, ADC12DIF = 1

Capacitance at VeREF+ or VeREF-

terminal

C_VeREF+/-

See ⁽²⁾

10

µF

(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance (C_I) is

also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the

recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.

(2) Connect two decoupling capacitors, 10 µF and 470 nF, to VeREF to decouple the dynamic current required for an external reference

source if it is used for the ADC12_B. Also see the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.

8.13.10.8 Temperature Sensor Typical Characteristics

950

900

850

800

750

700

650

600

550

500

–40

–20

0

20

40

60

80

Ambient Temperature (°C)

图8-17. Typical Temperature Sensor Voltage

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8.13.11 Reference

8.13.11.1 REF, Built-In Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

2.5 ±1.5%

2.0 ±1.5%

1.2 ±1.8%

MAX UNIT

REFVSEL = {2} for 2.5 V, REFON = 1

REFVSEL = {1} for 2.0 V, REFON = 1

REFVSEL = {0} for 1.2 V, REFON = 1

From 0.1 Hz to 10 Hz, REFVSEL = {0}

2.7 V

2.2 V

1.8 V

Positive built-in reference

voltage output

V_REF+

V

Noise

RMS noise at VREF ⁽³⁾

30

130

+16

µV

VREF ADC BUF_INT buffer T_A= 25°C, ADC on, REFVSEL = {0},

offset⁽⁵⁾

REFON = 1, REFOUT = 0

V_{OS_BUF_INT}

mV

–16

VREF ADC BUF_EXT buffer T_A= 25°C, REFVSEL = {0} , REFOUT = 1,

V_{OS_BUF_EXT}

AV_CC(min)

I_REF+

+16

mV

V

offset⁽⁴⁾

REFON = 1 or ADC on

REFVSEL = {0} for 1.2 V

REFVSEL = {1} for 2.0 V

REFVSEL = {2} for 2.5 V

1.8

2.2

2.7

AVCC minimum voltage,

Positive built-in reference

active

Operating supply current

into AVCC terminal⁽¹⁾

REFON = 1

3 V

19

26

µA

ADC ON, REFOUT = 0,

REFVSEL = {0, 1, or 2},

ADC12PWRMD = 0

247

400

ADC ON, REFOUT = 1,

REFVSEL = {0, 1, 2}, ADC12PWRMD = 0

3 V

1053

153

1820

240

Operating supply current

into AVCC terminal⁽¹⁾

I_{REF+_ADC_BUF}

ADC ON, REFOUT = 0,

REFVSEL = {0, 1, 2}, ADC12PWRMD = 1

µA

ADC ON, REFOUT = 1,

REFVSEL = {0, 1, 2}, ADC12PWRMD = 1

581

1030

1890

ADC OFF, REFON = 1, REFOUT = 1,

REFVSEL = {0, 1, 2}

1105

REFVSEL = {0, 1, 2}, AV_CC= AV_CC(min)for

each reference level,

REFON = REFOUT = 1

VREF maximum load

current, VREF+ terminal

I_O(VREF+)

+10

–1000

REFVSEL = {0, 1, 2},

ΔV_out

/

Load-current regulation,

VREF+ terminal

I_O(VREF+)= +10 µA or –1000 µA,

AV_CC= AV_CC(min)for each reference level,

REFON = REFOUT = 1

1500 µV/mA

ΔI_o(VREF+)

C_VREF+/-

TC_REF+

Capacitance at VREF+ and

VREF- terminals

REFON = REFOUT = 1

0

100

pF

REFVSEL = {0, 1, 2},

REFON = REFOUT = 1,

T_A= –40°C to 85°C⁽⁶⁾

Temperature coefficient of

built-in reference

24

50 ppm/K

AV_CC= AV_{CC (min)}to AV_CC(max)

T_A= 25°C, REFVSEL = {0, 1, 2},

REFON = REFOUT = 1

,

Power supply rejection ratio

(DC)

PSRR_DC

100

400 µV/V

mV/V

Power supply rejection ratio

(AC)

PSRR_AC

t_SETTLE

dAV_CC= 0.1 V at 1 kHz

3.0

40

AV_CC= AV_{CC (min)}to AV_CC(max)

REFVSEL = {0, 1, 2}, REFON = 0 →1

,

Settling time of reference

voltage⁽²⁾

80

2

µs

Settling time of ADC

AV_CC= AV_{CC (min)}to AV_CC(max)

REFVSEL = {0, 1, 2}, REFON = 1

,

T_{buf_settle}

0.4

reference voltage buffer⁽²⁾

(1) The internal reference current is supplied through the AVCC terminal.

(2) The condition is that the error in a conversion started after t_REFONis less than ±0.5 LSB.

(3) Internal reference noise affects ADC performance when ADC uses the internal reference. See Designing With the MSP430FR59xx

and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external

reference.

(4) Buffer offset affects ADC gain error and thus total unadjusted error.

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(5) Buffer offset affects ADC gain error and thus total unadjusted error.

(6) Calculated using the box method: (MAX(–40°C to 85°C) –MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C –(–40°C)).

8.13.12 Comparator

8.13.12.1 Comparator_E

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

CEPWRMD = 00, CEON = 1,

CERSx = 00 (fast)

12

16

CEPWRMD = 01, CEON = 1,

CERSx = 00 (medium)

Comparator operating

supply current into AVCC,

excludes reference resistor

ladder

10

0.1

0.3

14

µA

0.3

I_{AVCC_COMP}

2.2 V, 3.0 V

CEPWRMD = 10, CEON = 1,

CERSx = 00 (slow), T_A= 30°C

CEPWRMD = 10, CEON = 1,

CERSx = 00 (slow), T_A= 85°C

1.3

CEREFLx = 01, CERSx = 10,

REFON = 0, CEON = 1,

CEREFACC = 0

31

16

38

µA

19

Quiescent current of

resistor ladder into AVCC,

including REF module

current

I_{AVCC_COMP_REF}

2.2 V, 3.0 V

CEREFLx = 01, CERSx = 10,

REFON = 0, CEON = 1,

CEREFACC = 1

CERSx = 11, CEREFLx = 01,

CEREFACC = 0

1.8 V

2.2 V

2.7 V

1.8 V

2.2 V

2.7 V

1.152

1.92

2.40

1.10

1.90

2.35

1.2

2.0

2.5

1.2

2.0

2.5

1.248

2.08

CERSx = 11, CEREFLx = 10,

CEREFACC = 0

CERSx = 11, CEREFLx = 11,

CEREFACC = 0

2.60

V

V_REF

Reference voltage level

CERSx = 11, CEREFLx = 01,

CEREFACC = 1

1.245

CERSx = 11, CEREFLx = 10,

CEREFACC = 1

2.08

2.60

CERSx = 11, CEREFLx = 11,

CEREFACC = 1

V_IC

Common-mode input range

Input offset voltage

0

–16

–12

–37

V

V_CC–1

CEPWRMD = 00

CEPWRMD = 01

CEPWRMD = 10

16

12

37

V_OFFSET

mV

CEPWRMD = 00 or

CEPWRMD = 01

10

C_IN

Input capacitance

pF

CEPWRMD = 10

ON (switch closed)

OFF (switch open)

10

1

3

kΩ

R_SIN

Series input resistance

50

MΩ

CEPWRMD = 00, CEF = 0,

Overdrive ≥20 mV

193

230

5

330

400

15

ns

µs

CEPWRMD = 01, CEF = 0,

Overdrive ≥20 mV

Propagation delay,

response time

t_PD

CEPWRMD = 10, CEF = 0,

Overdrive ≥20 mV

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MAX UNIT

8.13.12.1 Comparator_E (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

CEPWRMD = 00 or 01, CEF = 1,

Overdrive ≥20 mV, CEFDLY = 00

700

1000

1.9

ns

CEPWRMD = 00 or 01, CEF = 1,

Overdrive ≥20 mV, CEFDLY = 01

1.0

2.0

4.0

Propagation delay with

filter active

t_PD,filter

CEPWRMD = 00 or 01, CEF = 1,

Overdrive ≥20 mV, CEFDLY = 10

3.7

µs

CEPWRMD = 00 or 01, CEF = 1,

Overdrive ≥20 mV, CEFDLY = 11

7.7

CEON = 0 →1, VIN+,

VIN- from pins,

Overdrive ≥20 mV,

CEPWRMD = 00

0.9

15

1.5

65

CEON = 0 →1, VIN+,

VIN- from pins,

Overdrive ≥20 mV,

CEPWRMD = 01

t_{EN_CMP}

Comparator enable time

µs

CEON = 0 →1,

VIN+, VIN- from pins,

Overdrive ≥20 mV,

CEPWRMD = 10

CEON = 0 →1, CEREFLX = 10,

CERSx = 10 or 11,

CEREF0 = CEREF1 = 0x0F,

REFON = 0

Comparator and reference

ladder and reference

voltage enable time

t_{EN_CMP_VREF}

120

220

µs

V

CEON = 0 →1, CEREFLX = 10,

CERSx = 10, REFON = 1,

CEREF0 = CEREF1 = 0x0F

Comparator and reference

ladder enable time

t_{EN_CMP_RL}

10

30

VIN ×

Reference voltage for a

given tap

VIN = reference into resistor ladder,

n = 0 to 31

V_{CE_REF}

(n + 0.5) (n + 1) / (n + 1.5) /

/ 32 32 32

8.13.13 FRAM

8.13.13.1 FRAM Memory

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

T_J

MIN

10¹⁵

100

40

TYP

MAX UNIT

Read and write endurance

cycles

25°C

70°C

85°C

t_RetentionData retention duration

years

10

I_WRITE

I_ERASE

t_WRITE

Current to write into FRAM⁽¹⁾

Erase current⁽²⁾

I_READ

N/A⁽³⁾

nA

ns

Write time⁽⁴⁾

t_READ

NWAITSx = 0

NWAITSx = 1

1 / f_SYSTEM

2 / f_SYSTEM

t_READ

Read time⁽⁵⁾

(1) Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read

current I_READis included in the active mode current consumption, I_AM,FRAM

(2) FRAM does not require a special erase sequence.

(3) N/A = Not applicable

.

(4) Writing into FRAM is as fast as reading.

(5) The maximum read (and write) speed is specified by f_SYSTEMusing the appropriate wait state settings (NWAITSx).

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8.13.14 USS

8.13.14.1 USS Recommended Operating Conditions

PARAMETER

TEST CONDITIONS

MIN

2.2

TYP

MAX UNIT

PV_CC

Analog supply voltage at PVCC pins for LDO operation

Analog supply voltage at PVCC pins for USS operation

3.6

V

2.2

8.13.14.2 USS LDO

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_CC_ldo

V_uss

Analog supply voltage at PVCC pins

USS voltage

2.2

3.6

V

1.52

1.6

0

1.65

0 ≤I_LOAD≤I_LOAD,MAX

LBHDEL = 0

LBHDEL = 1

LBHDEL = 2

LBHDEL = 3

100

200

300

T_holdoff

Hold off delay on power up

µs

T_timeout

Time-out on transition OFF to READY

160 +

T_holdoff

8.13.14.3 USSXTAL

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

N_{phase_osc}Integrated phase noise

f_osc= 4 MHz or 8 MHz, range = 10 kHz to 4 MHz

dBc

–74

FRQ_XTAL

DC_osc

Resonator frequency

Duty cycle

4

8

MHz

%

35

65

f_osc= 4 MHz or 8 MHz, C_L= 18 pF, C_S= 4 pF, fully

settled, ceramic resonator

180

240

I_osc

OSC supply current

Oscillation allowance

Startup time (gate)

µA

f_osc= 4 MHz or 8 MHz, C_L= 12 pF (4 MHz) or

16 pF(8 MHz), C_S= 7 pF, fully settled, crystal

resonator

f_osc= 4 MHz, C_L= 18 pF, C_S= 4 pF, ceramic

resonator

1500

1000

500

f_osc= 4 MHz, C_L= 12 pF, C_S= 7 pF, crystal

resonator

A_osc

Ω

f_osc= 8 MHz, C_L= 18 pF, C_S= 4 pF, ceramic

resonator

f_osc= 8 MHz, C_L= 16 pF, C_S= 7 pF, crystal

resonator

350

f_osc= 4 MHz, crystal resonator

f_osc= 8 MHz, crystal resonator

f_osc= 4 MHz, ceramic resonator

f_osc= 8 MHz, ceramic resonator

2.8

1

4.6

1.9

T_{start_osc}

ms

0.14

0.08

0.17

0.12

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MAX UNIT

8.13.14.4 USS HSPLL

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

PLL_CLK_in

Input clock to HSPLL

4

8

MHz

PLL_CLK_outOutput clock from HSPLL

68

80 MHz

Reference clock = PLL_CLK_in,

Sequence: Set USS.CTL.USSPWRUP bit = 1, then

measure the time between PSQ_PLLUP (internal

control signal) is set to 1 and

LOCK_pwr

Lock time from PLL power up

64 cycles

HSPLL.CTL.PLL_LOCK is set to 1

8.13.14.5 USS SDHS

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SDHS power domain

supply voltage

V_sdhs

V_sdhs= V_uss

1.52

1.6

1.65

V

Operating supply current Includes PLL, PGA, SDHS, and DTC,

I_{sdhs_product}

F_m

5.2

1.5

mA

into AVCC and DVCC

modulator clock = 80 MHz, output data rate = 8 Msps

Modulator clock⁽¹⁾

68

80 MHz

MHz

Modulator clock = 80 MHz, modulator only (no filter is

enabled)

BW_mod

Frequency at -3dB SNR

Bandwidth from 200 kHz

to 1.5 MHz, PGA gain: a Input signal level = 1000 mVpp,

gain from the PGA gain PVCC = 3.0 V, F_m= 80 MHz,

58.5

57.5

54.5

49

62.5

table for the maximum

SNR

OSR = 20

Bandwidth from 200 kHz

to 1.5 MHz, PGA gain: a Input signal level = 760 mVpp,

gain from the PGA gain PVCC = 2.5 V, F_m= 80 MHz,

62

57

53

43

table for the maximum

SNR

OSR = 20

Bandwidth from 200 kHz

to 1.5 MHz, PGA gain: a Input signal level = 200 mVpp,

gain from the PGA gain PVCC = 2.5 V, F_m= 80 MHz,

SNR

Signal-to-noise ratio⁽²⁾

dB

table for the maximum

SNR

OSR = 20

Bandwidth from 200 kHz

to 1.5 MHz, PGA gain: a Input signal level = 100 mVpp,

gain from the PGA gain PVCC = 2.5 V, F_m= 80 MHz,

table for the maximum

SNR

OSR = 20

Bandwidth from 200 kHz

to 1.5 MHz, PGA gain: a Input signal level = 30 mVpp,

gain from the PGA gain PVCC = 2.5 V, F_m= 80 MHz,

38.5

table for the maximum

SNR

OSR = 20

TM2 - TM1, AUTOSSDIS = 0, 1% of settled DC level

TM2 - TM1, AUTOSSDIS = 1, 1% of settled DC level

40

µs

40

SDHS settling time (PGA

+ Modulator)

T_{MOD_Settle}

DROUT_sdhsOutput data rate

8

Msps

(1) Informative parameter, not characterized

(2) SNR as specified, SINAD and THD not specified over complete signal chain

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8.13.14.6 USS PHY Output Stage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

PHY supply voltage

Output impedance of CH0OUT and CH1OUT for

TEST CONDITIONS

MIN

TYP

MAX UNIT

PVCC

R_DSonT

PVCC = V_CC, PVSS = V_SS

2.2

3.6

V

3

PVCC ≥ 2.5 V

Ω

high and low side (trimmed at 3-V PV_DD

)

Termination impedance of CH0OUT and

CH1OUT towards PVSS (trimmed)

R_Term

DrvM

Ω

High side to low side drive mismatch (trimmed)

5%

12.5%

PVCC ≥ 2.5 V

PVCC = V_CC(2.5 V to 3.6 V)

PVCC = V_CC

TermM Termination to drive mismatch (trimmed)

f_MAX

Maximum output frequency

4.5

22

MHz

µF

C_SUPP

R_SUPP

Supply buffering capacitance (low ESR type)

Series resistance to C_SUPP

100

22

PVCC = V_CC

Ω

8.13.14.7 USS PHY Input Stage, Multiplexer

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

1.8

PVSS

–0.3

V_IN

Input voltage on CH0IN or CH1IN

PVCC = V_CC, PVSS = V_SS

V

8.13.14.8 USS_PGA

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Supply voltage

Gain⁽¹⁾

TEST CONDITIONS

MIN

TYP

MAX UNIT

PV_cc

G_N

2.2

3.6

V

30.8

dB

–6.5

30

Vinr1

Vinr2

G_tol

Input range

Gain tolerance

800 mVpp

2.2 V ≤PVCC

2.5 V ≤ PVCC

30

1000 mVpp

Full PGA gain range, V_OUT= 600 mV

1.5

dB

–1.5

Gain drift over

temperature

GTdrift

0.0019

dB/℃

GVdrift

T_SET

Gain drift over voltage

Gain settling time

Full PGA gain range, V_OUT= 600 mV

Gain setting: from 0 dB to 6 dB, to ±5%

0.15

0.65

dB/V

µs

1.4

DC offset (PGA and

SDHS)

DC_offset

DC_drift

Full PGA gain range, measured at SDHS output

5.5

4.7

mV

DC offset drift (PGA and

SDHS)

µV/℃

PGA gain = 0 dB

-41

-37

-19

V_CC= 3 V + 50 mVpp × sin (2π× f_C)

where f_C= 1 MHz, V_IN= ground,

PSRR_AC = 20log(V_OUT/ 50 mV)

AC power supply

rejection ratio

PSRR_AC

PGA gain = 10 dB

PGA gain = 30 dB

dB

(1) See PGA Gain Table in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.

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8.13.14.9 USS Bias Voltage Generator

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PVCC = V_CC(2.2 V to 3.6 V), EXCBIAS = 0

PVCC = V_CC(2.2 V to 3.6 V), EXCBIAS = 1

PVCC = V_CC(2.2 V to 3.6 V), EXCBIAS = 2

PVCC = V_CC(2.2 V to 3.6 V), EXCBIAS = 3

PVCC = V_CC(2.2 V to 3.6 V), BIMP = 0

PVCC = V_CC(2.2 V to 3.6 V), BIMP = 1

PVCC = V_CC(2.2 V to 3.6 V), BIMP = 2

PVCC = V_CC(2.2 V to 3.6 V), BIMP = 3

200

300

Excitation bias voltage

(coupling capacitors)

V_{exc_bias}

mV

400

600

450

850

Impedance of excitation bias

generator

R_VBE

Ω

µs

1450

2900

PVCC = V_CC(2.2 V to 3.6 V) to 0.1% end value

R_ET= 200 Ω, C_K+ C_0P= 1 nF, BIMP = 2

T_SBE

Excitation bias settling time

20

PVCC = V_CC(2.2 V to 3.6 V), PGABIAS = 0

PVCC = V_CC(2.2 V to 3.6 V), PGABIAS = 1

PVCC = V_CC(2.2 V to 3.6 V), PGABIAS = 2

PVCC = V_CC(2.2 V to 3.6 V), PGABIAS = 3

PVCC = V_CC(2.2 V to 3.6 V), BIMP = 0

PVCC = V_CC(2.2 V to 3.6 V), BIMP = 1

PVCC = V_CC(2.2 V to 3.6 V), BIMP = 2

PVCC = V_CC(2.2 V to 3.6 V), BIMP = 3

750

800

PGA bias voltage (coupling

caps)

V_{pga_bias}

mV

900

950

500

900

Impedance of acquisition bias

generator

R_VBA

Ω

1500

2950

PVCC = V_CC(2.2 V to 3.6 V)to 0.1% end value

R_ET= 200 Ω, C_K+ C_0P= 1 nF, BIMP = 2

T_SBA

Acquisition bias settling time

22

µs

Impedance of bias switches

on XPB0/1 terminals on top of

R_VBA

PVCC = V_CC(2.2 V to 3.6 V), PGABIAS = 0;1;2;3 ,

BIMP = 0;1;2;3

R_VBX

1000

Ω

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8.13.15 Emulation and Debug

8.13.15.1 JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

V_CC

MIN

TYP

MAX UNIT

I_JTAG

Supply current adder when JTAG active (but not clocked)

Spy-Bi-Wire input frequency

2.2 V, 3.0 V

40

100

10

μA

MHz

μs

f_SBW

0

t_SBW,Low

Spy-Bi-Wire low clock pulse duration

0.04

15

Spy-Bi-Wire enable time (TEST high to acceptance of first clock

edge)⁽¹⁾

t_{SBW, En}

t_SBW,Rst

2.2 V, 3.0 V

110

μs

Spy-Bi-Wire return to normal operation time

TCK input frequency, 4-wire JTAG⁽²⁾

15

0

100

16

2.2 V

3.0 V

f_TCK

MHz

0

16

R_internal

f_TCLK

t_{TCLK,Low/High}

f_TCLK,FRAM

Internal pulldown resistance on TEST

2.2 V, 3.0 V

20

35

50

kΩ

TCLK/MCLK frequency during JTAG access, no FRAM access

16 MHz

(limited by f_SYSTEM

)

TCLK low or high clock pulse duration, no FRAM access

25

4

ns

MHz

ns

TCLK/MCLK frequency during JTAG access, including FRAM access

(limited by f_SYSTEMwith no FRAM wait states)

t_{TCLK,FRAM, Low/}TCLK low or high clock pulse duration, including FRAM accesses

100

High

(1) Tools that access the Spy-Bi-Wire and the BSL interfaces must wait for the t_SBW,Entime after the first transition of the TEST/SBWTCK

pin (low to high), before the second transition of the pin (high to low) during the entry sequence.

(2) f_TCKmay be restricted to meet the timing requirements of the module selected.

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9 Detailed Description

9.1 Overview

The MSP430FR604x and MSP430FR504x ultra-low-power microcontrollers feature different sets of peripherals.

The architecture, combined with seven low-power modes, is optimized to achieve extended battery life for

example in portable measurement applications. The devices features a powerful 16-bit RISC CPU, 16-bit

registers, and constant generators that contribute to maximum code efficiency.

The MSP430FR604x and MSP430FR504x MCUs feature an ultrasonic sensing solution (USS) module, a low-

energy accelerator (LEA), up to six 16-bit timers, up to six eUSCIs that support UART, SPI, and I²C, a

comparator, a hardware multiplier, an AES accelerator, a 6-channel DMA, an RTC module with alarm

capabilities, up to 57 I/O pins, and a high-performance 12-bit ADC. The MSP430FR604x MCUs also include an

LCD controller module with contrast control for displays with up to 248 segments.

9.2 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations

other than program-flow instructions are performed as register operations in conjunction with seven addressing

modes for the source operand and four addressing modes for the destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register

operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant

generator, respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be managed with all

instructions.

The instruction set consists of the original 51 instructions with three formats and seven address modes and

additional instructions for the expanded address range. Each instruction can operate on word and byte data.

9.3 Ultrasonic Sensing Solution (USS_A)

The USS_A module provides a high-precision ultrasonic-sensing solution. The USS_A module is a sophisticated

system that consists of six submodules:

• UUPS (universal USS power supply)

• HSPLL (high-speed PLL) with oscillator

• ASQ (acquisition sequencer)

• PHY (physical interface)

• PPG_A (programmable pulse generator "A") with low output impedance driver

• PGA (programmable gain amplifier)

• SDHS (sigma-delta high-speed ADC) with DTC (data transfer controller)

The submodules have different roles, and together the enable high-precision data acquisition in ultrasonic

applications. See the dedicated chapter for each submodule in the MSP430FR58xx, MSP430FR59xx, and

MSP430FR6xx Family User's Guide.

The USS module performs complete measurement sequence without CPU involvement to achieve ultra-low

power consumption for ultrasonic metrology. 节 7.1 shows the USS subsystem block diagram. The USS module

has dedicated I/O pins without secondary functions. See the Ultrasonic Sensing Solution (USS) chapter in the

MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for details.

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USS_A Module

USSXT

USSXTOUT

USSXTIN

USSXT_BOUT

SAPH_A

OSC

CH0_OUT

CH1_OUT

PPG_A

PHY

ASQ

PLL_CLK

PVSS

PLL

HSPLL

PVCC

V_OUT

UUPS

PVSS

SDHS

CH1_IN

CH0_IN

RAM

(shared with LEA)

PGA

MOD Filter

DTC

Optional external

signal handling

Bias

Generator

GPIOs

(software

control)

MSP430FRxxxx

图9-1. USS_A Subsystem Block Diagram

9.4 Low-Energy Accelerator (LEA) for Signal Processing

The LEA is a hardware engine designed for operations that involve vector-based signal processing, such as FIR,

IIR, and FFT. The LEA offers fast performance and low energy consumption when performing vector-based

digital signal processing computations. For performance benchmarks comparing LEA to using the CPU or other

processors, see Benchmarking the Signal-Processing Capabilities of the Low-Energy Accelerator.

The LEA requires MCLK to be operational; therefore, LEA runs only in active mode or LPM0. While the LEA is

running, the LEA data operations are performed on a shared 8KB of RAM out of the 12KB of total RAM (see 表

9-52). This shared RAM can also be used by the regular application. The MSP CPU and the LEA can run

simultaneously and independently unless they access the same system RAM.

Direct access to LEA registers is not supported, and TI recommends using the optimized Digital Signal

Processing (DSP) Library for MSP Microcontrollers for the operations that the LEA module supports.

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9.5.1 Peripherals in Low-Power Modes

Peripherals can be in different states that impact the achievable power modes of the device. The states depend

on the operational modes of the peripherals (see 表9-2). The states are:

• A peripheral is in a "high-frequency state" if it requires or uses a clock with a "high" frequency of more than

50 kHz.

• A peripheral is in a "low-frequency state" if it requires or uses a clock with a "low" frequency of 50 kHz or less.

• A peripheral is in an "unclocked state" if it does not require or use an internal clock.

If the CPU requests a power mode that does not support the current state of all active peripherals, the device

does not enter the requested power mode, but it does enter a power mode that still supports the current state of

the peripherals, except if an external clock is used. If an external clock is used, the application must use the

correct frequency range for the requested power mode.

表9-2. Peripheral States

PERIPHERAL

WDT

IN HIGH-FREQUENCY STATE ⁽¹⁾

Clocked by SMCLK

Not applicable

IN LOW-FREQUENCY STATE ⁽²⁾

IN UNCLOCKED STATE ⁽³⁾

Not applicable

Clocked by ACLK

DMA⁽⁴⁾

RTC_C

LCD_C

Not applicable

Waiting for a trigger.

Not applicable

Clocked by LFXT.

Not applicable

Clocked by ACLK or VLOCLK.

Not applicable

Clocked by ACLK or

clocked by external clock ≤50 kHz

Clocked by SMCLK or

clocked by external clock >50 kHz

Timer_A TAx

Timer_B TBx

Clocked by external clock ≤50 kHz

Waiting for first edge of START bit.

Not applicable

Clocked by ACLK or

clocked by external clock ≤50 kHz

Clocked by SMCLK or

clocked by external clock >50 kHz

eUSCI_Ax in

UART mode

Clocked by SMCLK

Clocked by ACLK

eUSCI_Ax in SPI

master mode

eUSCI_Ax in SPI

slave mode

Clocked by external clock >50 kHz

Clocked by external clock ≤50 kHz

Not applicable

eUSCI_Bx in I²C

master mode

Clocked by SMCLK or

clocked by external clock >50 kHz

Clocked by ACLK or

clocked by external clock ≤50 kHz

eUSCI_Bx in I²C

slave mode

Waiting for START condition or

clocked by external clock ≤50 kHz

Clocked by external clock >50 kHz

Clocked by SMCLK

Clocked by external clock ≤50 kHz

Clocked by ACLK

eUSCI_Bx in SPI

master mode

Not applicable

eUSCI_Bx in SPI

slave mode

Clocked by external clock >50 kHz

Clocked by external clock ≤50 kHz

ADC12_B

REF_A

COMP_E

CRC⁽⁵⁾

Clocked by SMCLK or by MODOSC

Not applicable

Clocked by ACLK

Not applicable

Waiting for a trigger

Always

Not applicable

Always

Not applicable

MPY⁽⁵⁾

Not applicable

AES⁽⁵⁾

Not applicable

(1) Peripherals are in a state that requires or uses a clock with a "high" frequency of more than 50 kHz.

(2) Peripherals are in a state that requires or uses a clock with a "low" frequency of 50 kHz or less.

(3) Peripherals are in a state that does not require or does not use an internal clock.

(4) The DMA always transfers data in active mode but can wait for a trigger in any low-power mode. A DMA trigger during a low-power

mode causes a temporary transition into active mode for the time of the transfer.

(5) This peripheral operates during active mode only and will delay the transition into a low-power mode until its operation is completed.

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9.5.2 Idle Currents of Peripherals in LPM3 and LPM4

Most peripherals can be operational in LPM3 if clocked by ACLK. Some modules are operational in LPM4,

because they do not require a clock to operate (for example, the comparator). Activating a peripheral in LPM3 or

LPM4 increases the current consumption due to its active supply current contribution but also due to an

additional idle current. To reduce the idle current adder, certain peripherals are grouped together. To achieve

optimal current consumption, use modules within one group and limit the number of groups with active modules.

表 9-3 lists the groups. Modules not listed in this table are either already included in the standard LPM3 current

consumption or cannot be used in LPM3 or LPM4.

The idle current adder is very small at room temperature (25°C) but increases at high temperatures (85°C). See

the I_IDLEcurrent parameters in 节8 for details.

表9-3. Peripheral Groups

GROUP A

Timer TA1

Timer TA2

Timer TB0

eUSCI_A0

eUSCI_A1

eUSCI_B0

GROUP B

Timer TA0

Timer TA3

Comparator

ADC12_B

REF_A

GROUP C

Timer TA4

eUSCI_A2

eUSCI_A3

eUSCI_B1

LCD_C

9.6 Interrupt Vector Table and Signatures

The interrupt vectors, the power-up start address and signatures are in the address range 0FFFFh to 0FF80h. 图

9-2 summarizes the content of this address range.

0FFFFh

Reset Vector

BSL Password

Interrupt

Vectors

0FFE0h

JTAG Password

Reserved

0FF88h

0FF80h

Signatures

图9-2. Interrupt Vectors, Signatures and Passwords

The power-up start address or reset vector is at 0FFFFh to 0FFFEh. It contains the 16-bit address pointing to the

start address of the application program.

The interrupt vectors start at 0FFFDh and extend to lower addresses. Each vector contains the 16-bit address of

the appropriate interrupt-handler instruction sequence. 表 9-4 shows the device specific interrupt vector

locations.

The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as BSL password (if enabled

by the corresponding signature).

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The signatures are located at 0FF80h and extend to higher addresses. Signatures are evaluated during device

start-up. 表9-5 shows the device specific signature locations.

A JTAG password can be programmed starting from address 0FF88h and extending to higher addresses. The

password can extend into the interrupt vector locations using the interrupt vector addresses as additional bits for

the password. The length of the JTAG password depends on the JTAG signature.

Refer to the chapter "System Resets, Interrupts, and Operating Modes, System Control Module (SYS)" in the

MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for details.

表9-4. Interrupt Sources, Flags, and Vectors

INTERRUPT

VECTOR

REGISTER

SYSTEM

INTERRUPT

WORD

ADDRESS

INTERRUPT SOURCE

System Reset

INTERRUPT FLAG

PRIORITY

Power up, brownout,

supply supervisor

SVSHIFG

External reset, RST

PMMRSTIFG

WDTIFG

Watchdog time-out

(watchdog mode)

SYSRSTIV⁽¹⁾

Reset

0FFFEh

Highest

WDT, FRCTL MPU, CS,

PMM password violation

WDTPW, FRCTLPW, MPUPW, CSPW,

PMMPW

FRAM uncorrectable bit

error detection

UBDIFG

MPU segment violation

MPUSEG1IFG, MPUSEG2IFG,

MPUSEG3IFG

Software POR, BOR

PMMPORIFG, PMMBORIFG

System NMI

Vacant memory access⁽²⁾

JTAG mailbox

VMAIFG

JMBINIFG, JMBOUTIFG

ACCTEIFG

FRAM access time error

SYSSNIV⁽¹⁾

(Non)maskable⁽³⁾

0FFFCh

FRAM write protection

error

WPIFG

FRAM bit error detection

CBDIFG, UBDIFG

MPUSEG1IFG, MPUSEG2IFG,

MPUSEG3IFG

MPU segment violation

User NMI

External NMI

NMIIFG

OFIFG

SYSUNIV⁽¹⁾

(Non)maskable⁽³⁾

0FFFAh

Oscillator fault

LEA RAM access conflict

DACCESSIFG

Comparator_E

TB0

CEIFG, CEIIFG

CEIV⁽¹⁾

Maskable

0FFF8h

0FFF6h

TB0CCR0 CCIFG

TB0CCR1 CCIFG to TB0CCR6 CCIFG,

TB0CTL.TBIFG

TB0

TB0IV⁽¹⁾

Maskable

0FFF4h

0FFF2h

Watchdog timer (interval

timer mode)

WDTIFG

UCRXIFG, UCTXIFG (SPI mode)

eUSCI_A0 receive or

transmit

UCA0IV⁽¹⁾

Maskable

0FFF0h

UCSTTIFG, UCTXCPTIFG, UCRXIFG,

UCTXIFG (UART mode)

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表9-4. Interrupt Sources, Flags, and Vectors (continued)

INTERRUPT

VECTOR

REGISTER

SYSTEM

INTERRUPT

WORD

ADDRESS

INTERRUPT SOURCE

INTERRUPT FLAG

PRIORITY

UCRXIFG, UCTXIFG (SPI mode)

UCALIFG, UCNACKIFG, UCSTTIFG,

UCSTPIFG, UCRXIFG0, UCTXIFG0,

UCRXIFG1, UCTXIFG1, UCRXIFG2,

UCTXIFG2, UCRXIFG3, UCTXIFG3,

UCCNTIFG, UCBIT9IFG (I²C mode)

eUSCI_B0 receive or

transmit

UCB0IV⁽¹⁾

Maskable

0FFEEh

ADC12IFG0 to ADC12IFG31,

ADC12LOIFG, ADC12INIFG,

ADC12HIIFG, ADC12RDYIFG,

ADC21OVIFG, ADC12TOVIFG

ADC12_B⁽⁴⁾

ADC12IV⁽¹⁾

Maskable

0FFECh

TA0

TA0CCR0 CCIFG

Maskable

0FFEAh

0FFE8h

TA0CCR1 CCIFG, TA0CCR2 CCIFG,

TA0CTL.TAIFG

TA0IV⁽¹⁾

UCA1IV⁽¹⁾

DMAIV⁽¹⁾

UCRXIFG, UCTXIFG (SPI mode)

eUSCI_A1 receive or

transmit

Maskable

0FFE6h

UCSTTIFG, UCTXCPTIFG, UCRXIFG,

UCTXIFG (UART mode)

DMA0CTL.DMAIFG, DMA1CTL.DMAIFG,

DMA2CTL.DMAIFG

DMA

TA1

Maskable

0FFE4h

0FFE2h

0FFE0h

TA1CCR0 CCIFG

TA1CCR1 CCIFG, TA1CCR2 CCIFG,

TA1CTL.TAIFG

TA1IV⁽¹⁾

P1IV⁽¹⁾

I/O port P1

TA2

P1IFG.0 to P1IFG.7

TA2CCR0 CCIFG

Maskable

0FFDEh

0FFDCh

0FFDAh

0FFD8h

0FFD6h

0FFD4h

0FFD2h

0FFD0h

TA2

TA2CCR1 CCIFG, TA2CTL.TAIFG

P2IFG.0 to P2IFG.7

TA2IV⁽¹⁾

P2IV⁽¹⁾

I/O port P2

TA3

TA3CCR0 CCIFG

TA3

TA3CCR1 CCIFG, TA3CTL.TAIFG

P3IFG.0 to P3IFG.7

TA3IV⁽¹⁾

P3IV⁽¹⁾

P4IV⁽¹⁾

I/O port P3

I/O port P4

P4IFG.0 to P4IFG.7

LCDNOCAPIFG, LCDBLKOFFIFG,

LCDBLKONIFG, LCDFRMIFG

LCD_C

RTC_C

LCDCIV⁽¹⁾

RTCIV⁽¹⁾

Maskable

0FFCEh

0FFCCh

RTCRDYIFG, RTCTEVIFG, RTCAIFG,

RT0PSIFG, RT1PSIFG, RTCOFIFG

AES

TA4

AESRDYIFG

TA4CCR0 CCIFG

Maskable

0FFCAh

0FFC8h

0FFC6h

0FFC4h

0FFC2h

TA4

TA4CCR1 CCIFG, TA4CTL.TAIFG

P5IFG.0 to P5IFG.7

TA4IV⁽¹⁾

P5IV⁽¹⁾

P6IV⁽¹⁾

I/O port P5

I/O port P6

P6IFG.0 to P6IFG.7

UCRXIFG, UCTXIFG (SPI mode)

eUSCI_A2 receive or

transmit

UCA2IV⁽¹⁾

UCA3IV⁽¹⁾

Maskable

0FFC0h

0FFBEh

UCSTTIFG, UCTXCPTIFG, UCRXIFG,

UCTXIFG (UART mode)

UCRXIFG, UCTXIFG (SPI mode)

eUSCI_A3 receive or

transmit

UCSTTIFG, UCTXCPTIFG, UCRXIFG,

UCTXIFG (UART mode)

UCRXIFG, UCTXIFG (SPI mode)

UCALIFG, UCNACKIFG, UCSTTIFG,

UCSTPIFG, UCRXIFG0, UCTXIFG0,

UCRXIFG1, UCTXIFG1, UCRXIFG2,

UCTXIFG2, UCRXIFG3, UCTXIFG3,

UCCNTIFG, UCBIT9IFG (I²C mode)

eUSCI_B1 receive or

transmit

UCB1IV⁽¹⁾

Maskable

0FFBCh

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PRIORITY

表9-4. Interrupt Sources, Flags, and Vectors (continued)

INTERRUPT

VECTOR

REGISTER

SYSTEM

INTERRUPT

WORD

ADDRESS

INTERRUPT SOURCE

INTERRUPT FLAG

I/O port P7

LEA

P7IFG.0 to P7IFG.7

P7IV⁽¹⁾

Maskable

0FFBAh

0FFB8h

CMDIFG, SDIIFG, OORIFG, TIFG,

COVLIFG

LEAIV⁽¹⁾

UUPS

HSPLL

PTMOUT, PREQIG

PLLUNLOCK

IIDX⁽¹⁾

Maskable

0FFB6h

0FFB4h

0FFB2h

SAPH_A

DATAERR, TAMTO, SEQDN, PNGDN

OVF, ACQDONE, SSTRG, DTRDY,

WINHI, WINLO

SDHS

IIDX⁽¹⁾

Maskable

0FFB0h

Lowest

(1) Multiple source flags

(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space.

(3) (Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it.

(4) Only on devices with ADC, otherwise reserved.

表9-5. Signatures

SIGNATURE

IP Encapsulation Signature2

IP Encapsulation Signature1⁽¹⁾

BSL Signature2

WORD ADDRESS

0FF8Ah

0FF88h

0FF86h

BSL Signature1

0FF84h

JTAG Signature2

0FF82h

JTAG Signature1

0FF80h

(1) Must not contain 0AAAAh if used as the JTAG password.

9.7 Bootloader (BSL)

The BSL can program the FRAM or RAM using a UART serial interface (FRxxxx devices) or an I²C interface

(FRxxxx1 devices). Access to the device memory through the BSL is protected by an user-defined password. 表

9-6 lists the pins that are required for use of the BSL. BSL entry requires a specific entry sequence on the

RST/NMI/SBWTDIO and TEST/SBWTCK pins. For a complete description of the features of the BSL and its

implementation, see the MSP430™ FRAM Devices Bootloader (BSL) User's Guide. More information on the

BSL can be found at www.ti.com/tool/mspbsl.

表9-6. BSL Pin Requirements and Functions

DEVICE SIGNAL

RST/NMI/SBWTDIO

TEST/SBWTCK

P2.0

BSL FUNCTION

Entry sequence signal

Devices with UART BSL (FRxxxx): Data transmit

Devices with UART BSL (FRxxxx): Data receive

Devices with I²C BSL (FRxxxx1): Data

Devices with I²C BSL (FRxxxx1): Clock

Power supply

P2.1

P1.6

P1.7

DVCC, AVCC

DVSS, AVSS

Ground supply

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9.8 JTAG Operation

9.8.1 JTAG Standard Interface

The MSP family supports the standard JTAG interface, which requires four signals for sending and receiving

data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the

JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP

development tools and device programmers. 表 9-7 lists the JTAG pin requirements. For further details on

interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For a

complete description of the features of the JTAG interface and its implementation, see MSP430 Programming

With the JTAG Interface.

表9-7. JTAG Pin Requirements and Functions

DEVICE SIGNAL

DIRECTION

FUNCTION

JTAG clock input

JTAG state control

JTAG data input, TCLK input

JTAG data output

Enable JTAG pins

External reset

PJ.3/TCK

IN

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

IN

OUT

IN

TEST/SBWTCK

RST/NMI/SBWTDIO

DVCC, AVCC

DVSS, AVSS

IN

Power supply

–

Ground supply

–

9.8.2 Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the MSP family supports the two wire Spy-Bi-Wire interface. Spy-Bi-

Wire can be used to interface with MSP development tools and device programmers. The Spy-Bi-Wire interface

pin requirements are shown in 表 9-8. For further details on interfacing to development tools and device

programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the

JTAG interface and its implementation, see MSP430 Programming With the JTAG Interface.

表9-8. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL

TEST/SBWTCK

RST/NMI/SBWTDIO

DVCC, AVCC

DIRECTION

FUNCTION

Spy-Bi-Wire clock input

Spy-Bi-Wire data input and output

Power supply

IN

IN, OUT

–

DVSS, AVSS

Ground supply

–

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9.9 FRAM Controller A (FRCTL_A)

The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU.

Features of the FRAM include:

• Ultra-low-power ultra-fast-write nonvolatile memory

• Byte and word access capability

• Programmable wait state generation

• Error correction coding (ECC)

Note

Wait States

For MCLK frequencies >8 MHz, wait states must be configured as described in the Wait State Control

section of the FRAM Controller A (FRCTRL_A) chapter in the MSP430FR58xx, MSP430FR59xx, and

MSP430FR6xx Family User's Guide.

For important software design information regarding FRAM including but not limited to partitioning the memory

layout according to application-specific code, constant, and data space requirements, the use of FRAM to

optimize application energy consumption, and the use of the memory protection unit (MPU) to maximize

application robustness by protecting the program code against unintended write accesses, see MSP430™

FRAM Technology –How to and Best Practices.

9.10 RAM

The RAM is made up of three sectors. Sector 0 = 2KB, Sector 1 = 2KB, Sector 2 = 8KB (shared with LEA). Each

sector can be individually powered down in LPM3 and LPM4 to save leakage. Data is lost when sectors are

powered down in LPM3 and LPM4.

9.11 Tiny RAM

22 bytes of Tiny RAM are provided in addition to the complete RAM (see 表 9-52). This memory is always

available, even in LPM3 and LPM4, while the complete RAM can be powered down in LPM3 and LPM4. Tiny

RAM can be used to hold data or a very small stack when the complete RAM is powered down in LPM3 and

LPM4. No memory is available in LPMx.5.

9.12 Memory Protection Unit (MPU) Including IP Encapsulation

The FRAM can be protected by the MPU from inadvertent CPU execution, read access, or write access.

Features of the MPU include:

• IP encapsulation with programmable boundaries in steps of 1KB (prevents reads from "outside"; for example,

through JTAG or by non-IP software).

• Main memory partitioning is programmable up to three segments in steps of 1KB.

• Access rights of each segment can be individually selected (main and information memory).

• Access violation flags with interrupt capability for easy servicing of access violations.

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9.13 Peripherals

Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be controlled

using all instructions. For complete module descriptions, see the MSP430FR58xx, MSP430FR59xx, and

MSP430FR6xx Family User's Guide.

9.13.1 Digital I/O

Up to eight 8-bit I/O ports are implemented:

• All individual I/O bits are independently programmable.

• Any combination of input, output, and interrupt conditions is possible.

• Programmable pullup or pulldown on all ports.

• Edge-selectable interrupt and LPM3.5 and LPM4.5 wakeup input capability is available for all pins of ports

P1, P2, P3, P4, P5, P6, and P7.

• Read and write access to port control registers is supported by all instructions.

• Ports P1/P2, P3/P4, P5/P6, P7/(P8) can be accessed byte-wise or word-wise in pairs.

• No cross-currents during start-up.

Note

Configuration of Digital I/Os After BOR Reset

To prevent any cross currents during start-up of the device, all port pins are high-impedance with

Schmitt triggers and their module functions disabled. To enable the I/O functionality after a BOR reset,

the ports must be configured first and then the LOCKLPM5 bit must be cleared. For details, refer to

the "Configuration After Reset" section of the Digital I/O chapter in the MSP430FR58xx,

MSP430FR59xx, and MSP430FR6xx Family User's Guide.

9.13.2 Oscillator and Clock System (CS)

The clock system includes support for a 32-kHz watch-crystal oscillator XT1 (LF), an internal very-low-power

low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency

crystal oscillator XT2 (HF). The clock system module is designed to meet the requirements of both low system

cost and low power consumption. A fail-safe mechanism exists for all crystal sources. The clock system module

provides the following clock signals:

• Auxiliary clock (ACLK). ACLK can be sourced from a 32-kHz watch crystal (LFXT1), the internal VLO, or a

digital external low-frequency (<50 kHz) clock source.

• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced from a high-frequency crystal

(HFXT2), the internal DCO, a 32-kHz watch crystal (LFXT1), the internal VLO, or a digital external clock

source.

• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by

same sources made available to MCLK.

• The high frequency oscillator XT2 (HF) can be sourced from the oscillator of the ultrasonic subsystem

USSXT through an internal connection.

9.13.3 Power-Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM also

includes supply voltage supervisor (SVS) and brownout protection. The brownout circuit provides the proper

internal reset signal to the device during power on and power off. The SVS circuitry detects if the supply voltage

drops below a safe level and below a user-selectable level. SVS circuitry is available on the primary and core

supplies.

9.13.4 Hardware Multiplier (MPY)

The multiplication operation is supported by a dedicated peripheral module. The module performs operations

with 32-, 24-, 16-, and 8-bit operands. The module supports signed multiplication, unsigned multiplication, signed

multiply-and-accumulate, and unsigned multiply-and-accumulate operations.

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9.13.5 Real-Time Clock (RTC_C)

The RTC_C module contains an integrated real-time clock (RTC) with the following features:

• Calendar mode with leap year correction

• General-purpose counter mode

The internal calendar compensates for months with fewer than 31 days and includes leap year correction. The

RTC_C also supports flexible alarm functions and offset-calibration hardware. RTC operation is available in

LPM3.5 modes to minimize power consumption.

9.13.6 Measurement Test Interface (MTIF)

The MTIF module provides a simple pulse-based test interface that is used to implement consumption

monitoring of "legal relevant data" with high integrity. MTIF consists of the a pulse generator, a pulse counter,

and a pulse interface. MTIF has following features:

• Independent passwords for generator counter and pulse interface

• Pulse rates up to 1016 pulses/second

• Pulse frame duration from 1/16 s to 16 s

• Count capacity up to 65535 (16 bit)

• Operating in LPM3.5 with 200 nA

• 2-pin interface with MTIF_OUT_IN and MTIF_PIN_EN

9.13.7 Watchdog Timer (WDT_A)

The primary function of the WDT_A module is to perform a controlled system restart if a software problem

occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed

in an application, the module can be configured as an interval timer and can generate interrupts at selected time

intervals. 表9-9 lists the clocks that can be selected by the WDT.

表9-9. WDT_A Clocks

NORMAL OPERATION

WDTSSEL

(WATCHDOG AND INTERVAL TIMER

MODE)

00

01

10

11

SMCLK

ACLK

VLOCLK

LFMODCLK

9.13.8 System Module (SYS)

The SYS module manages many of the system functions within the device. These include power-on reset (POR)

and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector generators,

bootloader (BSL) entry mechanisms, and configuration management (device descriptors). The SYS module also

includes a data exchange mechanism through JTAG called a JTAG mailbox that can be used in the application.

表9-10 lists the SYS module interrupt vector registers.

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表9-10. System Module Interrupt Vector Registers

INTERRUPT VECTOR REGISTER

ADDRESS

INTERRUPT EVENT

VALUE

00h

PRIORITY

No interrupt pending

Brownout (BOR)

02h

Highest

RSTIFG RST/NMI (BOR)

04h

PMMSWBOR software BOR (BOR)

LPMx.5 wakeup (BOR)

06h

08h

Security violation (BOR)

0Ah

0Ch

0Eh

10h

Reserved

SVSHIFG SVSH event (BOR)

Reserved

12h

PMMSWPOR software POR (POR)

WDTIFG watchdog timeout (PUC)

WDTPW password violation (PUC)

FRCTLPW password violation (PUC)

Uncorrectable FRAM bit error detection (PUC)

Peripheral area fetch (PUC)

PMMPW PMM password violation (PUC)

MPUPW MPU password violation (PUC)

CSPW CS password violation (PUC)

MPUSEGIPIFG encapsulated IP memory segment violation (PUC)

Reserved

14h

16h

SYSRSTIV, System Reset

019Eh

18h

1Ah

1Ch

1Eh

20h

22h

24h

26h

28h

MPUSEG1IFG segment 1 memory violation (PUC)

MPUSEG2IFG segment 2 memory violation (PUC)

MPUSEG3IFG segment 3 memory violation (PUC)

Reserved

2Ah

2Ch

2Eh

30h to 3Eh

00h

Lowest

Highest

No interrupt pending

Reserved

02h

Uncorrectable FRAM bit error detection

FRAM Access Time Error

04h

06h

MPUSEGIPIFG encapsulated IP memory segment violation

Reserved

08h

0Ah

0Ch

0Eh

10h

MPUSEG1IFG segment 1 memory violation

MPUSEG2IFG segment 2 memory violation

MPUSEG3IFG segment 3 memory violation

VMAIFG Vacant memory access

JMBINIFG JTAG mailbox input

JMBOUTIFG JTAG mailbox output

Correctable FRAM bit error detection

FRAM Write Protection Detection

LEA Time-out Fault

SYSSNIV, System NMI

019Ch

12h

14h

16h

18h

1Ah

1Ch

1Eh

00h

LEA Command Fault

Lowest

Highest

No interrupt pending

NMIIFG NMI pin

02h

OFIFG oscillator fault

04h

SYSUNIV, User NMI

019Ah

DACCESSIFG

06h

Reserved

08h

Reserved

0Ah to 1Eh

Lowest

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9.13.9 DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention.

For example, the DMA controller can be used to move data from the ADC12_B conversion memory to RAM.

Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces

system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move

data to or from a peripheral. 表9-11 lists the available DMA trigger assignments.

表9-11. DMA Trigger Assignments⁽¹⁾

TRIGGER

CHANNEL 0

DMAREQ

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

DMAREQ

CHANNEL 5

DMAREQ

0

1

DMAREQ

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA3CCR0 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

TA4CCR0 CCIFG

Reserved

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA3CCR0 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

TA4CCR0 CCIFG

Reserved

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA3CCR0 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

TA4CCR0 CCIFG

Reserved

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA3CCR0 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

TA4CCR0 CCIFG

Reserved

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA3CCR0 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

TA4CCR0 CCIFG

Reserved

TA0CCR0 CCIFG

TA0CCR2 CCIFG

TA1CCR0 CCIFG

TA1CCR2 CCIFG

TA2CCR0 CCIFG

TA3CCR0 CCIFG

TB0CCR0 CCIFG

TB0CCR2 CCIFG

TA4CCR0 CCIFG

Reserved

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

AES Trigger 0

AES Trigger 1

AES Trigger 2

UCA0RXIFG

AES Trigger 0

AES Trigger 1

AES Trigger 2

UCA0RXIFG

AES Trigger 0

AES Trigger 1

AES Trigger 2

UCA0RXIFG

AES Trigger 0

AES Trigger 1

AES Trigger 2

UCA2RXIFG

AES Trigger 0

AES Trigger 1

AES Trigger 2

UCA2RXIFG

AES Trigger 0

AES Trigger 1

AES Trigger 2

UCA2RXIFG

UCA0TXIFG

UCA2TXIFG

UCA1RXIFG

UCA3RXIFG

UCA1TXIFG

UCA3TXIFG

UCB0RXIFG (SPI)

UCB0RXIFG0 (I²C)

UCB0RXIFG (SPI)

UCB0RXIFG0 (I²C)

UCB0RXIFG (SPI)

UCB0RXIFG0 (I²C)

UCB1RXIFG (SPI)

UCB1RXIFG0 (I²C)

UCB1RXIFG (SPI)

UCB1RXIFG0 (I²C)

UCB1RXIFG (SPI)

UCB1RXIFG0 (I²C)

18

19

UCB0TXIFG (SPI)

UCB0TXIFG0 (I²C)

UCB0TXIFG (SPI)

UCB0TXIFG0 (I²C)

UCB0TXIFG (SPI)

UCB0TXIFG0 (I²C)

UCB1TXIFG (SPI)

UCB1TXIFG0 (I²C)

UCB1TXIFG (SPI)

UCB1TXIFG0 (I²C)

UCB1TXIFG (SPI)

UCB1TXIFG0 (I²C)

20

21

22

23

24

25

UCB0RXIFG1 (I²C)

UCB0TXIFG1 (I²C)

UCB0RXIFG2 (I²C)

UCB0TXIFG2 (I²C)

UCB0RXIFG3 (I²C)

UCB0TXIFG3 (I²C)

UCB0RXIFG1 (I²C)

UCB0TXIFG1 (I²C)

UCB0RXIFG2 (I²C)

UCB0TXIFG2 (I²C)

UCB0RXIFG3 (I²C)

UCB0TXIFG3 (I²C)

UCB0RXIFG1 (I²C)

UCB0TXIFG1 (I²C)

UCB0RXIFG2 (I²C)

UCB0TXIFG2 (I²C)

UCB0RXIFG3 (I²C)

UCB0TXIFG3 (I²C)

UCB1RXIFG1 (I²C)

UCB1TXIFG1 (I²C)

UCB1RXIFG2 (I²C)

UCB1TXIFG2 (I²C)

UCB1RXIFG3 (I²C)

UCB1TXIFG3 (I²C)

UCB1RXIFG1 (I²C)

UCB1TXIFG1 (I²C)

UCB1RXIFG2 (I²C)

UCB1TXIFG2 (I²C)

UCB1RXIFG3 (I²C)

UCB1TXIFG3 (I²C)

UCB1RXIFG1 (I²C)

UCB1TXIFG1 (I²C)

UCB1RXIFG2 (I²C)

UCB1TXIFG2 (I²C)

UCB1RXIFG3 (I²C)

UCB1TXIFG3 (I²C)

ADC12 end of

conversion

ADC12 end of

conversion

ADC12 end of

conversion

ADC12 end of

conversion

ADC12 end of

conversion

ADC12 end of

conversion

26

27

28

29

30

31

LEA Ready

Reserved

MPY ready

DMA2IFG

DMAE0

LEA Ready

Reserved

MPY ready

DMA0IFG

DMAE0

USS_A PPGTRIG

Reserved

USS_A PPGTRIG

Reserved

LEA Ready

Reserved

MPY ready

DMA3IFG

DMAE0

LEA Ready

Reserved

MPY ready

DMA4IFG

DMAE0

MPY ready

DMA1IFG

MPY ready

DMA5IFG

DMAE0

(1) If a reserved trigger source is selected, no trigger is generated.

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9.13.10 Enhanced Universal Serial Communication Interface (eUSCI)

The eUSCI modules are used for serial data communication. The eUSCI module supports synchronous

communication protocols such as SPI (3- or 4-pin) and I²C, and asynchronous communication protocols such as

UART, enhanced UART with automatic baud-rate detection, and IrDA.

The eUSCI_A0, eUSCI_A1, eUSCI_A2, and eUSCI_A3 modules support SPI (3- or 4-pin), UART, enhanced

UART, and IrDA.

The eUSCI_B0 and eUSCI_B1 modules support SPI (3- or 4-pin) and I²C.

Up to four eUSCI_A modules and up to two eUSCI_B modules are implemented.

9.13.11 TA0, TA1, and TA4

TA0, TA1, and TA4 are 16-bit timers and counters (Timer_A type) with three (TA0 and TA1) or two (TA4) capture/

compare registers each. Each timer can support multiple captures or compares, PWM outputs, and interval

timing (see 表 9-12, 表 9-13, and 表 9-14). Each timer has extensive interrupt capabilities. Interrupts may be

generated from the counter on overflow conditions and from each of the capture/compare registers.

表9-12. TA0 Signal Connections

DEVICE INPUT MODULE INPUT

MODULE

BLOCK

MODULE

OUTPUT SIGNAL

DEVICE OUTPUT

SIGNAL

INPUT PORT PIN

OUTPUT PORT PIN

SIGNAL

TACLK

ACLK

P2.4, P4.5, P6.0

TA0CLK

ACLK (internal)

SMCLK (internal)

TA0CLK

Timer

CCR0

N/A

TA0

N/A

SMCLK

INCLK

CCI0A

CCI0B

GND

P2.4. P4.5, P6.0

P2.3

TA0.0

P2.3

P5.4

TA0.0

DVSS

DVCC

V_CC

P6.7

P5.7

TA0.1

CCI1A

P6.7

ADC12(internal)⁽¹⁾

ADC12SHSx = {1}

COUT (internal)

CCI1B

CCR1

CCR2

TA1

TA2

TA0.1

TA0.2

DVSS

DVCC

GND

V_CC

TA0.2

CCI2A

CCI2B

P5.7

P2.5

ACLK (internal)

UUPS Trigger

(USSPWRUP)

UUPS.CTL.USSPWR

UPSEL = {2}

DVSS

DVCC

GND

V_CC

(1) Only on devices with ADC.

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表9-13. TA1 Signal Connections

DEVICE INPUT MODULE INPUT

MODULE

BLOCK

MODULE

OUTPUT SIGNAL

DEVICE OUTPUT

SIGNAL

INPUT PORT PIN

OUTPUT PORT PIN

SIGNAL

TACLK

ACLK

P2.4, P4.5, P3.1

TA1CLK

ACLK (internal)

SMCLK (internal)

TA1CLK

Timer

CCR0

N/A

TA0

N/A

SMCLK

INCLK

CCI0A

CCI0B

GND

P2.4. P4.5, P3.1

P1.0

TA1.0

P1.0

P1.2

P7.0

TA1.0

DVSS

DVCC

V_CC

P3.2

P2.6

TA1.1

CCI1A

CCI1B

P1.3

P3.2

COUT (internal)

ADC12(internal)⁽¹⁾

ADC12SHSx = {4}

CCR1

CCR2

TA1

TA2

TA1.1

TA1.2

DVSS

GND

DVCC

TA1.2

V_CC

CCI2A

CCI2B

P2.6

P7.0

ACLK (internal)

ASQ Trigger

(ASQTRIG)

SAPH.ASCTL0.TRIG

SEL={2}

DVSS

DVCC

GND

V_CC

(1) Only on devices with ADC.

表9-14. TA4 Signal Connections

DEVICE INPUT MODULE INPUT

MODULE

BLOCK

MODULE

OUTPUT SIGNAL

DEVICE OUTPUT

SIGNAL

INPUT PORT PIN

OUTPUT PORT PIN

SIGNAL

PJ.1, P4.6,

PPGTick

TA4CLK

TACLK

ACLK (internal)

ACLK

Timer

N/A

SMCLK (internal)

SMCLK

PJ.1, P4.6,

PPGTick

TA4CLK

INCLK

P1.1

P2.5

TA4.0

DVSS

DVCC

TA4.1

CCI0A

CCI0B

GND

P1.1

P2.5

CCR0

CCR1

TA0

TA1

TA4.0

TA4.1

V_CC

P5.5

P2.7

CCI1A

CCI1B

P5.5

P2.7

ADC12(internal)⁽¹⁾

ADC12SHSx = {7}

DVSS

DVCC

GND

V_CC

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9.13.12 TA2 and TA3

TA2 and TA3 are 16-bit timers and counters (Timer_A type) with two capture/compare registers each and with

internal connections only. Each timer can support multiple captures or compares, PWM outputs, and interval

timing (see 表 9-15 and 表 9-16). Each timer has extensive interrupt capabilities. Interrupts may be generated

from the counter on overflow conditions and from each of the capture/compare registers.

表9-15. TA2 Signal Connections

MODULE OUTPUT

SIGNAL

DEVICE OUTPUT

SIGNAL

DEVICE INPUT SIGNAL

MODULE INPUT NAME

MODULE BLOCK

COUT (internal)

ACLK (internal)

SMCLK (internal)

Reserved

TACLK

ACLK

Timer

N/A

TA0

SMCLK

INCLK

TA3 CCR0 output

(internal)

CCI0A

TA3 CCI0A input

ACLK (internal)

DVSS

CCI0B

GND

V_CC

CCR0

CCR1

DVCC

ADC12(internal)⁽¹⁾

ADC12SHSx = {5}

Reserved

CCI1A

CCI1B

PPG Trigger (PPGTRIG)

SAPH.PGCTL.TRSEL={2}

COUT (internal)

TA1

DVSS

DVCC

GND

V_CC

(1) Only on devices with ADC

表9-16. TA3 Signal Connections

MODULE OUTPUT

DEVICE OUTPUT

SIGNAL

DEVICE INPUT SIGNAL

MODULE INPUT NAME

MODULE BLOCK

SIGNAL

COUT (internal)

ACLK (internal)

SMCLK (internal)

Reserved

TACLK

ACLK

Timer

N/A

SMCLK

INCLK

TA2 CCR0 output

(internal)

CCI0A

TA2 CCI0A input

ACLK (internal)

DVSS

CCI0B

GND

V_CC

CCR0

CCR1

TA0

TA1

DVCC

ADC12(internal)⁽¹⁾

ADC12SHSx = {6}

Reserved

CCI1A

COUT (internal)

DVSS

CCI1B

GND

V_CC

DVCC

(1) Only on devices with ADC

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9.13.13 TB0

TB0 is a 16-bit timer and counter (Timer_B type) with seven capture/compare registers. TB0 can support

multiple captures or compares, PWM outputs, and interval timing (see 表 9-17). TB0 has extensive interrupt

capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/

compare registers.

表9-17. TB0 Signal Connections

DEVICE INPUT MODULE INPUT

MODULE

OUTPUT SIGNAL

DEVICE OUTPUT

SIGNAL

INPUT PORT PIN

MODULE BLOCK

OUTPUT PORT PIN

SIGNAL

TBCLK

ACLK

P2.4, P4.6, P6.2

TB0CLK

ACLK (internal)

SMCLK (internal)

TB0CLK

Timer

N/A

SMCLK

INCLK

CCI0A

CCI0B

P2.4, P4.6, P6.2

P3.0

TB0.0

P3.0

P5.0

TB0.0

ADC12 (internal)⁽¹⁾

ADC12SHSx = {2}

CCR0

CCR1

TB0

TB0.0

DVSS

GND

DVCC

TB0.1

V_CC

P3.1

P3.7

CCI1A

CCI1B

P3.1

P5.1

COUT (internal)

ADC12 (internal)⁽¹⁾

ADC12SHSx = {3}

TB1

TB0.1

DVSS

GND

DVCC

TB0.2

V_CC

CCI2A

CCI2B

GND

P3.7

P5.2

ACLK (internal)

DVSS

CCR2

CCR3

CCR4

CCR5

CCR6

TB2

TB3

TB4

TB5

TB6

TB0.2

TB0.3

TB0.4

TB0.5

TB0.6

DVCC

TB0.3

V_CC

P5.3

P3.3

CCI3A

CCI3B

GND

P5.3

P3.3

TB0.3

DVSS

DVCC

TB0.4

V_CC

P1.4

P4.1

CCI4A

CCI4B

GND

P1.4

P4.1

TB0.4

DVSS

DVCC

TB0.5

V_CC

P1.5

P4.2

CCI5A

CCI5B

GND

P1.5

P4.2

TB0.5

DVSS

DVCC

TB0.6

V_CC

PJ.3

P3.6

CCI6A

CCI6B

GND

PJ.3

P3.6

TB0.6

DVSS

DVCC

V_CC

(1) Only on devices with ADC.

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9.13.14 ADC12_B

The ADC12_B module supports fast 12-bit analog-to-digital conversions with differential and single-ended

inputs. The module implements a 12-bit SAR core, sample select control, a reference generator, and a

conversion result buffer. A window comparator with lower and upper limits allows CPU-independent result

monitoring with three window comparator interrupt flags.

表 9-18 lists the available external trigger sources. 表 9-19 lists the available multiplexing between internal and

external analog inputs.

表9-18. ADC12_B Trigger Signal Connections

ADC12SHSx

CONNECTED TRIGGER

SOURCE

BINARY

DECIMAL

000

001

010

011

100

101

110

111

0

1

2

3

4

5

6

7

Software (ADC12SC)

TA0 CCR1 output

TB0 CCR0 output

TB0 CCR1 output

TA1 CCR1 output

TA2 CCR1 output

TA3 CCR1 output

TA4 CCR1 output

表9-19. ADC12_B External and Internal Signal Mapping

CONTROL BIT IN ADC12CTL3

EXTERNAL ADC INPUT

(CONTROL BIT = 0)

INTERNAL ADC INPUT

REGISTER

(CONTROL BIT = 1)

Battery monitor

Temperature sensor

N/A⁽¹⁾

ADC12BATMAP

ADC12TCMAP

ADC12CH0MAP

ADC12CH1MAP

ADC12CH2MAP

ADC12CH3MAP

A31

A30

A29

A28

A27

A26

N/A⁽¹⁾

(1) N/A = No internal signal is available on this device.

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9.13.15 USS_A

表9-20 lists the available connections for the UUPS trigger signal.

表9-20. UUPS Trigger Signal Connections

UUPS.CTL.USSPWRUPSEL

CONNECTED TRIGGER SOURCE

Software (UUPS.CTL.USSPWRUP)

RTC (any enabled interrupt events)

TA0 CCR2 output

00b

01b

10b

11b

P1.7

表9-21 lists the available connections for the PPF trigger signal.

表9-21. PPG Trigger Signal Connections

SAPH.PGCTL.TRSEL

CONNECTED TRIGGER SOURCE

Software (SAPH.PPGTRIG.PPGTRIG)

ASQ (acquisition sequencer)

TA2 CCR1 output

00b

01b

10b

11b

Reserved

表9-22 lists the available connections for the ASQ trigger signal.

表9-22. ASQ Trigger Signal Connections

SAPH.ASCTL0.TRIGSEL

CONNECTED TRIGGER SOURCE

Software (SAPH.ASQTRIG.ASQTRIG)

PSQ (power sequencer)

TA1 CCR2 output

00b

01b

10b

11b

Reserved

9.13.16 Comparator_E

The primary function of the Comparator_E module is to support precision slope analog-to-digital conversions,

battery voltage supervision, and monitoring of external analog signals.

9.13.17 CRC16

The CRC16 module produces a signature based on a sequence of entered data values and can be used for data

checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.

9.13.18 CRC32

The CRC32 module produces a signature based on a sequence of entered data values and can be used for data

checking purposes. The CRC32 signature is based on the ISO 3309 standard.

9.13.19 AES256 Accelerator

The AES accelerator module performs encryption and decryption of 128-bit data with 128-, 192-, or 256-bit keys

according to the Advanced Encryption Standard (AES) (FIPS PUB 197) in hardware.

9.13.20 True Random Seed

The Device Descriptor Information (TLV) section contains a 128-bit true random seed that can be used to

implement a deterministic random number generator.

9.13.21 Shared Reference (REF)

The REF module is responsible for generation of all critical reference voltages that can be used by the various

analog peripherals in the device.

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9.13.22 LCD_C

The LCD_C driver generates the segment and common signals required to drive a liquid crystal display (LCD).

The LCD_C controller has dedicated data memories to hold segment drive information. Common and segment

signals are generated as defined by the mode. Static, and 2-mux up to 8-mux LCDs are supported. The module

can provide an LCD voltage independent of the supply voltage with its integrated charge pump. It is possible to

control the level of the LCD voltage and thus contrast by software. The module also provides an automatic

blinking capability for individual segments in static, 2-mux, 3-mux, and 4-mux modes.

To reduce system noise the charge pump can be temporarily disabled. 表 9-23 lists the available automatic

charge pump disable options.

表9-23. LCD Automatic Charge Pump Disable Bits (LCDCPDISx)

CONTROL BIT

DESCRIPTION

LCD charge pump disable during ADC12 conversion

LCDCPDIS0

0b = LCD charge pump not automatically disabled during conversion.

1b = LCD charge pump automatically disabled during conversion.

LCDCPDIS1 to

LCDCPDIS7

No functionality

9.13.23 Embedded Emulation

9.13.23.1 Embedded Emulation Module (EEM) (S Version)

The EEM supports real-time in-system debugging. The S version of the EEM has the following features:

• Three hardware triggers or breakpoints on memory access

• One hardware trigger or breakpoint on CPU register write access

• Up to four hardware triggers can be combined to form complex triggers or breakpoints

• One cycle counter

• Clock control on module level

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9.13.23.2 EnergyTrace++ Technology

The devices implement circuitry to support EnergyTrace++ technology. The EnergyTrace++ technology allows

you to observe information about the internal states of the microcontroller. These states include the CPU

Program Counter (PC), the ON or OFF status of the peripherals and the system clocks (regardless of the clock

source), and the low-power mode currently in use. These states can always be read by a debug tool, even when

the microcontroller sleeps in LPMx.5 modes.

The activity of the following modules can be observed:

• LEA is running.

• MPY is calculating.

• WDT is counting.

• RTC is counting.

• ADC: a sequence, sample, or conversion is active.

• REF: REFBG or REFGEN active and BG in static mode.

• COMP is on.

• AES is encrypting or decrypting.

• eUSCI_A0 is transferring (receiving or transmitting) data.

• eUSCI_A1 is transferring (receiving or transmitting) data.

• eUSCI_A2 is transferring (receiving or transmitting) data.

• eUSCI_A3 is transferring (receiving or transmitting) data.

• eUSCI_B0 is transferring (receiving or transmitting) data.

• eUSCI_B1 is transferring (receiving or transmitting) data.

• TB0 is counting.

• TA0 is counting.

• TA1 is counting.

• TA2 is counting.

• TA3 is counting.

• TA4 is counting.

• LCD_C is running.

• USS status

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9.14 Input/Output Diagrams

9.14.1 Port Function Select Registers (PySEL1 , PySEL0)

Port pins are multiplexed with peripheral module functions as described in the MSP430FR58xx,

MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide. The functions of each port pin are

controlled by its port function select registers, PySEL1 and PySEL0, where y = port number. The bits in the

registers are mapped to the pins in the port. The primary module function, secondary module function, and

tertiary module function of the pins are determined by the configuration of the PySEL1.x bit and the PySEL0.x bit

as shown in 表 9-24. For example, P1SEL1.0 and P1SEL0.0 determine the primary module function, secondary

module function, and tertiary module function of the P1.0 pin, which is in port 1. The module functions may also

require the PxDIR bits to be configured according to the direction needed for the module function.

表9-24. I/O Function Selection

I/O FUNCTIONS

PySEL1.x⁽¹⁾

PySEL0.x⁽¹⁾

General purpose I/O is selected

0

1

0

1

0

1

Primary module function is selected

Secondary module function is selected

Tertiary module function is selected

(1) y = port, x = bit

See the port pin function tables in the following sections for the configurations of the function and direction for

each pin.

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9.14.2 Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger

图9-3 shows the port diagram. 表9-25 summarizes the selection of the pin function.

Pad Logic

(ADC) Reference

To ADC

From ADC

To Comparator

From Comparator

CBPD.x

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

Module 1 or PxDIR.x

Module 2 or PxDIR.x

Module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

Module 1 or DVSS

Module 2 or DVSS

Module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-3. Port P1 (P1.0 to P1.1) Diagram

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表9-25. Port P1 (P1.0 to P1.1) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PM

PIN NAME (P1.x)

PN 80

FUNCTION

RGC 64

P1DIR.x

P1SEL1.x

P1SEL0.x

0 = Input,

1 = Output

P1.0 (I/O)

0

1

UCA1CLK

TA1.CCI0A

TA1.0

X⁽⁴⁾

P1.0/UCA1CLK/TA1.0/A0/

C0/VREF-/VeREF-

4

3

4

0

1

0

1

A0, C0, VREF-, VeREF-^{(2) (3)}

X

1

0

1

0

1

0 = Input,

1 = Output

P1.1 (I/O)

UCA1STE

X⁽⁴⁾

P1.1/UCA1STE/TA4.0/A1/

C1/VREF+/VeREF+

5

TA4.CCI0A

0

1

0

1

TA4.0

1

A1, C1, VREF+, VeREF+^{(2) (3)}

X

(1) X = Don't care

(2) Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

(3) Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents

when applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator

module automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.

(4) Direction is controlled by the eUSCI_A1 module.

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9.14.3 Port P1 (P1.2 to P1.5) Input/Output With Schmitt Trigger

图9-4 shows the port diagram. 表9-26 summarizes the selection of the pin function.

Pad Logic

To ADC

From ADC

To Comparator

From Comparator

CBPD.x

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

Module 1 or PxDIR.x

Module 2 or PxDIR.x

Module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

Module 1 or DVSS

Module 2 or DVSS

Module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-4. Port P1 (P1.2 to P1.5) Diagram

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表9-26. Port P1 (P1.2 to P1.5) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PM

PIN NAME (P1.x)

PN 80

FUNCTION

RGC 64

P1DIR.x

P1SEL1.x

P1SEL0.x

0 = Input,

1 = Output

P1.2 (I/O)

0

1

UCA1SIMO/UCA1TXD

X⁽³⁾

P1.2/UCA1SIMO/

UCA1TXD/TA1.0/A8/C8

25

19

20

25

26

N/A

0

1

0

TA1.0

1

A8, C8^{(4) (5)}

X

1

0

1

0

1

0 = Input,

1 = Output

P1.3 (I/O)

UCA1SOMI/UCA1RXD

X⁽³⁾

P1.3/UCA1SOMI/

UCA1RXD/TA1.1/A9/C9

26

31

32

N/A

0

1

0

TA1.1

1

A9, C9^{(4) (5)}

X

1

0

1

0

0 = Input,

1 = Output

P1.4 (I/O)

TB0.CCI4A

TB0.4

0

1

P1.4/TB0.4/UCB0STE/

A2/C2

0

1

UCB0STE

A2, C2^{(4) (5)}

X⁽²⁾

1

0

1

X

0 = Input,

1 = Output

P1.5(I/O)

0

1

TB0.CCI5A

TB0.5

0

1

P1.5/TB0.5/UCB0CLK/

A3/C3

UCB0CLK

A3, C3^{(4) (5)}

X⁽²⁾

1

0

1

X

(1) X = Don't care

(2) Direction is controlled by the eUSCI_B0 module.

(3) Direction is controlled by the eUSCI_A1 module.

(4) Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

(5) Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents

when applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator

module automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.

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9.14.4 Port P1 (P1.6 to P1.7) Input/Output With Schmitt Trigger

图9-5 shows the port diagram. 表9-27 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

Module 1 or PxDIR.x

Module 2 or PxDIR.x

Module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

Module 1 or DVSS

Module 2 or DVSS

Module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-5. Port P1 (P1.6 to P1.7) Diagram

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表9-27. Port P1 (P1.6 to P1.7) Pin Functions

PM

RGC

64

CONTROL BITS OR SIGNALS ⁽¹⁾

PIN NAME (P1.x)

PN 80

FUNCTION

P1DIR.x

P1SEL1.x

P1SEL0.x

LCDSz

0 = Input,

1 = Output

P1.6(I/O)

0

UCA3STE

X⁽³⁾

X⁽²⁾

0

1

0

P1.6/UCA3STE/

UCB0SIMO/UCB0SDA/

LCDS17

UCB0SIMO/UCB0SDA

29

23

N/A

1

0

Internally tied to DVSS

Sz ⁽⁴⁾

1

X

0

X

0

1

0

0 = Input,

1 = Output

P1.7(I/O)

X

1

0

1

X

1

0

USSTRG (independent function)

0

X

P1.7/USSTRG/

UCA3CLK/UCB0SOMI/

UCB0SCL/LCDS16

UCA3CLK

X⁽³⁾

X⁽²⁾

0

30

24

UCB0SOMI/UCB0SCL

N/A

1

0

1

Internally tied to DVSS

Sz ⁽⁴⁾

1

X

(1) X = Don't care

(2) Direction is controlled by the eUSCI_B0 module.

(3) Direction is controlled by the eUSCI_A3 module.

(4) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节7.

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9.14.5 Port P2 (P2.0 to P2.1) Input/Output With Schmitt Trigger

图9-6 shows the port diagram. 表9-28 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

Module 1 or PxDIR.x

Module 2 or PxDIR.x

Module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

Module 1 or DVSS

Module 2 or DVSS

Module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-6. Port P2 (P2.0 to P2.1) Diagram

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表9-28. Port P2 (P2.0 to P2.1) Pin Functions

PM

RGC

64

CONTROL BITS OR SIGNALS ⁽¹⁾

PIN NAME (P2.x)

PN 80

FUNCTION

P2DIR.x

P2SEL1.x

P2SEL0.x

LCDSz

0 = Input,

1 = Output

P2.0(I/O)

0

UCA1CLK

X⁽²⁾

X⁽³⁾

0

1

0

P2.0/UCA1CLK/

UCA3SIMO/UCA3TXD/

LCDS19

UCA3SIMO/UCA3TXD

27

21

N/A

1

0

Internally tied to DVSS

Sz ⁽⁴⁾

1

X

0

X

0

1

0

0 = Input,

1 = Output

P2.1(I/O)

UCA1STE

X⁽²⁾

X⁽³⁾

0

1

0

P2.1/UCA1STE/

UCA3SOMI/UCA3RXD/

LCDS18

UCA3SOMI/UCA3RXD

N/A

30

24

1

0

1

Internally tied to DVSS

Sz ⁽⁴⁾

1

X

(1) X = Don't care

(2) Direction is controlled by the eUSCI_A1 module.

(3) Direction is controlled by the eUSCI_A3 module.

(4) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节7.

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9.14.6 Port P2 (P2.2 to P2.3) Input/Output With Schmitt Trigger

图9-7 shows the port diagram. 表9-29 summarizes the selection of the pin function.

Pad Logic

To ADC

From ADC

To Comparator

From Comparator

CBPD.x

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

Module 1 or PxDIR.x

Module 2 or PxDIR.x

Module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

Module 1 or DVSS

Module 2 or DVSS

Module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-7. Port P2 (P2.2 to P2.3) Diagram

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表9-29. Port P2 (P2.2 to P2.3) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PM RGC

64

PIN NAME (P2.x)

PN 80

FUNCTION

P2DIR.x

P2SEL1.x

P2SEL0.x

0 = Input,

1 = Output

P2.2 (I/O)

0

N/A

0

1

P2.2/COUT/UCA0CLK/

A14/C14

0

1

2

COUT

UCA0CLK

A14, C14^{(3) (4)}

X⁽²⁾

1

0

1

X

0 = Input,

1 = Output

P2.3(I/O)

0

1

TA0.CCI0A

TA0.0

0

1

P2.3/TA0.0/UCA0STE/

A15/C15

3

--

UCA0STE

A15, C15^{(3) (4)}

X⁽²⁾

1

0

1

X

(1) X = Don't care

(2) Direction is controlled by the eUSCI_A0 module.

(3) Setting P2SEL1.x and P2SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

(4) Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents

when applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator

module automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.

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9.14.7 Port P2 (P2.4 to P2.5) Input/Output With Schmitt Trigger

图9-8 shows the port diagram. 表9-30 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

Module 1 or PxDIR.x

Module 2 or PxDIR.x

Module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

Module 1 or DVSS

Module 2 or DVSS

Module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-8. Port P2 (P2.4 to P2.5) Diagram

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表9-30. Port P2 (P2.4 to P2.5) Pin Functions

CONTROL BITS OR SIGNALS ⁽¹⁾

PM

RGC 64

PIN NAME (P2.x)

PN 80

FUNCTION

P2DIR.x

P2SEL1.x

P2SEL0.x

LCDSz

0 = Input,

1 = Output

P2.4 (I/O)

TA0CLK

0

1

0

1

0

1

X

0

1

0

1

0

Internally tied to DVSS

TB0CLK

P2.4/TA0CLK/TB0CLK/

TA1CLK/LCDS24

12

--

Internally tied to DVSS

TA1CLK

Internally tied to DVSS

Sz ⁽²⁾

X

0

X

0

1

0

0 = Input,

1 = Output

P2.5 (I/O)

N/A

0

1

0

1

0

1

X

0

1

0

TA0.2

TA4.CCI0B

P2.5/TA0.2/TA4.0/ LCDS21

23

--

TA4.0

N/A

1

0

1

Internally tied to DVSS

Sz ⁽²⁾

X

(1) X = Don't care

(2) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节7.

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9.14.8 Port P2 (P2.6 to P2.7) Input/Output With Schmitt Trigger

图9-9 shows the port diagram. 表9-31 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

Module 1 or PxDIR.x

DVSS

DVCC

0

1

Module 2 or PxDIR.x

Comparator COUT

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

Module 1 or DVSS

Module 2 or DVSS

Module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-9. Port P2 (P2.6 to P2.7) Diagram

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表9-31. Port P2 (P2.6 to P2.7) Pin Functions

CONTROL BITS OR SIGNALS ⁽¹⁾

PM

RGC 64

PIN NAME (P2.x)

PN 80

FUNCTION

P2DIR.x

P2SEL1.x

P2SEL0.x

LCDSz

0 = Input,

1 = Output

P2.6 (I/O)

0

1

0

UCA0SIMO/UCA0TXD

TA1.CCI2A

TA1.2

X⁽²⁾

P2.6/UCA0SIMO/

UCA0TXD/TA1.2/TA1.2C/

LCDS23

0

13

--

1

0

1

TA1.2C

X⁽³⁾

1

0

1

Sz ⁽⁴⁾

X

0 = Input,

1 = Output

P2.7 (I/O)

0

1

0

UCA0SOMI/UCA0RXD

TA4.CCI1B

TA4.1

X⁽²⁾

P2.7/UCA0SOMI/

UCA0RXD/TA4.1/TA4.1C/

LCDS22

0

14

--

1

0

1

TA4.1C

X⁽³⁾

1

0

1

Sz ⁽⁴⁾

X

(1) X = Don't care

(2) Direction is controlled by the eUSCI_A0 module.

(3) Direction / HiZ controlled by comparator output COUT.

(4) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节7.

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9.14.9 Port P3 (P3.0) Input/Output With Schmitt Trigger

图9-10 shows the port diagram. 表9-32 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

Module 1 or PxDIR.x

Module 2 or PxDIR.x

Module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

Module 1 or DVSS

Module 2 or DVSS

Module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-10. Port P3 (P3.0) Diagram

表9-32. Port P3 (P3.0) Pin Functions

CONTROL BITS OR SIGNALS ⁽¹⁾

PM

RGC 64

PIN NAME (P3.x)

PN 80

FUNCTION

P3DIR.x P3SEL1.x P3SEL0.x LCDSz

0 = Input,

1 = Output

P3.0 (I/O)

0

1

0

N/A

0

1

0

1

0

1

X

Internally tied to DVSS

TB0.CCI0A

P3.0/TB0.0/LCDS20

24

--

1

0

TB0.0

N/A

1

0

1

Internally tied to DVSS

Sz ⁽²⁾

X

(1) X = Don't care

(2) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节7.

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9.14.10 Port P3 (P3.1) Input/Output With Schmitt Trigger

图9-11 shows the port diagram. 表9-33 summarizes the selection of the pin function.

ACTIVATE

Pad Logic

1

0

MTIF_PIN_EN

TPOE

1

From MTIF

PxREN.x

0

1

0

0 0

0 1

1 0

1 1

PxDIR.x

DVSS

DVCC

0

1

Module 1 or PxDIR.x

Direction

0: Input

1: Output

1

Module 2 or PxDIR.x

Module 3 or PxDIR.x

1

0

1

0 0

0 1

1 0

1 1

PxOUT.x

Module 1 or DVSS

Module 2 or DVSS

Module 3 or DVSS

1

0

PxSEL1.x

PxSEL0.x

PxIN.x

EN

D

Bus

Keeper

To module

selector

To MTIF

TPIE

Functional representation only.

图9-11. Port P3 (P3.1) Diagram

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表9-33. Port P3 (P3.1) Pin Functions

CONTROL BITS OR SIGNALS ⁽¹⁾

PM

PN 80 RGC

64

PIN NAME

(P3.x)

Signal on

MTIF_PIN_E

N pin⁽³⁾

FUNCTION

P3SEL1. P3SEL0.

ACTIVATE

P3DIR.x

TPOE ⁽²⁾TPIE⁽²⁾

(2)

x

0 = Input,

1 = Outp

ut

P3.1 (I/O)

0

X

TA1CLK

0

1

0

1

0

1

0

X

Internally tied to

DVSS

TB0.CCI1A

TB0.1

0

1

0

P3.1/TA1CLK/

TB0.1/

MTIF_OUT_IN

33

27

N/A

Internally tied to

DVSS

1

MTIF_IN

X

0

1

X

0

X

MTIF_OUT⁽²⁾

X

Internally tied to

DVSS⁽²⁾

X

1

X

1

0

1

MTIF_OUT⁽²⁾

(1) X = Don't care

(2) See MTIF.TPCTL register

(3) When P3.1 pin is configured as MTIF_PIN_EN (see 节9.13.6 for details)

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9.14.11 Port P3 (P3.2) Input/Output With Schmitt Trigger

图9-12 shows the port diagram. 表9-34 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

COMx

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

module 1 or PxDIR.x

module 2 or PxDIR.x

module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-12. Port P3 (P3.2) Diagram

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表9-34. Port P3 (P3.2) Pin Functions

CONTROL BITS OR SIGNALS ⁽¹⁾

PM

PIN NAME (P3.x)

PN 80

FUNCTION

RGC 64

P3DIR.x

P3SEL1.x

P3SEL0.x

LCDSz

0 = Input,

1 = Output

P3.2 (I/O)

0

TA1.CCI1A

TA1.1

0

1

0

1

0

1

0

P3.2/TA1.1/COM5/

LCDS28

DMAE0

63

--

0

X

1

Internally tied to DVSS

COM5⁽²⁾

1

X

0

1

0

X

Sz ⁽³⁾

X

(1) X = Don't care

(2) Setting P6SEL1.x and P6SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

(3) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节7.

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9.14.12 Port P3 (P3.3) Input/Output With Schmitt Trigger

图9-13 shows the port diagram. 表9-35 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

From USS_A

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

Module 1 or PxDIR.x

Module 2 or PxDIR.x

Module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

Module 1 or DVSS

Module 2 or DVSS

Module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-13. Port P3 (P3.3) Diagram

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表9-35. Port P3 (P3.3) Pin Functions

CONTROL BITS OR SIGNALS ⁽¹⁾

PM

PIN NAME (P3.x)

PN 80

FUNCTION

RGC 64

P3DIR.x

P3SEL1.x

P3SEL0.x

LCDSz

0 = Input,

1 = Output

P3.4 (I/O)

0

N/A

0

1

0

1

0

MCLK

TB0.CCI3B

TB0.3

P3.3/MCLK/TB0.3/XPB1/

LCDS25

0

64

50

0

X

1

XPB1

X⁽²⁾

X

0

X

0

Sz ⁽³⁾

X

(1) X = Don't care

(2) XPB1 enable disables digital and LCD functions on this pin implicitly

(3) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节7.

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9.14.13 Port P3 (P3.4 to P3.5) Input/Output With Schmitt Trigger

图9-14 shows the port diagram. 表9-36 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

COMx

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

module 1 or PxDIR.x

module 2 or PxDIR.x

module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-14. Port P3 (P3.4 to P3.5) Diagram

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ZHCSJA6B –JANUARY 2019 –REVISED DECEMBER 2021

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表9-36. Port P3 (P3.4 to P3.5) Pin Functions

CONTROL BITS OR SIGNALS ⁽¹⁾

PM

RGC 64

PIN NAME (P3.x)

PN 80

FUNCTION

P3DIR.x

P3SEL1.x

P3SEL0.x

LCDSz

0 = Input,

1 = Output

P3.4 (I/O)

0

N/A

0

1

0

1

0

1

0

SMCLK

DMAE0

P3.4/SMCLK/DMAE0/

COM6/LCDS27

65

51

0

X

1

Internally tied to DVSS

COM6

1

X

0

1

0

X

Sz

X

0 = Input,

1 = Output

P3.5 (I/O)

0

1

0

N/A

0

1

0

1

X

ACLK

N/A

P3.5/ACLK/COUT/ COM3/

LCDS26

66

52

1

0

X

1

COUT

COM3

1

X

0

1

0

X

Sz ⁽²⁾

X

(1) X = Don't care

(2) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节7.

118

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9.14.14 Port P3 (P3.6 to P3.7) Input/Output With Schmitt Trigger

图9-15 shows the port diagram. 表9-37 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

Module 1 or PxDIR.x

Module 2 or PxDIR.x

Module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

Module 1 or DVSS

Module 2 or DVSS

Module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-15. Port P3 (P3.6 to P3.7) Diagram

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ZHCSJA6B –JANUARY 2019 –REVISED DECEMBER 2021

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表9-37. Port P3 (P3.6 to P3.7) Pin Functions

CONTROL BITS OR SIGNALS ⁽¹⁾

PM

RGC 64

PIN NAME (P3.x)

PN 80

FUNCTION

P3DIR.x

P3SEL1.x

P3SEL0.x

LCDSz

0 = Input,

1 = Output

P3.6 (I/O)

0

1

0

UCB1SIMO/UCB1SDA

TB0.CCI6B

TB0.6

X⁽²⁾

P3.6/UCB1SIMO/

0

1

0

1

0

UCB1SDA/TB0.6/

75

--

1

USSXT_BOUT/LCDS35

N/A

0

USSXT_BOUT

Sz ⁽³⁾

1

X

0

X

0

1

0

0 = Input,

1 = Output

P3.7 (I/O)

UCB1SOMI/UCB1SCL

TB0.CCI2A

X⁽²⁾

P3.7/UCB1SOMI/

UCB1SCL/TB0.2/

TB0OUTH/LCDS36

0

1

0

76

--

TB0.2

1

TB0OUTH

0

1

0

1

Internally tied to DVSS

Sz ⁽³⁾

1

X

(1) X = Don't care

(2) Direction is controlled by the eUSCI_B1 module.

(3) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节7.

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9.14.15 Port P4 (P4.0) Input/Output With Schmitt Trigger

图9-16 shows the port diagram. 表9-38 summarizes the selection of the pin function.

Pad Logic

ACTIVATE

0

1

0

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

Module 1 or PxDIR.x

Module 2 or PxDIR.x

Module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0

0 0

0 1

1 0

1 1

PxOUT.x

Module 1 or DVSS

Module 2 or DVSS

Module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

EN

D

Bus

Keeper

To module

selector

MTIF_PIN_EN

Functional representation only.

图9-16. Port P4 (P4.0) Diagram

表9-38. Port P4 (P4.0) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PM

PIN NAME (P4.x)

PN 80

FUNCTION

P4DIR.x

P4SEL1.x

P4SEL0.x ACTIVATE⁽²⁾

RGC 64

0 = Input,

1 = Output

P4.0(I/O)

0

1

0

N/A

0

1

0

1

0

1

X

0

1

Internally tied to DVSS

P4.0/RTCCLK/TA4.1/

MTIF_PIN_EN

N/A

34

28

0

RTCCLK

N/A

1

0

1

TA4.1

MTIF_PIN_EN

X

(1) X = Don't care

(2) See MTIF.TPCTL register

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9.14.16 Port P4 (P4.1 to P4.7) Input/Output With Schmitt Trigger

图9-17 shows the port diagram. 表9-39 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

Module 1 or PxDIR.x

Module 2 or PxDIR.x

Module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

Module 1 or DVSS

Module 2 or DVSS

Module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-17. Port P4 (P4.1 to P4.7) Diagram

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表9-39. Port P4 (P4.1 to P4.7) Pin Functions

CONTROL BITS OR SIGNALS ⁽¹⁾

PM

RGC 64

PIN NAME (P4.x)

PN 80

FUNCTION

P4DIR.x

P4SEL1.x

P4SEL0.x

LCDSz

0 = Input,

1 = Output

P4.1 (I/O)

0

1

0

UCA0CLK

TB0.CCI4B

TB0.4

X⁽²⁾

P4.1/UCA0CLK/TB0.4/

UCA3SOMI/UCA3RXD/

LCDS15

0

35

29

1

0

1

UCA3SOMI/UCA3RXD

Sz ⁽⁴⁾

X⁽³⁾

1

0

1

X

0 = Input,

1 = Output

P4.2 (I/O)

0

1

0

UCA0STE

TB0.CCI5B

TB0.5

X⁽²⁾

P4.2/UCA0STE/TB0.5/

UCA3SIMO/UCA3TXD/

LCDS14

0

36

30

1

0

1

UCA3SIMO/UCA3TXD

Sz ⁽⁴⁾

X⁽³⁾

1

0

1

X

0 = Input,

1 = Output

P4.3 (I/O)

0

1

0

UCA0SIMO/UCA0TXD

X⁽²⁾

N/A

0

P4.3/UCA0SIMO/

UCA0TXD/LCDS13

1

0

1

0

37

31

Internally tied to DVSS

1

N/A

0

Internally tied to DVSS

Sz ⁽⁴⁾

1

X

0

X

0

1

0

0 = Input,

1 = Output

P4.4 (I/O)

UCA0SOMI/UCA0RXD

X⁽²⁾

N/A

0

P4.4/UCA0SOMI/

UCA0RXD/LCDS12

1

0

1

0

38

32

Internally tied to DVSS

1

N/A

0

Internally tied to DVSS

Sz ⁽⁴⁾

1

X

0

X

0

1

0

0 = Input,

1 = Output

P4.5 (I/O)

TA0CLK

0

1

0

1

0

1

X

0

1

0

Internally tied to DVSS

TA1CLK

P4.5/TA0LCK/TA1CLK/

LCDS11

39

--

Internally tied to DVSS

N/A

1

0

1

Internally tied to DVSS

Sz ⁽⁴⁾

X

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表9-39. Port P4 (P4.1 to P4.7) Pin Functions (continued)

CONTROL BITS OR SIGNALS ⁽¹⁾

PM

RGC 64

PIN NAME (P4.x)

PN 80

FUNCTION

P4DIR.x

P4SEL1.x

P4SEL0.x

LCDSz

0 = Input,

1 = Output

P4.6 (I/O)

TB0CLK

0

1

0

1

0

1

X

0

1

0

1

0

Internally tied to DVSS

TA4CLK

P4.6/TB0CLK/TA4CLK/

LCDS10

40

--

Internally tied to DVSS

N/A

Internally tied to DVSS

Sz ⁽⁴⁾

X

0

X

0

1

0

0 = Input,

1 = Output

P4.7 (I/O)

N/A

0

1

0

1

0

1

X

0

1

0

Internally tied to DVSS

DMAE0

P4.7/DMAE0/LCDS9

42

--

Internally tied to DVSS

N/A

1

0

1

Internally tied to DVSS

Sz ⁽⁴⁾

X

(1) X = Don't care

(2) Direction is controlled by the eUSCI_A0 module.

(3) Direction is controlled by the eUSCI_A3 module.

(4) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节7.

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9.14.17 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger

图9-18 shows the port diagram. 表9-40 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

Module 1 or PxDIR.x

Module 2 or PxDIR.x

Module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

Module 1 or DVSS

Module 2 or DVSS

Module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-18. Port P5 (P5.0 to P5.7) Diagram

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表9-40. Port P5 (P5.0 to P5.7) Pin Functions

CONTROL BITS OR SIGNALS ⁽¹⁾

PM

RGC 64

PIN NAME (P5.x)

PN 80

FUNCTION

P5DIR.x

P5SEL1.x

P5SEL0.x

LCDSz

0 = Input,

1 = Output

P5.0 (I/O)

0

TB0.CCI0B

TB0.0

0

1

0

1

0

1

0

P5.0/TB0.0/UCA2SIMO/

UCA2TXD/LCDS8

43

34

35

36

37

38

UCA2SIMO/UCA2TXD

X⁽²⁾

N/A

0

Internally tied to DVSS

Sz ⁽³⁾

1

X

0

X

0

1

0

0 = Input,

1 = Output

P5.1 (I/O)

N/A

0

1

0

1

0

1

0

TB0.1

P5.1/TB0.1/UCA2SOMI/

UCA2RXD/LCDS7

44

45

46

47

UCA2SOMI/UCA2RXD

X⁽²⁾

N/A

0

Internally tied to DVSS

Sz ⁽³⁾

1

X

0

X

0

1

0

0 = Input,

1 = Output

P5.2 (I/O)

N/A

0

1

0

1

0

TB0.2

1

P5.2/TB0.2/UCA2CLK/

LCDS6

UCA2CLK

X⁽²⁾

0

N/A

Internally tied to DVSS

Sz ⁽³⁾

1

X

0

X

0

1

0

0 = Input,

1 = Output

P5.3 (I/O)

TB0.CCI3A

TB0.3

0

1

0

1

0

1

P5.3/TB0.3/UCA2STE/

LCDS5

UCA2STE

N/A

X⁽²⁾

0

Internally tied to DVSS

Sz ⁽³⁾

1

X

0

X

0

1

0

0 = Input,

1 = Output

P5.4 (I/O)

TA0.CCI0B

TA0.0

0

1

X

1

0

1

X

0

1

P5.4/TA0.0/UCB1CLK/

TA4.0/LCDS4

UCB1CLK

N/A

X⁽⁴⁾

0

TA4.0

1

Sz ⁽³⁾

X

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ZHCSJA6B –JANUARY 2019 –REVISED DECEMBER 2021

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表9-40. Port P5 (P5.0 to P5.7) Pin Functions (continued)

CONTROL BITS OR SIGNALS ⁽¹⁾

PM

RGC 64

PIN NAME (P5.x)

PN 80

FUNCTION

P5DIR.x

P5SEL1.x

P5SEL0.x

LCDSz

0 = Input,

1 = Output

P5.5 (I/O)

0

TA4.CCI1A

TA4.1

0

1

0

1

0

1

0

P5.5/TA4.1/UCB1SIMO/

UCB1SDA/LCDS3

48

39

40

--

UCB1SIMO/UCB1SDA

X⁽⁴⁾

N/A

0

Internally tied to DVSS

Sz ⁽³⁾

1

X

0

X

0

1

0

0 = Input,

1 = Output

P5.6 (I/O)

TB0OUTH

0

1

0

1

0

1

0

P5.6/TB0OUTH/

UCB1SOMI/UCB1SCL/

LCDS2

Internally tied to DVSS

UCB1SOMI/UCB1SCL

N/A

49

X⁽⁴⁾

0

Internally tied to DVSS

Sz ⁽³⁾

1

X

0

X

0

1

0

0 = Input,

1 = Output

P5.7 (I/O)

TA0.CCI2A

TA0.2

0

1

X

1

0

1

X

0

1

P5.7/TA0.2/UCB1STE/

LCDS1

42

UCB1STE

N/A

X⁽⁴⁾

0

Internally tied to DVSS

Sz ⁽³⁾

1

X

(1) X = Don't care

(2) Direction is controlled by the eUSCI_A2 module.

(3) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节7.

(4) Direction is controlled by the eUSCI_B1 module.

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9.14.18 Port P6 (P6.0) Input/Output With Schmitt Trigger

图9-19 shows the port diagram. 表9-41 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

module 1 or PxDIR.x

module 2 or PxDIR.x

module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To modules

Functional representation only.

图9-19. Port P6 (P6.0) Diagram

表9-41. Port P6 (P6.0) Pin Functions

CONTROL BITS OR SIGNALS ⁽¹⁾

PM

PIN NAME (P6.x)

PN 80

FUNCTION

RGC 64

P6DIR.x

P6SEL1.x

P6SEL0.x

LCDSz

0 = Input,

1 = Output

P6.0 (I/O)

0

TA0CLK

0

1

0

1

0

1

X

0

1

0

Internally tied to DVSS

P6.0/TA0CLK/COUT/

LCDS0

N/A

51

41

COUT

N/A

1

0

1

Internally tied to DVSS

Sz ⁽²⁾

X

(1) X = Don't care

(2) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节7.

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ZHCSJA6B –JANUARY 2019 –REVISED DECEMBER 2021

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9.14.19 Port P6 (P6.1 to P6.2) Input/Output With Schmitt Trigger

图9-20 shows the port diagram. 表9-42 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

To/From LCD

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

Module 1 or PxDIR.x

Module 2 or PxDIR.x

Module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

Module 1 or DVSS

Module 2 or DVSS

Module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-20. Port P6 (P6.1 to P6.2) Diagram

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ZHCSJA6B –JANUARY 2019 –REVISED DECEMBER 2021

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表9-42. Port P6 (P6.1 to P6.2) Pin Functions

CONTROL BITS OR SIGNALS⁽¹⁾

PM

RGC 64

PIN NAME (P6.x)

PN 80

FUNCTION

P6DIR.x

P6SEL1.x

P6SEL0.x

LCDSz

0 = Input,

1 = Output

P6.1 (I/O)

0

N/A

0

1

0

1

X

0

1

0

RTCCLK

N/A

P6.1/RTCCLK/R03/

LCDS33

56

--

0

X

1

Internally tied to DVSS

R03 ⁽²⁾

1

X

0

1

0

X

Sz ⁽³⁾

X

0 = Input,

1 = Output

P6.2 (I/O)

0

1

0

TB0CLK

0

1

0

1

X

Internally tied to DVSS

N/A

P6.2/TB0CLK/R13/

LCDREF/LCDS32

57

47

1

0

X

1

Internally tied to DVSS

R13/LCDREF ⁽²⁾

1

X

0

1

0

X

Sz ⁽³⁾

X

(1) X = Don't care

(2) Setting P6SEL1.x and P6SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

(3) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节7.

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9.14.20 Port P6 (P6.3) Input/Output With Schmitt Trigger

图9-21 shows the port diagram. 表9-43 summarizes the selection of the pin function.

Pad Logic

R23

COMx

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

Module 1 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

DVSS

0 0

0 1

1 0

1 1

PxOUT.x

Module 1 or DVSS

DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-21. Port P6 (P6.3) Diagram

表9-43. Port P6 (P6.3) Pin Functions

CONTROL BITS OR SIGNALS ⁽¹⁾

PM

PIN NAME (P6.x)

PN 80

FUNCTION

RGC 64

P6DIR.x

P6SEL1.x

P6SEL0.x

0 = Input,

1 = Output

P6.3 (I/O)

0

N/A

0

1

0

1

P6.3/COM7/R23

60

--

Internally tied to DVSS

COM7⁽²⁾

X

1

0

1

R23⁽²⁾

(1) X = Don't care

(2) Setting P6SEL1.x and P6SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

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9.14.21 Port P6 (P6.4) Input/Output With Schmitt Trigger

图9-22 shows the port diagram. 表9-44 summarizes the selection of the pin function.

Pad Logic

To/From LCD

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

Module 1 or PxDIR.x

Module 2 or PxDIR.x

Module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

Module 1 or DVSS

Module 2 or DVSS

Module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-22. Port P6 (P6.4) Diagram

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表9-44. Port P6 (P6.4) Pin Functions

CONTROL BITS OR SIGNALS ⁽¹⁾

PM RGC

64

PIN NAME (P6.x)

PN 80

FUNCTION

P6DIR.x

P6SEL1.x

P6SEL0.x

0 = Input,

1 = Output

P6.4 (I/O)

0

1

N/A

0

1

0

1

X

0

MCLK

N/A

P6.4/MCLK/COM0

(1) X = Don't care

52

43

1

0

1

Internally tied to DVSS

COM0 ⁽²⁾

(2) Setting P6SEL1.x = P6SEL0.x = 1 disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

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9.14.22 Port P6 (P6.5 and P6.7) Input/Output With Schmitt Trigger

图9-23 shows the port diagram. 表9-45 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

COMx

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

module 1 or PxDIR.x

module 2 or PxDIR.x

module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

module 1 or DVSS

module 2 or DVSS

module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-23. Port P6 (P6.5 and P6.7) Diagram

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表9-45. Port P6 (P6.5 to P6.7) Pin Functions

CONTROL BITS OR SIGNALS ⁽¹⁾

PM

RGC 64

PIN NAME (P6.x)

PN 80

FUNCTION

P6DIR.x

P6SEL1.x

P6SEL0.x

LCDSz

0 = Input,

1 = Output

P6.5(I/O)

0

N/A

0

1

0

1

X

0

1

0

SMCLK

N/A

P6.5/SMCLK/COM1/

LCDS34

53

44

45

--

0

X

1

Internally tied to DVSS

COM1⁽²⁾

1

X

0

1

0

X

Sz ⁽³⁾

X

0 = Input,

1 = Output

P6.6(I/O)

0

1

0

N/A

0

1

0

1

X

ACLK

P6.6/ACLK/COM2/

LCDS31

N/A

54

1

0

X

1

Internally tied to DVSS

COM2⁽²⁾

1

X

0

1

0

X

Sz ⁽³⁾

X

0 = Input,

1 = Output

P6.7(I/O)

0

1

0

TA0.CCI1A

TA0.1

0

1

0

1

X

P6.7/TA0.1/COM4/

LCDS29

N/A

62

1

0

X

1

Internally tied to DVSS

COM4⁽²⁾

1

X

0

1

0

X

Sz ⁽³⁾

X

(1) X = Don't care

(2) Setting P6SEL1.x and P6SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

(3) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节7.

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9.14.23 Port P7 (P7.0) Input/Output With Schmitt Trigger

图9-24 shows the port diagram. 表9-46 summarizes the selection of the pin function.

Pad Logic

Sz

LCDSz

From USS_A

PxREN.x

0 0

0 1

1 0

1 1

PxDIR.x

Module 1 or PxDIR.x

Module 2 or PxDIR.x

Module 3 or PxDIR.x

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PxOUT.x

Module 1 or DVSS

Module 2 or DVSS

Module 3 or DVSS

PxSEL1.x

PxSEL0.x

PxIN.x

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-24. Port P7 (P7.0) Diagram

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表9-46. Port P7 (P7.0) Pin Functions

CONTROL BITS OR SIGNALS ⁽¹⁾

PM

PIN NAME (P7.x)

PN 80

FUNCTION

RGC 64

P7DIR.x

P7SEL1.x

P7EL0.x

LCDSz

0 = Input,

1 = Output

P7.0 (I/O)

0

TA1.CCI0B

TA1.0

0

1

0

1

0

P7.0/TA1.0./TA1.2/XPB0/

LCDS30

N/A

0

55

46

TA1.2

1

XPB0

X⁽²⁾

X

0

X

0

X

1

Sz ⁽³⁾

X

(1) X = Don't care

(2) Enabling XPB0 implicitly disables digital and LCD functions on this pin.

(3) Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in 节7.

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9.14.24 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger

图9-25 shows the port diagram. 表9-47 summarizes the selection of the pin function.

To Comparator

From Comparator

Pad Logic

CBPD.x

JTAG enable

From JTAG

PJREN.x

0 0

0 1

1 0

1 1

PJDIR.x

Module 1 or PxDIR.x

Module 2 or PxDIR.x

Module 3 or PxDIR.x

1

0

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PJOUT.x

1

0

Module 1 or DVSS

Module 2 or DVSS

Module 3 or DVSS

PJSEL1.x

PJSEL0.x

PJIN.x

Bus

Keeper

EN

D

To module

selector

and JTAG

Functional representation only.

图9-25. Port PJ (PJ.0 to PJ.3) Diagram

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表9-47. Port PJ (PJ.0 to PJ.3) Pin Functions

CONTROL BITS/ SIGNALS⁽¹⁾

PM

RGC 64

PIN NAME (PJ.x)

PN 80

FUNCTION

CEPDx

(Cx)

PJDIR.x

PJSEL1.x

PJSEL0.x

0 = Input,

1 = Output

PJ.0 (I/O)⁽²⁾

0

TDO⁽³⁾

UCA2CLK

N/A

X

X⁽⁶⁾

0

X

0

X

1

0

PJ.0/TDO/UCA2CLK/

SRSCG1/DMAE0/C10

17

13

14

15

16

1

0

1

0

CPU Status Register Bit SCG1

DMAE0

1

0

Internally tied to DVSS

C10⁽⁴⁾

1

X

0

X

0

1

0

0 = Input,

1 = Output

PJ.1 (I/O)⁽²⁾

TDI/TCLK^{(3) (5)}

X

X⁽⁶⁾

0

X

0

X

1

0

UCA2STE

PJ.1/TDI/TCLK/ UCA2STE/

SRSCG0/ TA4CLK/C11

N/A

18

19

20

1

0

1

0

CPU Status Register Bit SCG0

TA4CLK

1

0

Internally tied to DVSS

C11⁽⁴⁾

1

X

0

X

0

1

0

0 = Input,

1 = Output

PJ.2 (I/O)⁽²⁾

TMS^{(3) (5)}

X

X⁽⁶⁾

0

X

0

X

1

0

UCA2SIMO/UCA2TXD

N/A

PJ.2/TMS/UCA2SIMO/

UCA2TXD/SROSCOFF/

TB0OUTH/C12

1

0

1

0

CPU Status Register Bit OSCOFF

TB0OUTH

1

0

Internally tied to DVSS

C12⁽⁴⁾

1

X

0

X

0

1

0

0 = Input,

1 = Output

PJ.3 (I/O)⁽²⁾

TCK^{(3) (5)}

X

X⁽⁶⁾

0

X

0

X

1

0

UCA2SOMI/UCA2RXD

PJ.3/TCK/UCA2SOMI/

UCA2RXD/SRCPUOFF/

TB0.6/C13

N/A

1

0

CPU Status Register Bit CPUOFF

1

TB0.CCI6A

0

1

0

1

TB0.6

1

C13⁽⁴⁾

X

(1) X = Don't care

(2) Default condition

(3) The pin direction is controlled by the JTAG module. JTAG mode selection is made through the SYS module or by the Spy-Bi-Wire four-

wire entry sequence. Neither PJSEL1.x and PJSEL0.x nor CEPDx bits have an effect in these cases.

(4) Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents

when applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator

module automatically disables The output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.

(5) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.

(6) Direction is controlled by the eUSCI_A2 module.

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9.14.25 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger

图9-26 and 图9-27 show the port diagrams. 表9-48 summarizes the selection of the pin function.

Pad Logic

To LFXT XIN

PJREN.4

0 0

0 1

1 0

1 1

PJDIR.4

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PJOUT.4

DVSS

PJ.4/LFXIN

PJSEL1.4

PJSEL0.4

PJIN.4

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-26. Port PJ (PJ.4) Diagram

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Pad Logic

To LFXT XOUT

PJSEL0.4

PJSEL1.4

LFXTBYPASS

PJREN.5

0 0

0 1

1 0

1 1

PJDIR.5

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PJOUT.5

DVSS

PJ.5/LFXOUT

PJSEL1.5

PJSEL0.5

PJIN.5

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-27. Port PJ (PJ.5) Diagram

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LFXTBYPA

表9-48. Port PJ (PJ.4 and PJ.5) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PM RGC

64

PIN NAME (PJ.x)

PN 80

FUNCTION

PJDIR.x

PJSEL1.5

PJSEL0.5

PJSEL1.4

PJSEL0.4

SS

0 = Input,

1 = Output

PJ.4 (I/O)

N/A

X

0

X

0

1

X

1

X

PJ.4/LFXIN

7

6

Internally tied to DVSS

LFXIN crystal mode⁽²⁾

LFXIN bypass mode⁽²⁾

X

0

1

X

0

1

X

0

1

X

0

1

0

1

0

1⁽³⁾

0

0 = Input,

1 = Output

PJ.5 (I/O)

N/A

0

X

0

see⁽⁴⁾

X

0

PJ.5/LFXOUT

8

7

1⁽³⁾

0

Internally tied to DVSS

LFXOUT crystal mode⁽²⁾

1

see⁽⁴⁾

X

1

1⁽³⁾

0

X

(1) X = Don't care

(2) If PJSEL1.4 = 0 and PJSEL0.4 = 1, the general-purpose I/O is disabled. When LFXTBYPASS = 0, PJ.4 and PJ.5 are configured for

crystal operation and PJSEL1.5 and PJSEL0.5 are don't care. When LFXTBYPASS = 1, PJ.4 is configured for bypass operation and

PJ.5 is configured as general-purpose I/O.

(3) When PJ.4 is configured in bypass mode, PJ.5 is configured as general-purpose I/O.

(4) If PJSEL0.5 = 1 or PJSEL1.5 = 1, the general-purpose I/O functionality is disabled. No input function is available. Configured as output,

the pin is actively pulled to zero.

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9.14.26 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger

图9-28 and 图9-29 show the port diagrams. 表9-49 summarizes the selection of the pin function.

Pad Logic

To HFXT XIN

PJREN.6

0 0

0 1

1 0

1 1

PJDIR.6

Direction

0: Input

1: Output

DVSS

DVCC

0

1

0 0

0 1

1 0

1 1

PJOUT.6

DVSS

USSXT_BOUT

PJ.6/HFXIN

PJSEL1.6

PJSEL0.6

PJIN.6

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-28. Port PJ (PJ.6) Diagram

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Pad Logic

To HFXT XOUT

PJSEL0.6

PJSEL1.6

HFXTBYPASS

PJREN.7

0 0

0 1

1 0

1 1

PJDIR.7

DVSS

DVCC

0

1

Direction

0: Input

1: Output

1

0 0

0 1

1 0

1 1

PJOUT.7

DVSS

PJ.7/HFXOUT

PJSEL1.7

PJSEL0.7

PJIN.7

Bus

Keeper

EN

D

To module

selector

Functional representation only.

图9-29. Port PJ (PJ.7) Diagram

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PIN NAME (PJ.x)

表9-49. Port PJ (PJ.6 and PJ.7) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PM RGC

64

PN 80

FUNCTION

HFXTBYPA

SS

PJDIR.x

PJSEL1.7

PJSEL0.7

PJSEL1.6

PJSEL0.6

0 = Input,

1 = Output

PJ.6 (I/O)

X

0

X

HFXIN crystal mode⁽²⁾

HFXIN bypass mode⁽²⁾

N/A

X

0

1

X

0

1

0

1

PJ.6/HFXIN/

USSXT_BOUT

10

9

X

1

0

1

X

Internally tied to DVSS

N/A

USSXT_BOUT ⁽³⁾

0

1

X

0

1

X

0

1

X

0

X

0

1⁽⁵⁾

0

0 = Input,

1 = Output

PJ.7 (I/O)⁽⁴⁾

0

N/A

0

see ⁽⁴⁾

X

0

PJ.7/HFXOUT

11

10

1⁽⁵⁾

0

Internally tied to DVSS

HFXOUT crystal mode⁽²⁾

1

see ⁽⁴⁾

X

1

1⁽⁵⁾

0

X

(1) X = Don't care

(2) Setting PJSEL1.6 = 0 and PJSEL0.6 = 1 causes the general-purpose I/O to be disabled. When HFXTBYPASS = 0, PJ.6 and PJ.7 are

configured for crystal operation and PJSEL1.7 and PJSEL0.7 are do not care. When HFXTBYPASS = 1, PJ.6 is configured for bypass

operation and PJ.7 is configured as general-purpose I/O.

(3) HFXT is connected to USSXT_BOUT ; USSXT and HFXT operate at same frequency bur without phase control; PJ.6 acts as output.

(4) With PJSEL0.7 = 1 or PJSEL1.7 =1 the general-purpose I/O functionality is disabled. No input function is available. Configured as

output the pin is actively pulled to zero.

(5) When PJ.6 is configured in bypass mode, PJ.7 is configured as general-purpose I/O.

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9.15 Device Descriptors (TLV)

表9-50 lists the Device IDs. 表9-51 lists the contents of the device descriptor tag-length-value (TLV) structure.

表9-50. Device IDs

DEVICE ID

DEVICE

PACKAGE

01A05h

83h

01A04h

12h

MSP430FR6043

MSP430FR60431

MSP430FR6041

PN

83h

1Ah

14h

PN

83h

PM

83h

17h

MSP430FR5043

MSP430FR50431

MSP430FR5041

RGC

PM

83h

17h

83h

0Fh

18h

RGC

PM

83h

RGC

83h

18h

表9-51. Device Descriptor Table

VALUE⁽¹⁾

DESCRIPTION

ADDRESS

FR604x

(UART BSL)

FR60431

(I²C BSL)

FR504x

(UART BSL)

FR50431

(I²C BSL)

Info Length

CRC Length

01A00h

01A01h

01A02h

01A03h

01A04h

01A05h

01A06h

01A07h

01A08h

01A09h

01A0Ah

01A0Bh

01A0Ch

01A0Dh

01A0Eh

01A0Fh

01A10h

01A11h

01A12h

01A13h

06h

Per unit

CRC Value

Device ID

Info Block

See 表9-50.

Hardware Revision

Firmware Revision

Die Record Tag

Per unit

08h

Per unit

08h

Per unit

08h

Per unit

08h

Die Record length

0Ah

Per unit

Lot/Wafer ID

Die Record

Die X Position

Die Y Position

Test Results

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表9-51. Device Descriptor Table (continued)

VALUE⁽¹⁾

DESCRIPTION

ADDRESS

FR604x

(UART BSL)

FR60431

FR504x

(UART BSL)

FR50431

(I²C BSL)

ADC12 Calibration Tag

01A14h

01A15h

01A16h

01A17h

01A18h

01A19h

01A1Ah

01A1Bh

01A1Ch

01A1Dh

01A1Eh

01A1Fh

01A20h

01A21h

01A22h

01A23h

01A24h

01A25h

01A26h

01A27h

01A28h

01A29h

01A2Ah

01A2Bh

01A2Ch

01A2Dh

01A2Eh

01A2Fh

01A30h

01A31h

01A32h

01A33h

01A34h

01A35h

01A36h

01A37h

01A38h

01A39h

01A3Ah

01A3Bh

01A3Ch

01A3Dh

01A3Eh

01A3Fh

11h

ADC12 Calibration Length

10h

Per unit

12h

Per unit

12h

Per unit

12h

Per unit

12h

ADC Gain Factor⁽²⁾

ADC Offset⁽³⁾

ADC 1.2-V Reference

Temperature Sensor 30°C

ADC12

Calibration

ADC 1.2-V Reference

Temperature Sensor 85°C

ADC 2.0-V Reference

Temperature Sensor 30°C

ADC 2.0-V Reference

Temperature Sensor 85°C

ADC 2.5-V Reference

Temperature Sensor 30°C

ADC 2.5-V Reference

Temperature Sensor 85°C

REF Calibration Tag

REF Calibration Length

06h

Per unit

15h

Per unit

15h

Per unit

15h

Per unit

15h

REF 1.2-V Reference

REF 2.0-V Reference

REF 2.5-V Reference

REF Calibration

128-Bit Random Number Tag

Random Number Length

10h

Per unit

Random

Number

128-Bit Random Number⁽⁴⁾

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表9-51. Device Descriptor Table (continued)

VALUE⁽¹⁾

DESCRIPTION

ADDRESS

FR604x

(UART BSL)

FR60431

FR504x

(UART BSL)

FR50431

(I²C BSL)

BSL Tag

01A40h

01A41h

01A42h

01A43h

1Ch

02h

00h

1Ch

02h

00h

1Ch

02h

01h

48h

BSL Length

02h

BSL

Configuration

BSL Interface

01h

BSL Interface Configuration

48h

(1) N/A = Not applicable, Per unit = content can differ from device to device

(2) ADC Gain: the gain correction factor is measured at room temperature using a 2.5-V external voltage reference without internal buffer

(ADC12VRSEL = 0x2, 0x4, or 0xE). Other settings (for example, using internal reference) can result in different correction factors.

(3) ADC Offset: the offset correction factor is measured at room temperature using ADC12VRSEL = 0x2 or 0x4, an external reference, V_R+

= external 2.5 V, V_R-= AVSS.

(4) 128-Bit Random Number: The random number is generated during production test using the Microsoft^®CryptGenRandom() function.

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9.16 Memory Map

表9-52 summarizes the memory map for all device variants.

表9-52. Memory Organization⁽¹⁾

MSP430FR5043(1),

MSP430FR5041, MSP430FR6041

MSP430FR6043(1)

Memory (FRAM)

Total Size

Size

64KB

32KB

Main: code memory

015FFFh to 006000h

00FFFFh to 00FF80h

8KB

00FFFFh to 008000h

00FFFFh to 00FF80h

8KB

Main: interrupt vectors and signatures

RAM (Shared with LEA)

(Sector 2)

(005FFFh to 004000h)

005FFFh to 005000h

004FFFh to 004000h

4KB

(005FFFh to 004000h)

005FFFh to 005000h

004FFFh to 004000h

4KB

Block 1

Block 0

System RAM

Size

(Sector 1 base location)

(Sector 0 base location)

Mirrored location: 001FFFh to 001C00h

Mirrored location: 002BFFh to 001C00h

Main: base location

(002BFFh to 002400h)

(0023FFh to 001C00h)

003FFFh to 003C00h

003BFFh to 002C00h

002BFFh to 001C00h

003BFFh to 003B80h

(002BFFh to 002400h)

(0023FFh to 001C00h)

003FFFh to 003C00h

003BFFh to 002C00h

002BFFh to 001C00h

003BFFh to 003B80h

Main: interrupt vectors

Device descriptor info (TLV) (FRAM)

Size

256 bytes

001AFFh to 001A00h

256 bytes

001AFFh to 001A00h

TI calibration and configuration (FRAM)

Bootloader (BSL) memory (ROM)

256 bytes

0019FFh to 001900h

256 bytes

0019FFh to 001900h

BSL 3

BSL 2

BSL 1

BSL 0

Size

512 bytes

0017FFh to 001600h

512 bytes

0017FFh to 001600h

512 bytes

0015FFh to 001400h

512 bytes

0015FFh to 001400h

512 bytes

0013FFh to 001200h

512 bytes

0013FFh to 001200h

512 bytes

0011FFh to 001000h

512 bytes

0011FFh to 001000h

Peripherals

Tiny RAM

Reserved

4KB

000FFFh to 000020h

Size

22 bytes

000001Fh to 00000Ah

22 bytes

000001Fh to 00000Ah

Size

10 bytes

000009h to 000000h

(1) All address space not listed is considered vacant memory.

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9.16.1 Peripheral File Map

For complete module register descriptions, see the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx

Family User's Guide.

表9-53. Peripherals

MODULE NAME

Special Functions (see 表9-54)

BASE ADDRESS

0100h

0120h

0140h

0150h

0158h

015Ch

0160h

0180h

01B0h

0200h

0340h

0380h

03C0h

0400h

0440h

04A0h

04C0h

0500h

05A0h

05C0h

05E0h

0600h

0620h

0640h

0680h

07C0h

0800h

08C0h

0980h

09C0h

0A00h

0A80h

0E00h

0E80h

0EC0h

0EE0h

0F00h

END ADDRESS

011Fh

013Fh

014Fh

0157h

0159h

015Dh

016Fh

019Fh

01B1h

033Fh

036Fh

03AFh

03EFh

042Fh

046Fh

04BFh

04EFh

056Fh

05AFh

05DFh

05FFh

061Fh

063Fh

066Fh

06AFh

07EFh

089Fh

08CFh

09AFh

09CFh

0A5Fh

0AFFh

0E7Fh

0EBFh

0EDFh

0EFFh

0F1Fh

PMM (see 表9-55)

FRAM Control (see 表9-56)

CRC (see 表9-57)

RAM Control (see 表9-58)

Watchdog (see 表9-59)

CS (see 表9-60)

SYS (see 表9-61)

Shared Reference (see 表9-62)

Digital I/O (see 表9-63)

TA0 (see 表9-64)

TA1 (see 表9-65)

TB0 (see 表9-66)

TA2 (see 表9-67)

TA3 (see 表9-68)

RTC_C (see 表9-69)

32-bit Hardware Multiplier (see 表9-70)

DMA (see 表9-71)

MPU Control (see 表9-72)

eUSCI_A0 (see 表9-73)

eUSCI_A1 (see 表9-74)

eUSCI_A2 (see 表9-75)

eUSCI_A3 (see 表9-76)

eUSCI_B0 (see 表9-77)

eUSCI_B1 (see 表9-78)

TA4 (see 表9-79)

ADC12_B (see 表9-80)

Comparator E (see 表9-81)

CRC32 (see 表9-82)

AES256 (see 表9-83)

LCD_C (see 表9-90)

LEA (see 表9-84)

SAPH_A (see 表9-85)

SDHS (see 表9-86)

UUPS (see 表9-87)

HSPLL (see 表9-88)

MTIF (see 表9-89)

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表9-54. Special Functions Registers

REGISTER DESCRIPTION

ACRONYM

ADDRESS

0100h

Interrupt Enable

Interrupt Flag

SFRIE1

SFRIFG1

SFRRPCR

0102h

Reset Pin Control

0104h

表9-55. PMM Registers

表9-56. FRAM Control Registers

表9-57. CRC Registers

REGISTER DESCRIPTION

ACRONYM

PMMCTL0

PMMIFG

ADDRESS

0120h

PMM control register 0

PMM interrupt flag register

012Ah

Power mode 5 control register 0

PM5CTL0

0130h

REGISTER DESCRIPTION

ACRONYM

FRCTL0

ADDRESS

0140h

FRAM Controller A Control Register 0

General Control Register 0

GCCTL0

GCCTL1

0144h

General Control Register 1

0146h

REGISTER DESCRIPTION

ACRONYM

CRCDI

ADDRESS

0150h

CRC Data In

CRC Data In Reverse Byte

CRC Initialization and Result

CRC Result Reverse

CRCDIRB

CRCINIRES

CRCRESR

0152h

0154h

0156h

表9-58. RAM Control Registers

REGISTER DESCRIPTION

ACRONYM

RCCTL0

ADDRESS

0158h

RAM Controller Control 0

RAM Controller Control 1

RCCTL1

015Ah

表9-59. Watchdog Registers

表9-60. CS Registers

REGISTER DESCRIPTION

Watchdog Timer Control Register

ACRONYM

ADDRESS

WDTCTL

015Ch

REGISTER DESCRIPTION

ACRONYM

CSCTL0

CSCTL1

CSCTL2

CSCTL3

CSCTL4

CSCTL5

CSCTL6

ADDRESS

0160h

Clock System Control 0

Clock System Control 1

Clock System Control 2

Clock System Control 3

Clock System Control 4

Clock System Control 5

Clock System Control 6

0162h

0164h

0166h

0168h

016Ah

016Ch

表9-61. SYS Registers

REGISTER DESCRIPTION

ACRONYM

SYSCTL

ADDRESS

0180h

System Control

JTAG Mailbox Control

JTAG Mailbox Input

SYSJMBC

SYSJMBI0

SYSJMBI1

0186h

0188h

018Ah

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表9-61. SYS Registers (continued)

REGISTER DESCRIPTION

ACRONYM

SYSJMBO0

SYSJMBO1

SYSUNIV

ADDRESS

JTAG Mailbox Output

User NMI Vector Generator

018Ch

018Eh

019Ah

019Ch

019Eh

System NMI Vector Generator

Reset Vector Generator

SYSSNIV

SYSRSTIV

表9-62. Shared Reference Registers

REGISTER DESCRIPTION

ACRONYM

ADDRESS

REF Control Register 0

REFCTL0

01B0h

表9-63. Digital I/O Registers

REGISTER DESCRIPTION

ACRONYM

PAIN

ADDRESS

0200h

0201h

0202h

0203h

0204h

0205h

0206h

0207h

020Ah

020Bh

020Ch

020Dh

020Eh

0216h

0217h

0218h

0219h

021Ah

021Bh

021Ch

021Dh

021Eh

0220h

Port A Input

Port 1 Input

P1IN

Port 2 Input

P2IN

Port A Output

PAOUT

P1OUT

P2OUT

PADIR

P1DIR

P2DIR

PAREN

P1REN

P2REN

PASEL0

P1SEL0

P2SEL0

PASEL1

P1SEL1

P2SEL1

P1IV

Port 1 Output

Port 2 Output

Port A Direction

Port 1 Direction

Port 2 Direction

Port A Resistor Enable

Port 1 Resistor Enable

Port 2 Resistor Enable

Port A Select 0

Port 1 Select 0

Port 2 Select 0

Port A Select 1

Port 1 Select 1

Port 2 Select 1

Port 1 Interrupt Vector Register

Port A Complement Select

Port 1 Complement Select

Port 2 Complement Select

Port A Interrupt Edge Select

Port 1 Interrupt Edge Select

Port 2 Interrupt Edge Select

Port A Interrupt Enable

Port 1 Interrupt Enable

Port 2 Interrupt Enable

Port A Interrupt Flag

PASELC

P1SELC

P2SELC

PAIES

P1IES

P2IES

PAIE

P1IE

P2IE

PAIFG

P1IFG

P2IFG

P2IV

Port 1 Interrupt Flag

Port 2 Interrupt Flag

Port 2 Interrupt Vector Register

Port B Input

PBIN

Port 3 Input

P3IN

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表9-63. Digital I/O Registers (continued)

REGISTER DESCRIPTION

ACRONYM

ADDRESS

0221h

0222h

0223h

0224h

0225h

0226h

0227h

022Ah

022Bh

022Ch

022Dh

022Eh

0236h

0237h

0238h

0239h

023Ah

023Bh

023Ch

023Dh

023Eh

0240h

0241h

0242h

0243h

0244h

0245h

0246h

0247h

024Ah

024Bh

Port 4 Input

P4IN

PBOUT

P3OUT

P4OUT

PBDIR

P3DIR

P4DIR

PBREN

P3REN

P4REN

PBSEL0

P3SEL0

P4SEL0

PBSEL1

P3SEL1

P4SEL1

P3IV

Port B Output

Port 3 Output

Port 4 Output

Port B Direction

Port 3 Direction

Port 4 Direction

Port B Resistor Enable

Port 3 Resistor Enable

Port 4 Resistor Enable

Port B Select 0

Port 3 Select 0

Port 4 Select 0

Port B Select 1

Port 3 Select 1

Port 4 Select 1

Port 3 Interrupt Vector Register

Port B Complement Select

Port 3 Complement Select

Port 4 Complement Select

Port B Interrupt Edge Select

Port 3 Interrupt Edge Select

Port 4 Interrupt Edge Select

Port B Interrupt Enable

Port 3 Interrupt Enable

Port 4 Interrupt Enable

Port B Interrupt Flag

Port 3 Interrupt Flag

Port 4 Interrupt Flag

Port 4 Interrupt Vector Register

Port C Input

PBSELC

P3SELC

P4SELC

PBIES

P3IES

P4IES

PBIE

P3IE

P4IE

PBIFG

P3IFG

P4IFG

P4IV

PCIN

Port 5 Input

P5IN

Port 6 Input

P6IN

Port C Output

PCOUT

P5OUT

P6OUT

PCDIR

P5DIR

P6DIR

PCREN

P5REN

P6REN

PCSEL0

P5SEL0

P6SEL0

Port 5 Output

Port 6 Output

Port C Direction

Port 5 Direction

Port 6 Direction

Port C Resistor Enable

Port 5 Resistor Enable

Port 6 Resistor Enable

Port C Select 0

Port 5 Select 0

Port 6 Select 0

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表9-63. Digital I/O Registers (continued)

REGISTER DESCRIPTION

ACRONYM

PCSEL1

P5SEL1

P6SEL1

P5IV

ADDRESS

Port C Select 1

Port 5 Select 1

Port 6 Select 1

024Ch

024Dh

024Eh

0256h

0257h

0258h

0259h

025Ah

025Bh

025Ch

025Dh

025Eh

0260h

0262h

0264h

0266h

026Ah

026Ch

026Eh

0276h

0278h

027Ah

027Ch

0320h

0322h

0324h

0326h

032Ah

032Ch

0336h

Port 5 Interrupt Vector Register

Port C Complement Select

Port 5 Complement Select

Port 6 Complement Select

Port C Interrupt Edge Select

Port 5 Interrupt Edge Select

Port 6 Interrupt Edge Select

Port C Interrupt Enable

Port 5 Interrupt Enable

Port 6 Interrupt Enable

Port C Interrupt Flag

Port 5 Interrupt Flag

Port 6 Interrupt Flag

Port 6 Interrupt Vector Register

Port D Input

PCSELC

P5SELC

P6SELC

PCIES

P5IES

P6IES

PCIE

P5IE

P6IE

PCIFG

P5IFG

P6IFG

P6IV

PDIN

Port 7 Input

P7IN

Port D Output

PDOUT

P7OUT

PDDIR

P7DIR

PDREN

P7REN

PDSEL0

P7SEL0

PDSEL1

P7SEL1

P7IV

Port 7 Output

Port D Direction

Port 7 Direction

Port D Resistor Enable

Port 7 Resistor Enable

Port D Select 0

Port 7 Select 0

Port D Select 1

Port 7 Select 1

Port 7 Interrupt Vector Register

Port D Complement Select

Port 7 Complement Select

Port D Interrupt Edge Select

Port 7 Interrupt Edge Select

Port D Interrupt Enable

Port 7 Interrupt Enable

Port D Interrupt Flag

Port 7 Interrupt Flag

Port J Input

PDSELC

P7SELC

PDIES

P7IES

PDIE

P7IE

PDIFG

P7IFG

PJIN

Port J Output

PJOUT

PJDIR

PJREN

PJSEL0

PJSEL1

PJSELC

Port J Direction

Port J Resistor Enable

Port J Select 0

Port J Select 1

Port J Complement Select

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表9-64. TA0 Registers

表9-65. TA1 Registers

表9-66. TB0 Registers

REGISTER DESCRIPTION

ACRONYM

TA0CTL

ADDRESS

0340h

0342h

0344h

0346h

0350h

0352h

0354h

0356h

0360h

036Eh

Timer_A0 Control Register

Timer_A0 Capture/Compare Control Register

Timer_A0 register

TA0CCTL0

TA0CCTL1

TA0CCTL2

TA0R

Timer_A0 Capture/Compare Register

Timer_A0 Expansion 0 Register

TA0CCR0

TA0CCR1

TA0CCR2

TA0EX0

Timer_A0 Interrupt Vector Register

TA0IV

REGISTER DESCRIPTION

ACRONYM

TA1CTL

ADDRESS

0380h

0382h

0384h

0386h

0390h

0392h

0394h

0396h

03A0h

03AEh

Timer_A1 Control Register

Timer_A1 Capture/Compare Control Register

Timer_A1 register

TA1CCTL0

TA1CCTL1

TA1CCTL2

TA1R

Timer_A1 Capture/Compare Register

Timer_A1 Expansion 0 Register

TA1CCR0

TA1CCR1

TA1CCR2

TA1EX0

Timer_A1 Interrupt Vector Register

TA1IV

REGISTER DESCRIPTION

ACRONYM

TB0CTL

ADDRESS

03C0h

03C2h

03C4h

03C6h

03C8h

03CAh

03CCh

03CEh

03D0h

03D2h

03D4h

03D6h

03D8h

03DAh

03DCh

03DEh

03E0h

03EEh

Timer_B0 Control Register

Timer_B0 Capture/Compare Control Register

Timer_B0 count register

TB0CCTL0

TB0CCTL1

TB0CCTL2

TB0CCTL3

TB0CCTL4

TB0CCTL5

TB0CCTL6

TB0R

Timer_B0 Capture/Compare Register

Timer_B0 Expansion Register 0

TB0CCR0

TB0CCR1

TB0CCR2

TB0CCR3

TB0CCR4

TB0CCR5

TB0CCR6

TB0EX0

Timer_B0 Interrupt Vector Register

TB0IV

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表9-67. TA2 Registers

REGISTER DESCRIPTION

ACRONYM

TA2CTL

ADDRESS

Timer_A2 Control Register

0400h

0402h

0404h

0410h

0412h

0414h

0420h

042Eh

Timer_A2 Capture/Compare Control Register

Timer_A2 register

TA2CCTL0

TA2CCTL1

TA2R

Timer_A2 Capture/Compare Register

Timer_A2 Expansion 0 Register

TA2CCR0

TA2CCR1

TA2EX0

Timer_A2 Interrupt Vector Register

TA2IV

表9-68. TA3 Registers

REGISTER DESCRIPTION

ACRONYM

TA3CTL

ADDRESS

0440h

0442h

0444h

0450h

0452h

0454h

0460h

046Eh

Timer_A3 Control Register

Timer_A3 Capture/Compare Control Register

Timer_A3 register

TA3CCTL0

TA3CCTL1

TA3R

Timer_A3 Capture/Compare Register

Timer_A3 Expansion 0 Register

Timer_A3 Interrupt Vector Register

TA3CCR0

TA3CCR1

TA3EX0

TA3IV

表9-69. RTC_C Registers

REGISTER DESCRIPTION

ACRONYM

RTCCTL0

RTCCTL13

RTCOCAL

RTCTCMP

RTCPS0CTL

RTCPS1CTL

RTCPS

ADDRESS

04A0h

04A2h

04A4h

04A6h

04A8h

04AAh

04ACh

04ADh

04AEh

04B0h

04B2h

04B4h

04B6h

04B8h

04BAh

04BCh

04BEh

RTCCTL0 Register

RTCCTL13 Register

RTCOCAL Register

RTCTCMP Register

Real-Time Clock Prescale Timer 0 Control Register

Real-Time Clock Prescale Timer 1 Control Register

Real-Time Clock Prescale Timer Counter Register

Prescale timer 0 counter value

RT0PS

Prescale timer 1 counter value

RT1PS

Real-Time Clock Interrupt Vector Register

RTCTIM0 Register –Hexadecimal Format

Real-Time Clock Hour, Day of Week

RTCDATE - Hexadecimal Format

RTCYEAR Register –Hexadecimal Format

RTCMINHR - Hexadecimal Format

RTCADOWDAY - Hexadecimal Format

Binary-to-BCD Conversion Register

BCD-to-Binary Conversion Register

RTCIV

RTCTIM0

RTCTIM1

RTCDATE

RTCYEAR

RTCAMINHR

RTCADOWDAY

BIN2BCD

BCD2BIN

表9-70. 32-bit Hardware Multiplier Registers

REGISTER DESCRIPTION

ACRONYM

ADDRESS

04C0h

MPY

MPYS

MAC

16-bit operand one –multiply

04C2h

16-bit operand one –signed multiply

16-bit operand one –multiply accumulate

04C4h

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表9-70. 32-bit Hardware Multiplier Registers (continued)

REGISTER DESCRIPTION

ACRONYM

ADDRESS

04C6h

04C8h

04CAh

04CCh

04CEh

04D0h

04D2h

04D4h

04D6h

04D8h

04DAh

04DCh

04DEh

04E0h

04E2h

04E4h

04E6h

04E8h

04EAh

04ECh

MACS

16-bit operand one –signed multiply accumulate

16-bit operand two

OP2

16x16-bit result low word

RESLO

RESHI

16x16-bit result high word

16x16-bit sum extension register

SUMEXT

MPY32L

MPY32H

MPYS32L

MPYS32H

MAC32L

MAC32H

MACS32L

MACS32H

OP2L

32-bit operand 1 –multiply –low word

32-bit operand 1 –multiply –high word

32-bit operand 1 –signed multiply –low word

32-bit operand 1 –signed multiply –high word

32-bit operand 1 –multiply accumulate –low word

32-bit operand 1 –multiply accumulate –high word

32-bit operand 1 –signed multiply accumulate –low word

32-bit operand 1 –signed multiply accumulate –high word

32-bit operand 2 –low word

OP2H

32-bit operand 2 –high word

RES0

32x32-bit result 0 –least significant word

32x32-bit result 1

RES1

32x32-bit result 2

RES2

RES3

32x32-bit result 3 –most significant word

MPY32 control register 0

MPY32CTL0

表9-71. DMA Registers

REGISTER DESCRIPTION

ACRONYM

DMACTL0

DMACTL1

DMACTL2

DMACTL4

DMAIV

ADDRESS

0500h

0502h

0504h

0508h

050Eh

0510h

0512h

0516h

051Ah

0520h

0522h

0526h

052Ah

0530h

0532h

0536h

053Ah

0540h

0542h

0546h

054Ah

0550h

DMA Control 0

DMA Control 1

DMA Control 2

DMA Control 4

DMA Interrupt Vector

DMA Channel 0 Control

DMA0CTL

DMA0SA

DMA0DA

DMA0SZ

DMA1CTL

DMA1SA

DMA1DA

DMA1SZ

DMA2CTL

DMA2SA

DMA2DA

DMA2SZ

DMA3CTL

DMA3SA

DMA3DA

DMA3SZ

DMA4CTL

DMA Channel 0 Source Address

DMA Channel 0 Destination Address

DMA Channel 0 Transfer Size

DMA Channel 1 Control

DMA Channel 1 Source Address

DMA Channel 1 Destination Address

DMA Channel 1 Transfer Size

DMA Channel 2 Control

DMA Channel 2 Source Address

DMA Channel 2 Destination Address

DMA Channel 2 Transfer Size

DMA Channel 3 Control

DMA Channel 3 Source Address

DMA Channel 3 Destination Address

DMA Channel 3 Transfer Size

DMA Channel 4 Control

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表9-71. DMA Registers (continued)

REGISTER DESCRIPTION

ACRONYM

DMA4SA

DMA4DA

DMA4SZ

DMA5CTL

DMA5SA

DMA5DA

DMA5SZ

ADDRESS

DMA Channel 4 Source Address

0552h

0556h

055Ah

0560h

0562h

0566h

056Ah

DMA Channel 4 Destination Address

DMA Channel 4 Transfer Size

DMA Channel 5 Control

DMA Channel 5 Source Address

DMA Channel 5 Destination Address

DMA Channel 5 Transfer Size

表9-72. MPU Control Registers

REGISTER DESCRIPTION

ACRONYM

MPUCTL0

ADDRESS

05A0h

05A2h

05A4h

05A6h

05A8h

05AAh

05ACh

05AEh

Memory Protection Unit Control 0

Memory Protection Unit Control 1

MPUCTL1

Memory Protection Unit Segmentation Border 2 Register

Memory Protection Unit Segmentation Border 1 Register

Memory Protection Unit Segmentation Access Management Register

Memory Protection Unit IP Control 0 Register

MPUSEGB2

MPUSEGB1

MPUSAM

MPUIPC0

Memory Protection Unit IP Encapsulation Segment Border 2 Register

Memory Protection Unit IP Encapsulation Segment Border 1 Register

MPUIPSEGB2

MPUIPSEGB1

表9-73. eUSCI_A0 Registers

REGISTER DESCRIPTION

ACRONYM

UCA0CTLW0

UCA0CTLW1

UCA0BRW

UCA0MCTLW

UCA0STATW

UCA0RXBUF

UCA0TXBUF

UCA0ABCTL

UCA0IRCTL

UCA0IE

ADDRESS

05C0h

05C2h

05C6h

05C8h

05CAh

05CCh

05CEh

05D0h

05D2h

05DAh

05DCh

05DEh

eUSCI_A0 Control Word Register 0

eUSCI_A0 Control Word Register 1

eUSCI_A0 Baud Rate Control Word Register

eUSCI_A0 Modulation Control Word Register

eUSCI_A0 Status Register

eUSCI_A0 Receive Buffer Register

eUSCI_A0 Transmit Buffer Register

eUSCI_A0 Auto Baud Rate Control Register

eUSCI_A0 IrDA Control Word Register

eUSCI_A0 Interrupt Enable Register

eUSCI_A0 Interrupt Flag Register

UCA0IFG

eUSCI_A0 Interrupt Vector Register

UCA0IV

表9-74. eUSCI_A1 Registers

REGISTER DESCRIPTION

ACRONYM

UCA1CTLW0

UCA1CTLW1

UCA1BRW

ADDRESS

05E0h

05E2h

05E6h

05E8h

05EAh

05ECh

05EEh

05F0h

05F2h

05FAh

05FCh

eUSCI_A1 Control Word Register 0

eUSCI_A1 Control Word Register 1

eUSCI_A1 Baud Rate Control Word Register

eUSCI_A1 Modulation Control Word Register

eUSCI_A1 Status Register

UCA1MCTLW

UCA1STATW

UCA1RXBUF

UCA1TXBUF

UCA1ABCTL

UCA1IRCTL

UCA1IE

eUSCI_A1 Receive Buffer Register

eUSCI_A1 Transmit Buffer Register

eUSCI_A1 Auto Baud Rate Control Register

eUSCI_A1 IrDA Control Word Register

eUSCI_A1 Interrupt Enable Register

eUSCI_A1 Interrupt Flag Register

UCA1IFG

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表9-74. eUSCI_A1 Registers (continued)

REGISTER DESCRIPTION

ACRONYM

ADDRESS

eUSCI_A1 Interrupt Vector Register

UCA1IV

05FEh

表9-75. eUSCI_A2 Registers

表9-76. eUSCI_A3 Registers

表9-77. eUSCI_B0 Registers

REGISTER DESCRIPTION

ACRONYM

UCA2CTLW0

UCA2CTLW1

UCA2BRW

UCA2MCTLW

UCA2STATW

UCA2RXBUF

UCA2TXBUF

UCA2ABCTL

UCA2IRCTL

UCA2IE

ADDRESS

0600h

0602h

0606h

0608h

060Ah

060Ch

060Eh

0610h

0612h

061Ah

061Ch

061Eh

eUSCI_A2 Control Word Register 0

eUSCI_A2 Control Word Register 1

eUSCI_A2 Baud Rate Control Word Register

eUSCI_A2 Modulation Control Word Register

eUSCI_A2 Status Register

eUSCI_A2 Receive Buffer Register

eUSCI_A2 Transmit Buffer Register

eUSCI_A2 Auto Baud Rate Control Register

eUSCI_A2 IrDA Control Word Register

eUSCI_A2 Interrupt Enable Register

eUSCI_A2 Interrupt Flag Register

UCA2IFG

eUSCI_A2 Interrupt Vector Register

UCA2IV

REGISTER DESCRIPTION

ACRONYM

UCA3CTLW0

UCA3CTLW1

UCA3BRW

UCA3MCTLW

UCA3STATW

UCA3RXBUF

UCA3TXBUF

UCA3ABCTL

UCA3IRCTL

UCA3IE

ADDRESS

0620h

0622h

0626h

0628h

062Ah

062Ch

062Eh

0630h

0632h

063Ah

063Ch

063Eh

eUSCI_A3 Control Word Register 0

eUSCI_A3 Control Word Register 1

eUSCI_A3 Baud Rate Control Word Register

eUSCI_A3 Modulation Control Word Register

eUSCI_A3 Status Register

eUSCI_A3 Receive Buffer Register

eUSCI_A3 Transmit Buffer Register

eUSCI_A3 Auto Baud Rate Control Register

eUSCI_A3 IrDA Control Word Register

eUSCI_A3 Interrupt Enable Register

eUSCI_A3 Interrupt Flag Register

UCA3IFG

eUSCI_A3 Interrupt Vector Register

UCA3IV

REGISTER DESCRIPTION

ACRONYM

UCB0CTLW0

UCB0CTLW1

UCB0BRW

ADDRESS

0640h

0642h

0646h

0648h

064Ah

064Ch

064Eh

0654h

0656h

0658h

065Ah

065Ch

065Eh

eUSCI_B0 Control Word Register 0

eUSCI_B0 Control Word Register 1

eUSCI_B0 Baud Rate Control Word Register

eUSCI_B0 Status Register

UCB0STATW

UCB0TBCNT

UCB0RXBUF

UCB0TXBUF

UCB0I2COA0

UCB0I2COA1

UCB0I2COA2

UCB0I2COA3

UCB0ADDRX

UCB0ADDMASK

eUSCI_B0 Byte Counter Threshold Register

eUSCI_B0 Receive Buffer Register

eUSCI_B0 Transmit Buffer Register

eUSCI_B0 I2C Own Address 0 Register

eUSCI_B0 I2C Own Address 1 Register

eUSCI_B0 I2C Own Address 2 Register

eUSCI_B0 I2C Own Address 3 Register

eUSCI_B0 I2C Received Address Register

eUSCI_B0 I2C Address Mask Register

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表9-77. eUSCI_B0 Registers (continued)

REGISTER DESCRIPTION

ACRONYM

UCB0I2CSA

UCB0IE

ADDRESS

eUSCI_B0 I2C Slave Address Register

0660h

066Ah

066Ch

066Eh

eUSCI_B0 Interrupt Enable Register

eUSCI_B0 Interrupt Flag Register

eUSCI_B0 Interrupt Vector Register

UCB0IFG

UCB0IV

表9-78. eUSCI_B1 Registers

REGISTER DESCRIPTION

ACRONYM

UCB1CTLW0

UCB1CTLW1

UCB1BRW

ADDRESS

0680h

0682h

0686h

0688h

068Ah

068Ch

068Eh

0694h

0696h

0698h

069Ah

069Ch

069Eh

06A0h

06AAh

06ACh

06AEh

eUSCI_B1 Control Word Register 0

eUSCI_B1 Control Word Register 1

eUSCI_B1 Baud Rate Control Word Register

eUSCI_B1 Status Register

UCB1STATW

UCB1TBCNT

UCB1RXBUF

UCB1TXBUF

UCB1I2COA0

UCB1I2COA1

UCB1I2COA2

UCB1I2COA3

UCB1ADDRX

UCB1ADDMASK

UCB1I2CSA

UCB1IE

eUSCI_B1 Byte Counter Threshold Register

eUSCI_B1 Receive Buffer Register

eUSCI_B1 Transmit Buffer Register

eUSCI_B1 I2C Own Address 0 Register

eUSCI_B1 I2C Own Address 1 Register

eUSCI_B1 I2C Own Address 2 Register

eUSCI_B1 I2C Own Address 3 Register

eUSCI_B1 I2C Received Address Register

eUSCI_B1 I2C Address Mask Register

eUSCI_B1 I2C Slave Address Register

eUSCI_B1 Interrupt Enable Register

eUSCI_B1 Interrupt Flag Register

UCB1IFG

eUSCI_B1 Interrupt Vector Register

UCB1IV

表9-79. TA4 Registers

REGISTER DESCRIPTION

ACRONYM

TA4CTL

ADDRESS

07C0h

07C2h

07C4h

07D0h

07D2h

07D4h

07E0h

07EEh

Timer_A4 Control Register

Timer_A4 Capture/Compare Control Register

Timer_A4 register

TA4CCTL0

TA4CCTL1

TA4R

Timer_A4 Capture/Compare Register

Timer_A4 Expansion 0 Register

Timer_A4 Interrupt Vector Register

TA4CCR0

TA4CCR1

TA4EX0

TA4IV

表9-80. ADC12_B Registers

REGISTER DESCRIPTION

ACRONYM

ADC12CTL0

ADC12CTL1

ADC12CTL2

ADC12CTL3

ADC12LO

ADDRESS

0800h

0802h

0804h

0806h

0808h

080Ah

080Ch

080Eh

0810h

ADC12_B Control 0

ADC12_B Control 1

ADC12_B Control 2

ADC12_B Control 3

ADC12_B Window Comparator Low Threshold Register

ADC12_B Window Comparator High Threshold Register

ADC12_B Interrupt Flag 0

ADC12HI

ADC12IFGR0

ADC12IFGR1

ADC12IFGR2

ADC12_B Interrupt Flag 1

ADC12_B Interrupt Flag 2

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表9-80. ADC12_B Registers (continued)

REGISTER DESCRIPTION

ACRONYM

ADDRESS

0812h

0814h

0816h

0818h

0820h

0822h

0824h

0826h

0828h

082Ah

082Ch

082Eh

0830h

0832h

0834h

0836h

0838h

083Ah

083Ch

083Eh

0840h

0842h

0844h

0846h

0848h

084Ah

084Ch

084Eh

0850h

0852h

0854h

0856h

0858h

085Ah

085Ch

085Eh

0860h

0862h

0864h

0866h

0868h

086Ah

086Ch

086Eh

0870h

ADC12_B Interrupt Enable 0

ADC12_B Interrupt Enable 1

ADC12_B Interrupt Enable 2

ADC12_B Interrupt Vector

ADC12IER0

ADC12IER1

ADC12IER2

ADC12IV

ADC12_B Memory Control 0 Register

ADC12_B Memory Control 1 Register

ADC12_B Memory Control 2 Register

ADC12_B Memory Control 3 Register

ADC12_B Memory Control 4 Register

ADC12_B Memory Control 5 Register

ADC12_B Memory Control 6 Register

ADC12_B Memory Control 7 Register

ADC12_B Memory Control 8 Register

ADC12_B Memory Control 9 Register

ADC12_B Memory Control 10 Register

ADC12_B Memory Control 11 Register

ADC12_B Memory Control 12 Register

ADC12_B Memory Control 13 Register

ADC12_B Memory Control 14 Register

ADC12_B Memory Control 15 Register

ADC12_B Memory Control 16 Register

ADC12_B Memory Control 17 Register

ADC12_B Memory Control 18 Register

ADC12_B Memory Control 19 Register

ADC12_B Memory Control 20 Register

ADC12_B Memory Control 21 Register

ADC12_B Memory Control 22 Register

ADC12_B Memory Control 23 Register

ADC12_B Memory Control 24 Register

ADC12_B Memory Control 25 Register

ADC12_B Memory Control 26 Register

ADC12_B Memory Control 27 Register

ADC12_B Memory Control 28 Register

ADC12_B Memory Control 29 Register

ADC12_B Memory Control 30 Register

ADC12_B Memory Control 31 Register

ADC12_B Memory 0 Register

ADC12MCTL0

ADC12MCTL1

ADC12MCTL2

ADC12MCTL3

ADC12MCTL4

ADC12MCTL5

ADC12MCTL6

ADC12MCTL7

ADC12MCTL8

ADC12MCTL9

ADC12MCTL10

ADC12MCTL11

ADC12MCTL12

ADC12MCTL13

ADC12MCTL14

ADC12MCTL15

ADC12MCTL16

ADC12MCTL17

ADC12MCTL18

ADC12MCTL19

ADC12MCTL20

ADC12MCTL21

ADC12MCTL22

ADC12MCTL23

ADC12MCTL24

ADC12MCTL25

ADC12MCTL26

ADC12MCTL27

ADC12MCTL28

ADC12MCTL29

ADC12MCTL30

ADC12MCTL31

ADC12MEM0

ADC12MEM1

ADC12MEM2

ADC12MEM3

ADC12MEM4

ADC12MEM5

ADC12MEM6

ADC12MEM7

ADC12MEM8

ADC12_B Memory 1 Register

ADC12_B Memory 2 Register

ADC12_B Memory 3 Register

ADC12_B Memory 4 Register

ADC12_B Memory 5 Register

ADC12_B Memory 6 Register

ADC12_B Memory 7 Register

ADC12_B Memory 8 Register

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表9-80. ADC12_B Registers (continued)

REGISTER DESCRIPTION

ACRONYM

ADDRESS

ADC12_B Memory 9 Register

ADC12MEM9

ADC12MEM10

ADC12MEM11

ADC12MEM12

ADC12MEM13

ADC12MEM14

ADC12MEM15

ADC12MEM16

ADC12MEM17

ADC12MEM18

ADC12MEM19

ADC12MEM20

ADC12MEM21

ADC12MEM22

ADC12MEM23

ADC12MEM24

ADC12MEM25

ADC12MEM26

ADC12MEM27

ADC12MEM28

ADC12MEM29

ADC12MEM30

ADC12MEM31

0872h

0874h

0876h

0878h

087Ah

087Ch

087Eh

0880h

0882h

0884h

0886h

0888h

088Ah

088Ch

088Eh

0890h

0892h

0894h

0896h

0898h

089Ah

089Ch

089Eh

ADC12_B Memory 10 Register

ADC12_B Memory 11 Register

ADC12_B Memory 12 Register

ADC12_B Memory 13 Register

ADC12_B Memory 14 Register

ADC12_B Memory 15 Register

ADC12_B Memory 16 Register

ADC12_B Memory 17 Register

ADC12_B Memory 18 Register

ADC12_B Memory 19 Register

ADC12_B Memory 20 Register

ADC12_B Memory 21 Register

ADC12_B Memory 22 Register

ADC12_B Memory 23 Register

ADC12_B Memory 24 Register

ADC12_B Memory 25 Register

ADC12_B Memory 26 Register

ADC12_B Memory 27 Register

ADC12_B Memory 28 Register

ADC12_B Memory 29 Register

ADC12_B Memory 30 Register

ADC12_B Memory 31 Register

表9-81. Comparator E Registers

REGISTER DESCRIPTION

ACRONYM

CECTL0

CECTL1

CECTL2

CECTL3

CEINT

ADDRESS

08C0h

Comparator Control Register 0

Comparator Control Register 1

08C2h

Comparator Control Register 2

08C4h

Comparator Control Register 3

08C6h

Comparator Interrupt Control Register

Comparator Interrupt Vector Word Register

08CCh

08CEh

CEIV

表9-82. CRC32 Registers

REGISTER DESCRIPTION

ACRONYM

CRC32DIW0

ADDRESS

0980h

0982h

0984h

0986h

0988h

098Ah

098Ch

098Eh

0990h

0996h

0998h

CRC32 Data Input Word 0

CRC32 Data Input Word 1

CRC32DIW1

CRC32 Data In Reverse Word 1

CRC32 Data In Reverse Word 0

CRC32 Initialization and Result Word 0

CRC32 Initialization and Result Word 1

CRC32 Result Reverse Word 1

CRC32 Result Reverse Word 0

CRC16 Data Input

CRC32DIRBW1

CRC32DIRBW0

CRC32INIRESW0

CRC32INIRESW1

CRC32RESRW1

CRC32RESRW0

CRC16DIW0

CRC16 Data In Reverse

CRC16DIRBW0

CRC16INIRESW0

CRC16 Init and Result

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表9-82. CRC32 Registers (continued)

REGISTER DESCRIPTION

ACRONYM

ADDRESS

CRC16 Result Reverse

CRC16RESRW0

099Eh

表9-83. AES256 Registers

REGISTER DESCRIPTION

ACRONYM

AESACTL0

AESACTL1

AESASTAT

AESAKEY

AESADIN

ADDRESS

09C0h

09C2h

09C4h

09C6h

09C8h

09CAh

09CCh

09CEh

AES Accelerator Control Register 0

AES Accelerator Control Register 1

AES Accelerator Status Register

AES Accelerator Key Register

AES Accelerator Data In Register

AES Accelerator Data Out Register

AES Accelerator XORed Data In Register

AESADOUT

AESAXDIN

AESAXIN

表9-84. LEA Registers

REGISTER DESCRIPTION

ACRONYM

LEACAP

ADDRESS

0A80h

0A84h

0A88h

0A8Ch

0A90h

0A94h

0A98h

0A9Ch

0AA8h

0AACh

0AB0h

0AB4h

0AC0h

0AC4h

0AC8h

0ACCh

0AD0h

0AF0h

0AF4h

0AF8h

0AFCh

LEA Capability Register

Configuration Register 0

Configuration Register 1

Configuration Register 2

Memory Bottom Register

Memory Top Register

LEACNF0

LEACNF1

LEACNF2

LEAMB

LEAMT

Code Memory Access Register

Code Memory Control Register

LEA Command Status Register

LEA Source 1 Status Register

LEA Source 0 Status Register

LEA Result Status Register

PM Control Register

LEACMA

LEACMCTL

LEACMDSTAT

LEAS1STAT

LEAS0STAT

LEADSTSTAT

LEAPMCTL

LEAPMDST

LEAPMS1

LEAPMS0

LEAPMCB

LEAIFGSET

LEAIE

PM Result Register

PM Source 1 Register

PM Source 0 Register

PM Command Buffer Register

Interrupt Flag and Set Register

Interrupt Enable Register

Interrupt Flag and Clear Register

Interrupt Vector Register

LEAIFG

LEAIV

表9-85. SAPH_A Registers

REGISTER DESCRIPTION

ACRONYM

SAPH_AIIDX

SAPH_AMIS

ADDRESS

0E00h

0E02h

0E04h

0E06h

0E08h

0E0Ah

0E0Ch

0E0Eh

Interrupt Index

Masked Interrupt Satus

Raw Interrupt Status

Interrupt Mask

SAPH_ARIS

SAPH_AIMSC

SAPH_AICR

Interrupt Clear

Interrupt Set

SAPH_AISR

Module-Descriptor Low Word

Module-Descriptor High Word

SAPH_ADESCLO

SAPH_ADESCHI

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表9-85. SAPH_A Registers (continued)

REGISTER DESCRIPTION

ACRONYM

ADDRESS

Key

SAPH_AKEY

0E10h

0E12h

0E14h

0E16h

0E20h

0E22h

0E24h

0E26h

0E28h

0E2Ah

0E2Ch

0E2Eh

0E30h

0E34h

0E40h

0E42h

0E44h

0E46h

0E48h

0E4Ah

0E4Ch

0E4Eh

0E60h

0E62h

0E64h

0E66h

0E68h

0E6Ah

0E6Eh

0E70h

0E72h

0E74h

0E76h

0E78h

0E7Ah

0E7Ch

0E7Eh

Physical Interface Output Control #0

Physical Interface Output Control #1

Physical Interface Output Function Select

Channel 0 Pull UpTrim Register

Channel 0 Pull DownTrim Register

Channel 0 Termination Trim

Channel 1 Pull UpTrim

SAPH_AOCTL0

SAPH_AOCTL1

SAPH_AOSEL

SAPH_ACH0PUT

SAPH_ACH0PDT

SAPH_ACH0TT

SAPH_ACH1PUT

SAPH_ACH1PDT

SAPH_ACH1TT

SAPH_AMCNF

SAPH_ATACTL

SAPH_AICTL0

Channel 1 Pull DownTrim

Channel 1 Termination Trim

Mode Configuration

Trim Access Control

Physical Interface Input Control #0

Bias Control

SAPH_ABCTL

PPG Count

SAPH_APGC

Pulse Generator Low Period

Pulse Generator High Period

PPG Control

SAPH_APGLPER

SAPH_APGHPER

SAPH_APGCTL

SAPH_APPGTRIG

SAPH_AXPGCTL

SAPH_AXPGLPER

SAPH_AXPGHPER

SAPH_AASCTL0

SAPH_AASCTL1

SAPH_AASQTRIG

SAPH_AAPOL

PPG Software Trigger

Extended Pulse Control Register

Extra Pulse Low Period Register

Extra Pulse High Period Register

A-SEQ control register 0

A-SEQ control register 1

ASQ Software Trigger

ASQ ping output polarity

ASQ ping pause level

SAPH_AAPLEV

SAPH_AAPHIZ

SAPH_AATM_A

SAPH_AATM_B

SAPH_AATM_C

SAPH_AATM_D

SAPH_AATM_E

SAPH_AATM_F

SAPH_ATBCTL

SAPH_AATIMLO

SAPH_AATIMHI

ASQ ping pause impedance

A-SEQ start to 1st ping

ASQ start to ADC arm

Count for the TIMEMARK C Event

ASQ start to ADC trig

ASQ start to restart

ASQ start to timeout

Time Base Control

Acquisition Timer Low Part

Acquisition Timer High Part

表9-86. SDHS Registers

REGISTER DESCRIPTION

ACRONYM

SDHSIIDX

SDHSMIS

SDHSRIS

SDHSIMSC

SDHSICR

SDHSISR

ADDRESS

0E80h

Interrupt Index Register

Masked Interrupt Status and Clear Register

Raw Interrupt Status Register

Interrupt Mask Register

0E82h

0E84h

0E86h

Interrupt Clear Register.

0E88h

Interrupt Set Register.

0E8Ah

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表9-86. SDHS Registers (continued)

REGISTER DESCRIPTION

ACRONYM

ADDRESS

0E8Ch

0E8Eh

0E90h

0E92h

0E94h

0E96h

0E98h

0E9Ah

0E9Ch

0E9Eh

0EA2h

0EA4h

0EA6h

0EA8h

SDHS Descriptor Register L.

SDHS Descriptor Register H.

SDHS Control Register 0

SDHS Control Register 1

SDHS Control Register 2

SDHS Control Register 3

SDHS Control Register 4

SDHS Control Register 5

SDHS Control Register 6

SDHS Control Register 7

SDHSDESCLO

SDHSDESCHI

SDHSCTL0

SDHSCTL1

SDHSCTL2

SDHSCTL3

SDHSCTL4

SDHSCTL5

SDHSCTL6

SDHSCTL7

SDHSDT

SDHS Data Converstion Register

SDHS Window Comparator High Threshold Register.

SDHS Window Comparator Low Threshold Register.

DTC destination address register

SDHSWINHITH

SDHSWINLOTH

SDHSDTCDA

表9-87. UUPS Registers

REGISTER DESCRIPTION

ACRONYM

UUPSIIDX

ADDRESS

0EC0h

0EC2h

0EC4h

0EC6h

0EC8h

0ECAh

0ECCh

0ECEh

0ED0h

Interrupt Index Register

Masked Interrupt Status Register

Raw Interrupt Status Register

Interrupt Mask Register

UUPSMIS

UUPSRIS

UUPSIMSC

UUPSICR

Interrupt Clear Register.

Interrupt Flag Set Register.

UUPS Descriptor Register L.

UUPS Descriptor Register H.

UUPS Control

UUPSISR

UUPSDESCLO

UUPSDESCHI

UUPSCTL

表9-88. HSPLL Registers

REGISTER DESCRIPTION

ACRONYM

HSPLLIIDX

ADDRESS

0EE0h

0EE2h

0EE4h

0EE6h

0EE8h

0EEAh

0EECh

0EEEh

0EF0h

0EF2h

Interrupt Index Register

Masked Interrupt Status Register.

Raw Interrupt Status Register

Interrupt Mask Register

HSPLLMIS

HSPLLRIS

HSPLLIMSC

HSPLLICR

Interrupt Flag Clear Register.

Interrupt Flag Set Register.

HSPLL Descriptor Register L.

HSPLL Descriptor Register H.

HSPLL Control Register

HSPLLISR

HSPLLDESCLO

HSPLLDESCHI

HSPLLCTL

USSXT Control Register

HSPLLUSSXTLCTL

表9-89. MTIF Registers

REGISTER DESCRIPTION

ACRONYM

MTIFPGCNF

MTIFPGKVAL

MTIFPGCTL

MTIFPGSR

ADDRESS

0F00h

Pulse Generator Configuration Register

Pulse Generator Value Register

0F02h

Pulse Generator Control Register

Pulse Generator Status Register

Pulse Counter Configuration Register

0F04h

0F06h

MTIFPCCNF

0F08h

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表9-89. MTIF Registers (continued)

REGISTER DESCRIPTION

ACRONYM

ADDRESS

Pulse Counter Value Register

MTIFPCR

0F0Ah

0F0Ch

0F0Eh

0F10h

Pulse Counter Control Register

Pulse Counter Status Register

MTIFPCCTL

MTIFPCSR

MTIFTPCTL

Measurement Test Port Control Register

表9-90. LCD_C Registers

REGISTER DESCRIPTION

ACRONYM

LCDCCTL0

LCDCCTL1

LCDCBLKCTL

LCDCMEMCTL

LCDCVCTL

LCDCPCTL0

LCDCPCTL1

LCDCPCTL2

LCDCPCTL3

LCDCCPCTL

LCDCIV

ADDRESS

0A00h

0A02h

0A04h

0A06h

0A08h

0A0Ah

0A0Ch

0A0Eh

0A10h

0A12h

0A1Eh

LCD_C control 0

LCD_C control 1

LCD_C blinking control

LCD_C memory control

LCD_C voltage control

LCD_C port control 0

LCD_C port control 1

LCD_C port control 2 (≥256 segments)

LCD_C port control 3 (384 segments)

LCD_C charge pump control register

LCD_C interrupt vector

Static and 2 to 4 mux modes

LCD_C memory 1

LCDM1

LCDM2

LCDM3

LCDM4

LCDM5

LCDM6

LCDM7

LCDM8

LCDM9

LCDM10

LCDM11

LCDM12

LCDM13

LCDM14

LCDM15

LCDM16

LCDM17

LCDM18

LCDM19

LCDM20

0A20h

0A21h

0A22h

0A23h

0A24h

0A25h

0A26h

0A27h

0A28h

0A29h

0A2Ah

0A2Bh

0A2Ch

0A2Dh

0A2Eh

0A2Fh

0A30h

0A31h

0A32h

0A33h

0A34h to 0A3Bh

0A40h

0A41h

0A42h

0A43h

0A44h

0A45h

LCD_C memory 2

LCD_C memory 3

LCD_C memory 4

LCD_C memory 5

LCD_C memory 6

LCD_C memory 7

LCD_C memory 8

LCD_C memory 9

LCD_C memory 10

LCD_C memory 11

LCD_C memory 12

LCD_C memory 13

LCD_C memory 14

LCD_C memory 15

LCD_C memory 16

LCD_C memory 17

LCD_C memory 18

LCD_C memory 19

LCD_C memory 20

Reserved

LCD_C blinking memory 1

LCD_C blinking memory 2

LCD_C blinking memory 3

LCD_C blinking memory 4

LCD_C blinking memory 5

LCD_C blinking memory 6

LCDBM1

LCDBM2

LCDBM3

LCDBM4

LCDBM5

LCDBM6

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表9-90. LCD_C Registers (continued)

REGISTER DESCRIPTION

ACRONYM

ADDRESS

0A46h

LCD_C blinking memory 7

LCD_C blinking memory 8

LCD_C blinking memory 9

LCD_C blinking memory 10

LCD_C blinking memory 11

LCD_C blinking memory 12

LCD_C blinking memory 13

LCD_C blinking memory 14

LCD_C blinking memory 15

LCD_C blinking memory 16

LCD_C blinking memory 17

LCD_C blinking memory 18

LCD_C blinking memory 19

LCD_C blinking memory 20

Reserved

LCDBM7

LCDBM8

0A47h

LCDBM9

0A48h

LCDBM10

LCDBM11

LCDBM12

LCDBM13

LCDBM14

LCDBM15

LCDBM16

LCDBM17

LCDBM18

LCDBM19

LCDBM20

0A49h

0A4Ah

0A4Bh

0A4Ch

0A4Dh

0A4Eh

0A4Fh

0A50h

0A51h

0A52h

0A53h

0A54h to 0A5Bh

5 to 8 mux modes

LCD_C memory 1

LCDM1

LCDM2

0A20h

0A21h

0A22h

0A23h

0A24h

0A25h

0A26h

0A27h

0A28h

0A29h

0A2Ah

0A2Bh

0A2Ch

0A2Dh

0A2Eh

0A2Fh

0A30h

0A31h

0A32h

0A33h

0A34h

0A35h

0A36h

0A37h

0A38h

0A39h

0A3Ah

0A3Bh

0A3Ch

LCD_C memory 2

LCD_C memory 3

LCDM3

LCD_C memory 4

LCDM4

LCD_C memory 5

LCDM5

LCD_C memory 6

LCDM6

LCD_C memory 7

LCDM7

LCD_C memory 8

LCDM8

LCD_C memory 9

LCDM9

LCD_C memory 10

LCDM10

LCDM11

LCDM12

LCDM13

LCDM14

LCDM15

LCDM16

LCDM17

LCDM18

LCDM19

LCDM20

LCDM21

LCDM22

LCDM23

LCDM24

LCDM25

LCDM26

LCDM27

LCDM28

LCDM29

LCD_C memory 11

LCD_C memory 12

LCD_C memory 13

LCD_C memory 14

LCD_C memory 15

LCD_C memory 16

LCD_C memory 17

LCD_C memory 18

LCD_C memory 19

LCD_C memory 20

LCD_C memory 21

LCD_C memory 22

LCD_C memory 23

LCD_C memory 24

LCD_C memory 25

LCD_C memory 26

LCD_C memory 27

LCD_C memory 28

LCD_C memory 29

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表9-90. LCD_C Registers (continued)

REGISTER DESCRIPTION

ACRONYM

LCDM30

LCDM31

LCDM32

LCDM33

LCDM34

LCDM35

LCDM36

ADDRESS

LCD_C memory 30

LCD_C memory 31

LCD_C memory 32

LCD_C memory 33

LCD_C memory 34

LCD_C memory 35

LCD_C memory 36

Reserved

0A3Dh

0A3Eh

0A3Fh

0A40h

0A41h

0A42h

0A43h

0A44h to 0A53h

LDC memory is implemented for groups of segments. Memory for non-existent segment lines is accessible but

cannot be used.

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9.17 Identification

9.17.1 Revision Identification

The device revision information is shown as part of the top-side marking on the device package. The device-

specific errata sheet describes these markings. For links to all of the errata sheets for the devices in this data

sheet, see 节11.4.

The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For details on

this value, see the "Hardware Revision" entries in the Device Descriptor structure (see 节9.15).

9.17.2 Device Identification

The device type can be identified from the top-side marking on the device package. The device-specific errata

sheet describes these markings. For links to all of the errata sheets for the devices in this data sheet, see 节

11.4.

A device identification value is also stored in the Device Descriptor structure in the Info Block section. For details

on this value, see the "Device ID" entries in the Device Descriptor structure (see 节9.15).

9.17.3 JTAG Identification

Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in MSP430

Programming With the JTAG Interface.

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10 Applications, Implementation, and Layout

Note

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

10.1 Device Connection and Layout Fundamentals

This section discusses the recommended guidelines when designing with the MSP430 MCU. These guidelines

are to make sure that the device has proper connections for powering, programming, debugging, and optimum

analog performance.

10.1.1 Power Supply and Bulk Capacitors

TI recommends connecting a combination of a 1-µF plus a 100-nF low-ESR ceramic decoupling capacitor to

each AVCC and DVCC pin. Higher-value capacitors may be used but can impact supply rail ramp-up time.

Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few

millimeters). Additionally, TI recommends separated grounds with a single-point connection for better noise

isolation from digital to analog circuits on the board and to achieve high analog accuracy.

DVCC

Digital Power

Supply Decoupling

+

DVSS

AVCC

1 µF

100 nF

Analog Power

Supply Decoupling

+

AVSS

1 µF

100 nF

图10-1. Power Supply Decoupling

For PVCC and PVSS, TI recommends connecting a combination of a 1-µF plus a 22-µF low-ESR ceramic

decoupling capacitor between the PVCC and PVSS pins and a serial 22-Ω resistor to filter low-frequency noise

on the supply line (see 图10-2).

22 W

PVCC

+

1 nF

22 µF

PVSS

USS module power supply decoupling

图10-2. Power Supply Decoupling for PVCC and PVSS

10.1.2 External Oscillator (HFXT and LFXT)

Depending on the device variant (see 节 6), the device can support a low-frequency crystal (32 kHz) on the

LFXT pins, a high-frequency crystal on the HFXT pins, or both. External bypass capacitors for the crystal

oscillator pins are required.

It is also possible to apply digital clock signals to the LFXIN and HFXIN input pins that meet the specifications of

the respective oscillator if the appropriate LFXTBYPASS or HFXTBYPASS mode is selected. In this case, the

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associated LFXOUT and HFXOUT pins can be used for other purposes. If they are left unused, they must be

terminated according to 节7.6.

图10-3 shows a typical connection diagram.

LFXIN

or

LFXOUT

or

HFXIN

HFXOUT

C_L1

C_L2

图10-3. Typical Crystal Connection

See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal

oscillator with MSP430 MCUs.

10.1.3 USS Oscillator (USSXT)

Depending on the device variant (see 节 6), the device with USS module supports a high-frequency crystal on

the USSXT pins. External bypass capacitors for the crystal oscillator pins are required. A 22-Ω resistor is

required to be serially connected closely to the USSXTOUT pin as shown in 图 10-4. The USSXT does not

support bypass mode, so it is not possible to apply digital clock signals to the USSXTIN pin. Never connect the

USSXTIN pin to a power supply line (AVCC, DVCC, or PVCC). If the USSXT pins are not used, terminate them

according to 节7.6.

图10-4 shows a typical connection diagram.

USSXTIN

USSXTOUT

22 W

C_L2

C_L1

图10-4. Typical Crystal Connection

Consider the following items for the USSXT layout:

• Keep the trace of USSXTIN and USSXTOUT as short as possible. In case one must be longer than the other,

keep USSXTIN shorter because USSXTIN is more sensitive to EMI

• Make ground shield open ended without making a loop

• Use ground plane to reduce the impedance of ground trace

• In case USSXT_BOUT is used, keep coupling to USSXTIN and CH0_IN to a minimum

• In case USSXT_BOUT is feeding other clock or device inputs, apply a small capacitor (10 pF) as the line

termination load at end of line. This avoids reflection artifacts on sensitive inputs (for example, HFXTIN).

图10-5 shows recommended PCB layout.

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Plane

Transducer

Interface

Area

Transducer

Interface

Area

Oscillator

Area

CL2

CL1

Oscillator

Area

XTAL

22R

Keep-out area for

high currents down

to next GND plane

Keep-out area for

high currents down

to next GND plane

图10-5. USSXT PCB Layout Recommendation

10.1.4 Transducer Connection to the USS Module

图 10-6 shows a typical connection of two transducers to the USS output and input pins. TI recommends 1%

error tolerance for the external termination resistors (Rterm0 and Rterm1) and the AC coupling capacitors (Cac0

and Cac1). Typical value of the termination resistors is in the range of 150 to 400 Ω, the AC coupling capacitors

are 1 to 2 nF. Actual values should be determined to meet the requirements of each application.

Rterm0

CH0_OUT

Rterm1

CH1_OUT

T0

T1

Cac0

Cac1

CH1_IN

CH0_IN

图10-6. Typical Transducer Connection

10.1.5 Charge Pump Control of Input Multiplexer

图 10-7 shows the control logic of the charge pump control of the input multiplexer of CHx_IN. The charge pump

is enabled as long the SAPH_AMCNF.CPEO is high and during the arming of the SDHS. Use the CPDA bit to

control the CP during data acquisition.

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SAPH_ABCTL.CPDA

ASQ.acquisition

Charge

pump

enable

ASQ.adc_arming

en CP

SAPH_AMCNF.CPEO

SDHS.adc_arming

SDHS.acquisition

CH0_IN

CH1_IN

PGA

To SDHS

图10-7. Control Of Input Multiplexer

10.1.6 JTAG

With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or MSP-

FET430UIF) can be used to program and debug code on the target board. In addition, the connections also

support the MSP-GANG production programmers, thus providing an easy way to program prototype boards, if

desired. 图 10-8 shows the connections between the 14-pin JTAG connector and the target device required to

support in-system programming and debugging for 4-wire JTAG communication. 图 10-9 shows the connections

for 2-wire JTAG mode (Spy-Bi-Wire).

The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are identical.

Both can supply V_CCto the target board (through pin 2). In addition, the MSP-FET and MSP-FET430UIF

interface modules and MSP-GANG have a V_CC-sense feature that, if used, requires an alternate connection (pin

4 instead of pin 2). The V_CC-sense feature senses the local V_CCpresent on the target board (that is, a battery or

other local power supply) and adjusts the output signals accordingly. 图 10-8 and 图 10-9 show a jumper block

that supports both scenarios of supplying V_CCto the target board. If this flexibility is not required, the desired V_CC

connections may be hard-wired to eliminate the jumper block. Pins 2 and 4 must not be connected at the same

time.

For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User’s Guide.

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V_CC

Important to connect

MSP430FRxxx

J1 (see Note A)

J2 (see Note A)

AVCC/DVCC

R1

47 kW

JTAG

RST/NMI/SBWTDIO

VCC TOOL

TDO/TDI

TDI

TDO/TDI

TDI

2

1

VCC TARGET

4

3

TMS

6

5

7

TEST

TCK

8

TCK

GND

RST

10

12

14

9

11

13

TEST/SBWTCK

AVSS/DVSS

C1

2.2 nF

(see Note B)

A. If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used, make connection

J2.

B. The upper limit for C1 is 2.2 nF when using current TI tools.

图10-8. Signal Connections for 4-Wire JTAG Communication

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V_CC

Important to connect

MSP430FRxxx

AVCC/DVCC

J1 (see Note A)

J2 (see Note A)

R1

47 kΩ

See Note B

JTAG

VCC TOOL

VCC TARGET

TDO/TDI

2

1

3

5

7

9

RST/NMI/SBWTDIO

4

6

TCK

8

GND

10

12

14

11

13

TEST/SBWTCK

AVSS/DVSS

C1

2.2 nF

See Note B

A. Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the debug or

programming adapter.

B. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during JTAG access, and

any capacitance that is attached to this signal may affect the ability to establish a connection with the device. The upper limit for C1 is

2.2 nF when using current TI tools.

图10-9. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)

10.1.7 Reset

The reset pin can be configured as a reset function (default) or as an NMI function in the SFRRPCR register.

In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing

specifications generates a BOR-type device reset.

Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is edge

sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the external NMI.

When an external NMI event occurs, the NMIIFG is set.

The RST/NMI pin can have either a pullup or pulldown resistor that is enabled or not. SYSRSTUP selects either

pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not. If the

RST/NMI pin is unused, either select and enable the internal pullup or connect an external 47-kΩpullup resistor

to the RST/NMI pin with a 2.2-nF pulldown capacitor. The pulldown capacitor should not exceed 2.2 nF when

using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools like FET

interfaces or GANG programmers.

See the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for more information on the

referenced control registers and bits.

10.1.8 Unused Pins

For details on the connection of unused pins, see 节7.6.

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10.1.9 General Layout Recommendations

• Use proper grounding and short traces for the external crystal to reduce parasitic capacitance. See MSP430

32-kHz Crystal Oscillators for recommended layout guidelines.

• Place the proper bypass capacitors on DVCC, AVCC, and reference pins, if used.

• Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital switching

signals (for example, PWM or JTAG signals) away from the oscillator circuit.

• Design for proper ESD level protection to protect the device from unintended high-voltage electrostatic

discharge. See MSP430 System-Level ESD Considerations for guidelines.

10.1.10 Do's and Don'ts

TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up, power

down, and device operation, the voltage difference between AVCC and DVCC must not exceed the limits

specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the device

including erroneous writes to RAM and FRAM.

10.2 Peripheral- and Interface-Specific Design Information

10.2.1 ADC12_B Peripheral

10.2.1.1 Partial Schematic

图 10-10 shows the recommended decoupling circuit when an external voltage reference is used. The internal

reference module has a maximum drive current as specified in the I_O(VREF+)specification of the REF module.

AVSS

VREF+/VEREF+

Using an

External

+

Positive

Reference

4.7 µF

10 µF

VEREF-

Using an

External

+

Negative

Reference

10 µF

4.7 µF

图10-10. ADC12_B Grounding and Noise Considerations

10.2.1.2 Design Requirements

As with any high-resolution ADC, follow appropriate PCB layout and grounding techniques to eliminate ground

loops, unwanted parasitic effects, and noise.

Ground loops are formed when return current from the ADC flows through paths that are common with other

analog or digital circuitry. If care is not taken, this current can generate small unwanted offset voltages that can

add to or subtract from the reference or input voltages of the ADC. The general guidelines in 节10.1.1 combined

with the connections shown in 节10.2.1.1 prevent these offsets.

In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital switching or

switching power supplies can corrupt the conversion result. TI recommends a noise-free design using separate

analog and digital ground planes with a single-point connection to achieve high accuracy.

The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are

selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage

enters the device. In this case, the 10-µF capacitor buffers the reference pin and filters low-frequency ripple. A

4.7-µF bypass capacitor filters out high-frequency noise.

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10.2.1.3 Detailed Design Procedure

For additional design information, see the application report Designing With the MSP430FR58xx, FR59xx,

FR68xx, and FR69xx ADC.

10.2.1.4 Layout Guidelines

Component that are shown in the partial schematic (see 图 10-10) should be placed as close as possible to the

respective device pins. Avoid long traces, because they add additional parasitic capacitance, inductance, and

resistance on the signal.

Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM), because

the high-frequency switching can be coupled into the analog signal.

If differential mode is used for the ADC12_B, the analog differential input signals must be routed closely together

to minimize the effect of noise on the resulting signal.

10.2.2 LCD_C Peripheral

10.2.2.1 Partial Schematic

Required LCD connections greatly vary by the type of display that is used (static or multiplexed), whether

external or internal biasing is used, and whether the on-chip charge pump is employed. Also, there is a fair

amount of flexibility as to how the segment (Sx) and common (COMx) signals are connected to the MCU which

can provide unique benefits. Since LCD connections are application specific, it is difficult to provide a single one-

fits-all schematic. However, for examples and how-to circuit-design guidance, see Designing With MSP430™

MCUs and Segment LCDs.

10.2.2.2 Design Requirements

Due to the flexibility of the LCD_C peripheral module to accommodate various segment-based LCDs, selecting

the right display for the application in combination with determining specific design requirements is often an

iterative process. TI strongly recommends reviewing the LCD_C peripheral module chapter in the

MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide and Designing With MSP430™

MCUs and Segment LCDs during the initial design requirements and decision process.

10.2.2.3 Detailed Design Procedure

A major component in designing the LCD solution is determining the exact connections between the LCD_C

peripheral module and the display itself. Two basic design processes can be employed for this step, although in

reality often a balanced co-design approach is recommended:

• PCB layout-driven design, optimizing signal routing

• Software-driven design, focusing on optimizing computational overhead

For a detailed discussion of the design procedure as well as for design information regarding the LCD controller

input voltage selection including internal and external options, contrast control, and bias generation, see

Designing With MSP430™ MCUs and Segment LCDs and the LCD_C Controller chapter in the MSP430FR58xx,

MSP430FR59xx, and MSP430FR6xx Family User's Guide.

10.2.2.4 Layout Guidelines

LCD segment (Sx) and common (COMx) signal traces are continuously switching while the LCD is enabled and

should, therefore, be kept away from sensitive analog signals such as ADC inputs to prevent any noise coupling.

TI recommends keeping the LCD signal traces on one side of the PCB grouped together in a bus-like fashion. A

ground plane underneath the LCD traces and guard traces employed alongside the LCD traces can provide

shielding.

If the internal charge pump of the LCD module is used, place the externally provided capacitor on the LCDCAP

pin as close as possible to the MCU. Connect the capacitor to the device using a short and direct trace and have

a solid connection to the ground plane that supplies the VSS pins of the MCU.

For an example layouts and a more in-depth discussion of this topic, see Designing With MSP430™ MCUs and

Segment LCDs.

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11 Device and Documentation Support

11.1 Getting Started

For more information on the MSP family of microcontrollers and the tools and libraries that are available to help

with your development, visit the MSP430™ ultra-low-power sensing & measurement MCUs overview.

11.2 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP

MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These

prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully

qualified production devices (MSP).

XMS –Experimental device that is not necessarily representative of the final device's electrical specifications

MSP –Fully qualified production device

XMS devices are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated

fully. TI's standard warranty applies.

Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.

TI recommends that these devices not be used in any production system because their expected end-use failure

rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature

range, package type, and distribution format. 图11-1 provides a legend for reading the complete device name.

MSP 430 FR

6

0431

I

PN

R

Feature Set

Processor Family

Distribution Format

MCU Platform

Packaging

Memory Type

Temperature Range

Series

AES

Oscillators, LEA

Optional: BSL

FRAM

Processor Family

MSP = Mixed-Signal Processor

XMS = Experimental Silicon

MCU Platform

Memory Type

Series

430 = MSP430 16-Bit Low-Power Platform

FR = FRAM

6 = FRAM 6 Series up to 16 MHz with LCD

5 = FRAM 5 Series up to 16 MHz without LCD

Feature Set

First Digit: Feature Second Digit: Oscillators, LEA Third Digit: FRAM (KB) Optional Fourth Digit: BSL

0 = USS

4 = HFXT + LFXT + LEA + USS

3 = HFXT + LFXT + LEA

2 = HFXT + LFXT

7 = 256

6 = 192

5 = 128

4 = 96

3 = 64

1 = 32

1 = I²C

No value = UART

1 = LFXT

Temperature Range

Packaging

I = –40°C to 85°C

http://www.ti.com/packaging

Distribution Format

T = Small reel

R = Large reel

No markings = Tube or tray

图11-1. Device Nomenclature

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11.3 Tools and Software

表11-1 lists the debug features supported by these microcontrollers.

For details on the available features, see the Code Composer Studio™ IDE for MSP430™ MCUs User's Guide.

For further usage information, see these application reports:

Advanced Debugging Using the Enhanced Emulation Module (EEM) With Code Composer Studio™ IDE

MSP430™ Advanced Power Optimizations: ULP Advisor™ and EnergyTrace™ Technology

表11-1. Hardware Features

BREAK-

POINTS

(N)

RANGE

BREAK-

POINTS

LPMx.5

MSP

ARCHITECTURE

4-WIRE

JTAG

2-WIRE

JTAG

CLOCK

CONTROL SEQUENCER

STATE

TRACE

BUFFER

DEBUGGING EnergyTrace++™

SUPPORT

MSP430Xv2

Yes

3

Yes

No

Yes

Design Kits and Evaluation Modules

EVM430-FR6043

The EVM430-FR6043 is a development platform to evaluate the performance of the MSP430FR6043 MCU for

ultrasonic sensing applications.

MSP-TS430PN80C

The MSP-TS430PN80C is a stand-alone 80-pin ZIF socket target board used to program and debug the

MSP430 MCU in-system through the JTAG interface or the Spy Bi-Wire (2-wire JTAG) protocol.

Ultrasonic Sensing Subsystem Reference Design for Gas Flow Measurement

This reference design helps designers develop an ultrasonic gas-metering subsystem using an integrated,

ultrasonic sensing solution (USS) module, which provides superior metrology performance, with low-power

consumption and maximum integration.

Software

MSP430Ware^™Software

MSP430Ware software is a collection of code examples, data sheets, and other design resources for all

MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing

MSP430 design resources, MSP430Ware software also includes a high-level API called MSP Driver Library. This

library makes it easy to program MSP430 hardware. MSP430Ware software is available as a component of CCS

or as a stand-alone package.

MSP430FR604x, MSP430FR504x Code Examples

C code examples are available for every MSP device that configures each of the integrated peripherals for

various application needs.

MSP Driver Library

The abstracted API of MSP Driver Library provides easy-to-use function calls that free you from directly

manipulating the bits and bytes of the MSP430 hardware. Thorough documentation is delivered through a

helpful API Guide, which includes details on each function call and the recognized parameters. Developers can

use Driver Library functions to write complete projects with minimal overhead.

MSP EnergyTrace^™Technology

EnergyTrace technology for MSP430 microcontrollers is an energy-based code analysis tool that measures and

displays the energy profile of the application and helps to optimize it for ultra-low-power consumption.

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ULP (Ultra-Low Power) Advisor

ULP Advisor^™software is a tool for guiding developers to write more efficient code to fully use the unique ultra-

low-power features of MSP430 and MSP432^™microcontrollers. Aimed at both experienced and new

microcontroller developers, ULP Advisor checks your code against a thorough ULP checklist to help minimize

the energy consumption of your application. At build time, ULP Advisor provides notifications and remarks to

highlight areas of your code that can be further optimized for lower power.

FRAM Embedded Software Utilities for MSP Ultra-Low-Power Microcontrollers

The FRAM Utilities is designed to grow as a collection of embedded software utilities that leverage the ultra-low-

power and virtually unlimited write endurance of FRAM. The utilities are available for MSP430FRxx FRAM

microcontrollers and provide example code to help start application development. Included utilities include

Compute Through Power Loss (CTPL). CTPL is utility API set that enables ease of use with LPMx.5 low-power

modes and a powerful shutdown mode that allows an application to save and restore critical system components

when a power loss is detected.

IEC60730 Software Package

The IEC60730 MSP430 software package was developed to help customers comply with IEC 60730-1:2010

(Automatic Electrical Controls for Household and Similar Use –Part 1: General Requirements) for up to Class B

products, which includes home appliances, arc detectors, power converters, power tools, e-bikes, and many

others. The IEC60730 MSP430 software package can be embedded in customer applications running on

MSP430 MCUs to help simplify the customer's certification efforts of functional safety-compliant consumer

devices to IEC 60730-1:2010 Class B.

Fixed Point Math Library for MSP

The MSP IQmath and Qmath Libraries are a collection of highly optimized and high-precision mathematical

functions for C programmers to seamlessly port a floating-point algorithm into fixed-point code on MSP430 and

MSP432 devices. These routines are typically used in computationally intensive real-time applications where

optimal execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and Qmath

libraries, it is possible to achieve execution speeds considerably faster and energy consumption considerably

lower than equivalent code written using floating-point math.

Floating Point Math Library for MSP430

Continuing to innovate in the low-power and low-cost microcontroller space, TI provides MSPMATHLIB.

Leveraging the intelligent peripherals of our devices, this floating-point math library of scalar functions that are up

to 26 times faster than the standard MSP430 math functions. Mathlib is easy to integrate into your designs. This

library is free and is integrated in both Code Composer Studio IDE and IAR Embedded Workbench IDE.

Development Tools

Code Composer Studio^™Integrated Development Environment for MSP Microcontrollers

Code Composer Studio (CCS) integrated development environment (IDE) supports all MSP microcontroller

devices. CCS comprises a suite of embedded software utilities used to develop and debug embedded

applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger,

profiler, and many other features.

IAR Embedded Workbench^®IDE

IAR Embedded Workbench IDE for MSP430 MCUs is a complete C/C++ compiler toolchain for building and

debugging embedded applications based on MSP430 microcontrollers. The debugger can be used for source

and disassembly code with support for complex code and data breakpoints. It also provides a hardware

simulator that allows debugging without a physical target connected.

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Uniflash Standalone Flash Tool

CCS Uniflash is a stand-alone tool used to program on-chip flash memory on TI MCUs. Uniflash has a GUI,

command line, and scripting interface. Uniflash is a software tool available by TI Cloud Tools or desktop

application download from the TI web page.

MSP MCU Programmer and Debugger

The MSP-FET is a powerful emulation development tool – often called a debug probe – which lets users

quickly begin application development on MSP low-power MCUs. Creating MCU software usually requires

downloading the resulting binary program to the MSP device for validation and debugging.

MSP-GANG Production Programmer

The MSP Gang Programmer is an MSP430 or MSP432 device programmer that can program up to eight

identical MSP430 or MSP432 flash or FRAM devices at the same time. The MSP Gang Programmer connects to

a host PC using a standard RS-232 or USB connection and provides flexible programming options that let the

user fully customize the process.

TIREX Resource Explorer (TIRex)

An online portal to examples, libraries, executables, and documentation for your device and development board.

TIRex can be accessed directly in Code Composer Studio IDE or in TI Cloud Tools.

TI Cloud Tools

Start development immediately on dev.ti.com. Begin by using the Resource Explorer interface to quickly find all

the files you need. Then, edit, build, and debug embedded applications in the cloud, using industry-leading Code

Composer Studio Cloud IDE.

GCC - Compiler for MSP

MSP430 and MSP432 GCC open source packages are complete debugger and open source C/C++ compiler

toolchains for building and debugging embedded applications based on MSP430 and MSP432 microcontrollers.

These free GCC compilers support all MSP430 and MSP432 devices without code size limitations. In addition,

these compilers can be used stand-alone from the command-line or within Code Composer Studio v6.0 or later.

Get started today whether you are using a Windows^®, Linux^®, or OS X^®environment.

11.4 Documentation Support

The following documents describe the MSP430FR604x and MSP430FR504x MCUs. Copies of these documents

are available on the Internet at www.ti.com.

Receiving Notification of Document Updates

To receive notification of documentation updates—including silicon errata—go to the product folder for your

device on ti.com (for example, MSP430FR6043). In the upper right corner, click the "Alert me" button. This

registers you to receive a weekly digest of product information that has changed (if any). For change details,

check the revision history of any revised document.

Errata

MSP430FR6043 Device Errata

Describes the known exceptions to the functional specifications for each silicon revision of this device.

MSP430FR60431 Device Errata

Describes the known exceptions to the functional specifications for each silicon revision of this device.

MSP430FR6041 Device Errata

Describes the known exceptions to the functional specifications for each silicon revision of this device.

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MSP430FR5043 Device Errata

Describes the known exceptions to the functional specifications for each silicon revision of this device.

MSP430FR50431 Device Errata

Describes the known exceptions to the functional specifications for each silicon revision of this device.

MSP430FR5041 Device Errata

Describes the known exceptions to the functional specifications for each silicon revision of this device.

User's Guides

MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide

Detailed description of all modules and peripherals available in this device family.

MSP430 FRAM Devices Bootloader (BSL) User's Guide

The bootloader (BSL) on MSP430 MCUs lets users communicate with embedded memory in the MSP430 MCU

during the prototyping phase, final production, and in service. Both the programmable memory (FRAM memory)

and the data memory (RAM) can be modified as required.

MSP430 Programming With the JTAG Interface

This document describes the functions that are required to erase, program, and verify the memory module of the

MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition,

it describes how to program the JTAG access security fuse that is available on all MSP430 devices. This

document describes device access using both the standard 4-wire JTAG interface and the 2-wire JTAG

interface, which is also referred to as Spy-Bi-Wire (SBW).

MSP430 Hardware Tools User's Guide

This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the

program development tool for the MSP430 ultra-low-power microcontroller. Both available interface types, the

parallel port interface and the USB interface, are described.

Application Reports

MSP430 32-kHz Crystal Oscillators

Selection of the right crystal, correct load circuit, and proper board layout are important for a stable crystal

oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the

correct crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout

are given. The document also contains detailed information on the possible oscillator tests to ensure stable

oscillator operation in mass production.

MSP430 System-Level ESD Considerations

System-level ESD has become increasingly demanding with silicon technology scaling towards lower voltages

and the need for designing cost-effective and ultra-low-power components. This application report addresses

three different ESD topics to help board designers and OEMs understand and design robust system-level

designs. A few real-world system-level ESD protection design examples and their results are also discussed.

11.5 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

MSP Academy is a starting point for all developers to learn about the MSP430 MCU Platform, which provides

affordable solutions for many applications. MSP Academy delivers easy-to-use training modules that span a

wide range of topics and LaunchPad development kits in the MSP430 MCU portfolio.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

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11.6 Trademarks

MSP430Ware^™, EnergyTrace^™, ULP Advisor^™, MSP432^™, Code Composer Studio^™, and TI E2E^™are

trademarks of Texas Instruments.

Arm^®and Cortex^®are registered trademarks of Arm Limited.

Microsoft^®and Windows^®are registered trademarks of Microsoft Corporation.

IAR Embedded Workbench^®is a registered trademark of IAR Systems.

Linux^®is a registered trademark of Linus Torvalds.

OS X^®is a registered trademark of Apple, Inc.

所有商标均为其各自所有者的财产。

11.7 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.8 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

11.9 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as

defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled

product restricted by other applicable national regulations, received from disclosing party under nondisclosure

obligations (if any), or any direct product of such technology, to any destination to which such export or re-export

is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.

Department of Commerce and other competent Government authorities to the extent required by those laws.

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

PM0064A

LQFP - 1.6 mm max height

SCALE 1.400

PLASTIC QUAD FLATPACK

10.2

9.8

B

NOTE 3

64

49

PIN 1 ID

1

48

10.2

9.8

12.2

TYP

11.8

NOTE 3

33

16

32

17

A

0.27

0.17

64X

60X 0.5

4X 7.5

0.08

C A B

C

(0.13) TYP

SEATING PLANE

0.08

SEE DETAIL A

0.25

GAGE PLANE

(1.4)

1.6 MAX

0.05 MIN

0.75

0.45

0 -7

DETAIL

SCALE: 14

A

DETAIL A

TYPICAL

4215162/A 03/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MS-026.

www.ti.com

EXAMPLE BOARD LAYOUT

PM0064A

LQFP - 1.6 mm max height

PLASTIC QUAD FLATPACK

SYMM

49

64

64X (1.5)

1

48

64X (0.3)

SYMM

(11.4)

60X (0.5)

(R0.05) TYP

33

16

17

32

(11.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

0.05 MAX

ALL AROUND

EXPOSED METAL

METAL

0.05 MIN

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4215162/A 03/2017

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

7. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).

www.ti.com

EXAMPLE STENCIL DESIGN

PM0064A

LQFP - 1.6 mm max height

PLASTIC QUAD FLATPACK

SYMM

64

49

64X (1.5)

1

48

64X (0.3)

SYMM

(11.4)

60X (0.5)

(R0.05) TYP

16

33

17

32

(11.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:8X

4215162/A 03/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

GENERIC PACKAGE VIEW

RGC 64

9 x 9, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224597/A

www.ti.com

PACKAGE OUTLINE

PN0080A

LQFP - 1.6 mm max height

SCALE 1.250

PLASTIC QUAD FLATPACK

12.2

11.8

B

PIN 1 ID

A

80

61

1

60

12.2

11.8

14.2

TYP

13.8

20

41

40

21

76X 0.5

0.27

80X

0.17

4X 9.5

0.08

C A B

1.6 MAX

C

(0.13) TYP

SEATING PLANE

0.08

SEE DETAIL A

0.25

GAGE PLANE

(1.4)

0.05 MIN

0.75

0.45

0 -7

DETAIL

SCALE: 14

A

DETAIL A

TYPICAL

4215166/A 08/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Reference JEDEC registration MS-026.

www.ti.com

EXAMPLE BOARD LAYOUT

PN0080A

LQFP - 1.6 mm max height

PLASTIC QUAD FLATPACK

SYMM

80

61

80X (1.5)

1

60

80X (0.3)

SYMM

(13.4)

76X (0.5)

(R0.05) TYP

20

41

21

40

(13.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:6X

0.05 MAX

ALL AROUND

EXPOSED METAL

METAL

0.05 MIN

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4215166/A 08/2022

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

6. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).

www.ti.com

EXAMPLE STENCIL DESIGN

PN0080A

LQFP - 1.6 mm max height

PLASTIC QUAD FLATPACK

SYMM

80

61

80X (1.5)

1

60

80X (0.3)

SYMM

(13.4)

76X (0.5)

(R0.05) TYP

20

41

21

40

(13.4)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:6X

4215166/A 08/2022

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	MSP430FR6041IPNR
厂家：	TEXAS INSTRUMENTS
描述：	具有 32KB FRAM、LCD、12 位高速 8MSPS Σ-Δ ADC 和集成传感器 AFE 的 16MHz MCU \| PN \| 80 \| -40 to 85 CD 传感器
文件：	总197页 (文件大小：5019K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MSP430FR6041IPNR [TI]

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